From 7d855f33508fa132431b96cbea76e9b7f4fa274a Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Fri, 25 Oct 2024 14:19:38 +0200 Subject: [PATCH 01/18] add code for tests with esp32s3 --- README.md | 1 + sensebox-bike-atrai-v2-esp32s3/.gitignore | 5 + .../.vscode/extensions.json | 10 + .../.vscode/settings.json | 53 + sensebox-bike-atrai-v2-esp32s3/include/README | 39 + sensebox-bike-atrai-v2-esp32s3/lib/README | 46 + .../esp32/esp32_camera/esp32_camera.ino | 383 + .../esp32/esp32_fusion/esp32_fusion.ino | 303 + .../esp32_microphone/esp32_microphone.ino | 299 + .../esp32_microphone_continuous.ino | 323 + .../nano_ble33_sense_accelerometer.ino | 144 + ...o_ble33_sense_accelerometer_continuous.ino | 188 + .../nano_ble33_sense_camera.ino | 773 + .../nano_ble33_sense_fusion.ino | 388 + .../nano_ble33_sense_microphone.ino | 220 + ...nano_ble33_sense_microphone_continuous.ino | 254 + .../nano_ble33_sense_rev2_accelerometer.ino | 145 + ...33_sense_rev2_accelerometer_continuous.ino | 189 + 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sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp create mode 100644 sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h create mode 100644 sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp create mode 100644 sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h create mode 100644 sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp create mode 100644 sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.h create mode 100644 sensebox-bike-atrai-v2-esp32s3/test/README diff --git a/README.md b/README.md index 6179e12..a8b4167 100644 --- a/README.md +++ b/README.md @@ -11,6 +11,7 @@ A mobile measurement station that measures temperature, relative humidity, parti | [senseBox:bike](senseBox-bike) | senseBox MCU S2 | BLE | | Used for the [senseBox:bike to buy](https://sensebox.kaufen/product/sensebox-bike) | | [senseBox:bike Atrai Bike](senseBox-bike-atrai) | senseBox MCU S2 | BLE | | Initial draft for [Atrai Bike](https://atrai.bike/) project | | [senseBox:bike Atrai Bike v2](senseBox-bike-atrai-v2) | senseBox MCU S2 | BLE | ✅ | AI powered version for [Atrai Bike](https://atrai.bike/) project | +| [senseBox:bike Atrai Bike v2 ESP32S2](senseBox-bike-atrai-v2-esp32s2) | Adafruit Feather ESP32S3 (with 2MB PSRAM) | BLE | ✅ | Testing the AI powered version for [Atrai Bike](https://atrai.bike/) project with an ESP32S3 chip | ### License diff --git a/sensebox-bike-atrai-v2-esp32s3/.gitignore b/sensebox-bike-atrai-v2-esp32s3/.gitignore new file mode 100644 index 0000000..89cc49c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/.gitignore @@ -0,0 +1,5 @@ +.pio +.vscode/.browse.c_cpp.db* +.vscode/c_cpp_properties.json +.vscode/launch.json +.vscode/ipch diff --git a/sensebox-bike-atrai-v2-esp32s3/.vscode/extensions.json b/sensebox-bike-atrai-v2-esp32s3/.vscode/extensions.json new file mode 100644 index 0000000..080e70d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/.vscode/extensions.json @@ -0,0 +1,10 @@ +{ + // See http://go.microsoft.com/fwlink/?LinkId=827846 + // for the documentation about the extensions.json format + "recommendations": [ + "platformio.platformio-ide" + ], + "unwantedRecommendations": [ + "ms-vscode.cpptools-extension-pack" + ] +} diff --git a/sensebox-bike-atrai-v2-esp32s3/.vscode/settings.json b/sensebox-bike-atrai-v2-esp32s3/.vscode/settings.json new file mode 100644 index 0000000..a3c054a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/.vscode/settings.json @@ -0,0 +1,53 @@ +{ + "editor.defaultFormatter": "ms-vscode.cpptools", + "files.associations": { + "array": "cpp", + "atomic": "cpp", + "*.tcc": "cpp", + "cctype": "cpp", + "clocale": "cpp", + "cmath": "cpp", + "cstdarg": "cpp", + "cstddef": "cpp", + "cstdint": "cpp", + "cstdio": "cpp", + "cstdlib": "cpp", + "cstring": "cpp", + "ctime": "cpp", + "cwchar": "cpp", + "cwctype": "cpp", + "deque": "cpp", + "unordered_map": "cpp", + "vector": "cpp", + "exception": "cpp", + "algorithm": "cpp", + "functional": "cpp", + "iterator": "cpp", + "map": "cpp", + "memory": "cpp", + "memory_resource": "cpp", + "numeric": "cpp", + "optional": "cpp", + "random": "cpp", + "set": "cpp", + "string": "cpp", + "string_view": "cpp", + "system_error": "cpp", + "tuple": "cpp", + "type_traits": "cpp", + "utility": "cpp", + "fstream": "cpp", + "initializer_list": "cpp", + "iomanip": "cpp", + "iosfwd": "cpp", + "istream": "cpp", + "limits": "cpp", + "new": "cpp", + "ostream": "cpp", + "sstream": "cpp", + "stdexcept": "cpp", + "streambuf": "cpp", + "cinttypes": "cpp", + "typeinfo": "cpp" + } +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/include/README b/sensebox-bike-atrai-v2-esp32s3/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/README b/sensebox-bike-atrai-v2-esp32s3/lib/README new file mode 100644 index 0000000..2593a33 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_camera/esp32_camera.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_camera/esp32_camera.ino new file mode 100644 index 0000000..13a4257 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_camera/esp32_camera.ino @@ -0,0 +1,383 @@ +/* Edge Impulse Arduino examples + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +// These sketches are tested with 2.0.4 ESP32 Arduino Core +// https://github.com/espressif/arduino-esp32/releases/tag/2.0.4 + +/* Includes ---------------------------------------------------------------- */ +#include +#include "edge-impulse-sdk/dsp/image/image.hpp" + +#include "esp_camera.h" + +// Select camera model - find more camera models in camera_pins.h file here +// https://github.com/espressif/arduino-esp32/blob/master/libraries/ESP32/examples/Camera/CameraWebServer/camera_pins.h + +#define CAMERA_MODEL_ESP_EYE // Has PSRAM +//#define CAMERA_MODEL_AI_THINKER // Has PSRAM + +#if defined(CAMERA_MODEL_ESP_EYE) +#define PWDN_GPIO_NUM -1 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 4 +#define SIOD_GPIO_NUM 18 +#define SIOC_GPIO_NUM 23 + +#define Y9_GPIO_NUM 36 +#define Y8_GPIO_NUM 37 +#define Y7_GPIO_NUM 38 +#define Y6_GPIO_NUM 39 +#define Y5_GPIO_NUM 35 +#define Y4_GPIO_NUM 14 +#define Y3_GPIO_NUM 13 +#define Y2_GPIO_NUM 34 +#define VSYNC_GPIO_NUM 5 +#define HREF_GPIO_NUM 27 +#define PCLK_GPIO_NUM 25 + +#elif defined(CAMERA_MODEL_AI_THINKER) +#define PWDN_GPIO_NUM 32 +#define RESET_GPIO_NUM -1 +#define XCLK_GPIO_NUM 0 +#define SIOD_GPIO_NUM 26 +#define SIOC_GPIO_NUM 27 + +#define Y9_GPIO_NUM 35 +#define Y8_GPIO_NUM 34 +#define Y7_GPIO_NUM 39 +#define Y6_GPIO_NUM 36 +#define Y5_GPIO_NUM 21 +#define Y4_GPIO_NUM 19 +#define Y3_GPIO_NUM 18 +#define Y2_GPIO_NUM 5 +#define VSYNC_GPIO_NUM 25 +#define HREF_GPIO_NUM 23 +#define PCLK_GPIO_NUM 22 + +#else +#error "Camera model not selected" +#endif + +/* Constant defines -------------------------------------------------------- */ +#define EI_CAMERA_RAW_FRAME_BUFFER_COLS 320 +#define EI_CAMERA_RAW_FRAME_BUFFER_ROWS 240 +#define EI_CAMERA_FRAME_BYTE_SIZE 3 + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static bool is_initialised = false; +uint8_t *snapshot_buf; //points to the output of the capture + +static camera_config_t camera_config = { + .pin_pwdn = PWDN_GPIO_NUM, + .pin_reset = RESET_GPIO_NUM, + .pin_xclk = XCLK_GPIO_NUM, + .pin_sscb_sda = SIOD_GPIO_NUM, + .pin_sscb_scl = SIOC_GPIO_NUM, + + .pin_d7 = Y9_GPIO_NUM, + .pin_d6 = Y8_GPIO_NUM, + .pin_d5 = Y7_GPIO_NUM, + .pin_d4 = Y6_GPIO_NUM, + .pin_d3 = Y5_GPIO_NUM, + .pin_d2 = Y4_GPIO_NUM, + .pin_d1 = Y3_GPIO_NUM, + .pin_d0 = Y2_GPIO_NUM, + .pin_vsync = VSYNC_GPIO_NUM, + .pin_href = HREF_GPIO_NUM, + .pin_pclk = PCLK_GPIO_NUM, + + //XCLK 20MHz or 10MHz for OV2640 double FPS (Experimental) + .xclk_freq_hz = 20000000, + .ledc_timer = LEDC_TIMER_0, + .ledc_channel = LEDC_CHANNEL_0, + + .pixel_format = PIXFORMAT_JPEG, //YUV422,GRAYSCALE,RGB565,JPEG + .frame_size = FRAMESIZE_QVGA, //QQVGA-UXGA Do not use sizes above QVGA when not JPEG + + .jpeg_quality = 12, //0-63 lower number means higher quality + .fb_count = 1, //if more than one, i2s runs in continuous mode. Use only with JPEG + .fb_location = CAMERA_FB_IN_PSRAM, + .grab_mode = CAMERA_GRAB_WHEN_EMPTY, +}; + +/* Function definitions ------------------------------------------------------- */ +bool ei_camera_init(void); +void ei_camera_deinit(void); +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) ; + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + //comment out the below line to start inference immediately after upload + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + if (ei_camera_init() == false) { + ei_printf("Failed to initialize Camera!\r\n"); + } + else { + ei_printf("Camera initialized\r\n"); + } + + ei_printf("\nStarting continious inference in 2 seconds...\n"); + ei_sleep(2000); +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + + // instead of wait_ms, we'll wait on the signal, this allows threads to cancel us... + if (ei_sleep(5) != EI_IMPULSE_OK) { + return; + } + + snapshot_buf = (uint8_t*)malloc(EI_CAMERA_RAW_FRAME_BUFFER_COLS * EI_CAMERA_RAW_FRAME_BUFFER_ROWS * EI_CAMERA_FRAME_BYTE_SIZE); + + // check if allocation was successful + if(snapshot_buf == nullptr) { + ei_printf("ERR: Failed to allocate snapshot buffer!\n"); + return; + } + + ei::signal_t signal; + signal.total_length = EI_CLASSIFIER_INPUT_WIDTH * EI_CLASSIFIER_INPUT_HEIGHT; + signal.get_data = &ei_camera_get_data; + + if (ei_camera_capture((size_t)EI_CLASSIFIER_INPUT_WIDTH, (size_t)EI_CLASSIFIER_INPUT_HEIGHT, snapshot_buf) == false) { + ei_printf("Failed to capture image\r\n"); + free(snapshot_buf); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.): \n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + +#if EI_CLASSIFIER_OBJECT_DETECTION == 1 + ei_printf("Object detection bounding boxes:\r\n"); + for (uint32_t i = 0; i < result.bounding_boxes_count; i++) { + ei_impulse_result_bounding_box_t bb = result.bounding_boxes[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } + + // Print the prediction results (classification) +#else + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } +#endif + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + ei_printf("Visual anomalies:\r\n"); + for (uint32_t i = 0; i < result.visual_ad_count; i++) { + ei_impulse_result_bounding_box_t bb = result.visual_ad_grid_cells[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } +#endif + + + free(snapshot_buf); + +} + +/** + * @brief Setup image sensor & start streaming + * + * @retval false if initialisation failed + */ +bool ei_camera_init(void) { + + if (is_initialised) return true; + +#if defined(CAMERA_MODEL_ESP_EYE) + pinMode(13, INPUT_PULLUP); + pinMode(14, INPUT_PULLUP); +#endif + + //initialize the camera + esp_err_t err = esp_camera_init(&camera_config); + if (err != ESP_OK) { + Serial.printf("Camera init failed with error 0x%x\n", err); + return false; + } + + sensor_t * s = esp_camera_sensor_get(); + // initial sensors are flipped vertically and colors are a bit saturated + if (s->id.PID == OV3660_PID) { + s->set_vflip(s, 1); // flip it back + s->set_brightness(s, 1); // up the brightness just a bit + s->set_saturation(s, 0); // lower the saturation + } + +#if defined(CAMERA_MODEL_M5STACK_WIDE) + s->set_vflip(s, 1); + s->set_hmirror(s, 1); +#elif defined(CAMERA_MODEL_ESP_EYE) + s->set_vflip(s, 1); + s->set_hmirror(s, 1); + s->set_awb_gain(s, 1); +#endif + + is_initialised = true; + return true; +} + +/** + * @brief Stop streaming of sensor data + */ +void ei_camera_deinit(void) { + + //deinitialize the camera + esp_err_t err = esp_camera_deinit(); + + if (err != ESP_OK) + { + ei_printf("Camera deinit failed\n"); + return; + } + + is_initialised = false; + return; +} + + +/** + * @brief Capture, rescale and crop image + * + * @param[in] img_width width of output image + * @param[in] img_height height of output image + * @param[in] out_buf pointer to store output image, NULL may be used + * if ei_camera_frame_buffer is to be used for capture and resize/cropping. + * + * @retval false if not initialised, image captured, rescaled or cropped failed + * + */ +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) { + bool do_resize = false; + + if (!is_initialised) { + ei_printf("ERR: Camera is not initialized\r\n"); + return false; + } + + camera_fb_t *fb = esp_camera_fb_get(); + + if (!fb) { + ei_printf("Camera capture failed\n"); + return false; + } + + bool converted = fmt2rgb888(fb->buf, fb->len, PIXFORMAT_JPEG, snapshot_buf); + + esp_camera_fb_return(fb); + + if(!converted){ + ei_printf("Conversion failed\n"); + return false; + } + + if ((img_width != EI_CAMERA_RAW_FRAME_BUFFER_COLS) + || (img_height != EI_CAMERA_RAW_FRAME_BUFFER_ROWS)) { + do_resize = true; + } + + if (do_resize) { + ei::image::processing::crop_and_interpolate_rgb888( + out_buf, + EI_CAMERA_RAW_FRAME_BUFFER_COLS, + EI_CAMERA_RAW_FRAME_BUFFER_ROWS, + out_buf, + img_width, + img_height); + } + + + return true; +} + +static int ei_camera_get_data(size_t offset, size_t length, float *out_ptr) +{ + // we already have a RGB888 buffer, so recalculate offset into pixel index + size_t pixel_ix = offset * 3; + size_t pixels_left = length; + size_t out_ptr_ix = 0; + + while (pixels_left != 0) { + // Swap BGR to RGB here + // due to https://github.com/espressif/esp32-camera/issues/379 + out_ptr[out_ptr_ix] = (snapshot_buf[pixel_ix + 2] << 16) + (snapshot_buf[pixel_ix + 1] << 8) + snapshot_buf[pixel_ix]; + + // go to the next pixel + out_ptr_ix++; + pixel_ix+=3; + pixels_left--; + } + // and done! + return 0; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_CAMERA +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_fusion/esp32_fusion.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_fusion/esp32_fusion.ino new file mode 100644 index 0000000..6ce4d0a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_fusion/esp32_fusion.ino @@ -0,0 +1,303 @@ +/* Edge Impulse Arduino examples + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +// These sketches are tested with 2.0.4 ESP32 Arduino Core +// https://github.com/espressif/arduino-esp32/releases/tag/2.0.4 + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: http://librarymanager/All#LIS3DHTR +#include + +/** Struct to link sensor axis name to sensor value function */ +typedef struct{ + const char *name; + float *value; + uint8_t (*poll_sensor)(void); + bool (*init_sensor)(void); + int8_t status; // -1 not used 0 used(unitialized) 1 used(initalized) 2 data sampled +} eiSensors; + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, + // but this example use Arudino library which set range to +-4g. + // If you are using an older model, ignore this value and use 4.0f instead +/** Number sensor axes used */ +#define N_SENSORS 7 + +/* Forward declarations ------------------------------------------------------- */ +float ei_get_sign(float number); +static bool ei_connect_fusion_list(const char *input_list); + +bool init_IMU(void); +bool init_ADC(void); +uint8_t poll_IMU(void); +uint8_t poll_ADC(void); + +/* Private variables ------------------------------------------------------- */ +static const bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static float data[N_SENSORS]; +static int8_t fusion_sensors[N_SENSORS]; +static int fusion_ix = 0; + +LIS3DHTR lis; + +/** Used sensors value function connected to label name */ +eiSensors sensors[] = +{ + "accX", &data[0], &poll_IMU, &init_IMU, -1, + "accY", &data[1], &poll_IMU, &init_IMU, -1, + "accZ", &data[2], &poll_IMU, &init_IMU, -1, + "adc", &data[6], &poll_ADC, &init_ADC, -1, +}; + +/** +* @brief Arduino setup function +*/ +void setup() +{ + /* Init serial */ + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Sensor Fusion Inference\r\n"); + + /* Connect used sensors */ + if(ei_connect_fusion_list(EI_CLASSIFIER_FUSION_AXES_STRING) == false) { + ei_printf("ERR: Errors in sensor list detected\r\n"); + return; + } + + /* Init & start sensors */ + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == 0) { + sensors[fusion_sensors[i]].status = sensors[fusion_sensors[i]].init_sensor(); + if (!sensors[fusion_sensors[i]].status) { + ei_printf("%s axis sensor initialization failed.\r\n", sensors[fusion_sensors[i]].name); + } + else { + ei_printf("%s axis sensor initialization successful.\r\n", sensors[fusion_sensors[i]].name); + } + } + } +} + +/** +* @brief Get data and run inferencing +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\r\n"); + + delay(2000); + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != fusion_ix) { + ei_printf("ERR: Sensors don't match the sensors required in the model\r\n" + "Following sensors are required: %s\r\n", EI_CLASSIFIER_FUSION_AXES_STRING); + return; + } + + ei_printf("Sampling...\r\n"); + + // Allocate a buffer here for the values we'll read from the sensor + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME) { + // Determine the next tick (and then sleep later) + int64_t next_tick = (int64_t)micros() + ((int64_t)EI_CLASSIFIER_INTERVAL_MS * 1000); + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == 1) { + sensors[fusion_sensors[i]].poll_sensor(); + sensors[fusion_sensors[i]].status = 2; + } + if (sensors[fusion_sensors[i]].status == 2) { + buffer[ix + i] = *sensors[fusion_sensors[i]].value; + //ei_printf("%d %f\n", fusion_sensors[i], buffer[ix + i]); + sensors[fusion_sensors[i]].status = 1; + } + } + + int64_t wait_time = next_tick - (int64_t)micros(); + + if(wait_time > 0) { + delayMicroseconds(wait_time); + } + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.):\r\n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf("%s: %.5f\r\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\r\n", result.anomaly); +#endif +} + +#if !defined(EI_CLASSIFIER_SENSOR) || (EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_FUSION && EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER) +#error "Invalid model for current sensor" +#endif + + +/** + * @brief Go through sensor list to find matching axis name + * + * @param axis_name + * @return int8_t index in sensor list, -1 if axis name is not found + */ +static int8_t ei_find_axis(char *axis_name) +{ + int ix; + for(ix = 0; ix < N_SENSORS; ix++) { + if(strstr(axis_name, sensors[ix].name)) { + return ix; + } + } + return -1; +} + +/** + * @brief Check if requested input list is valid sensor fusion, create sensor buffer + * + * @param[in] input_list Axes list to sample (ie. "accX + gyrY + magZ") + * @retval false if invalid sensor_list + */ +static bool ei_connect_fusion_list(const char *input_list) +{ + char *buff; + bool is_fusion = false; + + /* Copy const string in heap mem */ + char *input_string = (char *)ei_malloc(strlen(input_list) + 1); + if (input_string == NULL) { + return false; + } + memset(input_string, 0, strlen(input_list) + 1); + strncpy(input_string, input_list, strlen(input_list)); + + /* Clear fusion sensor list */ + memset(fusion_sensors, 0, N_SENSORS); + fusion_ix = 0; + + buff = strtok(input_string, "+"); + + while (buff != NULL) { /* Run through buffer */ + int8_t found_axis = 0; + + is_fusion = false; + found_axis = ei_find_axis(buff); + + if(found_axis >= 0) { + if(fusion_ix < N_SENSORS) { + fusion_sensors[fusion_ix++] = found_axis; + sensors[found_axis].status = 0; + } + is_fusion = true; + } + + buff = strtok(NULL, "+ "); + } + + ei_free(input_string); + + return is_fusion; +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +bool init_IMU(void) { + static bool init_status = false; + if (!init_status) { + lis.begin(Wire, LIS3DHTR_DEFAULT_ADDRESS); + init_status = lis.isConnection(); + + if(init_status == false) { + ei_printf("Failed to connect to Inertial sensor!\n"); + return false; + } + + ei_sleep(100); + lis.setFullScaleRange(LIS3DHTR_RANGE_2G); + lis.setOutputDataRate(LIS3DHTR_DATARATE_100HZ); + } + return init_status; +} + +bool init_ADC(void) { + static bool init_status = false; + if (!init_status) { + init_status = true; + } + return init_status; +} + +uint8_t poll_IMU(void) { + + lis.getAcceleration(&data[0], &data[1], &data[2]); + + for (int i = 0; i < 3; i++) { + if (fabs(data[i]) > MAX_ACCEPTED_RANGE) { + data[i] = ei_get_sign(data[i]) * MAX_ACCEPTED_RANGE; + } + } + + data[0] *= CONVERT_G_TO_MS2; + data[1] *= CONVERT_G_TO_MS2; + data[2] *= CONVERT_G_TO_MS2; + + return 0; +} + +uint8_t poll_ADC(void) { + // change to another pin if necessary + data[6] = analogRead(A0); + return 0; +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_microphone/esp32_microphone.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_microphone/esp32_microphone.ino new file mode 100644 index 0000000..148a3f9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_microphone/esp32_microphone.ino @@ -0,0 +1,299 @@ +/* Edge Impulse Arduino examples + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +// These sketches are tested with 2.0.4 ESP32 Arduino Core +// https://github.com/espressif/arduino-esp32/releases/tag/2.0.4 + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "driver/i2s.h" + +/** Audio buffers, pointers and selectors */ +typedef struct { + int16_t *buffer; + uint8_t buf_ready; + uint32_t buf_count; + uint32_t n_samples; +} inference_t; + +static inference_t inference; +static const uint32_t sample_buffer_size = 2048; +static signed short sampleBuffer[sample_buffer_size]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static bool record_status = true; + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + ei_printf("\nStarting continious inference in 2 seconds...\n"); + ei_sleep(2000); + + if (microphone_inference_start(EI_CLASSIFIER_RAW_SAMPLE_COUNT) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } + + ei_printf("Recording...\n"); +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + signal_t signal; + signal.total_length = EI_CLASSIFIER_RAW_SAMPLE_COUNT; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR r = run_classifier(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: ", result.classification[ix].label); + ei_printf_float(result.classification[ix].value); + ei_printf("\n"); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: "); + ei_printf_float(result.anomaly); + ei_printf("\n"); +#endif +} + +static void audio_inference_callback(uint32_t n_bytes) +{ + for(int i = 0; i < n_bytes>>1; i++) { + inference.buffer[inference.buf_count++] = sampleBuffer[i]; + + if(inference.buf_count >= inference.n_samples) { + inference.buf_count = 0; + inference.buf_ready = 1; + } + } +} + +static void capture_samples(void* arg) { + + const int32_t i2s_bytes_to_read = (uint32_t)arg; + size_t bytes_read = i2s_bytes_to_read; + + while (record_status) { + + /* read data at once from i2s */ + i2s_read((i2s_port_t)1, (void*)sampleBuffer, i2s_bytes_to_read, &bytes_read, 100); + + if (bytes_read <= 0) { + ei_printf("Error in I2S read : %d", bytes_read); + } + else { + if (bytes_read < i2s_bytes_to_read) { + ei_printf("Partial I2S read"); + } + + // scale the data (otherwise the sound is too quiet) + for (int x = 0; x < i2s_bytes_to_read/2; x++) { + sampleBuffer[x] = (int16_t)(sampleBuffer[x]) * 8; + } + + if (record_status) { + audio_inference_callback(i2s_bytes_to_read); + } + else { + break; + } + } + } + vTaskDelete(NULL); +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffer = (int16_t *)malloc(n_samples * sizeof(int16_t)); + + if(inference.buffer == NULL) { + return false; + } + + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + if (i2s_init(EI_CLASSIFIER_FREQUENCY)) { + ei_printf("Failed to start I2S!"); + } + + ei_sleep(100); + + record_status = true; + + xTaskCreate(capture_samples, "CaptureSamples", 1024 * 32, (void*)sample_buffer_size, 10, NULL); + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + while (inference.buf_ready == 0) { + delay(10); + } + + inference.buf_ready = 0; + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffer[offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + i2s_deinit(); + ei_free(inference.buffer); +} + + +static int i2s_init(uint32_t sampling_rate) { + // Start listening for audio: MONO @ 8/16KHz + i2s_config_t i2s_config = { + .mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_TX), + .sample_rate = sampling_rate, + .bits_per_sample = (i2s_bits_per_sample_t)16, + .channel_format = I2S_CHANNEL_FMT_ONLY_RIGHT, + .communication_format = I2S_COMM_FORMAT_I2S, + .intr_alloc_flags = 0, + .dma_buf_count = 8, + .dma_buf_len = 512, + .use_apll = false, + .tx_desc_auto_clear = false, + .fixed_mclk = -1, + }; + i2s_pin_config_t pin_config = { + .bck_io_num = 26, // IIS_SCLK + .ws_io_num = 32, // IIS_LCLK + .data_out_num = -1, // IIS_DSIN + .data_in_num = 33, // IIS_DOUT + }; + esp_err_t ret = 0; + + ret = i2s_driver_install((i2s_port_t)1, &i2s_config, 0, NULL); + if (ret != ESP_OK) { + ei_printf("Error in i2s_driver_install"); + } + + ret = i2s_set_pin((i2s_port_t)1, &pin_config); + if (ret != ESP_OK) { + ei_printf("Error in i2s_set_pin"); + } + + ret = i2s_zero_dma_buffer((i2s_port_t)1); + if (ret != ESP_OK) { + ei_printf("Error in initializing dma buffer with 0"); + } + + return int(ret); +} + +static int i2s_deinit(void) { + i2s_driver_uninstall((i2s_port_t)1); //stop & destroy i2s driver + return 0; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_microphone_continuous/esp32_microphone_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_microphone_continuous/esp32_microphone_continuous.ino new file mode 100644 index 0000000..530086d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/esp32/esp32_microphone_continuous/esp32_microphone_continuous.ino @@ -0,0 +1,323 @@ +/* Edge Impulse Arduino examples + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +// These sketches are tested with 2.0.4 ESP32 Arduino Core +// https://github.com/espressif/arduino-esp32/releases/tag/2.0.4 + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#include "driver/i2s.h" + +/** Audio buffers, pointers and selectors */ +typedef struct { + signed short *buffers[2]; + unsigned char buf_select; + unsigned char buf_ready; + unsigned int buf_count; + unsigned int n_samples; +} inference_t; + +static inference_t inference; +static const uint32_t sample_buffer_size = 2048; +static signed short sampleBuffer[sample_buffer_size]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static int print_results = -(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW); +static bool record_status = true; + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + run_classifier_init(); + ei_printf("\nStarting continious inference in 2 seconds...\n"); + ei_sleep(2000); + + if (microphone_inference_start(EI_CLASSIFIER_SLICE_SIZE) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } + + ei_printf("Recording...\n"); +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + signal_t signal; + signal.total_length = EI_CLASSIFIER_SLICE_SIZE; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = {0}; + + EI_IMPULSE_ERROR r = run_classifier_continuous(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + if (++print_results >= (EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)) { + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: ", result.classification[ix].label); + ei_printf_float(result.classification[ix].value); + ei_printf("\n"); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: "); + ei_printf_float(result.anomaly); + ei_printf("\n"); +#endif + + print_results = 0; + } +} + +static void audio_inference_callback(uint32_t n_bytes) +{ + for(int i = 0; i < n_bytes>>1; i++) { + inference.buffers[inference.buf_select][inference.buf_count++] = sampleBuffer[i]; + + if(inference.buf_count >= inference.n_samples) { + inference.buf_select ^= 1; + inference.buf_count = 0; + inference.buf_ready = 1; + } + } +} + +static void capture_samples(void* arg) { + + const int32_t i2s_bytes_to_read = (uint32_t)arg; + size_t bytes_read = i2s_bytes_to_read; + + while (record_status) { + + /* read data at once from i2s */ + i2s_read((i2s_port_t)1, (void*)sampleBuffer, i2s_bytes_to_read, &bytes_read, 100); + + if (bytes_read <= 0) { + ei_printf("Error in I2S read : %d", bytes_read); + } + else { + if (bytes_read < i2s_bytes_to_read) { + ei_printf("Partial I2S read"); + } + + // scale the data (otherwise the sound is too quiet) + for (int x = 0; x < i2s_bytes_to_read/2; x++) { + sampleBuffer[x] = (int16_t)(sampleBuffer[x]) * 8; + } + + if (record_status) { + audio_inference_callback(i2s_bytes_to_read); + } + else { + break; + } + } + } + vTaskDelete(NULL); +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffers[0] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[0] == NULL) { + return false; + } + + inference.buffers[1] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[1] == NULL) { + ei_free(inference.buffers[0]); + return false; + } + + inference.buf_select = 0; + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + if (i2s_init(EI_CLASSIFIER_FREQUENCY)) { + ei_printf("Failed to start I2S!"); + } + + ei_sleep(100); + + record_status = true; + + xTaskCreate(capture_samples, "CaptureSamples", 1024 * 32, (void*)sample_buffer_size, 10, NULL); + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + if (inference.buf_ready == 1) { + ei_printf( + "Error sample buffer overrun. Decrease the number of slices per model window " + "(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)\n"); + ret = false; + } + + while (inference.buf_ready == 0) { + delay(1); + } + + inference.buf_ready = 0; + return true; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffers[inference.buf_select ^ 1][offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + i2s_deinit(); + ei_free(inference.buffers[0]); + ei_free(inference.buffers[1]); +} + + +static int i2s_init(uint32_t sampling_rate) { + // Start listening for audio: MONO @ 8/16KHz + i2s_config_t i2s_config = { + .mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_TX), + .sample_rate = sampling_rate, + .bits_per_sample = (i2s_bits_per_sample_t)16, + .channel_format = I2S_CHANNEL_FMT_ONLY_RIGHT, + .communication_format = I2S_COMM_FORMAT_I2S, + .intr_alloc_flags = 0, + .dma_buf_count = 8, + .dma_buf_len = 512, + .use_apll = false, + .tx_desc_auto_clear = false, + .fixed_mclk = -1, + }; + i2s_pin_config_t pin_config = { + .bck_io_num = 26, // IIS_SCLK + .ws_io_num = 32, // IIS_LCLK + .data_out_num = -1, // IIS_DSIN + .data_in_num = 33, // IIS_DOUT + }; + esp_err_t ret = 0; + + ret = i2s_driver_install((i2s_port_t)1, &i2s_config, 0, NULL); + if (ret != ESP_OK) { + ei_printf("Error in i2s_driver_install"); + } + + ret = i2s_set_pin((i2s_port_t)1, &pin_config); + if (ret != ESP_OK) { + ei_printf("Error in i2s_set_pin"); + } + + ret = i2s_zero_dma_buffer((i2s_port_t)1); + if (ret != ESP_OK) { + ei_printf("Error in initializing dma buffer with 0"); + } + + return int(ret); +} + +static int i2s_deinit(void) { + i2s_driver_uninstall((i2s_port_t)1); //stop & destroy i2s driver + return 0; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_accelerometer/nano_ble33_sense_accelerometer.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_accelerometer/nano_ble33_sense_accelerometer.ino new file mode 100644 index 0000000..ec63b70 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_accelerometer/nano_ble33_sense_accelerometer.ino @@ -0,0 +1,144 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_lsm9ds1/ + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, but this example use Arudino library which set range to +-4g. If you are using an older model, ignore this value and use 4.0f instead + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + if (!IMU.begin()) { + ei_printf("Failed to initialize IMU!\r\n"); + } + else { + ei_printf("IMU initialized\r\n"); + } + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != 3) { + ei_printf("ERR: EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME should be equal to 3 (the 3 sensor axes)\n"); + return; + } +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\n"); + + delay(2000); + + ei_printf("Sampling...\n"); + + // Allocate a buffer here for the values we'll read from the IMU + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += 3) { + // Determine the next tick (and then sleep later) + uint64_t next_tick = micros() + (EI_CLASSIFIER_INTERVAL_MS * 1000); + + IMU.readAcceleration(buffer[ix], buffer[ix + 1], buffer[ix + 2]); + + for (int i = 0; i < 3; i++) { + if (fabs(buffer[ix + i]) > MAX_ACCEPTED_RANGE) { + buffer[ix + i] = ei_get_sign(buffer[ix + i]) * MAX_ACCEPTED_RANGE; + } + } + + buffer[ix + 0] *= CONVERT_G_TO_MS2; + buffer[ix + 1] *= CONVERT_G_TO_MS2; + buffer[ix + 2] *= CONVERT_G_TO_MS2; + + delayMicroseconds(next_tick - micros()); + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("Failed to create signal from buffer (%d)\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: %.5f\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\n", result.anomaly); +#endif +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_accelerometer_continuous/nano_ble33_sense_accelerometer_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_accelerometer_continuous/nano_ble33_sense_accelerometer_continuous.ino new file mode 100644 index 0000000..40689ea --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_accelerometer_continuous/nano_ble33_sense_accelerometer_continuous.ino @@ -0,0 +1,188 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_lsm9ds1/ + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, but this example use Arudino library which set range to +-4g. If you are using an older model, ignore this value and use 4.0f instead + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static uint32_t run_inference_every_ms = 200; +static rtos::Thread inference_thread(osPriorityLow); +static float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; +static float inference_buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE]; + +/* Forward declaration */ +void run_inference_background(); + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + if (!IMU.begin()) { + ei_printf("Failed to initialize IMU!\r\n"); + } + else { + ei_printf("IMU initialized\r\n"); + } + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != 3) { + ei_printf("ERR: EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME should be equal to 3 (the 3 sensor axes)\n"); + return; + } + + inference_thread.start(mbed::callback(&run_inference_background)); +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +/** + * @brief Run inferencing in the background. + */ +void run_inference_background() +{ + // wait until we have a full buffer + delay((EI_CLASSIFIER_INTERVAL_MS * EI_CLASSIFIER_RAW_SAMPLE_COUNT) + 100); + + // This is a structure that smoothens the output result + // With the default settings 70% of readings should be the same before classifying. + ei_classifier_smooth_t smooth; + ei_classifier_smooth_init(&smooth, 10 /* no. of readings */, 7 /* min. readings the same */, 0.8 /* min. confidence */, 0.3 /* max anomaly */); + + while (1) { + // copy the buffer + memcpy(inference_buffer, buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE * sizeof(float)); + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(inference_buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("Failed to create signal from buffer (%d)\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": "); + + // ei_classifier_smooth_update yields the predicted label + const char *prediction = ei_classifier_smooth_update(&smooth, &result); + ei_printf("%s ", prediction); + // print the cumulative results + ei_printf(" [ "); + for (size_t ix = 0; ix < smooth.count_size; ix++) { + ei_printf("%u", smooth.count[ix]); + if (ix != smooth.count_size + 1) { + ei_printf(", "); + } + else { + ei_printf(" "); + } + } + ei_printf("]\n"); + + delay(run_inference_every_ms); + } + + ei_classifier_smooth_free(&smooth); +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + while (1) { + // Determine the next tick (and then sleep later) + uint64_t next_tick = micros() + (EI_CLASSIFIER_INTERVAL_MS * 1000); + + // roll the buffer -3 points so we can overwrite the last one + numpy::roll(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, -3); + + // read to the end of the buffer + IMU.readAcceleration( + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3], + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 2], + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 1] + ); + + for (int i = 0; i < 3; i++) { + if (fabs(buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3 + i]) > MAX_ACCEPTED_RANGE) { + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3 + i] = ei_get_sign(buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3 + i]) * MAX_ACCEPTED_RANGE; + } + } + + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3] *= CONVERT_G_TO_MS2; + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 2] *= CONVERT_G_TO_MS2; + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 1] *= CONVERT_G_TO_MS2; + + // and wait for next tick + uint64_t time_to_wait = next_tick - micros(); + delay((int)floor((float)time_to_wait / 1000.0f)); + delayMicroseconds(time_to_wait % 1000); + } +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_camera/nano_ble33_sense_camera.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_camera/nano_ble33_sense_camera.ino new file mode 100644 index 0000000..2f05c48 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_camera/nano_ble33_sense_camera.ino @@ -0,0 +1,773 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_ov767x/ + +#include +#include + +/* Constant variables ------------------------------------------------------- */ +#define EI_CAMERA_RAW_FRAME_BUFFER_COLS 160 +#define EI_CAMERA_RAW_FRAME_BUFFER_ROWS 120 + +#define DWORD_ALIGN_PTR(a) ((a & 0x3) ?(((uintptr_t)a + 0x4) & ~(uintptr_t)0x3) : a) + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Edge Impulse ------------------------------------------------------------- */ +class OV7675 : public OV767X { + public: + int begin(int resolution, int format, int fps); + void readFrame(void* buffer); + + private: + int vsyncPin; + int hrefPin; + int pclkPin; + int xclkPin; + + volatile uint32_t* vsyncPort; + uint32_t vsyncMask; + volatile uint32_t* hrefPort; + uint32_t hrefMask; + volatile uint32_t* pclkPort; + uint32_t pclkMask; + + uint16_t width; + uint16_t height; + uint8_t bytes_per_pixel; + uint16_t bytes_per_row; + uint8_t buf_rows; + uint16_t buf_size; + uint8_t resize_height; + uint8_t *raw_buf; + void *buf_mem; + uint8_t *intrp_buf; + uint8_t *buf_limit; + + void readBuf(); + int allocate_scratch_buffs(); + int deallocate_scratch_buffs(); +}; + +typedef struct { + size_t width; + size_t height; +} ei_device_resize_resolutions_t; + +/** + * @brief Check if new serial data is available + * + * @return Returns number of available bytes + */ +int ei_get_serial_available(void) { + return Serial.available(); +} + +/** + * @brief Get next available byte + * + * @return byte + */ +char ei_get_serial_byte(void) { + return Serial.read(); +} + +/* Private variables ------------------------------------------------------- */ +static OV7675 Cam; +static bool is_initialised = false; + +/* +** @brief points to the output of the capture +*/ +static uint8_t *ei_camera_capture_out = NULL; +uint32_t resize_col_sz; +uint32_t resize_row_sz; +bool do_resize = false; +bool do_crop = false; + +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal + +/* Function definitions ------------------------------------------------------- */ +bool ei_camera_init(void); +void ei_camera_deinit(void); +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) ; +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize); +void resizeImage(int srcWidth, int srcHeight, uint8_t *srcImage, int dstWidth, int dstHeight, uint8_t *dstImage, int iBpp); +void cropImage(int srcWidth, int srcHeight, uint8_t *srcImage, int startX, int startY, int dstWidth, int dstHeight, uint8_t *dstImage, int iBpp); + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tImage resolution: %dx%d\n", EI_CLASSIFIER_INPUT_WIDTH, EI_CLASSIFIER_INPUT_HEIGHT); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + bool stop_inferencing = false; + + while(stop_inferencing == false) { + ei_printf("\nStarting inferencing in 2 seconds...\n"); + + // instead of wait_ms, we'll wait on the signal, this allows threads to cancel us... + if (ei_sleep(2000) != EI_IMPULSE_OK) { + break; + } + + ei_printf("Taking photo...\n"); + + if (ei_camera_init() == false) { + ei_printf("ERR: Failed to initialize image sensor\r\n"); + break; + } + + // choose resize dimensions + uint32_t resize_col_sz; + uint32_t resize_row_sz; + bool do_resize = false; + int res = calculate_resize_dimensions(EI_CLASSIFIER_INPUT_WIDTH, EI_CLASSIFIER_INPUT_HEIGHT, &resize_col_sz, &resize_row_sz, &do_resize); + if (res) { + ei_printf("ERR: Failed to calculate resize dimensions (%d)\r\n", res); + break; + } + + void *snapshot_mem = NULL; + uint8_t *snapshot_buf = NULL; + snapshot_mem = ei_malloc(resize_col_sz*resize_row_sz*2); + if(snapshot_mem == NULL) { + ei_printf("failed to create snapshot_mem\r\n"); + break; + } + snapshot_buf = (uint8_t *)DWORD_ALIGN_PTR((uintptr_t)snapshot_mem); + + if (ei_camera_capture(EI_CLASSIFIER_INPUT_WIDTH, EI_CLASSIFIER_INPUT_HEIGHT, snapshot_buf) == false) { + ei_printf("Failed to capture image\r\n"); + if (snapshot_mem) ei_free(snapshot_mem); + break; + } + + ei::signal_t signal; + signal.total_length = EI_CLASSIFIER_INPUT_WIDTH * EI_CLASSIFIER_INPUT_HEIGHT; + signal.get_data = &ei_camera_cutout_get_data; + + // run the impulse: DSP, neural network and the Anomaly algorithm + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR ei_error = run_classifier(&signal, &result, debug_nn); + if (ei_error != EI_IMPULSE_OK) { + ei_printf("Failed to run impulse (%d)\n", ei_error); + ei_free(snapshot_mem); + break; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.): \n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); +#if EI_CLASSIFIER_OBJECT_DETECTION == 1 + ei_printf("Object detection bounding boxes:\r\n"); + for (uint32_t i = 0; i < result.bounding_boxes_count; i++) { + ei_impulse_result_bounding_box_t bb = result.bounding_boxes[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } + + // Print the prediction results (classification) +#else + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } +#endif + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + ei_printf("Visual anomalies:\r\n"); + for (uint32_t i = 0; i < result.visual_ad_count; i++) { + ei_impulse_result_bounding_box_t bb = result.visual_ad_grid_cells[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } +#endif + + while (ei_get_serial_available() > 0) { + if (ei_get_serial_byte() == 'b') { + ei_printf("Inferencing stopped by user\r\n"); + stop_inferencing = true; + } + } + if (snapshot_mem) ei_free(snapshot_mem); + } + ei_camera_deinit(); +} + +/** + * @brief Determine whether to resize and to which dimension + * + * @param[in] out_width width of output image + * @param[in] out_height height of output image + * @param[out] resize_col_sz pointer to frame buffer's column/width value + * @param[out] resize_row_sz pointer to frame buffer's rows/height value + * @param[out] do_resize returns whether to resize (or not) + * + */ +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize) +{ + size_t list_size = 2; + const ei_device_resize_resolutions_t list[list_size] = { {42,32}, {128,96} }; + + // (default) conditions + *resize_col_sz = EI_CAMERA_RAW_FRAME_BUFFER_COLS; + *resize_row_sz = EI_CAMERA_RAW_FRAME_BUFFER_ROWS; + *do_resize = false; + + for (size_t ix = 0; ix < list_size; ix++) { + if ((out_width <= list[ix].width) && (out_height <= list[ix].height)) { + *resize_col_sz = list[ix].width; + *resize_row_sz = list[ix].height; + *do_resize = true; + break; + } + } + + return 0; +} + +/** + * @brief Setup image sensor & start streaming + * + * @retval false if initialisation failed + */ +bool ei_camera_init(void) { + if (is_initialised) return true; + + if (!Cam.begin(QQVGA, RGB565, 1)) { // VGA downsampled to QQVGA (OV7675) + ei_printf("ERR: Failed to initialize camera\r\n"); + return false; + } + is_initialised = true; + + return true; +} + +/** + * @brief Stop streaming of sensor data + */ +void ei_camera_deinit(void) { + if (is_initialised) { + Cam.end(); + is_initialised = false; + } +} + +/** + * @brief Capture, rescale and crop image + * + * @param[in] img_width width of output image + * @param[in] img_height height of output image + * @param[in] out_buf pointer to store output image, NULL may be used + * when full resolution is expected. + * + * @retval false if not initialised, image captured, rescaled or cropped failed + * + */ +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) +{ + if (!is_initialised) { + ei_printf("ERR: Camera is not initialized\r\n"); + return false; + } + + if (!out_buf) { + ei_printf("ERR: invalid parameters\r\n"); + return false; + } + + // choose resize dimensions + int res = calculate_resize_dimensions(img_width, img_height, &resize_col_sz, &resize_row_sz, &do_resize); + if (res) { + ei_printf("ERR: Failed to calculate resize dimensions (%d)\r\n", res); + return false; + } + + if ((img_width != resize_col_sz) + || (img_height != resize_row_sz)) { + do_crop = true; + } + + Cam.readFrame(out_buf); // captures image and resizes + + if (do_crop) { + uint32_t crop_col_sz; + uint32_t crop_row_sz; + uint32_t crop_col_start; + uint32_t crop_row_start; + crop_row_start = (resize_row_sz - img_height) / 2; + crop_col_start = (resize_col_sz - img_width) / 2; + crop_col_sz = img_width; + crop_row_sz = img_height; + + //ei_printf("crop cols: %d, rows: %d\r\n", crop_col_sz,crop_row_sz); + cropImage(resize_col_sz, resize_row_sz, + out_buf, + crop_col_start, crop_row_start, + crop_col_sz, crop_row_sz, + out_buf, + 16); + } + + // The following variables should always be assigned + // if this routine is to return true + // cutout values + //ei_camera_snapshot_is_resized = do_resize; + //ei_camera_snapshot_is_cropped = do_crop; + ei_camera_capture_out = out_buf; + + return true; +} + +/** + * @brief Convert RGB565 raw camera buffer to RGB888 + * + * @param[in] offset pixel offset of raw buffer + * @param[in] length number of pixels to convert + * @param[out] out_buf pointer to store output image + */ +int ei_camera_cutout_get_data(size_t offset, size_t length, float *out_ptr) { + size_t pixel_ix = offset * 2; + size_t bytes_left = length; + size_t out_ptr_ix = 0; + + // read byte for byte + while (bytes_left != 0) { + // grab the value and convert to r/g/b + uint16_t pixel = (ei_camera_capture_out[pixel_ix] << 8) | ei_camera_capture_out[pixel_ix+1]; + uint8_t r, g, b; + r = ((pixel >> 11) & 0x1f) << 3; + g = ((pixel >> 5) & 0x3f) << 2; + b = (pixel & 0x1f) << 3; + + // then convert to out_ptr format + float pixel_f = (r << 16) + (g << 8) + b; + out_ptr[out_ptr_ix] = pixel_f; + + // and go to the next pixel + out_ptr_ix++; + pixel_ix+=2; + bytes_left--; + } + + // and done! + return 0; +} + +// This include file works in the Arduino environment +// to define the Cortex-M intrinsics +#ifdef __ARM_FEATURE_SIMD32 +#include +#endif +// This needs to be < 16 or it won't fit. Cortex-M4 only has SIMD for signed multiplies +#define FRAC_BITS 14 +#define FRAC_VAL (1<> FRAC_BITS; // src y + y_frac = src_y_accum & FRAC_MASK; + src_y_accum += src_y_frac; + ny_frac = FRAC_VAL - y_frac; // y fraction and 1.0 - y fraction + y_frac2 = ny_frac | (y_frac << 16); // for M4/M4 SIMD + s = &srcImage[ty * srcWidth]; + s16 = (uint16_t *)&srcImage[ty * srcWidth * 2]; + d = &dstImage[y * dstWidth]; + d16 = (uint16_t *)&dstImage[y * dstWidth * 2]; + src_x_accum = FRAC_VAL/2; // start at 1/2 pixel in to account for integer downsampling which might miss pixels + if (iBpp == 8) { + for (x=0; x < dstWidth; x++) { + uint32_t tx, p00,p01,p10,p11; + tx = src_x_accum >> FRAC_BITS; + x_frac = src_x_accum & FRAC_MASK; + nx_frac = FRAC_VAL - x_frac; // x fraction and 1.0 - x fraction + x_frac2 = nx_frac | (x_frac << 16); + src_x_accum += src_x_frac; + p00 = s[tx]; p10 = s[tx+1]; + p01 = s[tx+srcWidth]; p11 = s[tx+srcWidth+1]; + #ifdef __ARM_FEATURE_SIMD32 + p00 = __SMLAD(p00 | (p10<<16), x_frac2, FRAC_VAL/2) >> FRAC_BITS; // top line + p01 = __SMLAD(p01 | (p11<<16), x_frac2, FRAC_VAL/2) >> FRAC_BITS; // bottom line + p00 = __SMLAD(p00 | (p01<<16), y_frac2, FRAC_VAL/2) >> FRAC_BITS; // combine + #else // generic C code + p00 = ((p00 * nx_frac) + (p10 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // top line + p01 = ((p01 * nx_frac) + (p11 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // bottom line + p00 = ((p00 * ny_frac) + (p01 * y_frac) + FRAC_VAL/2) >> FRAC_BITS; // combine top + bottom + #endif // Cortex-M4/M7 + *d++ = (uint8_t)p00; // store new pixel + } // for x + } // 8-bpp + else + { // RGB565 + for (x=0; x < dstWidth; x++) { + uint32_t tx, p00,p01,p10,p11; + uint32_t r00, r01, r10, r11, g00, g01, g10, g11, b00, b01, b10, b11; + tx = src_x_accum >> FRAC_BITS; + x_frac = src_x_accum & FRAC_MASK; + nx_frac = FRAC_VAL - x_frac; // x fraction and 1.0 - x fraction + x_frac2 = nx_frac | (x_frac << 16); + src_x_accum += src_x_frac; + p00 = __builtin_bswap16(s16[tx]); p10 = __builtin_bswap16(s16[tx+1]); + p01 = __builtin_bswap16(s16[tx+srcWidth]); p11 = __builtin_bswap16(s16[tx+srcWidth+1]); + #ifdef __ARM_FEATURE_SIMD32 + { + p00 |= (p10 << 16); + p01 |= (p11 << 16); + r00 = (p00 & r_mask) >> 1; g00 = p00 & g_mask; b00 = p00 & b_mask; + r01 = (p01 & r_mask) >> 1; g01 = p01 & g_mask; b01 = p01 & b_mask; + r00 = __SMLAD(r00, x_frac2, FRAC_VAL/2) >> FRAC_BITS; // top line + r01 = __SMLAD(r01, x_frac2, FRAC_VAL/2) >> FRAC_BITS; // bottom line + r00 = __SMLAD(r00 | (r01<<16), y_frac2, FRAC_VAL/2) >> FRAC_BITS; // combine + g00 = __SMLAD(g00, x_frac2, FRAC_VAL/2) >> FRAC_BITS; // top line + g01 = __SMLAD(g01, x_frac2, FRAC_VAL/2) >> FRAC_BITS; // bottom line + g00 = __SMLAD(g00 | (g01<<16), y_frac2, FRAC_VAL/2) >> FRAC_BITS; // combine + b00 = __SMLAD(b00, x_frac2, FRAC_VAL/2) >> FRAC_BITS; // top line + b01 = __SMLAD(b01, x_frac2, FRAC_VAL/2) >> FRAC_BITS; // bottom line + b00 = __SMLAD(b00 | (b01<<16), y_frac2, FRAC_VAL/2) >> FRAC_BITS; // combine + } + #else // generic C code + { + r00 = (p00 & r_mask) >> 1; g00 = p00 & g_mask; b00 = p00 & b_mask; + r10 = (p10 & r_mask) >> 1; g10 = p10 & g_mask; b10 = p10 & b_mask; + r01 = (p01 & r_mask) >> 1; g01 = p01 & g_mask; b01 = p01 & b_mask; + r11 = (p11 & r_mask) >> 1; g11 = p11 & g_mask; b11 = p11 & b_mask; + r00 = ((r00 * nx_frac) + (r10 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // top line + r01 = ((r01 * nx_frac) + (r11 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // bottom line + r00 = ((r00 * ny_frac) + (r01 * y_frac) + FRAC_VAL/2) >> FRAC_BITS; // combine top + bottom + g00 = ((g00 * nx_frac) + (g10 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // top line + g01 = ((g01 * nx_frac) + (g11 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // bottom line + g00 = ((g00 * ny_frac) + (g01 * y_frac) + FRAC_VAL/2) >> FRAC_BITS; // combine top + bottom + b00 = ((b00 * nx_frac) + (b10 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // top line + b01 = ((b01 * nx_frac) + (b11 * x_frac) + FRAC_VAL/2) >> FRAC_BITS; // bottom line + b00 = ((b00 * ny_frac) + (b01 * y_frac) + FRAC_VAL/2) >> FRAC_BITS; // combine top + bottom + } + #endif // Cortex-M4/M7 + r00 = (r00 << 1) & r_mask; + g00 = g00 & g_mask; + b00 = b00 & b_mask; + p00 = (r00 | g00 | b00); // re-combine color components + *d16++ = (uint16_t)__builtin_bswap16(p00); // store new pixel + } // for x + } // 16-bpp + } // for y +} /* resizeImage() */ +// +// Crop +// +// Assumes that the destination buffer is dword-aligned +// optimized for 32-bit MCUs +// Supports 8 and 16-bit pixels +// +void cropImage(int srcWidth, int srcHeight, uint8_t *srcImage, int startX, int startY, int dstWidth, int dstHeight, uint8_t *dstImage, int iBpp) +{ + uint32_t *s32, *d32; + int x, y; + + if (startX < 0 || startX >= srcWidth || startY < 0 || startY >= srcHeight || (startX + dstWidth) > srcWidth || (startY + dstHeight) > srcHeight) + return; // invalid parameters + if (iBpp != 8 && iBpp != 16) + return; + + if (iBpp == 8) { + uint8_t *s, *d; + for (y=0; y +#include + +#define digitalPinToBitMask(P) (1 << (digitalPinToPinName(P) % 32)) +#define portInputRegister(P) ((P == 0) ? &NRF_P0->IN : &NRF_P1->IN) + +// +// OV7675::begin() +// +// Extends the OV767X library function. Some private variables are needed +// to use the OV7675::readFrame function. +// +int OV7675::begin(int resolution, int format, int fps) +{ + pinMode(OV7670_VSYNC, INPUT); + pinMode(OV7670_HREF, INPUT); + pinMode(OV7670_PLK, INPUT); + pinMode(OV7670_XCLK, OUTPUT); + + vsyncPort = portInputRegister(digitalPinToPort(OV7670_VSYNC)); + vsyncMask = digitalPinToBitMask(OV7670_VSYNC); + hrefPort = portInputRegister(digitalPinToPort(OV7670_HREF)); + hrefMask = digitalPinToBitMask(OV7670_HREF); + pclkPort = portInputRegister(digitalPinToPort(OV7670_PLK)); + pclkMask = digitalPinToBitMask(OV7670_PLK); + + // init driver to use full image sensor size + bool ret = OV767X::begin(VGA, format, fps); + width = OV767X::width(); // full sensor width + height = OV767X::height(); // full sensor height + bytes_per_pixel = OV767X::bytesPerPixel(); + bytes_per_row = width * bytes_per_pixel; // each pixel is 2 bytes + resize_height = 2; + + buf_mem = NULL; + raw_buf = NULL; + intrp_buf = NULL; + //allocate_scratch_buffs(); + + return ret; +} /* OV7675::begin() */ + +int OV7675::allocate_scratch_buffs() +{ + //ei_printf("allocating buffers..\r\n"); + buf_rows = height / resize_row_sz * resize_height; + buf_size = bytes_per_row * buf_rows; + + buf_mem = ei_malloc(buf_size); + if(buf_mem == NULL) { + ei_printf("failed to create buf_mem\r\n"); + return false; + } + raw_buf = (uint8_t *)DWORD_ALIGN_PTR((uintptr_t)buf_mem); + + //ei_printf("allocating buffers OK\r\n"); + return 0; +} + +int OV7675::deallocate_scratch_buffs() +{ + //ei_printf("deallocating buffers...\r\n"); + ei_free(buf_mem); + buf_mem = NULL; + + //ei_printf("deallocating buffers OK\r\n"); + return 0; +} + +// +// OV7675::readFrame() +// +// Overrides the OV767X library function. Fixes the camera output to be +// a far more desirable image. This image utilizes the full sensor size +// and has the correct aspect ratio. Since there is limited memory on the +// Nano we bring in only part of the entire sensor at a time and then +// interpolate to a lower resolution. +// +void OV7675::readFrame(void* buffer) +{ + allocate_scratch_buffs(); + + uint8_t* out = (uint8_t*)buffer; + noInterrupts(); + + // Falling edge indicates start of frame + while ((*vsyncPort & vsyncMask) == 0); // wait for HIGH + while ((*vsyncPort & vsyncMask) != 0); // wait for LOW + + int out_row = 0; + for (int raw_height = 0; raw_height < height; raw_height += buf_rows) { + // read in 640xbuf_rows buffer to work with + readBuf(); + + resizeImage(width, buf_rows, + raw_buf, + resize_col_sz, resize_height, + &(out[out_row]), + 16); + + out_row += resize_col_sz * resize_height * bytes_per_pixel; /* resize_col_sz * 2 * 2 */ + } + + interrupts(); + + deallocate_scratch_buffs(); +} /* OV7675::readFrame() */ + +// +// OV7675::readBuf() +// +// Extends the OV767X library function. Reads buf_rows VGA rows from the +// image sensor. +// +void OV7675::readBuf() +{ + int offset = 0; + + uint32_t ulPin = 33; // P1.xx set of GPIO is in 'pin' 32 and above + NRF_GPIO_Type * port; + + port = nrf_gpio_pin_port_decode(&ulPin); + + for (int i = 0; i < buf_rows; i++) { + // rising edge indicates start of line + while ((*hrefPort & hrefMask) == 0); // wait for HIGH + + for (int col = 0; col < bytes_per_row; col++) { + // rising edges clock each data byte + while ((*pclkPort & pclkMask) != 0); // wait for LOW + + uint32_t in = port->IN; // read all bits in parallel + + in >>= 2; // place bits 0 and 1 at the "bottom" of the register + in &= 0x3f03; // isolate the 8 bits we care about + in |= (in >> 6); // combine the upper 6 and lower 2 bits + + raw_buf[offset++] = in; + + while ((*pclkPort & pclkMask) == 0); // wait for HIGH + } + + while ((*hrefPort & hrefMask) != 0); // wait for LOW + } +} /* OV7675::readBuf() */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_fusion/nano_ble33_sense_fusion.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_fusion/nano_ble33_sense_fusion.ino new file mode 100644 index 0000000..2a52005 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_fusion/nano_ble33_sense_fusion.ino @@ -0,0 +1,388 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_lsm9ds1/ +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_lps22hb/ +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_hts221/ +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_apds9960/ + +enum sensor_status { + NOT_USED = -1, + NOT_INIT, + INIT, + SAMPLED +}; + +/** Struct to link sensor axis name to sensor value function */ +typedef struct{ + const char *name; + float *value; + uint8_t (*poll_sensor)(void); + bool (*init_sensor)(void); + sensor_status status; +} eiSensors; + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, + // but this example use Arudino library which set range to +-4g. + // If you are using an older model, ignore this value and use 4.0f instead +/** Number sensor axes used */ +#define N_SENSORS 18 + +/* Forward declarations ------------------------------------------------------- */ +float ei_get_sign(float number); + +bool init_IMU(void); +bool init_HTS(void); +bool init_BARO(void); +bool init_APDS(void); + +uint8_t poll_acc(void); +uint8_t poll_gyr(void); +uint8_t poll_mag(void); +uint8_t poll_HTS(void); +uint8_t poll_BARO(void); +uint8_t poll_APDS_color(void); +uint8_t poll_APDS_proximity(void); +uint8_t poll_APDS_gesture(void); + +/* Private variables ------------------------------------------------------- */ +static const bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal + +static float data[N_SENSORS]; +static bool ei_connect_fusion_list(const char *input_list); + +static int8_t fusion_sensors[N_SENSORS]; +static int fusion_ix = 0; + +/** Used sensors value function connected to label name */ +eiSensors sensors[] = +{ + "accX", &data[0], &poll_acc, &init_IMU, NOT_USED, + "accY", &data[1], &poll_acc, &init_IMU, NOT_USED, + "accZ", &data[2], &poll_acc, &init_IMU, NOT_USED, + "gyrX", &data[3], &poll_gyr, &init_IMU, NOT_USED, + "gyrY", &data[4], &poll_gyr, &init_IMU, NOT_USED, + "gyrZ", &data[5], &poll_gyr, &init_IMU, NOT_USED, + "magX", &data[6], &poll_mag, &init_IMU, NOT_USED, + "magY", &data[7], &poll_mag, &init_IMU, NOT_USED, + "magZ", &data[8], &poll_mag, &init_IMU, NOT_USED, + + "temperature", &data[9], &poll_HTS, &init_HTS, NOT_USED, + "humidity", &data[10], &poll_HTS, &init_HTS, NOT_USED, + + "pressure", &data[11], &poll_BARO, &init_BARO, NOT_USED, + + "red", &data[12], &poll_APDS_color, &init_APDS, NOT_USED, + "green", &data[13], &poll_APDS_color, &init_APDS, NOT_USED, + "blue", &data[14], &poll_APDS_color, &init_APDS, NOT_USED, + "brightness", &data[15], &poll_APDS_color, &init_APDS, NOT_USED, + "proximity", &data[16], &poll_APDS_proximity, &init_APDS, NOT_USED, + "gesture", &data[17], &poll_APDS_gesture,&init_APDS, NOT_USED, +}; + +/** +* @brief Arduino setup function +*/ +void setup() +{ + /* Init serial */ + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Sensor Fusion Inference\r\n"); + + /* Connect used sensors */ + if(ei_connect_fusion_list(EI_CLASSIFIER_FUSION_AXES_STRING) == false) { + ei_printf("ERR: Errors in sensor list detected\r\n"); + return; + } + + /* Init & start sensors */ + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == NOT_INIT) { + sensors[fusion_sensors[i]].status = (sensor_status)sensors[fusion_sensors[i]].init_sensor(); + if (!sensors[fusion_sensors[i]].status) { + ei_printf("%s axis sensor initialization failed.\r\n", sensors[fusion_sensors[i]].name); + } + else { + ei_printf("%s axis sensor initialization successful.\r\n", sensors[fusion_sensors[i]].name); + } + } + } +} + +/** +* @brief Get data and run inferencing +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\r\n"); + + delay(2000); + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != fusion_ix) { + ei_printf("ERR: Sensors don't match the sensors required in the model\r\n" + "Following sensors are required: %s\r\n", EI_CLASSIFIER_FUSION_AXES_STRING); + return; + } + + ei_printf("Sampling...\r\n"); + + // Allocate a buffer here for the values we'll read from the sensor + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME) { + // Determine the next tick (and then sleep later) + int64_t next_tick = (int64_t)micros() + ((int64_t)EI_CLASSIFIER_INTERVAL_MS * 1000); + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == INIT) { + sensors[fusion_sensors[i]].poll_sensor(); + sensors[fusion_sensors[i]].status = SAMPLED; + } + if (sensors[fusion_sensors[i]].status == SAMPLED) { + buffer[ix + i] = *sensors[fusion_sensors[i]].value; + sensors[fusion_sensors[i]].status = INIT; + } + } + + int64_t wait_time = next_tick - (int64_t)micros(); + + if(wait_time > 0) { + delayMicroseconds(wait_time); + } + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.):\r\n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf("%s: %.5f\r\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\r\n", result.anomaly); +#endif +} + +#if !defined(EI_CLASSIFIER_SENSOR) || (EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_FUSION && EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER) +#error "Invalid model for current sensor" +#endif + + +/** + * @brief Go through sensor list to find matching axis name + * + * @param axis_name + * @return int8_t index in sensor list, -1 if axis name is not found + */ +static int8_t ei_find_axis(char *axis_name) +{ + int ix; + for(ix = 0; ix < N_SENSORS; ix++) { + if(strstr(axis_name, sensors[ix].name)) { + return ix; + } + } + return -1; +} + +/** + * @brief Check if requested input list is valid sensor fusion, create sensor buffer + * + * @param[in] input_list Axes list to sample (ie. "accX + gyrY + magZ") + * @retval false if invalid sensor_list + */ +static bool ei_connect_fusion_list(const char *input_list) +{ + char *buff; + bool is_fusion = false; + + /* Copy const string in heap mem */ + char *input_string = (char *)ei_malloc(strlen(input_list) + 1); + if (input_string == NULL) { + return false; + } + memset(input_string, 0, strlen(input_list) + 1); + strncpy(input_string, input_list, strlen(input_list)); + + /* Clear fusion sensor list */ + memset(fusion_sensors, 0, N_SENSORS); + fusion_ix = 0; + + buff = strtok(input_string, "+"); + + while (buff != NULL) { /* Run through buffer */ + int8_t found_axis = 0; + + is_fusion = false; + found_axis = ei_find_axis(buff); + + if(found_axis >= 0) { + if(fusion_ix < N_SENSORS) { + fusion_sensors[fusion_ix++] = found_axis; + sensors[found_axis].status = NOT_INIT; + } + is_fusion = true; + } + + buff = strtok(NULL, "+ "); + } + + ei_free(input_string); + + return is_fusion; +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +bool init_IMU(void) { + static bool init_status = false; + if (!init_status) { + init_status = IMU.begin(); + } + return init_status; +} + +bool init_HTS(void) { + static bool init_status = false; + if (!init_status) { + init_status = HTS.begin(); + } + return init_status; +} + +bool init_BARO(void) { + static bool init_status = false; + if (!init_status) { + init_status = BARO.begin(); + } + return init_status; +} + +bool init_APDS(void) { + static bool init_status = false; + if (!init_status) { + init_status = APDS.begin(); + } + return init_status; +} + +uint8_t poll_acc(void) { + + if (IMU.accelerationAvailable()) { + + IMU.readAcceleration(data[0], data[1], data[2]); + + for (int i = 0; i < 3; i++) { + if (fabs(data[i]) > MAX_ACCEPTED_RANGE) { + data[i] = ei_get_sign(data[i]) * MAX_ACCEPTED_RANGE; + } + } + + data[0] *= CONVERT_G_TO_MS2; + data[1] *= CONVERT_G_TO_MS2; + data[2] *= CONVERT_G_TO_MS2; + } + + return 0; +} + +uint8_t poll_gyr(void) { + + if (IMU.gyroscopeAvailable()) { + IMU.readGyroscope(data[3], data[4], data[5]); + } + return 0; +} + +uint8_t poll_mag(void) { + + if (IMU.magneticFieldAvailable()) { + IMU.readMagneticField(data[6], data[7], data[8]); + } + return 0; +} + +uint8_t poll_HTS(void) { + + data[9] = HTS.readTemperature(); + data[10] = HTS.readHumidity(); + return 0; +} + +uint8_t poll_BARO(void) { + + data[11] = BARO.readPressure(); // (PSI/MILLIBAR/KILOPASCAL) default kPa + return 0; +} + +uint8_t poll_APDS_color(void) { + + int temp_data[4]; + if (APDS.colorAvailable()) { + APDS.readColor(temp_data[0], temp_data[1], temp_data[2], temp_data[3]); + + data[12] = temp_data[0]; + data[13] = temp_data[1]; + data[14] = temp_data[2]; + data[15] = temp_data[3]; + } +} + +uint8_t poll_APDS_proximity(void) { + + if (APDS.proximityAvailable()) { + data[16] = (float)APDS.readProximity(); + } + return 0; +} + +uint8_t poll_APDS_gesture(void) { + if (APDS.gestureAvailable()) { + data[17] = (float)APDS.readGesture(); + } + return 0; +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_microphone/nano_ble33_sense_microphone.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_microphone/nano_ble33_sense_microphone.ino new file mode 100644 index 0000000..2451eae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_microphone/nano_ble33_sense_microphone.ino @@ -0,0 +1,220 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + int16_t *buffer; + uint8_t buf_ready; + uint32_t buf_count; + uint32_t n_samples; +} inference_t; + +static inference_t inference; +static signed short sampleBuffer[2048]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: %.2f ms.\n", (float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + if (microphone_inference_start(EI_CLASSIFIER_RAW_SAMPLE_COUNT) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + ei_printf("Starting inferencing in 2 seconds...\n"); + + delay(2000); + + ei_printf("Recording...\n"); + + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + ei_printf("Recording done\n"); + + signal_t signal; + signal.total_length = EI_CLASSIFIER_RAW_SAMPLE_COUNT; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR r = run_classifier(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: %.5f\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\n", result.anomaly); +#endif +} + +/** + * @brief PDM buffer full callback + * Get data and call audio thread callback + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if (inference.buf_ready == 0) { + for(int i = 0; i < bytesRead>>1; i++) { + inference.buffer[inference.buf_count++] = sampleBuffer[i]; + + if(inference.buf_count >= inference.n_samples) { + inference.buf_count = 0; + inference.buf_ready = 1; + break; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffer = (int16_t *)malloc(n_samples * sizeof(int16_t)); + + if(inference.buffer == NULL) { + return false; + } + + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(&pdm_data_ready_inference_callback); + + PDM.setBufferSize(4096); + + // initialize PDM with: + // - one channel (mono mode) + // - a 16 kHz sample rate + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("Failed to start PDM!"); + microphone_inference_end(); + + return false; + } + + // set the gain, defaults to 20 + PDM.setGain(127); + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + inference.buf_ready = 0; + inference.buf_count = 0; + + while(inference.buf_ready == 0) { + delay(10); + } + + return true; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffer[offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + free(inference.buffer); +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_microphone_continuous/nano_ble33_sense_microphone_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_microphone_continuous/nano_ble33_sense_microphone_continuous.ino new file mode 100644 index 0000000..164bbb9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense/nano_ble33_sense_microphone_continuous/nano_ble33_sense_microphone_continuous.ino @@ -0,0 +1,254 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/** + * Define the number of slices per model window. E.g. a model window of 1000 ms + * with slices per model window set to 4. Results in a slice size of 250 ms. + * For more info: https://docs.edgeimpulse.com/docs/continuous-audio-sampling + */ +#define EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW 4 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + signed short *buffers[2]; + unsigned char buf_select; + unsigned char buf_ready; + unsigned int buf_count; + unsigned int n_samples; +} inference_t; + +static inference_t inference; +static bool record_ready = false; +static signed short *sampleBuffer; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static int print_results = -(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW); + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: %.2f ms.\n", (float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / + sizeof(ei_classifier_inferencing_categories[0])); + + run_classifier_init(); + if (microphone_inference_start(EI_CLASSIFIER_SLICE_SIZE) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + signal_t signal; + signal.total_length = EI_CLASSIFIER_SLICE_SIZE; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = {0}; + + EI_IMPULSE_ERROR r = run_classifier_continuous(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + if (++print_results >= (EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)) { + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: %.5f\n", result.classification[ix].label, + result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\n", result.anomaly); +#endif + + print_results = 0; + } +} + +/** + * @brief PDM buffer full callback + * Get data and call audio thread callback + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if (record_ready == true) { + for (int i = 0; i> 1; i++) { + inference.buffers[inference.buf_select][inference.buf_count++] = sampleBuffer[i]; + + if (inference.buf_count >= inference.n_samples) { + inference.buf_select ^= 1; + inference.buf_count = 0; + inference.buf_ready = 1; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffers[0] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[0] == NULL) { + return false; + } + + inference.buffers[1] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[1] == NULL) { + free(inference.buffers[0]); + return false; + } + + sampleBuffer = (signed short *)malloc((n_samples >> 1) * sizeof(signed short)); + + if (sampleBuffer == NULL) { + free(inference.buffers[0]); + free(inference.buffers[1]); + return false; + } + + inference.buf_select = 0; + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(&pdm_data_ready_inference_callback); + + PDM.setBufferSize((n_samples >> 1) * sizeof(int16_t)); + + // initialize PDM with: + // - one channel (mono mode) + // - a 16 kHz sample rate + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("Failed to start PDM!"); + } + + // set the gain, defaults to 20 + PDM.setGain(127); + + record_ready = true; + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + if (inference.buf_ready == 1) { + ei_printf( + "Error sample buffer overrun. Decrease the number of slices per model window " + "(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)\n"); + ret = false; + } + + while (inference.buf_ready == 0) { + delay(1); + } + + inference.buf_ready = 0; + + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffers[inference.buf_select ^ 1][offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + free(inference.buffers[0]); + free(inference.buffers[1]); + free(sampleBuffer); +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_accelerometer/nano_ble33_sense_rev2_accelerometer.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_accelerometer/nano_ble33_sense_rev2_accelerometer.ino new file mode 100644 index 0000000..4bb962d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_accelerometer/nano_ble33_sense_rev2_accelerometer.ino @@ -0,0 +1,145 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_bmi270_bmm150/ + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, but this example use Arudino library which set range to +-4g. If you are using an older model, ignore this value and use 4.0f instead + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + if (!IMU.begin()) { + ei_printf("Failed to initialize IMU!\r\n"); + } + else { + IMU.setContinuousMode(); + ei_printf("IMU initialized\r\n"); + } + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != 3) { + ei_printf("ERR: EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME should be equal to 3 (the 3 sensor axes)\n"); + return; + } +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\n"); + + delay(2000); + + ei_printf("Sampling...\n"); + + // Allocate a buffer here for the values we'll read from the IMU + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += 3) { + // Determine the next tick (and then sleep later) + uint64_t next_tick = micros() + (EI_CLASSIFIER_INTERVAL_MS * 1000); + + IMU.readAcceleration(buffer[ix], buffer[ix + 1], buffer[ix + 2]); + + for (int i = 0; i < 3; i++) { + if (fabs(buffer[ix + i]) > MAX_ACCEPTED_RANGE) { + buffer[ix + i] = ei_get_sign(buffer[ix + i]) * MAX_ACCEPTED_RANGE; + } + } + + buffer[ix + 0] *= CONVERT_G_TO_MS2; + buffer[ix + 1] *= CONVERT_G_TO_MS2; + buffer[ix + 2] *= CONVERT_G_TO_MS2; + + delayMicroseconds(next_tick - micros()); + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("Failed to create signal from buffer (%d)\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: %.5f\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\n", result.anomaly); +#endif +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_accelerometer_continuous/nano_ble33_sense_rev2_accelerometer_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_accelerometer_continuous/nano_ble33_sense_rev2_accelerometer_continuous.ino new file mode 100644 index 0000000..18943dd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_accelerometer_continuous/nano_ble33_sense_rev2_accelerometer_continuous.ino @@ -0,0 +1,189 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_bmi270_bmm150/ + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, but this example use Arudino library which set range to +-4g. If you are using an older model, ignore this value and use 4.0f instead + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static uint32_t run_inference_every_ms = 200; +static rtos::Thread inference_thread(osPriorityLow); +static float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; +static float inference_buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE]; + +/* Forward declaration */ +void run_inference_background(); + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + if (!IMU.begin()) { + ei_printf("Failed to initialize IMU!\r\n"); + } + else { + IMU.setContinuousMode(); + ei_printf("IMU initialized\r\n"); + } + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != 3) { + ei_printf("ERR: EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME should be equal to 3 (the 3 sensor axes)\n"); + return; + } + + inference_thread.start(mbed::callback(&run_inference_background)); +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +/** + * @brief Run inferencing in the background. + */ +void run_inference_background() +{ + // wait until we have a full buffer + delay((EI_CLASSIFIER_INTERVAL_MS * EI_CLASSIFIER_RAW_SAMPLE_COUNT) + 100); + + // This is a structure that smoothens the output result + // With the default settings 70% of readings should be the same before classifying. + ei_classifier_smooth_t smooth; + ei_classifier_smooth_init(&smooth, 10 /* no. of readings */, 7 /* min. readings the same */, 0.8 /* min. confidence */, 0.3 /* max anomaly */); + + while (1) { + // copy the buffer + memcpy(inference_buffer, buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE * sizeof(float)); + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(inference_buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("Failed to create signal from buffer (%d)\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": "); + + // ei_classifier_smooth_update yields the predicted label + const char *prediction = ei_classifier_smooth_update(&smooth, &result); + ei_printf("%s ", prediction); + // print the cumulative results + ei_printf(" [ "); + for (size_t ix = 0; ix < smooth.count_size; ix++) { + ei_printf("%u", smooth.count[ix]); + if (ix != smooth.count_size + 1) { + ei_printf(", "); + } + else { + ei_printf(" "); + } + } + ei_printf("]\n"); + + delay(run_inference_every_ms); + } + + ei_classifier_smooth_free(&smooth); +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + while (1) { + // Determine the next tick (and then sleep later) + uint64_t next_tick = micros() + (EI_CLASSIFIER_INTERVAL_MS * 1000); + + // roll the buffer -3 points so we can overwrite the last one + numpy::roll(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, -3); + + // read to the end of the buffer + IMU.readAcceleration( + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3], + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 2], + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 1] + ); + + for (int i = 0; i < 3; i++) { + if (fabs(buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3 + i]) > MAX_ACCEPTED_RANGE) { + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3 + i] = ei_get_sign(buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3 + i]) * MAX_ACCEPTED_RANGE; + } + } + + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 3] *= CONVERT_G_TO_MS2; + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 2] *= CONVERT_G_TO_MS2; + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE - 1] *= CONVERT_G_TO_MS2; + + // and wait for next tick + uint64_t time_to_wait = next_tick - micros(); + delay((int)floor((float)time_to_wait / 1000.0f)); + delayMicroseconds(time_to_wait % 1000); + } +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_fusion/nano_ble33_sense_rev2_fusion.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_fusion/nano_ble33_sense_rev2_fusion.ino new file mode 100644 index 0000000..2083aad --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nano_ble33_sense_rev2/nano_ble33_sense_rev2_fusion/nano_ble33_sense_rev2_fusion.ino @@ -0,0 +1,388 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_bmi270_bmm150/ +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_lps22hb/ +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_hs300x/ +#include //Click here to get the library: https://www.arduino.cc/reference/en/libraries/arduino_apds9960/ + +enum sensor_status { + NOT_USED = -1, + NOT_INIT, + INIT, + SAMPLED +}; + +/** Struct to link sensor axis name to sensor value function */ +typedef struct{ + const char *name; + float *value; + uint8_t (*poll_sensor)(void); + bool (*init_sensor)(void); + sensor_status status; +} eiSensors; + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, + // but this example use Arudino library which set range to +-4g. + // If you are using an older model, ignore this value and use 4.0f instead +/** Number sensor axes used */ +#define N_SENSORS 18 + +/* Forward declarations ------------------------------------------------------- */ +float ei_get_sign(float number); + +bool init_IMU(void); +bool init_HTS(void); +bool init_BARO(void); +bool init_APDS(void); + +uint8_t poll_acc(void); +uint8_t poll_gyr(void); +uint8_t poll_mag(void); +uint8_t poll_HTS(void); +uint8_t poll_BARO(void); +uint8_t poll_APDS_color(void); +uint8_t poll_APDS_proximity(void); +uint8_t poll_APDS_gesture(void); + +/* Private variables ------------------------------------------------------- */ +static const bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal + +static float data[N_SENSORS]; +static bool ei_connect_fusion_list(const char *input_list); + +static int8_t fusion_sensors[N_SENSORS]; +static int fusion_ix = 0; + +/** Used sensors value function connected to label name */ +eiSensors sensors[] = +{ + "accX", &data[0], &poll_acc, &init_IMU, NOT_USED, + "accY", &data[1], &poll_acc, &init_IMU, NOT_USED, + "accZ", &data[2], &poll_acc, &init_IMU, NOT_USED, + "gyrX", &data[3], &poll_gyr, &init_IMU, NOT_USED, + "gyrY", &data[4], &poll_gyr, &init_IMU, NOT_USED, + "gyrZ", &data[5], &poll_gyr, &init_IMU, NOT_USED, + "magX", &data[6], &poll_mag, &init_IMU, NOT_USED, + "magY", &data[7], &poll_mag, &init_IMU, NOT_USED, + "magZ", &data[8], &poll_mag, &init_IMU, NOT_USED, + + "temperature", &data[9], &poll_HTS, &init_HTS, NOT_USED, + "humidity", &data[10], &poll_HTS, &init_HTS, NOT_USED, + + "pressure", &data[11], &poll_BARO, &init_BARO, NOT_USED, + + "red", &data[12], &poll_APDS_color, &init_APDS, NOT_USED, + "green", &data[13], &poll_APDS_color, &init_APDS, NOT_USED, + "blue", &data[14], &poll_APDS_color, &init_APDS, NOT_USED, + "brightness", &data[15], &poll_APDS_color, &init_APDS, NOT_USED, + "proximity", &data[16], &poll_APDS_proximity, &init_APDS, NOT_USED, + "gesture", &data[17], &poll_APDS_gesture,&init_APDS, NOT_USED, +}; + +/** +* @brief Arduino setup function +*/ +void setup() +{ + /* Init serial */ + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Sensor Fusion Inference\r\n"); + + /* Connect used sensors */ + if(ei_connect_fusion_list(EI_CLASSIFIER_FUSION_AXES_STRING) == false) { + ei_printf("ERR: Errors in sensor list detected\r\n"); + return; + } + + /* Init & start sensors */ + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == NOT_INIT) { + sensors[fusion_sensors[i]].status = (sensor_status)sensors[fusion_sensors[i]].init_sensor(); + if (!sensors[fusion_sensors[i]].status) { + ei_printf("%s axis sensor initialization failed.\r\n", sensors[fusion_sensors[i]].name); + } + else { + ei_printf("%s axis sensor initialization successful.\r\n", sensors[fusion_sensors[i]].name); + } + } + } +} + +/** +* @brief Get data and run inferencing +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\r\n"); + + delay(2000); + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != fusion_ix) { + ei_printf("ERR: Sensors don't match the sensors required in the model\r\n" + "Following sensors are required: %s\r\n", EI_CLASSIFIER_FUSION_AXES_STRING); + return; + } + + ei_printf("Sampling...\r\n"); + + // Allocate a buffer here for the values we'll read from the sensor + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME) { + // Determine the next tick (and then sleep later) + int64_t next_tick = (int64_t)micros() + ((int64_t)EI_CLASSIFIER_INTERVAL_MS * 1000); + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == INIT) { + sensors[fusion_sensors[i]].poll_sensor(); + sensors[fusion_sensors[i]].status = SAMPLED; + } + if (sensors[fusion_sensors[i]].status == SAMPLED) { + buffer[ix + i] = *sensors[fusion_sensors[i]].value; + sensors[fusion_sensors[i]].status = INIT; + } + } + + int64_t wait_time = next_tick - (int64_t)micros(); + + if(wait_time > 0) { + delayMicroseconds(wait_time); + } + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.):\r\n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf("%s: %.5f\r\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\r\n", result.anomaly); +#endif +} + +#if !defined(EI_CLASSIFIER_SENSOR) || (EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_FUSION && EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER) +#error "Invalid model for current sensor" +#endif + + +/** + * @brief Go through sensor list to find matching axis name + * + * @param axis_name + * @return int8_t index in sensor list, -1 if axis name is not found + */ +static int8_t ei_find_axis(char *axis_name) +{ + int ix; + for(ix = 0; ix < N_SENSORS; ix++) { + if(strstr(axis_name, sensors[ix].name)) { + return ix; + } + } + return -1; +} + +/** + * @brief Check if requested input list is valid sensor fusion, create sensor buffer + * + * @param[in] input_list Axes list to sample (ie. "accX + gyrY + magZ") + * @retval false if invalid sensor_list + */ +static bool ei_connect_fusion_list(const char *input_list) +{ + char *buff; + bool is_fusion = false; + + /* Copy const string in heap mem */ + char *input_string = (char *)ei_malloc(strlen(input_list) + 1); + if (input_string == NULL) { + return false; + } + memset(input_string, 0, strlen(input_list) + 1); + strncpy(input_string, input_list, strlen(input_list)); + + /* Clear fusion sensor list */ + memset(fusion_sensors, 0, N_SENSORS); + fusion_ix = 0; + + buff = strtok(input_string, "+"); + + while (buff != NULL) { /* Run through buffer */ + int8_t found_axis = 0; + + is_fusion = false; + found_axis = ei_find_axis(buff); + + if(found_axis >= 0) { + if(fusion_ix < N_SENSORS) { + fusion_sensors[fusion_ix++] = found_axis; + sensors[found_axis].status = NOT_INIT; + } + is_fusion = true; + } + + buff = strtok(NULL, "+ "); + } + + ei_free(input_string); + + return is_fusion; +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +bool init_IMU(void) { + static bool init_status = false; + if (!init_status) { + init_status = IMU.begin(); + } + return init_status; +} + +bool init_HTS(void) { + static bool init_status = false; + if (!init_status) { + init_status = HS300x.begin(); + } + return init_status; +} + +bool init_BARO(void) { + static bool init_status = false; + if (!init_status) { + init_status = BARO.begin(); + } + return init_status; +} + +bool init_APDS(void) { + static bool init_status = false; + if (!init_status) { + init_status = APDS.begin(); + } + return init_status; +} + +uint8_t poll_acc(void) { + + if (IMU.accelerationAvailable()) { + + IMU.readAcceleration(data[0], data[1], data[2]); + + for (int i = 0; i < 3; i++) { + if (fabs(data[i]) > MAX_ACCEPTED_RANGE) { + data[i] = ei_get_sign(data[i]) * MAX_ACCEPTED_RANGE; + } + } + + data[0] *= CONVERT_G_TO_MS2; + data[1] *= CONVERT_G_TO_MS2; + data[2] *= CONVERT_G_TO_MS2; + } + + return 0; +} + +uint8_t poll_gyr(void) { + + if (IMU.gyroscopeAvailable()) { + IMU.readGyroscope(data[3], data[4], data[5]); + } + return 0; +} + +uint8_t poll_mag(void) { + + if (IMU.magneticFieldAvailable()) { + IMU.readMagneticField(data[6], data[7], data[8]); + } + return 0; +} + +uint8_t poll_HTS(void) { + + data[9] = HS300x.readTemperature(); + data[10] = HS300x.readHumidity(); + return 0; +} + +uint8_t poll_BARO(void) { + + data[11] = BARO.readPressure(); // (PSI/MILLIBAR/KILOPASCAL) default kPa + return 0; +} + +uint8_t poll_APDS_color(void) { + + int temp_data[4]; + if (APDS.colorAvailable()) { + APDS.readColor(temp_data[0], temp_data[1], temp_data[2], temp_data[3]); + + data[12] = temp_data[0]; + data[13] = temp_data[1]; + data[14] = temp_data[2]; + data[15] = temp_data[3]; + } +} + +uint8_t poll_APDS_proximity(void) { + + if (APDS.proximityAvailable()) { + data[16] = (float)APDS.readProximity(); + } + return 0; +} + +uint8_t poll_APDS_gesture(void) { + if (APDS.gestureAvailable()) { + data[17] = (float)APDS.readGesture(); + } + return 0; +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_sense/nicla_sense_fusion/nicla_sense_fusion.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_sense/nicla_sense_fusion/nicla_sense_fusion.ino new file mode 100644 index 0000000..5a42a64 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_sense/nicla_sense_fusion/nicla_sense_fusion.ino @@ -0,0 +1,252 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include "Arduino_BHY2.h" //Click here to get the library: http://librarymanager/All#Arduino_BHY2 + +/** Struct to link sensor axis name to sensor value function */ +typedef struct{ + const char *name; + float (*get_value)(void); + +}eiSensors; + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f + +/** Number sensor axes used */ +#define NICLA_N_SENSORS 17 + + +/* Private variables ------------------------------------------------------- */ +static const bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal + +SensorXYZ accel(SENSOR_ID_ACC); +SensorXYZ gyro(SENSOR_ID_GYRO); +SensorOrientation ori(SENSOR_ID_ORI); +SensorQuaternion rotation(SENSOR_ID_RV); +Sensor temp(SENSOR_ID_TEMP); +Sensor baro(SENSOR_ID_BARO); +Sensor hum(SENSOR_ID_HUM); +Sensor gas(SENSOR_ID_GAS); + +static bool ei_connect_fusion_list(const char *input_list); +static float get_accX(void){return (accel.x() * 8.0 / 32768.0) * CONVERT_G_TO_MS2;} +static float get_accY(void){return (accel.y() * 8.0 / 32768.0) * CONVERT_G_TO_MS2;} +static float get_accZ(void){return (accel.z() * 8.0 / 32768.0) * CONVERT_G_TO_MS2;} +static float get_gyrX(void){return (gyro.x() * 8.0 / 32768.0) * CONVERT_G_TO_MS2;} +static float get_gyrY(void){return (gyro.y() * 8.0 / 32768.0) * CONVERT_G_TO_MS2;} +static float get_gyrZ(void){return (gyro.z() * 8.0 / 32768.0) * CONVERT_G_TO_MS2;} +static float get_oriHeading(void){return ori.heading();} +static float get_oriPitch(void){return ori.pitch();} +static float get_oriRoll(void){return ori.roll();} +static float get_rotX(void){return rotation.x();} +static float get_rotY(void){return rotation.y();} +static float get_rotZ(void){return rotation.z();} +static float get_rotW(void){return rotation.w();} +static float get_temperature(void){return temp.value();} +static float get_barrometric_pressure(void){return baro.value();} +static float get_humidity(void){return hum.value();} +static float get_gas(void){return gas.value();} + +static int8_t fusion_sensors[NICLA_N_SENSORS]; +static int fusion_ix = 0; + +/** Used sensors value function connected to label name */ +eiSensors nicla_sensors[] = +{ + "accX", &get_accX, + "accY", &get_accY, + "accZ", &get_accZ, + "gyrX", &get_gyrX, + "gyrY", &get_gyrY, + "gyrZ", &get_gyrZ, + "heading", &get_oriHeading, + "pitch", &get_oriPitch, + "roll", &get_oriRoll, + "rotX", &get_rotX, + "rotY", &get_rotY, + "rotZ", &get_rotZ, + "rotW", &get_rotW, + "temperature", &get_temperature, + "barometer", &get_barrometric_pressure, + "humidity", &get_humidity, + "gas", &get_gas, +}; + +/** +* @brief Arduino setup function +*/ +void setup() +{ + /* Init serial */ + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Sensor Fusion Inference\r\n"); + + /* Connect used sensors */ + if(ei_connect_fusion_list(EI_CLASSIFIER_FUSION_AXES_STRING) == false) { + ei_printf("ERR: Errors in sensor list detected\r\n"); + return; + } + + /* Init & start sensors */ + BHY2.begin(NICLA_I2C); + accel.begin(); + gyro.begin(); + ori.begin(); + rotation.begin(); + temp.begin(); + baro.begin(); + hum.begin(); + gas.begin(); +} + +/** +* @brief Get data and run inferencing +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\r\n"); + + delay(2000); + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != fusion_ix) { + ei_printf("ERR: Nicla sensors don't match the sensors required in the model\r\n" + "Following sensors are required: %s\r\n", EI_CLASSIFIER_FUSION_AXES_STRING); + return; + } + + ei_printf("Sampling...\r\n"); + + // Allocate a buffer here for the values we'll read from the IMU + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME) { + // Determine the next tick (and then sleep later) + int64_t next_tick = (int64_t)micros() + ((int64_t)EI_CLASSIFIER_INTERVAL_MS * 1000); + + // Update function should be continuously polled + BHY2.update(); + + for(int i = 0; i < fusion_ix; i++) { + buffer[ix + i] = nicla_sensors[fusion_sensors[i]].get_value(); + } + + int64_t wait_time = next_tick - (int64_t)micros(); + + if(wait_time > 0) { + delayMicroseconds(wait_time); + } + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.):\r\n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf("%s: %.5f\r\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\r\n", result.anomaly); +#endif +} + +#if !defined(EI_CLASSIFIER_SENSOR) || (EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_FUSION && EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER) +#error "Invalid model for current sensor" +#endif + + +/** + * @brief Go through nicla sensor list to find matching axis name + * + * @param axis_name + * @return int8_t index in nicla sensor list, -1 if axis name is not found + */ +static int8_t ei_find_axis(char *axis_name) +{ + int ix; + for(ix = 0; ix < NICLA_N_SENSORS; ix++) { + if(strstr(axis_name, nicla_sensors[ix].name)) { + return ix; + } + } + return -1; +} + +/** + * @brief Check if requested input list is valid sensor fusion, create sensor buffer + * + * @param[in] input_list Axes list to sample (ie. "accX + gyrY + magZ") + * @retval false if invalid sensor_list + */ +static bool ei_connect_fusion_list(const char *input_list) +{ + char *buff; + bool is_fusion = false; + + /* Copy const string in heap mem */ + char *input_string = (char *)ei_malloc(strlen(input_list) + 1); + if (input_string == NULL) { + return false; + } + memset(input_string, 0, strlen(input_list) + 1); + strncpy(input_string, input_list, strlen(input_list)); + + /* Clear fusion sensor list */ + memset(fusion_sensors, 0, NICLA_N_SENSORS); + fusion_ix = 0; + + buff = strtok(input_string, "+"); + + while (buff != NULL) { /* Run through buffer */ + int8_t found_axis = 0; + + is_fusion = false; + found_axis = ei_find_axis(buff); + + if(found_axis >= 0) { + if(fusion_ix < NICLA_N_SENSORS) { + fusion_sensors[fusion_ix++] = found_axis; + } + is_fusion = true; + } + + buff = strtok(NULL, "+ "); + } + + ei_free(input_string); + + return is_fusion; +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_camera/nicla_vision_camera.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_camera/nicla_vision_camera.ino new file mode 100644 index 0000000..d0ba538 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_camera/nicla_vision_camera.ino @@ -0,0 +1,401 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include + +#include "edge-impulse-sdk/dsp/image/image.hpp" + +#include "camera.h" +#include "gc2145.h" +#include + +/* Constant defines -------------------------------------------------------- */ +#define EI_CAMERA_RAW_FRAME_BUFFER_COLS 320 +#define EI_CAMERA_RAW_FRAME_BUFFER_ROWS 240 +#define EI_CAMERA_RAW_FRAME_BYTE_SIZE 2 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +#define ALIGN_PTR(p,a) ((p & (a-1)) ?(((uintptr_t)p + a) & ~(uintptr_t)(a-1)) : p) + +/* Edge Impulse ------------------------------------------------------------- */ + +typedef struct { + size_t width; + size_t height; +} ei_device_resize_resolutions_t; + +/** + * @brief Check if new serial data is available + * + * @return Returns number of available bytes + */ +int ei_get_serial_available(void) { + return Serial.available(); +} + +/** + * @brief Get next available byte + * + * @return byte + */ +char ei_get_serial_byte(void) { + return Serial.read(); +} + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static bool is_initialised = false; +static bool is_ll_initialised = false; + +GC2145 galaxyCore; +Camera cam(galaxyCore); +FrameBuffer fb; + +/* +** @brief points to the output of the capture +*/ +static uint8_t *ei_camera_capture_out = NULL; + +/* +** @brief used to store the raw frame +*/ +static uint8_t *ei_camera_frame_mem; +static uint8_t *ei_camera_frame_buffer; // 32-byte aligned + +/* Function definitions ------------------------------------------------------- */ +bool ei_camera_init(void); +void ei_camera_deinit(void); +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) ; +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize); + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // initialise M4 RAM + // Arduino Nicla Vision has 512KB of RAM allocated for M7 core + // and additional 244k (sic!) on the M4 address space + // allocating 288 kB as in the line below was + // advised by a member of Arduino team + malloc_addblock((void*)0x30000000, 288 * 1024); + + if (ei_camera_init() == false) { + ei_printf("Failed to initialize Camera!\r\n"); + } + else { + ei_printf("Camera initialized\r\n"); + } +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\n"); + + // instead of wait_ms, we'll wait on the signal, this allows threads to cancel us... + if (ei_sleep(2000) != EI_IMPULSE_OK) { + return; + } + + ei_printf("Taking photo...\n"); + + ei::signal_t signal; + signal.total_length = EI_CLASSIFIER_INPUT_WIDTH * EI_CLASSIFIER_INPUT_HEIGHT; + signal.get_data = &ei_camera_get_data; + + if (ei_camera_capture((size_t)EI_CLASSIFIER_INPUT_WIDTH, (size_t)EI_CLASSIFIER_INPUT_HEIGHT, NULL) == false) { + ei_printf("Failed to capture image\r\n"); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.): \n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); +#if EI_CLASSIFIER_OBJECT_DETECTION == 1 + ei_printf("Object detection bounding boxes:\r\n"); + for (uint32_t i = 0; i < result.bounding_boxes_count; i++) { + ei_impulse_result_bounding_box_t bb = result.bounding_boxes[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } + + // Print the prediction results (classification) +#else + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } +#endif + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + ei_printf("Visual anomalies:\r\n"); + for (uint32_t i = 0; i < result.visual_ad_count; i++) { + ei_impulse_result_bounding_box_t bb = result.visual_ad_grid_cells[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } +#endif +} + +/** + * @brief Setup image sensor & start streaming + * + * @retval false if initialisation failed + */ +bool ei_camera_init(void) { + if (is_initialised) return true; + + if (is_ll_initialised == false) { + if (!cam.begin(CAMERA_R320x240, CAMERA_RGB565, -1)) { + ei_printf("ERR: Failed to initialise camera\r\n"); + return false; + } + + // initialize frame buffer + ei_camera_frame_mem = (uint8_t *) ei_malloc(EI_CAMERA_RAW_FRAME_BUFFER_COLS * EI_CAMERA_RAW_FRAME_BUFFER_ROWS * EI_CAMERA_RAW_FRAME_BYTE_SIZE + 32 /*alignment*/); + if(ei_camera_frame_mem == NULL) { + ei_printf("failed to create ei_camera_frame_mem\r\n"); + return false; + } + ei_camera_frame_buffer = (uint8_t *)ALIGN_PTR((uintptr_t)ei_camera_frame_mem, 32); + + fb.setBuffer(ei_camera_frame_buffer); + is_initialised = true; + } + + return true; +} + +/** + * @brief Stop streaming of sensor data + */ +void ei_camera_deinit(void) { + + ei_free(ei_camera_frame_mem); + ei_camera_frame_mem = NULL; + ei_camera_frame_buffer = NULL; + is_initialised = false; +} + +/** + * @brief Capture, rescale and crop image + * + * @param[in] img_width width of output image + * @param[in] img_height height of output image + * @param[in] out_buf pointer to store output image, NULL may be used + * if ei_camera_frame_buffer is to be used for capture and resize/cropping. + * + * @retval false if not initialised, image captured, rescaled or cropped failed + * + */ +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) { + bool do_resize = false; + bool do_crop = false; + + ei_camera_capture_out = (uint8_t*)ea_malloc(EI_CAMERA_RAW_FRAME_BUFFER_COLS * EI_CAMERA_RAW_FRAME_BUFFER_ROWS * 3 + 32); + ei_camera_capture_out = (uint8_t *)ALIGN_PTR((uintptr_t)ei_camera_capture_out, 32); + + if (!is_initialised) { + ei_printf("ERR: Camera is not initialized\r\n"); + return false; + } + + int snapshot_response = cam.grabFrame(fb, 100); + if (snapshot_response != 0) { + ei_printf("ERR: Failed to get snapshot (%d)\r\n", snapshot_response); + return false; + } + + bool converted = RBG565ToRGB888(ei_camera_frame_buffer, ei_camera_capture_out, cam.frameSize()); + + if(!converted){ + ei_printf("ERR: Conversion failed\n"); + ei_free(ei_camera_frame_mem); + return false; + } + + uint32_t resize_col_sz; + uint32_t resize_row_sz; + // choose resize dimensions + int res = calculate_resize_dimensions(img_width, img_height, &resize_col_sz, &resize_row_sz, &do_resize); + if (res) { + ei_printf("ERR: Failed to calculate resize dimensions (%d)\r\n", res); + return false; + } + + if ((img_width != resize_col_sz) + || (img_height != resize_row_sz)) { + do_crop = true; + } + + if (do_resize) { + + ei::image::processing::crop_and_interpolate_rgb888( + ei_camera_capture_out, + EI_CAMERA_RAW_FRAME_BUFFER_COLS, + EI_CAMERA_RAW_FRAME_BUFFER_ROWS, + ei_camera_capture_out, + resize_col_sz, + resize_row_sz); + } + + ea_free(ei_camera_capture_out); + return true; +} + +/** + * @brief Convert rgb565 data to rgb888 + * + * @param[in] src_buf The rgb565 data + * @param dst_buf The rgb888 data + * @param src_len length of rgb565 data + */ + +bool RBG565ToRGB888(uint8_t *src_buf, uint8_t *dst_buf, uint32_t src_len) +{ + uint8_t hb, lb; + uint32_t pix_count = src_len / 2; + + for(uint32_t i = 0; i < pix_count; i ++) { + hb = *src_buf++; + lb = *src_buf++; + + *dst_buf++ = hb & 0xF8; + *dst_buf++ = (hb & 0x07) << 5 | (lb & 0xE0) >> 3; + *dst_buf++ = (lb & 0x1F) << 3; + } + + return true; +} + +static int ei_camera_get_data(size_t offset, size_t length, float *out_ptr) +{ + // we already have a RGB888 buffer, so recalculate offset into pixel index + size_t pixel_ix = offset * 3; + size_t pixels_left = length; + size_t out_ptr_ix = 0; + + while (pixels_left != 0) { + out_ptr[out_ptr_ix] = (ei_camera_capture_out[pixel_ix] << 16) + (ei_camera_capture_out[pixel_ix + 1] << 8) + ei_camera_capture_out[pixel_ix + 2]; + + // go to the next pixel + out_ptr_ix++; + pixel_ix+=3; + pixels_left--; + } + + // and done! + return 0; +} + +/** + * @brief Determine whether to resize and to which dimension + * + * @param[in] out_width width of output image + * @param[in] out_height height of output image + * @param[out] resize_col_sz pointer to frame buffer's column/width value + * @param[out] resize_row_sz pointer to frame buffer's rows/height value + * @param[out] do_resize returns whether to resize (or not) + * + */ +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize) +{ + size_t list_size = 6; + const ei_device_resize_resolutions_t list[list_size] = { + {64, 64}, + {96, 96}, + {160, 120}, + {160, 160}, + {320, 240}, + }; + + // (default) conditions + *resize_col_sz = EI_CAMERA_RAW_FRAME_BUFFER_COLS; + *resize_row_sz = EI_CAMERA_RAW_FRAME_BUFFER_ROWS; + *do_resize = false; + + for (size_t ix = 0; ix < list_size; ix++) { + if ((out_width <= list[ix].width) && (out_height <= list[ix].height)) { + *resize_col_sz = list[ix].width; + *resize_row_sz = list[ix].height; + *do_resize = true; + break; + } + } + + return 0; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_CAMERA +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_fusion/nicla_vision_fusion.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_fusion/nicla_vision_fusion.ino new file mode 100644 index 0000000..23d02bb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_fusion/nicla_vision_fusion.ino @@ -0,0 +1,306 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: http://librarymanager/All#Arduino_LSM6DSOX +#include "VL53L1X.h" //Click here to get the library (VL53L1X from Pololu): http://librarymanager/All#VL53L1X + +/** Struct to link sensor axis name to sensor value function */ +typedef struct{ + const char *name; + float *value; + uint8_t (*poll_sensor)(void); + bool (*init_sensor)(void); + int8_t status; // -1 not used 0 used(unitialized) 1 used(initalized) 2 data sampled +} eiSensors; + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 2.0f // starting 03/2022, models are generated setting range to +-2, + // but this example use Arudino library which set range to +-4g. + // If you are using an older model, ignore this value and use 4.0f instead +/** Number sensor axes used */ +#define N_SENSORS 7 + +/* Forward declarations ------------------------------------------------------- */ +float ei_get_sign(float number); +static bool ei_connect_fusion_list(const char *input_list); + +bool init_IMU(void); +bool init_VL53L1X(void); +uint8_t poll_acc(void); +uint8_t poll_gyr(void); +uint8_t poll_mag(void); +uint8_t poll_VL53L1X(void); + +/* Private variables ------------------------------------------------------- */ +static const bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static float data[N_SENSORS]; +static int8_t fusion_sensors[N_SENSORS]; +static int fusion_ix = 0; + +VL53L1X proximity; + +/** Used sensors value function connected to label name */ +eiSensors sensors[] = +{ + "accX", &data[0], &poll_acc, &init_IMU, -1, + "accY", &data[1], &poll_acc, &init_IMU, -1, + "accZ", &data[2], &poll_acc, &init_IMU, -1, + "gyrX", &data[3], &poll_gyr, &init_IMU, -1, + "gyrY", &data[4], &poll_gyr, &init_IMU, -1, + "gyrZ", &data[5], &poll_gyr, &init_IMU, -1, + "proximity", &data[6], &poll_VL53L1X, &init_VL53L1X, -1, +}; + +/** +* @brief Arduino setup function +*/ +void setup() +{ + /* Init serial */ + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Sensor Fusion Inference\r\n"); + + /* Connect used sensors */ + if(ei_connect_fusion_list(EI_CLASSIFIER_FUSION_AXES_STRING) == false) { + ei_printf("ERR: Errors in sensor list detected\r\n"); + return; + } + + /* Init & start sensors */ + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == 0) { + sensors[fusion_sensors[i]].status = sensors[fusion_sensors[i]].init_sensor(); + if (!sensors[fusion_sensors[i]].status) { + ei_printf("%s axis sensor initialization failed.\r\n", sensors[fusion_sensors[i]].name); + } + else { + ei_printf("%s axis sensor initialization successful.\r\n", sensors[fusion_sensors[i]].name); + } + } + } +} + +/** +* @brief Get data and run inferencing +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\r\n"); + + delay(2000); + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != fusion_ix) { + ei_printf("ERR: Sensors don't match the sensors required in the model\r\n" + "Following sensors are required: %s\r\n", EI_CLASSIFIER_FUSION_AXES_STRING); + return; + } + + ei_printf("Sampling...\r\n"); + + // Allocate a buffer here for the values we'll read from the sensor + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME) { + // Determine the next tick (and then sleep later) + int64_t next_tick = (int64_t)micros() + ((int64_t)EI_CLASSIFIER_INTERVAL_MS * 1000); + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == 1) { + sensors[fusion_sensors[i]].poll_sensor(); + sensors[fusion_sensors[i]].status = 2; + } + if (sensors[fusion_sensors[i]].status == 2) { + buffer[ix + i] = *sensors[fusion_sensors[i]].value; + //ei_printf("%d %f\n", fusion_sensors[i], buffer[ix + i]); + sensors[fusion_sensors[i]].status = 1; + } + } + + int64_t wait_time = next_tick - (int64_t)micros(); + + if(wait_time > 0) { + delayMicroseconds(wait_time); + } + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.):\r\n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf("%s: %.5f\r\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\r\n", result.anomaly); +#endif +} + +#if !defined(EI_CLASSIFIER_SENSOR) || (EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_FUSION && EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER) +#error "Invalid model for current sensor" +#endif + + +/** + * @brief Go through sensor list to find matching axis name + * + * @param axis_name + * @return int8_t index in sensor list, -1 if axis name is not found + */ +static int8_t ei_find_axis(char *axis_name) +{ + int ix; + for(ix = 0; ix < N_SENSORS; ix++) { + if(strstr(axis_name, sensors[ix].name)) { + return ix; + } + } + return -1; +} + +/** + * @brief Check if requested input list is valid sensor fusion, create sensor buffer + * + * @param[in] input_list Axes list to sample (ie. "accX + gyrY + magZ") + * @retval false if invalid sensor_list + */ +static bool ei_connect_fusion_list(const char *input_list) +{ + char *buff; + bool is_fusion = false; + + /* Copy const string in heap mem */ + char *input_string = (char *)ei_malloc(strlen(input_list) + 1); + if (input_string == NULL) { + return false; + } + memset(input_string, 0, strlen(input_list) + 1); + strncpy(input_string, input_list, strlen(input_list)); + + /* Clear fusion sensor list */ + memset(fusion_sensors, 0, N_SENSORS); + fusion_ix = 0; + + buff = strtok(input_string, "+"); + + while (buff != NULL) { /* Run through buffer */ + int8_t found_axis = 0; + + is_fusion = false; + found_axis = ei_find_axis(buff); + + if(found_axis >= 0) { + if(fusion_ix < N_SENSORS) { + fusion_sensors[fusion_ix++] = found_axis; + sensors[found_axis].status = 0; + } + is_fusion = true; + } + + buff = strtok(NULL, "+ "); + } + + ei_free(input_string); + + return is_fusion; +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +bool init_IMU(void) { + static bool init_status = false; + if (!init_status) { + init_status = IMU.begin(); + } + return init_status; +} + +bool init_VL53L1X(void) { + static bool init_status = false; + if (!init_status) { + Wire1.begin(); + Wire1.setClock(400000); // use 400 kHz I2C + proximity.setBus(&Wire1); + init_status = proximity.init(); + proximity.setDistanceMode(VL53L1X::Long); + proximity.setMeasurementTimingBudget(10000); + proximity.startContinuous(10); + } + return init_status; +} + +uint8_t poll_acc(void) { + + if (IMU.accelerationAvailable()) { + + IMU.readAcceleration(data[0], data[1], data[2]); + + for (int i = 0; i < 3; i++) { + if (fabs(data[i]) > MAX_ACCEPTED_RANGE) { + data[i] = ei_get_sign(data[i]) * MAX_ACCEPTED_RANGE; + } + } + + data[0] *= CONVERT_G_TO_MS2; + data[1] *= CONVERT_G_TO_MS2; + data[2] *= CONVERT_G_TO_MS2; + } + + return 0; +} + +uint8_t poll_gyr(void) { + + if (IMU.gyroscopeAvailable()) { + IMU.readGyroscope(data[3], data[4], data[5]); + } + return 0; +} + + +uint8_t poll_VL53L1X(void) { + data[6] = proximity.read(); + return 0; +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_microphone/nicla_vision_microphone.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_microphone/nicla_vision_microphone.ino new file mode 100644 index 0000000..2b2b7d3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_microphone/nicla_vision_microphone.ino @@ -0,0 +1,231 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + int16_t *buffer; + uint8_t buf_ready; + uint32_t buf_count; + uint32_t n_samples; +} inference_t; + +static inference_t inference; +static signed short sampleBuffer[2048]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static volatile bool record_ready = false; + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + if (microphone_inference_start(EI_CLASSIFIER_RAW_SAMPLE_COUNT) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + ei_printf("Starting inferencing in 2 seconds...\n"); + + delay(2000); + + ei_printf("Recording...\n"); + + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + ei_printf("Recording done\n"); + + signal_t signal; + signal.total_length = EI_CLASSIFIER_RAW_SAMPLE_COUNT; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR r = run_classifier(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: ", result.classification[ix].label); + ei_printf_float(result.classification[ix].value); + ei_printf("\n"); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: "); + ei_printf_float(result.anomaly); + ei_printf("\n"); +#endif +} + +/** + * @brief PDM buffer full callback + * Copy audio data to app buffers + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if ((inference.buf_ready == 0) && (record_ready == true)) { + + for(int i = 0; i < bytesRead>>1; i++) { + inference.buffer[inference.buf_count++] = sampleBuffer[i]; + + if(inference.buf_count >= inference.n_samples) { + inference.buf_count = 0; + inference.buf_ready = 1; + break; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffer = (int16_t *)malloc(n_samples * sizeof(int16_t)); + + if(inference.buffer == NULL) { + return false; + } + + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(pdm_data_ready_inference_callback); + + PDM.setBufferSize(2048); + delay(250); + + // initialize PDM with: + // - one channel (mono mode) + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("ERR: Failed to start PDM!"); + microphone_inference_end(); + return false; + } + + // optionally set the gain, defaults to 24 + // Note: values >=52 not supported + //PDM.setGain(40); + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + record_ready = true; + while (inference.buf_ready == 0) { + delay(10); + } + + inference.buf_ready = 0; + record_ready = false; + + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffer[offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + ei_free(inference.buffer); +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_microphone_continuous/nicla_vision_microphone_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_microphone_continuous/nicla_vision_microphone_continuous.ino new file mode 100644 index 0000000..ee51cda --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/nicla_vision/nicla_vision_microphone_continuous/nicla_vision_microphone_continuous.ino @@ -0,0 +1,249 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + signed short *buffers[2]; + unsigned char buf_select; + unsigned char buf_ready; + unsigned int buf_count; + unsigned int n_samples; +} inference_t; + +static inference_t inference; +static volatile bool record_ready = false; +// static signed short *sampleBuffer; +static signed short sampleBuffer[2048]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static int print_results = -(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW); + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / + sizeof(ei_classifier_inferencing_categories[0])); + + run_classifier_init(); + if (microphone_inference_start(EI_CLASSIFIER_SLICE_SIZE) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + signal_t signal; + signal.total_length = EI_CLASSIFIER_SLICE_SIZE; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = {0}; + + EI_IMPULSE_ERROR r = run_classifier_continuous(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + if (++print_results >= (EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)) { + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: ", result.classification[ix].label); + ei_printf_float(result.classification[ix].value); + ei_printf("\n"); + + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: "); + ei_printf_float(result.anomaly); + ei_printf("\n"); +#endif + + print_results = 0; + } +} + +/** + * @brief PDM buffer full callback + * Copy audio data to app buffers + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if ((inference.buf_ready == 0) && (record_ready == true)) { + for(int i = 0; i < bytesRead>>1; i++) { + inference.buffers[inference.buf_select][inference.buf_count++] = sampleBuffer[i]; + + if (inference.buf_count >= inference.n_samples) { + inference.buf_select ^= 1; + inference.buf_count = 0; + inference.buf_ready = 1; + break; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffers[0] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[0] == NULL) { + return false; + } + + inference.buffers[1] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[1] == NULL) { + ei_free(inference.buffers[0]); + return false; + } + + inference.buf_select = 0; + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(&pdm_data_ready_inference_callback); + + PDM.setBufferSize(2048); + delay(250); + + // initialize PDM with: + // - one channel (mono mode) + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("ERR: Failed to start PDM!"); + return false; + } + + // optionally set the gain, defaults to 24 + // Note: values >=52 not supported + //PDM.setGain(40); + + record_ready = true; + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + if (inference.buf_ready == 1) { + ei_printf( + "Error sample buffer overrun. Decrease the number of slices per model window " + "(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)\n"); + ret = false; + } + + while (inference.buf_ready == 0) { + delay(1); + } + + inference.buf_ready = 0; + + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffers[inference.buf_select ^ 1][offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + ei_free(inference.buffers[0]); + ei_free(inference.buffers[1]); + record_ready = false; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_camera/portenta_h7_camera.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_camera/portenta_h7_camera.ino new file mode 100644 index 0000000..a3b0bb7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_camera/portenta_h7_camera.ino @@ -0,0 +1,459 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include "camera.h" +#include "himax.h" +#include "edge-impulse-sdk/dsp/image/image.hpp" + +/* Constant defines -------------------------------------------------------- */ +#define EI_CAMERA_RAW_FRAME_BUFFER_COLS 320 +#define EI_CAMERA_RAW_FRAME_BUFFER_ROWS 240 + +// frame buffer allocation options: +// - static (default if none below is chosen) +// - heap or +// - SDRAM +#define EI_CAMERA_FRAME_BUFFER_SDRAM +//#define EI_CAMERA_FRAME_BUFFER_HEAP + +#ifdef EI_CAMERA_FRAME_BUFFER_SDRAM +#include "SDRAM.h" +#endif + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +#define ALIGN_PTR(p,a) ((p & (a-1)) ?(((uintptr_t)p + a) & ~(uintptr_t)(a-1)) : p) + +/* Edge Impulse ------------------------------------------------------------- */ + +typedef struct { + size_t width; + size_t height; +} ei_device_resize_resolutions_t; + +/** + * @brief Check if new serial data is available + * + * @return Returns number of available bytes + */ +int ei_get_serial_available(void) { + return Serial.available(); +} + +/** + * @brief Get next available byte + * + * @return byte + */ +char ei_get_serial_byte(void) { + return Serial.read(); +} + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static bool is_initialised = false; +static bool is_ll_initialised = false; +HM01B0 himax; +static Camera cam(himax); +FrameBuffer fb; + + +/* +** @brief points to the output of the capture +*/ +static uint8_t *ei_camera_capture_out = NULL; + +/* +** @brief used to store the raw frame +*/ +#if defined(EI_CAMERA_FRAME_BUFFER_SDRAM) || defined(EI_CAMERA_FRAME_BUFFER_HEAP) +static uint8_t *ei_camera_frame_mem; +static uint8_t *ei_camera_frame_buffer; // 32-byte aligned +#else +static uint8_t ei_camera_frame_buffer[EI_CAMERA_RAW_FRAME_BUFFER_COLS * EI_CAMERA_RAW_FRAME_BUFFER_ROWS] __attribute__((aligned(32))); +#endif + +/* Function definitions ------------------------------------------------------- */ +bool ei_camera_init(void); +void ei_camera_deinit(void); +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) ; +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize); + + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + +#ifdef EI_CAMERA_FRAME_BUFFER_SDRAM + // initialise the SDRAM + SDRAM.begin(SDRAM_START_ADDRESS); +#endif + + if (ei_camera_init() == false) { + ei_printf("Failed to initialize Camera!\r\n"); + } + else { + ei_printf("Camera initialized\r\n"); + } + + for (size_t ix = 0; ix < ei_dsp_blocks_size; ix++) { + ei_model_dsp_t block = ei_dsp_blocks[ix]; + if (block.extract_fn == &extract_image_features) { + ei_dsp_config_image_t config = *((ei_dsp_config_image_t*)block.config); + int16_t channel_count = strcmp(config.channels, "Grayscale") == 0 ? 1 : 3; + if (channel_count == 3) { + ei_printf("WARN: You've deployed a color model, but the Arduino Portenta H7 only has a monochrome image sensor. Set your DSP block to 'Grayscale' for best performance.\r\n"); + break; // only print this once + } + } + } +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\n"); + + // instead of wait_ms, we'll wait on the signal, this allows threads to cancel us... + if (ei_sleep(2000) != EI_IMPULSE_OK) { + return; + } + + ei_printf("Taking photo...\n"); + + ei::signal_t signal; + signal.total_length = EI_CLASSIFIER_INPUT_WIDTH * EI_CLASSIFIER_INPUT_HEIGHT; + signal.get_data = &ei_camera_cutout_get_data; + + if (ei_camera_capture((size_t)EI_CLASSIFIER_INPUT_WIDTH, (size_t)EI_CLASSIFIER_INPUT_HEIGHT, NULL) == false) { + ei_printf("Failed to capture image\r\n"); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.): \n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); +#if EI_CLASSIFIER_OBJECT_DETECTION == 1 + ei_printf("Object detection bounding boxes:\r\n"); + for (uint32_t i = 0; i < result.bounding_boxes_count; i++) { + ei_impulse_result_bounding_box_t bb = result.bounding_boxes[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } + + // Print the prediction results (classification) +#else + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } +#endif + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + ei_printf("Visual anomalies:\r\n"); + for (uint32_t i = 0; i < result.visual_ad_count; i++) { + ei_impulse_result_bounding_box_t bb = result.visual_ad_grid_cells[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } +#endif +} + +/** + * @brief Setup image sensor & start streaming + * + * @retval false if initialisation failed + */ +bool ei_camera_init(void) { + if (is_initialised) return true; + + if (is_ll_initialised == false) { + if (!cam.begin(CAMERA_R320x240, CAMERA_GRAYSCALE, 30)) { + ei_printf("ERR: Failed to initialise camera\r\n"); + return false; + } + + #ifdef EI_CAMERA_FRAME_BUFFER_SDRAM + ei_camera_frame_mem = (uint8_t *) SDRAM.malloc(EI_CAMERA_RAW_FRAME_BUFFER_COLS * EI_CAMERA_RAW_FRAME_BUFFER_ROWS + 32 /*alignment*/); + if(ei_camera_frame_mem == NULL) { + ei_printf("failed to create ei_camera_frame_mem\r\n"); + return false; + } + ei_camera_frame_buffer = (uint8_t *)ALIGN_PTR((uintptr_t)ei_camera_frame_mem, 32); + #endif + + is_ll_initialised = true; + } + + // initialize frame buffer +#if defined(EI_CAMERA_FRAME_BUFFER_HEAP) + ei_camera_frame_mem = (uint8_t *) ei_malloc(EI_CAMERA_RAW_FRAME_BUFFER_COLS * EI_CAMERA_RAW_FRAME_BUFFER_ROWS + 32 /*alignment*/); + if(ei_camera_frame_mem == NULL) { + ei_printf("failed to create ei_camera_frame_mem\r\n"); + return false; + } + ei_camera_frame_buffer = (uint8_t *)ALIGN_PTR((uintptr_t)ei_camera_frame_mem, 32); +#endif + + fb.setBuffer(ei_camera_frame_buffer); + is_initialised = true; + + return true; +} + +/** + * @brief Stop streaming of sensor data + */ +void ei_camera_deinit(void) { + +#if defined(EI_CAMERA_FRAME_BUFFER_HEAP) + ei_free(ei_camera_frame_mem); + ei_camera_frame_mem = NULL; + ei_camera_frame_buffer = NULL; +#endif + + is_initialised = false; +} + +/** + * @brief Capture, rescale and crop image + * + * @param[in] img_width width of output image + * @param[in] img_height height of output image + * @param[in] out_buf pointer to store output image, NULL may be used + * if ei_camera_frame_buffer is to be used for capture and resize/cropping. + * + * @retval false if not initialised, image captured, rescaled or cropped failed + * + */ +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) { + bool do_resize = false; + bool do_crop = false; + + if (!is_initialised) { + ei_printf("ERR: Camera is not initialized\r\n"); + return false; + } + + int snapshot_response = cam.grabFrame(fb, 3000); + if (snapshot_response != 0) { + ei_printf("ERR: Failed to get snapshot (%d)\r\n", snapshot_response); + return false; + } + + uint32_t resize_col_sz; + uint32_t resize_row_sz; + // choose resize dimensions + int res = calculate_resize_dimensions(img_width, img_height, &resize_col_sz, &resize_row_sz, &do_resize); + if (res) { + ei_printf("ERR: Failed to calculate resize dimensions (%d)\r\n", res); + return false; + } + + if ((img_width != resize_col_sz) + || (img_height != resize_row_sz)) { + do_crop = true; + } + + // The following variables should always be assigned + // if this routine is to return true + // cutout values + ei_camera_capture_out = ei_camera_frame_buffer; + + if (do_resize) { + + // if only resizing then and out_buf provided then use itinstead. + if (out_buf && !do_crop) ei_camera_capture_out = out_buf; + + //ei_printf("resize cols: %d, rows: %d\r\n", resize_col_sz,resize_row_sz); + ei::image::processing::resize_image( + ei_camera_frame_buffer, + EI_CAMERA_RAW_FRAME_BUFFER_COLS, + EI_CAMERA_RAW_FRAME_BUFFER_ROWS, + ei_camera_capture_out, + resize_col_sz, + resize_row_sz, + 1); // bytes per pixel + } + + if (do_crop) { + uint32_t crop_col_sz; + uint32_t crop_row_sz; + uint32_t crop_col_start; + uint32_t crop_row_start; + crop_row_start = (resize_row_sz - img_height) / 2; + crop_col_start = (resize_col_sz - img_width) / 2; + crop_col_sz = img_width; + crop_row_sz = img_height; + + // if (also) cropping and out_buf provided then use it instead. + if (out_buf) ei_camera_capture_out = out_buf; + + //ei_printf("crop cols: %d, rows: %d\r\n", crop_col_sz,crop_row_sz); + ei::image::processing::cropImage( + ei_camera_frame_buffer, + resize_col_sz, + resize_row_sz, + crop_col_start, + crop_row_start, + ei_camera_capture_out, + crop_col_sz, + crop_row_sz, + 8); // bits per pixel + } + + return true; +} + +/** + * @brief Convert monochrome data to rgb values + * + * @param[in] mono_data The mono data + * @param r red pixel value + * @param g green pixel value + * @param b blue pixel value + */ +static inline void mono_to_rgb(uint8_t mono_data, uint8_t *r, uint8_t *g, uint8_t *b) { + uint8_t v = mono_data; + *r = *g = *b = v; +} + + +int ei_camera_cutout_get_data(size_t offset, size_t length, float *out_ptr) { + size_t bytes_left = length; + size_t out_ptr_ix = 0; + + // read byte for byte + while (bytes_left != 0) { + + // grab the value and convert to r/g/b + uint8_t pixel = ei_camera_capture_out[offset]; + + uint8_t r, g, b; + mono_to_rgb(pixel, &r, &g, &b); + + // then convert to out_ptr format + float pixel_f = (r << 16) + (g << 8) + b; + out_ptr[out_ptr_ix] = pixel_f; + + // and go to the next pixel + out_ptr_ix++; + offset++; + bytes_left--; + } + + // and done! + return 0; +} + +/** + * @brief Determine whether to resize and to which dimension + * + * @param[in] out_width width of output image + * @param[in] out_height height of output image + * @param[out] resize_col_sz pointer to frame buffer's column/width value + * @param[out] resize_row_sz pointer to frame buffer's rows/height value + * @param[out] do_resize returns whether to resize (or not) + * + */ +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize) +{ + size_t list_size = 6; + const ei_device_resize_resolutions_t list[list_size] = { + {128, 96}, + {160, 120}, + {200, 150}, + {256, 192}, + {320, 240}, + }; + + // (default) conditions + *resize_col_sz = EI_CAMERA_RAW_FRAME_BUFFER_COLS; + *resize_row_sz = EI_CAMERA_RAW_FRAME_BUFFER_ROWS; + *do_resize = false; + + for (size_t ix = 0; ix < list_size; ix++) { + if ((out_width <= list[ix].width) && (out_height <= list[ix].height)) { + *resize_col_sz = list[ix].width; + *resize_row_sz = list[ix].height; + *do_resize = true; + break; + } + } + + return 0; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_CAMERA +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_microphone/portenta_h7_microphone.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_microphone/portenta_h7_microphone.ino new file mode 100644 index 0000000..49bea2a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_microphone/portenta_h7_microphone.ino @@ -0,0 +1,230 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + int16_t *buffer; + uint8_t buf_ready; + uint32_t buf_count; + uint32_t n_samples; +} inference_t; + +static inference_t inference; +static signed short sampleBuffer[2048]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static volatile bool record_ready = false; + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + if (microphone_inference_start(EI_CLASSIFIER_RAW_SAMPLE_COUNT) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + ei_printf("Starting inferencing in 2 seconds...\n"); + + delay(2000); + + ei_printf("Recording...\n"); + + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + ei_printf("Recording done\n"); + + signal_t signal; + signal.total_length = EI_CLASSIFIER_RAW_SAMPLE_COUNT; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR r = run_classifier(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: ", result.classification[ix].label); + ei_printf_float(result.classification[ix].value); + ei_printf("\n"); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: "); + ei_printf_float(result.anomaly); + ei_printf("\n"); +#endif +} + +/** + * @brief PDM buffer full callback + * Copy audio data to app buffers + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if ((inference.buf_ready == 0) && (record_ready == true)) { + for(int i = 0; i < bytesRead>>1; i++) { + inference.buffer[inference.buf_count++] = sampleBuffer[i]; + + if(inference.buf_count >= inference.n_samples) { + inference.buf_count = 0; + inference.buf_ready = 1; + break; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffer = (int16_t *)malloc(n_samples * sizeof(int16_t)); + + if(inference.buffer == NULL) { + return false; + } + + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(&pdm_data_ready_inference_callback); + + // optionally set the gain, defaults to 24 + // Note: values >=52 not supported + //PDM.setGain(40); + + PDM.setBufferSize(2048); + + // initialize PDM with: + // - one channel (mono mode) + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("ERR: Failed to start PDM!"); + microphone_inference_end(); + return false; + } + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + + record_ready = true; + while (inference.buf_ready == 0) { + delay(10); + } + + inference.buf_ready = 0; + record_ready = false; + + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffer[offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + ei_free(inference.buffer); +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_microphone_continuous/portenta_h7_microphone_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_microphone_continuous/portenta_h7_microphone_continuous.ino new file mode 100644 index 0000000..9b9be28 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/portenta_h7/portenta_h7_microphone_continuous/portenta_h7_microphone_continuous.ino @@ -0,0 +1,257 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + signed short *buffers[2]; + unsigned char buf_select; + unsigned char buf_ready; + unsigned int buf_count; + unsigned int n_samples; +} inference_t; + +static inference_t inference; +static volatile bool record_ready = false; +// static signed short *sampleBuffer; +static signed short sampleBuffer[2048]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static int print_results = -(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW); + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / + sizeof(ei_classifier_inferencing_categories[0])); + + run_classifier_init(); + if (microphone_inference_start(EI_CLASSIFIER_SLICE_SIZE) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + signal_t signal; + signal.total_length = EI_CLASSIFIER_SLICE_SIZE; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = {0}; + + EI_IMPULSE_ERROR r = run_classifier_continuous(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + if (++print_results >= (EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)) { + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: ", result.classification[ix].label); + ei_printf_float(result.classification[ix].value); + ei_printf("\n"); + + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: "); + ei_printf_float(result.anomaly); + ei_printf("\n"); +#endif + + print_results = 0; + } +} + +/** + * @brief PDM buffer full callback + * Copy audio data to app buffers + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if ((inference.buf_ready == 0) && (record_ready == true)) { + for(int i = 0; i < bytesRead>>1; i++) { + inference.buffers[inference.buf_select][inference.buf_count++] = sampleBuffer[i]; + + if (inference.buf_count >= inference.n_samples) { + inference.buf_select ^= 1; + inference.buf_count = 0; + inference.buf_ready = 1; + break; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffers[0] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[0] == NULL) { + return false; + } + + inference.buffers[1] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[1] == NULL) { + ei_free(inference.buffers[0]); + return false; + } + + // sampleBuffer = (signed short *)malloc((n_samples >> 1) * sizeof(signed short)); + + // if (sampleBuffer == NULL) { + // ei_free(inference.buffers[0]); + // ei_free(inference.buffers[1]); + // return false; + // } + + inference.buf_select = 0; + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(&pdm_data_ready_inference_callback); + + // optionally set the gain, defaults to 24 + // Note: values >=52 not supported + //PDM.setGain(40); + + PDM.setBufferSize(2048); + + // initialize PDM with: + // - one channel (mono mode) + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("ERR: Failed to start PDM!"); + return false; + } + + record_ready = true; + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + if (inference.buf_ready == 1) { + ei_printf( + "Error sample buffer overrun. Decrease the number of slices per model window " + "(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)\n"); + ret = false; + } + + while (inference.buf_ready == 0) { + delay(1); + } + + inference.buf_ready = 0; + + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffers[inference.buf_select ^ 1][offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + ei_free(inference.buffers[0]); + ei_free(inference.buffers[1]); + // ei_free(sampleBuffer); + record_ready = false; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_fusion/rp2040_fusion.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_fusion/rp2040_fusion.ino new file mode 100644 index 0000000..38bf7ac --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_fusion/rp2040_fusion.ino @@ -0,0 +1,309 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include //Click here to get the library: http://librarymanager/All#Arduino_LSM6DSOX + +enum sensor_status { + NOT_USED = -1, + NOT_INIT, + INIT, + SAMPLED +}; + +/** Struct to link sensor axis name to sensor value function */ +typedef struct{ + const char *name; + float *value; + uint8_t (*poll_sensor)(void); + bool (*init_sensor)(void); + int8_t status; // -1 not used 0 used(unitialized) 1 used(initalized) 2 data sampled +} eiSensors; + +/* Constant defines -------------------------------------------------------- */ +#define CONVERT_G_TO_MS2 9.80665f +#define MAX_ACCEPTED_RANGE 4.0f // starting 03/2022, models are generated setting range to +-2, + // but this example use Arudino library which set range to +-4g. + // If you are using an older model, ignore this value and use 4.0f instead +/** Number sensor axes used */ +#define N_SENSORS 7 + +/* Forward declarations ------------------------------------------------------- */ +float ei_get_sign(float number); +static bool ei_connect_fusion_list(const char *input_list); + +bool init_IMU(void); +uint8_t poll_acc(void); +uint8_t poll_gyr(void); +uint8_t poll_mag(void); +uint8_t poll_temp(void); + +/* Private variables ------------------------------------------------------- */ +static const bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static float data[N_SENSORS]; +static int8_t fusion_sensors[N_SENSORS]; +static int fusion_ix = 0; + +/** Used sensors value function connected to label name */ +eiSensors sensors[] = +{ + "accX", &data[0], &poll_acc, &init_IMU, NOT_USED, + "accY", &data[1], &poll_acc, &init_IMU, NOT_USED, + "accZ", &data[2], &poll_acc, &init_IMU, NOT_USED, + "gyrX", &data[3], &poll_gyr, &init_IMU, NOT_USED, + "gyrY", &data[4], &poll_gyr, &init_IMU, NOT_USED, + "gyrZ", &data[5], &poll_gyr, &init_IMU, NOT_USED, + "temperature", &data[6], &poll_temp, &init_IMU, NOT_USED, +}; + +/** +* @brief Arduino setup function +*/ +void setup() +{ + /* Init serial */ + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Sensor Fusion Inference\r\n"); + + /* Connect used sensors */ + if(ei_connect_fusion_list(EI_CLASSIFIER_FUSION_AXES_STRING) == false) { + ei_printf("ERR: Errors in sensor list detected\r\n"); + return; + } + + /* Init & start sensors */ + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == NOT_INIT) { + sensors[fusion_sensors[i]].status = (sensor_status)sensors[fusion_sensors[i]].init_sensor(); + if (!sensors[fusion_sensors[i]].status) { + ei_printf("%s axis sensor initialization failed.\r\n", sensors[fusion_sensors[i]].name); + } + else { + ei_printf("%s axis sensor initialization successful.\r\n", sensors[fusion_sensors[i]].name); + } + } + } +} + +/** +* @brief Get data and run inferencing +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\r\n"); + + delay(2000); + + if (EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME != fusion_ix) { + ei_printf("ERR: Sensors don't match the sensors required in the model\r\n" + "Following sensors are required: %s\r\n", EI_CLASSIFIER_FUSION_AXES_STRING); + return; + } + + ei_printf("Sampling...\r\n"); + + // Allocate a buffer here for the values we'll read from the sensor + float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = { 0 }; + + for (size_t ix = 0; ix < EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE; ix += EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME) { + // Determine the next tick (and then sleep later) + int64_t next_tick = (int64_t)micros() + ((int64_t)EI_CLASSIFIER_INTERVAL_MS * 1000); + + for(int i = 0; i < fusion_ix; i++) { + if (sensors[fusion_sensors[i]].status == INIT) { + sensors[fusion_sensors[i]].poll_sensor(); + sensors[fusion_sensors[i]].status = SAMPLED; + } + if (sensors[fusion_sensors[i]].status == SAMPLED) { + buffer[ix + i] = *sensors[fusion_sensors[i]].value; + sensors[fusion_sensors[i]].status = INIT; + } + } + + int64_t wait_time = next_tick - (int64_t)micros(); + + if(wait_time > 0) { + delayMicroseconds(wait_time); + } + } + + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR:(%d)\r\n", err); + return; + } + print_inference_result(result); +} + +/** + * @brief Go through sensor list to find matching axis name + * + * @param axis_name + * @return int8_t index in sensor list, -1 if axis name is not found + */ +static int8_t ei_find_axis(char *axis_name) +{ + int ix; + for(ix = 0; ix < N_SENSORS; ix++) { + if(strstr(axis_name, sensors[ix].name)) { + return ix; + } + } + return -1; +} + +/** + * @brief Check if requested input list is valid sensor fusion, create sensor buffer + * + * @param[in] input_list Axes list to sample (ie. "accX + gyrY + magZ") + * @retval false if invalid sensor_list + */ +static bool ei_connect_fusion_list(const char *input_list) +{ + char *buff; + bool is_fusion = false; + + /* Copy const string in heap mem */ + char *input_string = (char *)ei_malloc(strlen(input_list) + 1); + if (input_string == NULL) { + return false; + } + memset(input_string, 0, strlen(input_list) + 1); + strncpy(input_string, input_list, strlen(input_list)); + + /* Clear fusion sensor list */ + memset(fusion_sensors, 0, N_SENSORS); + fusion_ix = 0; + + buff = strtok(input_string, "+"); + + while (buff != NULL) { /* Run through buffer */ + int8_t found_axis = 0; + + is_fusion = false; + found_axis = ei_find_axis(buff); + + if(found_axis >= 0) { + if(fusion_ix < N_SENSORS) { + fusion_sensors[fusion_ix++] = found_axis; + sensors[found_axis].status = NOT_INIT; + } + is_fusion = true; + } + + buff = strtok(NULL, "+ "); + } + + ei_free(input_string); + + return is_fusion; +} + +/** + * @brief Return the sign of the number + * + * @param number + * @return int 1 if positive (or 0) -1 if negative + */ +float ei_get_sign(float number) { + return (number >= 0.0) ? 1.0 : -1.0; +} + +bool init_IMU(void) { + static bool init_status = false; + if (!init_status) { + init_status = IMU.begin(); + } + return init_status; +} + +uint8_t poll_acc(void) { + + if (IMU.accelerationAvailable()) { + + IMU.readAcceleration(data[0], data[1], data[2]); + + for (int i = 0; i < 3; i++) { + if (fabs(data[i]) > MAX_ACCEPTED_RANGE) { + data[i] = ei_get_sign(data[i]) * MAX_ACCEPTED_RANGE; + } + } + + data[0] *= CONVERT_G_TO_MS2; + data[1] *= CONVERT_G_TO_MS2; + data[2] *= CONVERT_G_TO_MS2; + } + + return 0; +} + +uint8_t poll_gyr(void) { + + if (IMU.gyroscopeAvailable()) { + IMU.readGyroscope(data[3], data[4], data[5]); + } + return 0; +} + +uint8_t poll_temp(void) { + + if (IMU.temperatureAvailable()) { + int temp; + IMU.readTemperature(temp); + data[6] = temp; + } + return 0; +} + +void print_inference_result(ei_impulse_result_t result) { + + // Print how long it took to perform inference + ei_printf("Timing: DSP %d ms, inference %d ms, anomaly %d ms\r\n", + result.timing.dsp, + result.timing.classification, + result.timing.anomaly); + + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +} + +#if !defined(EI_CLASSIFIER_SENSOR) || (EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_FUSION && EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_ACCELEROMETER) +#error "Invalid model for current sensor" +#endif \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_microphone/rp2040_microphone.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_microphone/rp2040_microphone.ino new file mode 100644 index 0000000..ec1aba5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_microphone/rp2040_microphone.ino @@ -0,0 +1,240 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + int16_t *buffer; + uint8_t buf_ready; + uint32_t buf_count; + uint32_t n_samples; +} inference_t; + +static inference_t inference; +static signed short sampleBuffer[2048]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static volatile bool record_ready = false; + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + if (microphone_inference_start(EI_CLASSIFIER_RAW_SAMPLE_COUNT) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + ei_printf("Starting inferencing in 2 seconds...\n"); + + delay(2000); + + ei_printf("Recording...\n"); + + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + ei_printf("Recording done\n"); + + signal_t signal; + signal.total_length = EI_CLASSIFIER_RAW_SAMPLE_COUNT; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR res = run_classifier_continuous(&signal, &result, debug_nn); + if (res != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", res); + return; + } + + // print inference return code + ei_printf("run_classifier returned: %d\r\n", res); + print_inference_result(result); +} + +/** + * @brief PDM buffer full callback + * Copy audio data to app buffers + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if ((inference.buf_ready == 0) && (record_ready == true)) { + + for(int i = 0; i < bytesRead>>1; i++) { + inference.buffer[inference.buf_count++] = sampleBuffer[i]; + + if(inference.buf_count >= inference.n_samples) { + inference.buf_count = 0; + inference.buf_ready = 1; + break; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffer = (int16_t *)malloc(n_samples * sizeof(int16_t)); + + if(inference.buffer == NULL) { + return false; + } + + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(pdm_data_ready_inference_callback); + + PDM.setBufferSize(2048); + delay(250); + + // initialize PDM with: + // - one channel (mono mode) + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("ERR: Failed to start PDM!"); + microphone_inference_end(); + return false; + } + + // optionally set the gain, defaults to 24 + // Note: values >=52 not supported + //PDM.setGain(40); + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + record_ready = true; + while (inference.buf_ready == 0) { + delay(10); + } + + inference.buf_ready = 0; + record_ready = false; + + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffer[offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + ei_free(inference.buffer); +} + +void print_inference_result(ei_impulse_result_t result) { + + // Print how long it took to perform inference + ei_printf("Timing: DSP %d ms, inference %d ms, anomaly %d ms\r\n", + result.timing.dsp, + result.timing.classification, + result.timing.anomaly); + + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_microphone_continuous/rp2040_microphone_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_microphone_continuous/rp2040_microphone_continuous.ino new file mode 100644 index 0000000..0030f27 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/rp2040/rp2040_microphone_continuous/rp2040_microphone_continuous.ino @@ -0,0 +1,267 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +// If your target is limited in memory remove this macro to save 10K RAM +#define EIDSP_QUANTIZE_FILTERBANK 0 +#define EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW 3 +#define EI_CLASSIFIER_SLICE_SIZE (EI_CLASSIFIER_RAW_SAMPLE_COUNT / EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW) + +/* + ** NOTE: If you run into TFLite arena allocation issue. + ** + ** This may be due to may dynamic memory fragmentation. + ** Try defining "-DEI_CLASSIFIER_ALLOCATION_STATIC" in boards.local.txt (create + ** if it doesn't exist) and copy this file to + ** `/arduino/hardware///`. + ** + ** See + ** (https://support.arduino.cc/hc/en-us/articles/360012076960-Where-are-the-installed-cores-located-) + ** to find where Arduino installs cores on your machine. + ** + ** If the problem persists then there's not enough memory for this model and application. + */ + +/* + ** NOTE: If you are seeing Error sample buffer overrun. + ** + ** Cortex M0+ has no hardware floating point support, therfore DSP + ** operations are rather slow. You can try decreasing + ** EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW or tweak the MFCC/MFE block parameters + ** in Studio and re-deploy your project to get faster processing times. + */ + +/* Includes ---------------------------------------------------------------- */ +#include +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + signed short *buffers[2]; + unsigned char buf_select; + unsigned char buf_ready; + unsigned int buf_count; + unsigned int n_samples; +} inference_t; + +static inference_t inference; +static volatile bool record_ready = false; +// static signed short *sampleBuffer; +static signed short sampleBuffer[2048]; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static int print_results = -(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW); + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: "); + ei_printf_float((float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf(" ms.\n"); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / + sizeof(ei_classifier_inferencing_categories[0])); + + run_classifier_init(); + if (microphone_inference_start(EI_CLASSIFIER_SLICE_SIZE) == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } +} + +/** + * @brief Arduino main function. Runs the inferencing loop. + */ +void loop() +{ + bool m = microphone_inference_record(); + if (!m) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + signal_t signal; + signal.total_length = EI_CLASSIFIER_SLICE_SIZE; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = {0}; + + EI_IMPULSE_ERROR res = run_classifier_continuous(&signal, &result, debug_nn); + if (res != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", res); + return; + } + + if (++print_results >= (EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW)) { + // print inference return code + ei_printf("run_classifier returned: %d\r\n", res); + print_inference_result(result); + print_results = 0; + } +} + +/** + * @brief PDM buffer full callback + * Copy audio data to app buffers + */ +static void pdm_data_ready_inference_callback(void) +{ + int bytesAvailable = PDM.available(); + + // read into the sample buffer + int bytesRead = PDM.read((char *)&sampleBuffer[0], bytesAvailable); + + if ((inference.buf_ready == 0) && (record_ready == true)) { + for(int i = 0; i < bytesRead>>1; i++) { + inference.buffers[inference.buf_select][inference.buf_count++] = sampleBuffer[i]; + + if (inference.buf_count >= inference.n_samples) { + inference.buf_select ^= 1; + inference.buf_count = 0; + inference.buf_ready = 1; + break; + } + } + } +} + +/** + * @brief Init inferencing struct and setup/start PDM + * + * @param[in] n_samples The n samples + * + * @return { description_of_the_return_value } + */ +static bool microphone_inference_start(uint32_t n_samples) +{ + inference.buffers[0] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[0] == NULL) { + return false; + } + + inference.buffers[1] = (signed short *)malloc(n_samples * sizeof(signed short)); + + if (inference.buffers[1] == NULL) { + ei_free(inference.buffers[0]); + return false; + } + + inference.buf_select = 0; + inference.buf_count = 0; + inference.n_samples = n_samples; + inference.buf_ready = 0; + + // configure the data receive callback + PDM.onReceive(&pdm_data_ready_inference_callback); + + PDM.setBufferSize(2048); + delay(250); + + // initialize PDM with: + // - one channel (mono mode) + if (!PDM.begin(1, EI_CLASSIFIER_FREQUENCY)) { + ei_printf("ERR: Failed to start PDM!"); + return false; + } + + // optionally set the gain, defaults to 24 + // Note: values >=52 not supported + //PDM.setGain(40); + + record_ready = true; + + return true; +} + +/** + * @brief Wait on new data + * + * @return True when finished + */ +static bool microphone_inference_record(void) +{ + bool ret = true; + + if (inference.buf_ready == 1) { + ei_printf( + "Error sample buffer overrun. Decrease the number of slices per model window " + "EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW is currently set to %d\n", EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW); + ret = false; + } + + while (inference.buf_ready == 0) { + delay(1); + } + + inference.buf_ready = 0; + + return ret; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffers[inference.buf_select ^ 1][offset], out_ptr, length); + + return 0; +} + +/** + * @brief Stop PDM and release buffers + */ +static void microphone_inference_end(void) +{ + PDM.end(); + ei_free(inference.buffers[0]); + ei_free(inference.buffers[1]); + record_ready = false; +} + +void print_inference_result(ei_impulse_result_t result) { + + // Print how long it took to perform inference + ei_printf("Timing: DSP %d ms, inference %d ms, anomaly %d ms\r\n", + result.timing.dsp, + result.timing.classification, + result.timing.anomaly); + + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_camera/sony_spresense_camera.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_camera/sony_spresense_camera.ino new file mode 100644 index 0000000..cb1822d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_camera/sony_spresense_camera.ino @@ -0,0 +1,397 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include + +#include "edge-impulse-sdk/dsp/image/image.hpp" +#include "Camera.h" + +/* + * IMPORTANT In Tools->Board select the Spresense device, then under Tools->Memory select 1536(kB). + * We do not need the audio or multi-core memory layouts for this project, but we do need as much memory available as possible for NN and image storage. +*/ + +/* Constant defines -------------------------------------------------------- */ +#define EI_CAMERA_RAW_FRAME_BUFFER_COLS CAM_IMGSIZE_QVGA_H +#define EI_CAMERA_RAW_FRAME_BUFFER_ROWS CAM_IMGSIZE_QVGA_V +#define EI_CAMERA_RAW_FRAME_BYTE_SIZE 2 + +#define ALIGN_PTR(p,a) ((p & (a-1)) ?(((uintptr_t)p + a) & ~(uintptr_t)(a-1)) : p) + +/* Edge Impulse ------------------------------------------------------------- */ + +typedef struct { + size_t width; + size_t height; +} ei_device_resize_resolutions_t; + +/** + * @brief Check if new serial data is available + * + * @return Returns number of available bytes + */ +int ei_get_serial_available(void) +{ + return Serial.available(); +} + +/** + * @brief Get next available byte + * + * @return byte + */ +char ei_get_serial_byte(void) +{ + return Serial.read(); +} + +/* Private variables ------------------------------------------------------- */ +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static bool is_initialised = false; + +/* +** @brief points to the output of the capture +*/ +static uint8_t *ei_camera_capture_out = NULL; + +/* Function definitions ------------------------------------------------------- */ +bool ei_camera_init(void); +void ei_camera_deinit(void); +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) ; +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize); +static int ei_camera_get_data(size_t offset, size_t length, float *out_ptr); + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + if (ei_camera_init() == false) { + ei_printf("Failed to initialize Camera!\r\n"); + } + else { + ei_printf("Camera initialized\r\n"); + } +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + ei_printf("\nStarting inferencing in 2 seconds...\n"); + + if (ei_sleep(2000) != EI_IMPULSE_OK) { + return; + } + + ei_printf("Taking photo...\n"); + + if (ei_camera_capture((size_t)EI_CLASSIFIER_INPUT_WIDTH, (size_t)EI_CLASSIFIER_INPUT_HEIGHT, NULL) == false) { + ei_printf("Failed to capture image\r\n"); + return; + } + + ei::signal_t signal; + signal.total_length = EI_CLASSIFIER_INPUT_WIDTH * EI_CLASSIFIER_INPUT_HEIGHT; + signal.get_data = &ei_camera_get_data; + + // Run the classifier + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR err = run_classifier(&signal, &result, debug_nn); + if (err != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + return; + } + + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.): \n", + result.timing.dsp, result.timing.classification, result.timing.anomaly); +#if EI_CLASSIFIER_OBJECT_DETECTION == 1 + ei_printf("Object detection bounding boxes:\r\n"); + for (uint32_t i = 0; i < result.bounding_boxes_count; i++) { + ei_impulse_result_bounding_box_t bb = result.bounding_boxes[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } + + // Print the prediction results (classification) +#else + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } +#endif + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + ei_printf("Visual anomalies:\r\n"); + for (uint32_t i = 0; i < result.visual_ad_count; i++) { + ei_impulse_result_bounding_box_t bb = result.visual_ad_grid_cells[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } +#endif +} + +/** + * @brief Setup image sensor & start streaming + * + * @retval false if initialisation failed + */ +bool ei_camera_init(void) +{ + CamErr err; + if (is_initialised) { + return true; + } + + Serial.println("Prepare camera"); + err = theCamera.begin(); + if (err != CAM_ERR_SUCCESS) { + ei_printf("Camera begin failed\r\n"); + return false; + } + if (theCamera.getDeviceType() == CAM_DEVICE_TYPE_UNKNOWN) { + ei_printf("Camera not found\r\n"); + return false; + } + + /* Auto white balance configuration */ + Serial.println("Set Auto white balance parameter"); + err = theCamera.setAutoWhiteBalanceMode(CAM_WHITE_BALANCE_AUTO); + if (err != CAM_ERR_SUCCESS) { + ei_printf("Auto white balancing setup failed\r\n"); + return false; + } + + /* Set parameters about still picture. + * In the following case, QVGA and YUV422. + */ + Serial.println("Set still picture format"); + err = theCamera.setStillPictureImageFormat( + EI_CAMERA_RAW_FRAME_BUFFER_COLS, + EI_CAMERA_RAW_FRAME_BUFFER_ROWS, + CAM_IMAGE_PIX_FMT_YUV422); + + if (err != CAM_ERR_SUCCESS) { + ei_printf("Camera set still image failed: %d\r\n", err); + return false; + } + + ei_camera_capture_out = (uint8_t*)ei_malloc(EI_CAMERA_RAW_FRAME_BUFFER_COLS * EI_CAMERA_RAW_FRAME_BUFFER_ROWS * 3 + 32); + ei_camera_capture_out = (uint8_t *)ALIGN_PTR((uintptr_t)ei_camera_capture_out, 32); + + if (ei_camera_capture_out == nullptr) { + ei_printf("ERR: Failed to allocate memory for capture buffer\r\n"); + return false; + } + + is_initialised = true; + + return true; +} + +/** + * @brief Stop streaming of sensor data + */ +void ei_camera_deinit(void) +{ + ei_free(ei_camera_capture_out); + ei_camera_capture_out = nullptr; + is_initialised = false; +} + +/** + * @brief Capture, rescale and crop image + * + * @param[in] img_width width of output image + * @param[in] img_height height of output image + * @param[in] out_buf pointer to store output image, NULL may be used + * if ei_camera_frame_buffer is to be used for capture and resize/cropping. + * + * @retval false if not initialised, image captured, rescaled or cropped failed + * + */ +bool ei_camera_capture(uint32_t img_width, uint32_t img_height, uint8_t *out_buf) +{ + bool do_resize = false; + bool do_crop = false; + + if (!is_initialised) { + ei_printf("ERR: Camera is not initialized\r\n"); + return false; + } + + CamImage img = theCamera.takePicture(); + + if (img.isAvailable() != true) { + ei_printf("ERR: Failed to get snapshot\r\n"); + return false; + } + + + // we take snapshot in yuv422 + if (ei::EIDSP_OK != ei::image::processing::yuv422_to_rgb888(ei_camera_capture_out, img.getImgBuff(), img.getImgSize(), ei::image::processing::BIG_ENDIAN_ORDER)) { + ei_printf("ERR: Conversion failed\n"); + return false; + } + + uint32_t resize_col_sz; + uint32_t resize_row_sz; + // choose resize dimensions + int res = calculate_resize_dimensions(img_width, img_height, &resize_col_sz, &resize_row_sz, &do_resize); + if (res) { + ei_printf("ERR: Failed to calculate resize dimensions (%d)\r\n", res); + return false; + } + + if ((img_width != resize_col_sz) + || (img_height != resize_row_sz)) { + do_crop = true; + } + + if (do_resize) { + ei::image::processing::crop_and_interpolate_rgb888( + ei_camera_capture_out, + EI_CAMERA_RAW_FRAME_BUFFER_COLS, + EI_CAMERA_RAW_FRAME_BUFFER_ROWS, + ei_camera_capture_out, + resize_col_sz, + resize_row_sz); + } + + return true; +} + +/** + * @brief Convert rgb565 data to rgb888 + * + * @param[in] src_buf The rgb565 data + * @param dst_buf The rgb888 data + * @param src_len length of rgb565 data + */ + +bool RBG565ToRGB888(uint8_t *src_buf, uint8_t *dst_buf, uint32_t src_len) +{ + uint8_t hb, lb; + uint32_t pix_count = src_len / 2; + + for(uint32_t i = 0; i < pix_count; i ++) { + hb = *src_buf++; + lb = *src_buf++; + + *dst_buf++ = hb & 0xF8; + *dst_buf++ = (hb & 0x07) << 5 | (lb & 0xE0) >> 3; + *dst_buf++ = (lb & 0x1F) << 3; + } + + return true; +} + +static int ei_camera_get_data(size_t offset, size_t length, float *out_ptr) +{ + // we already have a RGB888 buffer, so recalculate offset into pixel index + size_t pixel_ix = offset * 3; + size_t pixels_left = length; + size_t out_ptr_ix = 0; + + while (pixels_left != 0) { + out_ptr[out_ptr_ix] = (ei_camera_capture_out[pixel_ix] << 16) + (ei_camera_capture_out[pixel_ix + 1] << 8) + ei_camera_capture_out[pixel_ix + 2]; + + // go to the next pixel + out_ptr_ix++; + pixel_ix+=3; + pixels_left--; + } + + // and done! + return 0; +} + +/** + * @brief Determine whether to resize and to which dimension + * + * @param[in] out_width width of output image + * @param[in] out_height height of output image + * @param[out] resize_col_sz pointer to frame buffer's column/width value + * @param[out] resize_row_sz pointer to frame buffer's rows/height value + * @param[out] do_resize returns whether to resize (or not) + * + */ +int calculate_resize_dimensions(uint32_t out_width, uint32_t out_height, uint32_t *resize_col_sz, uint32_t *resize_row_sz, bool *do_resize) +{ + size_t list_size = 6; + const ei_device_resize_resolutions_t list[list_size] = { + {64, 64}, + {96, 96}, + {160, 120}, + {160, 160}, + {320, 240}, + }; + + // (default) conditions + *resize_col_sz = EI_CAMERA_RAW_FRAME_BUFFER_COLS; + *resize_row_sz = EI_CAMERA_RAW_FRAME_BUFFER_ROWS; + *do_resize = false; + + for (size_t ix = 0; ix < list_size; ix++) { + if ((out_width <= list[ix].width) && (out_height <= list[ix].height)) { + *resize_col_sz = list[ix].width; + *resize_row_sz = list[ix].height; + *do_resize = true; + break; + } + } + + return 0; +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_CAMERA +#error "Invalid model for current sensor" +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_microphone/sony_spresense_microphone.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_microphone/sony_spresense_microphone.ino new file mode 100644 index 0000000..9860cb9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_microphone/sony_spresense_microphone.ino @@ -0,0 +1,243 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include + +#include "edge-impulse-sdk/dsp/image/image.hpp" +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + int16_t *buffer; + uint8_t buf_ready; + uint32_t buf_count; + uint32_t n_samples; +} inference_t; + +/* Private variables ------------------------------------------------------- */ +static inference_t inference; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static AudioClass *theAudio; +static int32_t buffer_size = 1536; /*768sample,1ch,16bit*/ +static char *s_buffer; + +/* Recording bit rate + * Set in bps. + */ +static const int32_t recording_bitrate = ei_default_impulse.impulse->frequency; +/** + * number of channels + */ +static const uint8_t recording_channels = ei_default_impulse.impulse->raw_samples_per_frame; + +/* Function definitions ------------------------------------------------------- */ +static void audio_attention_cb(const ErrorAttentionParam *atprm); +static void microphone_inference_end(void); +static bool microphone_inference_record(void); +static bool microphone_inference_start(void); +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr); + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: %.4f ms.\n", (float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf("\tFrame size: %d\n", ei_default_impulse.impulse->dsp_input_frame_size); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + if (microphone_inference_start() == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } + +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + ei_printf("Starting inferencing in 2 seconds...\n"); + + delay(2000); + + ei_printf("Recording...\n"); + + if (AUDIOLIB_ECODE_OK != theAudio->startRecorder()) { + return false; + } + + if (microphone_inference_record() == false) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + theAudio->stopRecorder(); + + ei_printf("Recording done\n"); + + signal_t signal; + signal.total_length = ei_default_impulse.impulse->dsp_input_frame_size; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = { 0 }; + + EI_IMPULSE_ERROR r = run_classifier(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: %.5f\n", result.classification[ix].label, result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\n", result.anomaly); +#endif +} + +/** + * @brief + * + * @param n_samples + * @return true + * @return false + */ +static bool microphone_inference_start(void) +{ + inference.buffer = (int16_t *)ei_aligned_calloc(32, ei_default_impulse.impulse->raw_sample_count * sizeof(int16_t) * recording_channels); + + buffer_size *= recording_channels; + s_buffer = (char *)ei_aligned_calloc(32, buffer_size); + + if ((inference.buffer == NULL) || (s_buffer == NULL)) { + return false; + } + + inference.buf_count = 0; + inference.n_samples = ei_default_impulse.impulse->raw_sample_count; + inference.buf_ready = 0; + + theAudio = AudioClass::getInstance(); + + theAudio->begin(audio_attention_cb); + + /* Select input device as microphone */ + if (theAudio->setRecorderMode(AS_SETRECDR_STS_INPUTDEVICE_MIC, 220, SIMPLE_FIFO_BUF_SIZE, false) != 0) { + return false; + } + + if (theAudio->initRecorder(AS_CODECTYPE_PCM, "/mnt/sd0/BIN", recording_bitrate, recording_channels) != 0) { + return false; + } + + return true; +} + +/** + * @brief + * + * @return true + * @return false + */ +static bool microphone_inference_record(void) +{ + uint32_t length; + err_t err; + int16_t *samples = (int16_t *)s_buffer; + + inference.buf_ready = 0; + inference.buf_count = 0; + + do { + err = theAudio->readFrames(s_buffer, buffer_size, &length); + if ((err != AUDIOLIB_ECODE_OK) && (err != AUDIOLIB_ECODE_INSUFFICIENT_BUFFER_AREA)) { + return false; + } + for (uint32_t i = 0; i < (length >> 1); i++) { + inference.buffer[inference.buf_count++] = samples[i]; + + if (inference.buf_count >= (inference.n_samples * recording_channels)) { // n_samples is per channel + inference.buf_ready = 1; + break; + } + } + } while (inference.buf_ready == 0); + + return true; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + numpy::int16_to_float(&inference.buffer[offset], out_ptr, length); + + return 0; +} + +/** + * @brief + * + */ +static void microphone_inference_end(void) +{ + theAudio->stopRecorder(); + + theAudio->setReadyMode(); + theAudio->end(); + + ei_free(inference.buffer); + ei_free(s_buffer); +} + +/** + * @brief Audio attention callback + * + * When audio internal error occurs, this function will be called back. + */ + +static void audio_attention_cb(const ErrorAttentionParam *atprm) +{ + ei_printf("Audio error: %d\n", atprm->error_code); + + while(1){ + + } +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_microphone_continuous/sony_spresense_microphone_continuous.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_microphone_continuous/sony_spresense_microphone_continuous.ino new file mode 100644 index 0000000..e56f957 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/sony_spresense/sony_spresense_microphone_continuous/sony_spresense_microphone_continuous.ino @@ -0,0 +1,245 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include + +#include "edge-impulse-sdk/dsp/image/image.hpp" +#include + +/** Audio buffers, pointers and selectors */ +typedef struct { + signed short *buffers[2]; + unsigned char buf_select; + unsigned char buf_ready; + unsigned int buf_count; + unsigned int n_samples; +} inference_t; + +/* Private variables ------------------------------------------------------- */ +static inference_t inference; +static bool debug_nn = false; // Set this to true to see e.g. features generated from the raw signal +static AudioClass *theAudio; +static int32_t buffer_size = 1536; /*768sample,1ch,16bit*/ +static char *s_buffer; +static int print_results = -(EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW); + +/* Recording bit rate + * Set in bps. + */ +static const int32_t recording_bitrate = ei_default_impulse.impulse->frequency; +/** + * number of channels + */ +static const uint8_t recording_channels = ei_default_impulse.impulse->raw_samples_per_frame; + +/* Function definitions ------------------------------------------------------- */ +static void audio_attention_cb(const ErrorAttentionParam *atprm); +static void microphone_inference_end(void); +static bool microphone_inference_record(void); +static bool microphone_inference_start(void); +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr); + +/** +* @brief Arduino setup function +*/ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); + + // summary of inferencing settings (from model_metadata.h) + ei_printf("Inferencing settings:\n"); + ei_printf("\tInterval: %.4f ms.\n", (float)EI_CLASSIFIER_INTERVAL_MS); + ei_printf("\tFrame size: %d\n", EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE); + ei_printf("\tSample length: %d ms.\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT / 16); + ei_printf("\tNo. of classes: %d\n", sizeof(ei_classifier_inferencing_categories) / sizeof(ei_classifier_inferencing_categories[0])); + + if (microphone_inference_start() == false) { + ei_printf("ERR: Could not allocate audio buffer (size %d), this could be due to the window length of your model\r\n", EI_CLASSIFIER_RAW_SAMPLE_COUNT); + return; + } + +} + +/** +* @brief Get data and run inferencing +* +* @param[in] debug Get debug info if true +*/ +void loop() +{ + if (AUDIOLIB_ECODE_OK != theAudio->startRecorder()) { + return false; + } + + if (microphone_inference_record() == false) { + ei_printf("ERR: Failed to record audio...\n"); + return; + } + + theAudio->stopRecorder(); + + signal_t signal; + signal.total_length = ei_default_impulse.impulse->slice_size * ei_default_impulse.impulse->raw_samples_per_frame; + signal.get_data = µphone_audio_signal_get_data; + ei_impulse_result_t result = {0}; + + EI_IMPULSE_ERROR r = run_classifier_continuous(&signal, &result, debug_nn); + if (r != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", r); + return; + } + + if (++print_results >= (EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW >> 1)) { + // print the predictions + ei_printf("Predictions "); + ei_printf("(DSP: %d ms., Classification: %d ms., Anomaly: %d ms.)", + result.timing.dsp, result.timing.classification, result.timing.anomaly); + ei_printf(": \n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: %.5f\n", result.classification[ix].label, + result.classification[ix].value); + } +#if EI_CLASSIFIER_HAS_ANOMALY == 1 + ei_printf(" anomaly score: %.3f\n", result.anomaly); +#endif + + print_results = 0; + } +} + +/** + * @brief + * + * @param n_samples + * @return true + * @return false + */ +static bool microphone_inference_start(void) +{ + inference.buffers[0] = (int16_t *)ei_aligned_calloc(32, ei_default_impulse.impulse->slice_size * sizeof(int16_t) * recording_channels); + inference.buffers[1] = (int16_t *)ei_aligned_calloc(32, ei_default_impulse.impulse->slice_size * sizeof(int16_t) * recording_channels); + + buffer_size *= recording_channels; + s_buffer = (char *)ei_aligned_calloc(32, buffer_size); + + if ((inference.buffers[0] == NULL) || (inference.buffers[1] == NULL) || (s_buffer == NULL)) { + return false; + } + + inference.buf_select = 0; + inference.buf_count = 0; + inference.n_samples = ei_default_impulse.impulse->slice_size; + inference.buf_ready = 0; + + theAudio = AudioClass::getInstance(); + + theAudio->begin(audio_attention_cb); + + /* Select input device as microphone */ + if (theAudio->setRecorderMode(AS_SETRECDR_STS_INPUTDEVICE_MIC, 220, SIMPLE_FIFO_BUF_SIZE, false) != 0) { + return false; + } + + if (theAudio->initRecorder(AS_CODECTYPE_PCM, "/mnt/sd0/BIN", recording_bitrate, recording_channels) != 0) { + return false; + } + + return true; +} + +/** + * @brief + * + * @return true + * @return false + */ +static bool microphone_inference_record(void) +{ + uint32_t length; + err_t err; + int16_t *samples = (int16_t *)s_buffer; + + inference.buf_ready = 0; + + do { + err = theAudio->readFrames(s_buffer, buffer_size, &length); + if ((err != AUDIOLIB_ECODE_OK) && (err != AUDIOLIB_ECODE_INSUFFICIENT_BUFFER_AREA)) { + return false; + } + for (uint32_t i = 0; i < (length >> 1); i++) { + inference.buffers[inference.buf_select][inference.buf_count++] = samples[i]; + + if (inference.buf_count >= (inference.n_samples * recording_channels)) { // n_samples is per channel + inference.buf_select ^= 1; + inference.buf_count = 0; + inference.buf_ready = 1; + } + } + } while (inference.buf_ready == 0); + + return true; +} + +/** + * Get raw audio signal data + */ +static int microphone_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) +{ + ei::numpy::int16_to_float(&inference.buffers[inference.buf_select ^ 1][offset], out_ptr, length); + + return 0; +} + +/** + * @brief + * + */ +static void microphone_inference_end(void) +{ + theAudio->stopRecorder(); + + theAudio->setReadyMode(); + theAudio->end(); + + ei_free(inference.buffers[0]); + ei_free(inference.buffers[1]); + ei_free(s_buffer); +} + +/** + * @brief Audio attention callback + * + * When audio internal error occurs, this function will be called back. + */ + +static void audio_attention_cb(const ErrorAttentionParam *atprm) +{ + ei_printf("Audio error: %d\n", atprm->error_code); + + while(1){ + + } +} + +#if !defined(EI_CLASSIFIER_SENSOR) || EI_CLASSIFIER_SENSOR != EI_CLASSIFIER_SENSOR_MICROPHONE +#error "Invalid model for current sensor." +#endif \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/static_buffer/static_buffer/static_buffer.ino b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/static_buffer/static_buffer/static_buffer.ino new file mode 100644 index 0000000..a05c51c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/examples/static_buffer/static_buffer/static_buffer.ino @@ -0,0 +1,145 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* Includes ---------------------------------------------------------------- */ +#include + +static const float features[] = { + // copy raw features here (for example from the 'Live classification' page) + // see https://docs.edgeimpulse.com/docs/running-your-impulse-arduino +}; + +/** + * @brief Copy raw feature data in out_ptr + * Function called by inference library + * + * @param[in] offset The offset + * @param[in] length The length + * @param out_ptr The out pointer + * + * @return 0 + */ +int raw_feature_get_data(size_t offset, size_t length, float *out_ptr) { + memcpy(out_ptr, features + offset, length * sizeof(float)); + return 0; +} + +void print_inference_result(ei_impulse_result_t result); + +/** + * @brief Arduino setup function + */ +void setup() +{ + // put your setup code here, to run once: + Serial.begin(115200); + // comment out the below line to cancel the wait for USB connection (needed for native USB) + while (!Serial); + Serial.println("Edge Impulse Inferencing Demo"); +} + +/** + * @brief Arduino main function + */ +void loop() +{ + ei_printf("Edge Impulse standalone inferencing (Arduino)\n"); + + if (sizeof(features) / sizeof(float) != EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE) { + ei_printf("The size of your 'features' array is not correct. Expected %lu items, but had %lu\n", + EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, sizeof(features) / sizeof(float)); + delay(1000); + return; + } + + ei_impulse_result_t result = { 0 }; + + // the features are stored into flash, and we don't want to load everything into RAM + signal_t features_signal; + features_signal.total_length = sizeof(features) / sizeof(features[0]); + features_signal.get_data = &raw_feature_get_data; + + // invoke the impulse + EI_IMPULSE_ERROR res = run_classifier(&features_signal, &result, false /* debug */); + if (res != EI_IMPULSE_OK) { + ei_printf("ERR: Failed to run classifier (%d)\n", res); + return; + } + + // print inference return code + ei_printf("run_classifier returned: %d\r\n", res); + print_inference_result(result); + + delay(1000); +} + +void print_inference_result(ei_impulse_result_t result) { + + // Print how long it took to perform inference + ei_printf("Timing: DSP %d ms, inference %d ms, anomaly %d ms\r\n", + result.timing.dsp, + result.timing.classification, + result.timing.anomaly); + + // Print the prediction results (object detection) +#if EI_CLASSIFIER_OBJECT_DETECTION == 1 + ei_printf("Object detection bounding boxes:\r\n"); + for (uint32_t i = 0; i < result.bounding_boxes_count; i++) { + ei_impulse_result_bounding_box_t bb = result.bounding_boxes[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } + + // Print the prediction results (classification) +#else + ei_printf("Predictions:\r\n"); + for (uint16_t i = 0; i < EI_CLASSIFIER_LABEL_COUNT; i++) { + ei_printf(" %s: ", ei_classifier_inferencing_categories[i]); + ei_printf("%.5f\r\n", result.classification[i].value); + } +#endif + + // Print anomaly result (if it exists) +#if EI_CLASSIFIER_HAS_ANOMALY + ei_printf("Anomaly prediction: %.3f\r\n", result.anomaly); +#endif + +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + ei_printf("Visual anomalies:\r\n"); + for (uint32_t i = 0; i < result.visual_ad_count; i++) { + ei_impulse_result_bounding_box_t bb = result.visual_ad_grid_cells[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (%f) [ x: %u, y: %u, width: %u, height: %u ]\r\n", + bb.label, + bb.value, + bb.x, + bb.y, + bb.width, + bb.height); + } +#endif + +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/library.properties b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/library.properties new file mode 100644 index 0000000..7a602ef --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/library.properties @@ -0,0 +1,9 @@ +name=surface_inferencing +version=1.0.10 +author=EdgeImpulse Inc. +maintainer=EdgeImpulse Inc. +sentence=Arduino library for running machine learning models +paragraph=This library contains the signal processing code and machine learning models to classify real-world data for bike-3s-10Hz-5class. It has examples for the accelerometer, microphone and camera on the Arduino Nano 33 BLE Sense, Arduino Portenta H7 and Arduino Nicla Vision, but should run on most Arduino boards with an ARM core and at least 64K of RAM. +category=Data processing +url=https://forum.edgeimpulse.com/ +depends=Arduino_LSM9DS1, PDM, Arduino_OV767X \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/.gitignore b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/.gitignore new file mode 100644 index 0000000..ce7014e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/.gitignore @@ -0,0 +1,13 @@ +utensor/CTestTestfile.cmake +utensor/cmake_install.cmake +utensor/CMakeFiles/ +utensor/Makefile +utensor/CMakeCache.txt +utensor.lib +utensor/libutensor.a +*.o +*.d +doc/ +node_modules/ +package-lock.json +package.json \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/.mbedignore b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/.mbedignore new file mode 100644 index 0000000..08e33ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/.mbedignore @@ -0,0 +1,12 @@ +utensor/CMakeFiles/ +tensorflow/lite/micro/mbed/ +porting/arduino/ +porting/espressif/ +porting/himax/ +porting/posix/ +porting/silabs/ +porting/stm32-cubeai/ +porting/zephyr/ +classifier/ei_run_classifier_c* +third_party/arc_mli_package/ +tensorflow-lite/ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cachel1_armv7.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 0000000..e8f4002 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,434 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.2 + * @date 22. June 2022 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + /* + * For the endless loop issue with GCC and clang with O0. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack (GCC/clang O0). If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + SCB->DCCIMVAC = (uint32_t)&locals; + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armcc.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..a955d47 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..b4a1200 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.4 + * @date 30. May 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(fpscr) ((void)(fpscr)) +#endif + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang_ltm.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..1e255d5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_gcc.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..bf7cd11 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2217 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +// Patched by Edge Impulse, fix for targets that already have __enable_irq +#ifndef __enable_irq +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +// Patched by Edge Impulse, fix for targets that already have __disable_irq +#ifndef __disable_irq +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_iccarm.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..65b824b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_version.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..8b4765f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv81mml.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000..fa1afb8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv8mbl.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000..f99d5bf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv8mml.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000..ede72ec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.4 + * @date 30. May 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/** @} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/** @} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/** @} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/** @} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/** @} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/** @} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/** @}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/** @}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/** @}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/** @} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/** @} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/** @} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/** @} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/** @} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/** @} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/** @} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** @} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/** @} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/** @} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/** @} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/** @} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm0.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000..7d6938b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm0plus.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000..d854c85 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm1.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000..a96ab04 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm23.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000..1a6577a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm3.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000..b73615f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm33.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000..f964b15 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm35p.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000..c8bfddd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm4.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..a347f36 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm55.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 0000000..2f40d61 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4781 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.5 + * @date 12. May 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) ITM Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (0x1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (0x1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (0x1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm7.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000..649894a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm85.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 0000000..acb2eb1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4636 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.5 + * @date 12. May 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[27U]; + __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) ITM Integration Read Register */ + uint32_t RESERVED4[1U]; + __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + uint32_t RESERVED5[1U]; + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED6[46U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED7[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */ +#define ITM_ITREAD_AFVALID_Msk (0x1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */ + +#define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */ +#define ITM_ITREAD_ATREADY_Msk (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */ +#define ITM_ITWRITE_AFVALID_Msk (0x1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */ + +#define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */ +#define ITM_ITWRITE_ATREADY_Msk (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ +#define ITM_ITCTRL_IME_Msk (0x1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + __IOM uint32_t VMASK1; /*!< Offset: 0x03C (R/W) Comparator Value Mask 1 */ + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t VMASK3; /*!< Offset: 0x05C (R/W) Comparator Value Mask 3 */ + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED14[968U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ + uint32_t RESERVED15[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + uint32_t RESERVED1[3U]; + __IM uint32_t DDEVTYPE; /*!< Offset: 0x01C (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_sc000.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000..d01af06 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_sc300.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000..f6c3bfd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_starmc1.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 0000000..a6a399d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/mpu_armv7.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..d9eedf8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/mpu_armv8.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000..cb04a57 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.4 + * @date 30. May 2022 + ******************************************************************************/ +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/pac_armv81.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 0000000..854b60a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/pmu_armv8.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 0000000..f8f3d89 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/tz_context.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h new file mode 100644 index 0000000..55b789e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h @@ -0,0 +1,539 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Q31 */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Fast vector sqrt */ + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + /* Accurate scalar sqrt */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) + extern const q31_t sqrt_initial_lut_q31[32]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) + extern const q15_t sqrt_initial_lut_q15[16]; + #endif + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#ifdef __cplusplus +} +#endif + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h new file mode 100755 index 0000000..9c48086 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables_f16.h + * Description: Extern declaration for common tables + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_F16_H +#define _ARM_COMMON_TABLES_F16_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + /* F16 */ + #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) + extern const float16_t twiddleCoefF16_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + extern const float16_t twiddleCoefF16_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) + extern const float16_t twiddleCoefF16_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + extern const float16_t twiddleCoefF16_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) + extern const float16_t twiddleCoefF16_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + extern const float16_t twiddleCoefF16_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) + extern const float16_t twiddleCoefF16_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + extern const float16_t twiddleCoefF16_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + extern const float16_t twiddleCoefF16_4096[8192]; + #define twiddleCoefF16 twiddleCoefF16_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32) + extern const float16_t twiddleCoefF16_rfft_32[32]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64) + extern const float16_t twiddleCoefF16_rfft_64[64]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128) + extern const float16_t twiddleCoefF16_rfft_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256) + extern const float16_t twiddleCoefF16_rfft_256[256]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512) + extern const float16_t twiddleCoefF16_rfft_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024) + extern const float16_t twiddleCoefF16_rfft_1024[1024]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048) + extern const float16_t twiddleCoefF16_rfft_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096) + extern const float16_t twiddleCoefF16_rfft_4096[4096]; + #endif + + #endif /* ARMAC5 */ + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float16_t exp_tab_f16[8]; + extern const float16_t __logf_lut_f16[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_COMMON_TABLES_F16_H */ + + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h new file mode 100644 index 0000000..2efc0a1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h new file mode 100755 index 0000000..843f50e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs_f16.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f16() function. + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_F16_H +#define _ARM_CONST_STRUCTS_F16_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "arm_common_tables_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096; + #endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h new file mode 100755 index 0000000..8706197 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h @@ -0,0 +1,753 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + + +#ifdef __cplusplus +extern "C" +{ +#endif +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + + + + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df +#define INV_NEWTON_INIT_F32 0x7EF127EA + + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + + +/*************************************** + +Definitions available for f16 datatype with HW acceleration only + +***************************************/ +#if defined(ARM_FLOAT16_SUPPORTED) +#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in) +{ + float16x8_t tmpVec; + _Float16 acc; + + tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in); + in = vaddq_f16(tmpVec, in); + tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in); + in = vaddq_f16(tmpVec, in); + acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4); + + return acc; +} + +__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16( + float16x8_t vecIn) +{ + float16x8_t vecTmp, vecOut; + uint32_t tmp; + + vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn); + // TO TRACK : using canonical addition leads to unefficient code generation for f16 + // vecTmp = vecTmp + vecAccCpx0; + /* + * Compute + * re0+re1 | im0+im1 | re0+re1 | im0+im1 + * re2+re3 | im2+im3 | re2+re3 | im2+im3 + */ + vecTmp = vaddq_f16(vecTmp, vecIn); + vecOut = vecTmp; + /* + * shift left, random tmp insertion in bottom + */ + vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32)); + /* + * Compute: + * DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1 + * re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3 + */ + vecOut = vaddq_f16(vecOut, vecTmp); + /* + * Cmplx sum is in 4rd & 5th f16 elt + * return full vector + */ + return vecOut; +} + + +#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \ +{ \ + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \ + Re = vgetq_lane(vecOut, 4); \ + Im = vgetq_lane(vecOut, 5); \ +} + +__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16( + float16x8_t vecIn, + float16_t *pOut) +{ + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn); + /* + * Cmplx sum is in 4rd & 5th f16 elt + * use 32-bit extraction + */ + *(float32_t *) pOut = ((float32x4_t) vecOut)[2]; +} + + +#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */ + +/* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */ +#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \ +{ \ + float16x8_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} + +#endif +#endif + +/*************************************** + +Definitions available for MVEI and MVEF only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit( + uint16_t srcRows, + uint16_t srcCols, + uint32_t *pDataSrc, + uint16_t dstRows, + uint16_t dstCols, + uint32_t *pDataDest) +{ + uint32_t i; + uint32_t const *pDataC; + uint32_t *pDataRow; + uint32_t *pDataDestR, *pDataDestRow; + uint32x4_t vecOffsRef, vecOffsCur; + uint32_t blkCnt; + uint32x4_t vecIn; + +#ifdef ARM_MATH_MATRIX_CHECK + /* + * Check for matrix mismatch condition + */ + if ((srcRows != dstCols) || (srcCols != dstRows)) + { + /* + * Set status as ARM_MATH_SIZE_MISMATCH + */ + return ARM_MATH_SIZE_MISMATCH; + } +#else + (void)dstRows; + (void)dstCols; +#endif + + /* 2x2, 3x3 and 4x4 specialization to be added */ + + vecOffsRef[0] = 0; + vecOffsRef[1] = 1; + vecOffsRef[2] = srcCols << 1; + vecOffsRef[3] = (srcCols << 1) + 1; + + pDataRow = pDataSrc; + pDataDestRow = pDataDest; + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataRow; + pDataDestR = pDataDestRow; + vecOffsCur = vecOffsRef; + + blkCnt = (srcRows * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + vecOffsCur = vaddq(vecOffsCur, (srcCols << 2)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (srcRows * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataRow += CMPLX_DIM; + pDataDestRow += (srcRows * CMPLX_DIM); + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + pDataDest[0] = pDataSrc[0]; + pDataDest[3] = pDataSrc[3]; + pDataDest[2] = pDataSrc[1]; + pDataDest[1] = pDataSrc[2]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 }; + uint16x8_t vecOffs1; + uint16x8_t vecIn1; + /* + * + * | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 | + * | 3 4 5 | => | 1 4 7 | => | 8 . . . . . . . | + * | 6 7 8 | | 2 5 8 | (row major) + * + */ + vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33); + vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc); + + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 }; + static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 }; + uint16x8_t vecOffs1, vecOffs2; + uint16x8_t vecIn1, vecIn2; + uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc; + + /* + * 4x4 Matrix transposition + * + * | 0 1 2 3 | | 0 4 8 12 | 8 x 16 flattened version + * | 4 5 6 7 | => | 1 5 9 13 | => [0 4 8 12 1 5 9 13] + * | 8 9 10 11 | | 2 6 10 14 | [2 6 10 14 3 7 11 15] + * | 12 13 14 15 | | 3 7 11 15 | + */ + + vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1); + vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2); + vecIn1 = vldrhq_u16(pDataSrcVec); + pDataSrcVec += 8; + vecIn2 = vldrhq_u16(pDataSrcVec); + + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2); + + + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_trans_16bit_generic( + uint16_t srcRows, + uint16_t srcCols, + uint16_t * pDataSrc, + uint16_t * pDataDest) +{ + uint16x8_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint16_t const *pDataC; + uint16_t *pDataDestR; + uint16x8_t vecIn; + + vecOffs = vidupq_u16((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + while(i > 0U) + { + pDataC = (uint16_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 3; + while (blkCnt > 0U) + { + vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); + vstrhq_u16(pDataDestR, vecIn); + pDataDestR += 8; + pDataC = pDataC + srcCols * 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); + vstrhq_p_u16(pDataDestR, vecIn, p0); + } + pDataSrc += 1; + pDataDest += srcRows; + i--; + } + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( + uint16_t srcRows, + uint16_t srcCols, + uint16_t *pDataSrc, + uint16_t dstRows, + uint16_t dstCols, + uint16_t *pDataDest) +{ + static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 }; + int i; + uint16x8_t vecOffsRef, vecOffsCur; + uint16_t const *pDataC; + uint16_t *pDataRow; + uint16_t *pDataDestR, *pDataDestRow; + uint32_t blkCnt; + uint16x8_t vecIn; + +#ifdef ARM_MATH_MATRIX_CHECK + /* + * Check for matrix mismatch condition + */ + if ((srcRows != dstCols) || (srcCols != dstRows)) + { + /* + * Set status as ARM_MATH_SIZE_MISMATCH + */ + return ARM_MATH_SIZE_MISMATCH; + } +#else + (void)dstRows; + (void)dstCols; +#endif + + /* + * 2x2, 3x3 and 4x4 specialization to be added + */ + + + /* + * build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1] + */ + vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol); + vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM)) + + viwdupq_u16((uint32_t)0, (uint16_t) 2, 1); + + pDataRow = pDataSrc; + pDataDestRow = pDataDest; + i = srcCols; + do + { + pDataC = (uint16_t const *) pDataRow; + pDataDestR = pDataDestRow; + vecOffsCur = vecOffsRef; + + blkCnt = (srcRows * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); + vstrhq(pDataDestR, vecIn); + pDataDestR+= 8; // VEC_LANES_U16 + vecOffsCur = vaddq(vecOffsCur, (srcCols << 3)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (srcRows * CMPLX_DIM) & 0x7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); + vstrhq_p(pDataDestR, vecIn, p0); + } + + pDataRow += CMPLX_DIM; + pDataDestRow += (srcRows * CMPLX_DIM); + } + while (--i); + + return (ARM_MATH_SUCCESS); +} +#endif /* MVEF and MVEI */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) +#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff) + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq_n_s32(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq_n_s16(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h new file mode 100644 index 0000000..989ba29 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h @@ -0,0 +1,225 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * \section intro Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - \ref groupMath "Basic math functions" + * - \ref groupFastMath "Fast math functions" + * - \ref groupCmplxMath "Complex math functions" + * - \ref groupFilters "Filtering functions" + * - \ref groupMatrix "Matrix functions" + * - \ref groupTransforms "Transform functions" + * - \ref groupController "Motor control functions" + * - \ref groupStats "Statistical functions" + * - \ref groupSupport "Support functions" + * - \ref groupInterpolation "Interpolation functions" + * - \ref groupSVM "Support Vector Machine functions (SVM)" + * - \ref groupBayes "Bayes classifier functions" + * - \ref groupDistance "Distance functions" + * - \ref groupQuaternionMath "Quaternion functions" + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * The library is providing vectorized versions of most algorthms for Helium + * and of most f32 algorithms for Neon. + * + * When using a vectorized version, provide a little bit of padding after the end of + * a buffer (3 words) because the vectorized code may read a little bit after the end + * of a buffer. You don't have to modify your buffers but just ensure that the + * end of buffer + padding is not outside of a memory region. + * + * \section using Using the Library + * + * The library is released in source form. It is strongly advised to compile the library using -Ofast to + * have the best performances. + * + * The library functions are declared in the public file `arm_math.h` which is placed in the `Include` folder. + * Simply include this file. If you don't want to include everything, you can also rely + * on headers in `Include/dsp` folder and use only what you need. + * + * \section example Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. Please refer to \ref groupExamples. + * + * \section toolchain Toolchain Support + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M4, M7, M33, M55, A32 are tested. + * + * + * \section preprocessor Preprocessor Macros + * + * Each library project has different preprocessor macros. + * + * - `ARM_MATH_BIG_ENDIAN`: + * - Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * . + * - `ARM_MATH_MATRIX_CHECK`: + * - Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * . + * - `ARM_MATH_ROUNDING`: + * - Define macro ARM_MATH_ROUNDING for rounding on support functions + * . + * - `ARM_MATH_LOOPUNROLL`: + * - Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * . + * - `ARM_MATH_NEON`: + * - Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * . + * - `ARM_MATH_NEON_EXPERIMENTAL`: + * - Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * . + * - `ARM_MATH_HELIUM`: + * - It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16. + * . + * - `ARM_MATH_HELIUM_EXPERIMENTAL`: + * - Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined. + * Enable some vector versions which may have worse performance than scalar + * depending on the core / compiler configuration. + * . + * - `ARM_MATH_MVEF`: + * - Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * . + * - `ARM_MATH_MVEI`: + * - Select Helium versions of the int and fixed point algorithms. + * . + * - `ARM_MATH_MVE_FLOAT16`: + * - MVE Float16 implementations of some algorithms (Requires MVE extension). + * . + * - `DISABLEFLOAT16`: + * - Disable float16 algorithms when __fp16 is not supported for a + * specific compiler / core configuration. + * This is only valid for scalar. When vector architecture is + * supporting f16 then it can't be disabled. + * . + * - `ARM_MATH_AUTOVECTORIZE`: + * - With Helium or Neon, disable the use of vectorized code with C intrinsics + * and use pure C instead. The vectorization is then done by the compiler. + * + * \section pack CMSIS-DSP in ARM::CMSIS Pack + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\ComputeLibrary | Small Neon kernels when building on Cortex-A + * |\b CMSIS\\DSP\\Include | include files for using and building the lib + * |\b CMSIS\\DSP\\PrivateInclude | private include files for building the lib | + * |\b CMSIS\\DSP\\Source | source files | + * + * \section rev Revision History of CMSIS-DSP + * Please refer to \ref ChangeLog_pg. + * + * \section license License + * + * The CMSIS-DSP is provided free of charge under the Apache 2.0 License. + */ + + + + + + + + + + + +/** + * @defgroup groupExamples Examples + */ + + + + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" + + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +//#define TABLE_SPACING_Q31 0x400000 +//#define TABLE_SPACING_Q15 0x80 + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_f16.h new file mode 100755 index 0000000..166d7d6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_f16.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * @file arm_math_f16.h + * @brief Public header file for f16 function of the CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_F16_H +#define _ARM_MATH_F16_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_MATH_F16_H */ + + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h new file mode 100755 index 0000000..850d51e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file arm_math_memory.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_MEMORY_H_ + +#define _ARM_MATH_MEMORY_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t const * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +#define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2) + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +#define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2) + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (q15_t)(val & 0x0FFFF); + (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF); +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = (q15_t)(val & 0x0FFFF); + pQ15[1] = (q15_t)(val >> 16); +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4 ( + q7_t const * pQ7) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ7, 4); +#else + val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF); +#endif + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +#define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4) + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +#define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4) + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = (q7_t)(val & 0x0FF); + (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF); + (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF); + (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF); + +#endif + *pQ7 += 4; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_MEMORY_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h new file mode 100755 index 0000000..b3db6f7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h @@ -0,0 +1,616 @@ +/****************************************************************************** + * @file arm_math_types.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_TYPES_H_ + +#define _ARM_MATH_TYPES_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __APPLE_CC__ ) + #pragma GCC diagnostic ignored "-Wold-style-cast" + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) +#elif defined ( __APPLE_CC__ ) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __STATIC_INLINE static inline +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __STATIC_INLINE static inline + +#else +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) + #if defined(_MSC_VER) && defined(_M_ARM64EC) + #include + #else + #include + #endif + #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + #if !defined(ARM_MATH_NEON_FLOAT16) + #define ARM_MATH_NEON_FLOAT16 + #endif + #endif +#endif + +#if !defined(ARM_MATH_AUTOVECTORIZE) + + +#if defined(__ARM_FEATURE_MVE) +#if __ARM_FEATURE_MVE + #if !defined(ARM_MATH_MVEI) + #define ARM_MATH_MVEI + #endif +#endif + +#if (__ARM_FEATURE_MVE & 2) + #if !defined(ARM_MATH_MVEF) + #define ARM_MATH_MVEF + #endif + #if !defined(ARM_MATH_MVE_FLOAT16) + #define ARM_MATH_MVE_FLOAT16 + #endif +#endif + +#endif /*defined(__ARM_FEATURE_MVE)*/ +#endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#if defined (ARM_MATH_HELIUM) + #if !defined(ARM_MATH_MVEF) + #define ARM_MATH_MVEF + #endif + + #if !defined(ARM_MATH_MVEI) + #define ARM_MATH_MVEI + #endif + + #if !defined(ARM_MATH_MVE_FLOAT16) + #define ARM_MATH_MVE_FLOAT16 + #endif +#endif + + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __APPLE_CC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __APPLE_CC__ ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + +#if defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ +#if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2) + typedef float float32_t; +#endif + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + + + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + + + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + + + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */ + ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */ + } arm_status; + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_TYPES_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h new file mode 100755 index 0000000..771af5c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h @@ -0,0 +1,163 @@ +/****************************************************************************** + * @file arm_math_types_f16.h + * @brief Public header file for f16 function of the CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_TYPES_F16_H +#define _ARM_MATH_TYPES_F16_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined( __CC_ARM ) + +/** + * @brief 16-bit floating-point type definition. + * This is already defined in arm_mve.h + * + * This is not fully supported on ARM AC5. + */ + +/* + +Check if the type __fp16 is available. +If it is not available, f16 version of the kernels +won't be built. + +*/ +#if !(__ARM_FEATURE_MVE & 2) + #if !defined(DISABLEFLOAT16) + #if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE) + typedef __fp16 float16_t; + #define ARM_FLOAT16_SUPPORTED + #endif + #endif +#else + /* When Vector float16, this flag is always defined and can't be disabled */ + #define ARM_FLOAT16_SUPPORTED +#endif + +#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ + +#if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16) + + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; + + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; + + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + + +#if defined(ARM_MATH_NEON_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; + + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; + + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + +#endif + + + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if defined(__ICCARM__) + +#define F16INFINITY ((float16_t) INFINITY) + +#else + +#define F16INFINITY ((float16_t)__builtin_inf()) + +#endif + +#define F16_MAX ((float16_t)__FLT16_MAX__) +#define F16_MIN (-(_Float16)__FLT16_MAX__) + +#define F16_ABSMAX ((float16_t)__FLT16_MAX__) +#define F16_ABSMIN ((float16_t)0.0f16) + +#endif /* ARM_FLOAT16_SUPPORTED*/ +#endif /* !defined( __CC_ARM ) */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_MATH_F16_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h new file mode 100755 index 0000000..43456f0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h @@ -0,0 +1,231 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#ifdef __cplusplus +} +#endif + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h new file mode 100755 index 0000000..62b8d9b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables_f16.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_F16_H + #define _ARM_MVE_TABLES_F16_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2]; +extern float16_t rearranged_twiddle_stride1_16_f16[8]; +extern float16_t rearranged_twiddle_stride2_16_f16[8]; +extern float16_t rearranged_twiddle_stride3_16_f16[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3]; +extern float16_t rearranged_twiddle_stride1_64_f16[40]; +extern float16_t rearranged_twiddle_stride2_64_f16[40]; +extern float16_t rearranged_twiddle_stride3_64_f16[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4]; +extern float16_t rearranged_twiddle_stride1_256_f16[168]; +extern float16_t rearranged_twiddle_stride2_256_f16[168]; +extern float16_t rearranged_twiddle_stride3_256_f16[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5]; +extern float16_t rearranged_twiddle_stride1_1024_f16[680]; +extern float16_t rearranged_twiddle_stride2_1024_f16[680]; +extern float16_t rearranged_twiddle_stride3_1024_f16[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6]; +extern float16_t rearranged_twiddle_stride1_4096_f16[2728]; +extern float16_t rearranged_twiddle_stride2_4096_f16[2728]; +extern float16_t rearranged_twiddle_stride3_4096_f16[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#ifdef __cplusplus +} +#endif + +#endif /*_ARM_MVE_TABLES_F16_H*/ + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h new file mode 100644 index 0000000..215b52f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file arm_sorting.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_SORTING_H_ +#define _ARM_SORTING_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_bubble_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_heap_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_insertion_sort_f32( + const arm_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_quick_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_selection_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_bitonic_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +#if defined(ARM_MATH_NEON) + +#define vtrn256_128q(a, b) \ +do { \ + float32x4_t vtrn128_temp = a.val[1]; \ + a.val[1] = b.val[0]; \ + b.val[0] = vtrn128_temp ; \ +} while (0) + +#define vtrn128_64q(a, b) \ +do { \ + float32x2_t ab, cd, ef, gh; \ + ab = vget_low_f32(a); \ + ef = vget_low_f32(b); \ + cd = vget_high_f32(a); \ + gh = vget_high_f32(b); \ + a = vcombine_f32(ab, ef); \ + b = vcombine_f32(cd, gh); \ +} while (0) + +#define vtrn256_64q(a, b) \ +do { \ + float32x2_t a_0, a_1, a_2, a_3; \ + float32x2_t b_0, b_1, b_2, b_3; \ + a_0 = vget_low_f32(a.val[0]); \ + a_1 = vget_high_f32(a.val[0]); \ + a_2 = vget_low_f32(a.val[1]); \ + a_3 = vget_high_f32(a.val[1]); \ + b_0 = vget_low_f32(b.val[0]); \ + b_1 = vget_high_f32(b.val[0]); \ + b_2 = vget_low_f32(b.val[1]); \ + b_3 = vget_high_f32(b.val[1]); \ + a.val[0] = vcombine_f32(a_0, b_0); \ + a.val[1] = vcombine_f32(a_2, b_2); \ + b.val[0] = vcombine_f32(a_1, b_1); \ + b.val[1] = vcombine_f32(a_3, b_3); \ +} while (0) + +#define vtrn128_32q(a, b) \ +do { \ + float32x4x2_t vtrn32_tmp = vtrnq_f32((a), (b)); \ + (a) = vtrn32_tmp.val[0]; \ + (b) = vtrn32_tmp.val[1]; \ +} while (0) + +#define vtrn256_32q(a, b) \ +do { \ + float32x4x2_t vtrn32_tmp_1 = vtrnq_f32((a.val[0]), (b.val[0])); \ + float32x4x2_t vtrn32_tmp_2 = vtrnq_f32((a.val[1]), (b.val[1])); \ + a.val[0] = vtrn32_tmp_1.val[0]; \ + a.val[1] = vtrn32_tmp_2.val[0]; \ + b.val[0] = vtrn32_tmp_1.val[1]; \ + b.val[1] = vtrn32_tmp_2.val[1]; \ +} while (0) + +#define vminmaxq(a, b) \ + do { \ + float32x4_t minmax_tmp = (a); \ + (a) = vminq_f32((a), (b)); \ + (b) = vmaxq_f32(minmax_tmp, (b)); \ +} while (0) + +#define vminmax256q(a, b) \ + do { \ + float32x4x2_t minmax256_tmp = (a); \ + a.val[0] = vminq_f32(a.val[0], b.val[0]); \ + a.val[1] = vminq_f32(a.val[1], b.val[1]); \ + b.val[0] = vmaxq_f32(minmax256_tmp.val[0], b.val[0]); \ + b.val[1] = vmaxq_f32(minmax256_tmp.val[1], b.val[1]); \ +} while (0) + +#define vrev128q_f32(a) \ + vcombine_f32(vrev64_f32(vget_high_f32(a)), vrev64_f32(vget_low_f32(a))) + +#define vrev256q_f32(a) \ + do { \ + float32x4_t rev_tmp = vcombine_f32(vrev64_f32(vget_high_f32(a.val[0])), vrev64_f32(vget_low_f32(a.val[0]))); \ + a.val[0] = vcombine_f32(vrev64_f32(vget_high_f32(a.val[1])), vrev64_f32(vget_low_f32(a.val[1]))); \ + a.val[1] = rev_tmp; \ +} while (0) + +#define vldrev128q_f32(a, p) \ + do { \ + a = vld1q_f32(p); \ + a = vrev128q_f32(a); \ +} while (0) + +#endif /* ARM_MATH_NEON */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_SORTING_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h new file mode 100755 index 0000000..4994892 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h @@ -0,0 +1,325 @@ +/****************************************************************************** + * @file arm_vec_fft.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 07. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_FFT_H_ +#define _ARM_VEC_FFT_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_CMPLX_ADD_A_ixB(A, B) vcaddq_rot90(A,B) +#define MVE_CMPLX_SUB_A_ixB(A,B) vcaddq_rot270(A,B) +#define MVE_CMPLX_MULT_FLT_AxB(A,B) vcmlaq_rot90(vcmulq(A, B), A, B) +#define MVE_CMPLX_MULT_FLT_Conj_AxB(A,B) vcmlaq_rot270(vcmulq(A, B), A, B) + +#define MVE_CMPLX_MULT_FX_AxB(A,B,TyA) vqdmladhxq(vqdmlsdhq((TyA)vuninitializedq_s32(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB(A,B,TyA) vqdmladhq(vqdmlsdhxq((TyA)vuninitializedq_s32(), A, B), A, B) + +#define MVE_CMPLX_ADD_FX_A_ixB(A, B) vhcaddq_rot90(A,B) +#define MVE_CMPLX_SUB_FX_A_ixB(A,B) vhcaddq_rot270(A,B) + + +/** + @brief In-place 32 bit reversal function for helium + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_32_inpl_mve( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) + +{ + uint64_t *src = (uint64_t *) pSrc; + int32_t blkCnt; /* loop counters */ + uint32x4_t bitRevTabOff; + uint32x4_t one = vdupq_n_u32(1); + uint64x2_t inLow, inHigh; + uint64x2_t bitRevOff1Low, bitRevOff0Low; + uint64x2_t bitRevOff1High, bitRevOff0High; + + /* load scheduling to increase gather load idx update / gather load distance */ + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one); + + + blkCnt = bitRevLen / 8; + while (blkCnt > 0) { + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + /* 64-bit index expansion */ + bitRevOff1Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff1High = vmulltq_int_u32(bitRevTabOff, one); + + inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High); + + vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow); + + + /* unrolled */ + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one); + + inLow = vldrdq_gather_offset_u64(src, bitRevOff1Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff1High); + + vstrdq_scatter_offset_u64(src, bitRevOff1Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff1High, inLow); + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + if (bitRevLen & 7) { + /* FFT size = 16 */ + inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High); + + vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow); + } +} + + + +/** + @brief In-place 16 bit reversal function for helium + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_16_inpl_mve( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) + +{ + uint32_t *src = (uint32_t *) pSrc; + int32_t blkCnt; /* loop counters */ + uint32x4_t bitRevTabOff; + uint16x8_t one = vdupq_n_u16(1); + uint32x4_t bitRevOff1Low, bitRevOff0Low; + uint32x4_t bitRevOff1High, bitRevOff0High; + uint32x4_t inLow, inHigh; + + /* load scheduling to increase gather load idx update / gather load distance */ + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + blkCnt = (bitRevLen / 16); + while (blkCnt > 0) { + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff1Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff1High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff1Low = vshrq_n_u16((uint16x8_t)bitRevOff1Low, 3); + bitRevOff1High = vshrq_n_u16((uint16x8_t)bitRevOff1High, 3); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + + /* loop unrolling */ + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff1Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff1High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff1Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff1High, inLow); + + blkCnt--; + } + + /* tail handling */ + blkCnt = bitRevLen & 0xf; + if (blkCnt == 8) { + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + } else if (blkCnt == 12) { + /* FFT 16 special case */ + mve_pred16_t p = vctp16q(4); + + bitRevTabOff = vldrhq_z_u16(pBitRevTab, p); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + inLow = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0Low, p); + inHigh = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0High, p); + + vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0Low, inHigh, p); + vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0High, inLow, p); + } +} + +/** + @brief Out-of-place 32 bit reversal function for helium + @param[out] pDst points to destination buffer of unknown 32-bit data type + @param[in] pSrc points to input buffer of unknown 32-bit data type + @param[in] fftLen FFT length + @return none +*/ +__STATIC_INLINE void arm_bitreversal_32_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen) +{ + uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1; + uint32_t bitRevPos, blkCnt; + uint32_t *pDst32 = (uint32_t *) pDst; + + /* fwd indexes */ + idxOffs0 = vdupq_n_u32(0); + idxOffs1 = vdupq_n_u32(0); + idxOffs0[0] = 0; idxOffs0[2] = 4; + idxOffs1[0] = 8; idxOffs1[2] = 12; + + bitRevPos = (31 - __CLZ(fftLen)) + 5; + blkCnt = fftLen >> 2; + + /* issued earlier to increase gather load idx update / gather load distance */ + /* bit-reverse fwd indexes */ + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + while (blkCnt > 0) { + uint64x2_t vecIn; + + vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs0); + idxOffs0 = idxOffs0 + 16; + vst1q(pDst32, (uint32x4_t) vecIn); + pDst32 += 4; + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + + vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs1); + idxOffs1 = idxOffs1 + 16; + vst1q(pDst32, (uint32x4_t) vecIn); + pDst32 += 4; + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + + blkCnt--; + } +} + + +/** + @brief Out-of-place 16 bit reversal function for helium + @param[out] pDst points to destination buffer of unknown 16-bit data type + @param[in] pSrc points to input buffer of unknown 16-bit data type + @param[in] fftLen FFT length + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_16_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen) +{ + uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1; + uint32_t bitRevPos, blkCnt; + uint16_t *pDst16 = (uint16_t *) pDst; + uint32_t incrIdx = 0; + + /* fwd indexes */ + idxOffs0 = vidupq_wb_u32(&incrIdx, 4); // {0, 4, 8, 12} + idxOffs1 = vidupq_wb_u32(&incrIdx, 4); // {16, 20, 24, 28} + + bitRevPos = (31 - __CLZ(fftLen)) + 4; + blkCnt = fftLen >> 3; + + /* issued earlier to increase gather load idx update / gather load distance */ + /* bit-reverse fwd indexes */ + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + while (blkCnt > 0) { + uint32x4_t vecIn; + + vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs0); + idxOffs0 = idxOffs0 + 32; + vst1q(pDst16, (uint16x8_t) vecIn); + pDst16 += 8; + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + + vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs1); + idxOffs1 = idxOffs1 + 32; + vst1q(pDst16, (uint16x8_t) vecIn); + pDst16 += 8; + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + + blkCnt--; + } +} + + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_FFT_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h new file mode 100755 index 0000000..f10663d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h @@ -0,0 +1,1586 @@ +/****************************************************************************** + * @file arm_vec_filtering.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 30. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_FILTERING_H_ +#define _ARM_VEC_FILTERING_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F32(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, acc2Vec, acc3Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + acc2Vec = vdupq_n_f32(0.0f); \ + acc3Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vldrwq_f32(&pSrcX[2]); \ + acc2Vec = vfmaq_f32(acc2Vec, xVec, yVec); \ + xVec = vldrwq_f32(&pSrcX[3]); \ + acc3Vec = vfmaq_f32(acc3Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vldrwq_f32(&pSrcX[2]); \ + acc2Vec = vfmaq_m_f32(acc2Vec, xVec, yVec, p0); \ + xVec = vldrwq_f32(&pSrcX[3]); \ + acc3Vec = vfmaq_m_f32(acc3Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ + acc2 = vecAddAcrossF32Mve(acc2Vec); \ + acc3 = vecAddAcrossF32Mve(acc3Vec); \ +} + +#define MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count) \ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t accVec, xVec, yVec; \ + uint32_t k; \ + \ + accVec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + accVec = vfmaq_f32(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + accVec = vfmaq_m_f32(accVec, xVec, yVec, p0);\ + } \ + acc = vecAddAcrossF32Mve(accVec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + yVec = vldrwq_f32(&pSrcY[-1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + yVec = vldrwq_f32(&pSrcY[-1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec,p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = (count - 1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = (count - 1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + p0 = vctp32q(k+1); \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX; \ + const float32_t *pY1 = pY + 1; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \ + pY1-=4; \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t accVec, xVec, yVec; \ + uint32_t k; \ + \ + accVec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + accVec = vfmaq_f32(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + accVec = vfmaq_m_f32(accVec, xVec, yVec, p0); \ + } \ + acc = vecAddAcrossF32Mve(accVec); \ +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) + +#define MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 31); \ +} + + + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX; \ + const q31_t *pY1 = pY + 1; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \ + pY1-=4; \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ + acc2 = asrl(acc2, 31); \ + acc3 = asrl(acc3, 31); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_s32(&pSrcY[-1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_s32(&pSrcY[-1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 31); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ + acc2 = asrl(acc2, 31); \ + acc3 = asrl(acc3, 31); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_s16(&pSrcY[-1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_s16(&pSrcY[-1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 15); \ + acc = __SSAT(acc, 16); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc2 = asrl(acc2, 15); \ + acc3 = asrl(acc3, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ + acc2 = __SSAT(acc2, 16); \ + acc3 = __SSAT(acc3, 16); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x8U; \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX; \ + const q15_t *pY1 = pY + 1; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \ + pY1-=8; \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 15); \ + acc = __SSAT(acc, 16); \ +} + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc2 = asrl(acc2, 15); \ + acc3 = asrl(acc3, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ + acc2 = __SSAT(acc2, 16); \ + acc3 = __SSAT(acc3, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_s8(&pSrcY[-1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_s8(&pSrcY[-1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc = vmladavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc = vmladavaq_p(acc, xVec, yVec, p0); \ + } \ + acc =(acc >> 7); \ + acc = __SSAT(acc, 8); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq(acc2, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc2 = (acc2 >> 7); \ + acc3 = (acc3 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ + acc2 = __SSAT(acc2, 8); \ + acc3 = __SSAT(acc3, 8); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = (count-1) >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x10U; \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX; \ + const q7_t *pY1 = pY + 1; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \ + pY1-=16; \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc = vmladavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + acc = vmladavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = __SSAT(acc >> 7, 8); \ +} + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq(acc2, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = __SSAT(acc0 >> 7, 8); \ + acc1 = __SSAT(acc1 >> 7, 8); \ + acc2 = __SSAT(acc2 >> 7, 8); \ + acc3 = __SSAT(acc3 >> 7, 8); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = __SSAT(acc0 >> 7, 8); \ + acc1 = __SSAT(acc1 >> 7, 8); \ +} + + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = (count-1) >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_FILTERING_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h new file mode 100755 index 0000000..dc32ca6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h @@ -0,0 +1,373 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h new file mode 100755 index 0000000..bca9ef8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h @@ -0,0 +1,312 @@ +/****************************************************************************** + * @file arm_vec_math_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_F16_H +#define _ARM_VEC_MATH_F16_H + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "arm_common_tables_f16.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + +static const float16_t __logf_rng_f16=0.693147180f16; + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f16x8_t vrecip_medprec_f16( + f16x8_t x) +{ + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x03c00 - (xinv.i & 0x07c00); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f16x8_t vrecip_hiprec_f16( + f16x8_t x) +{ + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x03c00 - (xinv.i & 0x07c00); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f16x8_t vdiv_f16( + f16x8_t num, f16x8_t den) +{ + return vmulq(num, vrecip_hiprec_f16(den)); +} + + +/** + @brief Single-precision taylor dev. + @param[in] x f16 vector input + @param[in] coeffs f16 vector coeffs + @return destination f16 vector + */ + +__STATIC_INLINE float16x8_t vtaylor_polyq_f16( + float16x8_t x, + const float16_t * coeffs) +{ + float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]); + float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]); + float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]); + float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]); + float16x8_t x2 = vmulq(x, x); + float16x8_t x4 = vmulq(x2, x2); + float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4); + + return res; +} + +#define VMANT_EXP_F16(x) \ + any16x8_t r; \ + int16x8_t n; \ + \ + r.f = x; \ + n = r.i >> 10; \ + n = n - 15; \ + r.i = r.i - (n << 10);\ + \ + vecExpUnBiased = n; \ + vecTmpFlt1 = r.f; + +__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn) +{ + q15x8_t vecExpUnBiased; + float16x8_t vecTmpFlt0, vecTmpFlt1; + float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + float16x8_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + VMANT_EXP_F16(vecIn); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f16[4] * r.f) + (__logf_lut_f16[0]); + */ + vecAcc0 = vdupq_n_f16(__logf_lut_f16[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f16[4]); + /* + * b = (__logf_lut_f16[6] * r.f) + (__logf_lut_f16[2]); + */ + vecAcc1 = vdupq_n_f16(__logf_lut_f16[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f16[6]); + /* + * c = (__logf_lut_f16[5] * r.f) + (__logf_lut_f16[1]); + */ + vecAcc2 = vdupq_n_f16(__logf_lut_f16[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f16[5]); + /* + * d = (__logf_lut_f16[7] * r.f) + (__logf_lut_f16[3]); + */ + vecAcc3 = vdupq_n_f16(__logf_lut_f16[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f16[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f16_s16(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f16; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f16); + // set log0 down to -inf + vecAcc0 = vdupq_m_n_f16(vecAcc0, -(_Float16)F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE float16x8_t vexpq_f16( + float16x8_t x) +{ + // Perform range reduction [-log(2),log(2)] + int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16)); + float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16)); + + // Polynomial Approximation + float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16); + + // Reconstruct + poly = (float16x8_t) (vqaddq_s16((int16x8_t) (poly), vqshlq_n_s16(m, 10))); + + poly = vdupq_m_n_f16(poly, 0.0f16, vcmpltq_n_s16(m, -14)); + return poly; +} + +__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb) +{ + float16x8_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f16x8_t vpowq_f16( + f16x8_t val, + f16x8_t n) +{ + return vexpq_f16(vmulq_f16(n, vlogq_f16(val))); +} + +#define INV_NEWTON_INIT_F16 0x7773 + +__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn) +{ + f16x8_t vecSx, vecW, vecTmp; + any16x8_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s16(INV_NEWTON_INIT_F16), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f16(8.0f16), vecW); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -70.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 8.0f16); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m_n_f16(v.f, F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq_n_f16(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f16x8_t vtanhq_f16( + f16x8_t val) +{ + f16x8_t x = + vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16)); + f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16)); + f16x8_t num = vsubq_n_f16(exp2x, 1.f16); + f16x8_t den = vaddq_n_f16(exp2x, 1.f16); + f16x8_t tanh = vmulq_f16(num, vrecip_f16(den)); + return tanh; +} + +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + + + +#ifdef __cplusplus +} +#endif + +#endif /* ARM FLOAT16 SUPPORTED */ + +#endif /* _ARM_VEC_MATH_F16_H */ + +/** + * + * End of file. + */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h new file mode 100755 index 0000000..30ad98d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h @@ -0,0 +1,880 @@ +/****************************************************************************** + * @file basic_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_H_ +#define _BASIC_MATH_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMath Basic Math Functions + */ + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f64( + const float64_t * pSrc, + float64_t scale, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_f64( +const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + +/** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result); + + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_f64( +const float64_t * pSrc, + float64_t offset, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_f64( +const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h new file mode 100755 index 0000000..92f11da --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h @@ -0,0 +1,168 @@ +/****************************************************************************** + * @file basic_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_F16_H_ +#define _BASIC_MATH_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f16( + const float16_t * pSrc, + float16_t scale, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result); + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples); + +#endif /* defined(ARM_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions.h new file mode 100755 index 0000000..0d6d58b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * @file bayes_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_H_ +#define _BAYES_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions_f16.h new file mode 100755 index 0000000..a16c49b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions_f16.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * @file bayes_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_F16_H_ +#define _BAYES_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float16_t *theta; /**< Mean values for the Gaussians */ + const float16_t *sigma; /**< Variances for the Gaussians */ + const float16_t *classPriors; /**< Class prior probabilities */ + float16_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f16; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h new file mode 100755 index 0000000..b4394de --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h @@ -0,0 +1,345 @@ +/****************************************************************************** + * @file complex_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_H_ +#define _COMPLEX_MATH_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + float64_t * pDst, + uint32_t numSamples); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h new file mode 100755 index 0000000..e0baa6f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h @@ -0,0 +1,123 @@ +/****************************************************************************** + * @file complex_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ +#define _COMPLEX_MATH_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h new file mode 100755 index 0000000..886a23c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h @@ -0,0 +1,793 @@ +/****************************************************************************** + * @file controller_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_H_ +#define _CONTROLLER_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + +#define CONTROLLER_Q31_SHIFT (32 - 9) + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @defgroup groupController Controller Functions + */ + + +/** + @ingroup groupController + */ + +/** + @defgroup SinCos Sine Cosine + + Computes the trigonometric sine and cosine values using a combination of table lookup + and linear interpolation. + There are separate functions for Q31 and floating-point data types. + The input to the floating-point version is in degrees while the + fixed-point Q31 have a scaled input with the range + [-1 0.9999] mapping to [-180 +180] degrees. + + The floating point function also allows values that are out of the usual range. When this happens, the function will + take extra time to adjust the input value to the range of [-180 180]. + + The result is accurate to 5 digits after the decimal point. + + The implementation is based on table lookup using 360 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index. + -# Compute the fractional portion (fract) of the input. + -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1. + -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)). + -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1. + -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)). + */ + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + +/** + @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + /** + * @ingroup PID + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */ + q15_t A2; /**< The derived gain A1 = Kd. */ +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @ingroup PID + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @ingroup PID + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + + + + /** + * @ingroup PID + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @ingroup PID + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @ingroup PID + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + + /** + * @ingroup park + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @ingroup park + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + + /** + * @ingroup inv_park + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @ingroup inv_park + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + +/** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + /** + * + * @ingroup clarke + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib); + } + + +/** + @ingroup clarke + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + + /** + * @ingroup inv_clarke + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @ingroup inv_clarke + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions_f16.h new file mode 100755 index 0000000..8fae483 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions_f16.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * @file controller_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_F16_H_ +#define _CONTROLLER_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/debug.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/debug.h new file mode 100644 index 0000000..6fb7183 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/debug.h @@ -0,0 +1,146 @@ +/****************************************************************************** + * @file basic_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DEBUG_FUNCTIONS_H_ +#define _DEBUG_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) +#define PROW_f16(S,NB) \ +{ \ + printf("{%f",(double)(S)[0]); \ + for(unsigned int i=1;i<(NB) ;i++) \ + { \ + printf(",%f",(double)(S)[i]);\ + } \ + printf("}"); \ +}; + +#define PV_f16(S,V,NB)\ +{ \ + printf("%s=",(S)); \ + PROW_f16((V),(NB)); \ + printf(";\n"); \ +}; + +#define PM_f16(S,M) \ +{ \ + printf("%s={",(S)); \ + for(unsigned int row=0;row<(M)->numRows;row++) \ + { \ + if (row != 0) \ + { \ + printf("\n,"); \ + } \ + PROW_f16((M)->pData + row * (M)->numCols, (M)->numCols);\ + } \ + printf("};\n"); \ +} + +#endif + +#define PROW_f32(S,NB) \ +{ \ + printf("{%f",(double)(S)[0]); \ + for(unsigned int i=1;i<(NB) ;i++) \ + { \ + printf(",%f",(double)(S)[i]);\ + } \ + printf("}"); \ +}; + +#define PV_f32(S,V,NB)\ +{ \ + printf("%s=",(S)); \ + PROW_f32((V),(NB)); \ + printf(";\n"); \ +}; + +#define PM_f32(S,M) \ +{ \ + printf("%s={",(S)); \ + for(unsigned int row=0;row<(M)->numRows;row++) \ + { \ + if (row != 0) \ + { \ + printf("\n,"); \ + } \ + PROW_f32((M)->pData + row * (M)->numCols, (M)->numCols);\ + } \ + printf("};\n"); \ +} + +#define PROW_f64(S,NB) \ +{ \ + printf("{%.20g",(double)(S)[0]); \ + for(unsigned int i=1;i<(NB) ;i++) \ + { \ + printf(",%.20g",(double)(S)[i]);\ + } \ + printf("}"); \ +}; + +#define PV_f64(S,V,NB) \ +{ \ + printf("%s=",(S)); \ + PROW_f64((V),(NB));\ + printf(";\n"); \ +}; + +#define PM_f64(S,M) \ +{ \ + printf("%s={",(S)); \ + for(unsigned int row=0;row<(M)->numRows;row++) \ + { \ + if (row != 0) \ + { \ + printf("\n,"); \ + } \ + PROW_f64((M)->pData + row * (M)->numCols, (M)->numCols);\ + } \ + printf("};\n"); \ +} + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DEBUG_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h new file mode 100755 index 0000000..a8cc19d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h @@ -0,0 +1,341 @@ +/****************************************************************************** + * @file distance_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_H_ +#define _DISTANCE_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) + +__attribute__((weak)) float __powisf2(float a, int b); + +#endif + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h new file mode 100755 index 0000000..46ad233 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h @@ -0,0 +1,180 @@ +/****************************************************************************** + * @file distance_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_F16_H_ +#define _DISTANCE_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) +/* Defined in minkowski_f32 */ +__attribute__((weak)) float __powisf2(float a, int b); +#endif + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize); + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h new file mode 100755 index 0000000..758b0fb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h @@ -0,0 +1,367 @@ +/****************************************************************************** + * @file fast_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_H_ +#define _FAST_MATH_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) + +#ifndef PI + #define PI 3.14159265358979f +#endif + + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief q31 vector of log values. + * @param[in] pSrc points to the input vector in q31 + * @param[out] pDst points to the output vector in q5.26 + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_vlog_q31(const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief q15 vector of log values. + * @param[in] pSrc points to the input vector in q15 + * @param[out] pDst points to the output vector in q4.11 + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_vlog_q15(const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + const float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + + + /** + * @} end of SQRT group + */ + + /** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift); + + /** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q31(q31_t numerator, + q31_t denominator, + q31_t *quotient, + int16_t *shift); + + + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + */ + arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result); + + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.29 + @return error status. + */ + arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result); + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.13 + @return error status. + */ + arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h new file mode 100755 index 0000000..c97ec64 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h @@ -0,0 +1,125 @@ +/****************************************************************************** + * @file fast_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_F16_H_ +#define _FAST_MATH_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +/* For sqrt_f32 */ +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f16( + float16_t in, + float16_t * pOut) + { + float32_t r; + arm_status status; + status=arm_sqrt_f32((float32_t)in,&r); + *pOut=(float16_t)r; + return(status); + } + + +/** + @} end of SQRT group + */ + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Floating-point vector of inverse values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + */ + arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h new file mode 100755 index 0000000..38a40ba --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h @@ -0,0 +1,2529 @@ +/****************************************************************************** + * @file filtering_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_H_ +#define _FILTERING_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) + +/** + * @defgroup groupFilters Filtering Functions + */ + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float64_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f64; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * + * For the MVE version, the coefficient length must be a multiple of 16. + * You can pad with zeros if you have less coefficients. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + * + * For the MVE version, the coefficient length must be a multiple of 8. + * You can pad with zeros if you have less coefficients. + * + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * + * For the MVE version, the coefficient length must be a multiple of 4. + * You can pad with zeros if you have less coefficients. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f64( + const arm_fir_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f64( + arm_fir_instance_f64 * S, + uint16_t numTaps, + const float64_t * pCoeffs, + float64_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +/** + @brief Compute new coefficient arrays for use in vectorized filter (Neon only). + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the original filter coefficients. + @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized version. + @return none +*/ +void arm_biquad_cascade_df2T_compute_coefs_f32( + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pComputedCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f64( + const float64_t * pSrcA, + uint32_t srcALen, + const float64_t * pSrcB, + uint32_t srcBLen, + float64_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + + + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h new file mode 100755 index 0000000..21f33f4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h @@ -0,0 +1,237 @@ +/****************************************************************************** + * @file filtering_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_F16_H_ +#define _FILTERING_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f16; + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f16( + arm_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f16( + const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f16; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float16_t coeffs[12][8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f16; +#endif + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + arm_biquad_mod_coef_f16 * pCoeffsMod, + float16_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f16; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f16; + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f16( + arm_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f16( + arm_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h new file mode 100755 index 0000000..a650fe8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file interpolation_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_H_ +#define _INTERPOLATION_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x); + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t arm_linear_interp_q31( + const q31_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t arm_linear_interp_q15( + const q15_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +q7_t arm_linear_interp_q7( + const q7_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y); + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y); + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y); + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h new file mode 100755 index 0000000..227ecb0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h @@ -0,0 +1,107 @@ +/****************************************************************************** + * @file interpolation_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_F16_H_ +#define _INTERPOLATION_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +typedef struct +{ + uint32_t nValues; /**< nValues */ + float16_t x1; /**< x1 */ + float16_t xSpacing; /**< xSpacing */ + float16_t *pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f16; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct +{ + uint16_t numRows;/**< number of rows in the data table. */ + uint16_t numCols;/**< number of columns in the data table. */ + float16_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f16; + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t arm_linear_interp_f16( + arm_linear_interp_instance_f16 * S, + float16_t x); + + /** + * @} end of LinearInterpolate group + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t arm_bilinear_interp_f16( + const arm_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y); + + + /** + * @} end of BilinearInterpolate group + */ +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h new file mode 100755 index 0000000..9bab8e6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h @@ -0,0 +1,842 @@ +/****************************************************************************** + * @file matrix_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_H_ +#define _MATRIX_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + + #define DEFAULT_HOUSEHOLDER_THRESHOLD_F64 (1.0e-16) + #define DEFAULT_HOUSEHOLDER_THRESHOLD_F32 (1.0e-12f) + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q7 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q7_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q7; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q15 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q7 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q7( + const arm_matrix_instance_q7 * pSrc, + arm_matrix_instance_q7 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_f32( + const arm_matrix_instance_f32 *pSrcMat, + const float32_t *pVec, + float32_t *pDst); + + /** + * @brief Q7 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q7( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst, + q7_t * pState); + + /** + * @brief Q7 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q7( + const arm_matrix_instance_q7 *pSrcMat, + const q7_t *pVec, + q7_t *pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q15( + const arm_matrix_instance_q15 *pSrcMat, + const q15_t *pVec, + q15_t *pDst); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState); + + /** + * @brief Q31 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q31( + const arm_matrix_instance_q31 *pSrcMat, + const q31_t *pVec, + q31_t *pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f64( + const arm_matrix_instance_f64 * ut, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f64( + const arm_matrix_instance_f64 * lt, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst); + + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * l, + arm_matrix_instance_f32 * d, + uint16_t * pp); + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_ldlt_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * l, + arm_matrix_instance_f64 * d, + uint16_t * pp); + +/** + @brief QR decomposition of a m x n floating point matrix with m >= n. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[in] threshold norm2 threshold. + @param[out] pOutR points to output R matrix structure of dimension m x n + @param[out] pOutQ points to output Q matrix structure of dimension m x m + @param[out] pOutTau points to Householder scaling factors of dimension n + @param[inout] pTmpA points to a temporary vector of dimension m. + @param[inout] pTmpB points to a temporary vector of dimension n. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +arm_status arm_mat_qr_f32( + const arm_matrix_instance_f32 * pSrc, + const float32_t threshold, + arm_matrix_instance_f32 * pOutR, + arm_matrix_instance_f32 * pOutQ, + float32_t * pOutTau, + float32_t *pTmpA, + float32_t *pTmpB + ); + +/** + @brief QR decomposition of a m x n floating point matrix with m >= n. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[in] threshold norm2 threshold. + @param[out] pOutR points to output R matrix structure of dimension m x n + @param[out] pOutQ points to output Q matrix structure of dimension m x m + @param[out] pOutTau points to Householder scaling factors of dimension n + @param[inout] pTmpA points to a temporary vector of dimension m. + @param[inout] pTmpB points to a temporary vector of dimension n. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +arm_status arm_mat_qr_f64( + const arm_matrix_instance_f64 * pSrc, + const float64_t threshold, + arm_matrix_instance_f64 * pOutR, + arm_matrix_instance_f64 * pOutQ, + float64_t * pOutTau, + float64_t *pTmpA, + float64_t *pTmpB + ); + +/** + @brief Householder transform of a floating point vector. + @param[in] pSrc points to the input vector. + @param[in] threshold norm2 threshold. + @param[in] blockSize dimension of the vector space. + @param[outQ] pOut points to the output vector. + @return beta return the scaling factor beta + */ + +float32_t arm_householder_f32( + const float32_t * pSrc, + const float32_t threshold, + uint32_t blockSize, + float32_t * pOut + ); + +/** + @brief Householder transform of a double floating point vector. + @param[in] pSrc points to the input vector. + @param[in] threshold norm2 threshold. + @param[in] blockSize dimension of the vector space. + @param[outQ] pOut points to the output vector. + @return beta return the scaling factor beta + */ + +float64_t arm_householder_f64( + const float64_t * pSrc, + const float64_t threshold, + uint32_t blockSize, + float64_t * pOut + ); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h new file mode 100755 index 0000000..3f54651 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h @@ -0,0 +1,263 @@ +/****************************************************************************** + * @file matrix_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_F16_H_ +#define _MATRIX_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + #define DEFAULT_HOUSEHOLDER_THRESHOLD_F16 (1.0e-3f) + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float16_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f16; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_f16( + const arm_matrix_instance_f16 *pSrcMat, + const float16_t *pVec, + float16_t *pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f16( + arm_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * src, + arm_matrix_instance_f16 * dst); + + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * src, + arm_matrix_instance_f16 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst); + + +/** + @brief QR decomposition of a m x n floating point matrix with m >= n. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[in] threshold norm2 threshold. + @param[out] pOutR points to output R matrix structure of dimension m x n + @param[out] pOutQ points to output Q matrix structure of dimension m x m + @param[out] pOutTau points to Householder scaling factors of dimension n + @param[inout] pTmpA points to a temporary vector of dimension m. + @param[inout] pTmpB points to a temporary vector of dimension n. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +arm_status arm_mat_qr_f16( + const arm_matrix_instance_f16 * pSrc, + const float16_t threshold, + arm_matrix_instance_f16 * pOutR, + arm_matrix_instance_f16 * pOutQ, + float16_t * pOutTau, + float16_t *pTmpA, + float16_t *pTmpB + ); + +/** + @brief Householder transform of a half floating point vector. + @param[in] pSrc points to the input vector. + @param[in] threshold norm2 threshold. + @param[in] blockSize dimension of the vector space. + @param[outQ] pOut points to the output vector. + @return beta return the scaling factor beta + */ + +float16_t arm_householder_f16( + const float16_t * pSrc, + const float16_t threshold, + uint32_t blockSize, + float16_t * pOut + ); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h new file mode 100755 index 0000000..5b0f55d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h @@ -0,0 +1,640 @@ +/****************************************************************************** + * @file matrix_utils.h + * @brief Public header file for CMSIS DSP Library + * @version V1.11.0 + * @date 30 May 2022 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_UTILS_H_ +#define _MATRIX_UTILS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define ELEM(A,ROW,COL) &((A)->pData[(A)->numCols* (ROW) + (COL)]) + +#define SCALE_COL_T(T,CAST,A,ROW,v,i) \ +{ \ + int32_t w; \ + T *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + const int32_t nb = (A)->numRows - ROW;\ + \ + data += i + numCols * (ROW); \ + \ + for(w=0;w < nb; w++) \ + { \ + *data *= CAST v; \ + data += numCols; \ + } \ +} + +#define COPY_COL_T(T,A,ROW,COL,DST) \ +{ \ + uint32_t row; \ + T *pb=DST; \ + T *pa = (A)->pData + ROW * (A)->numCols + COL;\ + for(row = ROW; row < (A)->numRows; row ++) \ + { \ + *pb++ = *pa; \ + pa += (A)->numCols; \ + } \ +} + +#if defined(ARM_FLOAT16_SUPPORTED) +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define SWAP_ROWS_F16(A,COL,i,j) \ + { \ + int cnt = ((A)->numCols)-(COL); \ + int32_t w; \ + float16_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + \ + for(w=(COL);w < numCols; w+=8) \ + { \ + f16x8_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp16q(cnt); \ + \ + tmpa=vldrhq_z_f16(&data[i*numCols + w],p0);\ + tmpb=vldrhq_z_f16(&data[j*numCols + w],p0);\ + \ + vstrhq_p(&data[i*numCols + w], tmpb, p0); \ + vstrhq_p(&data[j*numCols + w], tmpa, p0); \ + \ + cnt -= 8; \ + } \ + } + +#define SCALE_ROW_F16(A,COL,v,i) \ +{ \ + int cnt = ((A)->numCols)-(COL); \ + int32_t w; \ + float16_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + \ + for(w=(COL);w < numCols; w+=8) \ + { \ + f16x8_t tmpa; \ + mve_pred16_t p0 = vctp16q(cnt); \ + tmpa = vldrhq_z_f16(&data[i*numCols + w],p0);\ + tmpa = vmulq_n_f16(tmpa,(_Float16)v); \ + vstrhq_p(&data[i*numCols + w], tmpa, p0); \ + cnt -= 8; \ + } \ + \ +} + +#define MAC_ROW_F16(COL,A,i,v,B,j) \ +{ \ + int cnt = ((A)->numCols)-(COL); \ + int32_t w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols; \ + \ + for(w=(COL);w < numCols; w+=8) \ + { \ + f16x8_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp16q(cnt); \ + tmpa = vldrhq_z_f16(&dataA[i*numCols + w],p0);\ + tmpb = vldrhq_z_f16(&dataB[j*numCols + w],p0);\ + tmpa = vfmaq_n_f16(tmpa,tmpb,v); \ + vstrhq_p(&dataA[i*numCols + w], tmpa, p0); \ + cnt -= 8; \ + } \ + \ +} + +#define MAS_ROW_F16(COL,A,i,v,B,j) \ +{ \ + int cnt = ((A)->numCols)-(COL); \ + int32_t w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols; \ + f16x8_t vec=vdupq_n_f16(v); \ + \ + for(w=(COL);w < numCols; w+=8) \ + { \ + f16x8_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp16q(cnt); \ + tmpa = vldrhq_z_f16(&dataA[i*numCols + w],p0);\ + tmpb = vldrhq_z_f16(&dataB[j*numCols + w],p0);\ + tmpa = vfmsq_f16(tmpa,tmpb,vec); \ + vstrhq_p(&dataA[i*numCols + w], tmpa, p0); \ + cnt -= 8; \ + } \ + \ +} + +#else + + +#define SWAP_ROWS_F16(A,COL,i,j) \ +{ \ + int32_t w; \ + float16_t *dataI = (A)->pData; \ + float16_t *dataJ = (A)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + dataI += i*numCols + (COL); \ + dataJ += j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + float16_t tmp; \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ +} + +#define SCALE_ROW_F16(A,COL,v,i) \ +{ \ + int32_t w; \ + float16_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + data += i*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *data++ *= (_Float16)v; \ + } \ +} + + +#define MAC_ROW_F16(COL,A,i,v,B,j) \ +{ \ + int32_t w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols; \ + const int32_t nb = numCols-(COL); \ + \ + dataA += i*numCols + (COL); \ + dataB += j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *dataA++ += (_Float16)v * (_Float16)*dataB++;\ + } \ +} + +#define MAS_ROW_F16(COL,A,i,v,B,j) \ +{ \ + int32_t w; \ + float16_t *dataA = (A)->pData; \ + float16_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols; \ + const int32_t nb = numCols-(COL); \ + \ + dataA += i*numCols + (COL); \ + dataB += j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *dataA++ -= (_Float16)v * (_Float16)*dataB++;\ + } \ +} + +#endif /*defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +/* Functions with only a scalar version */ +#define COPY_COL_F16(A,ROW,COL,DST) \ + COPY_COL_T(float16_t,A,ROW,COL,DST) + +#define SCALE_COL_F16(A,ROW,v,i) \ + SCALE_COL_T(float16_t,(_Float16),A,ROW,v,i) + +#endif /* defined(ARM_FLOAT16_SUPPORTED)*/ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define SWAP_ROWS_F32(A,COL,i,j) \ + { \ + int cnt = ((A)->numCols)-(COL); \ + float32_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + int32_t w; \ + \ + for(w=(COL);w < numCols; w+=4) \ + { \ + f32x4_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + \ + tmpa=vldrwq_z_f32(&data[i*numCols + w],p0);\ + tmpb=vldrwq_z_f32(&data[j*numCols + w],p0);\ + \ + vstrwq_p(&data[i*numCols + w], tmpb, p0); \ + vstrwq_p(&data[j*numCols + w], tmpa, p0); \ + \ + cnt -= 4; \ + } \ + } + +#define MAC_ROW_F32(COL,A,i,v,B,j) \ +{ \ + int cnt = ((A)->numCols)-(COL); \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols; \ + int32_t w; \ + \ + for(w=(COL);w < numCols; w+=4) \ + { \ + f32x4_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + tmpa = vldrwq_z_f32(&dataA[i*numCols + w],p0);\ + tmpb = vldrwq_z_f32(&dataB[j*numCols + w],p0);\ + tmpa = vfmaq_n_f32(tmpa,tmpb,v); \ + vstrwq_p(&dataA[i*numCols + w], tmpa, p0); \ + cnt -= 4; \ + } \ + \ +} + +#define MAS_ROW_F32(COL,A,i,v,B,j) \ +{ \ + int cnt = ((A)->numCols)-(COL); \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols; \ + int32_t w; \ + f32x4_t vec=vdupq_n_f32(v); \ + \ + for(w=(COL);w < numCols; w+=4) \ + { \ + f32x4_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + tmpa = vldrwq_z_f32(&dataA[i*numCols + w],p0);\ + tmpb = vldrwq_z_f32(&dataB[j*numCols + w],p0);\ + tmpa = vfmsq_f32(tmpa,tmpb,vec); \ + vstrwq_p(&dataA[i*numCols + w], tmpa, p0); \ + cnt -= 4; \ + } \ + \ +} + +#define SCALE_ROW_F32(A,COL,v,i) \ +{ \ + int cnt = ((A)->numCols)-(COL); \ + float32_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + int32_t w; \ + \ + for(w=(COL);w < numCols; w+=4) \ + { \ + f32x4_t tmpa; \ + mve_pred16_t p0 = vctp32q(cnt); \ + tmpa = vldrwq_z_f32(&data[i*numCols + w],p0);\ + tmpa = vmulq_n_f32(tmpa,v); \ + vstrwq_p(&data[i*numCols + w], tmpa, p0); \ + cnt -= 4; \ + } \ + \ +} + +#elif defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define SWAP_ROWS_F32(A,COL,i,j) \ +{ \ + int32_t w; \ + float32_t *dataI = (A)->pData; \ + float32_t *dataJ = (A)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols - COL; \ + \ + dataI += i*numCols + (COL); \ + dataJ += j*numCols + (COL); \ + \ + float32_t tmp; \ + \ + for(w=0;w < nb; w++) \ + { \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ +} + +#define MAC_ROW_F32(COL,A,i,v,B,j) \ +{ \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols - (COL); \ + int32_t nbElems; \ + f32x4_t vec = vdupq_n_f32(v); \ + \ + nbElems = nb >> 2; \ + \ + dataA += i*numCols + (COL); \ + dataB += j*numCols + (COL); \ + \ + while(nbElems>0) \ + { \ + f32x4_t tmpa,tmpb; \ + tmpa = vld1q_f32(dataA,p0); \ + tmpb = vld1q_f32(dataB,p0); \ + tmpa = vmlaq_f32(tmpa,tmpb,vec);\ + vst1q_f32(dataA, tmpa, p0); \ + nbElems--; \ + dataA += 4; \ + dataB += 4; \ + } \ + \ + nbElems = nb & 3; \ + while(nbElems > 0) \ + { \ + *dataA++ += v* *dataB++; \ + nbElems--; \ + } \ +} + +#define MAS_ROW_F32(COL,A,i,v,B,j) \ +{ \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols - (COL); \ + int32_t nbElems; \ + f32x4_t vec = vdupq_n_f32(v); \ + \ + nbElems = nb >> 2; \ + \ + dataA += i*numCols + (COL); \ + dataB += j*numCols + (COL); \ + \ + while(nbElems>0) \ + { \ + f32x4_t tmpa,tmpb; \ + tmpa = vld1q_f32(dataA); \ + tmpb = vld1q_f32(dataB); \ + tmpa = vmlsq_f32(tmpa,tmpb,vec);\ + vst1q_f32(dataA, tmpa); \ + nbElems--; \ + dataA += 4; \ + dataB += 4; \ + } \ + \ + nbElems = nb & 3; \ + while(nbElems > 0) \ + { \ + *dataA++ -= v* *dataB++; \ + nbElems--; \ + } \ +} + +#define SCALE_ROW_F32(A,COL,v,i) \ +{ \ + float32_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + const int32_t nb = numCols - (COL); \ + int32_t nbElems; \ + f32x4_t vec = vdupq_n_f32(v); \ + \ + nbElems = nb >> 2; \ + \ + data += i*numCols + (COL); \ + while(nbElems>0) \ + { \ + f32x4_t tmpa; \ + tmpa = vld1q_f32(data); \ + tmpa = vmulq_f32(tmpa,vec); \ + vst1q_f32(data, tmpa); \ + data += 4; \ + nbElems --; \ + } \ + \ + nbElems = nb & 3; \ + while(nbElems > 0) \ + { \ + *data++ *= v; \ + nbElems--; \ + } \ + \ +} + +#else + +#define SWAP_ROWS_F32(A,COL,i,j) \ +{ \ + int32_t w; \ + float32_t tmp; \ + float32_t *dataI = (A)->pData; \ + float32_t *dataJ = (A)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols - COL; \ + \ + dataI += i*numCols + (COL); \ + dataJ += j*numCols + (COL); \ + \ + \ + for(w=0;w < nb; w++) \ + { \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ +} + +#define SCALE_ROW_F32(A,COL,v,i) \ +{ \ + int32_t w; \ + float32_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols - COL; \ + \ + data += i*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *data++ *= v; \ + } \ +} + + +#define MAC_ROW_F32(COL,A,i,v,B,j) \ +{ \ + int32_t w; \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + dataA = dataA + i*numCols + (COL); \ + dataB = dataB + j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *dataA++ += v* *dataB++; \ + } \ +} + +#define MAS_ROW_F32(COL,A,i,v,B,j) \ +{ \ + int32_t w; \ + float32_t *dataA = (A)->pData; \ + float32_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + dataA = dataA + i*numCols + (COL); \ + dataB = dataB + j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *dataA++ -= v* *dataB++; \ + } \ +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/* Functions with only a scalar version */ + +#define COPY_COL_F32(A,ROW,COL,DST) \ + COPY_COL_T(float32_t,A,ROW,COL,DST) + +#define COPY_COL_F64(A,ROW,COL,DST) \ + COPY_COL_T(float64_t,A,ROW,COL,DST) + +#define SWAP_COLS_F32(A,COL,i,j) \ +{ \ + int32_t w; \ + float32_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + for(w=(COL);w < numCols; w++) \ + { \ + float32_t tmp; \ + tmp = data[w*numCols + i]; \ + data[w*numCols + i] = data[w*numCols + j];\ + data[w*numCols + j] = tmp; \ + } \ +} + +#define SCALE_COL_F32(A,ROW,v,i) \ + SCALE_COL_T(float32_t,,A,ROW,v,i) + +#define SWAP_ROWS_F64(A,COL,i,j) \ +{ \ + int32_t w; \ + float64_t *dataI = (A)->pData; \ + float64_t *dataJ = (A)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + dataI += i*numCols + (COL); \ + dataJ += j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + float64_t tmp; \ + tmp = *dataI; \ + *dataI++ = *dataJ; \ + *dataJ++ = tmp; \ + } \ +} + +#define SWAP_COLS_F64(A,COL,i,j) \ +{ \ + int32_t w; \ + float64_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols; \ + for(w=(COL);w < numCols; w++) \ + { \ + float64_t tmp; \ + tmp = data[w*numCols + i]; \ + data[w*numCols + i] = data[w*numCols + j];\ + data[w*numCols + j] = tmp; \ + } \ +} + +#define SCALE_ROW_F64(A,COL,v,i) \ +{ \ + int32_t w; \ + float64_t *data = (A)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + data += i*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *data++ *= v; \ + } \ +} + +#define SCALE_COL_F64(A,ROW,v,i) \ + SCALE_COL_T(float64_t,,A,ROW,v,i) + +#define MAC_ROW_F64(COL,A,i,v,B,j) \ +{ \ + int32_t w; \ + float64_t *dataA = (A)->pData; \ + float64_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + dataA += i*numCols + (COL); \ + dataB += j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *dataA++ += v* *dataB++; \ + } \ +} + +#define MAS_ROW_F64(COL,A,i,v,B,j) \ +{ \ + int32_t w; \ + float64_t *dataA = (A)->pData; \ + float64_t *dataB = (B)->pData; \ + const int32_t numCols = (A)->numCols;\ + const int32_t nb = numCols-(COL); \ + \ + dataA += i*numCols + (COL); \ + dataB += j*numCols + (COL); \ + \ + for(w=0;w < nb; w++) \ + { \ + *dataA++ -= v* *dataB++; \ + } \ +} + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_UTILS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h new file mode 100755 index 0000000..1e36a51 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h @@ -0,0 +1,631 @@ +/****************************************************************************** + * @file none.h + * @brief Intrinsincs when no DSP extension available + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + +Definitions in this file are allowing to reuse some versions of the +CMSIS-DSP to build on a core (M0 for instance) or a host where +DSP extension are not available. + +Ideally a pure C version should have been used instead. +But those are not always available or use a restricted set +of intrinsics. + +*/ + +#ifndef _NONE_H_ +#define _NONE_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } + + /** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +#endif + +/** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +// Patched by Edge Impulse, don't redefine these macros on Arm cores +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + + #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + + /* + * @brief C custom defined SADD16 (by Edge Impulse) + */ + __STATIC_FORCEINLINE uint32_t __SADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16))) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16))) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } +// Patched by Edge Impulse, don't redefine these macros on Arm cores +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + + +// Patched by Edge Impulse, remove `!defined (ARM_MATH_DSP)` check +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) || defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__) + // Rotate right, dual extract 8-bits and sign extend each to 16-bits. + // rotate value must be 8,16 or 24 + // Patched by Edge Impulse to polyfill x86 support + // Patched by Edge Impulse for IAR Workbench + __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t val1, uint32_t rotate) + { + uint32_t ret; + int8_t a, b; + int16_t a16, b16; + a = (int8_t)((val1 >> rotate) & 0xff); + rotate = (rotate + 16) & 31; // to extract second byte + b = (int8_t)((val1 >> rotate) & 0xff); + a16 = a; b16 = b; // sign extend + ret = (b16 << 16); + ret |= ((uint32_t)a16 & 0xffff); + return ret; + } +#endif + // Dual sign-extended 8 to 16-bit addition + // Patched by Edge Impulse to polyfill x86 support + __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t val1, uint32_t val2) + { + int8_t a, b; + int16_t a16, b16; + uint32_t ret; + a16 = (int16_t)(val1); + b16 = (int16_t)(val1 >> 16); + a = (int8_t)(val2 & 0xff); // bits 0-7 + b = (int8_t)((val2 >> 16) & 0xff); + a16 += a; + b16 += b; + ret = (b16 << 16); + ret |= ((uint32_t)a16 & 0xffff); + return ret; + } + +#endif /* !defined (ARM_MATH_DSP) || defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) */ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h new file mode 100755 index 0000000..8192cd8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h @@ -0,0 +1,159 @@ +/****************************************************************************** + * @file quaternion_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _QUATERNION_MATH_FUNCTIONS_H_ +#define _QUATERNION_MATH_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupQuaternionMath Quaternion Math Functions + * Functions to operates on quaternions and convert between a + * rotation and quaternion representation. + */ + + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions); + + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void arm_quaternion_normalize_f32(const float32_t *inputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions); + + +/** + @brief Floating-point product of two quaternions. + @param[in] qa First quaternion + @param[in] qb Second quaternion + @param[out] r Product of two quaternions + @return none + */ +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r); + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa First array of quaternions + @param[in] qb Second array of quaternions + @param[out] r Elementwise product of quaternions + @param[in] nbQuaternions Number of quaternions in the array + @return none + */ +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r, + uint32_t nbQuaternions); + +/** + * @brief Conversion of quaternion to equivalent rotation matrix. + * @param[in] pInputQuaternions points to an array of normalized quaternions + * @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + * @param[in] nbQuaternions in the array + * @return none. + * + * Format of rotation matrix + * \par + * The quaternion a + ib + jc + kd is converted into rotation matrix: + * a^2 + b^2 - c^2 - d^2 2bc - 2ad 2bd + 2ac + * 2bc + 2ad a^2 - b^2 + c^2 - d^2 2cd - 2ab + * 2bd - 2ac 2cd + 2ab a^2 - b^2 - c^2 + d^2 + * + * Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions); + +/** + * @brief Conversion of a rotation matrix to equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array of quaternions + * @param[in] nbQuaternions in the array + * @return none. +*/ +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _QUATERNION_MATH_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h new file mode 100755 index 0000000..866e467 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h @@ -0,0 +1,1003 @@ +/****************************************************************************** + * @file statistics_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.1 + * @date 14 July 2022 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_H_ +#define _STATISTICS_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of absolute values of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of absolute values of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + */ + void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Minimum value of absolute values of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult); + + /** + @brief Maximum value of a q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q31( + const q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + /** + @brief Maximum value of a q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q15( + const q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + /** + @brief Maximum value of a q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); + + /** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult); + +/** + @brief Minimum value of a q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q31( + const q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + /** + @brief Minimum value of a q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q15( + const q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + /** + @brief Minimum value of a q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); + +/** + @brief Mean square error between two Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult); + +/** + @brief Mean square error between two Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult); + +/** + @brief Mean square error between two Q31 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult); + +/** + @brief Mean square error between two single precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * pResult); + +/** + @brief Mean square error between two double precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * pResult); + + +/** + * @brief Accumulation value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + +void arm_accumulate_f32( +const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +/** + * @brief Accumulation value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + +void arm_accumulate_f64( +const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h new file mode 100755 index 0000000..a3db3ee --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h @@ -0,0 +1,279 @@ +/****************************************************************************** + * @file statistics_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.1 + * @date 14 July 2022 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_F16_H_ +#define _STATISTICS_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize); + +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer); + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA + ,const float16_t * pSrcB + ,uint32_t blockSize); + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult); + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult); + +/** + @brief Mean square error between two half precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * pResult); + + +/** + * @brief Sum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_accumulate_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h new file mode 100755 index 0000000..7b586e3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h @@ -0,0 +1,453 @@ +/****************************************************************************** + * @file support_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_H_ +#define _SUPPORT_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupSupport Support Functions + */ + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f64( + float64_t value, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + + + + + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h new file mode 100755 index 0000000..f36d06f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h @@ -0,0 +1,187 @@ +/****************************************************************************** + * @file support_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_F16_H_ +#define _SUPPORT_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize); + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + */ +void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the q15 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f32 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the f32 output vector + * @param[in] blockSize length of the input vector + */ +void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize); + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float16_t arm_weighted_sum_f16(const float16_t *in + , const float16_t *weigths + , uint32_t blockSize); + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f16(const float16_t *in + , const float16_t *weights + , float16_t *out + , uint32_t nbVectors + , uint32_t vecDim); + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup typecast Typecasting + */ + +/** + @addtogroup typecast + @{ + */ + +/** + * @brief Interpret a f16 as an s16 value + * @param[in] x input value. + * @return return value. + * + * @par Description + * It is a typecast. No conversion of the float to int is done. + * The memcpy will be optimized out by the compiler. + * memcpy is used to prevent type punning issues. + * With gcc, -fno-builtins MUST not be used or the + * memcpy will not be optimized out. + */ +__STATIC_INLINE int16_t arm_typecast_s16_f16(float16_t x) +{ + int16_t res; + res=*(int16_t*)memcpy((char*)&res,(char*)&x,sizeof(float16_t)); + return(res); +} + +/** + * @brief Interpret an s16 as an f16 value + * @param[in] x input value. + * @return return value. + * + * @par Description + * It is a typecast. No conversion of the int to float is done. + * The memcpy will be optimized out by the compiler. + * memcpy is used to prevent type punning issues. + * With gcc, -fno-builtins MUST not be used or the + * memcpy will not be optimized out. + */ +__STATIC_INLINE float16_t arm_typecast_f16_s16(int16_t x) +{ + float16_t res; + res=*(float16_t*)memcpy((char*)&res,(char*)&x,sizeof(int16_t)); + return(res); +} + + +/** + @} end of typecast group + */ + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_defines.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_defines.h new file mode 100755 index 0000000..f93e953 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_defines.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * @file svm_defines.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_DEFINES_H_ +#define _SVM_DEFINES_H_ + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h new file mode 100755 index 0000000..6576c93 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h @@ -0,0 +1,299 @@ +/****************************************************************************** + * @file svm_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_H_ +#define _SVM_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_defines.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + + + + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independent constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h new file mode 100755 index 0000000..67c97aa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h @@ -0,0 +1,281 @@ +/****************************************************************************** + * @file svm_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_F16_H_ +#define _SVM_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_defines.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f16; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float16_t coef0; /**< Polynomial constant */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f16; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f16; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t coef0; /**< Independent constant */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f16; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h new file mode 100755 index 0000000..2722620 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h @@ -0,0 +1,751 @@ +/****************************************************************************** + * @file transform_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_H_ +#define _TRANSFORM_FUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupTransforms Transform Functions + */ + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + arm_status arm_cfft_init_f64( + arm_cfft_instance_f64 * S, + uint16_t fftLen); + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + + // Patched by Edge Impulse, expose the specific init functions to the outside world + arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + arm_status arm_rfft_32_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + arm_status arm_rfft_64_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + arm_status arm_rfft_128_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + arm_status arm_rfft_256_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + arm_status arm_rfft_512_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + arm_status arm_rfft_1024_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + arm_status arm_rfft_2048_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + arm_status arm_rfft_4096_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S); + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Instance structure for the Floating-point MFCC function. + */ +typedef struct + { + const float32_t *dctCoefs; /**< Internal DCT coefficients */ + const float32_t *filterCoefs; /**< Internal Mel filter coefficients */ + const float32_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_f32 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_fast_instance_f32 rfft; +#endif + } arm_mfcc_instance_f32 ; + +arm_status arm_mfcc_init_f32( + arm_mfcc_instance_f32 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float32_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float32_t *filterCoefs, + const float32_t *windowCoefs + ); + + +/** + @brief MFCC F32 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + void arm_mfcc_f32( + const arm_mfcc_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pTmp + ); + +typedef struct + { + const q31_t *dctCoefs; /**< Internal DCT coefficients */ + const q31_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q31_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q31 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q31 rfft; +#endif + } arm_mfcc_instance_q31 ; + +arm_status arm_mfcc_init_q31( + arm_mfcc_instance_q31 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q31_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q31_t *filterCoefs, + const q31_t *windowCoefs + ); + + +/** + @brief MFCC Q31 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + arm_status arm_mfcc_q31( + const arm_mfcc_instance_q31 * S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pTmp + ); + +typedef struct + { + const q15_t *dctCoefs; /**< Internal DCT coefficients */ + const q15_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q15_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q15 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q15 rfft; +#endif + } arm_mfcc_instance_q15 ; + +arm_status arm_mfcc_init_q15( + arm_mfcc_instance_q15 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q15_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q15_t *filterCoefs, + const q15_t *windowCoefs + ); + + +/** + @brief MFCC Q15 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values in q8.7 format + @param[inout] pTmp points to a temporary buffer of complex + @return error status + */ + arm_status arm_mfcc_q15( + const arm_mfcc_instance_q15 * S, + q15_t *pSrc, + q15_t *pDst, + q31_t *pTmp + ); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h new file mode 100755 index 0000000..b38a587 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h @@ -0,0 +1,208 @@ +/****************************************************************************** + * @file transform_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_F16_H_ +#define _TRANSFORM_FUNCTIONS_F16_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_memory.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#if defined(ARM_FLOAT16_SUPPORTED) + + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float16_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f16; + + + arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen); + + void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f16 ; + +arm_status arm_rfft_fast_init_f16 ( + arm_rfft_fast_instance_f16 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, float16_t * pOut, + uint8_t ifftFlag); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f16( + arm_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f16( + const arm_cfft_radix4_instance_f16 * S, + float16_t * pSrc); + + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f16( + arm_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f16( + const arm_cfft_radix2_instance_f16 * S, + float16_t * pSrc); + + /** + * @brief Instance structure for the Floating-point MFCC function. + */ +typedef struct + { + const float16_t *dctCoefs; /**< Internal DCT coefficients */ + const float16_t *filterCoefs; /**< Internal Mel filter coefficients */ + const float16_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_f16 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_fast_instance_f16 rfft; +#endif + } arm_mfcc_instance_f16 ; + +arm_status arm_mfcc_init_f16( + arm_mfcc_instance_f16 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float16_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float16_t *filterCoefs, + const float16_t *windowCoefs + ); + + +/** + @brief MFCC F16 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + void arm_mfcc_f16( + const arm_mfcc_instance_f16 * S, + float16_t *pSrc, + float16_t *pDst, + float16_t *pTmp + ); + + +#endif /* defined(ARM_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_F16_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h new file mode 100755 index 0000000..e6e24df --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h @@ -0,0 +1,250 @@ +/****************************************************************************** + * @file arm_math_utils.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_UTILS_H_ + +#define _ARM_MATH_UTILS_H_ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define INDEX_MASK 0x0000003F + + +#define SQ(x) ((x) * (x)) + +#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S)) + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + It should not be used with negative values. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( (uint32_t)in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ((uint32_t)(-in)) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + It should not be used with negative values. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + int32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( (uint32_t)in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ((uint32_t)(-in)) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (q15_t)(in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ((uint32_t)hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ((uint32_t)lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (int32_t)(((uint32_t)lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE int32_t arm_div_int64_to_int32(int64_t num, int32_t den) +{ + int32_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + if (num == (int64_t)LONG_MIN) + { + absNum = LONG_MAX; + } + else + { + absNum = (uint64_t) (num > 0 ? num : -num); + } + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (int32_t) num / den; + else + /* + * 64-bit division + */ + result = (int32_t) (num / den); + + return result; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_UTILS_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/PrivateInclude/README.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/PrivateInclude/README.md new file mode 100644 index 0000000..77d2039 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/PrivateInclude/README.md @@ -0,0 +1 @@ +Note: All files have been moved from this folder into Include to simplify build management diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c new file mode 100644 index 0000000..e974c82 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c @@ -0,0 +1,189 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f16.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" +#include + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f16x8_t vec1; + f16x8_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vabsq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrc); + vstrhq_p(pDst, vabsq(vec1), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q_f16(pSrc); + res = vabsq_f16(vec1); + vst1q_f16(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicAbs group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 0000000..3d27210 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,200 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f32.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + + 
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f32x4_t vec1; + f32x4_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vabsq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrc); + vstrwq_p(pDst, vabsq(vec1), p0); + } + +} + +#else +void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vabsq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicAbs group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c new file mode 100644 index 0000000..a0bd5f0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c @@ -0,0 +1,78 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f64.c + * Description: Floating-point vector absolute value + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_abs_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabs(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 0000000..7c8ec53 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,182 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q15.c + * Description: Q15 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q15 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicAbs group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 0000000..fab95f2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,212 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q31.c + * Description: Q31 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q31 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * Tail + */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined(ARM_MATH_NEON) + int32x4_t vec1; + int32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + + vec1 = vld1q_s32(pSrc); + res = vqabsq_s32(vec1); + vst1q_s32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined (ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined (ARM_MATH_MVEI) */ +/** + @} end of BasicAbs group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 0000000..f62d67a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,184 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q7.c + * Description: Q7 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q7 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t) __QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicAbs group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c new file mode 100644 index 0000000..d9d6226 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c @@ -0,0 +1,162 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vaddq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vaddq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 0000000..4e854f5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,203 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + + 
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vaddq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vaddq(vec1,vec2), p0); + } + +} + +#else +void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c new file mode 100644 index 0000000..a1f01a7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f64.c + * Description: Floating-point vector addition + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_add_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 0000000..6265058 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,180 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q15.c + * Description: Q15 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q15 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqaddq(vecA, vecB), p0); + } +} + +#else +void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + inB2 = read_q15x2_ia (&pSrcB); + + /* Add and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QADD16(inA1, inB1)); + write_q15x2_ia (&pDst, __QADD16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 0000000..2d6e791 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,163 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q31.c + * Description: Q31 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q31 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecA; + q31x4_t vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqaddq(vecA, vecB), p0); + } +} + +#else +void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 0000000..46446c7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,163 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q7.c + * Description: Q7 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q7 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqaddq(vecA, vecB), p0); + } +} +#else +void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* Add and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8 (read_q7x4_ia (&pSrcA), read_q7x4_ia (&pSrcB))); +#else + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c new file mode 100644 index 0000000..82aabc8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c @@ -0,0 +1,141 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u16.c + * Description: uint16_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup And Vector bitwise AND + + Compute the logical bitwise AND. + + There are separate functions for uint32_t, uint16_t, and uint7_t data types. + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, vandq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, vandq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c new file mode 100644 index 0000000..0c4b090 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c @@ -0,0 +1,133 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u32.c + * Description: uint32_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, vandq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, vandq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c new file mode 100644 index 0000000..52ac33e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c @@ -0,0 +1,134 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u8.c + * Description: uint8_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, vandq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, vandq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c new file mode 100644 index 0000000..bc4e732 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c @@ -0,0 +1,145 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + f16x8_t curVec0, curVec1; + f16x8_t vecLow, vecHigh; + + vecLow = vdupq_n_f16(low); + vecHigh = vdupq_n_f16(high); + + curVec0 = vld1q(pSrc); + pSrc += 8; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 4; + while (blkCnt--) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 8; + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec1 = vmaxnmq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 8; + curVec1 = vminnmq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 8; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 4) << 4); + if (blkCnt >= 8) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec0 = vld1q(pSrc); + pSrc += 8; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt & 7); + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vstrhq_p(pDst, curVec0, p0); + } +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if ((_Float16)pSrc[i] > (_Float16)high) + pDst[i] = high; + else if ((_Float16)pSrc[i] < (_Float16)low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + @} end of BasicClip group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c new file mode 100644 index 0000000..b2b1374 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c @@ -0,0 +1,148 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicClip Elementwise clipping + + Element-by-element clipping of a value. + + The value is constrained between 2 bounds. + + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + f32x4_t curVec0, curVec1; + f32x4_t vecLow, vecHigh; + + vecLow = vdupq_n_f32(low); + vecHigh = vdupq_n_f32(high); + + curVec0 = vld1q(pSrc); + pSrc += 4; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 3; + while (blkCnt--) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 4; + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec1 = vmaxnmq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 4; + curVec1 = vminnmq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 4; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 3) << 3); + if (blkCnt >= 4) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec0 = vld1q(pSrc); + pSrc += 4; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt & 3); + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vstrwq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicClip group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c new file mode 100644 index 0000000..287109a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c @@ -0,0 +1,138 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q15.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q15x8_t curVec0, curVec1; + q15x8_t vecLow, vecHigh; + + vecLow = vdupq_n_s16(low); + vecHigh = vdupq_n_s16(high); + + curVec0 = vld1q(pSrc); + pSrc += 8; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 4; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 8; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 8; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 8; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 4) << 4); + if (blkCnt >= 8) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec0 = vld1q(pSrc); + pSrc += 8; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt & 7); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrhq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c new file mode 100644 index 0000000..a82d2df --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c @@ -0,0 +1,138 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q31.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q31x4_t curVec0, curVec1; + q31x4_t vecLow, vecHigh; + + vecLow = vdupq_n_s32(low); + vecHigh = vdupq_n_s32(high); + + curVec0 = vld1q(pSrc); + pSrc += 4; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 3; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 4; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 4; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 4; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 3) << 3); + if (blkCnt >= 4) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec0 = vld1q(pSrc); + pSrc += 4; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt & 3); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrwq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c new file mode 100644 index 0000000..f28678c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c @@ -0,0 +1,138 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q7.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q7x16_t curVec0, curVec1; + q7x16_t vecLow, vecHigh; + + vecLow = vdupq_n_s8(low); + vecHigh = vdupq_n_s8(high); + + curVec0 = vld1q(pSrc); + pSrc += 16; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 5; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 16; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 16; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 16; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 16; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 5) << 5); + if (blkCnt >= 16) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 16; + curVec0 = vld1q(pSrc); + pSrc += 16; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp8q(blkCnt & 0xf); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrbq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c new file mode 100644 index 0000000..71ea70d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c @@ -0,0 +1,176 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f16.c + * Description: Floating-point dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) +{ + f16x8_t vecA, vecB; + f16x8_t vecSum; + uint32_t blkCnt; + float16_t sum = 0.0f; + vecSum = vdupq_n_f16(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + * and advance vector source and destination pointers + */ + vecA = vld1q(pSrcA); + pSrcA += 8; + + vecB = vld1q(pSrcB); + pSrcB += 8; + + vecSum = vfmaq(vecSum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vecSum = vfmaq_m(vecSum, vecA, vecB, p0); + } + + sum = vecAddAcrossF16Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum; + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary return variable */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicDotProd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 0000000..6f5e421 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,232 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f32.c + * Description: Floating-point dot product + * + * $Date: 05 October 2021 + * $Revision: V1.9.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + + 
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + f32x4_t vecA, vecB; + f32x4_t vecSum; + uint32_t blkCnt; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + * and advance vector source and destination pointers + */ + vecA = vld1q(pSrcA); + pSrcA += 4; + + vecB = vld1q(pSrcB); + pSrcB += 4; + + vecSum = vfmaq(vecSum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vecSum = vfmaq_m(vecSum, vecA, vecB, p0); + } + + sum = vecAddAcrossF32Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum; + +} + +#else + +void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary return variable */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t accum = vdupq_n_f32(0); +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0); +#endif + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + while (blkCnt > 0U) + { + /* C = A[0]*B[0] + A[1]*B[1] + A[2]*B[2] + ... + A[blockSize-1]*B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + accum = vmlaq_f32(accum, vec1, vec2); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + /* Decrement the loop counter */ + blkCnt--; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(accum), vget_high_f32(accum))); +#else + tmp = vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + +#endif + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicDotProd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c new file mode 100644 index 0000000..821931f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c @@ -0,0 +1,82 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f64.c + * Description: Floating-point dot product + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +void arm_dot_prod_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary return variable */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} + +/** + @} end of BasicDotProd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 0000000..a8faebc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,176 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q15.c + * Description: Q15 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + results are added to a 64-bit accumulator in 34.30 format. + Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + there is no risk of overflow. + The return result is in 34.30 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + q63_t sum = 0LL; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmlaldavaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmlaldavaq_p(sum, vecA, vecB, p0); + } + + *result = sum; +} + +#else +void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* Calculate dot product and store result in a temporary buffer. */ + sum = __SMLALD(read_q15x2_ia (&pSrcA), read_q15x2_ia (&pSrcB), sum); + sum = __SMLALD(read_q15x2_ia (&pSrcA), read_q15x2_ia (&pSrcB), sum); +#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLALD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 34.30 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 0000000..bced7e8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,178 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q31.c + * Description: Q31 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q31 vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + are truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + There are 15 guard bits in the accumulator and there is no risk of overflow as long as + the length of the vectors is less than 2^16 elements. + The return result is in 16.48 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecA; + q31x4_t vecB; + q63_t sum = 0LL; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vrmlaldavhaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vrmlaldavhaq_p(sum, vecA, vecB, p0); + } + + /* + * vrmlaldavhaq provides extra intermediate accumulator headroom. + * limiting the need of intermediate scaling + * Scalar variant uses 2.48 accu format by right shifting accumulators by 14. + * 16.48 output conversion is performed outside the loop by scaling accu. by 6 + */ + *result = asrl(sum, (14 - 8)); +} + +#else +void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 16.48 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 0000000..594bd01 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,195 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q7.c + * Description: Q7 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + results are added to an accumulator in 18.14 format. + Nonsaturating additions are used and there is no danger of wrap around as long as + the vectors are less than 2^18 elements long. + The return result is in 18.14 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + q31_t sum = 0; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmladavaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmladavaq_p(sum, vecA, vecB, p0); + } + + *result = sum; +} +#else +void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t input1, input2; /* Temporary variables */ + q31_t inA1, inA2, inB1, inB2; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* read 4 samples at a time from sourceA */ + input1 = read_q7x4_ia (&pSrcA); + /* read 4 samples at a time from sourceB */ + input2 = read_q7x4_ia (&pSrcB); + + /* extract two q7_t samples to q15_t samples */ + inA1 = __SXTB16(__ROR(input1, 8)); + /* extract reminaing two samples */ + inA2 = __SXTB16(input1); + /* extract two q7_t samples to q15_t samples */ + inB1 = __SXTB16(__ROR(input2, 8)); + /* extract reminaing two samples */ + inB2 = __SXTB16(input2); + + /* multiply and accumulate two samples at a time */ + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); +#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLAD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 18.14 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c new file mode 100644 index 0000000..0b5994b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c @@ -0,0 +1,164 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f16.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vmulq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vmulq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 0000000..0744ac5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,204 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f32.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + + 
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vmulq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vmulq(vec1,vec2), p0); + } + +} + +#else +void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply the inputs and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vmulq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c new file mode 100644 index 0000000..9b914aa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f64.c + * Description: Floating-point vector multiplication + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_mult_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 0000000..d6ec9ec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,196 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q15.c + * Description: Q15 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q15 vector multiplication + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2, inB1, inB2; /* Temporary input variables */ + q15_t out1, out2, out3, out4; /* Temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + /* read 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + /* read 2 samples at a time from sourceA */ + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 samples at a time from sourceB */ + inB2 = read_q15x2_ia (&pSrcB); + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) (inA1 ) * (q15_t) (inB1 )); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 ) * (q15_t) (inB2 )); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT(mul1 >> 15, 16); + out2 = (q15_t) __SSAT(mul2 >> 15, 16); + out3 = (q15_t) __SSAT(mul3 >> 15, 16); + out4 = (q15_t) __SSAT(mul4 >> 15, 16); + + /* store result to destination */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(out2, out1, 16)); + write_q15x2_ia (&pDst, __PKHBT(out4, out3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pDst, __PKHBT(out3, out4, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 0000000..60c103c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,172 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q31.c + * Description: Q31 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q31 vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t out; /* Temporary output variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 0000000..fd0bc3b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,172 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q7.c + * Description: Q7 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q7 vector multiplication + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* Multiply inputs and store results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c new file mode 100644 index 0000000..c4d6ca0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c @@ -0,0 +1,157 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f16.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f16x8_t vec1; + f16x8_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vnegq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vnegq(vec1), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicNegate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 0000000..e4df7ad --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,196 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f32.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + + 
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f32x4_t vec1; + f32x4_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vnegq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vnegq(vec1), p0); + } + +} + +#else +void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vnegq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicNegate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c new file mode 100644 index 0000000..870a767 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c @@ -0,0 +1,77 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f64.c + * Description: Negates floating-point vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_negate_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicNegate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 0000000..c642c24 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,175 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q15.c + * Description: Negates Q15 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q15 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (2 samples at a time). */ + in1 = read_q15x2_ia (&pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); + + in1 = read_q15x2_ia (&pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 0000000..e0048e7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,182 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q31.c + * Description: Negates Q31 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 0000000..3d3cae1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,175 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q7.c + * Description: Negates Q7 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q7 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) is saturated to the maximum allowable positive value 0x7F. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variable */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (4 samples at a time). */ + in1 = read_q7x4_ia (&pSrc); + write_q7x4_ia (&pDst, __QSUB8(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + +#if defined (ARM_MATH_DSP) + *pDst++ = (q7_t) __QSUB8(0, in); +#else + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c new file mode 100644 index 0000000..5e58873 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c @@ -0,0 +1,134 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u16.c + * Description: uint16_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Not Vector bitwise NOT + + Compute the logical bitwise NOT. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u16(vecSrc) ); + + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vmvnq_u16(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t inV; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + inV = vld1q_u16(pSrc); + + vst1q_u16(pDst, vmvnq_u16(inV) ); + + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c new file mode 100644 index 0000000..634800a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c @@ -0,0 +1,126 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u32.c + * Description: uint32_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u32(vecSrc) ); + + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vmvnq_u32(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t inV; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inV = vld1q_u32(pSrc); + + vst1q_u32(pDst, vmvnq_u32(inV) ); + + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c new file mode 100644 index 0000000..b83fb0f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c @@ -0,0 +1,126 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u8.c + * Description: uint8_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u8(vecSrc) ); + + pSrc += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vmvnq_u8(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t inV; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + inV = vld1q_u8(pSrc); + + vst1q_u8(pDst, vmvnq_u8(inV) ); + + pSrc += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c new file mode 100644 index 0000000..4bb665c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c @@ -0,0 +1,160 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f16.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vaddq(vec1,offset); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vaddq(vec1, offset), p0); + } + + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicOffset group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 0000000..3033def --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,200 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f32.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + + 
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vaddq(vec1,offset); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vaddq(vec1, offset), p0); + } + + +} + +#else +void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vaddq_f32(vec1,vdupq_n_f32(offset)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicOffset group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c new file mode 100644 index 0000000..36b9007 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f64.c + * Description: Floating-point vector offset + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_offset_f64( + const float64_t * pSrc, + float64_t offset, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicOffset group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 0000000..9423730 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,172 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q15.c + * Description: Q15 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + + +#else +void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (2 samples at a time). */ + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia (&pSrc), offset_packed)); + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia (&pSrc), offset_packed)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 0000000..b0a1c99 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,163 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q31.c + * Description: Q31 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + +#else +void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 0000000..dacfe48 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,166 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q7.c + * Description: Q7 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + +#else +void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8(read_q7x4_ia (&pSrc), offset_packed)); +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c new file mode 100644 index 0000000..2de542a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c @@ -0,0 +1,141 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u16.c + * Description: uint16_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Or Vector bitwise inclusive OR + + Compute the logical bitwise OR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, vorrq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, vorrq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Or group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c new file mode 100644 index 0000000..6e285dc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c @@ -0,0 +1,132 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u32.c + * Description: uint32_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, vorrq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, vorrq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} +/** + @} end of Or group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c new file mode 100644 index 0000000..b9014a3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c @@ -0,0 +1,132 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u8.c + * Description: uint8_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, vorrq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, vorrq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} +/** + @} end of Or group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c new file mode 100644 index 0000000..ecd4180 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c @@ -0,0 +1,162 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f16.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_scale_f16( + const float16_t * pSrc, + float16_t scale, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vmulq(vec1,scale); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vmulq(vec1, scale), p0); + } + + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_scale_f16( + const float16_t *pSrc, + float16_t scale, + float16_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 0000000..c5c5479 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,220 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f32.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + + 
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + + 
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+
+ + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vmulq(vec1,scale); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vmulq(vec1, scale), p0); + } + + +} + +#else +void arm_scale_f32( + const float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale the input and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + float32_t in1, in2, in3, in4; + + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in1 = (*pSrc++) * scale; + + in2 = (*pSrc++) * scale; + + in3 = (*pSrc++) * scale; + + in4 = (*pSrc++) * scale; + + *pDst++ = in1; + *pDst++ = in2; + *pDst++ = in3; + *pDst++ = in4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c new file mode 100644 index 0000000..747f06b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f64.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_scale_f64( + const float64_t *pSrc, + float64_t scale, + float64_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 0000000..3443de5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,205 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q15.c + * Description: Multiplies a Q15 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q15 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15x8_t vecDst; + + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s16(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt);; + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s16(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrhq_p(pDst, vecDst, p0); + } + +} + + +#else +void arm_scale_q15( + const q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia (&pSrc); + inA2 = read_q15x2_ia (&pSrc); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pDst, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pDst, __PKHBT(in4, in3, 16)); +#else + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 0000000..271278b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,248 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q31.c + * Description: Multiplies a Q31 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q31 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31x4_t vecDst; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s32(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s32(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrwq_p(pDst, vecDst, p0); + } +} + +#else +void arm_scale_q31( + const q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in, out; /* Temporary variables */ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read input from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the result */ + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in >> -kShift; /* apply shifting */ + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 0000000..f4383ee --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,190 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q7.c + * Description: Multiplies a Q7 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q7 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.7 format. + These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t vecDst; + + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s8(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s8(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrbq_p(pDst, vecDst, p0); + } + +} + +#else +void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Scale inputs and store result in the temporary variable. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 0000000..3579dad --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,255 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q15.c + * Description: Shifts the elements of a Q15 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q15 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15x8_t vecDst; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrhq_p(pDst, vecDst, p0); + } +} + +#else +void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q15_t in1, in2; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in1 << shiftBits), 16), + __SSAT(((q31_t) in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in2 << shiftBits), 16), + __SSAT(((q31_t) in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in1 << shiftBits), 16), + __SSAT(((q31_t) in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in2 << shiftBits), 16), + __SSAT(((q31_t) in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 0000000..c2fc8fb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,236 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q31.c + * Description: Shifts the elements of a Q31 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ +/** + @defgroup BasicShift Vector Shift + + Shifts the elements of a fixed-point vector by a specified number of bits. + There are separate functions for Q7, Q15, and Q31 data types. + The underlying algorithm used is: + + 
+      pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.
+
+ + If shift is positive then the elements of the vector are shifted to the left. + If shift is negative then the elements of the vector are shifted to the right. + + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q31 vector a specified number of bits. + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31x4_t vecDst; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q((q31_t const *) pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q((q31_t const *) pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrwq_p(pDst, vecDst, p0); + } +} + + +#else +void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in, out; /* Temporary variables */ + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store results in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = clip_q63_to_q31((q63_t) *pSrc++ << shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 0000000..87ef339 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,229 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q7.c + * Description: Processing function for the Q7 Shifting + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q7 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par onditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t vecDst; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrbq_p(pDst, vecDst, p0); + } +} + +#else +void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(__SSAT(((q15_t) in1 << shiftBits), 8), + __SSAT(((q15_t) in2 << shiftBits), 8), + __SSAT(((q15_t) in3 << shiftBits), 8), + __SSAT(((q15_t) in4 << shiftBits), 8) )); +#else + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7((in1 >> -shiftBits), + (in2 >> -shiftBits), + (in3 >> -shiftBits), + (in4 >> -shiftBits) )); +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c new file mode 100644 index 0000000..571fe5f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c @@ -0,0 +1,164 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f16.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vsubq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vsubq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 0000000..476d7ee --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,206 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f32.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + + 
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vsubq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vsubq(vec1,vec2), p0); + } + +} + +#else +void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c new file mode 100644 index 0000000..a956a14 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f64.c + * Description: Floating-point vector subtraction + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_sub_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 0000000..0892988 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,182 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q15.c + * Description: Q15 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q15 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A - B + * Subtract and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqsubq(vecA, vecB), p0); + } +} + + +#else +void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + inB2 = read_q15x2_ia (&pSrcB); + + /* Subtract and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QSUB16(inA1, inB1)); + write_q15x2_ia (&pDst, __QSUB16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 0000000..8aaae08 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,163 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q31.c + * Description: Q31 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q31 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecA; + q31x4_t vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqsubq(vecA, vecB), p0); + } +} + +#else +void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 0000000..c2aea32 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,162 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q7.c + * Description: Q7 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q7 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A - B + * Subtract and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqsubq(vecA, vecB), p0); + } +} +#else +void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* Subtract and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QSUB8(read_q7x4_ia (&pSrcA), read_q7x4_ia (&pSrcB))); +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c new file mode 100644 index 0000000..def6516 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c @@ -0,0 +1,141 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u16.c + * Description: uint16_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Xor Vector bitwise exclusive OR + + Compute the logical bitwise XOR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, veorq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, veorq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c new file mode 100644 index 0000000..74c3d1c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c @@ -0,0 +1,133 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u32.c + * Description: uint32_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, veorq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, veorq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c new file mode 100644 index 0000000..c1c8615 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c @@ -0,0 +1,133 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u8.c + * Description: uint8_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, veorq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, veorq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c new file mode 100644 index 0000000..bfe2e28 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c @@ -0,0 +1,211 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_naive_gaussian_bayes_predict_f16 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB + ) +{ + uint32_t nbClass; + const float16_t *pTheta = S->theta; + const float16_t *pSigma = S->sigma; + float16_t *buffer = pOutputProbabilities; + const float16_t *pIn = in; + float16_t result; + f16x8_t vsigma; + _Float16 tmp; + f16x8_t vacc1, vacc2; + uint32_t index; + float16_t *logclassPriors=pBufferB; + float16_t *pLogPrior = logclassPriors; + + arm_vlog_f16((float16_t *) S->classPriors, logclassPriors, S->numberOfClasses); + + pTheta = S->theta; + pSigma = S->sigma; + + for (nbClass = 0; nbClass < S->numberOfClasses; nbClass++) { + pIn = in; + + vacc1 = vdupq_n_f16(0.0f16); + vacc2 = vdupq_n_f16(0.0f16); + + uint32_t blkCnt =S->vectorDimension >> 3; + while (blkCnt > 0U) { + f16x8_t vinvSigma, vtmp; + + vsigma = vaddq_n_f16(vld1q(pSigma), S->epsilon); + vacc1 = vaddq(vacc1, vlogq_f16(vmulq_n_f16(vsigma, 2.0f16 * (_Float16)PI))); + + vinvSigma = vrecip_medprec_f16(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq(vacc2, vtmp, vinvSigma); + + pIn += 8; + pTheta += 8; + pSigma += 8; + blkCnt--; + } + + blkCnt = S->vectorDimension & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vinvSigma, vtmp; + + vsigma = vaddq_n_f16(vld1q(pSigma), S->epsilon); + vacc1 = + vaddq_m_f16(vacc1, vacc1, vlogq_f16(vmulq_n_f16(vsigma, 2.0f16 * (_Float16)PI)), p0); + + vinvSigma = vrecip_medprec_f16(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq_m_f16(vacc2, vtmp, vinvSigma, p0); + + pTheta += blkCnt; + pSigma += blkCnt; + } + + tmp = -0.5f16 * (_Float16)vecAddAcrossF16Mve(vacc1); + tmp -= 0.5f16 * (_Float16)vecAddAcrossF16Mve(vacc2); + + *buffer = (_Float16)tmp + (_Float16)*pLogPrior++; + buffer++; + } + + arm_max_f16(pOutputProbabilities, S->numberOfClasses, &result, &index); + + return (index); +} + +#else + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float16_t *pPrior = S->classPriors; + const float16_t *pTheta = S->theta; + const float16_t *pSigma = S->sigma; + float16_t *buffer = pOutputProbabilities; + const float16_t *pIn=in; + float16_t result; + _Float16 sigma; + _Float16 tmp; + _Float16 acc1,acc2; + uint32_t index; + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = (_Float16)*pSigma + (_Float16)S->epsilon; + acc1 += (_Float16)logf(2.0f * PI * (float32_t)sigma); + acc2 += ((_Float16)*pIn - (_Float16)*pTheta) * ((_Float16)*pIn - (_Float16)*pTheta) / (_Float16)sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f16 * (_Float16)acc1; + tmp -= 0.5f16 * (_Float16)acc2; + + + *buffer = (_Float16)tmp + (_Float16)logf((float32_t)*pPrior++); + buffer++; + } + + arm_max_f16(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of groupBayes group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c new file mode 100644 index 0000000..30d1ab9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c @@ -0,0 +1,400 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_naive_gaussian_bayes_predict_f32 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/bayes_functions.h" +#include +#include + +#define PI_F 3.1415926535897932384626433832795f +#define DPI_F (2.0f*3.1415926535897932384626433832795f) + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB + ) +{ + uint32_t nbClass; + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn = in; + float32_t result; + f32x4_t vsigma; + float32_t tmp; + f32x4_t vacc1, vacc2; + uint32_t index; + float32_t *logclassPriors=pBufferB; + float32_t *pLogPrior = logclassPriors; + + arm_vlog_f32((float32_t *) S->classPriors, logclassPriors, S->numberOfClasses); + + pTheta = S->theta; + pSigma = S->sigma; + + for (nbClass = 0; nbClass < S->numberOfClasses; nbClass++) { + pIn = in; + + vacc1 = vdupq_n_f32(0); + vacc2 = vdupq_n_f32(0); + + uint32_t blkCnt =S->vectorDimension >> 2; + while (blkCnt > 0U) { + f32x4_t vinvSigma, vtmp; + + vsigma = vaddq_n_f32(vld1q(pSigma), S->epsilon); + vacc1 = vaddq(vacc1, vlogq_f32(vmulq_n_f32(vsigma, 2.0f * PI))); + + vinvSigma = vrecip_medprec_f32(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq(vacc2, vtmp, vinvSigma); + + pIn += 4; + pTheta += 4; + pSigma += 4; + blkCnt--; + } + + blkCnt = S->vectorDimension & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vinvSigma, vtmp; + + vsigma = vaddq_n_f32(vld1q(pSigma), S->epsilon); + vacc1 = + vaddq_m_f32(vacc1, vacc1, vlogq_f32(vmulq_n_f32(vsigma, 2.0f * PI)), p0); + + vinvSigma = vrecip_medprec_f32(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq_m_f32(vacc2, vtmp, vinvSigma, p0); + + pTheta += blkCnt; + pSigma += blkCnt; + } + + tmp = -0.5f * vecAddAcrossF32Mve(vacc1); + tmp -= 0.5f * vecAddAcrossF32Mve(vacc2); + + *buffer = tmp + *pLogPrior++; + buffer++; + } + + arm_max_f32(pOutputProbabilities, S->numberOfClasses, &result, &index); + + return (index); +} + +#else + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB) +{ + + const float32_t *pPrior = S->classPriors; + + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + + const float32_t *pTheta1 = S->theta + S->vectorDimension; + const float32_t *pSigma1 = S->sigma + S->vectorDimension; + + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn=in; + + float32_t result; + float32_t sigma,sigma1; + float32_t tmp,tmp1; + uint32_t index; + uint32_t vecBlkCnt; + uint32_t classBlkCnt; + float32x4_t epsilonV; + float32x4_t sigmaV,sigmaV1; + float32x4_t tmpV,tmpVb,tmpV1; + float32x2_t tmpV2; + float32x4_t thetaV,thetaV1; + float32x4_t inV; + (void)pBufferB; + + epsilonV = vdupq_n_f32(S->epsilon); + + classBlkCnt = S->numberOfClasses >> 1; + while(classBlkCnt > 0) + { + + + pIn = in; + + tmp = logf(*pPrior++); + tmp1 = logf(*pPrior++); + tmpV = vdupq_n_f32(0.0f); + tmpV1 = vdupq_n_f32(0.0f); + + vecBlkCnt = S->vectorDimension >> 2; + while(vecBlkCnt > 0) + { + sigmaV = vld1q_f32(pSigma); + thetaV = vld1q_f32(pTheta); + + sigmaV1 = vld1q_f32(pSigma1); + thetaV1 = vld1q_f32(pTheta1); + + inV = vld1q_f32(pIn); + + sigmaV = vaddq_f32(sigmaV, epsilonV); + sigmaV1 = vaddq_f32(sigmaV1, epsilonV); + + tmpVb = vmulq_n_f32(sigmaV,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vmulq_n_f32(sigmaV1,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV1 = vmlsq_n_f32(tmpV1,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV)); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV1); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV1)); + tmpV1 = vmlsq_n_f32(tmpV1,tmpVb,0.5f); + + pIn += 4; + pTheta += 4; + pSigma += 4; + pTheta1 += 4; + pSigma1 += 4; + + vecBlkCnt--; + } + tmpV2 = vpadd_f32(vget_low_f32(tmpV),vget_high_f32(tmpV)); + tmp += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + tmpV2 = vpadd_f32(vget_low_f32(tmpV1),vget_high_f32(tmpV1)); + tmp1 += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + vecBlkCnt = S->vectorDimension & 3; + while(vecBlkCnt > 0) + { + sigma = *pSigma + S->epsilon; + sigma1 = *pSigma1 + S->epsilon; + + tmp -= 0.5f*logf(2.0f * PI_F * sigma); + tmp -= 0.5f*(*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + tmp1 -= 0.5f*logf(2.0f * PI_F * sigma1); + tmp1 -= 0.5f*(*pIn - *pTheta1) * (*pIn - *pTheta1) / sigma1; + + pIn++; + pTheta++; + pSigma++; + pTheta1++; + pSigma1++; + vecBlkCnt--; + } + + *buffer++ = tmp; + *buffer++ = tmp1; + + pSigma += S->vectorDimension; + pTheta += S->vectorDimension; + pSigma1 += S->vectorDimension; + pTheta1 += S->vectorDimension; + + classBlkCnt--; + } + + classBlkCnt = S->numberOfClasses & 1; + + while(classBlkCnt > 0) + { + + + pIn = in; + + tmp = logf(*pPrior++); + tmpV = vdupq_n_f32(0.0f); + + vecBlkCnt = S->vectorDimension >> 2; + while(vecBlkCnt > 0) + { + sigmaV = vld1q_f32(pSigma); + thetaV = vld1q_f32(pTheta); + inV = vld1q_f32(pIn); + + sigmaV = vaddq_f32(sigmaV, epsilonV); + + tmpVb = vmulq_n_f32(sigmaV,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV)); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + pIn += 4; + pTheta += 4; + pSigma += 4; + + vecBlkCnt--; + } + tmpV2 = vpadd_f32(vget_low_f32(tmpV),vget_high_f32(tmpV)); + tmp += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + vecBlkCnt = S->vectorDimension & 3; + while(vecBlkCnt > 0) + { + sigma = *pSigma + S->epsilon; + tmp -= 0.5f*logf(2.0f * PI_F * sigma); + tmp -= 0.5f*(*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + vecBlkCnt--; + } + + *buffer++ = tmp; + + classBlkCnt--; + } + + arm_max_f32(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#else + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float32_t *pPrior = S->classPriors; + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn=in; + float32_t result; + float32_t sigma; + float32_t tmp; + float32_t acc1,acc2; + uint32_t index; + + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0; + acc1 = 0.0f; + acc2 = 0.0f; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = *pSigma + S->epsilon; + acc1 += logf(2.0f * PI_F * sigma); + acc2 += (*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f * acc1; + tmp -= 0.5f * acc2; + + + *buffer = tmp + logf(*pPrior++); + buffer++; + } + + arm_max_f32(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of groupBayes group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables.c new file mode 100644 index 0000000..28a2085 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,70580 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + +/** + @par + Pseudo code for Generation of Bit reversal Table is + @par + 
for (l = 1; l <= N/4; l++)
+  {
+    for (i = 0; i< logN2; i++)
+    {
+      a[i] = l & (1 << i);
+    }
+    for (j = 0; j < logN2; j++)
+    {
+      if (a[j] != 0)
+      y[l] += (1 << ((logN2 - 1) - j));
+    }
+    y[l] = y[l] >> 1;
+   }
+ @par + where N = 4096, logN2 = 12 + @par + N is the maximum FFT Size supported +*/ + +/** + @brief Table for bit reversal process +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) +const uint16_t armBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x080, 0x480, 0x280, + 0x680, 0x180, 0x580, 0x380, 0x780, 0x040, 0x440, 0x240, 0x640, 0x140, + 0x540, 0x340, 0x740, 0x0c0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, + 0x7c0, 0x020, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0x0a0, + 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x060, 0x460, 0x260, + 0x660, 0x160, 0x560, 0x360, 0x760, 0x0e0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, + 0x5e0, 0x3e0, 0x7e0, 0x010, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, + 0x710, 0x090, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x050, + 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0x0d0, 0x4d0, 0x2d0, + 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x030, 0x430, 0x230, 0x630, 0x130, + 0x530, 0x330, 0x730, 0x0b0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, + 0x7b0, 0x070, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0x0f0, + 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x008, 0x408, 0x208, + 0x608, 0x108, 0x508, 0x308, 0x708, 0x088, 0x488, 0x288, 0x688, 0x188, + 0x588, 0x388, 0x788, 0x048, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, + 0x748, 0x0c8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x028, + 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0x0a8, 0x4a8, 0x2a8, + 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x068, 0x468, 0x268, 0x668, 0x168, + 0x568, 0x368, 0x768, 0x0e8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, + 0x7e8, 0x018, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x098, + 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x058, 0x458, 0x258, + 0x658, 0x158, 0x558, 0x358, 0x758, 0x0d8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, + 0x5d8, 0x3d8, 0x7d8, 0x038, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, + 0x738, 0x0b8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x078, + 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0x0f8, 0x4f8, 0x2f8, + 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x004, 0x404, 0x204, 0x604, 0x104, + 0x504, 0x304, 0x704, 0x084, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, + 0x784, 0x044, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0x0c4, + 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x024, 0x424, 0x224, + 0x624, 0x124, 0x524, 0x324, 0x724, 0x0a4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, + 0x5a4, 0x3a4, 0x7a4, 0x064, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, + 0x764, 0x0e4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x014, + 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x094, 0x494, 0x294, + 0x694, 0x194, 0x594, 0x394, 0x794, 0x054, 0x454, 0x254, 0x654, 0x154, + 0x554, 0x354, 0x754, 0x0d4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, + 0x7d4, 0x034, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0x0b4, + 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x074, 0x474, 0x274, + 0x674, 0x174, 0x574, 0x374, 0x774, 0x0f4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, + 0x5f4, 0x3f4, 0x7f4, 0x00c, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, + 0x70c, 0x08c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x04c, + 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0x0cc, 0x4cc, 0x2cc, + 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x02c, 0x42c, 0x22c, 0x62c, 0x12c, + 0x52c, 0x32c, 0x72c, 0x0ac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, + 0x7ac, 0x06c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0x0ec, + 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x01c, 0x41c, 0x21c, + 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x09c, 0x49c, 0x29c, 0x69c, 0x19c, + 0x59c, 0x39c, 0x79c, 0x05c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, + 0x75c, 0x0dc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x03c, + 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0x0bc, 0x4bc, 0x2bc, + 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x07c, 0x47c, 0x27c, 0x67c, 0x17c, + 0x57c, 0x37c, 0x77c, 0x0fc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, + 0x7fc, 0x002, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x082, + 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x042, 0x442, 0x242, + 0x642, 0x142, 0x542, 0x342, 0x742, 0x0c2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, + 0x5c2, 0x3c2, 0x7c2, 0x022, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, + 0x722, 0x0a2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x062, + 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0x0e2, 0x4e2, 0x2e2, + 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x012, 0x412, 0x212, 0x612, 0x112, + 0x512, 0x312, 0x712, 0x092, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, + 0x792, 0x052, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0x0d2, + 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x032, 0x432, 0x232, + 0x632, 0x132, 0x532, 0x332, 0x732, 0x0b2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, + 0x5b2, 0x3b2, 0x7b2, 0x072, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, + 0x772, 0x0f2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0x00a, + 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x08a, 0x48a, 0x28a, + 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x04a, 0x44a, 0x24a, 0x64a, 0x14a, + 0x54a, 0x34a, 0x74a, 0x0ca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, + 0x7ca, 0x02a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0x0aa, + 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x06a, 0x46a, 0x26a, + 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0x0ea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, + 0x5ea, 0x3ea, 0x7ea, 0x01a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a, + 0x71a, 0x09a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, + 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0x0da, 0x4da, 0x2da, + 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x03a, 0x43a, 0x23a, 0x63a, 0x13a, + 0x53a, 0x33a, 0x73a, 0x0ba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba, + 0x7ba, 0x07a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0x0fa, + 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x006, 0x406, 0x206, + 0x606, 0x106, 0x506, 0x306, 0x706, 0x086, 0x486, 0x286, 0x686, 0x186, + 0x586, 0x386, 0x786, 0x046, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, + 0x746, 0x0c6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x026, + 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0x0a6, 0x4a6, 0x2a6, + 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x066, 0x466, 0x266, 0x666, 0x166, + 0x566, 0x366, 0x766, 0x0e6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, + 0x7e6, 0x016, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x096, + 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x056, 0x456, 0x256, + 0x656, 0x156, 0x556, 0x356, 0x756, 0x0d6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, + 0x5d6, 0x3d6, 0x7d6, 0x036, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, + 0x736, 0x0b6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x076, + 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0x0f6, 0x4f6, 0x2f6, + 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0x00e, 0x40e, 0x20e, 0x60e, 0x10e, + 0x50e, 0x30e, 0x70e, 0x08e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, + 0x78e, 0x04e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0x0ce, + 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x02e, 0x42e, 0x22e, + 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0x0ae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, + 0x5ae, 0x3ae, 0x7ae, 0x06e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, + 0x76e, 0x0ee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x01e, + 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x09e, 0x49e, 0x29e, + 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x05e, 0x45e, 0x25e, 0x65e, 0x15e, + 0x55e, 0x35e, 0x75e, 0x0de, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, + 0x7de, 0x03e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0x0be, + 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x07e, 0x47e, 0x27e, + 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0x0fe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, + 0x5fe, 0x3fe, 0x7fe, 0x001 +}; +#endif + +/** + @brief Double Precision Floating-point Twiddle factors Table Generation +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(double)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(double)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_16[32] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_32[64] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, //-0.19509, 0.98079' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, //-0.55557, 0.83147' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, //-0.83147, 0.55557' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, //-0.98079, 0.19509' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, //-0.98079,-0.19509' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, //-0.83147,-0.55557' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, //-0.55557,-0.83147' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, //-0.19509,-0.98079' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509,-0.98079' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557,-0.83147' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147,-0.55557' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079,-0.19509' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_64[128] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + }; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_128[256] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_256[512] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_512[1024] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, //-0.012272, 0.99992 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa2d865759455cd, 0x3feffa72effef75d, //-0.036807, 0.99932 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, //-0.061321, 0.99812 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //-0.085797, 0.99631 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992,-0.012272 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932,-0.036807 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812,-0.061321 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631,-0.085797 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //-0.085797, -0.99631 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, //-0.061321, -0.99812 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, //-0.036807, -0.99932 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, //-0.012272, -0.99992 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_1024[2048] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_2048[4096] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_4096[8192] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, // 0.0076698, 0.99997 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, // 0.0046019, 0.99999 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf5921faaee6472d, 0x3feffffd88586ee6, // -0.001534, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf72d97822f996bc, 0x3fefffe9cb1e2e8d, //-0.0046019, 0.99999 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf7f6a65f9a2a3c5, 0x3fefffc250b5daef, //-0.0076698, 0.99997 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf85fda037ac05e0, 0x3fefff871937ce2f, // -0.010738, 0.99994 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8c45ffe1e48ad9, 0x3fefff3824c88f6f, // -0.013805, 0.9999 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf9147270dad7132, 0x3feffed57398d2b7, // -0.016873, 0.99986 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf946b4381fce81c, 0x3feffe5f05e578db, // -0.01994, 0.9998 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf978f535ddc9f03, 0x3feffdd4dbf78f52, // -0.023008, 0.99974 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9ab354b1504fca, 0x3feffd36f624500c, // -0.026075, 0.99966 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9dd7458c64ab39, 0x3feffc8554cd213a, // -0.029142, 0.99958 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa07d91ff984580, 0x3feffbbff85f9515, // -0.032208, 0.99948 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa20f770ceb11c6, 0x3feffae6e1556998, // -0.035274, 0.99938 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa3a150f6421afc, 0x3feff9fa10348837, // -0.03834, 0.99926 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5331ec3bba0eb, 0x3feff8f9858f058b, // -0.041406, 0.99914 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa6c4df7d7d5b84, 0x3feff7e5420320f9, // -0.044471, 0.99901 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa856922bb513c1, 0x3feff6bd463b444d, // -0.047535, 0.99887 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfa9e835d6993c87, 0x3feff58192ee0358, // -0.0506, 0.99872 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfab79c986698b78, 0x3feff43228de1b77, // -0.053664, 0.99856 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfad0b4c436f91d0, 0x3feff2cf08da7321, // -0.056727, 0.99839 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfae9cbd15ff5527, 0x3feff15833be1965, // -0.05979, 0.99821 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb0170d833bf421, 0x3fefefcdaa704562, // -0.062852, 0.99802 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb0dfb28ea201e6, 0x3fefee2f6de455ba, // -0.065913, 0.99783 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb1a84d316d4f8a, 0x3fefec7d7f19cffc, // -0.068974, 0.99762 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb270dcefdfc45b, 0x3fefeab7df1c6005, // -0.072035, 0.9974 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb339614e41ffa5, 0x3fefe8de8f03d75c, // -0.075094, 0.99718 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb401d9d0e3a507, 0x3fefe6f18ff42c84, // -0.078153, 0.99694 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // -0.081211, 0.9967 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb592a554489bc8, 0x3fefe2dc89bbff08, // -0.084269, 0.99644 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb65af75dd0f87b, 0x3fefe0b485181be3, // -0.087326, 0.99618 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb7233b9d236e71, 0x3fefde78d68653fd, // -0.090381, 0.99591 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb7eb7196b72ee4, 0x3fefdc297f674ba9, // -0.093436, 0.99563 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb8b398cf0c38e0, 0x3fefd9c68127c78c, // -0.09649, 0.99533 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb97bb0caaba56f, 0x3fefd74fdd40abbf, // -0.099544, 0.99503 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfba43b90e27f3c4, 0x3fefd4c59536fae4, // -0.1026, 0.99472 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb0bb11e1d5559, 0x3fefd227aa9bd53b, // -0.10565, 0.9944 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbbd3987f31fa0e, 0x3fefcf761f0c77a3, // -0.1087, 0.99407 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbc9b6eb6165c42, 0x3fefccb0f4323aa3, // -0.11175, 0.99374 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbd633347858ce4, 0x3fefc9d82bc2915e, // -0.11479, 0.99339 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe2ae5b8457f77, 0x3fefc6ebc77f0887, // -0.11784, 0.99303 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbef2858d27561b, 0x3fefc3ebc935454c, // -0.12089, 0.99267 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfbfba124b07ad85, 0x3fefc0d832bf043a, // -0.12393, 0.99229 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc040c5bb67747e, 0x3fefbdb106021816, // -0.12698, 0.99191 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0a4784ab8bf1d, 0x3fefba7644f068b5, // -0.13002, 0.99151 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc1082095f820b0, 0x3fefb727f187f1c7, // -0.13306, 0.99111 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc16bbe5fac5865, 0x3fefb3c60dd2c199, // -0.1361, 0.9907 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc1cf516a62a077, 0x3fefb0509be6f7db, // -0.13914, 0.99027 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc232d978aed413, 0x3fefacc79de6c44f, // -0.14218, 0.98984 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc296564d2b953e, 0x3fefa92b1600657c, // -0.14521, 0.9894 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc2f9c7aa7a72af, 0x3fefa57b066e2754, // -0.14825, 0.98895 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc35d2d53440db2, 0x3fefa1b7717661d5, // -0.15128, 0.98849 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3c0870a383ff6, 0x3fef9de0596b77a3, // -0.15431, 0.98802 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc423d4920e4166, 0x3fef99f5c0abd496, // -0.15734, 0.98754 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc48715ad84cdf5, 0x3fef95f7a9a1ec47, // -0.16037, 0.98706 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc4ea4a1f624b61, 0x3fef91e616c43891, // -0.1634, 0.98656 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc54d71aa74ef02, 0x3fef8dc10a95380d, // -0.16643, 0.98605 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5b08c1192e381, 0x3fef898887a36c84, // -0.16945, 0.98554 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc61399179a6e94, 0x3fef853c9089595e, // -0.17247, 0.98501 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc676987f7216b8, 0x3fef80dd27ed8204, // -0.17549, 0.98448 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc6d98a0c08c8da, 0x3fef7c6a50826840, // -0.17851, 0.98394 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc73c6d8055fe0a, 0x3fef77e40d068a90, // -0.18153, 0.98339 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc79f429f59e11d, 0x3fef734a60446279, // -0.18455, 0.98282 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc802092c1d744b, 0x3fef6e9d4d1262ca, // -0.18756, 0.98225 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc864c0e9b2b6cf, 0x3fef69dcd652f5de, // -0.19057, 0.98167 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8c7699b34ca7e, 0x3fef6508fef47bd5, // -0.19359, 0.98108 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc92a0303c8194f, 0x3fef6021c9f148c2, // -0.19659, 0.98048 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // -0.1996, 0.97988 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfc9ef0706e35a35, 0x3fef56195321c090, // -0.20261, 0.97926 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca517127e3dabc, 0x3fef50f81785c6b9, // -0.20561, 0.97863 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // -0.20861, 0.978 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb16147941ca2a, 0x3fef467bafb7bbe0, // -0.21161, 0.97735 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcb784d30536cda, 0x3fef412089fd8adc, // -0.21461, 0.9767 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcbda74f5856330, 0x3fef3bb21cc4fe47, // -0.2176, 0.97604 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc3c8b8c4b9dd7, 0x3fef36306b67c556, // -0.2206, 0.97536 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcc9e90b824a6a9, 0x3fef309b794b719f, // -0.22359, 0.97468 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd00843c99c5f9, 0x3fef2af349e17507, // -0.22658, 0.97399 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd6265dd3f27e3, 0x3fef2537e0a71f9f, // -0.22957, 0.97329 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdc4355db40195, 0x3fef1f6941259d7a, // -0.23255, 0.97258 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce25f281a2b684, 0x3fef19876ef1f486, // -0.23553, 0.97187 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfce879d0cc0fdaf, 0x3fef13926dad024e, // -0.23851, 0.97114 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcee934c2d006c7, 0x3fef0d8a410379c5, // -0.24149, 0.9704 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf4ab9679c9f5c, 0x3fef076eecade0fa, // -0.24447, 0.96966 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfac2abeff57ff, 0x3fef014074708ed3, // -0.24744, 0.9689 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd006c4466e54af, 0x3feefafedc1ba8b7, // -0.25041, 0.96814 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd037694a928cac, 0x3feef4aa278b2032, // -0.25338, 0.96737 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd068044deab002, 0x3feeee425aa6b09a, // -0.25635, 0.96658 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd09895327b465e, 0x3feee7c77961dc9e, // -0.25931, 0.96579 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0c91bda4f158d, 0x3feee13987bbebdc, // -0.26227, 0.96499 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd0f998277733f7, 0x3feeda9889bfe86a, // -0.26523, 0.96418 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd12a09fc0b1b12, 0x3feed3e483849c51, // -0.26819, 0.96337 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd15a713a28b9d9, 0x3feecd1d792c8f10, // -0.27115, 0.96254 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd18acdc3f4873a, 0x3feec6436ee60309, // -0.2741, 0.9617 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1bb1f7b999480, 0x3feebf5668eaf2ef, // -0.27705, 0.96086 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd1eb6643499fbb, 0x3feeb8566b810f2a, // -0.27999, 0.96 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd21ba1fd3d2623, 0x3feeb1437af9bb34, // -0.28294, 0.95914 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd24bd28bb37672, 0x3feeaa1d9bb20af3, // -0.28588, 0.95827 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd27bf7d0f2c346, 0x3feea2e4d212c000, // -0.28882, 0.95738 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2ac11af483572, 0x3fee9b99229046f8, // -0.29175, 0.95649 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2dc200907fe51, 0x3fee943a91aab4b4, // -0.29469, 0.95559 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd30c22c08d6a13, 0x3fee8cc923edc388, // -0.29762, 0.95469 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd33c19b83af207, 0x3fee8544ddf0d075, // -0.30054, 0.95377 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd36c04d27a4edf, 0x3fee7dadc456d850, // -0.30347, 0.95284 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd39be3f1bc8aef, 0x3fee7603dbce74e9, // -0.30639, 0.95191 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3cbb6f87a146e, 0x3fee6e472911da27, // -0.30931, 0.95096 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // -0.31222, 0.95001 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd42b38466e2928, 0x3fee5e95781ebf1c, // -0.31514, 0.94905 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd45ae652bb2800, 0x3fee56a083968eb1, // -0.31805, 0.94807 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd48a87d0b07fd7, 0x3fee4e98d836c0af, // -0.32096, 0.94709 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4ba1ca2eca31c, 0x3fee467e7af35f23, // -0.32386, 0.94611 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd4e9a4ac15d520, 0x3fee3e5170cbfc46, // -0.32676, 0.94511 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd5191fceda3c35, 0x3fee3611becbaf69, // -0.32966, 0.9441 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5488dedeff3be, 0x3fee2dbf6a0911d9, // -0.33255, 0.94308 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd577eeec151e47, 0x3fee255a77a63bb8, // -0.33545, 0.94206 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // -0.33833, 0.94103 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5d68910aee686, 0x3fee1458cec1ad83, // -0.34122, 0.93998 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd605c1fcc88f63, 0x3fee0bbc22bd8349, // -0.3441, 0.93893 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd634ed533be58e, 0x3fee030cee1435b8, // -0.34698, 0.93787 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6640af6f03d9e, 0x3fedfa4b3621271d, // -0.34986, 0.9368 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6931acad55f51, 0x3fedf177004b2534, // -0.35273, 0.93573 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6c21cb1e39771, 0x3fede890520465ce, // -0.3556, 0.93464 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd6f1108f1bc9c5, 0x3feddf9730ca837b, // -0.35846, 0.93354 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd71ff6458782ec, 0x3fedd68ba2267a25, // -0.36133, 0.93244 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // -0.36418, 0.93133 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd77d96ca4b73a6, 0x3fedc43d52fcb453, // -0.36704, 0.93021 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7ac515ee2b172, 0x3fedbafa9dc1b78d, // -0.36989, 0.92907 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7dafd592ba621, 0x3fedb1a591b20c38, // -0.37274, 0.92794 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd8099a9c5c362d, 0x3feda83e348f613b, // -0.37559, 0.92679 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd838290bb359c8, 0x3fed9ec48c26b1f3, // -0.37843, 0.92563 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd866a88a792ea0, 0x3fed95389e50429b, // -0.38127, 0.92447 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd89518fbff098e, 0x3fed8b9a70ef9cb4, // -0.3841, 0.92329 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8c37a439f884f, 0x3fed81ea09f38b63, // -0.38693, 0.92211 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd8f1cc44bea329, 0x3fed78276f5617c6, // -0.38976, 0.92092 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9200ee2c9be97, 0x3fed6e52a71c8547, // -0.39258, 0.91972 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd94e420137bce3, 0x3fed646bb7574de5, // -0.3954, 0.91851 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd97c6583890fc2, 0x3fed5a72a6221e73, // -0.39822, 0.91729 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9aa794d47c9ee, 0x3fed506779a3d2d9, // -0.40103, 0.91606 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9d87d4207b0ab, 0x3fed464a380e7242, // -0.40384, 0.91483 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda067145664d57, 0x3fed3c1ae79f2b4e, // -0.40664, 0.91359 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda34553b0afee5, 0x3fed31d98e9e503a, // -0.40944, 0.91234 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda622906a70b63, 0x3fed2786335f52fc, // -0.41224, 0.91107 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfda8fec8bf5b166, 0x3fed1d20dc40c15c, // -0.41503, 0.90981 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdabd9faebc3980, 0x3fed12a98fac410c, // -0.41782, 0.90853 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdaeb4252ca07ab, 0x3fed082054168bac, // -0.42061, 0.90724 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb18d45bf8aca6, 0x3fecfd852fff6ad4, // -0.42339, 0.90595 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb4655ae2bf757, 0x3fecf2d829f1b40e, // -0.42617, 0.90464 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb73c62d520624, 0x3fece819488344ce, // -0.42894, 0.90333 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdba125bd63583e, 0x3fecdd489254fe65, // -0.43171, 0.90201 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbce744262deee, 0x3fecd2660e12c1e6, // -0.43448, 0.90068 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdbfbb1a05e0edc, 0x3fecc771c2736c09, // -0.43724, 0.89935 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc28ddbb6cf145, 0x3fecbc6bb638d10b, // -0.43999, 0.898 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc55f877b23537, 0x3fecb153f02fb87d, // -0.44275, 0.89665 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc8301b95b40c2, 0x3feca62a772fd919, // -0.4455, 0.89528 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcaff964a0421d, 0x3fec9aef521bd480, // -0.44824, 0.89391 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcdcdf5dc440ce, 0x3fec8fa287e13305, // -0.45098, 0.89253 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd09b389152ec1, 0x3fec84441f785f61, // -0.45372, 0.89115 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd3675caebf962, 0x3fec78d41fe4a267, // -0.45645, 0.88975 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd632607ac9aa9, 0x3fec6d5290341eb2, // -0.45918, 0.88835 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdd8fc423c62a25, 0x3fec61bf777fcc48, // -0.4619, 0.88693 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddbc5003b2edf8, 0x3fec561adceb743e, // -0.46462, 0.88551 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // -0.46733, 0.88408 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde1530a12779f4, 0x3fec3e9d3ee7d262, // -0.47004, 0.88264 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde418527dc4ffa, 0x3fec32c449f60831, // -0.47275, 0.8812 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde6dc704be97e2, 0x3fec26d9f01f2eaf, // -0.47545, 0.87974 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfde99f61c817eda, 0x3fec1ade38bce19b, // -0.47815, 0.87828 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdec61253e3c61b, 0x3fec0ed12b3372e9, // -0.48084, 0.87681 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdef21b8fafd3b5, 0x3fec02b2cef1e641, // -0.48353, 0.87533 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf1e11b4bbc35c, 0x3febf6832b71ec5b, // -0.48621, 0.87384 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf49f4a7e97729, 0x3febea424837de6d, // -0.48889, 0.87235 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf75c44e26a852, 0x3febddf02cd2b983, // -0.49156, 0.87084 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // -0.49423, 0.86933 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfcd2947c1ff57, 0x3febc5186bf8361d, // -0.4969, 0.86781 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfdff8be6537615e, 0x3febb892d5d5dad5, // -0.49956, 0.86628 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe0121fe4f56d2c, 0x3febabfc262e6586, // -0.50221, 0.86474 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe027d6ad83287e, 0x3feb9f5464c5bffc, // -0.50486, 0.8632 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe03d837edff370, 0x3feb929b996a5b7f, // -0.50751, 0.86165 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe053264bad0483, 0x3feb85d1cbf52c02, // -0.51015, 0.86009 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe068bf0691c028, 0x3feb78f70449a34b, // -0.51279, 0.85852 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe07e4da23bc102, 0x3feb6c0b4a55ac17, // -0.51542, 0.85694 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe093d2115ee018, 0x3feb5f0ea611a532, // -0.51804, 0.85535 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0a94c46b53d0b, 0x3feb52011f805c92, // -0.52067, 0.85376 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0bebc34ff4646, 0x3feb44e2beaf0a61, // -0.52328, 0.85216 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0d421cf03c12b, 0x3feb37b38bb54c09, // -0.5259, 0.85055 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0e97d078fd23b, 0x3feb2a738eb51f33, // -0.5285, 0.84893 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe0fecdd1770537, 0x3feb1d22cfdadcc6, // -0.5311, 0.84731 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe114141f935545, 0x3feb0fc1575d33db, // -0.5337, 0.84567 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1294fe4c5350a, 0x3feb024f2d7d24a9, // -0.53629, 0.84403 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe13e8113f396c1, 0x3feaf4cc5a85fb73, // -0.53888, 0.84238 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe153a7a00bf453, 0x3feae738e6cd4b67, // -0.54146, 0.84073 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe168c37c025764, 0x3fead994dab2e979, // -0.54404, 0.83906 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe17dd49ad16161, 0x3feacbe03ea0e73b, // -0.54661, 0.83739 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe192daef7a5386, 0x3feabe1b1b0b8dac, // -0.54918, 0.83571 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1a7d66d0516e6, 0x3feab045787157ff, // -0.55174, 0.83402 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1bcc706804467, 0x3feaa25f5f5aee60, // -0.55429, 0.83232 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1d1acaf012cc2, 0x3fea9468d85b20ae, // -0.55685, 0.83062 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1e68759a3e074, 0x3fea8661ec0ee133, // -0.55939, 0.8289 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe1fb56f98b37b8, 0x3fea784aa31d3f55, // -0.56193, 0.82718 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe2101b81e0da78, 0x3fea6a230637623b, // -0.56447, 0.82546 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe224d4e5d5482e, 0x3fea5beb1e188375, // -0.567, 0.82372 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe23983189fdfd5, 0x3fea4da2f385e997, // -0.56952, 0.82198 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // -0.57204, 0.82023 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe262bdb7b795a2, 0x3fea30e1fa4cbf81, // -0.57455, 0.81847 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2774a0a961612, 0x3fea22693d62ccb9, // -0.57706, 0.8167 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe28bcaf96d94ba, 0x3fea13e0617e4ec7, // -0.57956, 0.81493 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2a040779843fb, 0x3fea05476f967bb5, // -0.58206, 0.81314 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2b4aa787764c4, 0x3fe9f69e70ac75bc, // -0.58455, 0.81135 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2c908ef734e57, 0x3fe9e7e56dcb45bd, // -0.58704, 0.80956 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // -0.58952, 0.80775 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2f1a30d86773a, 0x3fe9ca438080eadb, // -0.592, 0.80594 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe305de9b921a94, 0x3fe9bb5aa85f2098, // -0.59447, 0.80412 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe31a0e6da35e44, 0x3fe9ac61f0d4e247, // -0.59693, 0.80229 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe32e3277467d6b, 0x3fe99d59631e65d5, // -0.59939, 0.80046 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe3424aac0ef7d6, 0x3fe98e410881a600, // -0.60184, 0.79861 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe35656ff9799ae, 0x3fe97f18ea4e5c9e, // -0.60429, 0.79676 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe36a576582831b, 0x3fe96fe111ddfce0, // -0.60673, 0.79491 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe37e4bd1792fe2, 0x3fe960998893ad8c, // -0.60917, 0.79304 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39234372c7f04, 0x3fe9514257dc4335, // -0.6116, 0.79117 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3a6108a54ba58, 0x3fe941db892e3a65, // -0.61402, 0.78929 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3b9e0beb19e18, 0x3fe932652609b1cf, // -0.61644, 0.7874 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3cda4c80a6076, 0x3fe922df37f8646a, // -0.61885, 0.78551 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3e15c9a2db922, 0x3fe91349c88da398, // -0.62126, 0.7836 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3f50828f1e8d2, 0x3fe903a4e1665133, // -0.62366, 0.78169 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe408a76834c0c0, 0x3fe8f3f08c28d9ac, // -0.62606, 0.77978 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // -0.62845, 0.77785 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // -0.63083, 0.77592 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe4433ad0117b1d, 0x3fe8c47758fa71cb, // -0.63321, 0.77398 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe456a858917046, 0x3fe8b485aca2a468, // -0.63558, 0.77204 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe46a095557a0f1, 0x3fe8a484c3031d50, // -0.63794, 0.77008 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe47d5dba6fde01, 0x3fe89474a5fb0a84, // -0.6403, 0.76812 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe490a57bedbcdf, 0x3fe884555f72fa6b, // -0.64266, 0.76615 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // -0.645, 0.76418 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4b70ee48fb869, 0x3fe863e97db3d95a, // -0.64735, 0.7622 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4ca30740218a3, 0x3fe8539cf67c9029, // -0.64968, 0.76021 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4dd453076b064, 0x3fe843416dc4cce2, // -0.65201, 0.75821 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // -0.65433, 0.75621 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe503480159ded2, 0x3fe8225d803964e5, // -0.65665, 0.75419 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51635fe5601d7, 0x3fe811d52faf94dc, // -0.65896, 0.75218 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe52916f96f8388, 0x3fe8013e0638e795, // -0.66127, 0.75015 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe53beae7012abe, 0x3fe7f0980e113978, // -0.66356, 0.74812 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // -0.66586, 0.74608 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe5616b6b204e6e, 0x3fe7cf1fdacbf179, // -0.66814, 0.74403 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57417ea8bb75c, 0x3fe7be4db453a27c, // -0.67042, 0.74198 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // -0.67269, 0.73992 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe599492a81ffbc, 0x3fe79c7d8198e56e, // -0.67496, 0.73785 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // -0.67722, 0.73578 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5be451f8bf980, 0x3fe77a730cbb9100, // -0.67948, 0.7337 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d0af016ed1d4, 0x3fe7695813b9b594, // -0.68172, 0.73161 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5e30b6e6877f3, 0x3fe7582ea9b9a329, // -0.68397, 0.72951 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5f55a5b2576f8, 0x3fe746f6d9516d59, // -0.6862, 0.72741 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe6079bbc5aadfa, 0x3fe735b0ad2009b2, // -0.68843, 0.7253 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe619cf86c55702, 0x3fe7245c2fcd492a, // -0.69065, 0.72319 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe62bf5af2b0dfd, 0x3fe712f96c09d18d, // -0.69287, 0.72107 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe63e0e2a59d7aa, 0x3fe701886c8f16e6, // -0.69508, 0.71894 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe65018ed28287f, 0x3fe6f0093c1f54de, // -0.69728, 0.7168 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66215ec74eb91, 0x3fe6de7be585881d, // -0.69947, 0.71466 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe674051d27896c, 0x3fe6cce07395679f, // -0.70166, 0.71251 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe685e6742feeef, 0x3fe6bb36f12b5e06, // -0.70385, 0.71035 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe697b9e686941c, 0x3fe6a97f692c82ea, // -0.70602, 0.70819 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6a97f692c82ea, 0x3fe697b9e686941c, // -0.70819, 0.70602 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6bb36f12b5e06, 0x3fe685e6742feeef, // -0.71035, 0.70385 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6cce07395679f, 0x3fe674051d27896c, // -0.71251, 0.70166 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6de7be585881d, 0x3fe66215ec74eb91, // -0.71466, 0.69947 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f0093c1f54de, 0x3fe65018ed28287f, // -0.7168, 0.69728 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe701886c8f16e6, 0x3fe63e0e2a59d7aa, // -0.71894, 0.69508 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe712f96c09d18d, 0x3fe62bf5af2b0dfd, // -0.72107, 0.69287 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe7245c2fcd492a, 0x3fe619cf86c55702, // -0.72319, 0.69065 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe735b0ad2009b2, 0x3fe6079bbc5aadfa, // -0.7253, 0.68843 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe746f6d9516d59, 0x3fe5f55a5b2576f8, // -0.72741, 0.6862 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe7582ea9b9a329, 0x3fe5e30b6e6877f3, // -0.72951, 0.68397 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe7695813b9b594, 0x3fe5d0af016ed1d4, // -0.73161, 0.68172 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe77a730cbb9100, 0x3fe5be451f8bf980, // -0.7337, 0.67948 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // -0.73578, 0.67722 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe79c7d8198e56e, 0x3fe599492a81ffbc, // -0.73785, 0.67496 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // -0.73992, 0.67269 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7be4db453a27c, 0x3fe57417ea8bb75c, // -0.74198, 0.67042 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7cf1fdacbf179, 0x3fe5616b6b204e6e, // -0.74403, 0.66814 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // -0.74608, 0.66586 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f0980e113978, 0x3fe53beae7012abe, // -0.74812, 0.66356 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8013e0638e795, 0x3fe52916f96f8388, // -0.75015, 0.66127 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe811d52faf94dc, 0x3fe51635fe5601d7, // -0.75218, 0.65896 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe8225d803964e5, 0x3fe503480159ded2, // -0.75419, 0.65665 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // -0.75621, 0.65433 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe843416dc4cce2, 0x3fe4dd453076b064, // -0.75821, 0.65201 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe8539cf67c9029, 0x3fe4ca30740218a3, // -0.76021, 0.64968 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe863e97db3d95a, 0x3fe4b70ee48fb869, // -0.7622, 0.64735 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // -0.76418, 0.645 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe884555f72fa6b, 0x3fe490a57bedbcdf, // -0.76615, 0.64266 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89474a5fb0a84, 0x3fe47d5dba6fde01, // -0.76812, 0.6403 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8a484c3031d50, 0x3fe46a095557a0f1, // -0.77008, 0.63794 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8b485aca2a468, 0x3fe456a858917046, // -0.77204, 0.63558 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8c47758fa71cb, 0x3fe4433ad0117b1d, // -0.77398, 0.63321 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // -0.77592, 0.63083 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // -0.77785, 0.62845 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8f3f08c28d9ac, 0x3fe408a76834c0c0, // -0.77978, 0.62606 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe903a4e1665133, 0x3fe3f50828f1e8d2, // -0.78169, 0.62366 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91349c88da398, 0x3fe3e15c9a2db922, // -0.7836, 0.62126 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe922df37f8646a, 0x3fe3cda4c80a6076, // -0.78551, 0.61885 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe932652609b1cf, 0x3fe3b9e0beb19e18, // -0.7874, 0.61644 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe941db892e3a65, 0x3fe3a6108a54ba58, // -0.78929, 0.61402 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe9514257dc4335, 0x3fe39234372c7f04, // -0.79117, 0.6116 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe960998893ad8c, 0x3fe37e4bd1792fe2, // -0.79304, 0.60917 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe96fe111ddfce0, 0x3fe36a576582831b, // -0.79491, 0.60673 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe97f18ea4e5c9e, 0x3fe35656ff9799ae, // -0.79676, 0.60429 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe98e410881a600, 0x3fe3424aac0ef7d6, // -0.79861, 0.60184 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe99d59631e65d5, 0x3fe32e3277467d6b, // -0.80046, 0.59939 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9ac61f0d4e247, 0x3fe31a0e6da35e44, // -0.80229, 0.59693 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9bb5aa85f2098, 0x3fe305de9b921a94, // -0.80412, 0.59447 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9ca438080eadb, 0x3fe2f1a30d86773a, // -0.80594, 0.592 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // -0.80775, 0.58952 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9e7e56dcb45bd, 0x3fe2c908ef734e57, // -0.80956, 0.58704 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9f69e70ac75bc, 0x3fe2b4aa787764c4, // -0.81135, 0.58455 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea05476f967bb5, 0x3fe2a040779843fb, // -0.81314, 0.58206 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea13e0617e4ec7, 0x3fe28bcaf96d94ba, // -0.81493, 0.57956 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea22693d62ccb9, 0x3fe2774a0a961612, // -0.8167, 0.57706 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea30e1fa4cbf81, 0x3fe262bdb7b795a2, // -0.81847, 0.57455 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // -0.82023, 0.57204 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea4da2f385e997, 0x3fe23983189fdfd5, // -0.82198, 0.56952 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea5beb1e188375, 0x3fe224d4e5d5482e, // -0.82372, 0.567 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea6a230637623b, 0x3fe2101b81e0da78, // -0.82546, 0.56447 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea784aa31d3f55, 0x3fe1fb56f98b37b8, // -0.82718, 0.56193 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8661ec0ee133, 0x3fe1e68759a3e074, // -0.8289, 0.55939 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9468d85b20ae, 0x3fe1d1acaf012cc2, // -0.83062, 0.55685 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa25f5f5aee60, 0x3fe1bcc706804467, // -0.83232, 0.55429 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab045787157ff, 0x3fe1a7d66d0516e6, // -0.83402, 0.55174 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeabe1b1b0b8dac, 0x3fe192daef7a5386, // -0.83571, 0.54918 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfeacbe03ea0e73b, 0x3fe17dd49ad16161, // -0.83739, 0.54661 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfead994dab2e979, 0x3fe168c37c025764, // -0.83906, 0.54404 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeae738e6cd4b67, 0x3fe153a7a00bf453, // -0.84073, 0.54146 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeaf4cc5a85fb73, 0x3fe13e8113f396c1, // -0.84238, 0.53888 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb024f2d7d24a9, 0x3fe1294fe4c5350a, // -0.84403, 0.53629 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb0fc1575d33db, 0x3fe114141f935545, // -0.84567, 0.5337 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb1d22cfdadcc6, 0x3fe0fecdd1770537, // -0.84731, 0.5311 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb2a738eb51f33, 0x3fe0e97d078fd23b, // -0.84893, 0.5285 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb37b38bb54c09, 0x3fe0d421cf03c12b, // -0.85055, 0.5259 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb44e2beaf0a61, 0x3fe0bebc34ff4646, // -0.85216, 0.52328 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb52011f805c92, 0x3fe0a94c46b53d0b, // -0.85376, 0.52067 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb5f0ea611a532, 0x3fe093d2115ee018, // -0.85535, 0.51804 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb6c0b4a55ac17, 0x3fe07e4da23bc102, // -0.85694, 0.51542 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb78f70449a34b, 0x3fe068bf0691c028, // -0.85852, 0.51279 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb85d1cbf52c02, 0x3fe053264bad0483, // -0.86009, 0.51015 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb929b996a5b7f, 0x3fe03d837edff370, // -0.86165, 0.50751 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeb9f5464c5bffc, 0x3fe027d6ad83287e, // -0.8632, 0.50486 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebabfc262e6586, 0x3fe0121fe4f56d2c, // -0.86474, 0.50221 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebb892d5d5dad5, 0x3fdff8be6537615e, // -0.86628, 0.49956 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebc5186bf8361d, 0x3fdfcd2947c1ff57, // -0.86781, 0.4969 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // -0.86933, 0.49423 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebddf02cd2b983, 0x3fdf75c44e26a852, // -0.87084, 0.49156 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebea424837de6d, 0x3fdf49f4a7e97729, // -0.87235, 0.48889 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebf6832b71ec5b, 0x3fdf1e11b4bbc35c, // -0.87384, 0.48621 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec02b2cef1e641, 0x3fdef21b8fafd3b5, // -0.87533, 0.48353 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec0ed12b3372e9, 0x3fdec61253e3c61b, // -0.87681, 0.48084 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec1ade38bce19b, 0x3fde99f61c817eda, // -0.87828, 0.47815 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec26d9f01f2eaf, 0x3fde6dc704be97e2, // -0.87974, 0.47545 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec32c449f60831, 0x3fde418527dc4ffa, // -0.8812, 0.47275 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec3e9d3ee7d262, 0x3fde1530a12779f4, // -0.88264, 0.47004 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // -0.88408, 0.46733 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec561adceb743e, 0x3fddbc5003b2edf8, // -0.88551, 0.46462 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec61bf777fcc48, 0x3fdd8fc423c62a25, // -0.88693, 0.4619 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec6d5290341eb2, 0x3fdd632607ac9aa9, // -0.88835, 0.45918 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec78d41fe4a267, 0x3fdd3675caebf962, // -0.88975, 0.45645 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec84441f785f61, 0x3fdd09b389152ec1, // -0.89115, 0.45372 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec8fa287e13305, 0x3fdcdcdf5dc440ce, // -0.89253, 0.45098 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfec9aef521bd480, 0x3fdcaff964a0421d, // -0.89391, 0.44824 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfeca62a772fd919, 0x3fdc8301b95b40c2, // -0.89528, 0.4455 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb153f02fb87d, 0x3fdc55f877b23537, // -0.89665, 0.44275 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecbc6bb638d10b, 0x3fdc28ddbb6cf145, // -0.898, 0.43999 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecc771c2736c09, 0x3fdbfbb1a05e0edc, // -0.89935, 0.43724 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd2660e12c1e6, 0x3fdbce744262deee, // -0.90068, 0.43448 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfecdd489254fe65, 0x3fdba125bd63583e, // -0.90201, 0.43171 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfece819488344ce, 0x3fdb73c62d520624, // -0.90333, 0.42894 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf2d829f1b40e, 0x3fdb4655ae2bf757, // -0.90464, 0.42617 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfecfd852fff6ad4, 0x3fdb18d45bf8aca6, // -0.90595, 0.42339 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed082054168bac, 0x3fdaeb4252ca07ab, // -0.90724, 0.42061 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed12a98fac410c, 0x3fdabd9faebc3980, // -0.90853, 0.41782 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed1d20dc40c15c, 0x3fda8fec8bf5b166, // -0.90981, 0.41503 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2786335f52fc, 0x3fda622906a70b63, // -0.91107, 0.41224 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed31d98e9e503a, 0x3fda34553b0afee5, // -0.91234, 0.40944 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed3c1ae79f2b4e, 0x3fda067145664d57, // -0.91359, 0.40664 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed464a380e7242, 0x3fd9d87d4207b0ab, // -0.91483, 0.40384 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed506779a3d2d9, 0x3fd9aa794d47c9ee, // -0.91606, 0.40103 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5a72a6221e73, 0x3fd97c6583890fc2, // -0.91729, 0.39822 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed646bb7574de5, 0x3fd94e420137bce3, // -0.91851, 0.3954 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed6e52a71c8547, 0x3fd9200ee2c9be97, // -0.91972, 0.39258 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed78276f5617c6, 0x3fd8f1cc44bea329, // -0.92092, 0.38976 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed81ea09f38b63, 0x3fd8c37a439f884f, // -0.92211, 0.38693 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed8b9a70ef9cb4, 0x3fd89518fbff098e, // -0.92329, 0.3841 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed95389e50429b, 0x3fd866a88a792ea0, // -0.92447, 0.38127 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfed9ec48c26b1f3, 0x3fd838290bb359c8, // -0.92563, 0.37843 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfeda83e348f613b, 0x3fd8099a9c5c362d, // -0.92679, 0.37559 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb1a591b20c38, 0x3fd7dafd592ba621, // -0.92794, 0.37274 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbafa9dc1b78d, 0x3fd7ac515ee2b172, // -0.92907, 0.36989 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc43d52fcb453, 0x3fd77d96ca4b73a6, // -0.93021, 0.36704 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // -0.93133, 0.36418 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfedd68ba2267a25, 0x3fd71ff6458782ec, // -0.93244, 0.36133 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeddf9730ca837b, 0x3fd6f1108f1bc9c5, // -0.93354, 0.35846 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfede890520465ce, 0x3fd6c21cb1e39771, // -0.93464, 0.3556 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf177004b2534, 0x3fd6931acad55f51, // -0.93573, 0.35273 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfa4b3621271d, 0x3fd6640af6f03d9e, // -0.9368, 0.34986 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee030cee1435b8, 0x3fd634ed533be58e, // -0.93787, 0.34698 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee0bbc22bd8349, 0x3fd605c1fcc88f63, // -0.93893, 0.3441 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee1458cec1ad83, 0x3fd5d68910aee686, // -0.93998, 0.34122 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // -0.94103, 0.33833 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee255a77a63bb8, 0x3fd577eeec151e47, // -0.94206, 0.33545 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee2dbf6a0911d9, 0x3fd5488dedeff3be, // -0.94308, 0.33255 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3611becbaf69, 0x3fd5191fceda3c35, // -0.9441, 0.32966 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee3e5170cbfc46, 0x3fd4e9a4ac15d520, // -0.94511, 0.32676 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee467e7af35f23, 0x3fd4ba1ca2eca31c, // -0.94611, 0.32386 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee4e98d836c0af, 0x3fd48a87d0b07fd7, // -0.94709, 0.32096 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee56a083968eb1, 0x3fd45ae652bb2800, // -0.94807, 0.31805 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee5e95781ebf1c, 0x3fd42b38466e2928, // -0.94905, 0.31514 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // -0.95001, 0.31222 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee6e472911da27, 0x3fd3cbb6f87a146e, // -0.95096, 0.30931 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee7603dbce74e9, 0x3fd39be3f1bc8aef, // -0.95191, 0.30639 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee7dadc456d850, 0x3fd36c04d27a4edf, // -0.95284, 0.30347 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee8544ddf0d075, 0x3fd33c19b83af207, // -0.95377, 0.30054 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee8cc923edc388, 0x3fd30c22c08d6a13, // -0.95469, 0.29762 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee943a91aab4b4, 0x3fd2dc200907fe51, // -0.95559, 0.29469 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9b99229046f8, 0x3fd2ac11af483572, // -0.95649, 0.29175 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea2e4d212c000, 0x3fd27bf7d0f2c346, // -0.95738, 0.28882 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeaa1d9bb20af3, 0x3fd24bd28bb37672, // -0.95827, 0.28588 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb1437af9bb34, 0x3fd21ba1fd3d2623, // -0.95914, 0.28294 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeeb8566b810f2a, 0x3fd1eb6643499fbb, // -0.96, 0.27999 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeebf5668eaf2ef, 0x3fd1bb1f7b999480, // -0.96086, 0.27705 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec6436ee60309, 0x3fd18acdc3f4873a, // -0.9617, 0.2741 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeecd1d792c8f10, 0x3fd15a713a28b9d9, // -0.96254, 0.27115 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed3e483849c51, 0x3fd12a09fc0b1b12, // -0.96337, 0.26819 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeda9889bfe86a, 0x3fd0f998277733f7, // -0.96418, 0.26523 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee13987bbebdc, 0x3fd0c91bda4f158d, // -0.96499, 0.26227 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeee7c77961dc9e, 0x3fd09895327b465e, // -0.96579, 0.25931 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeeee425aa6b09a, 0x3fd068044deab002, // -0.96658, 0.25635 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef4aa278b2032, 0x3fd037694a928cac, // -0.96737, 0.25338 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefafedc1ba8b7, 0x3fd006c4466e54af, // -0.96814, 0.25041 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef014074708ed3, 0x3fcfac2abeff57ff, // -0.9689, 0.24744 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef076eecade0fa, 0x3fcf4ab9679c9f5c, // -0.96966, 0.24447 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef0d8a410379c5, 0x3fcee934c2d006c7, // -0.9704, 0.24149 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef13926dad024e, 0x3fce879d0cc0fdaf, // -0.97114, 0.23851 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef19876ef1f486, 0x3fce25f281a2b684, // -0.97187, 0.23553 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef1f6941259d7a, 0x3fcdc4355db40195, // -0.97258, 0.23255 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2537e0a71f9f, 0x3fcd6265dd3f27e3, // -0.97329, 0.22957 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2af349e17507, 0x3fcd00843c99c5f9, // -0.97399, 0.22658 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef309b794b719f, 0x3fcc9e90b824a6a9, // -0.97468, 0.22359 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef36306b67c556, 0x3fcc3c8b8c4b9dd7, // -0.97536, 0.2206 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3bb21cc4fe47, 0x3fcbda74f5856330, // -0.97604, 0.2176 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef412089fd8adc, 0x3fcb784d30536cda, // -0.9767, 0.21461 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef467bafb7bbe0, 0x3fcb16147941ca2a, // -0.97735, 0.21161 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // -0.978, 0.20861 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef50f81785c6b9, 0x3fca517127e3dabc, // -0.97863, 0.20561 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef56195321c090, 0x3fc9ef0706e35a35, // -0.97926, 0.20261 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // -0.97988, 0.1996 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6021c9f148c2, 0x3fc92a0303c8194f, // -0.98048, 0.19659 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6508fef47bd5, 0x3fc8c7699b34ca7e, // -0.98108, 0.19359 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef69dcd652f5de, 0x3fc864c0e9b2b6cf, // -0.98167, 0.19057 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef6e9d4d1262ca, 0x3fc802092c1d744b, // -0.98225, 0.18756 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef734a60446279, 0x3fc79f429f59e11d, // -0.98282, 0.18455 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef77e40d068a90, 0x3fc73c6d8055fe0a, // -0.98339, 0.18153 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7c6a50826840, 0x3fc6d98a0c08c8da, // -0.98394, 0.17851 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef80dd27ed8204, 0x3fc676987f7216b8, // -0.98448, 0.17549 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef853c9089595e, 0x3fc61399179a6e94, // -0.98501, 0.17247 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef898887a36c84, 0x3fc5b08c1192e381, // -0.98554, 0.16945 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8dc10a95380d, 0x3fc54d71aa74ef02, // -0.98605, 0.16643 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef91e616c43891, 0x3fc4ea4a1f624b61, // -0.98656, 0.1634 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef95f7a9a1ec47, 0x3fc48715ad84cdf5, // -0.98706, 0.16037 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef99f5c0abd496, 0x3fc423d4920e4166, // -0.98754, 0.15734 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9de0596b77a3, 0x3fc3c0870a383ff6, // -0.98802, 0.15431 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa1b7717661d5, 0x3fc35d2d53440db2, // -0.98849, 0.15128 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa57b066e2754, 0x3fc2f9c7aa7a72af, // -0.98895, 0.14825 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefa92b1600657c, 0x3fc296564d2b953e, // -0.9894, 0.14521 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefacc79de6c44f, 0x3fc232d978aed413, // -0.98984, 0.14218 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb0509be6f7db, 0x3fc1cf516a62a077, // -0.99027, 0.13914 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb3c60dd2c199, 0x3fc16bbe5fac5865, // -0.9907, 0.1361 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb727f187f1c7, 0x3fc1082095f820b0, // -0.99111, 0.13306 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefba7644f068b5, 0x3fc0a4784ab8bf1d, // -0.99151, 0.13002 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbdb106021816, 0x3fc040c5bb67747e, // -0.99191, 0.12698 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc0d832bf043a, 0x3fbfba124b07ad85, // -0.99229, 0.12393 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc3ebc935454c, 0x3fbef2858d27561b, // -0.99267, 0.12089 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc6ebc77f0887, 0x3fbe2ae5b8457f77, // -0.99303, 0.11784 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefc9d82bc2915e, 0x3fbd633347858ce4, // -0.99339, 0.11479 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefccb0f4323aa3, 0x3fbc9b6eb6165c42, // -0.99374, 0.11175 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefcf761f0c77a3, 0x3fbbd3987f31fa0e, // -0.99407, 0.1087 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd227aa9bd53b, 0x3fbb0bb11e1d5559, // -0.9944, 0.10565 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd4c59536fae4, 0x3fba43b90e27f3c4, // -0.99472, 0.1026 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd74fdd40abbf, 0x3fb97bb0caaba56f, // -0.99503, 0.099544 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefd9c68127c78c, 0x3fb8b398cf0c38e0, // -0.99533, 0.09649 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdc297f674ba9, 0x3fb7eb7196b72ee4, // -0.99563, 0.093436 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefde78d68653fd, 0x3fb7233b9d236e71, // -0.99591, 0.090381 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe0b485181be3, 0x3fb65af75dd0f87b, // -0.99618, 0.087326 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe2dc89bbff08, 0x3fb592a554489bc8, // -0.99644, 0.084269 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // -0.9967, 0.081211 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe6f18ff42c84, 0x3fb401d9d0e3a507, // -0.99694, 0.078153 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe8de8f03d75c, 0x3fb339614e41ffa5, // -0.99718, 0.075094 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeab7df1c6005, 0x3fb270dcefdfc45b, // -0.9974, 0.072035 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefec7d7f19cffc, 0x3fb1a84d316d4f8a, // -0.99762, 0.068974 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefee2f6de455ba, 0x3fb0dfb28ea201e6, // -0.99783, 0.065913 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfefefcdaa704562, 0x3fb0170d833bf421, // -0.99802, 0.062852 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff15833be1965, 0x3fae9cbd15ff5527, // -0.99821, 0.05979 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff2cf08da7321, 0x3fad0b4c436f91d0, // -0.99839, 0.056727 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff43228de1b77, 0x3fab79c986698b78, // -0.99856, 0.053664 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff58192ee0358, 0x3fa9e835d6993c87, // -0.99872, 0.0506 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff6bd463b444d, 0x3fa856922bb513c1, // -0.99887, 0.047535 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff7e5420320f9, 0x3fa6c4df7d7d5b84, // -0.99901, 0.044471 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff8f9858f058b, 0x3fa5331ec3bba0eb, // -0.99914, 0.041406 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeff9fa10348837, 0x3fa3a150f6421afc, // -0.99926, 0.03834 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffae6e1556998, 0x3fa20f770ceb11c6, // -0.99938, 0.035274 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffbbff85f9515, 0x3fa07d91ff984580, // -0.99948, 0.032208 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffc8554cd213a, 0x3f9dd7458c64ab39, // -0.99958, 0.029142 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd36f624500c, 0x3f9ab354b1504fca, // -0.99966, 0.026075 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffdd4dbf78f52, 0x3f978f535ddc9f03, // -0.99974, 0.023008 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe5f05e578db, 0x3f946b4381fce81c, // -0.9998, 0.01994 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfeffed57398d2b7, 0x3f9147270dad7132, // -0.99986, 0.016873 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff3824c88f6f, 0x3f8c45ffe1e48ad9, // -0.9999, 0.013805 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefff871937ce2f, 0x3f85fda037ac05e0, // -0.99994, 0.010738 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffc250b5daef, 0x3f7f6a65f9a2a3c5, // -0.99997, 0.0076698 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfefffe9cb1e2e8d, 0x3f72d97822f996bc, // -0.99999, 0.0046019 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbfeffffd88586ee6, 0x3f5921faaee6472d, // -1, 0.001534 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffffd88586ee6, 0xbf5921faaee6472d, // -1, -0.001534 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffe9cb1e2e8d, 0xbf72d97822f996bc, // -0.99999,-0.0046019 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffc250b5daef, 0xbf7f6a65f9a2a3c5, // -0.99997,-0.0076698 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff871937ce2f, 0xbf85fda037ac05e0, // -0.99994, -0.010738 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff3824c88f6f, 0xbf8c45ffe1e48ad9, // -0.9999, -0.013805 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffed57398d2b7, 0xbf9147270dad7132, // -0.99986, -0.016873 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe5f05e578db, 0xbf946b4381fce81c, // -0.9998, -0.01994 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffdd4dbf78f52, 0xbf978f535ddc9f03, // -0.99974, -0.023008 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffd36f624500c, 0xbf9ab354b1504fca, // -0.99966, -0.026075 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc8554cd213a, 0xbf9dd7458c64ab39, // -0.99958, -0.029142 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffbbff85f9515, 0xbfa07d91ff984580, // -0.99948, -0.032208 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffae6e1556998, 0xbfa20f770ceb11c6, // -0.99938, -0.035274 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff9fa10348837, 0xbfa3a150f6421afc, // -0.99926, -0.03834 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff8f9858f058b, 0xbfa5331ec3bba0eb, // -0.99914, -0.041406 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff7e5420320f9, 0xbfa6c4df7d7d5b84, // -0.99901, -0.044471 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff6bd463b444d, 0xbfa856922bb513c1, // -0.99887, -0.047535 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff58192ee0358, 0xbfa9e835d6993c87, // -0.99872, -0.0506 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff43228de1b77, 0xbfab79c986698b78, // -0.99856, -0.053664 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff2cf08da7321, 0xbfad0b4c436f91d0, // -0.99839, -0.056727 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff15833be1965, 0xbfae9cbd15ff5527, // -0.99821, -0.05979 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefefcdaa704562, 0xbfb0170d833bf421, // -0.99802, -0.062852 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefee2f6de455ba, 0xbfb0dfb28ea201e6, // -0.99783, -0.065913 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefec7d7f19cffc, 0xbfb1a84d316d4f8a, // -0.99762, -0.068974 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefeab7df1c6005, 0xbfb270dcefdfc45b, // -0.9974, -0.072035 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe8de8f03d75c, 0xbfb339614e41ffa5, // -0.99718, -0.075094 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe6f18ff42c84, 0xbfb401d9d0e3a507, // -0.99694, -0.078153 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // -0.9967, -0.081211 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe2dc89bbff08, 0xbfb592a554489bc8, // -0.99644, -0.084269 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefe0b485181be3, 0xbfb65af75dd0f87b, // -0.99618, -0.087326 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefde78d68653fd, 0xbfb7233b9d236e71, // -0.99591, -0.090381 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdc297f674ba9, 0xbfb7eb7196b72ee4, // -0.99563, -0.093436 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd9c68127c78c, 0xbfb8b398cf0c38e0, // -0.99533, -0.09649 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd74fdd40abbf, 0xbfb97bb0caaba56f, // -0.99503, -0.099544 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd4c59536fae4, 0xbfba43b90e27f3c4, // -0.99472, -0.1026 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd227aa9bd53b, 0xbfbb0bb11e1d5559, // -0.9944, -0.10565 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefcf761f0c77a3, 0xbfbbd3987f31fa0e, // -0.99407, -0.1087 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefccb0f4323aa3, 0xbfbc9b6eb6165c42, // -0.99374, -0.11175 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc9d82bc2915e, 0xbfbd633347858ce4, // -0.99339, -0.11479 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc6ebc77f0887, 0xbfbe2ae5b8457f77, // -0.99303, -0.11784 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc3ebc935454c, 0xbfbef2858d27561b, // -0.99267, -0.12089 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefc0d832bf043a, 0xbfbfba124b07ad85, // -0.99229, -0.12393 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbdb106021816, 0xbfc040c5bb67747e, // -0.99191, -0.12698 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefba7644f068b5, 0xbfc0a4784ab8bf1d, // -0.99151, -0.13002 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb727f187f1c7, 0xbfc1082095f820b0, // -0.99111, -0.13306 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb3c60dd2c199, 0xbfc16bbe5fac5865, // -0.9907, -0.1361 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefb0509be6f7db, 0xbfc1cf516a62a077, // -0.99027, -0.13914 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefacc79de6c44f, 0xbfc232d978aed413, // -0.98984, -0.14218 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa92b1600657c, 0xbfc296564d2b953e, // -0.9894, -0.14521 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa57b066e2754, 0xbfc2f9c7aa7a72af, // -0.98895, -0.14825 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfefa1b7717661d5, 0xbfc35d2d53440db2, // -0.98849, -0.15128 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9de0596b77a3, 0xbfc3c0870a383ff6, // -0.98802, -0.15431 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef99f5c0abd496, 0xbfc423d4920e4166, // -0.98754, -0.15734 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef95f7a9a1ec47, 0xbfc48715ad84cdf5, // -0.98706, -0.16037 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef91e616c43891, 0xbfc4ea4a1f624b61, // -0.98656, -0.1634 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8dc10a95380d, 0xbfc54d71aa74ef02, // -0.98605, -0.16643 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef898887a36c84, 0xbfc5b08c1192e381, // -0.98554, -0.16945 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef853c9089595e, 0xbfc61399179a6e94, // -0.98501, -0.17247 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef80dd27ed8204, 0xbfc676987f7216b8, // -0.98448, -0.17549 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7c6a50826840, 0xbfc6d98a0c08c8da, // -0.98394, -0.17851 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef77e40d068a90, 0xbfc73c6d8055fe0a, // -0.98339, -0.18153 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef734a60446279, 0xbfc79f429f59e11d, // -0.98282, -0.18455 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6e9d4d1262ca, 0xbfc802092c1d744b, // -0.98225, -0.18756 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef69dcd652f5de, 0xbfc864c0e9b2b6cf, // -0.98167, -0.19057 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6508fef47bd5, 0xbfc8c7699b34ca7e, // -0.98108, -0.19359 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef6021c9f148c2, 0xbfc92a0303c8194f, // -0.98048, -0.19659 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // -0.97988, -0.1996 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef56195321c090, 0xbfc9ef0706e35a35, // -0.97926, -0.20261 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef50f81785c6b9, 0xbfca517127e3dabc, // -0.97863, -0.20561 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // -0.978, -0.20861 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef467bafb7bbe0, 0xbfcb16147941ca2a, // -0.97735, -0.21161 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef412089fd8adc, 0xbfcb784d30536cda, // -0.9767, -0.21461 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef3bb21cc4fe47, 0xbfcbda74f5856330, // -0.97604, -0.2176 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef36306b67c556, 0xbfcc3c8b8c4b9dd7, // -0.97536, -0.2206 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef309b794b719f, 0xbfcc9e90b824a6a9, // -0.97468, -0.22359 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2af349e17507, 0xbfcd00843c99c5f9, // -0.97399, -0.22658 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2537e0a71f9f, 0xbfcd6265dd3f27e3, // -0.97329, -0.22957 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1f6941259d7a, 0xbfcdc4355db40195, // -0.97258, -0.23255 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef19876ef1f486, 0xbfce25f281a2b684, // -0.97187, -0.23553 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef13926dad024e, 0xbfce879d0cc0fdaf, // -0.97114, -0.23851 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0d8a410379c5, 0xbfcee934c2d006c7, // -0.9704, -0.24149 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef076eecade0fa, 0xbfcf4ab9679c9f5c, // -0.96966, -0.24447 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfef014074708ed3, 0xbfcfac2abeff57ff, // -0.9689, -0.24744 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeefafedc1ba8b7, 0xbfd006c4466e54af, // -0.96814, -0.25041 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef4aa278b2032, 0xbfd037694a928cac, // -0.96737, -0.25338 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeee425aa6b09a, 0xbfd068044deab002, // -0.96658, -0.25635 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee7c77961dc9e, 0xbfd09895327b465e, // -0.96579, -0.25931 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeee13987bbebdc, 0xbfd0c91bda4f158d, // -0.96499, -0.26227 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeeda9889bfe86a, 0xbfd0f998277733f7, // -0.96418, -0.26523 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed3e483849c51, 0xbfd12a09fc0b1b12, // -0.96337, -0.26819 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeecd1d792c8f10, 0xbfd15a713a28b9d9, // -0.96254, -0.27115 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec6436ee60309, 0xbfd18acdc3f4873a, // -0.9617, -0.2741 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebf5668eaf2ef, 0xbfd1bb1f7b999480, // -0.96086, -0.27705 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb8566b810f2a, 0xbfd1eb6643499fbb, // -0.96, -0.27999 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeb1437af9bb34, 0xbfd21ba1fd3d2623, // -0.95914, -0.28294 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeeaa1d9bb20af3, 0xbfd24bd28bb37672, // -0.95827, -0.28588 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfeea2e4d212c000, 0xbfd27bf7d0f2c346, // -0.95738, -0.28882 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9b99229046f8, 0xbfd2ac11af483572, // -0.95649, -0.29175 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee943a91aab4b4, 0xbfd2dc200907fe51, // -0.95559, -0.29469 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee8cc923edc388, 0xbfd30c22c08d6a13, // -0.95469, -0.29762 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee8544ddf0d075, 0xbfd33c19b83af207, // -0.95377, -0.30054 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7dadc456d850, 0xbfd36c04d27a4edf, // -0.95284, -0.30347 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7603dbce74e9, 0xbfd39be3f1bc8aef, // -0.95191, -0.30639 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6e472911da27, 0xbfd3cbb6f87a146e, // -0.95096, -0.30931 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // -0.95001, -0.31222 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5e95781ebf1c, 0xbfd42b38466e2928, // -0.94905, -0.31514 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee56a083968eb1, 0xbfd45ae652bb2800, // -0.94807, -0.31805 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4e98d836c0af, 0xbfd48a87d0b07fd7, // -0.94709, -0.32096 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee467e7af35f23, 0xbfd4ba1ca2eca31c, // -0.94611, -0.32386 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3e5170cbfc46, 0xbfd4e9a4ac15d520, // -0.94511, -0.32676 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee3611becbaf69, 0xbfd5191fceda3c35, // -0.9441, -0.32966 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee2dbf6a0911d9, 0xbfd5488dedeff3be, // -0.94308, -0.33255 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee255a77a63bb8, 0xbfd577eeec151e47, // -0.94206, -0.33545 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // -0.94103, -0.33833 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee1458cec1ad83, 0xbfd5d68910aee686, // -0.93998, -0.34122 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0bbc22bd8349, 0xbfd605c1fcc88f63, // -0.93893, -0.3441 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfee030cee1435b8, 0xbfd634ed533be58e, // -0.93787, -0.34698 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedfa4b3621271d, 0xbfd6640af6f03d9e, // -0.9368, -0.34986 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfedf177004b2534, 0xbfd6931acad55f51, // -0.93573, -0.35273 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede890520465ce, 0xbfd6c21cb1e39771, // -0.93464, -0.3556 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddf9730ca837b, 0xbfd6f1108f1bc9c5, // -0.93354, -0.35846 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd68ba2267a25, 0xbfd71ff6458782ec, // -0.93244, -0.36133 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // -0.93133, -0.36418 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedc43d52fcb453, 0xbfd77d96ca4b73a6, // -0.93021, -0.36704 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedbafa9dc1b78d, 0xbfd7ac515ee2b172, // -0.92907, -0.36989 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedb1a591b20c38, 0xbfd7dafd592ba621, // -0.92794, -0.37274 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda83e348f613b, 0xbfd8099a9c5c362d, // -0.92679, -0.37559 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9ec48c26b1f3, 0xbfd838290bb359c8, // -0.92563, -0.37843 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed95389e50429b, 0xbfd866a88a792ea0, // -0.92447, -0.38127 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed8b9a70ef9cb4, 0xbfd89518fbff098e, // -0.92329, -0.3841 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed81ea09f38b63, 0xbfd8c37a439f884f, // -0.92211, -0.38693 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed78276f5617c6, 0xbfd8f1cc44bea329, // -0.92092, -0.38976 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed6e52a71c8547, 0xbfd9200ee2c9be97, // -0.91972, -0.39258 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed646bb7574de5, 0xbfd94e420137bce3, // -0.91851, -0.3954 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed5a72a6221e73, 0xbfd97c6583890fc2, // -0.91729, -0.39822 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed506779a3d2d9, 0xbfd9aa794d47c9ee, // -0.91606, -0.40103 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed464a380e7242, 0xbfd9d87d4207b0ab, // -0.91483, -0.40384 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed3c1ae79f2b4e, 0xbfda067145664d57, // -0.91359, -0.40664 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed31d98e9e503a, 0xbfda34553b0afee5, // -0.91234, -0.40944 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2786335f52fc, 0xbfda622906a70b63, // -0.91107, -0.41224 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed1d20dc40c15c, 0xbfda8fec8bf5b166, // -0.90981, -0.41503 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed12a98fac410c, 0xbfdabd9faebc3980, // -0.90853, -0.41782 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed082054168bac, 0xbfdaeb4252ca07ab, // -0.90724, -0.42061 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecfd852fff6ad4, 0xbfdb18d45bf8aca6, // -0.90595, -0.42339 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfecf2d829f1b40e, 0xbfdb4655ae2bf757, // -0.90464, -0.42617 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece819488344ce, 0xbfdb73c62d520624, // -0.90333, -0.42894 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecdd489254fe65, 0xbfdba125bd63583e, // -0.90201, -0.43171 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecd2660e12c1e6, 0xbfdbce744262deee, // -0.90068, -0.43448 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc771c2736c09, 0xbfdbfbb1a05e0edc, // -0.89935, -0.43724 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecbc6bb638d10b, 0xbfdc28ddbb6cf145, // -0.898, -0.43999 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecb153f02fb87d, 0xbfdc55f877b23537, // -0.89665, -0.44275 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca62a772fd919, 0xbfdc8301b95b40c2, // -0.89528, -0.4455 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec9aef521bd480, 0xbfdcaff964a0421d, // -0.89391, -0.44824 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec8fa287e13305, 0xbfdcdcdf5dc440ce, // -0.89253, -0.45098 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec84441f785f61, 0xbfdd09b389152ec1, // -0.89115, -0.45372 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec78d41fe4a267, 0xbfdd3675caebf962, // -0.88975, -0.45645 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec6d5290341eb2, 0xbfdd632607ac9aa9, // -0.88835, -0.45918 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec61bf777fcc48, 0xbfdd8fc423c62a25, // -0.88693, -0.4619 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec561adceb743e, 0xbfddbc5003b2edf8, // -0.88551, -0.46462 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // -0.88408, -0.46733 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec3e9d3ee7d262, 0xbfde1530a12779f4, // -0.88264, -0.47004 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec32c449f60831, 0xbfde418527dc4ffa, // -0.8812, -0.47275 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec26d9f01f2eaf, 0xbfde6dc704be97e2, // -0.87974, -0.47545 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec1ade38bce19b, 0xbfde99f61c817eda, // -0.87828, -0.47815 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec0ed12b3372e9, 0xbfdec61253e3c61b, // -0.87681, -0.48084 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfec02b2cef1e641, 0xbfdef21b8fafd3b5, // -0.87533, -0.48353 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf6832b71ec5b, 0xbfdf1e11b4bbc35c, // -0.87384, -0.48621 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebea424837de6d, 0xbfdf49f4a7e97729, // -0.87235, -0.48889 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebddf02cd2b983, 0xbfdf75c44e26a852, // -0.87084, -0.49156 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // -0.86933, -0.49423 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebc5186bf8361d, 0xbfdfcd2947c1ff57, // -0.86781, -0.4969 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb892d5d5dad5, 0xbfdff8be6537615e, // -0.86628, -0.49956 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfebabfc262e6586, 0xbfe0121fe4f56d2c, // -0.86474, -0.50221 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb9f5464c5bffc, 0xbfe027d6ad83287e, // -0.8632, -0.50486 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb929b996a5b7f, 0xbfe03d837edff370, // -0.86165, -0.50751 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb85d1cbf52c02, 0xbfe053264bad0483, // -0.86009, -0.51015 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb78f70449a34b, 0xbfe068bf0691c028, // -0.85852, -0.51279 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb6c0b4a55ac17, 0xbfe07e4da23bc102, // -0.85694, -0.51542 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5f0ea611a532, 0xbfe093d2115ee018, // -0.85535, -0.51804 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb52011f805c92, 0xbfe0a94c46b53d0b, // -0.85376, -0.52067 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb44e2beaf0a61, 0xbfe0bebc34ff4646, // -0.85216, -0.52328 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb37b38bb54c09, 0xbfe0d421cf03c12b, // -0.85055, -0.5259 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb2a738eb51f33, 0xbfe0e97d078fd23b, // -0.84893, -0.5285 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb1d22cfdadcc6, 0xbfe0fecdd1770537, // -0.84731, -0.5311 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb0fc1575d33db, 0xbfe114141f935545, // -0.84567, -0.5337 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeb024f2d7d24a9, 0xbfe1294fe4c5350a, // -0.84403, -0.53629 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaf4cc5a85fb73, 0xbfe13e8113f396c1, // -0.84238, -0.53888 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae738e6cd4b67, 0xbfe153a7a00bf453, // -0.84073, -0.54146 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead994dab2e979, 0xbfe168c37c025764, // -0.83906, -0.54404 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeacbe03ea0e73b, 0xbfe17dd49ad16161, // -0.83739, -0.54661 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeabe1b1b0b8dac, 0xbfe192daef7a5386, // -0.83571, -0.54918 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeab045787157ff, 0xbfe1a7d66d0516e6, // -0.83402, -0.55174 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfeaa25f5f5aee60, 0xbfe1bcc706804467, // -0.83232, -0.55429 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea9468d85b20ae, 0xbfe1d1acaf012cc2, // -0.83062, -0.55685 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea8661ec0ee133, 0xbfe1e68759a3e074, // -0.8289, -0.55939 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea784aa31d3f55, 0xbfe1fb56f98b37b8, // -0.82718, -0.56193 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea6a230637623b, 0xbfe2101b81e0da78, // -0.82546, -0.56447 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea5beb1e188375, 0xbfe224d4e5d5482e, // -0.82372, -0.567 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4da2f385e997, 0xbfe23983189fdfd5, // -0.82198, -0.56952 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // -0.82023, -0.57204 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea30e1fa4cbf81, 0xbfe262bdb7b795a2, // -0.81847, -0.57455 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea22693d62ccb9, 0xbfe2774a0a961612, // -0.8167, -0.57706 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea13e0617e4ec7, 0xbfe28bcaf96d94ba, // -0.81493, -0.57956 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfea05476f967bb5, 0xbfe2a040779843fb, // -0.81314, -0.58206 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9f69e70ac75bc, 0xbfe2b4aa787764c4, // -0.81135, -0.58455 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e7e56dcb45bd, 0xbfe2c908ef734e57, // -0.80956, -0.58704 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // -0.80775, -0.58952 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9ca438080eadb, 0xbfe2f1a30d86773a, // -0.80594, -0.592 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9bb5aa85f2098, 0xbfe305de9b921a94, // -0.80412, -0.59447 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9ac61f0d4e247, 0xbfe31a0e6da35e44, // -0.80229, -0.59693 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe99d59631e65d5, 0xbfe32e3277467d6b, // -0.80046, -0.59939 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe98e410881a600, 0xbfe3424aac0ef7d6, // -0.79861, -0.60184 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe97f18ea4e5c9e, 0xbfe35656ff9799ae, // -0.79676, -0.60429 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe96fe111ddfce0, 0xbfe36a576582831b, // -0.79491, -0.60673 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe960998893ad8c, 0xbfe37e4bd1792fe2, // -0.79304, -0.60917 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe9514257dc4335, 0xbfe39234372c7f04, // -0.79117, -0.6116 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe941db892e3a65, 0xbfe3a6108a54ba58, // -0.78929, -0.61402 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe932652609b1cf, 0xbfe3b9e0beb19e18, // -0.7874, -0.61644 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe922df37f8646a, 0xbfe3cda4c80a6076, // -0.78551, -0.61885 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe91349c88da398, 0xbfe3e15c9a2db922, // -0.7836, -0.62126 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe903a4e1665133, 0xbfe3f50828f1e8d2, // -0.78169, -0.62366 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8f3f08c28d9ac, 0xbfe408a76834c0c0, // -0.77978, -0.62606 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // -0.77785, -0.62845 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // -0.77592, -0.63083 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8c47758fa71cb, 0xbfe4433ad0117b1d, // -0.77398, -0.63321 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8b485aca2a468, 0xbfe456a858917046, // -0.77204, -0.63558 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe8a484c3031d50, 0xbfe46a095557a0f1, // -0.77008, -0.63794 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe89474a5fb0a84, 0xbfe47d5dba6fde01, // -0.76812, -0.6403 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe884555f72fa6b, 0xbfe490a57bedbcdf, // -0.76615, -0.64266 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // -0.76418, -0.645 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe863e97db3d95a, 0xbfe4b70ee48fb869, // -0.7622, -0.64735 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe8539cf67c9029, 0xbfe4ca30740218a3, // -0.76021, -0.64968 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe843416dc4cce2, 0xbfe4dd453076b064, // -0.75821, -0.65201 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // -0.75621, -0.65433 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe8225d803964e5, 0xbfe503480159ded2, // -0.75419, -0.65665 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe811d52faf94dc, 0xbfe51635fe5601d7, // -0.75218, -0.65896 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe8013e0638e795, 0xbfe52916f96f8388, // -0.75015, -0.66127 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7f0980e113978, 0xbfe53beae7012abe, // -0.74812, -0.66356 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // -0.74608, -0.66586 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7cf1fdacbf179, 0xbfe5616b6b204e6e, // -0.74403, -0.66814 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7be4db453a27c, 0xbfe57417ea8bb75c, // -0.74198, -0.67042 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // -0.73992, -0.67269 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79c7d8198e56e, 0xbfe599492a81ffbc, // -0.73785, -0.67496 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // -0.73578, -0.67722 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe77a730cbb9100, 0xbfe5be451f8bf980, // -0.7337, -0.67948 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe7695813b9b594, 0xbfe5d0af016ed1d4, // -0.73161, -0.68172 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe7582ea9b9a329, 0xbfe5e30b6e6877f3, // -0.72951, -0.68397 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe746f6d9516d59, 0xbfe5f55a5b2576f8, // -0.72741, -0.6862 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe735b0ad2009b2, 0xbfe6079bbc5aadfa, // -0.7253, -0.68843 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe7245c2fcd492a, 0xbfe619cf86c55702, // -0.72319, -0.69065 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe712f96c09d18d, 0xbfe62bf5af2b0dfd, // -0.72107, -0.69287 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe701886c8f16e6, 0xbfe63e0e2a59d7aa, // -0.71894, -0.69508 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6f0093c1f54de, 0xbfe65018ed28287f, // -0.7168, -0.69728 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6de7be585881d, 0xbfe66215ec74eb91, // -0.71466, -0.69947 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6cce07395679f, 0xbfe674051d27896c, // -0.71251, -0.70166 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6bb36f12b5e06, 0xbfe685e6742feeef, // -0.71035, -0.70385 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a97f692c82ea, 0xbfe697b9e686941c, // -0.70819, -0.70602 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe697b9e686941c, 0xbfe6a97f692c82ea, // -0.70602, -0.70819 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe685e6742feeef, 0xbfe6bb36f12b5e06, // -0.70385, -0.71035 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe674051d27896c, 0xbfe6cce07395679f, // -0.70166, -0.71251 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe66215ec74eb91, 0xbfe6de7be585881d, // -0.69947, -0.71466 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe65018ed28287f, 0xbfe6f0093c1f54de, // -0.69728, -0.7168 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63e0e2a59d7aa, 0xbfe701886c8f16e6, // -0.69508, -0.71894 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe62bf5af2b0dfd, 0xbfe712f96c09d18d, // -0.69287, -0.72107 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe619cf86c55702, 0xbfe7245c2fcd492a, // -0.69065, -0.72319 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe6079bbc5aadfa, 0xbfe735b0ad2009b2, // -0.68843, -0.7253 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5f55a5b2576f8, 0xbfe746f6d9516d59, // -0.6862, -0.72741 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5e30b6e6877f3, 0xbfe7582ea9b9a329, // -0.68397, -0.72951 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5d0af016ed1d4, 0xbfe7695813b9b594, // -0.68172, -0.73161 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5be451f8bf980, 0xbfe77a730cbb9100, // -0.67948, -0.7337 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // -0.67722, -0.73578 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe599492a81ffbc, 0xbfe79c7d8198e56e, // -0.67496, -0.73785 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // -0.67269, -0.73992 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe57417ea8bb75c, 0xbfe7be4db453a27c, // -0.67042, -0.74198 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5616b6b204e6e, 0xbfe7cf1fdacbf179, // -0.66814, -0.74403 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // -0.66586, -0.74608 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe53beae7012abe, 0xbfe7f0980e113978, // -0.66356, -0.74812 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe52916f96f8388, 0xbfe8013e0638e795, // -0.66127, -0.75015 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe51635fe5601d7, 0xbfe811d52faf94dc, // -0.65896, -0.75218 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe503480159ded2, 0xbfe8225d803964e5, // -0.65665, -0.75419 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // -0.65433, -0.75621 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4dd453076b064, 0xbfe843416dc4cce2, // -0.65201, -0.75821 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4ca30740218a3, 0xbfe8539cf67c9029, // -0.64968, -0.76021 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4b70ee48fb869, 0xbfe863e97db3d95a, // -0.64735, -0.7622 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // -0.645, -0.76418 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe490a57bedbcdf, 0xbfe884555f72fa6b, // -0.64266, -0.76615 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe47d5dba6fde01, 0xbfe89474a5fb0a84, // -0.6403, -0.76812 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe46a095557a0f1, 0xbfe8a484c3031d50, // -0.63794, -0.77008 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe456a858917046, 0xbfe8b485aca2a468, // -0.63558, -0.77204 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4433ad0117b1d, 0xbfe8c47758fa71cb, // -0.63321, -0.77398 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // -0.63083, -0.77592 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // -0.62845, -0.77785 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe408a76834c0c0, 0xbfe8f3f08c28d9ac, // -0.62606, -0.77978 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3f50828f1e8d2, 0xbfe903a4e1665133, // -0.62366, -0.78169 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3e15c9a2db922, 0xbfe91349c88da398, // -0.62126, -0.7836 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3cda4c80a6076, 0xbfe922df37f8646a, // -0.61885, -0.78551 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3b9e0beb19e18, 0xbfe932652609b1cf, // -0.61644, -0.7874 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3a6108a54ba58, 0xbfe941db892e3a65, // -0.61402, -0.78929 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe39234372c7f04, 0xbfe9514257dc4335, // -0.6116, -0.79117 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe37e4bd1792fe2, 0xbfe960998893ad8c, // -0.60917, -0.79304 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36a576582831b, 0xbfe96fe111ddfce0, // -0.60673, -0.79491 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe35656ff9799ae, 0xbfe97f18ea4e5c9e, // -0.60429, -0.79676 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe3424aac0ef7d6, 0xbfe98e410881a600, // -0.60184, -0.79861 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32e3277467d6b, 0xbfe99d59631e65d5, // -0.59939, -0.80046 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe31a0e6da35e44, 0xbfe9ac61f0d4e247, // -0.59693, -0.80229 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe305de9b921a94, 0xbfe9bb5aa85f2098, // -0.59447, -0.80412 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2f1a30d86773a, 0xbfe9ca438080eadb, // -0.592, -0.80594 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // -0.58952, -0.80775 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2c908ef734e57, 0xbfe9e7e56dcb45bd, // -0.58704, -0.80956 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2b4aa787764c4, 0xbfe9f69e70ac75bc, // -0.58455, -0.81135 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2a040779843fb, 0xbfea05476f967bb5, // -0.58206, -0.81314 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe28bcaf96d94ba, 0xbfea13e0617e4ec7, // -0.57956, -0.81493 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe2774a0a961612, 0xbfea22693d62ccb9, // -0.57706, -0.8167 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe262bdb7b795a2, 0xbfea30e1fa4cbf81, // -0.57455, -0.81847 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // -0.57204, -0.82023 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe23983189fdfd5, 0xbfea4da2f385e997, // -0.56952, -0.82198 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe224d4e5d5482e, 0xbfea5beb1e188375, // -0.567, -0.82372 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe2101b81e0da78, 0xbfea6a230637623b, // -0.56447, -0.82546 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1fb56f98b37b8, 0xbfea784aa31d3f55, // -0.56193, -0.82718 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1e68759a3e074, 0xbfea8661ec0ee133, // -0.55939, -0.8289 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1d1acaf012cc2, 0xbfea9468d85b20ae, // -0.55685, -0.83062 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1bcc706804467, 0xbfeaa25f5f5aee60, // -0.55429, -0.83232 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe1a7d66d0516e6, 0xbfeab045787157ff, // -0.55174, -0.83402 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe192daef7a5386, 0xbfeabe1b1b0b8dac, // -0.54918, -0.83571 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe17dd49ad16161, 0xbfeacbe03ea0e73b, // -0.54661, -0.83739 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe168c37c025764, 0xbfead994dab2e979, // -0.54404, -0.83906 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe153a7a00bf453, 0xbfeae738e6cd4b67, // -0.54146, -0.84073 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe13e8113f396c1, 0xbfeaf4cc5a85fb73, // -0.53888, -0.84238 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe1294fe4c5350a, 0xbfeb024f2d7d24a9, // -0.53629, -0.84403 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe114141f935545, 0xbfeb0fc1575d33db, // -0.5337, -0.84567 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0fecdd1770537, 0xbfeb1d22cfdadcc6, // -0.5311, -0.84731 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0e97d078fd23b, 0xbfeb2a738eb51f33, // -0.5285, -0.84893 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0d421cf03c12b, 0xbfeb37b38bb54c09, // -0.5259, -0.85055 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0bebc34ff4646, 0xbfeb44e2beaf0a61, // -0.52328, -0.85216 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe0a94c46b53d0b, 0xbfeb52011f805c92, // -0.52067, -0.85376 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe093d2115ee018, 0xbfeb5f0ea611a532, // -0.51804, -0.85535 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe07e4da23bc102, 0xbfeb6c0b4a55ac17, // -0.51542, -0.85694 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe068bf0691c028, 0xbfeb78f70449a34b, // -0.51279, -0.85852 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe053264bad0483, 0xbfeb85d1cbf52c02, // -0.51015, -0.86009 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe03d837edff370, 0xbfeb929b996a5b7f, // -0.50751, -0.86165 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe027d6ad83287e, 0xbfeb9f5464c5bffc, // -0.50486, -0.8632 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe0121fe4f56d2c, 0xbfebabfc262e6586, // -0.50221, -0.86474 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdff8be6537615e, 0xbfebb892d5d5dad5, // -0.49956, -0.86628 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfcd2947c1ff57, 0xbfebc5186bf8361d, // -0.4969, -0.86781 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // -0.49423, -0.86933 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf75c44e26a852, 0xbfebddf02cd2b983, // -0.49156, -0.87084 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf49f4a7e97729, 0xbfebea424837de6d, // -0.48889, -0.87235 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // -0.48621, -0.87384 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdef21b8fafd3b5, 0xbfec02b2cef1e641, // -0.48353, -0.87533 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdec61253e3c61b, 0xbfec0ed12b3372e9, // -0.48084, -0.87681 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde99f61c817eda, 0xbfec1ade38bce19b, // -0.47815, -0.87828 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde6dc704be97e2, 0xbfec26d9f01f2eaf, // -0.47545, -0.87974 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde418527dc4ffa, 0xbfec32c449f60831, // -0.47275, -0.8812 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfde1530a12779f4, 0xbfec3e9d3ee7d262, // -0.47004, -0.88264 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // -0.46733, -0.88408 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfddbc5003b2edf8, 0xbfec561adceb743e, // -0.46462, -0.88551 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd8fc423c62a25, 0xbfec61bf777fcc48, // -0.4619, -0.88693 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd632607ac9aa9, 0xbfec6d5290341eb2, // -0.45918, -0.88835 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd3675caebf962, 0xbfec78d41fe4a267, // -0.45645, -0.88975 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdd09b389152ec1, 0xbfec84441f785f61, // -0.45372, -0.89115 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcdcdf5dc440ce, 0xbfec8fa287e13305, // -0.45098, -0.89253 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdcaff964a0421d, 0xbfec9aef521bd480, // -0.44824, -0.89391 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc8301b95b40c2, 0xbfeca62a772fd919, // -0.4455, -0.89528 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc55f877b23537, 0xbfecb153f02fb87d, // -0.44275, -0.89665 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc28ddbb6cf145, 0xbfecbc6bb638d10b, // -0.43999, -0.898 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbfbb1a05e0edc, 0xbfecc771c2736c09, // -0.43724, -0.89935 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbce744262deee, 0xbfecd2660e12c1e6, // -0.43448, -0.90068 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdba125bd63583e, 0xbfecdd489254fe65, // -0.43171, -0.90201 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb73c62d520624, 0xbfece819488344ce, // -0.42894, -0.90333 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb4655ae2bf757, 0xbfecf2d829f1b40e, // -0.42617, -0.90464 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb18d45bf8aca6, 0xbfecfd852fff6ad4, // -0.42339, -0.90595 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaeb4252ca07ab, 0xbfed082054168bac, // -0.42061, -0.90724 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdabd9faebc3980, 0xbfed12a98fac410c, // -0.41782, -0.90853 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda8fec8bf5b166, 0xbfed1d20dc40c15c, // -0.41503, -0.90981 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda622906a70b63, 0xbfed2786335f52fc, // -0.41224, -0.91107 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda34553b0afee5, 0xbfed31d98e9e503a, // -0.40944, -0.91234 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfda067145664d57, 0xbfed3c1ae79f2b4e, // -0.40664, -0.91359 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9d87d4207b0ab, 0xbfed464a380e7242, // -0.40384, -0.91483 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd9aa794d47c9ee, 0xbfed506779a3d2d9, // -0.40103, -0.91606 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd97c6583890fc2, 0xbfed5a72a6221e73, // -0.39822, -0.91729 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd94e420137bce3, 0xbfed646bb7574de5, // -0.3954, -0.91851 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd9200ee2c9be97, 0xbfed6e52a71c8547, // -0.39258, -0.91972 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8f1cc44bea329, 0xbfed78276f5617c6, // -0.38976, -0.92092 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8c37a439f884f, 0xbfed81ea09f38b63, // -0.38693, -0.92211 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd89518fbff098e, 0xbfed8b9a70ef9cb4, // -0.3841, -0.92329 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd866a88a792ea0, 0xbfed95389e50429b, // -0.38127, -0.92447 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd838290bb359c8, 0xbfed9ec48c26b1f3, // -0.37843, -0.92563 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd8099a9c5c362d, 0xbfeda83e348f613b, // -0.37559, -0.92679 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7dafd592ba621, 0xbfedb1a591b20c38, // -0.37274, -0.92794 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7ac515ee2b172, 0xbfedbafa9dc1b78d, // -0.36989, -0.92907 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd77d96ca4b73a6, 0xbfedc43d52fcb453, // -0.36704, -0.93021 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // -0.36418, -0.93133 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd71ff6458782ec, 0xbfedd68ba2267a25, // -0.36133, -0.93244 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6f1108f1bc9c5, 0xbfeddf9730ca837b, // -0.35846, -0.93354 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6c21cb1e39771, 0xbfede890520465ce, // -0.3556, -0.93464 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd6931acad55f51, 0xbfedf177004b2534, // -0.35273, -0.93573 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd6640af6f03d9e, 0xbfedfa4b3621271d, // -0.34986, -0.9368 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd634ed533be58e, 0xbfee030cee1435b8, // -0.34698, -0.93787 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd605c1fcc88f63, 0xbfee0bbc22bd8349, // -0.3441, -0.93893 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5d68910aee686, 0xbfee1458cec1ad83, // -0.34122, -0.93998 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // -0.33833, -0.94103 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd577eeec151e47, 0xbfee255a77a63bb8, // -0.33545, -0.94206 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd5488dedeff3be, 0xbfee2dbf6a0911d9, // -0.33255, -0.94308 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd5191fceda3c35, 0xbfee3611becbaf69, // -0.32966, -0.9441 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4e9a4ac15d520, 0xbfee3e5170cbfc46, // -0.32676, -0.94511 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4ba1ca2eca31c, 0xbfee467e7af35f23, // -0.32386, -0.94611 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd48a87d0b07fd7, 0xbfee4e98d836c0af, // -0.32096, -0.94709 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd45ae652bb2800, 0xbfee56a083968eb1, // -0.31805, -0.94807 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd42b38466e2928, 0xbfee5e95781ebf1c, // -0.31514, -0.94905 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // -0.31222, -0.95001 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3cbb6f87a146e, 0xbfee6e472911da27, // -0.30931, -0.95096 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd39be3f1bc8aef, 0xbfee7603dbce74e9, // -0.30639, -0.95191 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd36c04d27a4edf, 0xbfee7dadc456d850, // -0.30347, -0.95284 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd33c19b83af207, 0xbfee8544ddf0d075, // -0.30054, -0.95377 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd30c22c08d6a13, 0xbfee8cc923edc388, // -0.29762, -0.95469 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2dc200907fe51, 0xbfee943a91aab4b4, // -0.29469, -0.95559 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd2ac11af483572, 0xbfee9b99229046f8, // -0.29175, -0.95649 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd27bf7d0f2c346, 0xbfeea2e4d212c000, // -0.28882, -0.95738 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd24bd28bb37672, 0xbfeeaa1d9bb20af3, // -0.28588, -0.95827 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd21ba1fd3d2623, 0xbfeeb1437af9bb34, // -0.28294, -0.95914 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1eb6643499fbb, 0xbfeeb8566b810f2a, // -0.27999, -0.96 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1bb1f7b999480, 0xbfeebf5668eaf2ef, // -0.27705, -0.96086 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd18acdc3f4873a, 0xbfeec6436ee60309, // -0.2741, -0.9617 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd15a713a28b9d9, 0xbfeecd1d792c8f10, // -0.27115, -0.96254 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd12a09fc0b1b12, 0xbfeed3e483849c51, // -0.26819, -0.96337 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0f998277733f7, 0xbfeeda9889bfe86a, // -0.26523, -0.96418 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0c91bda4f158d, 0xbfeee13987bbebdc, // -0.26227, -0.96499 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd09895327b465e, 0xbfeee7c77961dc9e, // -0.25931, -0.96579 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd068044deab002, 0xbfeeee425aa6b09a, // -0.25635, -0.96658 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd037694a928cac, 0xbfeef4aa278b2032, // -0.25338, -0.96737 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfd006c4466e54af, 0xbfeefafedc1ba8b7, // -0.25041, -0.96814 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcfac2abeff57ff, 0xbfef014074708ed3, // -0.24744, -0.9689 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf4ab9679c9f5c, 0xbfef076eecade0fa, // -0.24447, -0.96966 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcee934c2d006c7, 0xbfef0d8a410379c5, // -0.24149, -0.9704 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce879d0cc0fdaf, 0xbfef13926dad024e, // -0.23851, -0.97114 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfce25f281a2b684, 0xbfef19876ef1f486, // -0.23553, -0.97187 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcdc4355db40195, 0xbfef1f6941259d7a, // -0.23255, -0.97258 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd6265dd3f27e3, 0xbfef2537e0a71f9f, // -0.22957, -0.97329 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcd00843c99c5f9, 0xbfef2af349e17507, // -0.22658, -0.97399 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc9e90b824a6a9, 0xbfef309b794b719f, // -0.22359, -0.97468 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc3c8b8c4b9dd7, 0xbfef36306b67c556, // -0.2206, -0.97536 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcbda74f5856330, 0xbfef3bb21cc4fe47, // -0.2176, -0.97604 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb784d30536cda, 0xbfef412089fd8adc, // -0.21461, -0.9767 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcb16147941ca2a, 0xbfef467bafb7bbe0, // -0.21161, -0.97735 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // -0.20861, -0.978 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca517127e3dabc, 0xbfef50f81785c6b9, // -0.20561, -0.97863 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9ef0706e35a35, 0xbfef56195321c090, // -0.20261, -0.97926 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // -0.1996, -0.97988 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc92a0303c8194f, 0xbfef6021c9f148c2, // -0.19659, -0.98048 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8c7699b34ca7e, 0xbfef6508fef47bd5, // -0.19359, -0.98108 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc864c0e9b2b6cf, 0xbfef69dcd652f5de, // -0.19057, -0.98167 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc802092c1d744b, 0xbfef6e9d4d1262ca, // -0.18756, -0.98225 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc79f429f59e11d, 0xbfef734a60446279, // -0.18455, -0.98282 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc73c6d8055fe0a, 0xbfef77e40d068a90, // -0.18153, -0.98339 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6d98a0c08c8da, 0xbfef7c6a50826840, // -0.17851, -0.98394 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc676987f7216b8, 0xbfef80dd27ed8204, // -0.17549, -0.98448 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc61399179a6e94, 0xbfef853c9089595e, // -0.17247, -0.98501 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc5b08c1192e381, 0xbfef898887a36c84, // -0.16945, -0.98554 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc54d71aa74ef02, 0xbfef8dc10a95380d, // -0.16643, -0.98605 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4ea4a1f624b61, 0xbfef91e616c43891, // -0.1634, -0.98656 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc48715ad84cdf5, 0xbfef95f7a9a1ec47, // -0.16037, -0.98706 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc423d4920e4166, 0xbfef99f5c0abd496, // -0.15734, -0.98754 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc3c0870a383ff6, 0xbfef9de0596b77a3, // -0.15431, -0.98802 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc35d2d53440db2, 0xbfefa1b7717661d5, // -0.15128, -0.98849 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2f9c7aa7a72af, 0xbfefa57b066e2754, // -0.14825, -0.98895 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc296564d2b953e, 0xbfefa92b1600657c, // -0.14521, -0.9894 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc232d978aed413, 0xbfefacc79de6c44f, // -0.14218, -0.98984 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc1cf516a62a077, 0xbfefb0509be6f7db, // -0.13914, -0.99027 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc16bbe5fac5865, 0xbfefb3c60dd2c199, // -0.1361, -0.9907 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc1082095f820b0, 0xbfefb727f187f1c7, // -0.13306, -0.99111 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc0a4784ab8bf1d, 0xbfefba7644f068b5, // -0.13002, -0.99151 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc040c5bb67747e, 0xbfefbdb106021816, // -0.12698, -0.99191 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbfba124b07ad85, 0xbfefc0d832bf043a, // -0.12393, -0.99229 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbef2858d27561b, 0xbfefc3ebc935454c, // -0.12089, -0.99267 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbe2ae5b8457f77, 0xbfefc6ebc77f0887, // -0.11784, -0.99303 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbd633347858ce4, 0xbfefc9d82bc2915e, // -0.11479, -0.99339 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc9b6eb6165c42, 0xbfefccb0f4323aa3, // -0.11175, -0.99374 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbbd3987f31fa0e, 0xbfefcf761f0c77a3, // -0.1087, -0.99407 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbb0bb11e1d5559, 0xbfefd227aa9bd53b, // -0.10565, -0.9944 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfba43b90e27f3c4, 0xbfefd4c59536fae4, // -0.1026, -0.99472 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb97bb0caaba56f, 0xbfefd74fdd40abbf, // -0.099544, -0.99503 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb8b398cf0c38e0, 0xbfefd9c68127c78c, // -0.09649, -0.99533 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb7eb7196b72ee4, 0xbfefdc297f674ba9, // -0.093436, -0.99563 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb7233b9d236e71, 0xbfefde78d68653fd, // -0.090381, -0.99591 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb65af75dd0f87b, 0xbfefe0b485181be3, // -0.087326, -0.99618 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb592a554489bc8, 0xbfefe2dc89bbff08, // -0.084269, -0.99644 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // -0.081211, -0.9967 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb401d9d0e3a507, 0xbfefe6f18ff42c84, // -0.078153, -0.99694 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb339614e41ffa5, 0xbfefe8de8f03d75c, // -0.075094, -0.99718 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb270dcefdfc45b, 0xbfefeab7df1c6005, // -0.072035, -0.9974 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1a84d316d4f8a, 0xbfefec7d7f19cffc, // -0.068974, -0.99762 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb0dfb28ea201e6, 0xbfefee2f6de455ba, // -0.065913, -0.99783 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfb0170d833bf421, 0xbfefefcdaa704562, // -0.062852, -0.99802 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfae9cbd15ff5527, 0xbfeff15833be1965, // -0.05979, -0.99821 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfad0b4c436f91d0, 0xbfeff2cf08da7321, // -0.056727, -0.99839 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfab79c986698b78, 0xbfeff43228de1b77, // -0.053664, -0.99856 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa9e835d6993c87, 0xbfeff58192ee0358, // -0.0506, -0.99872 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa856922bb513c1, 0xbfeff6bd463b444d, // -0.047535, -0.99887 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa6c4df7d7d5b84, 0xbfeff7e5420320f9, // -0.044471, -0.99901 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa5331ec3bba0eb, 0xbfeff8f9858f058b, // -0.041406, -0.99914 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa3a150f6421afc, 0xbfeff9fa10348837, // -0.03834, -0.99926 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa20f770ceb11c6, 0xbfeffae6e1556998, // -0.035274, -0.99938 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbfa07d91ff984580, 0xbfeffbbff85f9515, // -0.032208, -0.99948 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9dd7458c64ab39, 0xbfeffc8554cd213a, // -0.029142, -0.99958 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf9ab354b1504fca, 0xbfeffd36f624500c, // -0.026075, -0.99966 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf978f535ddc9f03, 0xbfeffdd4dbf78f52, // -0.023008, -0.99974 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf946b4381fce81c, 0xbfeffe5f05e578db, // -0.01994, -0.9998 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf9147270dad7132, 0xbfeffed57398d2b7, // -0.016873, -0.99986 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8c45ffe1e48ad9, 0xbfefff3824c88f6f, // -0.013805, -0.9999 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf85fda037ac05e0, 0xbfefff871937ce2f, // -0.010738, -0.99994 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7f6a65f9a2a3c5, 0xbfefffc250b5daef, //-0.0076698, -0.99997 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf72d97822f996bc, 0xbfefffe9cb1e2e8d, //-0.0046019, -0.99999 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0xbf5921faaee6472d, 0xbfeffffd88586ee6, // -0.001534, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, // 0.0046019, -0.99999 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, // 0.0076698, -0.99997 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + + +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_16[32] = { + 1.000000000f, 0.000000000f, + 0.923879533f, 0.382683432f, + 0.707106781f, 0.707106781f, + 0.382683432f, 0.923879533f, + 0.000000000f, 1.000000000f, + -0.382683432f, 0.923879533f, + -0.707106781f, 0.707106781f, + -0.923879533f, 0.382683432f, + -1.000000000f, 0.000000000f, + -0.923879533f, -0.382683432f, + -0.707106781f, -0.707106781f, + -0.382683432f, -0.923879533f, + -0.000000000f, -1.000000000f, + 0.382683432f, -0.923879533f, + 0.707106781f, -0.707106781f, + 0.923879533f, -0.382683432f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_32[64] = { + 1.000000000f, 0.000000000f, + 0.980785280f, 0.195090322f, + 0.923879533f, 0.382683432f, + 0.831469612f, 0.555570233f, + 0.707106781f, 0.707106781f, + 0.555570233f, 0.831469612f, + 0.382683432f, 0.923879533f, + 0.195090322f, 0.980785280f, + 0.000000000f, 1.000000000f, + -0.195090322f, 0.980785280f, + -0.382683432f, 0.923879533f, + -0.555570233f, 0.831469612f, + -0.707106781f, 0.707106781f, + -0.831469612f, 0.555570233f, + -0.923879533f, 0.382683432f, + -0.980785280f, 0.195090322f, + -1.000000000f, 0.000000000f, + -0.980785280f, -0.195090322f, + -0.923879533f, -0.382683432f, + -0.831469612f, -0.555570233f, + -0.707106781f, -0.707106781f, + -0.555570233f, -0.831469612f, + -0.382683432f, -0.923879533f, + -0.195090322f, -0.980785280f, + -0.000000000f, -1.000000000f, + 0.195090322f, -0.980785280f, + 0.382683432f, -0.923879533f, + 0.555570233f, -0.831469612f, + 0.707106781f, -0.707106781f, + 0.831469612f, -0.555570233f, + 0.923879533f, -0.382683432f, + 0.980785280f, -0.195090322f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_64[128] = { + 1.000000000f, 0.000000000f, + 0.995184727f, 0.098017140f, + 0.980785280f, 0.195090322f, + 0.956940336f, 0.290284677f, + 0.923879533f, 0.382683432f, + 0.881921264f, 0.471396737f, + 0.831469612f, 0.555570233f, + 0.773010453f, 0.634393284f, + 0.707106781f, 0.707106781f, + 0.634393284f, 0.773010453f, + 0.555570233f, 0.831469612f, + 0.471396737f, 0.881921264f, + 0.382683432f, 0.923879533f, + 0.290284677f, 0.956940336f, + 0.195090322f, 0.980785280f, + 0.098017140f, 0.995184727f, + 0.000000000f, 1.000000000f, + -0.098017140f, 0.995184727f, + -0.195090322f, 0.980785280f, + -0.290284677f, 0.956940336f, + -0.382683432f, 0.923879533f, + -0.471396737f, 0.881921264f, + -0.555570233f, 0.831469612f, + -0.634393284f, 0.773010453f, + -0.707106781f, 0.707106781f, + -0.773010453f, 0.634393284f, + -0.831469612f, 0.555570233f, + -0.881921264f, 0.471396737f, + -0.923879533f, 0.382683432f, + -0.956940336f, 0.290284677f, + -0.980785280f, 0.195090322f, + -0.995184727f, 0.098017140f, + -1.000000000f, 0.000000000f, + -0.995184727f, -0.098017140f, + -0.980785280f, -0.195090322f, + -0.956940336f, -0.290284677f, + -0.923879533f, -0.382683432f, + -0.881921264f, -0.471396737f, + -0.831469612f, -0.555570233f, + -0.773010453f, -0.634393284f, + -0.707106781f, -0.707106781f, + -0.634393284f, -0.773010453f, + -0.555570233f, -0.831469612f, + -0.471396737f, -0.881921264f, + -0.382683432f, -0.923879533f, + -0.290284677f, -0.956940336f, + -0.195090322f, -0.980785280f, + -0.098017140f, -0.995184727f, + -0.000000000f, -1.000000000f, + 0.098017140f, -0.995184727f, + 0.195090322f, -0.980785280f, + 0.290284677f, -0.956940336f, + 0.382683432f, -0.923879533f, + 0.471396737f, -0.881921264f, + 0.555570233f, -0.831469612f, + 0.634393284f, -0.773010453f, + 0.707106781f, -0.707106781f, + 0.773010453f, -0.634393284f, + 0.831469612f, -0.555570233f, + 0.881921264f, -0.471396737f, + 0.923879533f, -0.382683432f, + 0.956940336f, -0.290284677f, + 0.980785280f, -0.195090322f, + 0.995184727f, -0.098017140f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_128[256] = { + 1.000000000f, 0.000000000f, + 0.998795456f, 0.049067674f, + 0.995184727f, 0.098017140f, + 0.989176510f, 0.146730474f, + 0.980785280f, 0.195090322f, + 0.970031253f, 0.242980180f, + 0.956940336f, 0.290284677f, + 0.941544065f, 0.336889853f, + 0.923879533f, 0.382683432f, + 0.903989293f, 0.427555093f, + 0.881921264f, 0.471396737f, + 0.857728610f, 0.514102744f, + 0.831469612f, 0.555570233f, + 0.803207531f, 0.595699304f, + 0.773010453f, 0.634393284f, + 0.740951125f, 0.671558955f, + 0.707106781f, 0.707106781f, + 0.671558955f, 0.740951125f, + 0.634393284f, 0.773010453f, + 0.595699304f, 0.803207531f, + 0.555570233f, 0.831469612f, + 0.514102744f, 0.857728610f, + 0.471396737f, 0.881921264f, + 0.427555093f, 0.903989293f, + 0.382683432f, 0.923879533f, + 0.336889853f, 0.941544065f, + 0.290284677f, 0.956940336f, + 0.242980180f, 0.970031253f, + 0.195090322f, 0.980785280f, + 0.146730474f, 0.989176510f, + 0.098017140f, 0.995184727f, + 0.049067674f, 0.998795456f, + 0.000000000f, 1.000000000f, + -0.049067674f, 0.998795456f, + -0.098017140f, 0.995184727f, + -0.146730474f, 0.989176510f, + -0.195090322f, 0.980785280f, + -0.242980180f, 0.970031253f, + -0.290284677f, 0.956940336f, + -0.336889853f, 0.941544065f, + -0.382683432f, 0.923879533f, + -0.427555093f, 0.903989293f, + -0.471396737f, 0.881921264f, + -0.514102744f, 0.857728610f, + -0.555570233f, 0.831469612f, + -0.595699304f, 0.803207531f, + -0.634393284f, 0.773010453f, + -0.671558955f, 0.740951125f, + -0.707106781f, 0.707106781f, + -0.740951125f, 0.671558955f, + -0.773010453f, 0.634393284f, + -0.803207531f, 0.595699304f, + -0.831469612f, 0.555570233f, + -0.857728610f, 0.514102744f, + -0.881921264f, 0.471396737f, + -0.903989293f, 0.427555093f, + -0.923879533f, 0.382683432f, + -0.941544065f, 0.336889853f, + -0.956940336f, 0.290284677f, + -0.970031253f, 0.242980180f, + -0.980785280f, 0.195090322f, + -0.989176510f, 0.146730474f, + -0.995184727f, 0.098017140f, + -0.998795456f, 0.049067674f, + -1.000000000f, 0.000000000f, + -0.998795456f, -0.049067674f, + -0.995184727f, -0.098017140f, + -0.989176510f, -0.146730474f, + -0.980785280f, -0.195090322f, + -0.970031253f, -0.242980180f, + -0.956940336f, -0.290284677f, + -0.941544065f, -0.336889853f, + -0.923879533f, -0.382683432f, + -0.903989293f, -0.427555093f, + -0.881921264f, -0.471396737f, + -0.857728610f, -0.514102744f, + -0.831469612f, -0.555570233f, + -0.803207531f, -0.595699304f, + -0.773010453f, -0.634393284f, + -0.740951125f, -0.671558955f, + -0.707106781f, -0.707106781f, + -0.671558955f, -0.740951125f, + -0.634393284f, -0.773010453f, + -0.595699304f, -0.803207531f, + -0.555570233f, -0.831469612f, + -0.514102744f, -0.857728610f, + -0.471396737f, -0.881921264f, + -0.427555093f, -0.903989293f, + -0.382683432f, -0.923879533f, + -0.336889853f, -0.941544065f, + -0.290284677f, -0.956940336f, + -0.242980180f, -0.970031253f, + -0.195090322f, -0.980785280f, + -0.146730474f, -0.989176510f, + -0.098017140f, -0.995184727f, + -0.049067674f, -0.998795456f, + -0.000000000f, -1.000000000f, + 0.049067674f, -0.998795456f, + 0.098017140f, -0.995184727f, + 0.146730474f, -0.989176510f, + 0.195090322f, -0.980785280f, + 0.242980180f, -0.970031253f, + 0.290284677f, -0.956940336f, + 0.336889853f, -0.941544065f, + 0.382683432f, -0.923879533f, + 0.427555093f, -0.903989293f, + 0.471396737f, -0.881921264f, + 0.514102744f, -0.857728610f, + 0.555570233f, -0.831469612f, + 0.595699304f, -0.803207531f, + 0.634393284f, -0.773010453f, + 0.671558955f, -0.740951125f, + 0.707106781f, -0.707106781f, + 0.740951125f, -0.671558955f, + 0.773010453f, -0.634393284f, + 0.803207531f, -0.595699304f, + 0.831469612f, -0.555570233f, + 0.857728610f, -0.514102744f, + 0.881921264f, -0.471396737f, + 0.903989293f, -0.427555093f, + 0.923879533f, -0.382683432f, + 0.941544065f, -0.336889853f, + 0.956940336f, -0.290284677f, + 0.970031253f, -0.242980180f, + 0.980785280f, -0.195090322f, + 0.989176510f, -0.146730474f, + 0.995184727f, -0.098017140f, + 0.998795456f, -0.049067674f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_256[512] = { + 1.000000000f, 0.000000000f, + 0.999698819f, 0.024541229f, + 0.998795456f, 0.049067674f, + 0.997290457f, 0.073564564f, + 0.995184727f, 0.098017140f, + 0.992479535f, 0.122410675f, + 0.989176510f, 0.146730474f, + 0.985277642f, 0.170961889f, + 0.980785280f, 0.195090322f, + 0.975702130f, 0.219101240f, + 0.970031253f, 0.242980180f, + 0.963776066f, 0.266712757f, + 0.956940336f, 0.290284677f, + 0.949528181f, 0.313681740f, + 0.941544065f, 0.336889853f, + 0.932992799f, 0.359895037f, + 0.923879533f, 0.382683432f, + 0.914209756f, 0.405241314f, + 0.903989293f, 0.427555093f, + 0.893224301f, 0.449611330f, + 0.881921264f, 0.471396737f, + 0.870086991f, 0.492898192f, + 0.857728610f, 0.514102744f, + 0.844853565f, 0.534997620f, + 0.831469612f, 0.555570233f, + 0.817584813f, 0.575808191f, + 0.803207531f, 0.595699304f, + 0.788346428f, 0.615231591f, + 0.773010453f, 0.634393284f, + 0.757208847f, 0.653172843f, + 0.740951125f, 0.671558955f, + 0.724247083f, 0.689540545f, + 0.707106781f, 0.707106781f, + 0.689540545f, 0.724247083f, + 0.671558955f, 0.740951125f, + 0.653172843f, 0.757208847f, + 0.634393284f, 0.773010453f, + 0.615231591f, 0.788346428f, + 0.595699304f, 0.803207531f, + 0.575808191f, 0.817584813f, + 0.555570233f, 0.831469612f, + 0.534997620f, 0.844853565f, + 0.514102744f, 0.857728610f, + 0.492898192f, 0.870086991f, + 0.471396737f, 0.881921264f, + 0.449611330f, 0.893224301f, + 0.427555093f, 0.903989293f, + 0.405241314f, 0.914209756f, + 0.382683432f, 0.923879533f, + 0.359895037f, 0.932992799f, + 0.336889853f, 0.941544065f, + 0.313681740f, 0.949528181f, + 0.290284677f, 0.956940336f, + 0.266712757f, 0.963776066f, + 0.242980180f, 0.970031253f, + 0.219101240f, 0.975702130f, + 0.195090322f, 0.980785280f, + 0.170961889f, 0.985277642f, + 0.146730474f, 0.989176510f, + 0.122410675f, 0.992479535f, + 0.098017140f, 0.995184727f, + 0.073564564f, 0.997290457f, + 0.049067674f, 0.998795456f, + 0.024541229f, 0.999698819f, + 0.000000000f, 1.000000000f, + -0.024541229f, 0.999698819f, + -0.049067674f, 0.998795456f, + -0.073564564f, 0.997290457f, + -0.098017140f, 0.995184727f, + -0.122410675f, 0.992479535f, + -0.146730474f, 0.989176510f, + -0.170961889f, 0.985277642f, + -0.195090322f, 0.980785280f, + -0.219101240f, 0.975702130f, + -0.242980180f, 0.970031253f, + -0.266712757f, 0.963776066f, + -0.290284677f, 0.956940336f, + -0.313681740f, 0.949528181f, + -0.336889853f, 0.941544065f, + -0.359895037f, 0.932992799f, + -0.382683432f, 0.923879533f, + -0.405241314f, 0.914209756f, + -0.427555093f, 0.903989293f, + -0.449611330f, 0.893224301f, + -0.471396737f, 0.881921264f, + -0.492898192f, 0.870086991f, + -0.514102744f, 0.857728610f, + -0.534997620f, 0.844853565f, + -0.555570233f, 0.831469612f, + -0.575808191f, 0.817584813f, + -0.595699304f, 0.803207531f, + -0.615231591f, 0.788346428f, + -0.634393284f, 0.773010453f, + -0.653172843f, 0.757208847f, + -0.671558955f, 0.740951125f, + -0.689540545f, 0.724247083f, + -0.707106781f, 0.707106781f, + -0.724247083f, 0.689540545f, + -0.740951125f, 0.671558955f, + -0.757208847f, 0.653172843f, + -0.773010453f, 0.634393284f, + -0.788346428f, 0.615231591f, + -0.803207531f, 0.595699304f, + -0.817584813f, 0.575808191f, + -0.831469612f, 0.555570233f, + -0.844853565f, 0.534997620f, + -0.857728610f, 0.514102744f, + -0.870086991f, 0.492898192f, + -0.881921264f, 0.471396737f, + -0.893224301f, 0.449611330f, + -0.903989293f, 0.427555093f, + -0.914209756f, 0.405241314f, + -0.923879533f, 0.382683432f, + -0.932992799f, 0.359895037f, + -0.941544065f, 0.336889853f, + -0.949528181f, 0.313681740f, + -0.956940336f, 0.290284677f, + -0.963776066f, 0.266712757f, + -0.970031253f, 0.242980180f, + -0.975702130f, 0.219101240f, + -0.980785280f, 0.195090322f, + -0.985277642f, 0.170961889f, + -0.989176510f, 0.146730474f, + -0.992479535f, 0.122410675f, + -0.995184727f, 0.098017140f, + -0.997290457f, 0.073564564f, + -0.998795456f, 0.049067674f, + -0.999698819f, 0.024541229f, + -1.000000000f, 0.000000000f, + -0.999698819f, -0.024541229f, + -0.998795456f, -0.049067674f, + -0.997290457f, -0.073564564f, + -0.995184727f, -0.098017140f, + -0.992479535f, -0.122410675f, + -0.989176510f, -0.146730474f, + -0.985277642f, -0.170961889f, + -0.980785280f, -0.195090322f, + -0.975702130f, -0.219101240f, + -0.970031253f, -0.242980180f, + -0.963776066f, -0.266712757f, + -0.956940336f, -0.290284677f, + -0.949528181f, -0.313681740f, + -0.941544065f, -0.336889853f, + -0.932992799f, -0.359895037f, + -0.923879533f, -0.382683432f, + -0.914209756f, -0.405241314f, + -0.903989293f, -0.427555093f, + -0.893224301f, -0.449611330f, + -0.881921264f, -0.471396737f, + -0.870086991f, -0.492898192f, + -0.857728610f, -0.514102744f, + -0.844853565f, -0.534997620f, + -0.831469612f, -0.555570233f, + -0.817584813f, -0.575808191f, + -0.803207531f, -0.595699304f, + -0.788346428f, -0.615231591f, + -0.773010453f, -0.634393284f, + -0.757208847f, -0.653172843f, + -0.740951125f, -0.671558955f, + -0.724247083f, -0.689540545f, + -0.707106781f, -0.707106781f, + -0.689540545f, -0.724247083f, + -0.671558955f, -0.740951125f, + -0.653172843f, -0.757208847f, + -0.634393284f, -0.773010453f, + -0.615231591f, -0.788346428f, + -0.595699304f, -0.803207531f, + -0.575808191f, -0.817584813f, + -0.555570233f, -0.831469612f, + -0.534997620f, -0.844853565f, + -0.514102744f, -0.857728610f, + -0.492898192f, -0.870086991f, + -0.471396737f, -0.881921264f, + -0.449611330f, -0.893224301f, + -0.427555093f, -0.903989293f, + -0.405241314f, -0.914209756f, + -0.382683432f, -0.923879533f, + -0.359895037f, -0.932992799f, + -0.336889853f, -0.941544065f, + -0.313681740f, -0.949528181f, + -0.290284677f, -0.956940336f, + -0.266712757f, -0.963776066f, + -0.242980180f, -0.970031253f, + -0.219101240f, -0.975702130f, + -0.195090322f, -0.980785280f, + -0.170961889f, -0.985277642f, + -0.146730474f, -0.989176510f, + -0.122410675f, -0.992479535f, + -0.098017140f, -0.995184727f, + -0.073564564f, -0.997290457f, + -0.049067674f, -0.998795456f, + -0.024541229f, -0.999698819f, + -0.000000000f, -1.000000000f, + 0.024541229f, -0.999698819f, + 0.049067674f, -0.998795456f, + 0.073564564f, -0.997290457f, + 0.098017140f, -0.995184727f, + 0.122410675f, -0.992479535f, + 0.146730474f, -0.989176510f, + 0.170961889f, -0.985277642f, + 0.195090322f, -0.980785280f, + 0.219101240f, -0.975702130f, + 0.242980180f, -0.970031253f, + 0.266712757f, -0.963776066f, + 0.290284677f, -0.956940336f, + 0.313681740f, -0.949528181f, + 0.336889853f, -0.941544065f, + 0.359895037f, -0.932992799f, + 0.382683432f, -0.923879533f, + 0.405241314f, -0.914209756f, + 0.427555093f, -0.903989293f, + 0.449611330f, -0.893224301f, + 0.471396737f, -0.881921264f, + 0.492898192f, -0.870086991f, + 0.514102744f, -0.857728610f, + 0.534997620f, -0.844853565f, + 0.555570233f, -0.831469612f, + 0.575808191f, -0.817584813f, + 0.595699304f, -0.803207531f, + 0.615231591f, -0.788346428f, + 0.634393284f, -0.773010453f, + 0.653172843f, -0.757208847f, + 0.671558955f, -0.740951125f, + 0.689540545f, -0.724247083f, + 0.707106781f, -0.707106781f, + 0.724247083f, -0.689540545f, + 0.740951125f, -0.671558955f, + 0.757208847f, -0.653172843f, + 0.773010453f, -0.634393284f, + 0.788346428f, -0.615231591f, + 0.803207531f, -0.595699304f, + 0.817584813f, -0.575808191f, + 0.831469612f, -0.555570233f, + 0.844853565f, -0.534997620f, + 0.857728610f, -0.514102744f, + 0.870086991f, -0.492898192f, + 0.881921264f, -0.471396737f, + 0.893224301f, -0.449611330f, + 0.903989293f, -0.427555093f, + 0.914209756f, -0.405241314f, + 0.923879533f, -0.382683432f, + 0.932992799f, -0.359895037f, + 0.941544065f, -0.336889853f, + 0.949528181f, -0.313681740f, + 0.956940336f, -0.290284677f, + 0.963776066f, -0.266712757f, + 0.970031253f, -0.242980180f, + 0.975702130f, -0.219101240f, + 0.980785280f, -0.195090322f, + 0.985277642f, -0.170961889f, + 0.989176510f, -0.146730474f, + 0.992479535f, -0.122410675f, + 0.995184727f, -0.098017140f, + 0.997290457f, -0.073564564f, + 0.998795456f, -0.049067674f, + 0.999698819f, -0.024541229f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_512[1024] = { + 1.000000000f, 0.000000000f, + 0.999924702f, 0.012271538f, + 0.999698819f, 0.024541229f, + 0.999322385f, 0.036807223f, + 0.998795456f, 0.049067674f, + 0.998118113f, 0.061320736f, + 0.997290457f, 0.073564564f, + 0.996312612f, 0.085797312f, + 0.995184727f, 0.098017140f, + 0.993906970f, 0.110222207f, + 0.992479535f, 0.122410675f, + 0.990902635f, 0.134580709f, + 0.989176510f, 0.146730474f, + 0.987301418f, 0.158858143f, + 0.985277642f, 0.170961889f, + 0.983105487f, 0.183039888f, + 0.980785280f, 0.195090322f, + 0.978317371f, 0.207111376f, + 0.975702130f, 0.219101240f, + 0.972939952f, 0.231058108f, + 0.970031253f, 0.242980180f, + 0.966976471f, 0.254865660f, + 0.963776066f, 0.266712757f, + 0.960430519f, 0.278519689f, + 0.956940336f, 0.290284677f, + 0.953306040f, 0.302005949f, + 0.949528181f, 0.313681740f, + 0.945607325f, 0.325310292f, + 0.941544065f, 0.336889853f, + 0.937339012f, 0.348418680f, + 0.932992799f, 0.359895037f, + 0.928506080f, 0.371317194f, + 0.923879533f, 0.382683432f, + 0.919113852f, 0.393992040f, + 0.914209756f, 0.405241314f, + 0.909167983f, 0.416429560f, + 0.903989293f, 0.427555093f, + 0.898674466f, 0.438616239f, + 0.893224301f, 0.449611330f, + 0.887639620f, 0.460538711f, + 0.881921264f, 0.471396737f, + 0.876070094f, 0.482183772f, + 0.870086991f, 0.492898192f, + 0.863972856f, 0.503538384f, + 0.857728610f, 0.514102744f, + 0.851355193f, 0.524589683f, + 0.844853565f, 0.534997620f, + 0.838224706f, 0.545324988f, + 0.831469612f, 0.555570233f, + 0.824589303f, 0.565731811f, + 0.817584813f, 0.575808191f, + 0.810457198f, 0.585797857f, + 0.803207531f, 0.595699304f, + 0.795836905f, 0.605511041f, + 0.788346428f, 0.615231591f, + 0.780737229f, 0.624859488f, + 0.773010453f, 0.634393284f, + 0.765167266f, 0.643831543f, + 0.757208847f, 0.653172843f, + 0.749136395f, 0.662415778f, + 0.740951125f, 0.671558955f, + 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0.405241314f, 0.914209756f, + 0.393992040f, 0.919113852f, + 0.382683432f, 0.923879533f, + 0.371317194f, 0.928506080f, + 0.359895037f, 0.932992799f, + 0.348418680f, 0.937339012f, + 0.336889853f, 0.941544065f, + 0.325310292f, 0.945607325f, + 0.313681740f, 0.949528181f, + 0.302005949f, 0.953306040f, + 0.290284677f, 0.956940336f, + 0.278519689f, 0.960430519f, + 0.266712757f, 0.963776066f, + 0.254865660f, 0.966976471f, + 0.242980180f, 0.970031253f, + 0.231058108f, 0.972939952f, + 0.219101240f, 0.975702130f, + 0.207111376f, 0.978317371f, + 0.195090322f, 0.980785280f, + 0.183039888f, 0.983105487f, + 0.170961889f, 0.985277642f, + 0.158858143f, 0.987301418f, + 0.146730474f, 0.989176510f, + 0.134580709f, 0.990902635f, + 0.122410675f, 0.992479535f, + 0.110222207f, 0.993906970f, + 0.098017140f, 0.995184727f, + 0.085797312f, 0.996312612f, + 0.073564564f, 0.997290457f, + 0.061320736f, 0.998118113f, + 0.049067674f, 0.998795456f, + 0.036807223f, 0.999322385f, + 0.024541229f, 0.999698819f, + 0.012271538f, 0.999924702f, + 0.000000000f, 1.000000000f, + -0.012271538f, 0.999924702f, + -0.024541229f, 0.999698819f, + -0.036807223f, 0.999322385f, + -0.049067674f, 0.998795456f, + -0.061320736f, 0.998118113f, + -0.073564564f, 0.997290457f, + -0.085797312f, 0.996312612f, + -0.098017140f, 0.995184727f, + -0.110222207f, 0.993906970f, + -0.122410675f, 0.992479535f, + -0.134580709f, 0.990902635f, + -0.146730474f, 0.989176510f, + -0.158858143f, 0.987301418f, + -0.170961889f, 0.985277642f, + -0.183039888f, 0.983105487f, + -0.195090322f, 0.980785280f, + -0.207111376f, 0.978317371f, + -0.219101240f, 0.975702130f, + -0.231058108f, 0.972939952f, + -0.242980180f, 0.970031253f, + -0.254865660f, 0.966976471f, + -0.266712757f, 0.963776066f, + -0.278519689f, 0.960430519f, + -0.290284677f, 0.956940336f, + -0.302005949f, 0.953306040f, + -0.313681740f, 0.949528181f, + -0.325310292f, 0.945607325f, + -0.336889853f, 0.941544065f, + -0.348418680f, 0.937339012f, + -0.359895037f, 0.932992799f, + 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0.998118113f, -0.061320736f, + 0.998795456f, -0.049067674f, + 0.999322385f, -0.036807223f, + 0.999698819f, -0.024541229f, + 0.999924702f, -0.012271538f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_1024[2048] = { + 1.000000000f, 0.000000000f, + 0.999981175f, 0.006135885f, + 0.999924702f, 0.012271538f, + 0.999830582f, 0.018406730f, + 0.999698819f, 0.024541229f, + 0.999529418f, 0.030674803f, + 0.999322385f, 0.036807223f, + 0.999077728f, 0.042938257f, + 0.998795456f, 0.049067674f, + 0.998475581f, 0.055195244f, + 0.998118113f, 0.061320736f, + 0.997723067f, 0.067443920f, + 0.997290457f, 0.073564564f, + 0.996820299f, 0.079682438f, + 0.996312612f, 0.085797312f, + 0.995767414f, 0.091908956f, + 0.995184727f, 0.098017140f, + 0.994564571f, 0.104121634f, + 0.993906970f, 0.110222207f, + 0.993211949f, 0.116318631f, + 0.992479535f, 0.122410675f, + 0.991709754f, 0.128498111f, + 0.990902635f, 0.134580709f, + 0.990058210f, 0.140658239f, + 0.989176510f, 0.146730474f, + 0.988257568f, 0.152797185f, + 0.987301418f, 0.158858143f, + 0.986308097f, 0.164913120f, + 0.985277642f, 0.170961889f, + 0.984210092f, 0.177004220f, + 0.983105487f, 0.183039888f, + 0.981963869f, 0.189068664f, + 0.980785280f, 0.195090322f, + 0.979569766f, 0.201104635f, + 0.978317371f, 0.207111376f, + 0.977028143f, 0.213110320f, + 0.975702130f, 0.219101240f, + 0.974339383f, 0.225083911f, + 0.972939952f, 0.231058108f, + 0.971503891f, 0.237023606f, + 0.970031253f, 0.242980180f, + 0.968522094f, 0.248927606f, + 0.966976471f, 0.254865660f, + 0.965394442f, 0.260794118f, + 0.963776066f, 0.266712757f, + 0.962121404f, 0.272621355f, + 0.960430519f, 0.278519689f, + 0.958703475f, 0.284407537f, + 0.956940336f, 0.290284677f, + 0.955141168f, 0.296150888f, + 0.953306040f, 0.302005949f, + 0.951435021f, 0.307849640f, + 0.949528181f, 0.313681740f, + 0.947585591f, 0.319502031f, + 0.945607325f, 0.325310292f, + 0.943593458f, 0.331106306f, + 0.941544065f, 0.336889853f, + 0.939459224f, 0.342660717f, + 0.937339012f, 0.348418680f, + 0.935183510f, 0.354163525f, + 0.932992799f, 0.359895037f, + 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0.999529418f, -0.030674803f, + 0.999698819f, -0.024541229f, + 0.999830582f, -0.018406730f, + 0.999924702f, -0.012271538f, + 0.999981175f, -0.006135885f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_2048[4096] = { + 1.000000000f, 0.000000000f, + 0.999995294f, 0.003067957f, + 0.999981175f, 0.006135885f, + 0.999957645f, 0.009203755f, + 0.999924702f, 0.012271538f, + 0.999882347f, 0.015339206f, + 0.999830582f, 0.018406730f, + 0.999769405f, 0.021474080f, + 0.999698819f, 0.024541229f, + 0.999618822f, 0.027608146f, + 0.999529418f, 0.030674803f, + 0.999430605f, 0.033741172f, + 0.999322385f, 0.036807223f, + 0.999204759f, 0.039872928f, + 0.999077728f, 0.042938257f, + 0.998941293f, 0.046003182f, + 0.998795456f, 0.049067674f, + 0.998640218f, 0.052131705f, + 0.998475581f, 0.055195244f, + 0.998301545f, 0.058258265f, + 0.998118113f, 0.061320736f, + 0.997925286f, 0.064382631f, + 0.997723067f, 0.067443920f, + 0.997511456f, 0.070504573f, + 0.997290457f, 0.073564564f, + 0.997060070f, 0.076623861f, + 0.996820299f, 0.079682438f, + 0.996571146f, 0.082740265f, + 0.996312612f, 0.085797312f, + 0.996044701f, 0.088853553f, + 0.995767414f, 0.091908956f, + 0.995480755f, 0.094963495f, + 0.995184727f, 0.098017140f, + 0.994879331f, 0.101069863f, + 0.994564571f, 0.104121634f, + 0.994240449f, 0.107172425f, + 0.993906970f, 0.110222207f, + 0.993564136f, 0.113270952f, + 0.993211949f, 0.116318631f, + 0.992850414f, 0.119365215f, + 0.992479535f, 0.122410675f, + 0.992099313f, 0.125454983f, + 0.991709754f, 0.128498111f, + 0.991310860f, 0.131540029f, + 0.990902635f, 0.134580709f, + 0.990485084f, 0.137620122f, + 0.990058210f, 0.140658239f, + 0.989622017f, 0.143695033f, + 0.989176510f, 0.146730474f, + 0.988721692f, 0.149764535f, + 0.988257568f, 0.152797185f, + 0.987784142f, 0.155828398f, + 0.987301418f, 0.158858143f, + 0.986809402f, 0.161886394f, + 0.986308097f, 0.164913120f, + 0.985797509f, 0.167938295f, + 0.985277642f, 0.170961889f, + 0.984748502f, 0.173983873f, + 0.984210092f, 0.177004220f, + 0.983662419f, 0.180022901f, + 0.983105487f, 0.183039888f, + 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0.999882347f, -0.015339206f, + 0.999924702f, -0.012271538f, + 0.999957645f, -0.009203755f, + 0.999981175f, -0.006135885f, + 0.999995294f, -0.003067957f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_4096[8192] = { + 1.000000000f, 0.000000000f, + 0.999998823f, 0.001533980f, + 0.999995294f, 0.003067957f, + 0.999989411f, 0.004601926f, + 0.999981175f, 0.006135885f, + 0.999970586f, 0.007669829f, + 0.999957645f, 0.009203755f, + 0.999942350f, 0.010737659f, + 0.999924702f, 0.012271538f, + 0.999904701f, 0.013805389f, + 0.999882347f, 0.015339206f, + 0.999857641f, 0.016872988f, + 0.999830582f, 0.018406730f, + 0.999801170f, 0.019940429f, + 0.999769405f, 0.021474080f, + 0.999735288f, 0.023007681f, + 0.999698819f, 0.024541229f, + 0.999659997f, 0.026074718f, + 0.999618822f, 0.027608146f, + 0.999575296f, 0.029141509f, + 0.999529418f, 0.030674803f, + 0.999481187f, 0.032208025f, + 0.999430605f, 0.033741172f, + 0.999377670f, 0.035274239f, + 0.999322385f, 0.036807223f, + 0.999264747f, 0.038340120f, + 0.999204759f, 0.039872928f, + 0.999142419f, 0.041405641f, + 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0.999957645f, -0.009203755f, + 0.999970586f, -0.007669829f, + 0.999981175f, -0.006135885f, + 0.999989411f, -0.004601926f, + 0.999995294f, -0.003067957f, + 0.999998823f, -0.001533980f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + +/** + @brief Q31 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
 for(i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_16_q31[24] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_32_q31[48] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xB8E31319, (q31_t)0x9592675B, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xE70747C3, (q31_t)0x8275A0C0 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_64_q31[96] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i < 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_128_q31[192] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_256_q31[384] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_512_q31[768] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + 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(q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_1024_q31[1536] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5F5E0DB3, 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(q31_t)0xF8EF5CBB, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x804A9C4D, + (q31_t)0xF75DFF65, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x8078D40D, + (q31_t)0xF50497FA, (q31_t)0x808AB180, (q31_t)0xF43C53CA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80B21BAF, + (q31_t)0xF2AC246D, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8145C5C6, + (q31_t)0xEDFEE92B, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81A01B6C, + (q31_t)0xEBAA894E, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x829D753A, (q31_t)0xE642340D, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82F0BDE8, + (q31_t)0xE4B8CD10, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x8376B422, + (q31_t)0xE26CB01A, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8549345C, + (q31_t)0xDB9888A8, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85FA1152, + (q31_t)0xD957DE7A, (q31_t)0x86376092, (q31_t)0xD898620C, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86B583EE, + (q31_t)0xD71A8EB5, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x87BFCCD7, (q31_t)0xD423B190, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x884BE820, + (q31_t)0xD2AAC504, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x8926B677, + (q31_t)0xD078AD9D, (q31_t)0x8971F15A, (q31_t)0xCFBE389F, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A0BD3F5, + (q31_t)0xCE4AB5A2, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BF4AC05, + (q31_t)0xC9FBE527, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CF83C30, + (q31_t)0xC7DB6C50, (q31_t)0x8D50FA59, (q31_t)0xC727016C, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E05C6B7, + (q31_t)0xC5BFD22E, (q31_t)0x8E61D32D, (q31_t)0xC50D1148, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x903E6C7A, + (q31_t)0xC197F4D3, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x91695663, + (q31_t)0xBF8C0DE2, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x929DD805, + (q31_t)0xBD85BE2F, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9447ED2F, (q31_t)0xBADBA943, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9523369B, + (q31_t)0xB98A97D8, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x9673DB94, + (q31_t)0xB796199B, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97CDA855, + (q31_t)0xB5A7E362, (q31_t)0x9842F043, (q31_t)0xB5049368, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A9C406D, + (q31_t)0xB1DEF9E8, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9C10CD70, + (q31_t)0xB0049AB2, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D8E0596, + (q31_t)0xAE312B91, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0x9F979331, (q31_t)0xABCCFD82, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA0A1F24C, + (q31_t)0xAA9FBF1D, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA2386283, + (q31_t)0xA8E21106, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3D6F533, + (q31_t)0xA72BF173, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA72BF173, + (q31_t)0xA3D6F533, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8E21106, + (q31_t)0xA2386283, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA9FBF1D, + (q31_t)0xA0A1F24C, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAE312B91, + (q31_t)0x9D8E0596, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xB0049AB2, + (q31_t)0x9C10CD70, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB1DEF9E8, + (q31_t)0x9A9C406D, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB461FC70, (q31_t)0x98B93828, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB5A7E362, + (q31_t)0x97CDA855, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB796199B, + (q31_t)0x9673DB94, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_2048_q31[3072] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885, + (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1, + (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477, + (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108, + (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853, + (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2, + (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15, + (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4, + (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450, + (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E, + (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635, + (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39, + (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1, + (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF, + (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7, + (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D, + (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E, + (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218, + (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168, + (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2, + (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830, + (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31, + (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C, + (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3, + (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8, + (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715, + (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11, + (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1, + (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64, + (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF, + (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE, + (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376, + (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x75F42C0A, + (q31_t)0x31B54A5D, (q31_t)0x75CCFD42, (q31_t)0x3211DF03, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x757DC5CA, + (q31_t)0x32CAAB6F, (q31_t)0x7555BD4B, (q31_t)0x3326E2C2, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x74DBF1EF, (q31_t)0x343ACA87, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x7489571B, + (q31_t)0x34F219A7, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x740B53FA, + (q31_t)0x36041AD9, (q31_t)0x73E0C3A3, (q31_t)0x365F2E3B, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x738ACC9E, + (q31_t)0x3714F02A, (q31_t)0x735F6626, (q31_t)0x376F9E46, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72DB8828, (q31_t)0x387EDA8E, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72823C66, + (q31_t)0x3932FF87, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x71FA3948, + (q31_t)0x3A402DD1, (q31_t)0x71CC5626, (q31_t)0x3A99A057, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x716FBD68, + (q31_t)0x3B4C18BA, (q31_t)0x71410804, (q31_t)0x3BA51E29, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70B34524, (q31_t)0x3CAF50DA, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70536771, + (q31_t)0x3D600D2B, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FC19385, + (q31_t)0x3E680B2C, (q31_t)0x6F906D84, (q31_t)0x3EBFBDCC, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F2D532C, + (q31_t)0x3F6EAEB8, (q31_t)0x6EFB5F12, (q31_t)0x3FC5EC97, + (q31_t)0x6EC92682, (q31_t)0x401D0320, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6E63E87F, (q31_t)0x40CAB957, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DFD9A1B, + (q31_t)0x4177CFB0, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6D963C54, (q31_t)0x42244480, (q31_t)0x6D6227FA, + (q31_t)0x427A41D0, (q31_t)0x6D2DD027, (q31_t)0x42D0161E, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6CC45697, + (q31_t)0x437B42E1, (q31_t)0x6C8F351C, (q31_t)0x43D09AEC, + (q31_t)0x6C59D0A9, (q31_t)0x4425C923, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6BEE3F62, (q31_t)0x44CFA73F, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B81A3CD, + (q31_t)0x4578DB93, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6B13FEF5, (q31_t)0x4621647C, (q31_t)0x6ADCC964, + (q31_t)0x46756827, (q31_t)0x6AA551E8, (q31_t)0x46C9405C, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x6A359DB9, + (q31_t)0x47706D93, (q31_t)0x69FD614A, (q31_t)0x47C3C22E, + (q31_t)0x69C4E37A, (q31_t)0x4816EA85, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x69532442, (q31_t)0x48BCB598, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68E06129, + (q31_t)0x4961CD32, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x686C9B4B, (q31_t)0x4A062FBD, (q31_t)0x683257AA, + (q31_t)0x4A581C9D, (q31_t)0x67F7D3C4, (q31_t)0x4AA9DBA1, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x67820BB6, + (q31_t)0x4B4CCF4D, (q31_t)0x6746C7D7, (q31_t)0x4B9E038F, + (q31_t)0x670B4443, (q31_t)0x4BEF092D, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x66937E90, (q31_t)0x4C9087B1, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x661ABBC5, + (q31_t)0x4D31494B, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x65A0FD0B, (q31_t)0x4DD14C6E, (q31_t)0x6563BF92, + (q31_t)0x4E210617, (q31_t)0x6526438E, (q31_t)0x4E708F8F, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x64AA907F, + (q31_t)0x4F0F1126, (q31_t)0x646C59BF, (q31_t)0x4F5E08E3, + (q31_t)0x642DE50D, (q31_t)0x4FACCFAB, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x63B0426D, (q31_t)0x5049C999, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x6331A9D4, + (q31_t)0x50E5FD6C, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x62B21C7B, (q31_t)0x518169A4, (q31_t)0x6271FA69, + (q31_t)0x51CED46E, (q31_t)0x62319B9D, (q31_t)0x521C0CC1, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x61B02876, + (q31_t)0x52B5E545, (q31_t)0x616F146B, (q31_t)0x53028517, + (q31_t)0x612DC446, (q31_t)0x534EF1B5, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x60AA704F, (q31_t)0x53E73097, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x60262DD5, + (q31_t)0x547EA073, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5FA0FE1E, (q31_t)0x55153FD4, (q31_t)0x5F5E0DB3, + (q31_t)0x556040E2, (q31_t)0x5F1AE273, (q31_t)0x55AB0D46, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E93DC1F, + (q31_t)0x56400757, (q31_t)0x5E50015D, (q31_t)0x568A34A9, + (q31_t)0x5E0BEC6E, (q31_t)0x56D42C99, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5D8314B0, (q31_t)0x57677B9D, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CF95638, + (q31_t)0x57F9F2F7, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5C6EB258, (q31_t)0x588B913F, (q31_t)0x5C290ACC, + (q31_t)0x58D40E8C, (q31_t)0x5BE32A67, (q31_t)0x591C550E, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B56BFBD, + (q31_t)0x59AC3CFD, (q31_t)0x5B1035CF, (q31_t)0x59F3DE12, + (q31_t)0x5AC973B4, (q31_t)0x5A3B47AA, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x5A3B47AA, (q31_t)0x5AC973B4, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59AC3CFD, + (q31_t)0x5B56BFBD, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x591C550E, (q31_t)0x5BE32A67, (q31_t)0x58D40E8C, + (q31_t)0x5C290ACC, (q31_t)0x588B913F, (q31_t)0x5C6EB258, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57F9F2F7, + (q31_t)0x5CF95638, (q31_t)0x57B0D256, (q31_t)0x5D3E5236, + (q31_t)0x57677B9D, (q31_t)0x5D8314B0, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x56D42C99, (q31_t)0x5E0BEC6E, + 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(q31_t)0x9447ED2F, (q31_t)0xBB3058C0, + (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513, + (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1, + (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8, + (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368, + (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233, + (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25, + (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7, + (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8, + (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571, + (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA, + (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4, + (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578, + (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D, + (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC, + (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459, + (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1, + (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38, + (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8, + (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE, + (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D, + (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439, + (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A, + (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD, + (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220, + (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60, + (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2, + (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1, + (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C, + (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB, + (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616, + (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917, + (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273, + (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80, + (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F, + (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2, + (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752, + (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A, + (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89, + (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260, + (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743, + (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5, + (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90, + (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB, + (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89, + (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69, + (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078, + (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_4096_q31[6144] = +{ + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621, + (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3, + (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64, + (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F, + (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17, + (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4, + (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553, + (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790, + (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840, + (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C, + (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518, + (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152, + (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23, + (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE, + (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7, + (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494, + (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C, + (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89, + (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226, + (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B, + (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD, + (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389, + (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654, + (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + 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(q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8, + (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79, + (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0, + (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1, + (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5, + (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406, + (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2, + (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3, + (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0, + (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243, + (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44, + (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3, + (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23, + (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662, + (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0, + (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C, + (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A, + (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76, + (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231, + (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74, + (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01, + (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076, + (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188, + (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B, + (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E, + (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41, + (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E, + (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD, + (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820, + (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4, + (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C, + (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F, + (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569, + (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B, + (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E, + (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0, + (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0, + (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9, + (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D, + (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @brief q15 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
fori = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_16_q15[24] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xCF04, (q15_t)0x89BE +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_32_q15[48] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7D8A, (q15_t)0x18F8, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x6A6D, (q15_t)0x471C, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x471C, (q15_t)0x6A6D, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x18F8, (q15_t)0x7D8A, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xE707, (q15_t)0x7D8A, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xB8E3, (q15_t)0x6A6D, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x9592, (q15_t)0x471C, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8275, (q15_t)0x18F8, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x8275, (q15_t)0xE707, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0x9592, (q15_t)0xB8E3, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xB8E3, (q15_t)0x9592, + (q15_t)0xCF04, (q15_t)0x89BE, + (q15_t)0xE707, (q15_t)0x8275 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_64_q15[96] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_128_q15[192] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_256_q15[384] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_512_q15[768] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + + */ +const q15_t twiddleCoef_1024_q15[1536] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, (q15_t)0x735F, + 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(q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_2048_q15[3072] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, (q15_t)0x4425, + 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(q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_4096_q15[6144] = +{ + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032, + (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB, + (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01C4, + (q15_t)0x7FFC, (q15_t)0x01F6, (q15_t)0x7FFB, (q15_t)0x0228, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF9, (q15_t)0x028D, + (q15_t)0x7FF8, (q15_t)0x02BF, (q15_t)0x7FF7, (q15_t)0x02F1, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF4, (q15_t)0x0356, + (q15_t)0x7FF3, (q15_t)0x0388, (q15_t)0x7FF2, (q15_t)0x03BA, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FEE, (q15_t)0x041F, + (q15_t)0x7FED, (q15_t)0x0451, (q15_t)0x7FEB, (q15_t)0x0483, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE7, (q15_t)0x04E8, + (q15_t)0x7FE5, (q15_t)0x051A, (q15_t)0x7FE3, (q15_t)0x054C, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDF, (q15_t)0x05B1, + (q15_t)0x7FDD, (q15_t)0x05E3, (q15_t)0x7FDA, (q15_t)0x0615, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD6, (q15_t)0x067A, + (q15_t)0x7FD3, (q15_t)0x06AC, (q15_t)0x7FD0, (q15_t)0x06DE, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FCB, (q15_t)0x0742, + (q15_t)0x7FC8, (q15_t)0x0775, (q15_t)0x7FC5, (q15_t)0x07A7, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBF, (q15_t)0x080B, + (q15_t)0x7FBC, (q15_t)0x083D, (q15_t)0x7FB8, (q15_t)0x086F, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FB1, (q15_t)0x08D4, + (q15_t)0x7FAE, (q15_t)0x0906, (q15_t)0x7FAA, (q15_t)0x0938, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7FA3, (q15_t)0x099C, + (q15_t)0x7F9F, (q15_t)0x09CE, (q15_t)0x7F9B, (q15_t)0x0A00, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F93, (q15_t)0x0A65, + (q15_t)0x7F8F, (q15_t)0x0A97, (q15_t)0x7F8B, (q15_t)0x0AC9, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F82, (q15_t)0x0B2D, + (q15_t)0x7F7E, (q15_t)0x0B5F, (q15_t)0x7F79, (q15_t)0x0B91, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F70, (q15_t)0x0BF5, + (q15_t)0x7F6B, (q15_t)0x0C27, (q15_t)0x7F67, (q15_t)0x0C59, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F5D, (q15_t)0x0CBD, + (q15_t)0x7F58, (q15_t)0x0CEF, (q15_t)0x7F53, (q15_t)0x0D21, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F48, (q15_t)0x0D85, + (q15_t)0x7F43, (q15_t)0x0DB7, (q15_t)0x7F3D, (q15_t)0x0DE9, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F32, (q15_t)0x0E4D, + (q15_t)0x7F2D, (q15_t)0x0E7F, (q15_t)0x7F27, (q15_t)0x0EB1, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F1B, (q15_t)0x0F15, + (q15_t)0x7F15, (q15_t)0x0F47, (q15_t)0x7F0F, (q15_t)0x0F79, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7F03, (q15_t)0x0FDD, + (q15_t)0x7EFD, (q15_t)0x100E, (q15_t)0x7EF6, (q15_t)0x1040, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE9, (q15_t)0x10A4, + (q15_t)0x7EE3, (q15_t)0x10D6, (q15_t)0x7EDC, (q15_t)0x1108, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7ECF, (q15_t)0x116B, + (q15_t)0x7EC8, (q15_t)0x119D, (q15_t)0x7EC1, (q15_t)0x11CF, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EB3, (q15_t)0x1232, + (q15_t)0x7EAB, (q15_t)0x1264, (q15_t)0x7EA4, (q15_t)0x1296, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E95, (q15_t)0x12F9, + (q15_t)0x7E8E, (q15_t)0x132B, (q15_t)0x7E86, (q15_t)0x135D, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E77, (q15_t)0x13C0, + (q15_t)0x7E6F, (q15_t)0x13F2, (q15_t)0x7E67, (q15_t)0x1423, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E57, (q15_t)0x1487, + (q15_t)0x7E4F, (q15_t)0x14B8, (q15_t)0x7E47, (q15_t)0x14EA, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E37, (q15_t)0x154D, + (q15_t)0x7E2E, (q15_t)0x157F, (q15_t)0x7E26, (q15_t)0x15B0, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E14, (q15_t)0x1613, + (q15_t)0x7E0C, (q15_t)0x1645, (q15_t)0x7E03, (q15_t)0x1676, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DF1, (q15_t)0x16D9, + (q15_t)0x7DE8, (q15_t)0x170A, (q15_t)0x7DDF, (q15_t)0x173C, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DCD, (q15_t)0x179F, + (q15_t)0x7DC3, (q15_t)0x17D0, (q15_t)0x7DBA, (q15_t)0x1802, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7DA7, (q15_t)0x1864, + (q15_t)0x7D9D, (q15_t)0x1896, (q15_t)0x7D94, (q15_t)0x18C7, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D80, (q15_t)0x192A, + (q15_t)0x7D76, (q15_t)0x195B, (q15_t)0x7D6C, (q15_t)0x198C, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D58, (q15_t)0x19EF, + (q15_t)0x7D4E, (q15_t)0x1A20, (q15_t)0x7D43, (q15_t)0x1A51, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D2F, (q15_t)0x1AB3, + (q15_t)0x7D24, (q15_t)0x1AE4, (q15_t)0x7D19, (q15_t)0x1B16, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7D04, (q15_t)0x1B78, + (q15_t)0x7CF9, (q15_t)0x1BA9, (q15_t)0x7CEE, (q15_t)0x1BDA, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CD8, (q15_t)0x1C3C, + (q15_t)0x7CCD, (q15_t)0x1C6D, (q15_t)0x7CC2, (q15_t)0x1C9E, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CAB, (q15_t)0x1D00, + (q15_t)0x7CA0, (q15_t)0x1D31, (q15_t)0x7C94, (q15_t)0x1D62, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C7D, (q15_t)0x1DC4, + (q15_t)0x7C71, (q15_t)0x1DF5, (q15_t)0x7C66, (q15_t)0x1E25, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C4E, (q15_t)0x1E87, + (q15_t)0x7C42, (q15_t)0x1EB8, (q15_t)0x7C36, (q15_t)0x1EE9, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C1D, (q15_t)0x1F4A, + (q15_t)0x7C11, (q15_t)0x1F7B, (q15_t)0x7C05, (q15_t)0x1FAC, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BEB, (q15_t)0x200D, + (q15_t)0x7BDF, (q15_t)0x203E, (q15_t)0x7BD2, (q15_t)0x206E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BB9, (q15_t)0x20D0, + (q15_t)0x7BAC, (q15_t)0x2100, (q15_t)0x7B9F, (q15_t)0x2131, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B84, (q15_t)0x2192, + (q15_t)0x7B77, (q15_t)0x21C2, (q15_t)0x7B6A, (q15_t)0x21F3, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B4F, (q15_t)0x2254, + (q15_t)0x7B42, (q15_t)0x2284, (q15_t)0x7B34, (q15_t)0x22B4, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B19, (q15_t)0x2315, + (q15_t)0x7B0B, (q15_t)0x2345, (q15_t)0x7AFD, (q15_t)0x2376, + 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(q15_t)0x9842, (q15_t)0xB504, (q15_t)0x9860, (q15_t)0xB4DB, + (q15_t)0x987D, (q15_t)0xB4B3, (q15_t)0x989B, (q15_t)0xB48A, + (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98D6, (q15_t)0xB439, + (q15_t)0x98F4, (q15_t)0xB410, (q15_t)0x9912, (q15_t)0xB3E8, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x994E, (q15_t)0xB397, + (q15_t)0x996C, (q15_t)0xB36F, (q15_t)0x998A, (q15_t)0xB347, + (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99C6, (q15_t)0xB2F6, + (q15_t)0x99E5, (q15_t)0xB2CE, (q15_t)0x9A03, (q15_t)0xB2A6, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A40, (q15_t)0xB256, + (q15_t)0x9A5F, (q15_t)0xB22E, (q15_t)0x9A7D, (q15_t)0xB206, + (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9ABA, (q15_t)0xB1B7, + (q15_t)0x9AD9, (q15_t)0xB18F, (q15_t)0x9AF8, (q15_t)0xB167, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B36, (q15_t)0xB118, + (q15_t)0x9B55, (q15_t)0xB0F0, (q15_t)0x9B74, (q15_t)0xB0C9, + (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BB2, (q15_t)0xB07A, + (q15_t)0x9BD2, (q15_t)0xB053, (q15_t)0x9BF1, (q15_t)0xB02B, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C30, (q15_t)0xAFDD, + (q15_t)0x9C4F, (q15_t)0xAFB6, (q15_t)0x9C6F, (q15_t)0xAF8F, + (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CAE, (q15_t)0xAF40, + (q15_t)0x9CCE, (q15_t)0xAF1A, (q15_t)0x9CEE, (q15_t)0xAEF3, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D2D, (q15_t)0xAEA5, + (q15_t)0x9D4D, (q15_t)0xAE7E, (q15_t)0x9D6D, (q15_t)0xAE57, + (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DAE, (q15_t)0xAE0A, + (q15_t)0x9DCE, (q15_t)0xADE3, (q15_t)0x9DEE, (q15_t)0xADBD, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E2F, (q15_t)0xAD70, + (q15_t)0x9E4F, (q15_t)0xAD4A, (q15_t)0x9E70, (q15_t)0xAD23, + (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9EB1, (q15_t)0xACD7, + (q15_t)0x9ED2, (q15_t)0xACB1, (q15_t)0x9EF2, (q15_t)0xAC8A, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F34, (q15_t)0xAC3E, + (q15_t)0x9F55, (q15_t)0xAC18, (q15_t)0x9F76, (q15_t)0xABF2, + (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FB8, (q15_t)0xABA7, + (q15_t)0x9FD9, (q15_t)0xAB81, (q15_t)0x9FFB, (q15_t)0xAB5B, + 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(q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7BF, (q15_t)0x9657, + (q15_t)0xB7E9, (q15_t)0x963B, (q15_t)0xB812, (q15_t)0x961E, + (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB865, (q15_t)0x95E6, + (q15_t)0xB88F, (q15_t)0x95CA, (q15_t)0xB8B9, (q15_t)0x95AE, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB90C, (q15_t)0x9576, + (q15_t)0xB936, (q15_t)0x955A, (q15_t)0xB960, (q15_t)0x953E, + (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9B4, (q15_t)0x9507, + (q15_t)0xB9DE, (q15_t)0x94EC, (q15_t)0xBA08, (q15_t)0x94D0, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA5C, (q15_t)0x9499, + (q15_t)0xBA87, (q15_t)0x947E, (q15_t)0xBAB1, (q15_t)0x9463, + (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB05, (q15_t)0x942C, + (q15_t)0xBB30, (q15_t)0x9411, (q15_t)0xBB5A, (q15_t)0x93F6, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBAF, (q15_t)0x93C0, + (q15_t)0xBBDA, (q15_t)0x93A6, (q15_t)0xBC04, (q15_t)0x938B, + (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC5A, (q15_t)0x9356, + (q15_t)0xBC84, (q15_t)0x933B, (q15_t)0xBCAF, (q15_t)0x9321, + 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(q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3, + (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE, + (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A, + (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727, + (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6, + (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5, + (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666, + (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627, + (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA, + (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF, + (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574, + (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A, + (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502, + (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB, + (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495, + (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460, + (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D, + (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA, + (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9, + (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399, + (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B, + (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D, + (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311, + (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6, + (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC, + (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293, + (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B, + (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245, + (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220, + (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC, + (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9, + (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8, + (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198, + (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179, + (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B, + (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E, + (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123, + (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109, + (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0, + (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8, + (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2, + (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC, + (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098, + (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086, + (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074, + (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064, + (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055, + (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047, + (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A, + (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F, + (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025, + (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C, + (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014, + (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D, + (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008, + (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004, + (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001, + (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000, + (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @} end of CFFT_CIFFT group +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + +const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) +const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) +const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) +const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) +const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) +const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) +const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) +const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 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10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) +const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 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22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + +const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH] = +{ + /* 8x2, size 20 */ + 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + +const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH] = +{ + /* 8x4, size 48 */ + 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208, + 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208, + 152,224, 176,208, 184,232, 216,240, 200,224, 232,240 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + +const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH] = +{ + /* radix 8, size 56 */ + 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, + 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, + 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, + 368,424, 376,488, 440,496 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + +const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = +{ + /* 8x2, size 208 */ + 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, + 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, + 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, + 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, + 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, + 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, + 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, + 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, + 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, + 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, + 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, + 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, + 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + +const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = +{ + /* 8x4, size 440 */ + 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, + 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, + 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, + 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, + 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, + 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, + 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, + 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, + 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, + 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, + 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, + 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, + 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, + 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, + 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, + 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, + 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, + 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, + 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, + 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, + 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, + 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, + 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, + 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, + 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, + 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, + 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, + 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, + 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, + 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, + 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, + 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032, + 1960,1968, 2008,2032, 1992,2016, 2024,2032 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + +const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = +{ + /* radix 8, size 448 */ + 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, + 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, + 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, + 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, + 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, + 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, + 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, + 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, + 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, + 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, + 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, + 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, + 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, + 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, + 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, + 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, + 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, + 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, + 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, + 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, + 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, + 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, + 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, + 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, + 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, + 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, + 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, + 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, + 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, + 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, + 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, + 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, + 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, + 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, + 3448,3952, 3512,4016, 3576,4080 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + +const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH] = +{ + /* 8x2, size 1800 */ + 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, + 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, + 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, + 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, + 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, + 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, + 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, + 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, + 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, + 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, + 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, + 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, + 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, + 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, + 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, + 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, + 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, + 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, + 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, + 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, + 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, + 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, + 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, + 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, + 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, + 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, + 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, + 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, + 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, + 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, + 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, + 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, + 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, + 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, + 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, + 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, + 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, + 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, + 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, + 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, + 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, + 2152,7184, 2160,3600, 2168,7696, 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7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, + 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, + 8112,8136, 8120,8168, 8136,8160, 8152,8176 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + +const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH] = +{ + /* 8x2, size 3808 */ + 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, + 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, + 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, + 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, + 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, + 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, + 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, + 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, + 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, + 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, + 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, + 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, + 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, + 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, + 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, + 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, + 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, + 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, + 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, + 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, + 1128,5888, 1136,9984, 1144,14080, 1152,2304, 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1856,3392, + 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, + 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, + 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, + 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, + 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, + 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, + 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, + 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, + 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, + 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, + 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, + 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, + 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, + 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, + 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16216,16240, 16224,16320, 16232,16336, 16240,16352, + 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368, + 16328,16352, 16360,16368 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + +const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH] = +{ + /* radix 8, size 4032 */ + 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, + 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, + 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600, + 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016, + 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432, + 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848, + 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264, + 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680, + 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160, + 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672, + 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088, + 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760, + 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176, + 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592, + 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008, + 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424, + 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840, + 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224, + 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800, + 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216, + 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632, + 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952, + 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272, + 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848, + 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168, + 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488, + 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808, + 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384, + 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768, + 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184, + 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600, + 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016, + 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336, + 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912, + 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232, + 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552, + 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872, + 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448, + 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832, + 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248, + 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664, + 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080, + 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496, + 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816, + 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392, + 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712, + 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032, + 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416, 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25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, + 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, + 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, + 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, + 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, + 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, + 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, + 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, + 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, + 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, + 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, + 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, + 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, + 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, + 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, + 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, + 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, + 32248,32696 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + +const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) +const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) +const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) +const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) +const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) +const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) +const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) +const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, + 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, + 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, + 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, + 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, + 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, + 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, + 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, + 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, + 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, + 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, + 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, + 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, + 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, + 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) +const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 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11096,27472, 11112,23376, 11120,15184, + 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544, + 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592, + 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640, + 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808, + 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760, + 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008, + 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440, + 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176, + 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848, + 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088, + 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968, + 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824, + 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648, + 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384, + 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624, + 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528, + 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768, + 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504, + 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136, + 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088, + 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872, + 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304, + 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928, + 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808, + 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664, + 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248, + 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416, + 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368, + 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848, + 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584, + 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728, + 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360, + 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096, + 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336, + 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912, + 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152, + 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080, + 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424, + 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664, + 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592, + 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592, + 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520, + 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664, + 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296, + 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032, + 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176, + 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040, + 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968, + 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728, + 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312, + 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384, + 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624, + 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864, + 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936, + 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328, + 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472, + 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400, + 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976, + 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904, + 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048, + 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440, + 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512, + 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584, + 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728, + 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656, + 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192, + 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120, + 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264, + 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792, + 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720, + 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448, + 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376, + 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520, + 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664, + 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784, + 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080, + 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152, + 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968, + 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112, + 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944, + 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528, + 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360, + 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744, + 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768, + 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064, + 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184, + 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328, + 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048, + 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880, + 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368, + 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488, + 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824, + 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848, + 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336, + 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168, + 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128, + 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152, + 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640, + 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664, + 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664, + 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688, + 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176, + 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200, + 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824, + 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848, + 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528, + 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552, + 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768, + 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352, + 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, + 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, + 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) +/** + @par + Example code for Double Precision Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_rfft_32[32] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, //0.19509, 0.98079 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, //0.38268, 0.92388 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, //0.55557, 0.83147 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //0.70711, 0.70711 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, //0.83147, 0.55557 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, //0.92388, 0.38268 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, //0.98079, 0.19509 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, //0.98079,-0.19509 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, //0.92388,-0.38268 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, //0.83147,-0.55557 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //0.70711,-0.70711 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, //0.55557,-0.83147 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, //0.38268,-0.92388 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, //0.19509,-0.98079 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) +const uint64_t twiddleCoefF64_rfft_64[64] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) +const uint64_t twiddleCoefF64_rfft_128[128] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) +const uint64_t twiddleCoefF64_rfft_256[256] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997 + + +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) +const uint64_t twiddleCoefF64_rfft_512[512] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, //0.012272, 0.99992' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997' + 0x3fa2d865759455cd, 0x3feffa72effef75d, //0.036807, 0.99932' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3faf656e79f820e0, 0x3feff095658e71ad, //0.061321, 0.99812' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //0.085797, 0.99631' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //0.085797, -0.99631' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, //0.061321, -0.99812' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, //0.036807, -0.99932' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, //0.012272, -0.99992' + + +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) +const uint64_t twiddleCoefF64_rfft_1024[1024] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992' + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997' + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953' + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932' + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848' + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812' + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729' + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631' + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272' + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541' + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807' + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068' + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321' + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565' + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797' + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017' + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631' + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729' + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812' + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932' + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997' + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992' + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) +const uint64_t twiddleCoefF64_rfft_2048[2048] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) +const uint64_t twiddleCoefF64_rfft_4096[4096] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, //0.0046019, 0.99999 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, //0.0076698, 0.99997 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, //0.0076698, -0.99997 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, //0.0046019, -0.99999 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 +}; + +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const float32_t twiddleCoef_rfft_32[32] = { + 0.000000000f, 1.000000000f, + 0.195090322f, 0.980785280f, + 0.382683432f, 0.923879533f, + 0.555570233f, 0.831469612f, + 0.707106781f, 0.707106781f, + 0.831469612f, 0.555570233f, + 0.923879533f, 0.382683432f, + 0.980785280f, 0.195090322f, + 1.000000000f, 0.000000000f, + 0.980785280f, -0.195090322f, + 0.923879533f, -0.382683432f, + 0.831469612f, -0.555570233f, + 0.707106781f, -0.707106781f, + 0.555570233f, -0.831469612f, + 0.382683432f, -0.923879533f, + 0.195090322f, -0.980785280f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) +const float32_t twiddleCoef_rfft_64[64] = { + 0.000000000000000f, 1.000000000000000f, + 0.098017140329561f, 0.995184726672197f, + 0.195090322016128f, 0.980785280403230f, + 0.290284677254462f, 0.956940335732209f, + 0.382683432365090f, 0.923879532511287f, + 0.471396736825998f, 0.881921264348355f, + 0.555570233019602f, 0.831469612302545f, + 0.634393284163645f, 0.773010453362737f, + 0.707106781186547f, 0.707106781186548f, + 0.773010453362737f, 0.634393284163645f, + 0.831469612302545f, 0.555570233019602f, + 0.881921264348355f, 0.471396736825998f, + 0.923879532511287f, 0.382683432365090f, + 0.956940335732209f, 0.290284677254462f, + 0.980785280403230f, 0.195090322016128f, + 0.995184726672197f, 0.098017140329561f, + 1.000000000000000f, 0.000000000000000f, + 0.995184726672197f, -0.098017140329561f, + 0.980785280403230f, -0.195090322016128f, + 0.956940335732209f, -0.290284677254462f, + 0.923879532511287f, -0.382683432365090f, + 0.881921264348355f, -0.471396736825998f, + 0.831469612302545f, -0.555570233019602f, + 0.773010453362737f, -0.634393284163645f, + 0.707106781186548f, -0.707106781186547f, + 0.634393284163645f, -0.773010453362737f, + 0.555570233019602f, -0.831469612302545f, + 0.471396736825998f, -0.881921264348355f, + 0.382683432365090f, -0.923879532511287f, + 0.290284677254462f, -0.956940335732209f, + 0.195090322016129f, -0.980785280403230f, + 0.098017140329561f, -0.995184726672197f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) +const float32_t twiddleCoef_rfft_128[128] = { + 0.000000000f, 1.000000000f, + 0.049067674f, 0.998795456f, + 0.098017140f, 0.995184727f, + 0.146730474f, 0.989176510f, + 0.195090322f, 0.980785280f, + 0.242980180f, 0.970031253f, + 0.290284677f, 0.956940336f, + 0.336889853f, 0.941544065f, + 0.382683432f, 0.923879533f, + 0.427555093f, 0.903989293f, + 0.471396737f, 0.881921264f, + 0.514102744f, 0.857728610f, + 0.555570233f, 0.831469612f, + 0.595699304f, 0.803207531f, + 0.634393284f, 0.773010453f, + 0.671558955f, 0.740951125f, + 0.707106781f, 0.707106781f, + 0.740951125f, 0.671558955f, + 0.773010453f, 0.634393284f, + 0.803207531f, 0.595699304f, + 0.831469612f, 0.555570233f, + 0.857728610f, 0.514102744f, + 0.881921264f, 0.471396737f, + 0.903989293f, 0.427555093f, + 0.923879533f, 0.382683432f, + 0.941544065f, 0.336889853f, + 0.956940336f, 0.290284677f, + 0.970031253f, 0.242980180f, + 0.980785280f, 0.195090322f, + 0.989176510f, 0.146730474f, + 0.995184727f, 0.098017140f, + 0.998795456f, 0.049067674f, + 1.000000000f, 0.000000000f, + 0.998795456f, -0.049067674f, + 0.995184727f, -0.098017140f, + 0.989176510f, -0.146730474f, + 0.980785280f, -0.195090322f, + 0.970031253f, -0.242980180f, + 0.956940336f, -0.290284677f, + 0.941544065f, -0.336889853f, + 0.923879533f, -0.382683432f, + 0.903989293f, -0.427555093f, + 0.881921264f, -0.471396737f, + 0.857728610f, -0.514102744f, + 0.831469612f, -0.555570233f, + 0.803207531f, -0.595699304f, + 0.773010453f, -0.634393284f, + 0.740951125f, -0.671558955f, + 0.707106781f, -0.707106781f, + 0.671558955f, -0.740951125f, + 0.634393284f, -0.773010453f, + 0.595699304f, -0.803207531f, + 0.555570233f, -0.831469612f, + 0.514102744f, -0.857728610f, + 0.471396737f, -0.881921264f, + 0.427555093f, -0.903989293f, + 0.382683432f, -0.923879533f, + 0.336889853f, -0.941544065f, + 0.290284677f, -0.956940336f, + 0.242980180f, -0.970031253f, + 0.195090322f, -0.980785280f, + 0.146730474f, -0.989176510f, + 0.098017140f, -0.995184727f, + 0.049067674f, -0.998795456f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) +const float32_t twiddleCoef_rfft_256[256] = { + 0.000000000f, 1.000000000f, + 0.024541229f, 0.999698819f, + 0.049067674f, 0.998795456f, + 0.073564564f, 0.997290457f, + 0.098017140f, 0.995184727f, + 0.122410675f, 0.992479535f, + 0.146730474f, 0.989176510f, + 0.170961889f, 0.985277642f, + 0.195090322f, 0.980785280f, + 0.219101240f, 0.975702130f, + 0.242980180f, 0.970031253f, + 0.266712757f, 0.963776066f, + 0.290284677f, 0.956940336f, + 0.313681740f, 0.949528181f, + 0.336889853f, 0.941544065f, + 0.359895037f, 0.932992799f, + 0.382683432f, 0.923879533f, + 0.405241314f, 0.914209756f, + 0.427555093f, 0.903989293f, + 0.449611330f, 0.893224301f, + 0.471396737f, 0.881921264f, + 0.492898192f, 0.870086991f, + 0.514102744f, 0.857728610f, + 0.534997620f, 0.844853565f, + 0.555570233f, 0.831469612f, + 0.575808191f, 0.817584813f, + 0.595699304f, 0.803207531f, + 0.615231591f, 0.788346428f, + 0.634393284f, 0.773010453f, + 0.653172843f, 0.757208847f, + 0.671558955f, 0.740951125f, + 0.689540545f, 0.724247083f, + 0.707106781f, 0.707106781f, + 0.724247083f, 0.689540545f, + 0.740951125f, 0.671558955f, + 0.757208847f, 0.653172843f, + 0.773010453f, 0.634393284f, + 0.788346428f, 0.615231591f, + 0.803207531f, 0.595699304f, + 0.817584813f, 0.575808191f, + 0.831469612f, 0.555570233f, + 0.844853565f, 0.534997620f, + 0.857728610f, 0.514102744f, + 0.870086991f, 0.492898192f, + 0.881921264f, 0.471396737f, + 0.893224301f, 0.449611330f, + 0.903989293f, 0.427555093f, + 0.914209756f, 0.405241314f, + 0.923879533f, 0.382683432f, + 0.932992799f, 0.359895037f, + 0.941544065f, 0.336889853f, + 0.949528181f, 0.313681740f, + 0.956940336f, 0.290284677f, + 0.963776066f, 0.266712757f, + 0.970031253f, 0.242980180f, + 0.975702130f, 0.219101240f, + 0.980785280f, 0.195090322f, + 0.985277642f, 0.170961889f, + 0.989176510f, 0.146730474f, + 0.992479535f, 0.122410675f, + 0.995184727f, 0.098017140f, + 0.997290457f, 0.073564564f, + 0.998795456f, 0.049067674f, + 0.999698819f, 0.024541229f, + 1.000000000f, 0.000000000f, + 0.999698819f, -0.024541229f, + 0.998795456f, -0.049067674f, + 0.997290457f, -0.073564564f, + 0.995184727f, -0.098017140f, + 0.992479535f, -0.122410675f, + 0.989176510f, -0.146730474f, + 0.985277642f, -0.170961889f, + 0.980785280f, -0.195090322f, + 0.975702130f, -0.219101240f, + 0.970031253f, -0.242980180f, + 0.963776066f, -0.266712757f, + 0.956940336f, -0.290284677f, + 0.949528181f, -0.313681740f, + 0.941544065f, -0.336889853f, + 0.932992799f, -0.359895037f, + 0.923879533f, -0.382683432f, + 0.914209756f, -0.405241314f, + 0.903989293f, -0.427555093f, + 0.893224301f, -0.449611330f, + 0.881921264f, -0.471396737f, + 0.870086991f, -0.492898192f, + 0.857728610f, -0.514102744f, + 0.844853565f, -0.534997620f, + 0.831469612f, -0.555570233f, + 0.817584813f, -0.575808191f, + 0.803207531f, -0.595699304f, + 0.788346428f, -0.615231591f, + 0.773010453f, -0.634393284f, + 0.757208847f, -0.653172843f, + 0.740951125f, -0.671558955f, + 0.724247083f, -0.689540545f, + 0.707106781f, -0.707106781f, + 0.689540545f, -0.724247083f, + 0.671558955f, -0.740951125f, + 0.653172843f, -0.757208847f, + 0.634393284f, -0.773010453f, + 0.615231591f, -0.788346428f, + 0.595699304f, -0.803207531f, + 0.575808191f, -0.817584813f, + 0.555570233f, -0.831469612f, + 0.534997620f, -0.844853565f, + 0.514102744f, -0.857728610f, + 0.492898192f, -0.870086991f, + 0.471396737f, -0.881921264f, + 0.449611330f, -0.893224301f, + 0.427555093f, -0.903989293f, + 0.405241314f, -0.914209756f, + 0.382683432f, -0.923879533f, + 0.359895037f, -0.932992799f, + 0.336889853f, -0.941544065f, + 0.313681740f, -0.949528181f, + 0.290284677f, -0.956940336f, + 0.266712757f, -0.963776066f, + 0.242980180f, -0.970031253f, + 0.219101240f, -0.975702130f, + 0.195090322f, -0.980785280f, + 0.170961889f, -0.985277642f, + 0.146730474f, -0.989176510f, + 0.122410675f, -0.992479535f, + 0.098017140f, -0.995184727f, + 0.073564564f, -0.997290457f, + 0.049067674f, -0.998795456f, + 0.024541229f, -0.999698819f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) +const float32_t twiddleCoef_rfft_512[512] = { + 0.000000000f, 1.000000000f, + 0.012271538f, 0.999924702f, + 0.024541229f, 0.999698819f, + 0.036807223f, 0.999322385f, + 0.049067674f, 0.998795456f, + 0.061320736f, 0.998118113f, + 0.073564564f, 0.997290457f, + 0.085797312f, 0.996312612f, + 0.098017140f, 0.995184727f, + 0.110222207f, 0.993906970f, + 0.122410675f, 0.992479535f, + 0.134580709f, 0.990902635f, + 0.146730474f, 0.989176510f, + 0.158858143f, 0.987301418f, + 0.170961889f, 0.985277642f, + 0.183039888f, 0.983105487f, + 0.195090322f, 0.980785280f, + 0.207111376f, 0.978317371f, + 0.219101240f, 0.975702130f, + 0.231058108f, 0.972939952f, + 0.242980180f, 0.970031253f, + 0.254865660f, 0.966976471f, + 0.266712757f, 0.963776066f, + 0.278519689f, 0.960430519f, + 0.290284677f, 0.956940336f, + 0.302005949f, 0.953306040f, + 0.313681740f, 0.949528181f, + 0.325310292f, 0.945607325f, + 0.336889853f, 0.941544065f, + 0.348418680f, 0.937339012f, + 0.359895037f, 0.932992799f, + 0.371317194f, 0.928506080f, + 0.382683432f, 0.923879533f, + 0.393992040f, 0.919113852f, + 0.405241314f, 0.914209756f, + 0.416429560f, 0.909167983f, + 0.427555093f, 0.903989293f, + 0.438616239f, 0.898674466f, + 0.449611330f, 0.893224301f, + 0.460538711f, 0.887639620f, + 0.471396737f, 0.881921264f, + 0.482183772f, 0.876070094f, + 0.492898192f, 0.870086991f, + 0.503538384f, 0.863972856f, + 0.514102744f, 0.857728610f, + 0.524589683f, 0.851355193f, + 0.534997620f, 0.844853565f, + 0.545324988f, 0.838224706f, + 0.555570233f, 0.831469612f, + 0.565731811f, 0.824589303f, + 0.575808191f, 0.817584813f, + 0.585797857f, 0.810457198f, + 0.595699304f, 0.803207531f, + 0.605511041f, 0.795836905f, + 0.615231591f, 0.788346428f, + 0.624859488f, 0.780737229f, + 0.634393284f, 0.773010453f, + 0.643831543f, 0.765167266f, + 0.653172843f, 0.757208847f, + 0.662415778f, 0.749136395f, + 0.671558955f, 0.740951125f, + 0.680600998f, 0.732654272f, + 0.689540545f, 0.724247083f, + 0.698376249f, 0.715730825f, + 0.707106781f, 0.707106781f, + 0.715730825f, 0.698376249f, + 0.724247083f, 0.689540545f, + 0.732654272f, 0.680600998f, + 0.740951125f, 0.671558955f, + 0.749136395f, 0.662415778f, + 0.757208847f, 0.653172843f, + 0.765167266f, 0.643831543f, + 0.773010453f, 0.634393284f, + 0.780737229f, 0.624859488f, + 0.788346428f, 0.615231591f, + 0.795836905f, 0.605511041f, + 0.803207531f, 0.595699304f, + 0.810457198f, 0.585797857f, + 0.817584813f, 0.575808191f, + 0.824589303f, 0.565731811f, + 0.831469612f, 0.555570233f, + 0.838224706f, 0.545324988f, + 0.844853565f, 0.534997620f, + 0.851355193f, 0.524589683f, + 0.857728610f, 0.514102744f, + 0.863972856f, 0.503538384f, + 0.870086991f, 0.492898192f, + 0.876070094f, 0.482183772f, + 0.881921264f, 0.471396737f, + 0.887639620f, 0.460538711f, + 0.893224301f, 0.449611330f, + 0.898674466f, 0.438616239f, + 0.903989293f, 0.427555093f, + 0.909167983f, 0.416429560f, + 0.914209756f, 0.405241314f, + 0.919113852f, 0.393992040f, + 0.923879533f, 0.382683432f, + 0.928506080f, 0.371317194f, + 0.932992799f, 0.359895037f, + 0.937339012f, 0.348418680f, + 0.941544065f, 0.336889853f, + 0.945607325f, 0.325310292f, + 0.949528181f, 0.313681740f, + 0.953306040f, 0.302005949f, + 0.956940336f, 0.290284677f, + 0.960430519f, 0.278519689f, + 0.963776066f, 0.266712757f, + 0.966976471f, 0.254865660f, + 0.970031253f, 0.242980180f, + 0.972939952f, 0.231058108f, + 0.975702130f, 0.219101240f, + 0.978317371f, 0.207111376f, + 0.980785280f, 0.195090322f, + 0.983105487f, 0.183039888f, + 0.985277642f, 0.170961889f, + 0.987301418f, 0.158858143f, + 0.989176510f, 0.146730474f, + 0.990902635f, 0.134580709f, + 0.992479535f, 0.122410675f, + 0.993906970f, 0.110222207f, + 0.995184727f, 0.098017140f, + 0.996312612f, 0.085797312f, + 0.997290457f, 0.073564564f, + 0.998118113f, 0.061320736f, + 0.998795456f, 0.049067674f, + 0.999322385f, 0.036807223f, + 0.999698819f, 0.024541229f, + 0.999924702f, 0.012271538f, + 1.000000000f, 0.000000000f, + 0.999924702f, -0.012271538f, + 0.999698819f, -0.024541229f, + 0.999322385f, -0.036807223f, + 0.998795456f, -0.049067674f, + 0.998118113f, -0.061320736f, + 0.997290457f, -0.073564564f, + 0.996312612f, -0.085797312f, + 0.995184727f, -0.098017140f, + 0.993906970f, -0.110222207f, + 0.992479535f, -0.122410675f, + 0.990902635f, -0.134580709f, + 0.989176510f, -0.146730474f, + 0.987301418f, -0.158858143f, + 0.985277642f, -0.170961889f, + 0.983105487f, -0.183039888f, + 0.980785280f, -0.195090322f, + 0.978317371f, -0.207111376f, + 0.975702130f, -0.219101240f, + 0.972939952f, -0.231058108f, + 0.970031253f, -0.242980180f, + 0.966976471f, -0.254865660f, + 0.963776066f, -0.266712757f, + 0.960430519f, -0.278519689f, + 0.956940336f, -0.290284677f, + 0.953306040f, -0.302005949f, + 0.949528181f, -0.313681740f, + 0.945607325f, -0.325310292f, + 0.941544065f, -0.336889853f, + 0.937339012f, -0.348418680f, + 0.932992799f, -0.359895037f, + 0.928506080f, -0.371317194f, + 0.923879533f, -0.382683432f, + 0.919113852f, -0.393992040f, + 0.914209756f, -0.405241314f, + 0.909167983f, -0.416429560f, + 0.903989293f, -0.427555093f, + 0.898674466f, -0.438616239f, + 0.893224301f, -0.449611330f, + 0.887639620f, -0.460538711f, + 0.881921264f, -0.471396737f, + 0.876070094f, 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-0.960430519f, + 0.266712757f, -0.963776066f, + 0.254865660f, -0.966976471f, + 0.242980180f, -0.970031253f, + 0.231058108f, -0.972939952f, + 0.219101240f, -0.975702130f, + 0.207111376f, -0.978317371f, + 0.195090322f, -0.980785280f, + 0.183039888f, -0.983105487f, + 0.170961889f, -0.985277642f, + 0.158858143f, -0.987301418f, + 0.146730474f, -0.989176510f, + 0.134580709f, -0.990902635f, + 0.122410675f, -0.992479535f, + 0.110222207f, -0.993906970f, + 0.098017140f, -0.995184727f, + 0.085797312f, -0.996312612f, + 0.073564564f, -0.997290457f, + 0.061320736f, -0.998118113f, + 0.049067674f, -0.998795456f, + 0.036807223f, -0.999322385f, + 0.024541229f, -0.999698819f, + 0.012271538f, -0.999924702f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) +const float32_t twiddleCoef_rfft_1024[1024] = { + 0.000000000f, 1.000000000f, + 0.006135885f, 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-0.999322385f, + 0.035274239f, -0.999377670f, + 0.033741172f, -0.999430605f, + 0.032208025f, -0.999481187f, + 0.030674803f, -0.999529418f, + 0.029141509f, -0.999575296f, + 0.027608146f, -0.999618822f, + 0.026074718f, -0.999659997f, + 0.024541229f, -0.999698819f, + 0.023007681f, -0.999735288f, + 0.021474080f, -0.999769405f, + 0.019940429f, -0.999801170f, + 0.018406730f, -0.999830582f, + 0.016872988f, -0.999857641f, + 0.015339206f, -0.999882347f, + 0.013805389f, -0.999904701f, + 0.012271538f, -0.999924702f, + 0.010737659f, -0.999942350f, + 0.009203755f, -0.999957645f, + 0.007669829f, -0.999970586f, + 0.006135885f, -0.999981175f, + 0.004601926f, -0.999989411f, + 0.003067957f, -0.999995294f, + 0.001533980f, -0.999998823f +}; + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALL_TABLES) */ + +/** + @ingroup RealFFT + */ + +/** + @addtogroup RealFFT_Table Real FFT Tables + @{ + */ + +/** + @par + Generation of realCoefA array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) +const float32_t realCoefA[8192] = { + 0.500000000000000f, -0.500000000000000f, 0.499616503715515f, -0.499999850988388f, + 0.499233007431030f, -0.499999403953552f, 0.498849511146545f, -0.499998688697815f, + 0.498466014862061f, -0.499997645616531f, 0.498082518577576f, -0.499996334314346f, + 0.497699022293091f, -0.499994695186615f, 0.497315555810928f, -0.499992787837982f, + 0.496932059526443f, -0.499990582466125f, 0.496548563241959f, -0.499988079071045f, + 0.496165096759796f, -0.499985307455063f, 0.495781600475311f, -0.499982208013535f, + 0.495398133993149f, -0.499978810548782f, 0.495014637708664f, -0.499975144863129f, + 0.494631171226501f, -0.499971181154251f, 0.494247704744339f, -0.499966919422150f, + 0.493864238262177f, -0.499962359666824f, 0.493480771780014f, -0.499957501888275f, + 0.493097305297852f, -0.499952346086502f, 0.492713838815689f, -0.499946922063828f, + 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0.485045909881592f, 0.499776333570480f, + 0.485429257154465f, 0.499787658452988f, 0.485812574625015f, 0.499798685312271f, + 0.486195921897888f, 0.499809414148331f, 0.486579269170761f, 0.499819844961166f, + 0.486962646245956f, 0.499830007553101f, 0.487346023321152f, 0.499839842319489f, + 0.487729400396347f, 0.499849408864975f, 0.488112777471542f, 0.499858677387238f, + 0.488496154546738f, 0.499867647886276f, 0.488879561424255f, 0.499876320362091f, + 0.489262968301773f, 0.499884694814682f, 0.489646375179291f, 0.499892801046371f, + 0.490029782056808f, 0.499900579452515f, 0.490413218736649f, 0.499908089637756f, + 0.490796625614166f, 0.499915301799774f, 0.491180062294006f, 0.499922215938568f, + 0.491563498973846f, 0.499928832054138f, 0.491946935653687f, 0.499935150146484f, + 0.492330402135849f, 0.499941170215607f, 0.492713838815689f, 0.499946922063828f, + 0.493097305297852f, 0.499952346086502f, 0.493480771780014f, 0.499957501888275f, + 0.493864238262177f, 0.499962359666824f, 0.494247704744339f, 0.499966919422150f, + 0.494631171226501f, 0.499971181154251f, 0.495014637708664f, 0.499975144863129f, + 0.495398133993149f, 0.499978810548782f, 0.495781600475311f, 0.499982208013535f, + 0.496165096759796f, 0.499985307455063f, 0.496548563241959f, 0.499988079071045f, + 0.496932059526443f, 0.499990582466125f, 0.497315555810928f, 0.499992787837982f, + 0.497699022293091f, 0.499994695186615f, 0.498082518577576f, 0.499996334314346f, + 0.498466014862061f, 0.499997645616531f, 0.498849511146545f, 0.499998688697815f, + 0.499233007431030f, 0.499999403953552f, 0.499616503715515f, 0.499999850988388f, +}; + + +/** + @par + Generation of realCoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +const float32_t realCoefB[8192] = { + 0.500000000000000f, 0.500000000000000f, 0.500383496284485f, 0.499999850988388f, + 0.500766992568970f, 0.499999403953552f, 0.501150488853455f, 0.499998688697815f, + 0.501533985137939f, 0.499997645616531f, 0.501917481422424f, 0.499996334314346f, + 0.502300977706909f, 0.499994695186615f, 0.502684473991394f, 0.499992787837982f, + 0.503067970275879f, 0.499990582466125f, 0.503451406955719f, 0.499988079071045f, + 0.503834903240204f, 0.499985307455063f, 0.504218399524689f, 0.499982208013535f, + 0.504601895809174f, 0.499978810548782f, 0.504985332489014f, 0.499975144863129f, + 0.505368828773499f, 0.499971181154251f, 0.505752325057983f, 0.499966919422150f, + 0.506135761737823f, 0.499962359666824f, 0.506519258022308f, 0.499957501888275f, + 0.506902694702148f, 0.499952346086502f, 0.507286131381989f, 0.499946922063828f, + 0.507669627666473f, 0.499941170215607f, 0.508053064346313f, 0.499935150146484f, + 0.508436501026154f, 0.499928832054138f, 0.508819937705994f, 0.499922215938568f, + 0.509203374385834f, 0.499915301799774f, 0.509586811065674f, 0.499908089637756f, + 0.509970188140869f, 0.499900579452515f, 0.510353624820709f, 0.499892801046371f, + 0.510737061500549f, 0.499884694814682f, 0.511120438575745f, 0.499876320362091f, + 0.511503815650940f, 0.499867647886276f, 0.511887252330780f, 0.499858677387238f, + 0.512270629405975f, 0.499849408864975f, 0.512654006481171f, 0.499839842319489f, + 0.513037383556366f, 0.499830007553101f, 0.513420701026917f, 0.499819844961166f, + 0.513804078102112f, 0.499809414148331f, 0.514187395572662f, 0.499798685312271f, + 0.514570772647858f, 0.499787658452988f, 0.514954090118408f, 0.499776333570480f, + 0.515337407588959f, 0.499764710664749f, 0.515720725059509f, 0.499752789735794f, + 0.516103982925415f, 0.499740600585938f, 0.516487300395966f, 0.499728083610535f, + 0.516870558261871f, 0.499715298414230f, 0.517253875732422f, 0.499702215194702f, + 0.517637133598328f, 0.499688833951950f, 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for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pATable[i] * pow(2, 31)) +*/ +const q31_t realCoefAQ31[8192] = { + (q31_t)0x40000000, (q31_t)0xc0000000, (q31_t)0x3ff36f02, (q31_t)0xc000013c, + (q31_t)0x3fe6de05, (q31_t)0xc00004ef, (q31_t)0x3fda4d09, (q31_t)0xc0000b1a, + (q31_t)0x3fcdbc0f, (q31_t)0xc00013bd, (q31_t)0x3fc12b16, (q31_t)0xc0001ed8, + (q31_t)0x3fb49a1f, (q31_t)0xc0002c6a, (q31_t)0x3fa8092c, (q31_t)0xc0003c74, + (q31_t)0x3f9b783c, (q31_t)0xc0004ef5, (q31_t)0x3f8ee750, (q31_t)0xc00063ee, + (q31_t)0x3f825668, (q31_t)0xc0007b5f, (q31_t)0x3f75c585, (q31_t)0xc0009547, + (q31_t)0x3f6934a8, (q31_t)0xc000b1a7, (q31_t)0x3f5ca3d0, (q31_t)0xc000d07e, + (q31_t)0x3f5012fe, (q31_t)0xc000f1ce, (q31_t)0x3f438234, (q31_t)0xc0011594, + (q31_t)0x3f36f170, (q31_t)0xc0013bd3, (q31_t)0x3f2a60b4, (q31_t)0xc0016489, + (q31_t)0x3f1dd001, (q31_t)0xc0018fb6, (q31_t)0x3f113f56, (q31_t)0xc001bd5c, + (q31_t)0x3f04aeb5, (q31_t)0xc001ed78, (q31_t)0x3ef81e1d, (q31_t)0xc002200d, + (q31_t)0x3eeb8d8f, (q31_t)0xc0025519, (q31_t)0x3edefd0c, (q31_t)0xc0028c9c, + (q31_t)0x3ed26c94, (q31_t)0xc002c697, (q31_t)0x3ec5dc28, (q31_t)0xc003030a, + (q31_t)0x3eb94bc8, (q31_t)0xc00341f4, (q31_t)0x3eacbb74, (q31_t)0xc0038356, + (q31_t)0x3ea02b2e, (q31_t)0xc003c72f, (q31_t)0x3e939af5, (q31_t)0xc0040d80, + (q31_t)0x3e870aca, (q31_t)0xc0045648, (q31_t)0x3e7a7aae, (q31_t)0xc004a188, + (q31_t)0x3e6deaa1, (q31_t)0xc004ef3f, (q31_t)0x3e615aa3, (q31_t)0xc0053f6e, + (q31_t)0x3e54cab5, (q31_t)0xc0059214, (q31_t)0x3e483ad8, (q31_t)0xc005e731, + (q31_t)0x3e3bab0b, (q31_t)0xc0063ec6, (q31_t)0x3e2f1b50, (q31_t)0xc00698d3, + (q31_t)0x3e228ba7, (q31_t)0xc006f556, (q31_t)0x3e15fc11, (q31_t)0xc0075452, + (q31_t)0x3e096c8d, (q31_t)0xc007b5c4, (q31_t)0x3dfcdd1d, (q31_t)0xc00819ae, + (q31_t)0x3df04dc0, (q31_t)0xc008800f, (q31_t)0x3de3be78, (q31_t)0xc008e8e8, + (q31_t)0x3dd72f45, (q31_t)0xc0095438, (q31_t)0x3dcaa027, (q31_t)0xc009c1ff, + (q31_t)0x3dbe111e, (q31_t)0xc00a323d, (q31_t)0x3db1822c, (q31_t)0xc00aa4f3, + (q31_t)0x3da4f351, (q31_t)0xc00b1a20, (q31_t)0x3d98648d, (q31_t)0xc00b91c4, + (q31_t)0x3d8bd5e1, (q31_t)0xc00c0be0, (q31_t)0x3d7f474d, (q31_t)0xc00c8872, + (q31_t)0x3d72b8d2, (q31_t)0xc00d077c, (q31_t)0x3d662a70, (q31_t)0xc00d88fd, + (q31_t)0x3d599c28, (q31_t)0xc00e0cf5, (q31_t)0x3d4d0df9, (q31_t)0xc00e9364, + (q31_t)0x3d407fe6, (q31_t)0xc00f1c4a, (q31_t)0x3d33f1ed, (q31_t)0xc00fa7a8, + (q31_t)0x3d276410, (q31_t)0xc010357c, (q31_t)0x3d1ad650, (q31_t)0xc010c5c7, + (q31_t)0x3d0e48ab, (q31_t)0xc011588a, (q31_t)0x3d01bb24, (q31_t)0xc011edc3, + (q31_t)0x3cf52dbb, (q31_t)0xc0128574, (q31_t)0x3ce8a06f, (q31_t)0xc0131f9b, + (q31_t)0x3cdc1342, (q31_t)0xc013bc39, (q31_t)0x3ccf8634, (q31_t)0xc0145b4e, + (q31_t)0x3cc2f945, (q31_t)0xc014fcda, (q31_t)0x3cb66c77, (q31_t)0xc015a0dd, + (q31_t)0x3ca9dfc8, (q31_t)0xc0164757, (q31_t)0x3c9d533b, (q31_t)0xc016f047, + (q31_t)0x3c90c6cf, (q31_t)0xc0179bae, (q31_t)0x3c843a85, (q31_t)0xc018498c, + (q31_t)0x3c77ae5e, (q31_t)0xc018f9e1, (q31_t)0x3c6b2259, (q31_t)0xc019acac, + (q31_t)0x3c5e9678, (q31_t)0xc01a61ee, (q31_t)0x3c520aba, (q31_t)0xc01b19a7, + (q31_t)0x3c457f21, (q31_t)0xc01bd3d6, (q31_t)0x3c38f3ac, (q31_t)0xc01c907c, + (q31_t)0x3c2c685d, (q31_t)0xc01d4f99, (q31_t)0x3c1fdd34, (q31_t)0xc01e112b, + (q31_t)0x3c135231, (q31_t)0xc01ed535, (q31_t)0x3c06c754, (q31_t)0xc01f9bb5, + (q31_t)0x3bfa3c9f, (q31_t)0xc02064ab, (q31_t)0x3bedb212, (q31_t)0xc0213018, + (q31_t)0x3be127ac, (q31_t)0xc021fdfb, (q31_t)0x3bd49d70, (q31_t)0xc022ce54, + (q31_t)0x3bc8135c, (q31_t)0xc023a124, (q31_t)0x3bbb8973, (q31_t)0xc024766a, + (q31_t)0x3baeffb3, (q31_t)0xc0254e27, (q31_t)0x3ba2761e, (q31_t)0xc0262859, + (q31_t)0x3b95ecb4, (q31_t)0xc0270502, (q31_t)0x3b896375, (q31_t)0xc027e421, + (q31_t)0x3b7cda63, (q31_t)0xc028c5b6, (q31_t)0x3b70517d, (q31_t)0xc029a9c1, + (q31_t)0x3b63c8c4, (q31_t)0xc02a9042, (q31_t)0x3b574039, (q31_t)0xc02b7939, + (q31_t)0x3b4ab7db, (q31_t)0xc02c64a6, (q31_t)0x3b3e2fac, (q31_t)0xc02d5289, + (q31_t)0x3b31a7ac, (q31_t)0xc02e42e2, (q31_t)0x3b251fdc, (q31_t)0xc02f35b1, + (q31_t)0x3b18983b, (q31_t)0xc0302af5, (q31_t)0x3b0c10cb, (q31_t)0xc03122b0, + (q31_t)0x3aff898c, (q31_t)0xc0321ce0, (q31_t)0x3af3027e, (q31_t)0xc0331986, + (q31_t)0x3ae67ba2, (q31_t)0xc03418a2, (q31_t)0x3ad9f4f8, (q31_t)0xc0351a33, + (q31_t)0x3acd6e81, (q31_t)0xc0361e3a, (q31_t)0x3ac0e83d, (q31_t)0xc03724b6, + (q31_t)0x3ab4622d, (q31_t)0xc0382da8, (q31_t)0x3aa7dc52, (q31_t)0xc0393910, + (q31_t)0x3a9b56ab, (q31_t)0xc03a46ed, (q31_t)0x3a8ed139, (q31_t)0xc03b573f, + (q31_t)0x3a824bfd, (q31_t)0xc03c6a07, (q31_t)0x3a75c6f8, (q31_t)0xc03d7f44, + (q31_t)0x3a694229, (q31_t)0xc03e96f6, (q31_t)0x3a5cbd91, (q31_t)0xc03fb11d, + (q31_t)0x3a503930, (q31_t)0xc040cdba, (q31_t)0x3a43b508, (q31_t)0xc041eccc, + (q31_t)0x3a373119, (q31_t)0xc0430e53, (q31_t)0x3a2aad62, (q31_t)0xc044324f, + (q31_t)0x3a1e29e5, (q31_t)0xc04558c0, (q31_t)0x3a11a6a3, (q31_t)0xc04681a6, + (q31_t)0x3a05239a, (q31_t)0xc047ad01, (q31_t)0x39f8a0cd, (q31_t)0xc048dad1, + (q31_t)0x39ec1e3b, (q31_t)0xc04a0b16, (q31_t)0x39df9be6, (q31_t)0xc04b3dcf, + (q31_t)0x39d319cc, (q31_t)0xc04c72fe, (q31_t)0x39c697f0, (q31_t)0xc04daaa1, + (q31_t)0x39ba1651, (q31_t)0xc04ee4b8, (q31_t)0x39ad94f0, (q31_t)0xc0502145, + (q31_t)0x39a113cd, (q31_t)0xc0516045, (q31_t)0x399492ea, (q31_t)0xc052a1bb, + (q31_t)0x39881245, (q31_t)0xc053e5a5, (q31_t)0x397b91e1, (q31_t)0xc0552c03, + (q31_t)0x396f11bc, (q31_t)0xc05674d6, (q31_t)0x396291d9, (q31_t)0xc057c01d, + (q31_t)0x39561237, (q31_t)0xc0590dd8, (q31_t)0x394992d7, (q31_t)0xc05a5e07, + (q31_t)0x393d13b8, (q31_t)0xc05bb0ab, (q31_t)0x393094dd, (q31_t)0xc05d05c3, + (q31_t)0x39241645, (q31_t)0xc05e5d4e, (q31_t)0x391797f0, (q31_t)0xc05fb74e, + (q31_t)0x390b19e0, (q31_t)0xc06113c2, (q31_t)0x38fe9c15, (q31_t)0xc06272aa, + (q31_t)0x38f21e8e, (q31_t)0xc063d405, (q31_t)0x38e5a14d, (q31_t)0xc06537d4, + (q31_t)0x38d92452, (q31_t)0xc0669e18, (q31_t)0x38cca79e, (q31_t)0xc06806ce, + (q31_t)0x38c02b31, (q31_t)0xc06971f9, (q31_t)0x38b3af0c, (q31_t)0xc06adf97, + (q31_t)0x38a7332e, (q31_t)0xc06c4fa8, (q31_t)0x389ab799, (q31_t)0xc06dc22e, + (q31_t)0x388e3c4d, (q31_t)0xc06f3726, (q31_t)0x3881c14b, (q31_t)0xc070ae92, + (q31_t)0x38754692, (q31_t)0xc0722871, (q31_t)0x3868cc24, (q31_t)0xc073a4c3, + (q31_t)0x385c5201, (q31_t)0xc0752389, (q31_t)0x384fd829, (q31_t)0xc076a4c2, + (q31_t)0x38435e9d, (q31_t)0xc078286e, (q31_t)0x3836e55d, (q31_t)0xc079ae8c, + (q31_t)0x382a6c6a, (q31_t)0xc07b371e, (q31_t)0x381df3c5, (q31_t)0xc07cc223, + (q31_t)0x38117b6d, (q31_t)0xc07e4f9b, (q31_t)0x38050364, (q31_t)0xc07fdf85, + (q31_t)0x37f88ba9, (q31_t)0xc08171e2, (q31_t)0x37ec143e, (q31_t)0xc08306b2, + (q31_t)0x37df9d22, (q31_t)0xc0849df4, (q31_t)0x37d32657, (q31_t)0xc08637a9, + (q31_t)0x37c6afdc, (q31_t)0xc087d3d0, (q31_t)0x37ba39b3, (q31_t)0xc089726a, + (q31_t)0x37adc3db, (q31_t)0xc08b1376, (q31_t)0x37a14e55, (q31_t)0xc08cb6f5, + (q31_t)0x3794d922, (q31_t)0xc08e5ce5, (q31_t)0x37886442, (q31_t)0xc0900548, + (q31_t)0x377befb5, (q31_t)0xc091b01d, (q31_t)0x376f7b7d, (q31_t)0xc0935d64, + (q31_t)0x37630799, (q31_t)0xc0950d1d, (q31_t)0x3756940a, (q31_t)0xc096bf48, + (q31_t)0x374a20d0, (q31_t)0xc09873e4, (q31_t)0x373daded, (q31_t)0xc09a2af3, + (q31_t)0x37313b60, (q31_t)0xc09be473, (q31_t)0x3724c92a, (q31_t)0xc09da065, + (q31_t)0x3718574b, (q31_t)0xc09f5ec8, (q31_t)0x370be5c4, (q31_t)0xc0a11f9d, + (q31_t)0x36ff7496, (q31_t)0xc0a2e2e3, (q31_t)0x36f303c0, (q31_t)0xc0a4a89b, + (q31_t)0x36e69344, (q31_t)0xc0a670c4, (q31_t)0x36da2321, (q31_t)0xc0a83b5e, + (q31_t)0x36cdb359, (q31_t)0xc0aa086a, (q31_t)0x36c143ec, (q31_t)0xc0abd7e6, + (q31_t)0x36b4d4d9, (q31_t)0xc0ada9d4, (q31_t)0x36a86623, (q31_t)0xc0af7e33, + (q31_t)0x369bf7c9, (q31_t)0xc0b15502, (q31_t)0x368f89cb, (q31_t)0xc0b32e42, + (q31_t)0x36831c2b, (q31_t)0xc0b509f3, (q31_t)0x3676aee8, (q31_t)0xc0b6e815, + (q31_t)0x366a4203, (q31_t)0xc0b8c8a7, (q31_t)0x365dd57d, (q31_t)0xc0baabaa, + (q31_t)0x36516956, (q31_t)0xc0bc911d, (q31_t)0x3644fd8f, (q31_t)0xc0be7901, + (q31_t)0x36389228, (q31_t)0xc0c06355, (q31_t)0x362c2721, (q31_t)0xc0c25019, + (q31_t)0x361fbc7b, (q31_t)0xc0c43f4d, (q31_t)0x36135237, (q31_t)0xc0c630f2, + (q31_t)0x3606e854, (q31_t)0xc0c82506, (q31_t)0x35fa7ed4, (q31_t)0xc0ca1b8a, + (q31_t)0x35ee15b7, (q31_t)0xc0cc147f, (q31_t)0x35e1acfd, (q31_t)0xc0ce0fe3, + (q31_t)0x35d544a7, (q31_t)0xc0d00db6, (q31_t)0x35c8dcb6, (q31_t)0xc0d20dfa, + (q31_t)0x35bc7529, (q31_t)0xc0d410ad, (q31_t)0x35b00e02, (q31_t)0xc0d615cf, + (q31_t)0x35a3a740, (q31_t)0xc0d81d61, (q31_t)0x359740e5, (q31_t)0xc0da2762, + (q31_t)0x358adaf0, (q31_t)0xc0dc33d2, (q31_t)0x357e7563, (q31_t)0xc0de42b2, + (q31_t)0x3572103d, (q31_t)0xc0e05401, (q31_t)0x3565ab80, (q31_t)0xc0e267be, + (q31_t)0x3559472b, (q31_t)0xc0e47deb, (q31_t)0x354ce33f, (q31_t)0xc0e69686, + (q31_t)0x35407fbd, (q31_t)0xc0e8b190, (q31_t)0x35341ca5, (q31_t)0xc0eacf09, + (q31_t)0x3527b9f7, (q31_t)0xc0eceef1, (q31_t)0x351b57b5, (q31_t)0xc0ef1147, + (q31_t)0x350ef5de, (q31_t)0xc0f1360b, (q31_t)0x35029473, (q31_t)0xc0f35d3e, + (q31_t)0x34f63374, (q31_t)0xc0f586df, (q31_t)0x34e9d2e3, (q31_t)0xc0f7b2ee, + (q31_t)0x34dd72be, (q31_t)0xc0f9e16b, (q31_t)0x34d11308, (q31_t)0xc0fc1257, + (q31_t)0x34c4b3c0, (q31_t)0xc0fe45b0, (q31_t)0x34b854e7, (q31_t)0xc1007b77, + (q31_t)0x34abf67e, (q31_t)0xc102b3ac, (q31_t)0x349f9884, (q31_t)0xc104ee4f, + (q31_t)0x34933afa, (q31_t)0xc1072b5f, (q31_t)0x3486dde1, (q31_t)0xc1096add, + (q31_t)0x347a8139, (q31_t)0xc10bacc8, (q31_t)0x346e2504, (q31_t)0xc10df120, + (q31_t)0x3461c940, (q31_t)0xc11037e6, (q31_t)0x34556def, (q31_t)0xc1128119, + (q31_t)0x34491311, (q31_t)0xc114ccb9, (q31_t)0x343cb8a7, (q31_t)0xc1171ac6, + (q31_t)0x34305eb0, (q31_t)0xc1196b3f, (q31_t)0x3424052f, (q31_t)0xc11bbe26, + (q31_t)0x3417ac22, (q31_t)0xc11e1379, (q31_t)0x340b538b, (q31_t)0xc1206b39, + (q31_t)0x33fefb6a, (q31_t)0xc122c566, (q31_t)0x33f2a3bf, (q31_t)0xc12521ff, + (q31_t)0x33e64c8c, (q31_t)0xc1278104, (q31_t)0x33d9f5cf, (q31_t)0xc129e276, + (q31_t)0x33cd9f8b, (q31_t)0xc12c4653, (q31_t)0x33c149bf, (q31_t)0xc12eac9d, + (q31_t)0x33b4f46c, (q31_t)0xc1311553, (q31_t)0x33a89f92, (q31_t)0xc1338075, + (q31_t)0x339c4b32, (q31_t)0xc135ee02, (q31_t)0x338ff74d, (q31_t)0xc1385dfb, + (q31_t)0x3383a3e2, (q31_t)0xc13ad060, (q31_t)0x337750f2, (q31_t)0xc13d4530, + (q31_t)0x336afe7e, (q31_t)0xc13fbc6c, (q31_t)0x335eac86, (q31_t)0xc1423613, + (q31_t)0x33525b0b, (q31_t)0xc144b225, (q31_t)0x33460a0d, (q31_t)0xc14730a3, + (q31_t)0x3339b98d, (q31_t)0xc149b18b, (q31_t)0x332d698a, (q31_t)0xc14c34df, + (q31_t)0x33211a07, (q31_t)0xc14eba9d, (q31_t)0x3314cb02, (q31_t)0xc15142c6, + (q31_t)0x33087c7d, (q31_t)0xc153cd5a, (q31_t)0x32fc2e77, (q31_t)0xc1565a58, + (q31_t)0x32efe0f2, (q31_t)0xc158e9c1, (q31_t)0x32e393ef, (q31_t)0xc15b7b94, + (q31_t)0x32d7476c, (q31_t)0xc15e0fd1, (q31_t)0x32cafb6b, (q31_t)0xc160a678, + (q31_t)0x32beafed, (q31_t)0xc1633f8a, (q31_t)0x32b264f2, (q31_t)0xc165db05, + (q31_t)0x32a61a7a, (q31_t)0xc16878eb, (q31_t)0x3299d085, (q31_t)0xc16b193a, + (q31_t)0x328d8715, (q31_t)0xc16dbbf3, (q31_t)0x32813e2a, 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(q31_t)0x3acd6e81, (q31_t)0x3fc9e1c6, (q31_t)0x3ad9f4f8, (q31_t)0x3fcae5cd, + (q31_t)0x3ae67ba2, (q31_t)0x3fcbe75e, (q31_t)0x3af3027e, (q31_t)0x3fcce67a, + (q31_t)0x3aff898c, (q31_t)0x3fcde320, (q31_t)0x3b0c10cb, (q31_t)0x3fcedd50, + (q31_t)0x3b18983b, (q31_t)0x3fcfd50b, (q31_t)0x3b251fdc, (q31_t)0x3fd0ca4f, + (q31_t)0x3b31a7ac, (q31_t)0x3fd1bd1e, (q31_t)0x3b3e2fac, (q31_t)0x3fd2ad77, + (q31_t)0x3b4ab7db, (q31_t)0x3fd39b5a, (q31_t)0x3b574039, (q31_t)0x3fd486c7, + (q31_t)0x3b63c8c4, (q31_t)0x3fd56fbe, (q31_t)0x3b70517d, (q31_t)0x3fd6563f, + (q31_t)0x3b7cda63, (q31_t)0x3fd73a4a, (q31_t)0x3b896375, (q31_t)0x3fd81bdf, + (q31_t)0x3b95ecb4, (q31_t)0x3fd8fafe, (q31_t)0x3ba2761e, (q31_t)0x3fd9d7a7, + (q31_t)0x3baeffb3, (q31_t)0x3fdab1d9, (q31_t)0x3bbb8973, (q31_t)0x3fdb8996, + (q31_t)0x3bc8135c, (q31_t)0x3fdc5edc, (q31_t)0x3bd49d70, (q31_t)0x3fdd31ac, + (q31_t)0x3be127ac, (q31_t)0x3fde0205, (q31_t)0x3bedb212, (q31_t)0x3fdecfe8, + (q31_t)0x3bfa3c9f, (q31_t)0x3fdf9b55, (q31_t)0x3c06c754, (q31_t)0x3fe0644b, + (q31_t)0x3c135231, (q31_t)0x3fe12acb, (q31_t)0x3c1fdd34, (q31_t)0x3fe1eed5, + (q31_t)0x3c2c685d, (q31_t)0x3fe2b067, (q31_t)0x3c38f3ac, (q31_t)0x3fe36f84, + (q31_t)0x3c457f21, (q31_t)0x3fe42c2a, (q31_t)0x3c520aba, (q31_t)0x3fe4e659, + (q31_t)0x3c5e9678, (q31_t)0x3fe59e12, (q31_t)0x3c6b2259, (q31_t)0x3fe65354, + (q31_t)0x3c77ae5e, (q31_t)0x3fe7061f, (q31_t)0x3c843a85, (q31_t)0x3fe7b674, + (q31_t)0x3c90c6cf, (q31_t)0x3fe86452, (q31_t)0x3c9d533b, (q31_t)0x3fe90fb9, + (q31_t)0x3ca9dfc8, (q31_t)0x3fe9b8a9, (q31_t)0x3cb66c77, (q31_t)0x3fea5f23, + (q31_t)0x3cc2f945, (q31_t)0x3feb0326, (q31_t)0x3ccf8634, (q31_t)0x3feba4b2, + (q31_t)0x3cdc1342, (q31_t)0x3fec43c7, (q31_t)0x3ce8a06f, (q31_t)0x3fece065, + (q31_t)0x3cf52dbb, (q31_t)0x3fed7a8c, (q31_t)0x3d01bb24, (q31_t)0x3fee123d, + (q31_t)0x3d0e48ab, (q31_t)0x3feea776, (q31_t)0x3d1ad650, (q31_t)0x3fef3a39, + (q31_t)0x3d276410, (q31_t)0x3fefca84, (q31_t)0x3d33f1ed, (q31_t)0x3ff05858, + (q31_t)0x3d407fe6, (q31_t)0x3ff0e3b6, (q31_t)0x3d4d0df9, (q31_t)0x3ff16c9c, + (q31_t)0x3d599c28, (q31_t)0x3ff1f30b, (q31_t)0x3d662a70, (q31_t)0x3ff27703, + (q31_t)0x3d72b8d2, (q31_t)0x3ff2f884, (q31_t)0x3d7f474d, (q31_t)0x3ff3778e, + (q31_t)0x3d8bd5e1, (q31_t)0x3ff3f420, (q31_t)0x3d98648d, (q31_t)0x3ff46e3c, + (q31_t)0x3da4f351, (q31_t)0x3ff4e5e0, (q31_t)0x3db1822c, (q31_t)0x3ff55b0d, + (q31_t)0x3dbe111e, (q31_t)0x3ff5cdc3, (q31_t)0x3dcaa027, (q31_t)0x3ff63e01, + (q31_t)0x3dd72f45, (q31_t)0x3ff6abc8, (q31_t)0x3de3be78, (q31_t)0x3ff71718, + (q31_t)0x3df04dc0, (q31_t)0x3ff77ff1, (q31_t)0x3dfcdd1d, (q31_t)0x3ff7e652, + (q31_t)0x3e096c8d, (q31_t)0x3ff84a3c, (q31_t)0x3e15fc11, (q31_t)0x3ff8abae, + (q31_t)0x3e228ba7, (q31_t)0x3ff90aaa, (q31_t)0x3e2f1b50, (q31_t)0x3ff9672d, + (q31_t)0x3e3bab0b, (q31_t)0x3ff9c13a, (q31_t)0x3e483ad8, (q31_t)0x3ffa18cf, + (q31_t)0x3e54cab5, (q31_t)0x3ffa6dec, (q31_t)0x3e615aa3, (q31_t)0x3ffac092, + (q31_t)0x3e6deaa1, (q31_t)0x3ffb10c1, (q31_t)0x3e7a7aae, (q31_t)0x3ffb5e78, + (q31_t)0x3e870aca, (q31_t)0x3ffba9b8, (q31_t)0x3e939af5, (q31_t)0x3ffbf280, + (q31_t)0x3ea02b2e, (q31_t)0x3ffc38d1, (q31_t)0x3eacbb74, (q31_t)0x3ffc7caa, + (q31_t)0x3eb94bc8, (q31_t)0x3ffcbe0c, (q31_t)0x3ec5dc28, (q31_t)0x3ffcfcf6, + (q31_t)0x3ed26c94, (q31_t)0x3ffd3969, (q31_t)0x3edefd0c, (q31_t)0x3ffd7364, + (q31_t)0x3eeb8d8f, (q31_t)0x3ffdaae7, (q31_t)0x3ef81e1d, (q31_t)0x3ffddff3, + (q31_t)0x3f04aeb5, (q31_t)0x3ffe1288, (q31_t)0x3f113f56, (q31_t)0x3ffe42a4, + (q31_t)0x3f1dd001, (q31_t)0x3ffe704a, (q31_t)0x3f2a60b4, (q31_t)0x3ffe9b77, + (q31_t)0x3f36f170, (q31_t)0x3ffec42d, (q31_t)0x3f438234, (q31_t)0x3ffeea6c, + (q31_t)0x3f5012fe, (q31_t)0x3fff0e32, (q31_t)0x3f5ca3d0, (q31_t)0x3fff2f82, + (q31_t)0x3f6934a8, (q31_t)0x3fff4e59, (q31_t)0x3f75c585, (q31_t)0x3fff6ab9, + (q31_t)0x3f825668, (q31_t)0x3fff84a1, (q31_t)0x3f8ee750, (q31_t)0x3fff9c12, + (q31_t)0x3f9b783c, (q31_t)0x3fffb10b, (q31_t)0x3fa8092c, (q31_t)0x3fffc38c, + (q31_t)0x3fb49a1f, (q31_t)0x3fffd396, (q31_t)0x3fc12b16, (q31_t)0x3fffe128, + (q31_t)0x3fcdbc0f, (q31_t)0x3fffec43, (q31_t)0x3fda4d09, (q31_t)0x3ffff4e6, + (q31_t)0x3fe6de05, (q31_t)0x3ffffb11, (q31_t)0x3ff36f02, (q31_t)0x3ffffec4, +}; + + +/** + @par + Generation of realCoefBQ31 array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pBTable[i] * pow(2, 31)) + */ + +const q31_t realCoefBQ31[8192] = { + (q31_t)0x40000000, (q31_t)0x40000000, (q31_t)0x400c90fe, (q31_t)0x3ffffec4, + (q31_t)0x401921fb, (q31_t)0x3ffffb11, (q31_t)0x4025b2f7, (q31_t)0x3ffff4e6, + (q31_t)0x403243f1, (q31_t)0x3fffec43, (q31_t)0x403ed4ea, (q31_t)0x3fffe128, + (q31_t)0x404b65e1, (q31_t)0x3fffd396, (q31_t)0x4057f6d4, (q31_t)0x3fffc38c, + (q31_t)0x406487c4, (q31_t)0x3fffb10b, (q31_t)0x407118b0, (q31_t)0x3fff9c12, + (q31_t)0x407da998, (q31_t)0x3fff84a1, (q31_t)0x408a3a7b, (q31_t)0x3fff6ab9, + (q31_t)0x4096cb58, (q31_t)0x3fff4e59, (q31_t)0x40a35c30, (q31_t)0x3fff2f82, + (q31_t)0x40afed02, (q31_t)0x3fff0e32, (q31_t)0x40bc7dcc, (q31_t)0x3ffeea6c, + (q31_t)0x40c90e90, (q31_t)0x3ffec42d, (q31_t)0x40d59f4c, (q31_t)0x3ffe9b77, + (q31_t)0x40e22fff, (q31_t)0x3ffe704a, (q31_t)0x40eec0aa, (q31_t)0x3ffe42a4, + (q31_t)0x40fb514b, (q31_t)0x3ffe1288, (q31_t)0x4107e1e3, (q31_t)0x3ffddff3, + (q31_t)0x41147271, (q31_t)0x3ffdaae7, (q31_t)0x412102f4, (q31_t)0x3ffd7364, + (q31_t)0x412d936c, (q31_t)0x3ffd3969, (q31_t)0x413a23d8, (q31_t)0x3ffcfcf6, + (q31_t)0x4146b438, (q31_t)0x3ffcbe0c, (q31_t)0x4153448c, (q31_t)0x3ffc7caa, + (q31_t)0x415fd4d2, (q31_t)0x3ffc38d1, (q31_t)0x416c650b, (q31_t)0x3ffbf280, + (q31_t)0x4178f536, (q31_t)0x3ffba9b8, (q31_t)0x41858552, (q31_t)0x3ffb5e78, + (q31_t)0x4192155f, (q31_t)0x3ffb10c1, (q31_t)0x419ea55d, (q31_t)0x3ffac092, + (q31_t)0x41ab354b, (q31_t)0x3ffa6dec, (q31_t)0x41b7c528, (q31_t)0x3ffa18cf, + (q31_t)0x41c454f5, (q31_t)0x3ff9c13a, (q31_t)0x41d0e4b0, (q31_t)0x3ff9672d, + (q31_t)0x41dd7459, (q31_t)0x3ff90aaa, (q31_t)0x41ea03ef, (q31_t)0x3ff8abae, + (q31_t)0x41f69373, (q31_t)0x3ff84a3c, (q31_t)0x420322e3, (q31_t)0x3ff7e652, + (q31_t)0x420fb240, (q31_t)0x3ff77ff1, (q31_t)0x421c4188, (q31_t)0x3ff71718, + (q31_t)0x4228d0bb, (q31_t)0x3ff6abc8, (q31_t)0x42355fd9, (q31_t)0x3ff63e01, + (q31_t)0x4241eee2, (q31_t)0x3ff5cdc3, (q31_t)0x424e7dd4, (q31_t)0x3ff55b0d, + (q31_t)0x425b0caf, (q31_t)0x3ff4e5e0, (q31_t)0x42679b73, (q31_t)0x3ff46e3c, + (q31_t)0x42742a1f, (q31_t)0x3ff3f420, (q31_t)0x4280b8b3, (q31_t)0x3ff3778e, + (q31_t)0x428d472e, (q31_t)0x3ff2f884, (q31_t)0x4299d590, (q31_t)0x3ff27703, + (q31_t)0x42a663d8, (q31_t)0x3ff1f30b, (q31_t)0x42b2f207, (q31_t)0x3ff16c9c, + (q31_t)0x42bf801a, (q31_t)0x3ff0e3b6, (q31_t)0x42cc0e13, (q31_t)0x3ff05858, + (q31_t)0x42d89bf0, (q31_t)0x3fefca84, (q31_t)0x42e529b0, (q31_t)0x3fef3a39, + (q31_t)0x42f1b755, (q31_t)0x3feea776, (q31_t)0x42fe44dc, (q31_t)0x3fee123d, + (q31_t)0x430ad245, (q31_t)0x3fed7a8c, (q31_t)0x43175f91, (q31_t)0x3fece065, + (q31_t)0x4323ecbe, (q31_t)0x3fec43c7, (q31_t)0x433079cc, (q31_t)0x3feba4b2, + (q31_t)0x433d06bb, (q31_t)0x3feb0326, (q31_t)0x43499389, (q31_t)0x3fea5f23, + (q31_t)0x43562038, (q31_t)0x3fe9b8a9, (q31_t)0x4362acc5, (q31_t)0x3fe90fb9, + (q31_t)0x436f3931, (q31_t)0x3fe86452, (q31_t)0x437bc57b, (q31_t)0x3fe7b674, + (q31_t)0x438851a2, (q31_t)0x3fe7061f, (q31_t)0x4394dda7, (q31_t)0x3fe65354, + (q31_t)0x43a16988, (q31_t)0x3fe59e12, (q31_t)0x43adf546, (q31_t)0x3fe4e659, + (q31_t)0x43ba80df, (q31_t)0x3fe42c2a, (q31_t)0x43c70c54, (q31_t)0x3fe36f84, + (q31_t)0x43d397a3, (q31_t)0x3fe2b067, (q31_t)0x43e022cc, (q31_t)0x3fe1eed5, + (q31_t)0x43ecadcf, (q31_t)0x3fe12acb, (q31_t)0x43f938ac, (q31_t)0x3fe0644b, + (q31_t)0x4405c361, (q31_t)0x3fdf9b55, (q31_t)0x44124dee, (q31_t)0x3fdecfe8, + (q31_t)0x441ed854, (q31_t)0x3fde0205, (q31_t)0x442b6290, (q31_t)0x3fdd31ac, + (q31_t)0x4437eca4, (q31_t)0x3fdc5edc, (q31_t)0x4444768d, (q31_t)0x3fdb8996, + (q31_t)0x4451004d, (q31_t)0x3fdab1d9, (q31_t)0x445d89e2, (q31_t)0x3fd9d7a7, + (q31_t)0x446a134c, (q31_t)0x3fd8fafe, (q31_t)0x44769c8b, (q31_t)0x3fd81bdf, + (q31_t)0x4483259d, (q31_t)0x3fd73a4a, (q31_t)0x448fae83, (q31_t)0x3fd6563f, + (q31_t)0x449c373c, (q31_t)0x3fd56fbe, (q31_t)0x44a8bfc7, (q31_t)0x3fd486c7, + (q31_t)0x44b54825, (q31_t)0x3fd39b5a, (q31_t)0x44c1d054, (q31_t)0x3fd2ad77, + (q31_t)0x44ce5854, (q31_t)0x3fd1bd1e, (q31_t)0x44dae024, (q31_t)0x3fd0ca4f, + (q31_t)0x44e767c5, (q31_t)0x3fcfd50b, (q31_t)0x44f3ef35, (q31_t)0x3fcedd50, + (q31_t)0x45007674, (q31_t)0x3fcde320, (q31_t)0x450cfd82, (q31_t)0x3fcce67a, + (q31_t)0x4519845e, (q31_t)0x3fcbe75e, (q31_t)0x45260b08, (q31_t)0x3fcae5cd, + (q31_t)0x4532917f, (q31_t)0x3fc9e1c6, (q31_t)0x453f17c3, (q31_t)0x3fc8db4a, + (q31_t)0x454b9dd3, (q31_t)0x3fc7d258, (q31_t)0x455823ae, (q31_t)0x3fc6c6f0, + (q31_t)0x4564a955, (q31_t)0x3fc5b913, (q31_t)0x45712ec7, (q31_t)0x3fc4a8c1, + (q31_t)0x457db403, (q31_t)0x3fc395f9, (q31_t)0x458a3908, (q31_t)0x3fc280bc, + (q31_t)0x4596bdd7, (q31_t)0x3fc1690a, (q31_t)0x45a3426f, (q31_t)0x3fc04ee3, + (q31_t)0x45afc6d0, (q31_t)0x3fbf3246, (q31_t)0x45bc4af8, (q31_t)0x3fbe1334, + (q31_t)0x45c8cee7, (q31_t)0x3fbcf1ad, (q31_t)0x45d5529e, (q31_t)0x3fbbcdb1, + (q31_t)0x45e1d61b, (q31_t)0x3fbaa740, (q31_t)0x45ee595d, (q31_t)0x3fb97e5a, + (q31_t)0x45fadc66, (q31_t)0x3fb852ff, (q31_t)0x46075f33, (q31_t)0x3fb7252f, + (q31_t)0x4613e1c5, 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(q31_t)0x4596bdd7, (q31_t)0xc03e96f6, (q31_t)0x458a3908, (q31_t)0xc03d7f44, + (q31_t)0x457db403, (q31_t)0xc03c6a07, (q31_t)0x45712ec7, (q31_t)0xc03b573f, + (q31_t)0x4564a955, (q31_t)0xc03a46ed, (q31_t)0x455823ae, (q31_t)0xc0393910, + (q31_t)0x454b9dd3, (q31_t)0xc0382da8, (q31_t)0x453f17c3, (q31_t)0xc03724b6, + (q31_t)0x4532917f, (q31_t)0xc0361e3a, (q31_t)0x45260b08, (q31_t)0xc0351a33, + (q31_t)0x4519845e, (q31_t)0xc03418a2, (q31_t)0x450cfd82, (q31_t)0xc0331986, + (q31_t)0x45007674, (q31_t)0xc0321ce0, (q31_t)0x44f3ef35, (q31_t)0xc03122b0, + (q31_t)0x44e767c5, (q31_t)0xc0302af5, (q31_t)0x44dae024, (q31_t)0xc02f35b1, + (q31_t)0x44ce5854, (q31_t)0xc02e42e2, (q31_t)0x44c1d054, (q31_t)0xc02d5289, + (q31_t)0x44b54825, (q31_t)0xc02c64a6, (q31_t)0x44a8bfc7, (q31_t)0xc02b7939, + (q31_t)0x449c373c, (q31_t)0xc02a9042, (q31_t)0x448fae83, (q31_t)0xc029a9c1, + (q31_t)0x4483259d, (q31_t)0xc028c5b6, (q31_t)0x44769c8b, (q31_t)0xc027e421, + (q31_t)0x446a134c, (q31_t)0xc0270502, (q31_t)0x445d89e2, (q31_t)0xc0262859, + (q31_t)0x4451004d, (q31_t)0xc0254e27, (q31_t)0x4444768d, (q31_t)0xc024766a, + (q31_t)0x4437eca4, (q31_t)0xc023a124, (q31_t)0x442b6290, (q31_t)0xc022ce54, + (q31_t)0x441ed854, (q31_t)0xc021fdfb, (q31_t)0x44124dee, (q31_t)0xc0213018, + (q31_t)0x4405c361, (q31_t)0xc02064ab, (q31_t)0x43f938ac, (q31_t)0xc01f9bb5, + (q31_t)0x43ecadcf, (q31_t)0xc01ed535, (q31_t)0x43e022cc, (q31_t)0xc01e112b, + (q31_t)0x43d397a3, (q31_t)0xc01d4f99, (q31_t)0x43c70c54, (q31_t)0xc01c907c, + (q31_t)0x43ba80df, (q31_t)0xc01bd3d6, (q31_t)0x43adf546, (q31_t)0xc01b19a7, + (q31_t)0x43a16988, (q31_t)0xc01a61ee, (q31_t)0x4394dda7, (q31_t)0xc019acac, + (q31_t)0x438851a2, (q31_t)0xc018f9e1, (q31_t)0x437bc57b, (q31_t)0xc018498c, + (q31_t)0x436f3931, (q31_t)0xc0179bae, (q31_t)0x4362acc5, (q31_t)0xc016f047, + (q31_t)0x43562038, (q31_t)0xc0164757, (q31_t)0x43499389, (q31_t)0xc015a0dd, + (q31_t)0x433d06bb, (q31_t)0xc014fcda, (q31_t)0x433079cc, (q31_t)0xc0145b4e, + (q31_t)0x4323ecbe, (q31_t)0xc013bc39, (q31_t)0x43175f91, (q31_t)0xc0131f9b, + (q31_t)0x430ad245, (q31_t)0xc0128574, (q31_t)0x42fe44dc, (q31_t)0xc011edc3, + (q31_t)0x42f1b755, (q31_t)0xc011588a, (q31_t)0x42e529b0, (q31_t)0xc010c5c7, + (q31_t)0x42d89bf0, (q31_t)0xc010357c, (q31_t)0x42cc0e13, (q31_t)0xc00fa7a8, + (q31_t)0x42bf801a, (q31_t)0xc00f1c4a, (q31_t)0x42b2f207, (q31_t)0xc00e9364, + (q31_t)0x42a663d8, (q31_t)0xc00e0cf5, (q31_t)0x4299d590, (q31_t)0xc00d88fd, + (q31_t)0x428d472e, (q31_t)0xc00d077c, (q31_t)0x4280b8b3, (q31_t)0xc00c8872, + (q31_t)0x42742a1f, (q31_t)0xc00c0be0, (q31_t)0x42679b73, (q31_t)0xc00b91c4, + (q31_t)0x425b0caf, (q31_t)0xc00b1a20, (q31_t)0x424e7dd4, (q31_t)0xc00aa4f3, + (q31_t)0x4241eee2, (q31_t)0xc00a323d, (q31_t)0x42355fd9, (q31_t)0xc009c1ff, + (q31_t)0x4228d0bb, (q31_t)0xc0095438, (q31_t)0x421c4188, (q31_t)0xc008e8e8, + (q31_t)0x420fb240, (q31_t)0xc008800f, (q31_t)0x420322e3, (q31_t)0xc00819ae, + (q31_t)0x41f69373, (q31_t)0xc007b5c4, (q31_t)0x41ea03ef, (q31_t)0xc0075452, + (q31_t)0x41dd7459, (q31_t)0xc006f556, (q31_t)0x41d0e4b0, (q31_t)0xc00698d3, + (q31_t)0x41c454f5, (q31_t)0xc0063ec6, (q31_t)0x41b7c528, (q31_t)0xc005e731, + (q31_t)0x41ab354b, (q31_t)0xc0059214, (q31_t)0x419ea55d, (q31_t)0xc0053f6e, + (q31_t)0x4192155f, (q31_t)0xc004ef3f, (q31_t)0x41858552, (q31_t)0xc004a188, + (q31_t)0x4178f536, (q31_t)0xc0045648, (q31_t)0x416c650b, (q31_t)0xc0040d80, + (q31_t)0x415fd4d2, (q31_t)0xc003c72f, (q31_t)0x4153448c, (q31_t)0xc0038356, + (q31_t)0x4146b438, (q31_t)0xc00341f4, (q31_t)0x413a23d8, (q31_t)0xc003030a, + (q31_t)0x412d936c, (q31_t)0xc002c697, (q31_t)0x412102f4, (q31_t)0xc0028c9c, + (q31_t)0x41147271, (q31_t)0xc0025519, (q31_t)0x4107e1e3, (q31_t)0xc002200d, + (q31_t)0x40fb514b, (q31_t)0xc001ed78, (q31_t)0x40eec0aa, (q31_t)0xc001bd5c, + (q31_t)0x40e22fff, (q31_t)0xc0018fb6, (q31_t)0x40d59f4c, (q31_t)0xc0016489, + (q31_t)0x40c90e90, (q31_t)0xc0013bd3, (q31_t)0x40bc7dcc, (q31_t)0xc0011594, + (q31_t)0x40afed02, (q31_t)0xc000f1ce, (q31_t)0x40a35c30, (q31_t)0xc000d07e, + (q31_t)0x4096cb58, (q31_t)0xc000b1a7, (q31_t)0x408a3a7b, (q31_t)0xc0009547, + (q31_t)0x407da998, (q31_t)0xc0007b5f, (q31_t)0x407118b0, (q31_t)0xc00063ee, + (q31_t)0x406487c4, (q31_t)0xc0004ef5, (q31_t)0x4057f6d4, (q31_t)0xc0003c74, + (q31_t)0x404b65e1, (q31_t)0xc0002c6a, (q31_t)0x403ed4ea, (q31_t)0xc0001ed8, + (q31_t)0x403243f1, (q31_t)0xc00013bd, (q31_t)0x4025b2f7, (q31_t)0xc0000b1a, + (q31_t)0x401921fb, (q31_t)0xc00004ef, (q31_t)0x400c90fe, (q31_t)0xc000013c, +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) +/** + @par + Generation fixed-point realCoefAQ15 array in Q15 format: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pATable[i] * pow(2, 15)) + */ +const q15_t __ALIGNED(4) realCoefAQ15[8192] = { + (q15_t)0x4000, (q15_t)0xc000, (q15_t)0x3ff3, (q15_t)0xc000, (q15_t)0x3fe7, (q15_t)0xc000, (q15_t)0x3fda, (q15_t)0xc000, + (q15_t)0x3fce, (q15_t)0xc000, (q15_t)0x3fc1, (q15_t)0xc000, (q15_t)0x3fb5, (q15_t)0xc000, (q15_t)0x3fa8, (q15_t)0xc000, + (q15_t)0x3f9b, (q15_t)0xc000, (q15_t)0x3f8f, (q15_t)0xc000, (q15_t)0x3f82, (q15_t)0xc000, (q15_t)0x3f76, (q15_t)0xc001, + (q15_t)0x3f69, (q15_t)0xc001, (q15_t)0x3f5d, (q15_t)0xc001, (q15_t)0x3f50, (q15_t)0xc001, (q15_t)0x3f44, (q15_t)0xc001, + (q15_t)0x3f37, (q15_t)0xc001, (q15_t)0x3f2a, (q15_t)0xc001, (q15_t)0x3f1e, (q15_t)0xc002, (q15_t)0x3f11, (q15_t)0xc002, + (q15_t)0x3f05, (q15_t)0xc002, (q15_t)0x3ef8, (q15_t)0xc002, (q15_t)0x3eec, (q15_t)0xc002, (q15_t)0x3edf, (q15_t)0xc003, + (q15_t)0x3ed2, (q15_t)0xc003, (q15_t)0x3ec6, (q15_t)0xc003, (q15_t)0x3eb9, (q15_t)0xc003, (q15_t)0x3ead, (q15_t)0xc004, + (q15_t)0x3ea0, (q15_t)0xc004, (q15_t)0x3e94, (q15_t)0xc004, (q15_t)0x3e87, (q15_t)0xc004, (q15_t)0x3e7a, (q15_t)0xc005, + (q15_t)0x3e6e, (q15_t)0xc005, (q15_t)0x3e61, (q15_t)0xc005, (q15_t)0x3e55, (q15_t)0xc006, (q15_t)0x3e48, (q15_t)0xc006, + (q15_t)0x3e3c, (q15_t)0xc006, (q15_t)0x3e2f, (q15_t)0xc007, (q15_t)0x3e23, (q15_t)0xc007, (q15_t)0x3e16, (q15_t)0xc007, + (q15_t)0x3e09, (q15_t)0xc008, (q15_t)0x3dfd, (q15_t)0xc008, (q15_t)0x3df0, (q15_t)0xc009, (q15_t)0x3de4, (q15_t)0xc009, + (q15_t)0x3dd7, (q15_t)0xc009, (q15_t)0x3dcb, (q15_t)0xc00a, (q15_t)0x3dbe, (q15_t)0xc00a, (q15_t)0x3db2, (q15_t)0xc00b, + (q15_t)0x3da5, (q15_t)0xc00b, (q15_t)0x3d98, (q15_t)0xc00c, (q15_t)0x3d8c, (q15_t)0xc00c, (q15_t)0x3d7f, (q15_t)0xc00d, + (q15_t)0x3d73, (q15_t)0xc00d, (q15_t)0x3d66, (q15_t)0xc00e, (q15_t)0x3d5a, (q15_t)0xc00e, (q15_t)0x3d4d, (q15_t)0xc00f, + (q15_t)0x3d40, (q15_t)0xc00f, (q15_t)0x3d34, (q15_t)0xc010, (q15_t)0x3d27, (q15_t)0xc010, (q15_t)0x3d1b, (q15_t)0xc011, + (q15_t)0x3d0e, (q15_t)0xc011, (q15_t)0x3d02, (q15_t)0xc012, (q15_t)0x3cf5, (q15_t)0xc013, (q15_t)0x3ce9, (q15_t)0xc013, + (q15_t)0x3cdc, (q15_t)0xc014, (q15_t)0x3cd0, (q15_t)0xc014, (q15_t)0x3cc3, (q15_t)0xc015, (q15_t)0x3cb6, (q15_t)0xc016, + (q15_t)0x3caa, (q15_t)0xc016, (q15_t)0x3c9d, (q15_t)0xc017, (q15_t)0x3c91, (q15_t)0xc018, (q15_t)0x3c84, (q15_t)0xc018, + (q15_t)0x3c78, (q15_t)0xc019, (q15_t)0x3c6b, (q15_t)0xc01a, (q15_t)0x3c5f, (q15_t)0xc01a, (q15_t)0x3c52, (q15_t)0xc01b, + (q15_t)0x3c45, (q15_t)0xc01c, (q15_t)0x3c39, (q15_t)0xc01d, (q15_t)0x3c2c, (q15_t)0xc01d, (q15_t)0x3c20, (q15_t)0xc01e, + (q15_t)0x3c13, (q15_t)0xc01f, (q15_t)0x3c07, (q15_t)0xc020, (q15_t)0x3bfa, (q15_t)0xc020, (q15_t)0x3bee, (q15_t)0xc021, + (q15_t)0x3be1, (q15_t)0xc022, (q15_t)0x3bd5, (q15_t)0xc023, (q15_t)0x3bc8, (q15_t)0xc024, (q15_t)0x3bbc, (q15_t)0xc024, + (q15_t)0x3baf, (q15_t)0xc025, (q15_t)0x3ba2, (q15_t)0xc026, (q15_t)0x3b96, (q15_t)0xc027, (q15_t)0x3b89, (q15_t)0xc028, + (q15_t)0x3b7d, (q15_t)0xc029, (q15_t)0x3b70, (q15_t)0xc02a, (q15_t)0x3b64, (q15_t)0xc02b, (q15_t)0x3b57, (q15_t)0xc02b, + (q15_t)0x3b4b, (q15_t)0xc02c, (q15_t)0x3b3e, (q15_t)0xc02d, (q15_t)0x3b32, (q15_t)0xc02e, (q15_t)0x3b25, (q15_t)0xc02f, + (q15_t)0x3b19, (q15_t)0xc030, (q15_t)0x3b0c, (q15_t)0xc031, (q15_t)0x3b00, (q15_t)0xc032, (q15_t)0x3af3, (q15_t)0xc033, + (q15_t)0x3ae6, (q15_t)0xc034, (q15_t)0x3ada, (q15_t)0xc035, (q15_t)0x3acd, (q15_t)0xc036, (q15_t)0x3ac1, (q15_t)0xc037, + (q15_t)0x3ab4, (q15_t)0xc038, (q15_t)0x3aa8, (q15_t)0xc039, (q15_t)0x3a9b, (q15_t)0xc03a, (q15_t)0x3a8f, (q15_t)0xc03b, + (q15_t)0x3a82, (q15_t)0xc03c, (q15_t)0x3a76, (q15_t)0xc03d, (q15_t)0x3a69, (q15_t)0xc03f, (q15_t)0x3a5d, (q15_t)0xc040, + (q15_t)0x3a50, (q15_t)0xc041, (q15_t)0x3a44, (q15_t)0xc042, (q15_t)0x3a37, (q15_t)0xc043, (q15_t)0x3a2b, (q15_t)0xc044, + (q15_t)0x3a1e, (q15_t)0xc045, (q15_t)0x3a12, (q15_t)0xc047, (q15_t)0x3a05, (q15_t)0xc048, (q15_t)0x39f9, (q15_t)0xc049, + (q15_t)0x39ec, (q15_t)0xc04a, (q15_t)0x39e0, (q15_t)0xc04b, (q15_t)0x39d3, (q15_t)0xc04c, (q15_t)0x39c7, (q15_t)0xc04e, + (q15_t)0x39ba, (q15_t)0xc04f, (q15_t)0x39ae, (q15_t)0xc050, (q15_t)0x39a1, (q15_t)0xc051, (q15_t)0x3995, (q15_t)0xc053, + (q15_t)0x3988, (q15_t)0xc054, (q15_t)0x397c, (q15_t)0xc055, (q15_t)0x396f, (q15_t)0xc056, (q15_t)0x3963, (q15_t)0xc058, + (q15_t)0x3956, (q15_t)0xc059, (q15_t)0x394a, (q15_t)0xc05a, (q15_t)0x393d, (q15_t)0xc05c, (q15_t)0x3931, (q15_t)0xc05d, + (q15_t)0x3924, (q15_t)0xc05e, (q15_t)0x3918, (q15_t)0xc060, (q15_t)0x390b, (q15_t)0xc061, (q15_t)0x38ff, (q15_t)0xc062, + (q15_t)0x38f2, (q15_t)0xc064, (q15_t)0x38e6, (q15_t)0xc065, (q15_t)0x38d9, (q15_t)0xc067, (q15_t)0x38cd, (q15_t)0xc068, + (q15_t)0x38c0, (q15_t)0xc069, (q15_t)0x38b4, (q15_t)0xc06b, (q15_t)0x38a7, (q15_t)0xc06c, (q15_t)0x389b, (q15_t)0xc06e, + (q15_t)0x388e, (q15_t)0xc06f, (q15_t)0x3882, (q15_t)0xc071, (q15_t)0x3875, (q15_t)0xc072, (q15_t)0x3869, (q15_t)0xc074, + (q15_t)0x385c, (q15_t)0xc075, (q15_t)0x3850, (q15_t)0xc077, (q15_t)0x3843, (q15_t)0xc078, (q15_t)0x3837, (q15_t)0xc07a, + (q15_t)0x382a, (q15_t)0xc07b, (q15_t)0x381e, (q15_t)0xc07d, (q15_t)0x3811, (q15_t)0xc07e, (q15_t)0x3805, (q15_t)0xc080, + (q15_t)0x37f9, (q15_t)0xc081, (q15_t)0x37ec, (q15_t)0xc083, (q15_t)0x37e0, (q15_t)0xc085, (q15_t)0x37d3, (q15_t)0xc086, + (q15_t)0x37c7, (q15_t)0xc088, (q15_t)0x37ba, (q15_t)0xc089, (q15_t)0x37ae, (q15_t)0xc08b, (q15_t)0x37a1, (q15_t)0xc08d, + (q15_t)0x3795, (q15_t)0xc08e, (q15_t)0x3788, (q15_t)0xc090, (q15_t)0x377c, (q15_t)0xc092, (q15_t)0x376f, (q15_t)0xc093, + (q15_t)0x3763, (q15_t)0xc095, (q15_t)0x3757, (q15_t)0xc097, (q15_t)0x374a, (q15_t)0xc098, (q15_t)0x373e, (q15_t)0xc09a, + (q15_t)0x3731, (q15_t)0xc09c, (q15_t)0x3725, (q15_t)0xc09e, (q15_t)0x3718, (q15_t)0xc09f, (q15_t)0x370c, (q15_t)0xc0a1, + (q15_t)0x36ff, (q15_t)0xc0a3, (q15_t)0x36f3, (q15_t)0xc0a5, (q15_t)0x36e7, (q15_t)0xc0a6, (q15_t)0x36da, (q15_t)0xc0a8, + (q15_t)0x36ce, (q15_t)0xc0aa, (q15_t)0x36c1, (q15_t)0xc0ac, (q15_t)0x36b5, (q15_t)0xc0ae, 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(q15_t)0x3fc6, (q15_t)0x3aa8, (q15_t)0x3fc7, + (q15_t)0x3ab4, (q15_t)0x3fc8, (q15_t)0x3ac1, (q15_t)0x3fc9, (q15_t)0x3acd, (q15_t)0x3fca, (q15_t)0x3ada, (q15_t)0x3fcb, + (q15_t)0x3ae6, (q15_t)0x3fcc, (q15_t)0x3af3, (q15_t)0x3fcd, (q15_t)0x3b00, (q15_t)0x3fce, (q15_t)0x3b0c, (q15_t)0x3fcf, + (q15_t)0x3b19, (q15_t)0x3fd0, (q15_t)0x3b25, (q15_t)0x3fd1, (q15_t)0x3b32, (q15_t)0x3fd2, (q15_t)0x3b3e, (q15_t)0x3fd3, + (q15_t)0x3b4b, (q15_t)0x3fd4, (q15_t)0x3b57, (q15_t)0x3fd5, (q15_t)0x3b64, (q15_t)0x3fd5, (q15_t)0x3b70, (q15_t)0x3fd6, + (q15_t)0x3b7d, (q15_t)0x3fd7, (q15_t)0x3b89, (q15_t)0x3fd8, (q15_t)0x3b96, (q15_t)0x3fd9, (q15_t)0x3ba2, (q15_t)0x3fda, + (q15_t)0x3baf, (q15_t)0x3fdb, (q15_t)0x3bbc, (q15_t)0x3fdc, (q15_t)0x3bc8, (q15_t)0x3fdc, (q15_t)0x3bd5, (q15_t)0x3fdd, + (q15_t)0x3be1, (q15_t)0x3fde, (q15_t)0x3bee, (q15_t)0x3fdf, (q15_t)0x3bfa, (q15_t)0x3fe0, (q15_t)0x3c07, (q15_t)0x3fe0, + (q15_t)0x3c13, (q15_t)0x3fe1, (q15_t)0x3c20, (q15_t)0x3fe2, (q15_t)0x3c2c, (q15_t)0x3fe3, (q15_t)0x3c39, (q15_t)0x3fe3, + (q15_t)0x3c45, (q15_t)0x3fe4, (q15_t)0x3c52, (q15_t)0x3fe5, (q15_t)0x3c5f, (q15_t)0x3fe6, (q15_t)0x3c6b, (q15_t)0x3fe6, + (q15_t)0x3c78, (q15_t)0x3fe7, (q15_t)0x3c84, (q15_t)0x3fe8, (q15_t)0x3c91, (q15_t)0x3fe8, (q15_t)0x3c9d, (q15_t)0x3fe9, + (q15_t)0x3caa, (q15_t)0x3fea, (q15_t)0x3cb6, (q15_t)0x3fea, (q15_t)0x3cc3, (q15_t)0x3feb, (q15_t)0x3cd0, (q15_t)0x3fec, + (q15_t)0x3cdc, (q15_t)0x3fec, (q15_t)0x3ce9, (q15_t)0x3fed, (q15_t)0x3cf5, (q15_t)0x3fed, (q15_t)0x3d02, (q15_t)0x3fee, + (q15_t)0x3d0e, (q15_t)0x3fef, (q15_t)0x3d1b, (q15_t)0x3fef, (q15_t)0x3d27, (q15_t)0x3ff0, (q15_t)0x3d34, (q15_t)0x3ff0, + (q15_t)0x3d40, (q15_t)0x3ff1, (q15_t)0x3d4d, (q15_t)0x3ff1, (q15_t)0x3d5a, (q15_t)0x3ff2, (q15_t)0x3d66, (q15_t)0x3ff2, + (q15_t)0x3d73, (q15_t)0x3ff3, (q15_t)0x3d7f, (q15_t)0x3ff3, (q15_t)0x3d8c, (q15_t)0x3ff4, (q15_t)0x3d98, (q15_t)0x3ff4, + (q15_t)0x3da5, (q15_t)0x3ff5, (q15_t)0x3db2, (q15_t)0x3ff5, (q15_t)0x3dbe, (q15_t)0x3ff6, (q15_t)0x3dcb, (q15_t)0x3ff6, + (q15_t)0x3dd7, (q15_t)0x3ff7, (q15_t)0x3de4, (q15_t)0x3ff7, (q15_t)0x3df0, (q15_t)0x3ff7, (q15_t)0x3dfd, (q15_t)0x3ff8, + (q15_t)0x3e09, (q15_t)0x3ff8, (q15_t)0x3e16, (q15_t)0x3ff9, (q15_t)0x3e23, (q15_t)0x3ff9, (q15_t)0x3e2f, (q15_t)0x3ff9, + (q15_t)0x3e3c, (q15_t)0x3ffa, (q15_t)0x3e48, (q15_t)0x3ffa, (q15_t)0x3e55, (q15_t)0x3ffa, (q15_t)0x3e61, (q15_t)0x3ffb, + (q15_t)0x3e6e, (q15_t)0x3ffb, (q15_t)0x3e7a, (q15_t)0x3ffb, (q15_t)0x3e87, (q15_t)0x3ffc, (q15_t)0x3e94, (q15_t)0x3ffc, + (q15_t)0x3ea0, (q15_t)0x3ffc, (q15_t)0x3ead, (q15_t)0x3ffc, (q15_t)0x3eb9, (q15_t)0x3ffd, (q15_t)0x3ec6, (q15_t)0x3ffd, + (q15_t)0x3ed2, (q15_t)0x3ffd, (q15_t)0x3edf, (q15_t)0x3ffd, (q15_t)0x3eec, (q15_t)0x3ffe, (q15_t)0x3ef8, (q15_t)0x3ffe, + (q15_t)0x3f05, (q15_t)0x3ffe, (q15_t)0x3f11, (q15_t)0x3ffe, (q15_t)0x3f1e, (q15_t)0x3ffe, (q15_t)0x3f2a, (q15_t)0x3fff, + (q15_t)0x3f37, (q15_t)0x3fff, (q15_t)0x3f44, (q15_t)0x3fff, (q15_t)0x3f50, (q15_t)0x3fff, (q15_t)0x3f5d, (q15_t)0x3fff, + (q15_t)0x3f69, (q15_t)0x3fff, (q15_t)0x3f76, (q15_t)0x3fff, (q15_t)0x3f82, (q15_t)0x4000, (q15_t)0x3f8f, (q15_t)0x4000, + (q15_t)0x3f9b, (q15_t)0x4000, (q15_t)0x3fa8, (q15_t)0x4000, (q15_t)0x3fb5, (q15_t)0x4000, (q15_t)0x3fc1, (q15_t)0x4000, + (q15_t)0x3fce, (q15_t)0x4000, (q15_t)0x3fda, (q15_t)0x4000, (q15_t)0x3fe7, (q15_t)0x4000, (q15_t)0x3ff3, (q15_t)0x4000, +}; + +/** + @par + Generation of real_CoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pBTable[i] * pow(2, 15)) +*/ +const q15_t __ALIGNED(4) realCoefBQ15[8192] = { + (q15_t)0x4000, (q15_t)0x4000, (q15_t)0x400d, (q15_t)0x4000, (q15_t)0x4019, (q15_t)0x4000, (q15_t)0x4026, (q15_t)0x4000, + (q15_t)0x4032, (q15_t)0x4000, (q15_t)0x403f, (q15_t)0x4000, (q15_t)0x404b, (q15_t)0x4000, (q15_t)0x4058, (q15_t)0x4000, + (q15_t)0x4065, (q15_t)0x4000, (q15_t)0x4071, (q15_t)0x4000, (q15_t)0x407e, (q15_t)0x4000, (q15_t)0x408a, (q15_t)0x3fff, + (q15_t)0x4097, (q15_t)0x3fff, (q15_t)0x40a3, (q15_t)0x3fff, (q15_t)0x40b0, (q15_t)0x3fff, (q15_t)0x40bc, (q15_t)0x3fff, + (q15_t)0x40c9, (q15_t)0x3fff, (q15_t)0x40d6, (q15_t)0x3fff, (q15_t)0x40e2, (q15_t)0x3ffe, (q15_t)0x40ef, (q15_t)0x3ffe, + (q15_t)0x40fb, (q15_t)0x3ffe, (q15_t)0x4108, (q15_t)0x3ffe, (q15_t)0x4114, (q15_t)0x3ffe, (q15_t)0x4121, (q15_t)0x3ffd, + (q15_t)0x412e, (q15_t)0x3ffd, (q15_t)0x413a, (q15_t)0x3ffd, (q15_t)0x4147, (q15_t)0x3ffd, (q15_t)0x4153, (q15_t)0x3ffc, + (q15_t)0x4160, (q15_t)0x3ffc, (q15_t)0x416c, (q15_t)0x3ffc, (q15_t)0x4179, (q15_t)0x3ffc, (q15_t)0x4186, (q15_t)0x3ffb, + (q15_t)0x4192, (q15_t)0x3ffb, (q15_t)0x419f, (q15_t)0x3ffb, (q15_t)0x41ab, (q15_t)0x3ffa, (q15_t)0x41b8, (q15_t)0x3ffa, + (q15_t)0x41c4, (q15_t)0x3ffa, (q15_t)0x41d1, (q15_t)0x3ff9, (q15_t)0x41dd, (q15_t)0x3ff9, (q15_t)0x41ea, (q15_t)0x3ff9, + (q15_t)0x41f7, (q15_t)0x3ff8, (q15_t)0x4203, (q15_t)0x3ff8, (q15_t)0x4210, (q15_t)0x3ff7, (q15_t)0x421c, (q15_t)0x3ff7, + (q15_t)0x4229, (q15_t)0x3ff7, (q15_t)0x4235, (q15_t)0x3ff6, (q15_t)0x4242, (q15_t)0x3ff6, (q15_t)0x424e, (q15_t)0x3ff5, + (q15_t)0x425b, (q15_t)0x3ff5, (q15_t)0x4268, (q15_t)0x3ff4, (q15_t)0x4274, (q15_t)0x3ff4, (q15_t)0x4281, (q15_t)0x3ff3, + (q15_t)0x428d, (q15_t)0x3ff3, (q15_t)0x429a, (q15_t)0x3ff2, (q15_t)0x42a6, (q15_t)0x3ff2, (q15_t)0x42b3, (q15_t)0x3ff1, + (q15_t)0x42c0, (q15_t)0x3ff1, (q15_t)0x42cc, (q15_t)0x3ff0, (q15_t)0x42d9, (q15_t)0x3ff0, (q15_t)0x42e5, (q15_t)0x3fef, + (q15_t)0x42f2, (q15_t)0x3fef, (q15_t)0x42fe, (q15_t)0x3fee, (q15_t)0x430b, (q15_t)0x3fed, (q15_t)0x4317, (q15_t)0x3fed, + (q15_t)0x4324, (q15_t)0x3fec, (q15_t)0x4330, (q15_t)0x3fec, (q15_t)0x433d, (q15_t)0x3feb, (q15_t)0x434a, (q15_t)0x3fea, + (q15_t)0x4356, (q15_t)0x3fea, (q15_t)0x4363, (q15_t)0x3fe9, (q15_t)0x436f, (q15_t)0x3fe8, (q15_t)0x437c, (q15_t)0x3fe8, + (q15_t)0x4388, (q15_t)0x3fe7, (q15_t)0x4395, (q15_t)0x3fe6, (q15_t)0x43a1, (q15_t)0x3fe6, (q15_t)0x43ae, (q15_t)0x3fe5, + (q15_t)0x43bb, (q15_t)0x3fe4, (q15_t)0x43c7, (q15_t)0x3fe3, (q15_t)0x43d4, (q15_t)0x3fe3, (q15_t)0x43e0, (q15_t)0x3fe2, + (q15_t)0x43ed, (q15_t)0x3fe1, (q15_t)0x43f9, (q15_t)0x3fe0, (q15_t)0x4406, (q15_t)0x3fe0, (q15_t)0x4412, (q15_t)0x3fdf, + (q15_t)0x441f, (q15_t)0x3fde, (q15_t)0x442b, (q15_t)0x3fdd, (q15_t)0x4438, (q15_t)0x3fdc, (q15_t)0x4444, (q15_t)0x3fdc, + (q15_t)0x4451, (q15_t)0x3fdb, (q15_t)0x445e, (q15_t)0x3fda, (q15_t)0x446a, (q15_t)0x3fd9, (q15_t)0x4477, (q15_t)0x3fd8, + (q15_t)0x4483, (q15_t)0x3fd7, (q15_t)0x4490, (q15_t)0x3fd6, (q15_t)0x449c, (q15_t)0x3fd5, (q15_t)0x44a9, (q15_t)0x3fd5, + (q15_t)0x44b5, (q15_t)0x3fd4, (q15_t)0x44c2, (q15_t)0x3fd3, (q15_t)0x44ce, (q15_t)0x3fd2, (q15_t)0x44db, (q15_t)0x3fd1, + (q15_t)0x44e7, (q15_t)0x3fd0, (q15_t)0x44f4, (q15_t)0x3fcf, (q15_t)0x4500, (q15_t)0x3fce, (q15_t)0x450d, (q15_t)0x3fcd, + (q15_t)0x451a, (q15_t)0x3fcc, (q15_t)0x4526, (q15_t)0x3fcb, (q15_t)0x4533, (q15_t)0x3fca, (q15_t)0x453f, (q15_t)0x3fc9, + (q15_t)0x454c, (q15_t)0x3fc8, (q15_t)0x4558, (q15_t)0x3fc7, (q15_t)0x4565, (q15_t)0x3fc6, (q15_t)0x4571, (q15_t)0x3fc5, + (q15_t)0x457e, (q15_t)0x3fc4, (q15_t)0x458a, (q15_t)0x3fc3, (q15_t)0x4597, (q15_t)0x3fc1, (q15_t)0x45a3, (q15_t)0x3fc0, + (q15_t)0x45b0, (q15_t)0x3fbf, (q15_t)0x45bc, (q15_t)0x3fbe, (q15_t)0x45c9, (q15_t)0x3fbd, (q15_t)0x45d5, (q15_t)0x3fbc, + (q15_t)0x45e2, (q15_t)0x3fbb, (q15_t)0x45ee, (q15_t)0x3fb9, (q15_t)0x45fb, (q15_t)0x3fb8, (q15_t)0x4607, (q15_t)0x3fb7, + (q15_t)0x4614, (q15_t)0x3fb6, (q15_t)0x4620, (q15_t)0x3fb5, (q15_t)0x462d, (q15_t)0x3fb4, (q15_t)0x4639, (q15_t)0x3fb2, + (q15_t)0x4646, (q15_t)0x3fb1, (q15_t)0x4652, (q15_t)0x3fb0, (q15_t)0x465f, (q15_t)0x3faf, (q15_t)0x466b, (q15_t)0x3fad, + (q15_t)0x4678, (q15_t)0x3fac, (q15_t)0x4684, (q15_t)0x3fab, (q15_t)0x4691, (q15_t)0x3faa, (q15_t)0x469d, (q15_t)0x3fa8, + (q15_t)0x46aa, (q15_t)0x3fa7, (q15_t)0x46b6, (q15_t)0x3fa6, (q15_t)0x46c3, (q15_t)0x3fa4, (q15_t)0x46cf, (q15_t)0x3fa3, + (q15_t)0x46dc, (q15_t)0x3fa2, (q15_t)0x46e8, (q15_t)0x3fa0, (q15_t)0x46f5, (q15_t)0x3f9f, (q15_t)0x4701, (q15_t)0x3f9e, + (q15_t)0x470e, (q15_t)0x3f9c, (q15_t)0x471a, (q15_t)0x3f9b, (q15_t)0x4727, (q15_t)0x3f99, (q15_t)0x4733, (q15_t)0x3f98, + (q15_t)0x4740, (q15_t)0x3f97, (q15_t)0x474c, (q15_t)0x3f95, (q15_t)0x4759, (q15_t)0x3f94, (q15_t)0x4765, (q15_t)0x3f92, + (q15_t)0x4772, (q15_t)0x3f91, (q15_t)0x477e, (q15_t)0x3f8f, (q15_t)0x478b, (q15_t)0x3f8e, (q15_t)0x4797, (q15_t)0x3f8c, + (q15_t)0x47a4, (q15_t)0x3f8b, (q15_t)0x47b0, (q15_t)0x3f89, (q15_t)0x47bd, (q15_t)0x3f88, (q15_t)0x47c9, (q15_t)0x3f86, + (q15_t)0x47d6, (q15_t)0x3f85, (q15_t)0x47e2, (q15_t)0x3f83, (q15_t)0x47ef, (q15_t)0x3f82, (q15_t)0x47fb, (q15_t)0x3f80, + (q15_t)0x4807, (q15_t)0x3f7f, (q15_t)0x4814, (q15_t)0x3f7d, (q15_t)0x4820, (q15_t)0x3f7b, (q15_t)0x482d, (q15_t)0x3f7a, + (q15_t)0x4839, (q15_t)0x3f78, (q15_t)0x4846, (q15_t)0x3f77, (q15_t)0x4852, (q15_t)0x3f75, (q15_t)0x485f, (q15_t)0x3f73, + (q15_t)0x486b, (q15_t)0x3f72, (q15_t)0x4878, (q15_t)0x3f70, (q15_t)0x4884, (q15_t)0x3f6e, (q15_t)0x4891, (q15_t)0x3f6d, + (q15_t)0x489d, (q15_t)0x3f6b, (q15_t)0x48a9, (q15_t)0x3f69, (q15_t)0x48b6, (q15_t)0x3f68, (q15_t)0x48c2, (q15_t)0x3f66, + (q15_t)0x48cf, (q15_t)0x3f64, (q15_t)0x48db, (q15_t)0x3f62, (q15_t)0x48e8, (q15_t)0x3f61, (q15_t)0x48f4, (q15_t)0x3f5f, + (q15_t)0x4901, (q15_t)0x3f5d, (q15_t)0x490d, (q15_t)0x3f5b, (q15_t)0x4919, (q15_t)0x3f5a, (q15_t)0x4926, (q15_t)0x3f58, + (q15_t)0x4932, (q15_t)0x3f56, (q15_t)0x493f, (q15_t)0x3f54, (q15_t)0x494b, (q15_t)0x3f52, (q15_t)0x4958, (q15_t)0x3f51, + (q15_t)0x4964, (q15_t)0x3f4f, (q15_t)0x4970, (q15_t)0x3f4d, (q15_t)0x497d, (q15_t)0x3f4b, (q15_t)0x4989, (q15_t)0x3f49, + (q15_t)0x4996, (q15_t)0x3f47, (q15_t)0x49a2, (q15_t)0x3f45, (q15_t)0x49af, (q15_t)0x3f43, (q15_t)0x49bb, (q15_t)0x3f42, + (q15_t)0x49c7, (q15_t)0x3f40, (q15_t)0x49d4, (q15_t)0x3f3e, (q15_t)0x49e0, (q15_t)0x3f3c, (q15_t)0x49ed, (q15_t)0x3f3a, + (q15_t)0x49f9, (q15_t)0x3f38, (q15_t)0x4a06, (q15_t)0x3f36, (q15_t)0x4a12, (q15_t)0x3f34, (q15_t)0x4a1e, (q15_t)0x3f32, + (q15_t)0x4a2b, (q15_t)0x3f30, (q15_t)0x4a37, (q15_t)0x3f2e, (q15_t)0x4a44, (q15_t)0x3f2c, (q15_t)0x4a50, (q15_t)0x3f2a, + (q15_t)0x4a5c, (q15_t)0x3f28, (q15_t)0x4a69, (q15_t)0x3f26, (q15_t)0x4a75, (q15_t)0x3f24, (q15_t)0x4a82, (q15_t)0x3f22, + (q15_t)0x4a8e, (q15_t)0x3f20, (q15_t)0x4a9a, (q15_t)0x3f1e, (q15_t)0x4aa7, (q15_t)0x3f1c, (q15_t)0x4ab3, (q15_t)0x3f19, + (q15_t)0x4ac0, (q15_t)0x3f17, (q15_t)0x4acc, (q15_t)0x3f15, (q15_t)0x4ad8, (q15_t)0x3f13, (q15_t)0x4ae5, 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(q15_t)0x493f, (q15_t)0xc0ac, + (q15_t)0x4932, (q15_t)0xc0aa, (q15_t)0x4926, (q15_t)0xc0a8, (q15_t)0x4919, (q15_t)0xc0a6, (q15_t)0x490d, (q15_t)0xc0a5, + (q15_t)0x4901, (q15_t)0xc0a3, (q15_t)0x48f4, (q15_t)0xc0a1, (q15_t)0x48e8, (q15_t)0xc09f, (q15_t)0x48db, (q15_t)0xc09e, + (q15_t)0x48cf, (q15_t)0xc09c, (q15_t)0x48c2, (q15_t)0xc09a, (q15_t)0x48b6, (q15_t)0xc098, (q15_t)0x48a9, (q15_t)0xc097, + (q15_t)0x489d, (q15_t)0xc095, (q15_t)0x4891, (q15_t)0xc093, (q15_t)0x4884, (q15_t)0xc092, (q15_t)0x4878, (q15_t)0xc090, + (q15_t)0x486b, (q15_t)0xc08e, (q15_t)0x485f, (q15_t)0xc08d, (q15_t)0x4852, (q15_t)0xc08b, (q15_t)0x4846, (q15_t)0xc089, + (q15_t)0x4839, (q15_t)0xc088, (q15_t)0x482d, (q15_t)0xc086, (q15_t)0x4820, (q15_t)0xc085, (q15_t)0x4814, (q15_t)0xc083, + (q15_t)0x4807, (q15_t)0xc081, (q15_t)0x47fb, (q15_t)0xc080, (q15_t)0x47ef, (q15_t)0xc07e, (q15_t)0x47e2, (q15_t)0xc07d, + (q15_t)0x47d6, (q15_t)0xc07b, (q15_t)0x47c9, (q15_t)0xc07a, (q15_t)0x47bd, (q15_t)0xc078, (q15_t)0x47b0, (q15_t)0xc077, + (q15_t)0x47a4, (q15_t)0xc075, (q15_t)0x4797, (q15_t)0xc074, (q15_t)0x478b, (q15_t)0xc072, (q15_t)0x477e, (q15_t)0xc071, + (q15_t)0x4772, (q15_t)0xc06f, (q15_t)0x4765, (q15_t)0xc06e, (q15_t)0x4759, (q15_t)0xc06c, (q15_t)0x474c, (q15_t)0xc06b, + (q15_t)0x4740, (q15_t)0xc069, (q15_t)0x4733, (q15_t)0xc068, (q15_t)0x4727, (q15_t)0xc067, (q15_t)0x471a, (q15_t)0xc065, + (q15_t)0x470e, (q15_t)0xc064, (q15_t)0x4701, (q15_t)0xc062, (q15_t)0x46f5, (q15_t)0xc061, (q15_t)0x46e8, (q15_t)0xc060, + (q15_t)0x46dc, (q15_t)0xc05e, (q15_t)0x46cf, (q15_t)0xc05d, (q15_t)0x46c3, (q15_t)0xc05c, (q15_t)0x46b6, (q15_t)0xc05a, + (q15_t)0x46aa, (q15_t)0xc059, (q15_t)0x469d, (q15_t)0xc058, (q15_t)0x4691, (q15_t)0xc056, (q15_t)0x4684, (q15_t)0xc055, + (q15_t)0x4678, (q15_t)0xc054, (q15_t)0x466b, (q15_t)0xc053, (q15_t)0x465f, (q15_t)0xc051, (q15_t)0x4652, (q15_t)0xc050, + (q15_t)0x4646, (q15_t)0xc04f, (q15_t)0x4639, (q15_t)0xc04e, (q15_t)0x462d, (q15_t)0xc04c, (q15_t)0x4620, (q15_t)0xc04b, + (q15_t)0x4614, (q15_t)0xc04a, (q15_t)0x4607, (q15_t)0xc049, (q15_t)0x45fb, (q15_t)0xc048, (q15_t)0x45ee, (q15_t)0xc047, + (q15_t)0x45e2, (q15_t)0xc045, (q15_t)0x45d5, (q15_t)0xc044, (q15_t)0x45c9, (q15_t)0xc043, (q15_t)0x45bc, (q15_t)0xc042, + (q15_t)0x45b0, (q15_t)0xc041, (q15_t)0x45a3, (q15_t)0xc040, (q15_t)0x4597, (q15_t)0xc03f, (q15_t)0x458a, (q15_t)0xc03d, + (q15_t)0x457e, (q15_t)0xc03c, (q15_t)0x4571, (q15_t)0xc03b, (q15_t)0x4565, (q15_t)0xc03a, (q15_t)0x4558, (q15_t)0xc039, + (q15_t)0x454c, (q15_t)0xc038, (q15_t)0x453f, (q15_t)0xc037, (q15_t)0x4533, (q15_t)0xc036, (q15_t)0x4526, (q15_t)0xc035, + (q15_t)0x451a, (q15_t)0xc034, (q15_t)0x450d, (q15_t)0xc033, (q15_t)0x4500, (q15_t)0xc032, (q15_t)0x44f4, (q15_t)0xc031, + (q15_t)0x44e7, (q15_t)0xc030, (q15_t)0x44db, (q15_t)0xc02f, (q15_t)0x44ce, (q15_t)0xc02e, (q15_t)0x44c2, (q15_t)0xc02d, + (q15_t)0x44b5, (q15_t)0xc02c, (q15_t)0x44a9, (q15_t)0xc02b, (q15_t)0x449c, (q15_t)0xc02b, (q15_t)0x4490, (q15_t)0xc02a, + (q15_t)0x4483, (q15_t)0xc029, (q15_t)0x4477, (q15_t)0xc028, (q15_t)0x446a, (q15_t)0xc027, (q15_t)0x445e, (q15_t)0xc026, + (q15_t)0x4451, (q15_t)0xc025, (q15_t)0x4444, (q15_t)0xc024, (q15_t)0x4438, (q15_t)0xc024, (q15_t)0x442b, (q15_t)0xc023, + (q15_t)0x441f, (q15_t)0xc022, (q15_t)0x4412, (q15_t)0xc021, (q15_t)0x4406, (q15_t)0xc020, (q15_t)0x43f9, (q15_t)0xc020, + (q15_t)0x43ed, (q15_t)0xc01f, (q15_t)0x43e0, (q15_t)0xc01e, (q15_t)0x43d4, (q15_t)0xc01d, (q15_t)0x43c7, (q15_t)0xc01d, + (q15_t)0x43bb, (q15_t)0xc01c, (q15_t)0x43ae, (q15_t)0xc01b, (q15_t)0x43a1, (q15_t)0xc01a, (q15_t)0x4395, (q15_t)0xc01a, + (q15_t)0x4388, (q15_t)0xc019, (q15_t)0x437c, (q15_t)0xc018, (q15_t)0x436f, (q15_t)0xc018, (q15_t)0x4363, (q15_t)0xc017, + (q15_t)0x4356, (q15_t)0xc016, (q15_t)0x434a, (q15_t)0xc016, (q15_t)0x433d, (q15_t)0xc015, (q15_t)0x4330, (q15_t)0xc014, + (q15_t)0x4324, (q15_t)0xc014, (q15_t)0x4317, (q15_t)0xc013, (q15_t)0x430b, (q15_t)0xc013, (q15_t)0x42fe, (q15_t)0xc012, + (q15_t)0x42f2, (q15_t)0xc011, (q15_t)0x42e5, (q15_t)0xc011, (q15_t)0x42d9, (q15_t)0xc010, (q15_t)0x42cc, (q15_t)0xc010, + (q15_t)0x42c0, (q15_t)0xc00f, (q15_t)0x42b3, (q15_t)0xc00f, (q15_t)0x42a6, (q15_t)0xc00e, (q15_t)0x429a, (q15_t)0xc00e, + (q15_t)0x428d, (q15_t)0xc00d, (q15_t)0x4281, (q15_t)0xc00d, (q15_t)0x4274, (q15_t)0xc00c, (q15_t)0x4268, (q15_t)0xc00c, + (q15_t)0x425b, (q15_t)0xc00b, (q15_t)0x424e, (q15_t)0xc00b, (q15_t)0x4242, (q15_t)0xc00a, (q15_t)0x4235, (q15_t)0xc00a, + (q15_t)0x4229, (q15_t)0xc009, (q15_t)0x421c, (q15_t)0xc009, (q15_t)0x4210, (q15_t)0xc009, (q15_t)0x4203, (q15_t)0xc008, + (q15_t)0x41f7, (q15_t)0xc008, (q15_t)0x41ea, (q15_t)0xc007, (q15_t)0x41dd, (q15_t)0xc007, (q15_t)0x41d1, (q15_t)0xc007, + (q15_t)0x41c4, (q15_t)0xc006, (q15_t)0x41b8, (q15_t)0xc006, (q15_t)0x41ab, (q15_t)0xc006, (q15_t)0x419f, (q15_t)0xc005, + (q15_t)0x4192, (q15_t)0xc005, (q15_t)0x4186, (q15_t)0xc005, (q15_t)0x4179, (q15_t)0xc004, (q15_t)0x416c, (q15_t)0xc004, + (q15_t)0x4160, (q15_t)0xc004, (q15_t)0x4153, (q15_t)0xc004, (q15_t)0x4147, (q15_t)0xc003, (q15_t)0x413a, (q15_t)0xc003, + (q15_t)0x412e, (q15_t)0xc003, (q15_t)0x4121, (q15_t)0xc003, (q15_t)0x4114, (q15_t)0xc002, (q15_t)0x4108, (q15_t)0xc002, + (q15_t)0x40fb, (q15_t)0xc002, (q15_t)0x40ef, (q15_t)0xc002, (q15_t)0x40e2, (q15_t)0xc002, (q15_t)0x40d6, (q15_t)0xc001, + (q15_t)0x40c9, (q15_t)0xc001, (q15_t)0x40bc, (q15_t)0xc001, (q15_t)0x40b0, (q15_t)0xc001, (q15_t)0x40a3, (q15_t)0xc001, + (q15_t)0x4097, (q15_t)0xc001, (q15_t)0x408a, (q15_t)0xc001, (q15_t)0x407e, (q15_t)0xc000, (q15_t)0x4071, (q15_t)0xc000, + (q15_t)0x4065, (q15_t)0xc000, (q15_t)0x4058, (q15_t)0xc000, (q15_t)0x404b, (q15_t)0xc000, (q15_t)0x403f, (q15_t)0xc000, + (q15_t)0x4032, (q15_t)0xc000, (q15_t)0x4026, (q15_t)0xc000, (q15_t)0x4019, (q15_t)0xc000, (q15_t)0x400d, (q15_t)0xc000, +}; + +#endif +/** + @} end of RealFFT_Table group + */ + +/** + @ingroup DCT4_IDCT4 + */ + +/** + @addtogroup DCT4_IDCT4_Table DCT Type IV Tables + @{ + */ + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos (i*c);
+    weights[(2*i)+1] = -sin (i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + @par + 
 for(i = 0; i< N; i++)
+  {
+     cos_factors[i]= 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) +*/ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + const float32_t Weights_128[256] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f, -0.012271538285719925f, + 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f, -0.036807222941358832f, + 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f, -0.061320736302208578f, + 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f, -0.085797312344439894f, + 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f, -0.110222207293883060f, + 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f, -0.134580708507126170f, + 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f, -0.158858143333861450f, + 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f, -0.183039887955140950f, + 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f, -0.207111376192218560f, + 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f, -0.231058108280671110f, + 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f, -0.254865659604514570f, + 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f, -0.278519689385053060f, + 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f, -0.302005949319228080f, + 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f, -0.325310292162262930f, + 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f, -0.348418680249434560f, + 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f, -0.371317193951837540f, + 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f, -0.393992040061048100f, + 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f, -0.416429560097637150f, + 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f, -0.438616238538527660f, + 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f, -0.460538710958240010f, + 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f, -0.482183772079122720f, + 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f, -0.503538383725717580f, + 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f, -0.524589682678468950f, + 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f, -0.545324988422046460f, + 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f, -0.565731810783613120f, + 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f, -0.585797857456438860f, + 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f, -0.605511041404325550f, + 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f, -0.624859488142386340f, + 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f, -0.643831542889791390f, + 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f, -0.662415777590171780f, + 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f, -0.680600997795453020f, + 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f, -0.698376249408972920f, + 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f, -0.715730825283818590f, + 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f, -0.732654271672412820f, + 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f, -0.749136394523459260f, + 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f, -0.765167265622458960f, + 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f, -0.780737228572094380f, + 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f, -0.795836904608883460f, + 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f, 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0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f, -0.937339011912574960f, + 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f, -0.945607325380521280f, + 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f, -0.953306040354193750f, + 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f, -0.960430519415565790f, + 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f, -0.966976471044852070f, + 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f, -0.972939952205560070f, + 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f, -0.978317370719627650f, + 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f, -0.983105487431216290f, + 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f, -0.987301418157858430f, + 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f, -0.990902635427780010f, + 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f, -0.993906970002356060f, + 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f, -0.996312612182778000f, + 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f, -0.998118112900149180f, + 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f, -0.999322384588349540f, + 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f, -0.999924701839144500f +}; + + const float32_t cos_factors_128[128] = { + 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f, + 0.999077727752645360f, + 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f, + 0.995767414467659820f, + 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f, + 0.990058210262297120f, + 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f, + 0.981963869109555240f, + 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f, + 0.971503890986251780f, + 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0.000191747598192208f +}; + #endif + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  { 
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Converted the output to q15 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q15 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + + const q15_t __ALIGNED(4) WeightsQ15_128[256] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7fe9, (q15_t)0xfb4a, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f87, (q15_t)0xf505, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7ed5, (q15_t)0xeec7, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7dd6, (q15_t)0xe893, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7c89, (q15_t)0xe26d, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7aef, (q15_t)0xdc5a, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7909, (q15_t)0xd65d, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x76d9, (q15_t)0xd079, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x745f, (q15_t)0xcab3, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x719e, (q15_t)0xc50e, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6e96, (q15_t)0xbf8d, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6b4a, (q15_t)0xba33, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x67bd, (q15_t)0xb505, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x63ef, (q15_t)0xb005, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x5fe3, (q15_t)0xab36, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5b9d, (q15_t)0xa69c, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x571d, (q15_t)0xa239, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5269, (q15_t)0x9e0f, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4d81, (q15_t)0x9a23, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4869, (q15_t)0x9674, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4325, (q15_t)0x9307, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3db8, (q15_t)0x8fdd, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3824, (q15_t)0x8cf9, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x326e, (q15_t)0x8a5b, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2c98, (q15_t)0x8806, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x26a8, (q15_t)0x85fb, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x209f, (q15_t)0x843b, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1a82, (q15_t)0x82c7, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x1455, (q15_t)0x81a1, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1139, (q15_t)0x812b, (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xe1b, (q15_t)0x80c8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xafb, (q15_t)0x8079, (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x7d9, (q15_t)0x803e, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x324, (q15_t)0x800a, (q15_t)0x192, (q15_t)0x8003 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_128[128] = { + (q15_t)0x7fff, (q15_t)0x7ffa, (q15_t)0x7ff0, (q15_t)0x7fe1, (q15_t)0x7fce, (q15_t)0x7fb5, (q15_t)0x7f97, (q15_t)0x7f75, + (q15_t)0x7f4d, (q15_t)0x7f21, (q15_t)0x7ef0, (q15_t)0x7eba, (q15_t)0x7e7f, (q15_t)0x7e3f, (q15_t)0x7dfa, (q15_t)0x7db0, + (q15_t)0x7d62, (q15_t)0x7d0f, (q15_t)0x7cb7, (q15_t)0x7c5a, (q15_t)0x7bf8, (q15_t)0x7b92, (q15_t)0x7b26, (q15_t)0x7ab6, + (q15_t)0x7a42, (q15_t)0x79c8, (q15_t)0x794a, (q15_t)0x78c7, (q15_t)0x7840, (q15_t)0x77b4, (q15_t)0x7723, (q15_t)0x768e, + (q15_t)0x75f4, (q15_t)0x7555, (q15_t)0x74b2, (q15_t)0x740b, (q15_t)0x735f, (q15_t)0x72af, (q15_t)0x71fa, (q15_t)0x7141, + (q15_t)0x7083, (q15_t)0x6fc1, (q15_t)0x6efb, (q15_t)0x6e30, (q15_t)0x6d62, (q15_t)0x6c8f, (q15_t)0x6bb8, (q15_t)0x6adc, + (q15_t)0x69fd, (q15_t)0x6919, (q15_t)0x6832, (q15_t)0x6746, (q15_t)0x6657, (q15_t)0x6563, (q15_t)0x646c, (q15_t)0x6371, + (q15_t)0x6271, (q15_t)0x616f, (q15_t)0x6068, (q15_t)0x5f5e, (q15_t)0x5e50, (q15_t)0x5d3e, (q15_t)0x5c29, (q15_t)0x5b10, + (q15_t)0x59f3, (q15_t)0x58d4, (q15_t)0x57b0, (q15_t)0x568a, (q15_t)0x5560, (q15_t)0x5433, (q15_t)0x5302, (q15_t)0x51ce, + (q15_t)0x5097, (q15_t)0x4f5e, (q15_t)0x4e21, (q15_t)0x4ce1, (q15_t)0x4b9e, (q15_t)0x4a58, (q15_t)0x490f, (q15_t)0x47c3, + (q15_t)0x4675, (q15_t)0x4524, (q15_t)0x43d0, (q15_t)0x427a, (q15_t)0x4121, (q15_t)0x3fc5, (q15_t)0x3e68, (q15_t)0x3d07, + (q15_t)0x3ba5, (q15_t)0x3a40, (q15_t)0x38d8, (q15_t)0x376f, (q15_t)0x3604, (q15_t)0x3496, (q15_t)0x3326, (q15_t)0x31b5, + (q15_t)0x3041, (q15_t)0x2ecc, (q15_t)0x2d55, (q15_t)0x2bdc, (q15_t)0x2a61, (q15_t)0x28e5, (q15_t)0x2767, (q15_t)0x25e8, + (q15_t)0x2467, (q15_t)0x22e5, (q15_t)0x2161, (q15_t)0x1fdc, (q15_t)0x1e56, (q15_t)0x1ccf, (q15_t)0x1b47, (q15_t)0x19bd, + (q15_t)0x1833, (q15_t)0x16a8, (q15_t)0x151b, (q15_t)0x138e, (q15_t)0x1201, (q15_t)0x1072, (q15_t)0xee3, (q15_t)0xd53, + (q15_t)0xbc3, (q15_t)0xa33, (q15_t)0x8a2, (q15_t)0x710, (q15_t)0x57f, (q15_t)0x3ed, (q15_t)0x25b, (q15_t)0xc9 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + const q15_t __ALIGNED(4) WeightsQ15_512[1024] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7ffe, (q15_t)0xfed3, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff8, (q15_t)0xfd41, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fed, (q15_t)0xfbaf, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fdd, (q15_t)0xfa1d, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fc8, (q15_t)0xf88b, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fae, (q15_t)0xf6fa, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f8f, (q15_t)0xf569, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f6b, (q15_t)0xf3d9, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f43, (q15_t)0xf249, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f15, (q15_t)0xf0b9, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7ee3, (q15_t)0xef2a, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eab, (q15_t)0xed9c, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e6f, (q15_t)0xec0e, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e2e, (q15_t)0xea81, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7de8, (q15_t)0xe8f6, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7d9d, (q15_t)0xe76a, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d4e, (q15_t)0xe5e0, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7cf9, (q15_t)0xe457, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7ca0, (q15_t)0xe2cf, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c42, (q15_t)0xe148, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bdf, (q15_t)0xdfc2, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b77, (q15_t)0xde3e, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b0b, (q15_t)0xdcbb, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7a9a, (q15_t)0xdb39, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a24, (q15_t)0xd9b8, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79a9, (q15_t)0xd839, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x792a, (q15_t)0xd6bc, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78a6, (q15_t)0xd540, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x781d, (q15_t)0xd3c6, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x7790, (q15_t)0xd24d, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x76fe, (q15_t)0xd0d7, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7668, (q15_t)0xcf62, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75cc, (q15_t)0xcdef, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x752d, (q15_t)0xcc7e, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x7489, (q15_t)0xcb0e, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x73e0, (q15_t)0xc9a1, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7333, (q15_t)0xc836, + (q15_t)0x7307, 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(q15_t)0x90d3, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e10, (q15_t)0x900e, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3caf, (q15_t)0x8f4d, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b4c, (q15_t)0x8e91, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x39e6, (q15_t)0x8dd9, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x387e, (q15_t)0x8d25, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3714, (q15_t)0x8c76, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35a8, (q15_t)0x8bcb, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x343a, (q15_t)0x8b25, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x32ca, (q15_t)0x8a83, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x3158, (q15_t)0x89e5, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x2fe4, (q15_t)0x894d, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2e6e, (q15_t)0x88b9, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2cf7, (q15_t)0x8829, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2b7d, (q15_t)0x879e, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a02, (q15_t)0x8718, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x2886, (q15_t)0x8696, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2707, (q15_t)0x8619, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x2588, (q15_t)0x85a1, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2407, (q15_t)0x852d, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x2284, (q15_t)0x84be, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2100, (q15_t)0x8454, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1f7b, (q15_t)0x83ef, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1df5, (q15_t)0x838f, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1c6d, (q15_t)0x8333, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1ae4, (q15_t)0x82dc, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x195b, (q15_t)0x828a, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x17d0, (q15_t)0x823d, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x1645, (q15_t)0x81f4, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x14b8, (q15_t)0x81b1, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x132b, (q15_t)0x8172, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x119d, (q15_t)0x8138, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x100e, (q15_t)0x8103, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xe7f, (q15_t)0x80d3, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xcef, (q15_t)0x80a8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xb5f, (q15_t)0x8082, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa33, (q15_t)0x8069, (q15_t)0x9ce, (q15_t)0x8061, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x83d, (q15_t)0x8044, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x775, (q15_t)0x8038, (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6ac, (q15_t)0x802d, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x51a, (q15_t)0x801b, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x451, (q15_t)0x8013, (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x388, (q15_t)0x800d, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x1f6, (q15_t)0x8004, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x12d, (q15_t)0x8002, (q15_t)0xc9, (q15_t)0x8001, (q15_t)0x64, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_512[512] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ff9, (q15_t)0x7ff7, + (q15_t)0x7ff4, (q15_t)0x7ff2, (q15_t)0x7fee, (q15_t)0x7feb, (q15_t)0x7fe7, (q15_t)0x7fe3, (q15_t)0x7fdf, (q15_t)0x7fda, + (q15_t)0x7fd6, (q15_t)0x7fd0, (q15_t)0x7fcb, (q15_t)0x7fc5, (q15_t)0x7fbf, (q15_t)0x7fb8, (q15_t)0x7fb1, (q15_t)0x7faa, + (q15_t)0x7fa3, (q15_t)0x7f9b, (q15_t)0x7f93, (q15_t)0x7f8b, (q15_t)0x7f82, (q15_t)0x7f79, (q15_t)0x7f70, (q15_t)0x7f67, + (q15_t)0x7f5d, (q15_t)0x7f53, (q15_t)0x7f48, (q15_t)0x7f3d, (q15_t)0x7f32, (q15_t)0x7f27, (q15_t)0x7f1b, (q15_t)0x7f0f, + (q15_t)0x7f03, (q15_t)0x7ef6, (q15_t)0x7ee9, (q15_t)0x7edc, (q15_t)0x7ecf, (q15_t)0x7ec1, (q15_t)0x7eb3, (q15_t)0x7ea4, + (q15_t)0x7e95, (q15_t)0x7e86, (q15_t)0x7e77, (q15_t)0x7e67, (q15_t)0x7e57, (q15_t)0x7e47, (q15_t)0x7e37, (q15_t)0x7e26, + (q15_t)0x7e14, (q15_t)0x7e03, (q15_t)0x7df1, (q15_t)0x7ddf, (q15_t)0x7dcd, (q15_t)0x7dba, (q15_t)0x7da7, (q15_t)0x7d94, + (q15_t)0x7d80, (q15_t)0x7d6c, (q15_t)0x7d58, (q15_t)0x7d43, (q15_t)0x7d2f, (q15_t)0x7d19, (q15_t)0x7d04, (q15_t)0x7cee, + (q15_t)0x7cd8, (q15_t)0x7cc2, (q15_t)0x7cab, (q15_t)0x7c94, (q15_t)0x7c7d, (q15_t)0x7c66, (q15_t)0x7c4e, (q15_t)0x7c36, + (q15_t)0x7c1d, (q15_t)0x7c05, (q15_t)0x7beb, (q15_t)0x7bd2, (q15_t)0x7bb9, (q15_t)0x7b9f, (q15_t)0x7b84, (q15_t)0x7b6a, + (q15_t)0x7b4f, (q15_t)0x7b34, (q15_t)0x7b19, (q15_t)0x7afd, (q15_t)0x7ae1, (q15_t)0x7ac5, (q15_t)0x7aa8, (q15_t)0x7a8b, + (q15_t)0x7a6e, (q15_t)0x7a50, (q15_t)0x7a33, (q15_t)0x7a15, (q15_t)0x79f6, (q15_t)0x79d8, (q15_t)0x79b9, (q15_t)0x7999, + (q15_t)0x797a, (q15_t)0x795a, (q15_t)0x793a, (q15_t)0x7919, (q15_t)0x78f9, (q15_t)0x78d8, (q15_t)0x78b6, (q15_t)0x7895, + (q15_t)0x7873, (q15_t)0x7851, (q15_t)0x782e, (q15_t)0x780c, (q15_t)0x77e9, (q15_t)0x77c5, (q15_t)0x77a2, (q15_t)0x777e, + (q15_t)0x775a, (q15_t)0x7735, (q15_t)0x7710, (q15_t)0x76eb, (q15_t)0x76c6, (q15_t)0x76a0, (q15_t)0x767b, (q15_t)0x7654, + (q15_t)0x762e, (q15_t)0x7607, (q15_t)0x75e0, (q15_t)0x75b9, (q15_t)0x7591, (q15_t)0x7569, (q15_t)0x7541, (q15_t)0x7519, + (q15_t)0x74f0, (q15_t)0x74c7, (q15_t)0x749e, (q15_t)0x7474, (q15_t)0x744a, (q15_t)0x7420, (q15_t)0x73f6, (q15_t)0x73cb, + (q15_t)0x73a0, (q15_t)0x7375, (q15_t)0x7349, (q15_t)0x731d, (q15_t)0x72f1, (q15_t)0x72c5, (q15_t)0x7298, (q15_t)0x726b, + (q15_t)0x723e, (q15_t)0x7211, (q15_t)0x71e3, (q15_t)0x71b5, (q15_t)0x7186, (q15_t)0x7158, (q15_t)0x7129, (q15_t)0x70fa, + (q15_t)0x70cb, (q15_t)0x709b, (q15_t)0x706b, (q15_t)0x703b, (q15_t)0x700a, (q15_t)0x6fda, (q15_t)0x6fa9, (q15_t)0x6f77, + (q15_t)0x6f46, (q15_t)0x6f14, (q15_t)0x6ee2, (q15_t)0x6eaf, (q15_t)0x6e7d, (q15_t)0x6e4a, (q15_t)0x6e17, (q15_t)0x6de3, + (q15_t)0x6db0, (q15_t)0x6d7c, (q15_t)0x6d48, (q15_t)0x6d13, (q15_t)0x6cde, (q15_t)0x6ca9, (q15_t)0x6c74, (q15_t)0x6c3f, + (q15_t)0x6c09, (q15_t)0x6bd3, (q15_t)0x6b9c, (q15_t)0x6b66, (q15_t)0x6b2f, (q15_t)0x6af8, (q15_t)0x6ac1, (q15_t)0x6a89, + (q15_t)0x6a51, (q15_t)0x6a19, (q15_t)0x69e1, (q15_t)0x69a8, (q15_t)0x696f, (q15_t)0x6936, (q15_t)0x68fd, (q15_t)0x68c3, + (q15_t)0x6889, (q15_t)0x684f, (q15_t)0x6815, (q15_t)0x67da, (q15_t)0x679f, (q15_t)0x6764, (q15_t)0x6729, (q15_t)0x66ed, + (q15_t)0x66b1, (q15_t)0x6675, (q15_t)0x6639, (q15_t)0x65fc, (q15_t)0x65bf, (q15_t)0x6582, (q15_t)0x6545, (q15_t)0x6507, + (q15_t)0x64c9, (q15_t)0x648b, (q15_t)0x644d, (q15_t)0x640e, (q15_t)0x63cf, (q15_t)0x6390, (q15_t)0x6351, (q15_t)0x6311, + (q15_t)0x62d2, (q15_t)0x6292, (q15_t)0x6251, (q15_t)0x6211, (q15_t)0x61d0, (q15_t)0x618f, (q15_t)0x614e, (q15_t)0x610d, + (q15_t)0x60cb, (q15_t)0x6089, (q15_t)0x6047, (q15_t)0x6004, (q15_t)0x5fc2, (q15_t)0x5f7f, (q15_t)0x5f3c, (q15_t)0x5ef9, + (q15_t)0x5eb5, (q15_t)0x5e71, (q15_t)0x5e2d, (q15_t)0x5de9, (q15_t)0x5da5, (q15_t)0x5d60, (q15_t)0x5d1b, (q15_t)0x5cd6, + (q15_t)0x5c91, (q15_t)0x5c4b, (q15_t)0x5c06, (q15_t)0x5bc0, (q15_t)0x5b79, (q15_t)0x5b33, (q15_t)0x5aec, (q15_t)0x5aa5, + (q15_t)0x5a5e, (q15_t)0x5a17, (q15_t)0x59d0, (q15_t)0x5988, (q15_t)0x5940, (q15_t)0x58f8, (q15_t)0x58af, (q15_t)0x5867, + (q15_t)0x581e, (q15_t)0x57d5, (q15_t)0x578c, (q15_t)0x5742, (q15_t)0x56f9, (q15_t)0x56af, (q15_t)0x5665, (q15_t)0x561a, + (q15_t)0x55d0, (q15_t)0x5585, (q15_t)0x553a, (q15_t)0x54ef, (q15_t)0x54a4, (q15_t)0x5458, (q15_t)0x540d, (q15_t)0x53c1, + (q15_t)0x5375, (q15_t)0x5328, (q15_t)0x52dc, (q15_t)0x528f, (q15_t)0x5242, (q15_t)0x51f5, (q15_t)0x51a8, (q15_t)0x515a, + (q15_t)0x510c, (q15_t)0x50bf, (q15_t)0x5070, (q15_t)0x5022, (q15_t)0x4fd4, (q15_t)0x4f85, (q15_t)0x4f36, (q15_t)0x4ee7, + (q15_t)0x4e98, (q15_t)0x4e48, (q15_t)0x4df9, (q15_t)0x4da9, (q15_t)0x4d59, (q15_t)0x4d09, (q15_t)0x4cb8, (q15_t)0x4c68, + (q15_t)0x4c17, (q15_t)0x4bc6, (q15_t)0x4b75, (q15_t)0x4b24, (q15_t)0x4ad2, (q15_t)0x4a81, (q15_t)0x4a2f, (q15_t)0x49dd, + (q15_t)0x498a, (q15_t)0x4938, (q15_t)0x48e6, (q15_t)0x4893, (q15_t)0x4840, (q15_t)0x47ed, (q15_t)0x479a, (q15_t)0x4746, + (q15_t)0x46f3, (q15_t)0x469f, (q15_t)0x464b, (q15_t)0x45f7, (q15_t)0x45a3, (q15_t)0x454e, (q15_t)0x44fa, (q15_t)0x44a5, + (q15_t)0x4450, (q15_t)0x43fb, (q15_t)0x43a5, (q15_t)0x4350, (q15_t)0x42fa, (q15_t)0x42a5, (q15_t)0x424f, (q15_t)0x41f9, + (q15_t)0x41a2, (q15_t)0x414c, (q15_t)0x40f6, (q15_t)0x409f, (q15_t)0x4048, (q15_t)0x3ff1, (q15_t)0x3f9a, (q15_t)0x3f43, + (q15_t)0x3eeb, (q15_t)0x3e93, (q15_t)0x3e3c, (q15_t)0x3de4, (q15_t)0x3d8c, (q15_t)0x3d33, (q15_t)0x3cdb, (q15_t)0x3c83, + (q15_t)0x3c2a, (q15_t)0x3bd1, (q15_t)0x3b78, (q15_t)0x3b1f, (q15_t)0x3ac6, (q15_t)0x3a6c, (q15_t)0x3a13, (q15_t)0x39b9, + (q15_t)0x395f, (q15_t)0x3906, (q15_t)0x38ab, (q15_t)0x3851, (q15_t)0x37f7, (q15_t)0x379c, (q15_t)0x3742, (q15_t)0x36e7, + (q15_t)0x368c, (q15_t)0x3631, (q15_t)0x35d6, (q15_t)0x357b, (q15_t)0x351f, (q15_t)0x34c4, (q15_t)0x3468, (q15_t)0x340c, + (q15_t)0x33b0, (q15_t)0x3354, (q15_t)0x32f8, (q15_t)0x329c, (q15_t)0x3240, (q15_t)0x31e3, (q15_t)0x3186, (q15_t)0x312a, + (q15_t)0x30cd, (q15_t)0x3070, (q15_t)0x3013, (q15_t)0x2fb5, (q15_t)0x2f58, (q15_t)0x2efb, (q15_t)0x2e9d, (q15_t)0x2e3f, + (q15_t)0x2de2, (q15_t)0x2d84, (q15_t)0x2d26, (q15_t)0x2cc8, (q15_t)0x2c69, (q15_t)0x2c0b, (q15_t)0x2bad, (q15_t)0x2b4e, + (q15_t)0x2aef, (q15_t)0x2a91, (q15_t)0x2a32, (q15_t)0x29d3, (q15_t)0x2974, (q15_t)0x2915, (q15_t)0x28b5, (q15_t)0x2856, + (q15_t)0x27f6, (q15_t)0x2797, (q15_t)0x2737, (q15_t)0x26d8, (q15_t)0x2678, (q15_t)0x2618, (q15_t)0x25b8, (q15_t)0x2558, + (q15_t)0x24f7, (q15_t)0x2497, (q15_t)0x2437, (q15_t)0x23d6, (q15_t)0x2376, (q15_t)0x2315, (q15_t)0x22b4, (q15_t)0x2254, + (q15_t)0x21f3, (q15_t)0x2192, (q15_t)0x2131, (q15_t)0x20d0, (q15_t)0x206e, (q15_t)0x200d, (q15_t)0x1fac, (q15_t)0x1f4a, + (q15_t)0x1ee9, (q15_t)0x1e87, (q15_t)0x1e25, (q15_t)0x1dc4, (q15_t)0x1d62, (q15_t)0x1d00, (q15_t)0x1c9e, (q15_t)0x1c3c, + (q15_t)0x1bda, (q15_t)0x1b78, (q15_t)0x1b16, (q15_t)0x1ab3, (q15_t)0x1a51, (q15_t)0x19ef, (q15_t)0x198c, (q15_t)0x192a, + (q15_t)0x18c7, (q15_t)0x1864, (q15_t)0x1802, (q15_t)0x179f, (q15_t)0x173c, (q15_t)0x16d9, (q15_t)0x1676, (q15_t)0x1613, + (q15_t)0x15b0, (q15_t)0x154d, (q15_t)0x14ea, (q15_t)0x1487, (q15_t)0x1423, (q15_t)0x13c0, (q15_t)0x135d, (q15_t)0x12f9, + (q15_t)0x1296, (q15_t)0x1232, (q15_t)0x11cf, (q15_t)0x116b, (q15_t)0x1108, (q15_t)0x10a4, (q15_t)0x1040, (q15_t)0xfdd, + (q15_t)0xf79, (q15_t)0xf15, (q15_t)0xeb1, (q15_t)0xe4d, (q15_t)0xde9, (q15_t)0xd85, (q15_t)0xd21, (q15_t)0xcbd, + (q15_t)0xc59, (q15_t)0xbf5, (q15_t)0xb91, (q15_t)0xb2d, (q15_t)0xac9, (q15_t)0xa65, (q15_t)0xa00, (q15_t)0x99c, + (q15_t)0x938, (q15_t)0x8d4, (q15_t)0x86f, (q15_t)0x80b, (q15_t)0x7a7, (q15_t)0x742, (q15_t)0x6de, (q15_t)0x67a, + (q15_t)0x615, (q15_t)0x5b1, (q15_t)0x54c, (q15_t)0x4e8, (q15_t)0x483, (q15_t)0x41f, (q15_t)0x3ba, (q15_t)0x356, + (q15_t)0x2f1, (q15_t)0x28d, (q15_t)0x228, (q15_t)0x1c4, (q15_t)0x15f, (q15_t)0xfb, (q15_t)0x96, (q15_t)0x32 +}; + + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + const q15_t __ALIGNED(4) WeightsQ15_2048[4096] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffb5, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff51, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeec, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffd, (q15_t)0xfe88, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe23, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffa, (q15_t)0xfdbe, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff8, (q15_t)0xfd5a, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff6, (q15_t)0xfcf5, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfc91, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc2c, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbc8, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7fea, (q15_t)0xfb64, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe6, (q15_t)0xfaff, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe2, (q15_t)0xfa9b, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fde, (q15_t)0xfa36, + (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fd9, (q15_t)0xf9d2, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd4, (q15_t)0xf96d, + (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fcf, (q15_t)0xf909, + (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fc9, (q15_t)0xf8a5, + (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc3, (q15_t)0xf840, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbd, (q15_t)0xf7dc, + (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb7, (q15_t)0xf778, + (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb0, (q15_t)0xf713, + (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7fa9, (q15_t)0xf6af, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa1, (q15_t)0xf64b, + (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f99, (q15_t)0xf5e7, + (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f91, (q15_t)0xf582, + (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f89, (q15_t)0xf51e, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f80, (q15_t)0xf4ba, + (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f77, (q15_t)0xf456, + (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f6e, (q15_t)0xf3f2, + (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f64, (q15_t)0xf38e, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5a, (q15_t)0xf32a, + (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f50, (q15_t)0xf2c6, + (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f45, (q15_t)0xf262, + (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3b, (q15_t)0xf1fe, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f2f, (q15_t)0xf19a, + (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f24, (q15_t)0xf136, + (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f18, (q15_t)0xf0d2, + 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(q15_t)0x8067, (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9e7, (q15_t)0x8063, + (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x983, (q15_t)0x805b, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x951, (q15_t)0x8057, (q15_t)0x938, (q15_t)0x8056, (q15_t)0x91f, (q15_t)0x8054, + (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8bb, (q15_t)0x804d, + (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x888, (q15_t)0x8049, (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x856, (q15_t)0x8046, + (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x824, (q15_t)0x8043, (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x7f2, (q15_t)0x8040, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x78e, (q15_t)0x803a, + (q15_t)0x775, (q15_t)0x8038, (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x742, (q15_t)0x8035, (q15_t)0x729, (q15_t)0x8034, + (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6c5, (q15_t)0x802e, + (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x693, (q15_t)0x802c, (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x660, (q15_t)0x8029, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x615, (q15_t)0x8026, (q15_t)0x5fc, (q15_t)0x8024, + (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x598, (q15_t)0x8020, + (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x565, (q15_t)0x801e, (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x533, (q15_t)0x801c, + (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4cf, (q15_t)0x8018, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x483, (q15_t)0x8015, (q15_t)0x46a, (q15_t)0x8014, + (q15_t)0x451, (q15_t)0x8013, (q15_t)0x438, (q15_t)0x8012, (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x406, (q15_t)0x8011, + (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3a1, (q15_t)0x800e, + (q15_t)0x388, (q15_t)0x800d, (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x356, (q15_t)0x800c, (q15_t)0x33d, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2d8, (q15_t)0x8009, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x274, (q15_t)0x8007, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x242, (q15_t)0x8006, (q15_t)0x228, (q15_t)0x8005, (q15_t)0x20f, (q15_t)0x8005, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1ab, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x178, (q15_t)0x8003, (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x146, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x114, (q15_t)0x8002, (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xe2, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xaf, (q15_t)0x8001, (q15_t)0x96, (q15_t)0x8001, (q15_t)0x7d, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x32, (q15_t)0x8001, (q15_t)0x19, (q15_t)0x8001 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_2048[2048] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, + (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff1, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7fea, + (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe3, (q15_t)0x7fe2, + (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fda, (q15_t)0x7fd9, + (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd0, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc4, (q15_t)0x7fc3, + (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fbe, (q15_t)0x7fbc, (q15_t)0x7fbb, (q15_t)0x7fb9, (q15_t)0x7fb7, (q15_t)0x7fb6, + (q15_t)0x7fb4, (q15_t)0x7fb2, (q15_t)0x7fb1, (q15_t)0x7faf, (q15_t)0x7fad, (q15_t)0x7fab, (q15_t)0x7fa9, (q15_t)0x7fa8, + (q15_t)0x7fa6, (q15_t)0x7fa4, (q15_t)0x7fa2, (q15_t)0x7fa0, (q15_t)0x7f9e, (q15_t)0x7f9c, (q15_t)0x7f9a, (q15_t)0x7f98, + (q15_t)0x7f96, (q15_t)0x7f94, (q15_t)0x7f92, (q15_t)0x7f90, (q15_t)0x7f8e, (q15_t)0x7f8c, (q15_t)0x7f8a, (q15_t)0x7f88, + (q15_t)0x7f86, (q15_t)0x7f83, (q15_t)0x7f81, (q15_t)0x7f7f, (q15_t)0x7f7d, (q15_t)0x7f7b, (q15_t)0x7f78, (q15_t)0x7f76, + (q15_t)0x7f74, (q15_t)0x7f71, (q15_t)0x7f6f, (q15_t)0x7f6d, (q15_t)0x7f6a, (q15_t)0x7f68, (q15_t)0x7f65, (q15_t)0x7f63, + (q15_t)0x7f60, (q15_t)0x7f5e, (q15_t)0x7f5b, (q15_t)0x7f59, (q15_t)0x7f56, (q15_t)0x7f54, (q15_t)0x7f51, (q15_t)0x7f4f, + (q15_t)0x7f4c, (q15_t)0x7f49, (q15_t)0x7f47, (q15_t)0x7f44, (q15_t)0x7f41, (q15_t)0x7f3f, (q15_t)0x7f3c, (q15_t)0x7f39, + (q15_t)0x7f36, (q15_t)0x7f34, (q15_t)0x7f31, (q15_t)0x7f2e, (q15_t)0x7f2b, (q15_t)0x7f28, (q15_t)0x7f25, (q15_t)0x7f23, + (q15_t)0x7f20, (q15_t)0x7f1d, (q15_t)0x7f1a, (q15_t)0x7f17, (q15_t)0x7f14, (q15_t)0x7f11, (q15_t)0x7f0e, (q15_t)0x7f0b, + (q15_t)0x7f08, (q15_t)0x7f04, (q15_t)0x7f01, (q15_t)0x7efe, (q15_t)0x7efb, (q15_t)0x7ef8, (q15_t)0x7ef5, (q15_t)0x7ef1, + (q15_t)0x7eee, (q15_t)0x7eeb, (q15_t)0x7ee8, (q15_t)0x7ee4, (q15_t)0x7ee1, (q15_t)0x7ede, (q15_t)0x7eda, (q15_t)0x7ed7, + (q15_t)0x7ed4, (q15_t)0x7ed0, (q15_t)0x7ecd, (q15_t)0x7ec9, (q15_t)0x7ec6, (q15_t)0x7ec3, (q15_t)0x7ebf, (q15_t)0x7ebb, + (q15_t)0x7eb8, (q15_t)0x7eb4, (q15_t)0x7eb1, (q15_t)0x7ead, (q15_t)0x7eaa, (q15_t)0x7ea6, (q15_t)0x7ea2, (q15_t)0x7e9f, + (q15_t)0x7e9b, (q15_t)0x7e97, (q15_t)0x7e94, (q15_t)0x7e90, (q15_t)0x7e8c, (q15_t)0x7e88, (q15_t)0x7e84, (q15_t)0x7e81, + (q15_t)0x7e7d, (q15_t)0x7e79, (q15_t)0x7e75, (q15_t)0x7e71, (q15_t)0x7e6d, (q15_t)0x7e69, (q15_t)0x7e65, (q15_t)0x7e61, + (q15_t)0x7e5d, (q15_t)0x7e59, (q15_t)0x7e55, (q15_t)0x7e51, (q15_t)0x7e4d, (q15_t)0x7e49, (q15_t)0x7e45, (q15_t)0x7e41, + (q15_t)0x7e3d, (q15_t)0x7e39, (q15_t)0x7e34, (q15_t)0x7e30, (q15_t)0x7e2c, (q15_t)0x7e28, (q15_t)0x7e24, (q15_t)0x7e1f, + (q15_t)0x7e1b, (q15_t)0x7e17, (q15_t)0x7e12, (q15_t)0x7e0e, (q15_t)0x7e0a, (q15_t)0x7e05, (q15_t)0x7e01, (q15_t)0x7dfc, + (q15_t)0x7df8, (q15_t)0x7df3, (q15_t)0x7def, (q15_t)0x7dea, (q15_t)0x7de6, (q15_t)0x7de1, (q15_t)0x7ddd, (q15_t)0x7dd8, + (q15_t)0x7dd4, (q15_t)0x7dcf, (q15_t)0x7dca, (q15_t)0x7dc6, (q15_t)0x7dc1, (q15_t)0x7dbc, (q15_t)0x7db8, (q15_t)0x7db3, + (q15_t)0x7dae, (q15_t)0x7da9, (q15_t)0x7da5, (q15_t)0x7da0, (q15_t)0x7d9b, (q15_t)0x7d96, (q15_t)0x7d91, (q15_t)0x7d8c, + (q15_t)0x7d87, (q15_t)0x7d82, (q15_t)0x7d7e, (q15_t)0x7d79, (q15_t)0x7d74, (q15_t)0x7d6f, (q15_t)0x7d6a, (q15_t)0x7d65, + (q15_t)0x7d60, (q15_t)0x7d5a, (q15_t)0x7d55, (q15_t)0x7d50, (q15_t)0x7d4b, (q15_t)0x7d46, (q15_t)0x7d41, (q15_t)0x7d3c, + (q15_t)0x7d36, (q15_t)0x7d31, (q15_t)0x7d2c, (q15_t)0x7d27, (q15_t)0x7d21, (q15_t)0x7d1c, (q15_t)0x7d17, (q15_t)0x7d11, + (q15_t)0x7d0c, (q15_t)0x7d07, (q15_t)0x7d01, (q15_t)0x7cfc, (q15_t)0x7cf6, (q15_t)0x7cf1, (q15_t)0x7cec, (q15_t)0x7ce6, + (q15_t)0x7ce1, (q15_t)0x7cdb, (q15_t)0x7cd5, (q15_t)0x7cd0, (q15_t)0x7cca, (q15_t)0x7cc5, (q15_t)0x7cbf, (q15_t)0x7cb9, + (q15_t)0x7cb4, (q15_t)0x7cae, (q15_t)0x7ca8, (q15_t)0x7ca3, (q15_t)0x7c9d, (q15_t)0x7c97, (q15_t)0x7c91, (q15_t)0x7c8c, + (q15_t)0x7c86, (q15_t)0x7c80, (q15_t)0x7c7a, (q15_t)0x7c74, (q15_t)0x7c6e, (q15_t)0x7c69, (q15_t)0x7c63, (q15_t)0x7c5d, + (q15_t)0x7c57, (q15_t)0x7c51, (q15_t)0x7c4b, (q15_t)0x7c45, (q15_t)0x7c3f, (q15_t)0x7c39, (q15_t)0x7c33, (q15_t)0x7c2d, + (q15_t)0x7c26, (q15_t)0x7c20, (q15_t)0x7c1a, (q15_t)0x7c14, (q15_t)0x7c0e, (q15_t)0x7c08, (q15_t)0x7c01, (q15_t)0x7bfb, + (q15_t)0x7bf5, (q15_t)0x7bef, (q15_t)0x7be8, (q15_t)0x7be2, (q15_t)0x7bdc, (q15_t)0x7bd5, (q15_t)0x7bcf, (q15_t)0x7bc9, + (q15_t)0x7bc2, (q15_t)0x7bbc, (q15_t)0x7bb5, (q15_t)0x7baf, (q15_t)0x7ba8, (q15_t)0x7ba2, (q15_t)0x7b9b, (q15_t)0x7b95, + (q15_t)0x7b8e, (q15_t)0x7b88, (q15_t)0x7b81, (q15_t)0x7b7a, (q15_t)0x7b74, (q15_t)0x7b6d, (q15_t)0x7b67, (q15_t)0x7b60, + (q15_t)0x7b59, (q15_t)0x7b52, (q15_t)0x7b4c, (q15_t)0x7b45, (q15_t)0x7b3e, (q15_t)0x7b37, (q15_t)0x7b31, (q15_t)0x7b2a, + (q15_t)0x7b23, (q15_t)0x7b1c, (q15_t)0x7b15, (q15_t)0x7b0e, (q15_t)0x7b07, (q15_t)0x7b00, (q15_t)0x7af9, (q15_t)0x7af2, + (q15_t)0x7aeb, (q15_t)0x7ae4, (q15_t)0x7add, (q15_t)0x7ad6, (q15_t)0x7acf, (q15_t)0x7ac8, (q15_t)0x7ac1, (q15_t)0x7aba, + (q15_t)0x7ab3, (q15_t)0x7aac, (q15_t)0x7aa4, (q15_t)0x7a9d, (q15_t)0x7a96, (q15_t)0x7a8f, (q15_t)0x7a87, (q15_t)0x7a80, + (q15_t)0x7a79, (q15_t)0x7a72, (q15_t)0x7a6a, (q15_t)0x7a63, (q15_t)0x7a5c, (q15_t)0x7a54, (q15_t)0x7a4d, (q15_t)0x7a45, + (q15_t)0x7a3e, (q15_t)0x7a36, (q15_t)0x7a2f, (q15_t)0x7a27, (q15_t)0x7a20, (q15_t)0x7a18, (q15_t)0x7a11, (q15_t)0x7a09, + (q15_t)0x7a02, (q15_t)0x79fa, (q15_t)0x79f2, (q15_t)0x79eb, (q15_t)0x79e3, (q15_t)0x79db, (q15_t)0x79d4, (q15_t)0x79cc, + (q15_t)0x79c4, (q15_t)0x79bc, (q15_t)0x79b5, (q15_t)0x79ad, (q15_t)0x79a5, (q15_t)0x799d, (q15_t)0x7995, (q15_t)0x798e, + (q15_t)0x7986, (q15_t)0x797e, (q15_t)0x7976, (q15_t)0x796e, (q15_t)0x7966, (q15_t)0x795e, (q15_t)0x7956, (q15_t)0x794e, + (q15_t)0x7946, (q15_t)0x793e, (q15_t)0x7936, (q15_t)0x792e, (q15_t)0x7926, (q15_t)0x791e, (q15_t)0x7915, (q15_t)0x790d, + (q15_t)0x7905, (q15_t)0x78fd, (q15_t)0x78f5, (q15_t)0x78ec, (q15_t)0x78e4, (q15_t)0x78dc, (q15_t)0x78d4, (q15_t)0x78cb, + (q15_t)0x78c3, (q15_t)0x78bb, (q15_t)0x78b2, (q15_t)0x78aa, (q15_t)0x78a2, (q15_t)0x7899, (q15_t)0x7891, (q15_t)0x7888, + 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(q15_t)0x1098, (q15_t)0x107f, + (q15_t)0x1066, (q15_t)0x104d, (q15_t)0x1034, (q15_t)0x101b, (q15_t)0x1002, (q15_t)0xfe9, (q15_t)0xfd0, (q15_t)0xfb7, + (q15_t)0xf9e, (q15_t)0xf85, (q15_t)0xf6c, (q15_t)0xf53, (q15_t)0xf3a, (q15_t)0xf21, (q15_t)0xf08, (q15_t)0xef0, + (q15_t)0xed7, (q15_t)0xebe, (q15_t)0xea5, (q15_t)0xe8c, (q15_t)0xe73, (q15_t)0xe5a, (q15_t)0xe41, (q15_t)0xe28, + (q15_t)0xe0f, (q15_t)0xdf6, (q15_t)0xddd, (q15_t)0xdc4, (q15_t)0xdab, (q15_t)0xd92, (q15_t)0xd79, (q15_t)0xd60, + (q15_t)0xd47, (q15_t)0xd2e, (q15_t)0xd15, (q15_t)0xcfc, (q15_t)0xce3, (q15_t)0xcca, (q15_t)0xcb1, (q15_t)0xc98, + (q15_t)0xc7f, (q15_t)0xc66, (q15_t)0xc4d, (q15_t)0xc34, (q15_t)0xc1b, (q15_t)0xc02, (q15_t)0xbe9, (q15_t)0xbd0, + (q15_t)0xbb7, (q15_t)0xb9e, (q15_t)0xb85, (q15_t)0xb6c, (q15_t)0xb53, (q15_t)0xb3a, (q15_t)0xb20, (q15_t)0xb07, + (q15_t)0xaee, (q15_t)0xad5, (q15_t)0xabc, (q15_t)0xaa3, (q15_t)0xa8a, (q15_t)0xa71, (q15_t)0xa58, (q15_t)0xa3f, + (q15_t)0xa26, (q15_t)0xa0d, (q15_t)0x9f4, (q15_t)0x9db, (q15_t)0x9c2, (q15_t)0x9a9, (q15_t)0x990, (q15_t)0x977, + (q15_t)0x95e, (q15_t)0x944, (q15_t)0x92b, (q15_t)0x912, (q15_t)0x8f9, (q15_t)0x8e0, (q15_t)0x8c7, (q15_t)0x8ae, + (q15_t)0x895, (q15_t)0x87c, (q15_t)0x863, (q15_t)0x84a, (q15_t)0x831, (q15_t)0x818, (q15_t)0x7fe, (q15_t)0x7e5, + (q15_t)0x7cc, (q15_t)0x7b3, (q15_t)0x79a, (q15_t)0x781, (q15_t)0x768, (q15_t)0x74f, (q15_t)0x736, (q15_t)0x71d, + (q15_t)0x704, (q15_t)0x6ea, (q15_t)0x6d1, (q15_t)0x6b8, (q15_t)0x69f, (q15_t)0x686, (q15_t)0x66d, (q15_t)0x654, + (q15_t)0x63b, (q15_t)0x622, (q15_t)0x609, (q15_t)0x5ef, (q15_t)0x5d6, (q15_t)0x5bd, (q15_t)0x5a4, (q15_t)0x58b, + (q15_t)0x572, (q15_t)0x559, (q15_t)0x540, (q15_t)0x527, (q15_t)0x50d, (q15_t)0x4f4, (q15_t)0x4db, (q15_t)0x4c2, + (q15_t)0x4a9, (q15_t)0x490, (q15_t)0x477, (q15_t)0x45e, (q15_t)0x445, (q15_t)0x42b, (q15_t)0x412, (q15_t)0x3f9, + (q15_t)0x3e0, (q15_t)0x3c7, (q15_t)0x3ae, (q15_t)0x395, (q15_t)0x37c, (q15_t)0x362, (q15_t)0x349, (q15_t)0x330, + (q15_t)0x317, (q15_t)0x2fe, (q15_t)0x2e5, (q15_t)0x2cc, (q15_t)0x2b3, (q15_t)0x299, (q15_t)0x280, (q15_t)0x267, + (q15_t)0x24e, (q15_t)0x235, (q15_t)0x21c, (q15_t)0x203, (q15_t)0x1ea, (q15_t)0x1d0, (q15_t)0x1b7, (q15_t)0x19e, + (q15_t)0x185, (q15_t)0x16c, (q15_t)0x153, (q15_t)0x13a, (q15_t)0x121, (q15_t)0x107, (q15_t)0xee, (q15_t)0xd5, + (q15_t)0xbc, (q15_t)0xa3, (q15_t)0x8a, (q15_t)0x71, (q15_t)0x57, (q15_t)0x3e, (q15_t)0x25, (q15_t)0xc + +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + const q15_t __ALIGNED(4) WeightsQ15_8192[16384] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfffa, (q15_t)0x7fff, (q15_t)0xfff4, (q15_t)0x7fff, (q15_t)0xffee, + (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffe1, (q15_t)0x7fff, (q15_t)0xffdb, (q15_t)0x7fff, (q15_t)0xffd5, + (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc8, (q15_t)0x7fff, (q15_t)0xffc2, (q15_t)0x7fff, (q15_t)0xffbb, + (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffaf, (q15_t)0x7fff, (q15_t)0xffa9, (q15_t)0x7fff, (q15_t)0xffa2, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff96, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff89, + (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff7d, (q15_t)0x7fff, (q15_t)0xff76, (q15_t)0x7fff, (q15_t)0xff70, + (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff63, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff57, + (q15_t)0x7fff, (q15_t)0xff51, (q15_t)0x7fff, (q15_t)0xff4a, (q15_t)0x7fff, (q15_t)0xff44, (q15_t)0x7fff, (q15_t)0xff3e, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff31, (q15_t)0x7fff, (q15_t)0xff2b, (q15_t)0x7fff, (q15_t)0xff25, + (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff18, (q15_t)0x7fff, (q15_t)0xff12, (q15_t)0x7fff, (q15_t)0xff0b, + (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeff, (q15_t)0x7ffe, (q15_t)0xfef9, (q15_t)0x7ffe, (q15_t)0xfef2, + (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffe, (q15_t)0xfee6, (q15_t)0x7ffe, (q15_t)0xfedf, (q15_t)0x7ffe, (q15_t)0xfed9, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfecd, (q15_t)0x7ffe, (q15_t)0xfec6, (q15_t)0x7ffe, (q15_t)0xfec0, + (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfeb3, (q15_t)0x7ffe, (q15_t)0xfead, (q15_t)0x7ffe, (q15_t)0xfea7, + (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffe, (q15_t)0xfe9a, (q15_t)0x7ffd, (q15_t)0xfe94, (q15_t)0x7ffd, (q15_t)0xfe8e, + (q15_t)0x7ffd, (q15_t)0xfe88, (q15_t)0x7ffd, (q15_t)0xfe81, (q15_t)0x7ffd, (q15_t)0xfe7b, (q15_t)0x7ffd, (q15_t)0xfe75, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe68, (q15_t)0x7ffd, (q15_t)0xfe62, (q15_t)0x7ffd, (q15_t)0xfe5c, + (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffd, (q15_t)0xfe4f, (q15_t)0x7ffd, (q15_t)0xfe49, (q15_t)0x7ffc, (q15_t)0xfe42, + (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe36, (q15_t)0x7ffc, (q15_t)0xfe30, (q15_t)0x7ffc, (q15_t)0xfe29, + (q15_t)0x7ffc, (q15_t)0xfe23, (q15_t)0x7ffc, (q15_t)0xfe1d, (q15_t)0x7ffc, (q15_t)0xfe16, (q15_t)0x7ffc, (q15_t)0xfe10, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffc, (q15_t)0xfe04, (q15_t)0x7ffb, (q15_t)0xfdfd, (q15_t)0x7ffb, (q15_t)0xfdf7, + (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdea, (q15_t)0x7ffb, (q15_t)0xfde4, (q15_t)0x7ffb, (q15_t)0xfdde, + (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffb, (q15_t)0xfdd1, (q15_t)0x7ffb, (q15_t)0xfdcb, (q15_t)0x7ffb, (q15_t)0xfdc5, + (q15_t)0x7ffa, (q15_t)0xfdbe, (q15_t)0x7ffa, (q15_t)0xfdb8, (q15_t)0x7ffa, (q15_t)0xfdb2, (q15_t)0x7ffa, (q15_t)0xfdac, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ffa, (q15_t)0xfd9f, (q15_t)0x7ffa, (q15_t)0xfd99, (q15_t)0x7ffa, (q15_t)0xfd93, + (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd86, (q15_t)0x7ff9, (q15_t)0xfd80, (q15_t)0x7ff9, (q15_t)0xfd79, + (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff9, (q15_t)0xfd6d, (q15_t)0x7ff9, (q15_t)0xfd67, (q15_t)0x7ff9, (q15_t)0xfd60, + (q15_t)0x7ff8, (q15_t)0xfd5a, (q15_t)0x7ff8, (q15_t)0xfd54, (q15_t)0x7ff8, (q15_t)0xfd4d, (q15_t)0x7ff8, (q15_t)0xfd47, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff8, (q15_t)0xfd3b, (q15_t)0x7ff8, (q15_t)0xfd34, (q15_t)0x7ff8, (q15_t)0xfd2e, + (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd21, (q15_t)0x7ff7, (q15_t)0xfd1b, (q15_t)0x7ff7, (q15_t)0xfd15, + (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff7, (q15_t)0xfd08, (q15_t)0x7ff7, (q15_t)0xfd02, (q15_t)0x7ff6, (q15_t)0xfcfc, + (q15_t)0x7ff6, (q15_t)0xfcf5, (q15_t)0x7ff6, (q15_t)0xfcef, (q15_t)0x7ff6, (q15_t)0xfce9, (q15_t)0x7ff6, (q15_t)0xfce3, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcd6, (q15_t)0x7ff5, (q15_t)0xfcd0, (q15_t)0x7ff5, (q15_t)0xfcc9, + (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff5, (q15_t)0xfcbd, (q15_t)0x7ff5, (q15_t)0xfcb7, (q15_t)0x7ff5, (q15_t)0xfcb0, + (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfca4, (q15_t)0x7ff4, (q15_t)0xfc9e, (q15_t)0x7ff4, (q15_t)0xfc97, + (q15_t)0x7ff4, (q15_t)0xfc91, (q15_t)0x7ff4, (q15_t)0xfc8b, (q15_t)0x7ff3, (q15_t)0xfc84, (q15_t)0x7ff3, (q15_t)0xfc7e, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff3, (q15_t)0xfc72, (q15_t)0x7ff3, (q15_t)0xfc6b, (q15_t)0x7ff2, (q15_t)0xfc65, + (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc58, (q15_t)0x7ff2, (q15_t)0xfc52, (q15_t)0x7ff2, (q15_t)0xfc4c, + (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc3f, (q15_t)0x7ff1, (q15_t)0xfc39, (q15_t)0x7ff1, (q15_t)0xfc33, + (q15_t)0x7ff1, (q15_t)0xfc2c, (q15_t)0x7ff1, (q15_t)0xfc26, (q15_t)0x7ff0, (q15_t)0xfc20, (q15_t)0x7ff0, (q15_t)0xfc1a, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7ff0, (q15_t)0xfc0d, (q15_t)0x7ff0, (q15_t)0xfc07, (q15_t)0x7fef, (q15_t)0xfc01, + (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fef, (q15_t)0xfbf4, (q15_t)0x7fef, (q15_t)0xfbee, (q15_t)0x7fef, (q15_t)0xfbe7, + (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbdb, (q15_t)0x7fee, (q15_t)0xfbd5, (q15_t)0x7fee, (q15_t)0xfbce, + (q15_t)0x7fee, (q15_t)0xfbc8, (q15_t)0x7fed, (q15_t)0xfbc2, (q15_t)0x7fed, (q15_t)0xfbbb, (q15_t)0x7fed, (q15_t)0xfbb5, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fed, (q15_t)0xfba9, (q15_t)0x7fec, (q15_t)0xfba2, (q15_t)0x7fec, (q15_t)0xfb9c, + (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7fec, (q15_t)0xfb8f, (q15_t)0x7fec, (q15_t)0xfb89, (q15_t)0x7feb, (q15_t)0xfb83, + (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7feb, (q15_t)0xfb76, (q15_t)0x7feb, (q15_t)0xfb70, (q15_t)0x7fea, (q15_t)0xfb6a, + (q15_t)0x7fea, (q15_t)0xfb64, (q15_t)0x7fea, (q15_t)0xfb5d, (q15_t)0x7fea, (q15_t)0xfb57, (q15_t)0x7fea, (q15_t)0xfb51, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe9, (q15_t)0xfb44, (q15_t)0x7fe9, (q15_t)0xfb3e, (q15_t)0x7fe9, (q15_t)0xfb38, + (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe8, (q15_t)0xfb2b, (q15_t)0x7fe8, (q15_t)0xfb25, (q15_t)0x7fe8, (q15_t)0xfb1e, + (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe7, (q15_t)0xfb12, (q15_t)0x7fe7, (q15_t)0xfb0c, (q15_t)0x7fe7, (q15_t)0xfb05, + (q15_t)0x7fe6, (q15_t)0xfaff, (q15_t)0x7fe6, (q15_t)0xfaf9, (q15_t)0x7fe6, (q15_t)0xfaf3, (q15_t)0x7fe6, (q15_t)0xfaec, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe5, (q15_t)0xfae0, (q15_t)0x7fe5, (q15_t)0xfad9, (q15_t)0x7fe5, (q15_t)0xfad3, + (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe4, (q15_t)0xfac7, (q15_t)0x7fe4, (q15_t)0xfac0, (q15_t)0x7fe4, (q15_t)0xfaba, + (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe3, (q15_t)0xfaad, (q15_t)0x7fe3, (q15_t)0xfaa7, (q15_t)0x7fe3, (q15_t)0xfaa1, + (q15_t)0x7fe2, (q15_t)0xfa9b, (q15_t)0x7fe2, (q15_t)0xfa94, (q15_t)0x7fe2, (q15_t)0xfa8e, (q15_t)0x7fe2, (q15_t)0xfa88, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe1, (q15_t)0xfa7b, (q15_t)0x7fe1, (q15_t)0xfa75, (q15_t)0x7fe0, (q15_t)0xfa6f, + (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fe0, (q15_t)0xfa62, (q15_t)0x7fe0, (q15_t)0xfa5c, (q15_t)0x7fdf, (q15_t)0xfa56, + (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fdf, (q15_t)0xfa49, (q15_t)0x7fdf, (q15_t)0xfa43, (q15_t)0x7fde, (q15_t)0xfa3c, + (q15_t)0x7fde, (q15_t)0xfa36, (q15_t)0x7fde, (q15_t)0xfa30, (q15_t)0x7fdd, (q15_t)0xfa2a, (q15_t)0x7fdd, (q15_t)0xfa23, + (q15_t)0x7fdd, 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(q15_t)0x356, (q15_t)0x800c, (q15_t)0x350, (q15_t)0x800b, (q15_t)0x349, (q15_t)0x800b, (q15_t)0x343, (q15_t)0x800b, + (q15_t)0x33d, (q15_t)0x800b, (q15_t)0x337, (q15_t)0x800b, (q15_t)0x330, (q15_t)0x800b, (q15_t)0x32a, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x31d, (q15_t)0x800a, (q15_t)0x317, (q15_t)0x800a, (q15_t)0x311, (q15_t)0x800a, + (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x304, (q15_t)0x800a, (q15_t)0x2fe, (q15_t)0x8009, (q15_t)0x2f8, (q15_t)0x8009, + (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2eb, (q15_t)0x8009, (q15_t)0x2e5, (q15_t)0x8009, (q15_t)0x2df, (q15_t)0x8009, + (q15_t)0x2d8, (q15_t)0x8009, (q15_t)0x2d2, (q15_t)0x8008, (q15_t)0x2cc, (q15_t)0x8008, (q15_t)0x2c5, (q15_t)0x8008, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2b9, (q15_t)0x8008, (q15_t)0x2b3, (q15_t)0x8008, (q15_t)0x2ac, (q15_t)0x8008, + (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x2a0, (q15_t)0x8007, (q15_t)0x299, (q15_t)0x8007, (q15_t)0x293, (q15_t)0x8007, + (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x287, (q15_t)0x8007, (q15_t)0x280, (q15_t)0x8007, (q15_t)0x27a, (q15_t)0x8007, + (q15_t)0x274, (q15_t)0x8007, (q15_t)0x26d, (q15_t)0x8006, (q15_t)0x267, (q15_t)0x8006, (q15_t)0x261, (q15_t)0x8006, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x254, (q15_t)0x8006, (q15_t)0x24e, (q15_t)0x8006, (q15_t)0x248, (q15_t)0x8006, + (q15_t)0x242, (q15_t)0x8006, (q15_t)0x23b, (q15_t)0x8005, (q15_t)0x235, (q15_t)0x8005, (q15_t)0x22f, (q15_t)0x8005, + (q15_t)0x228, (q15_t)0x8005, (q15_t)0x222, (q15_t)0x8005, (q15_t)0x21c, (q15_t)0x8005, (q15_t)0x216, (q15_t)0x8005, + (q15_t)0x20f, (q15_t)0x8005, (q15_t)0x209, (q15_t)0x8005, (q15_t)0x203, (q15_t)0x8005, (q15_t)0x1fc, (q15_t)0x8004, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1f0, (q15_t)0x8004, (q15_t)0x1ea, (q15_t)0x8004, (q15_t)0x1e3, (q15_t)0x8004, + (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1d7, (q15_t)0x8004, (q15_t)0x1d0, (q15_t)0x8004, (q15_t)0x1ca, (q15_t)0x8004, + (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1be, (q15_t)0x8004, (q15_t)0x1b7, (q15_t)0x8003, (q15_t)0x1b1, (q15_t)0x8003, + (q15_t)0x1ab, (q15_t)0x8003, (q15_t)0x1a4, (q15_t)0x8003, (q15_t)0x19e, (q15_t)0x8003, (q15_t)0x198, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x18b, (q15_t)0x8003, (q15_t)0x185, (q15_t)0x8003, (q15_t)0x17f, (q15_t)0x8003, + (q15_t)0x178, (q15_t)0x8003, (q15_t)0x172, (q15_t)0x8003, (q15_t)0x16c, (q15_t)0x8003, (q15_t)0x166, (q15_t)0x8002, + (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x159, (q15_t)0x8002, (q15_t)0x153, (q15_t)0x8002, (q15_t)0x14d, (q15_t)0x8002, + (q15_t)0x146, (q15_t)0x8002, (q15_t)0x140, (q15_t)0x8002, (q15_t)0x13a, (q15_t)0x8002, (q15_t)0x133, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x127, (q15_t)0x8002, (q15_t)0x121, (q15_t)0x8002, (q15_t)0x11a, (q15_t)0x8002, + (q15_t)0x114, (q15_t)0x8002, (q15_t)0x10e, (q15_t)0x8002, (q15_t)0x107, (q15_t)0x8002, (q15_t)0x101, (q15_t)0x8002, + (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xf5, (q15_t)0x8001, (q15_t)0xee, (q15_t)0x8001, (q15_t)0xe8, (q15_t)0x8001, + (q15_t)0xe2, (q15_t)0x8001, (q15_t)0xdb, (q15_t)0x8001, (q15_t)0xd5, (q15_t)0x8001, (q15_t)0xcf, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xc2, (q15_t)0x8001, (q15_t)0xbc, (q15_t)0x8001, (q15_t)0xb6, (q15_t)0x8001, + (q15_t)0xaf, (q15_t)0x8001, (q15_t)0xa9, (q15_t)0x8001, (q15_t)0xa3, (q15_t)0x8001, (q15_t)0x9d, (q15_t)0x8001, + (q15_t)0x96, (q15_t)0x8001, (q15_t)0x90, (q15_t)0x8001, (q15_t)0x8a, (q15_t)0x8001, (q15_t)0x83, (q15_t)0x8001, + (q15_t)0x7d, (q15_t)0x8001, (q15_t)0x77, (q15_t)0x8001, (q15_t)0x71, (q15_t)0x8001, (q15_t)0x6a, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x5e, (q15_t)0x8001, (q15_t)0x57, (q15_t)0x8001, (q15_t)0x51, (q15_t)0x8001, + (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x45, (q15_t)0x8001, (q15_t)0x3e, (q15_t)0x8001, (q15_t)0x38, (q15_t)0x8001, + (q15_t)0x32, (q15_t)0x8001, (q15_t)0x2b, (q15_t)0x8001, (q15_t)0x25, (q15_t)0x8001, (q15_t)0x1f, (q15_t)0x8001, + (q15_t)0x19, (q15_t)0x8001, (q15_t)0x12, (q15_t)0x8001, (q15_t)0xc, (q15_t)0x8001, (q15_t)0x6, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_8192[8192] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, + (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, + (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, + (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, + (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, + (q15_t)0x7ff6, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, + (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, + (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, + (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff0, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, + (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fed, + (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7feb, + (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fe9, + (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, + (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, + (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, + (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe1, + (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdf, + (q15_t)0x7fdf, (q15_t)0x7fdf, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fdd, (q15_t)0x7fdd, + (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, + (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd8, (q15_t)0x7fd8, + (q15_t)0x7fd8, (q15_t)0x7fd8, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd6, (q15_t)0x7fd6, + (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd3, (q15_t)0x7fd3, + (q15_t)0x7fd3, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd0, + (q15_t)0x7fd0, (q15_t)0x7fd0, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fce, (q15_t)0x7fce, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcb, (q15_t)0x7fcb, + (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc8, (q15_t)0x7fc8, + (q15_t)0x7fc8, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc6, (q15_t)0x7fc5, (q15_t)0x7fc5, + (q15_t)0x7fc5, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc3, (q15_t)0x7fc3, (q15_t)0x7fc2, (q15_t)0x7fc2, + (q15_t)0x7fc2, (q15_t)0x7fc1, (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fbf, (q15_t)0x7fbf, + (q15_t)0x7fbf, (q15_t)0x7fbe, (q15_t)0x7fbe, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbc, (q15_t)0x7fbc, + (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fba, (q15_t)0x7fba, (q15_t)0x7fb9, (q15_t)0x7fb9, (q15_t)0x7fb8, + (q15_t)0x7fb8, (q15_t)0x7fb8, (q15_t)0x7fb7, (q15_t)0x7fb7, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb5, + (q15_t)0x7fb5, (q15_t)0x7fb4, (q15_t)0x7fb4, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb2, (q15_t)0x7fb2, + (q15_t)0x7fb1, (q15_t)0x7fb1, (q15_t)0x7fb0, (q15_t)0x7fb0, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7fae, + (q15_t)0x7fae, (q15_t)0x7fad, (q15_t)0x7fad, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fab, (q15_t)0x7fab, + (q15_t)0x7faa, (q15_t)0x7faa, (q15_t)0x7fa9, (q15_t)0x7fa9, (q15_t)0x7fa8, (q15_t)0x7fa8, (q15_t)0x7fa7, (q15_t)0x7fa7, + (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa6, 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(q15_t)0xe50, + (q15_t)0xe4a, (q15_t)0xe44, (q15_t)0xe3e, (q15_t)0xe37, (q15_t)0xe31, (q15_t)0xe2b, (q15_t)0xe25, (q15_t)0xe1e, + (q15_t)0xe18, (q15_t)0xe12, (q15_t)0xe0c, (q15_t)0xe05, (q15_t)0xdff, (q15_t)0xdf9, (q15_t)0xdf3, (q15_t)0xdec, + (q15_t)0xde6, (q15_t)0xde0, (q15_t)0xdda, (q15_t)0xdd3, (q15_t)0xdcd, (q15_t)0xdc7, (q15_t)0xdc1, (q15_t)0xdba, + (q15_t)0xdb4, (q15_t)0xdae, (q15_t)0xda8, (q15_t)0xda1, (q15_t)0xd9b, (q15_t)0xd95, (q15_t)0xd8f, (q15_t)0xd88, + (q15_t)0xd82, (q15_t)0xd7c, (q15_t)0xd76, (q15_t)0xd6f, (q15_t)0xd69, (q15_t)0xd63, (q15_t)0xd5d, (q15_t)0xd56, + (q15_t)0xd50, (q15_t)0xd4a, (q15_t)0xd44, (q15_t)0xd3d, (q15_t)0xd37, (q15_t)0xd31, (q15_t)0xd2b, (q15_t)0xd24, + (q15_t)0xd1e, (q15_t)0xd18, (q15_t)0xd12, (q15_t)0xd0b, (q15_t)0xd05, (q15_t)0xcff, (q15_t)0xcf9, (q15_t)0xcf2, + (q15_t)0xcec, (q15_t)0xce6, (q15_t)0xce0, (q15_t)0xcd9, (q15_t)0xcd3, (q15_t)0xccd, (q15_t)0xcc7, (q15_t)0xcc0, + (q15_t)0xcba, (q15_t)0xcb4, (q15_t)0xcae, (q15_t)0xca7, (q15_t)0xca1, (q15_t)0xc9b, (q15_t)0xc95, (q15_t)0xc8e, + (q15_t)0xc88, (q15_t)0xc82, (q15_t)0xc7c, (q15_t)0xc75, (q15_t)0xc6f, (q15_t)0xc69, (q15_t)0xc63, (q15_t)0xc5c, + (q15_t)0xc56, (q15_t)0xc50, (q15_t)0xc4a, (q15_t)0xc43, (q15_t)0xc3d, (q15_t)0xc37, (q15_t)0xc31, (q15_t)0xc2a, + (q15_t)0xc24, (q15_t)0xc1e, (q15_t)0xc18, (q15_t)0xc11, (q15_t)0xc0b, (q15_t)0xc05, (q15_t)0xbff, (q15_t)0xbf8, + (q15_t)0xbf2, (q15_t)0xbec, (q15_t)0xbe6, (q15_t)0xbdf, (q15_t)0xbd9, (q15_t)0xbd3, (q15_t)0xbcd, (q15_t)0xbc6, + (q15_t)0xbc0, (q15_t)0xbba, (q15_t)0xbb4, (q15_t)0xbad, (q15_t)0xba7, (q15_t)0xba1, (q15_t)0xb9b, (q15_t)0xb94, + (q15_t)0xb8e, (q15_t)0xb88, (q15_t)0xb81, (q15_t)0xb7b, (q15_t)0xb75, (q15_t)0xb6f, (q15_t)0xb68, (q15_t)0xb62, + (q15_t)0xb5c, (q15_t)0xb56, (q15_t)0xb4f, (q15_t)0xb49, (q15_t)0xb43, (q15_t)0xb3d, (q15_t)0xb36, (q15_t)0xb30, + (q15_t)0xb2a, (q15_t)0xb24, (q15_t)0xb1d, (q15_t)0xb17, (q15_t)0xb11, (q15_t)0xb0b, (q15_t)0xb04, (q15_t)0xafe, + (q15_t)0xaf8, (q15_t)0xaf2, (q15_t)0xaeb, (q15_t)0xae5, (q15_t)0xadf, (q15_t)0xad8, (q15_t)0xad2, (q15_t)0xacc, + (q15_t)0xac6, (q15_t)0xabf, (q15_t)0xab9, (q15_t)0xab3, (q15_t)0xaad, (q15_t)0xaa6, (q15_t)0xaa0, (q15_t)0xa9a, + (q15_t)0xa94, (q15_t)0xa8d, (q15_t)0xa87, (q15_t)0xa81, (q15_t)0xa7b, (q15_t)0xa74, (q15_t)0xa6e, (q15_t)0xa68, + (q15_t)0xa62, (q15_t)0xa5b, (q15_t)0xa55, (q15_t)0xa4f, (q15_t)0xa48, (q15_t)0xa42, (q15_t)0xa3c, (q15_t)0xa36, + (q15_t)0xa2f, (q15_t)0xa29, (q15_t)0xa23, (q15_t)0xa1d, (q15_t)0xa16, (q15_t)0xa10, (q15_t)0xa0a, (q15_t)0xa04, + (q15_t)0x9fd, (q15_t)0x9f7, (q15_t)0x9f1, (q15_t)0x9eb, (q15_t)0x9e4, (q15_t)0x9de, (q15_t)0x9d8, (q15_t)0x9d1, + (q15_t)0x9cb, (q15_t)0x9c5, (q15_t)0x9bf, (q15_t)0x9b8, (q15_t)0x9b2, (q15_t)0x9ac, (q15_t)0x9a6, (q15_t)0x99f, + (q15_t)0x999, (q15_t)0x993, (q15_t)0x98d, (q15_t)0x986, (q15_t)0x980, (q15_t)0x97a, (q15_t)0x973, (q15_t)0x96d, + (q15_t)0x967, (q15_t)0x961, (q15_t)0x95a, (q15_t)0x954, (q15_t)0x94e, (q15_t)0x948, (q15_t)0x941, (q15_t)0x93b, + (q15_t)0x935, (q15_t)0x92f, (q15_t)0x928, (q15_t)0x922, (q15_t)0x91c, (q15_t)0x915, (q15_t)0x90f, (q15_t)0x909, + (q15_t)0x903, (q15_t)0x8fc, (q15_t)0x8f6, (q15_t)0x8f0, (q15_t)0x8ea, (q15_t)0x8e3, (q15_t)0x8dd, (q15_t)0x8d7, + (q15_t)0x8d1, (q15_t)0x8ca, (q15_t)0x8c4, (q15_t)0x8be, (q15_t)0x8b7, (q15_t)0x8b1, (q15_t)0x8ab, (q15_t)0x8a5, + (q15_t)0x89e, (q15_t)0x898, (q15_t)0x892, (q15_t)0x88c, (q15_t)0x885, (q15_t)0x87f, (q15_t)0x879, (q15_t)0x872, + (q15_t)0x86c, (q15_t)0x866, (q15_t)0x860, (q15_t)0x859, (q15_t)0x853, (q15_t)0x84d, (q15_t)0x847, (q15_t)0x840, + (q15_t)0x83a, (q15_t)0x834, (q15_t)0x82e, (q15_t)0x827, (q15_t)0x821, (q15_t)0x81b, (q15_t)0x814, (q15_t)0x80e, + (q15_t)0x808, (q15_t)0x802, (q15_t)0x7fb, (q15_t)0x7f5, (q15_t)0x7ef, (q15_t)0x7e9, (q15_t)0x7e2, (q15_t)0x7dc, + (q15_t)0x7d6, (q15_t)0x7cf, (q15_t)0x7c9, (q15_t)0x7c3, (q15_t)0x7bd, (q15_t)0x7b6, (q15_t)0x7b0, (q15_t)0x7aa, + (q15_t)0x7a4, (q15_t)0x79d, (q15_t)0x797, (q15_t)0x791, (q15_t)0x78a, (q15_t)0x784, (q15_t)0x77e, (q15_t)0x778, + (q15_t)0x771, (q15_t)0x76b, (q15_t)0x765, (q15_t)0x75f, (q15_t)0x758, (q15_t)0x752, (q15_t)0x74c, (q15_t)0x745, + (q15_t)0x73f, (q15_t)0x739, (q15_t)0x733, (q15_t)0x72c, (q15_t)0x726, (q15_t)0x720, (q15_t)0x71a, (q15_t)0x713, + (q15_t)0x70d, (q15_t)0x707, (q15_t)0x700, (q15_t)0x6fa, (q15_t)0x6f4, (q15_t)0x6ee, (q15_t)0x6e7, (q15_t)0x6e1, + (q15_t)0x6db, (q15_t)0x6d5, (q15_t)0x6ce, (q15_t)0x6c8, (q15_t)0x6c2, (q15_t)0x6bb, (q15_t)0x6b5, (q15_t)0x6af, + (q15_t)0x6a9, (q15_t)0x6a2, (q15_t)0x69c, (q15_t)0x696, (q15_t)0x690, (q15_t)0x689, (q15_t)0x683, (q15_t)0x67d, + (q15_t)0x676, (q15_t)0x670, (q15_t)0x66a, (q15_t)0x664, (q15_t)0x65d, (q15_t)0x657, (q15_t)0x651, (q15_t)0x64a, + (q15_t)0x644, (q15_t)0x63e, (q15_t)0x638, (q15_t)0x631, (q15_t)0x62b, (q15_t)0x625, (q15_t)0x61f, (q15_t)0x618, + (q15_t)0x612, (q15_t)0x60c, (q15_t)0x605, (q15_t)0x5ff, (q15_t)0x5f9, (q15_t)0x5f3, (q15_t)0x5ec, (q15_t)0x5e6, + (q15_t)0x5e0, (q15_t)0x5da, (q15_t)0x5d3, (q15_t)0x5cd, (q15_t)0x5c7, (q15_t)0x5c0, (q15_t)0x5ba, (q15_t)0x5b4, + (q15_t)0x5ae, (q15_t)0x5a7, (q15_t)0x5a1, (q15_t)0x59b, (q15_t)0x594, (q15_t)0x58e, (q15_t)0x588, (q15_t)0x582, + (q15_t)0x57b, (q15_t)0x575, (q15_t)0x56f, (q15_t)0x569, (q15_t)0x562, (q15_t)0x55c, (q15_t)0x556, (q15_t)0x54f, + (q15_t)0x549, (q15_t)0x543, (q15_t)0x53d, (q15_t)0x536, (q15_t)0x530, (q15_t)0x52a, (q15_t)0x523, (q15_t)0x51d, + (q15_t)0x517, (q15_t)0x511, (q15_t)0x50a, (q15_t)0x504, (q15_t)0x4fe, (q15_t)0x4f8, (q15_t)0x4f1, (q15_t)0x4eb, + (q15_t)0x4e5, (q15_t)0x4de, (q15_t)0x4d8, (q15_t)0x4d2, (q15_t)0x4cc, (q15_t)0x4c5, (q15_t)0x4bf, (q15_t)0x4b9, + (q15_t)0x4b2, (q15_t)0x4ac, (q15_t)0x4a6, (q15_t)0x4a0, (q15_t)0x499, (q15_t)0x493, (q15_t)0x48d, (q15_t)0x487, + (q15_t)0x480, (q15_t)0x47a, (q15_t)0x474, (q15_t)0x46d, (q15_t)0x467, (q15_t)0x461, (q15_t)0x45b, (q15_t)0x454, + (q15_t)0x44e, (q15_t)0x448, (q15_t)0x441, (q15_t)0x43b, (q15_t)0x435, (q15_t)0x42f, (q15_t)0x428, (q15_t)0x422, + (q15_t)0x41c, (q15_t)0x415, (q15_t)0x40f, (q15_t)0x409, (q15_t)0x403, (q15_t)0x3fc, (q15_t)0x3f6, (q15_t)0x3f0, + (q15_t)0x3ea, (q15_t)0x3e3, (q15_t)0x3dd, (q15_t)0x3d7, (q15_t)0x3d0, (q15_t)0x3ca, (q15_t)0x3c4, (q15_t)0x3be, + (q15_t)0x3b7, (q15_t)0x3b1, (q15_t)0x3ab, (q15_t)0x3a4, (q15_t)0x39e, (q15_t)0x398, (q15_t)0x392, (q15_t)0x38b, + (q15_t)0x385, (q15_t)0x37f, (q15_t)0x378, (q15_t)0x372, (q15_t)0x36c, (q15_t)0x366, (q15_t)0x35f, (q15_t)0x359, + (q15_t)0x353, (q15_t)0x34c, (q15_t)0x346, (q15_t)0x340, (q15_t)0x33a, (q15_t)0x333, (q15_t)0x32d, (q15_t)0x327, + (q15_t)0x321, (q15_t)0x31a, (q15_t)0x314, (q15_t)0x30e, (q15_t)0x307, (q15_t)0x301, (q15_t)0x2fb, (q15_t)0x2f5, + (q15_t)0x2ee, (q15_t)0x2e8, (q15_t)0x2e2, (q15_t)0x2db, (q15_t)0x2d5, (q15_t)0x2cf, (q15_t)0x2c9, (q15_t)0x2c2, + (q15_t)0x2bc, (q15_t)0x2b6, (q15_t)0x2af, (q15_t)0x2a9, (q15_t)0x2a3, (q15_t)0x29d, (q15_t)0x296, (q15_t)0x290, + (q15_t)0x28a, (q15_t)0x283, (q15_t)0x27d, (q15_t)0x277, (q15_t)0x271, (q15_t)0x26a, (q15_t)0x264, (q15_t)0x25e, + (q15_t)0x258, (q15_t)0x251, (q15_t)0x24b, (q15_t)0x245, (q15_t)0x23e, (q15_t)0x238, (q15_t)0x232, (q15_t)0x22c, + (q15_t)0x225, (q15_t)0x21f, (q15_t)0x219, (q15_t)0x212, (q15_t)0x20c, (q15_t)0x206, (q15_t)0x200, (q15_t)0x1f9, + (q15_t)0x1f3, (q15_t)0x1ed, (q15_t)0x1e6, (q15_t)0x1e0, (q15_t)0x1da, (q15_t)0x1d4, (q15_t)0x1cd, (q15_t)0x1c7, + (q15_t)0x1c1, (q15_t)0x1ba, (q15_t)0x1b4, (q15_t)0x1ae, (q15_t)0x1a8, (q15_t)0x1a1, (q15_t)0x19b, (q15_t)0x195, + (q15_t)0x18e, (q15_t)0x188, (q15_t)0x182, (q15_t)0x17c, (q15_t)0x175, (q15_t)0x16f, (q15_t)0x169, (q15_t)0x162, + (q15_t)0x15c, (q15_t)0x156, (q15_t)0x150, (q15_t)0x149, (q15_t)0x143, (q15_t)0x13d, (q15_t)0x137, (q15_t)0x130, + (q15_t)0x12a, (q15_t)0x124, (q15_t)0x11d, (q15_t)0x117, (q15_t)0x111, (q15_t)0x10b, (q15_t)0x104, (q15_t)0xfe, + (q15_t)0xf8, (q15_t)0xf1, (q15_t)0xeb, (q15_t)0xe5, (q15_t)0xdf, (q15_t)0xd8, (q15_t)0xd2, (q15_t)0xcc, + (q15_t)0xc5, (q15_t)0xbf, (q15_t)0xb9, (q15_t)0xb3, (q15_t)0xac, (q15_t)0xa6, (q15_t)0xa0, (q15_t)0x99, + (q15_t)0x93, (q15_t)0x8d, (q15_t)0x87, (q15_t)0x80, (q15_t)0x7a, (q15_t)0x74, (q15_t)0x6d, (q15_t)0x67, + (q15_t)0x61, (q15_t)0x5b, (q15_t)0x54, (q15_t)0x4e, (q15_t)0x48, (q15_t)0x41, (q15_t)0x3b, (q15_t)0x35, + (q15_t)0x2f, (q15_t)0x28, (q15_t)0x22, (q15_t)0x1c, (q15_t)0x15, (q15_t)0xf, (q15_t)0x9, (q15_t)0x3 +}; + #endif + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Convert the output to q31 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q31 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + const q31_t WeightsQ31_128[256] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f872bf3, (q31_t)0xf50497fb, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7dd6668f, (q31_t)0xe8922622, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7c894bde, (q31_t)0xe26cb01b, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7aef6323, (q31_t)0xdc597781, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x76d94989, (q31_t)0xd078ad9e, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x719e2cd2, (q31_t)0xc50d1149, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6b4af279, (q31_t)0xba32ca71, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x67bd0fbd, (q31_t)0xb5049368, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x63ef3290, (q31_t)0xb0049ab3, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x571deefa, (q31_t)0xa2386284, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x5269126e, (q31_t)0x9e0effc1, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4d8162c4, (q31_t)0x9a22042d, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4869e665, (q31_t)0x9673db94, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4325c135, (q31_t)0x9306cb04, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3db832a6, (q31_t)0x8fdcef66, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x382493b0, (q31_t)0x8cf83c30, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2c98fbba, (q31_t)0x88054677, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x26a82186, (q31_t)0x85fa1153, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x209f701c, (q31_t)0x843a1d70, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1a82a026, (q31_t)0x82c67f14, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x145576b1, (q31_t)0x81a01b6d, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x07d95b9e, (q31_t)0x803daa6a, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x01921d20, (q31_t)0x800277a6 +}; + const q31_t cos_factorsQ31_128[128] = { + (q31_t)0x7fff6216, (q31_t)0x7ffa72d1, (q31_t)0x7ff09478, (q31_t)0x7fe1c76b, (q31_t)0x7fce0c3e, (q31_t)0x7fb563b3, + (q31_t)0x7f97cebd, (q31_t)0x7f754e80, + (q31_t)0x7f4de451, (q31_t)0x7f2191b4, (q31_t)0x7ef05860, (q31_t)0x7eba3a39, (q31_t)0x7e7f3957, (q31_t)0x7e3f57ff, + (q31_t)0x7dfa98a8, (q31_t)0x7db0fdf8, + (q31_t)0x7d628ac6, (q31_t)0x7d0f4218, (q31_t)0x7cb72724, (q31_t)0x7c5a3d50, (q31_t)0x7bf88830, (q31_t)0x7b920b89, + (q31_t)0x7b26cb4f, (q31_t)0x7ab6cba4, + (q31_t)0x7a4210d8, (q31_t)0x79c89f6e, (q31_t)0x794a7c12, (q31_t)0x78c7aba2, (q31_t)0x78403329, (q31_t)0x77b417df, + (q31_t)0x77235f2d, (q31_t)0x768e0ea6, + (q31_t)0x75f42c0b, (q31_t)0x7555bd4c, (q31_t)0x74b2c884, (q31_t)0x740b53fb, (q31_t)0x735f6626, (q31_t)0x72af05a7, + (q31_t)0x71fa3949, (q31_t)0x71410805, + (q31_t)0x708378ff, (q31_t)0x6fc19385, (q31_t)0x6efb5f12, (q31_t)0x6e30e34a, (q31_t)0x6d6227fa, (q31_t)0x6c8f351c, + (q31_t)0x6bb812d1, (q31_t)0x6adcc964, + (q31_t)0x69fd614a, (q31_t)0x6919e320, (q31_t)0x683257ab, (q31_t)0x6746c7d8, (q31_t)0x66573cbb, (q31_t)0x6563bf92, + (q31_t)0x646c59bf, (q31_t)0x637114cc, + (q31_t)0x6271fa69, (q31_t)0x616f146c, (q31_t)0x60686ccf, (q31_t)0x5f5e0db3, (q31_t)0x5e50015d, (q31_t)0x5d3e5237, + (q31_t)0x5c290acc, (q31_t)0x5b1035cf, + (q31_t)0x59f3de12, (q31_t)0x58d40e8c, (q31_t)0x57b0d256, (q31_t)0x568a34a9, (q31_t)0x556040e2, (q31_t)0x5433027d, + (q31_t)0x53028518, (q31_t)0x51ced46e, + (q31_t)0x5097fc5e, (q31_t)0x4f5e08e3, (q31_t)0x4e210617, (q31_t)0x4ce10034, (q31_t)0x4b9e0390, (q31_t)0x4a581c9e, + (q31_t)0x490f57ee, (q31_t)0x47c3c22f, + (q31_t)0x46756828, (q31_t)0x452456bd, (q31_t)0x43d09aed, (q31_t)0x427a41d0, (q31_t)0x4121589b, (q31_t)0x3fc5ec98, + (q31_t)0x3e680b2c, (q31_t)0x3d07c1d6, + (q31_t)0x3ba51e29, (q31_t)0x3a402dd2, (q31_t)0x38d8fe93, (q31_t)0x376f9e46, (q31_t)0x36041ad9, (q31_t)0x34968250, + (q31_t)0x3326e2c3, (q31_t)0x31b54a5e, + (q31_t)0x3041c761, (q31_t)0x2ecc681e, (q31_t)0x2d553afc, (q31_t)0x2bdc4e6f, (q31_t)0x2a61b101, (q31_t)0x28e5714b, + (q31_t)0x27679df4, (q31_t)0x25e845b6, + (q31_t)0x24677758, (q31_t)0x22e541af, (q31_t)0x2161b3a0, (q31_t)0x1fdcdc1b, (q31_t)0x1e56ca1e, (q31_t)0x1ccf8cb3, + (q31_t)0x1b4732ef, (q31_t)0x19bdcbf3, + (q31_t)0x183366e9, (q31_t)0x16a81305, (q31_t)0x151bdf86, (q31_t)0x138edbb1, (q31_t)0x120116d5, (q31_t)0x1072a048, + (q31_t)0xee38766, (q31_t)0xd53db92, + (q31_t)0xbc3ac35, (q31_t)0xa3308bd, (q31_t)0x8a2009a, (q31_t)0x710a345, (q31_t)0x57f0035, (q31_t)0x3ed26e6, (q31_t)0x25b26d7, + (q31_t)0xc90f88 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + const q31_t WeightsQ31_512[1024] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff871a2, (q31_t)0xfd40565c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fed5791, (q31_t)0xfbae5e89, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fc85854, (q31_t)0xf88afe42, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f434563, (q31_t)0xf2482c8a, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7ee34636, (q31_t)0xef29b243, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7de8a670, (q31_t)0xe8f50273, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c71eaf9, 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(q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x588b9140, (q31_t)0xa3914da8, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56400758, (q31_t)0xa16c23e1, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x55153fd4, (q31_t)0xa05f01e1, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x53e73097, (q31_t)0x9f558fb0, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x518169a5, (q31_t)0x9d4de385, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x5049c999, (q31_t)0x9c4fbd93, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f0f1126, (q31_t)0x9b556f81, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4c9087b1, (q31_t)0x996c816f, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b4ccf4d, (q31_t)0x987df449, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a062fbd, (q31_t)0x979364b5, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48bcb599, (q31_t)0x96acdbbe, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47706d93, (q31_t)0x95ca6247, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x4621647d, (q31_t)0x94ec010b, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x44cfa740, (q31_t)0x9411c09e, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x437b42e1, (q31_t)0x933ba968, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x42244481, (q31_t)0x9269c3ac, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x40cab958, (q31_t)0x919c1781, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e10320d, (q31_t)0x900d8b69, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b4c18ba, (q31_t)0x8e904298, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x39e6975e, (q31_t)0x8dd829e4, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x387eda8e, (q31_t)0x8d2477d8, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3714f02a, (q31_t)0x8c753362, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35a8e625, (q31_t)0x8bca6343, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x343aca87, (q31_t)0x8b240e11, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x32caab6f, (q31_t)0x8a823a36, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x3158970e, (q31_t)0x89e4edef, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2e6ec792, (q31_t)0x88b80432, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2cf72939, (q31_t)0x88287256, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a02c7b8, (q31_t)0x8717304e, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x288621b9, (q31_t)0x86958aac, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2707ebc7, (q31_t)0x86189359, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x2588349d, (q31_t)0x85a04f28, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x24070b08, (q31_t)0x852cc2bb, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22847de0, (q31_t)0x84bdf286, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21009c0c, (q31_t)0x8453e2cf, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1df5163f, (q31_t)0x838e1507, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1c6d9053, (q31_t)0x83325e97, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x195b49ea, (q31_t)0x8289644b, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16451a83, (q31_t)0x81f3c2d7, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x132b7bf9, (q31_t)0x8171914e, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x119d8941, (q31_t)0x8137c8e6, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, + (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0f475bff, (q31_t)0x80ea4712, (q31_t)0x0ee38766, (q31_t)0x80de6e4c, (q31_t)0x0e7fa99e, (q31_t)0x80d2e3f2, + (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, (q31_t)0x0db7d376, (q31_t)0x80bcba9d, (q31_t)0x0d53db92, (q31_t)0x80b21baf, (q31_t)0x0cefdb76, (q31_t)0x80a7cb49, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0c27c389, (q31_t)0x8094162c, (q31_t)0x0bc3ac35, (q31_t)0x808ab180, (q31_t)0x0b5f8d9f, (q31_t)0x80819b74, + (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x0a973ba5, (q31_t)0x80705b50, (q31_t)0x0a3308bd, (q31_t)0x80683143, (q31_t)0x09cecf89, (q31_t)0x806055eb, + (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x09064b3a, (q31_t)0x80518b6b, (q31_t)0x08a2009a, (q31_t)0x804a9c4d, (q31_t)0x083db0a7, (q31_t)0x8043fbf6, + (q31_t)0x07d95b9e, (q31_t)0x803daa6a, (q31_t)0x077501be, (q31_t)0x8037a7ac, (q31_t)0x0710a345, (q31_t)0x8031f3c2, (q31_t)0x06ac406f, (q31_t)0x802c8ead, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x05e36ea9, (q31_t)0x8022b114, (q31_t)0x057f0035, (q31_t)0x801e3895, (q31_t)0x051a8e5c, (q31_t)0x801a0ef8, + (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x0451a177, (q31_t)0x8012a86f, (q31_t)0x03ed26e6, (q31_t)0x800f6b88, (q31_t)0x0388a9ea, (q31_t)0x800c7d8c, + (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x02bfa9a4, (q31_t)0x80078e5e, (q31_t)0x025b26d7, (q31_t)0x80058d2f, (q31_t)0x01f6a297, (q31_t)0x8003daf1, + (q31_t)0x01921d20, (q31_t)0x800277a6, (q31_t)0x012d96b1, (q31_t)0x8001634e, (q31_t)0x00c90f88, (q31_t)0x80009dea, (q31_t)0x006487e3, (q31_t)0x8000277a +}; + const q31_t cos_factorsQ31_512[512] = { + (q31_t)0x7ffff621, (q31_t)0x7fffa72c, (q31_t)0x7fff0943, (q31_t)0x7ffe1c65, (q31_t)0x7ffce093, (q31_t)0x7ffb55ce, + (q31_t)0x7ff97c18, (q31_t)0x7ff75370, + (q31_t)0x7ff4dbd9, (q31_t)0x7ff21553, (q31_t)0x7feeffe1, (q31_t)0x7feb9b85, (q31_t)0x7fe7e841, (q31_t)0x7fe3e616, + (q31_t)0x7fdf9508, (q31_t)0x7fdaf519, + (q31_t)0x7fd6064c, (q31_t)0x7fd0c8a3, (q31_t)0x7fcb3c23, (q31_t)0x7fc560cf, (q31_t)0x7fbf36aa, (q31_t)0x7fb8bdb8, + (q31_t)0x7fb1f5fc, (q31_t)0x7faadf7c, + (q31_t)0x7fa37a3c, (q31_t)0x7f9bc640, (q31_t)0x7f93c38c, (q31_t)0x7f8b7227, (q31_t)0x7f82d214, (q31_t)0x7f79e35a, + (q31_t)0x7f70a5fe, (q31_t)0x7f671a05, + (q31_t)0x7f5d3f75, (q31_t)0x7f531655, (q31_t)0x7f489eaa, (q31_t)0x7f3dd87c, (q31_t)0x7f32c3d1, (q31_t)0x7f2760af, + (q31_t)0x7f1baf1e, (q31_t)0x7f0faf25, + (q31_t)0x7f0360cb, (q31_t)0x7ef6c418, (q31_t)0x7ee9d914, (q31_t)0x7edc9fc6, (q31_t)0x7ecf1837, (q31_t)0x7ec14270, + (q31_t)0x7eb31e78, (q31_t)0x7ea4ac58, + (q31_t)0x7e95ec1a, (q31_t)0x7e86ddc6, (q31_t)0x7e778166, (q31_t)0x7e67d703, (q31_t)0x7e57dea7, (q31_t)0x7e47985b, + (q31_t)0x7e37042a, (q31_t)0x7e26221f, + (q31_t)0x7e14f242, (q31_t)0x7e0374a0, (q31_t)0x7df1a942, (q31_t)0x7ddf9034, (q31_t)0x7dcd2981, (q31_t)0x7dba7534, + (q31_t)0x7da77359, (q31_t)0x7d9423fc, + (q31_t)0x7d808728, (q31_t)0x7d6c9ce9, (q31_t)0x7d58654d, (q31_t)0x7d43e05e, (q31_t)0x7d2f0e2b, (q31_t)0x7d19eebf, + (q31_t)0x7d048228, (q31_t)0x7ceec873, + (q31_t)0x7cd8c1ae, (q31_t)0x7cc26de5, (q31_t)0x7cabcd28, (q31_t)0x7c94df83, (q31_t)0x7c7da505, (q31_t)0x7c661dbc, + (q31_t)0x7c4e49b7, (q31_t)0x7c362904, + (q31_t)0x7c1dbbb3, (q31_t)0x7c0501d2, (q31_t)0x7bebfb70, (q31_t)0x7bd2a89e, (q31_t)0x7bb9096b, (q31_t)0x7b9f1de6, + (q31_t)0x7b84e61f, (q31_t)0x7b6a6227, + (q31_t)0x7b4f920e, (q31_t)0x7b3475e5, (q31_t)0x7b190dbc, (q31_t)0x7afd59a4, (q31_t)0x7ae159ae, (q31_t)0x7ac50dec, + (q31_t)0x7aa8766f, (q31_t)0x7a8b9348, + (q31_t)0x7a6e648a, (q31_t)0x7a50ea47, (q31_t)0x7a332490, (q31_t)0x7a151378, (q31_t)0x79f6b711, (q31_t)0x79d80f6f, + (q31_t)0x79b91ca4, (q31_t)0x7999dec4, + (q31_t)0x797a55e0, (q31_t)0x795a820e, (q31_t)0x793a6361, (q31_t)0x7919f9ec, (q31_t)0x78f945c3, (q31_t)0x78d846fb, + (q31_t)0x78b6fda8, (q31_t)0x789569df, + (q31_t)0x78738bb3, (q31_t)0x7851633b, (q31_t)0x782ef08b, (q31_t)0x780c33b8, (q31_t)0x77e92cd9, (q31_t)0x77c5dc01, + (q31_t)0x77a24148, (q31_t)0x777e5cc3, + (q31_t)0x775a2e89, (q31_t)0x7735b6af, (q31_t)0x7710f54c, (q31_t)0x76ebea77, (q31_t)0x76c69647, (q31_t)0x76a0f8d2, + (q31_t)0x767b1231, (q31_t)0x7654e279, + (q31_t)0x762e69c4, (q31_t)0x7607a828, (q31_t)0x75e09dbd, (q31_t)0x75b94a9c, (q31_t)0x7591aedd, (q31_t)0x7569ca99, + (q31_t)0x75419de7, (q31_t)0x751928e0, + (q31_t)0x74f06b9e, (q31_t)0x74c7663a, (q31_t)0x749e18cd, (q31_t)0x74748371, (q31_t)0x744aa63f, (q31_t)0x74208150, + (q31_t)0x73f614c0, (q31_t)0x73cb60a8, + (q31_t)0x73a06522, (q31_t)0x73752249, (q31_t)0x73499838, (q31_t)0x731dc70a, (q31_t)0x72f1aed9, (q31_t)0x72c54fc1, + (q31_t)0x7298a9dd, (q31_t)0x726bbd48, + (q31_t)0x723e8a20, (q31_t)0x7211107e, (q31_t)0x71e35080, (q31_t)0x71b54a41, (q31_t)0x7186fdde, (q31_t)0x71586b74, + (q31_t)0x7129931f, (q31_t)0x70fa74fc, + (q31_t)0x70cb1128, (q31_t)0x709b67c0, (q31_t)0x706b78e3, (q31_t)0x703b44ad, (q31_t)0x700acb3c, (q31_t)0x6fda0cae, + (q31_t)0x6fa90921, (q31_t)0x6f77c0b3, + (q31_t)0x6f463383, (q31_t)0x6f1461b0, (q31_t)0x6ee24b57, (q31_t)0x6eaff099, (q31_t)0x6e7d5193, (q31_t)0x6e4a6e66, + (q31_t)0x6e174730, (q31_t)0x6de3dc11, + (q31_t)0x6db02d29, (q31_t)0x6d7c3a98, (q31_t)0x6d48047e, (q31_t)0x6d138afb, (q31_t)0x6cdece2f, (q31_t)0x6ca9ce3b, + (q31_t)0x6c748b3f, (q31_t)0x6c3f055d, + (q31_t)0x6c093cb6, (q31_t)0x6bd3316a, (q31_t)0x6b9ce39b, (q31_t)0x6b66536b, (q31_t)0x6b2f80fb, (q31_t)0x6af86c6c, + (q31_t)0x6ac115e2, (q31_t)0x6a897d7d, + (q31_t)0x6a51a361, (q31_t)0x6a1987b0, (q31_t)0x69e12a8c, (q31_t)0x69a88c19, (q31_t)0x696fac78, (q31_t)0x69368bce, + (q31_t)0x68fd2a3d, (q31_t)0x68c387e9, + (q31_t)0x6889a4f6, (q31_t)0x684f8186, (q31_t)0x68151dbe, (q31_t)0x67da79c3, (q31_t)0x679f95b7, (q31_t)0x676471c0, + (q31_t)0x67290e02, (q31_t)0x66ed6aa1, + (q31_t)0x66b187c3, (q31_t)0x6675658c, (q31_t)0x66390422, (q31_t)0x65fc63a9, (q31_t)0x65bf8447, (q31_t)0x65826622, + (q31_t)0x6545095f, (q31_t)0x65076e25, + (q31_t)0x64c99498, (q31_t)0x648b7ce0, (q31_t)0x644d2722, (q31_t)0x640e9386, (q31_t)0x63cfc231, (q31_t)0x6390b34a, + (q31_t)0x635166f9, (q31_t)0x6311dd64, + (q31_t)0x62d216b3, (q31_t)0x6292130c, (q31_t)0x6251d298, (q31_t)0x6211557e, (q31_t)0x61d09be5, (q31_t)0x618fa5f7, + (q31_t)0x614e73da, (q31_t)0x610d05b7, + (q31_t)0x60cb5bb7, (q31_t)0x60897601, (q31_t)0x604754bf, (q31_t)0x6004f819, (q31_t)0x5fc26038, (q31_t)0x5f7f8d46, + (q31_t)0x5f3c7f6b, (q31_t)0x5ef936d1, + (q31_t)0x5eb5b3a2, (q31_t)0x5e71f606, (q31_t)0x5e2dfe29, (q31_t)0x5de9cc33, (q31_t)0x5da5604f, (q31_t)0x5d60baa7, + (q31_t)0x5d1bdb65, (q31_t)0x5cd6c2b5, + (q31_t)0x5c9170bf, (q31_t)0x5c4be5b0, (q31_t)0x5c0621b2, (q31_t)0x5bc024f0, (q31_t)0x5b79ef96, (q31_t)0x5b3381ce, + (q31_t)0x5aecdbc5, (q31_t)0x5aa5fda5, + (q31_t)0x5a5ee79a, (q31_t)0x5a1799d1, (q31_t)0x59d01475, (q31_t)0x598857b2, (q31_t)0x594063b5, (q31_t)0x58f838a9, + (q31_t)0x58afd6bd, (q31_t)0x58673e1b, + (q31_t)0x581e6ef1, (q31_t)0x57d5696d, (q31_t)0x578c2dba, (q31_t)0x5742bc06, (q31_t)0x56f9147e, (q31_t)0x56af3750, + (q31_t)0x566524aa, (q31_t)0x561adcb9, + (q31_t)0x55d05faa, (q31_t)0x5585adad, (q31_t)0x553ac6ee, (q31_t)0x54efab9c, (q31_t)0x54a45be6, (q31_t)0x5458d7f9, + (q31_t)0x540d2005, (q31_t)0x53c13439, + (q31_t)0x537514c2, (q31_t)0x5328c1d0, (q31_t)0x52dc3b92, (q31_t)0x528f8238, (q31_t)0x524295f0, (q31_t)0x51f576ea, + (q31_t)0x51a82555, (q31_t)0x515aa162, + (q31_t)0x510ceb40, (q31_t)0x50bf031f, (q31_t)0x5070e92f, (q31_t)0x50229da1, (q31_t)0x4fd420a4, (q31_t)0x4f857269, + (q31_t)0x4f369320, (q31_t)0x4ee782fb, + (q31_t)0x4e984229, (q31_t)0x4e48d0dd, (q31_t)0x4df92f46, (q31_t)0x4da95d96, (q31_t)0x4d595bfe, (q31_t)0x4d092ab0, + (q31_t)0x4cb8c9dd, (q31_t)0x4c6839b7, + (q31_t)0x4c177a6e, (q31_t)0x4bc68c36, (q31_t)0x4b756f40, (q31_t)0x4b2423be, (q31_t)0x4ad2a9e2, (q31_t)0x4a8101de, + (q31_t)0x4a2f2be6, (q31_t)0x49dd282a, + (q31_t)0x498af6df, (q31_t)0x49389836, (q31_t)0x48e60c62, (q31_t)0x48935397, (q31_t)0x48406e08, (q31_t)0x47ed5be6, + (q31_t)0x479a1d67, (q31_t)0x4746b2bc, + (q31_t)0x46f31c1a, (q31_t)0x469f59b4, (q31_t)0x464b6bbe, (q31_t)0x45f7526b, (q31_t)0x45a30df0, (q31_t)0x454e9e80, + (q31_t)0x44fa0450, (q31_t)0x44a53f93, + (q31_t)0x4450507e, (q31_t)0x43fb3746, (q31_t)0x43a5f41e, (q31_t)0x4350873c, (q31_t)0x42faf0d4, (q31_t)0x42a5311b, + (q31_t)0x424f4845, (q31_t)0x41f93689, + (q31_t)0x41a2fc1a, (q31_t)0x414c992f, (q31_t)0x40f60dfb, (q31_t)0x409f5ab6, (q31_t)0x40487f94, (q31_t)0x3ff17cca, + (q31_t)0x3f9a5290, (q31_t)0x3f430119, + (q31_t)0x3eeb889c, (q31_t)0x3e93e950, (q31_t)0x3e3c2369, (q31_t)0x3de4371f, (q31_t)0x3d8c24a8, (q31_t)0x3d33ec39, + (q31_t)0x3cdb8e09, (q31_t)0x3c830a50, + (q31_t)0x3c2a6142, (q31_t)0x3bd19318, (q31_t)0x3b78a007, (q31_t)0x3b1f8848, (q31_t)0x3ac64c0f, (q31_t)0x3a6ceb96, + (q31_t)0x3a136712, (q31_t)0x39b9bebc, + (q31_t)0x395ff2c9, (q31_t)0x39060373, (q31_t)0x38abf0ef, (q31_t)0x3851bb77, (q31_t)0x37f76341, (q31_t)0x379ce885, + (q31_t)0x37424b7b, (q31_t)0x36e78c5b, + (q31_t)0x368cab5c, (q31_t)0x3631a8b8, (q31_t)0x35d684a6, (q31_t)0x357b3f5d, (q31_t)0x351fd918, (q31_t)0x34c4520d, + (q31_t)0x3468aa76, (q31_t)0x340ce28b, + (q31_t)0x33b0fa84, (q31_t)0x3354f29b, (q31_t)0x32f8cb07, (q31_t)0x329c8402, (q31_t)0x32401dc6, (q31_t)0x31e39889, + (q31_t)0x3186f487, (q31_t)0x312a31f8, + (q31_t)0x30cd5115, (q31_t)0x30705217, (q31_t)0x30133539, (q31_t)0x2fb5fab2, (q31_t)0x2f58a2be, (q31_t)0x2efb2d95, + (q31_t)0x2e9d9b70, (q31_t)0x2e3fec8b, + (q31_t)0x2de2211e, (q31_t)0x2d843964, (q31_t)0x2d263596, (q31_t)0x2cc815ee, (q31_t)0x2c69daa6, (q31_t)0x2c0b83fa, + (q31_t)0x2bad1221, (q31_t)0x2b4e8558, + (q31_t)0x2aefddd8, (q31_t)0x2a911bdc, (q31_t)0x2a323f9e, (q31_t)0x29d34958, (q31_t)0x29743946, (q31_t)0x29150fa1, + (q31_t)0x28b5cca5, (q31_t)0x2856708d, + (q31_t)0x27f6fb92, (q31_t)0x27976df1, (q31_t)0x2737c7e3, (q31_t)0x26d809a5, (q31_t)0x26783370, (q31_t)0x26184581, + (q31_t)0x25b84012, (q31_t)0x2558235f, + (q31_t)0x24f7efa2, (q31_t)0x2497a517, (q31_t)0x243743fa, (q31_t)0x23d6cc87, (q31_t)0x23763ef7, (q31_t)0x23159b88, + (q31_t)0x22b4e274, (q31_t)0x225413f8, + (q31_t)0x21f3304f, (q31_t)0x219237b5, (q31_t)0x21312a65, (q31_t)0x20d0089c, (q31_t)0x206ed295, (q31_t)0x200d888d, + (q31_t)0x1fac2abf, (q31_t)0x1f4ab968, + (q31_t)0x1ee934c3, (q31_t)0x1e879d0d, (q31_t)0x1e25f282, (q31_t)0x1dc4355e, (q31_t)0x1d6265dd, (q31_t)0x1d00843d, + (q31_t)0x1c9e90b8, (q31_t)0x1c3c8b8c, + (q31_t)0x1bda74f6, (q31_t)0x1b784d30, (q31_t)0x1b161479, (q31_t)0x1ab3cb0d, (q31_t)0x1a517128, (q31_t)0x19ef0707, + (q31_t)0x198c8ce7, (q31_t)0x192a0304, + (q31_t)0x18c7699b, (q31_t)0x1864c0ea, (q31_t)0x1802092c, (q31_t)0x179f429f, (q31_t)0x173c6d80, (q31_t)0x16d98a0c, + (q31_t)0x1676987f, (q31_t)0x16139918, + (q31_t)0x15b08c12, (q31_t)0x154d71aa, (q31_t)0x14ea4a1f, (q31_t)0x148715ae, (q31_t)0x1423d492, (q31_t)0x13c0870a, + (q31_t)0x135d2d53, (q31_t)0x12f9c7aa, + (q31_t)0x1296564d, (q31_t)0x1232d979, (q31_t)0x11cf516a, (q31_t)0x116bbe60, (q31_t)0x11082096, (q31_t)0x10a4784b, + (q31_t)0x1040c5bb, (q31_t)0xfdd0926, + (q31_t)0xf7942c7, (q31_t)0xf1572dc, (q31_t)0xeb199a4, (q31_t)0xe4db75b, (q31_t)0xde9cc40, (q31_t)0xd85d88f, (q31_t)0xd21dc87, + (q31_t)0xcbdd865, + (q31_t)0xc59cc68, (q31_t)0xbf5b8cb, (q31_t)0xb919dcf, (q31_t)0xb2d7baf, (q31_t)0xac952aa, (q31_t)0xa6522fe, (q31_t)0xa00ece8, + (q31_t)0x99cb0a7, + (q31_t)0x9386e78, (q31_t)0x8d42699, (q31_t)0x86fd947, (q31_t)0x80b86c2, (q31_t)0x7a72f45, (q31_t)0x742d311, (q31_t)0x6de7262, + (q31_t)0x67a0d76, + (q31_t)0x615a48b, (q31_t)0x5b137df, (q31_t)0x54cc7b1, (q31_t)0x4e8543e, (q31_t)0x483ddc3, (q31_t)0x41f6480, (q31_t)0x3bae8b2, + (q31_t)0x3566a96, + (q31_t)0x2f1ea6c, (q31_t)0x28d6870, (q31_t)0x228e4e2, (q31_t)0x1c45ffe, (q31_t)0x15fda03, (q31_t)0xfb5330, (q31_t)0x96cbc1, + (q31_t)0x3243f5 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + const q31_t WeightsQ31_2048[4096] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff8719, (q31_t)0xff501258, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffc8549, (q31_t)0xfe227eac, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4319d, (q31_t)0xfc9075af, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, + (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feab61a, (q31_t)0xfb630459, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, + (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, + (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, + (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, + (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, + (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, + (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, + (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb7132b, (q31_t)0xf77712e5, + (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, + (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, + (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, + (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f91b694, (q31_t)0xf581d07b, + (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f895182, (q31_t)0xf51da273, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, + (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f779b62, (q31_t)0xf4555ac5, + (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, + (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, + (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, + (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f45f47b, (q31_t)0xf26129ba, + (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, + (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f247ba5, (q31_t)0xf1356f32, + (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f18b679, (q31_t)0xf0d19848, + (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, + (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef390ae, (q31_t)0xefa64cae, + (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee69217, (q31_t)0xef429caa, + (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7ed94538, (q31_t)0xeedef6f9, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, + (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, + (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eaf8943, (q31_t)0xedb44642, + (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea1039b, (q31_t)0xed50cc46, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, + (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e830dff, (q31_t)0xec89fb1e, + (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e739e1d, (q31_t)0xec26a46d, + (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e63e03b, (q31_t)0xebc359fb, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e53d462, (q31_t)0xeb601c04, + (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e437a9c, (q31_t)0xeafceac6, + (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, + (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e21dd73, (q31_t)0xea36af69, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, + (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e0374a0, 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(q31_t)0x17e958ea, (q31_t)0x8240d673, + (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x17868eb3, (q31_t)0x822e358b, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x1723b5f9, (q31_t)0x821be240, + (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, + (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x165dd9f0, (q31_t)0x81f824ae, + (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x1597c6b7, (q31_t)0x81d59e13, + (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x1534a901, (q31_t)0x81c4cf7d, + (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14d17e36, (q31_t)0x81b44ec4, + (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x146e4694, (q31_t)0x81a41bf4, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x140b0258, (q31_t)0x81943715, + (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13a7b1bf, (q31_t)0x8184a032, + (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x13445505, (q31_t)0x81755754, + (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12e0ec6a, (q31_t)0x81665c84, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x127d7829, (q31_t)0x8157afcd, + (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x1219f880, (q31_t)0x81495136, + (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11b66dad, (q31_t)0x813b40ca, + (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x10ef377d, (q31_t)0x81200a90, + (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, + (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x1027d784, (q31_t)0x81060d63, + (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfc41876, (q31_t)0x80f98446, + (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf604faf, (q31_t)0x80ed4984, + (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xefc7d6b, (q31_t)0x80e15d24, + (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, + (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, + (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, + (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, + (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd08dc3f, (q31_t)0x80aa5806, + (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xca4d620, (q31_t)0x80a04289, + (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc40c835, (q31_t)0x80967b9f, + (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbdcb2bb, (q31_t)0x808d034c, + (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb7895f0, (q31_t)0x8083d998, + (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb147211, (q31_t)0x807afe87, + (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xab0475c, (q31_t)0x8072721f, + (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa4c1610, (q31_t)0x806a3466, + (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9e7de6a, (q31_t)0x80624560, + (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x983a0a7, (q31_t)0x805aa512, + (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x91f5d06, (q31_t)0x80535381, + (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8bb13c5, (q31_t)0x804c50b2, + (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x856c520, (q31_t)0x80459ca9, + (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x7f27157, (q31_t)0x803f376a, + (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x78e18a7, (q31_t)0x803920f8, + (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x729bb4e, (q31_t)0x80335959, + (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6c5598a, (q31_t)0x802de08e, + (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x660f398, (q31_t)0x8028b69c, + (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x5fc89b8, (q31_t)0x8023db86, + (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5981c26, (q31_t)0x801f4f4f, + (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x533ab20, (q31_t)0x801b11fa, + (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4cf36e5, (q31_t)0x80172388, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x46abfb3, (q31_t)0x801383fe, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x40645c7, (q31_t)0x8010335c, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3a1c960, (q31_t)0x800d31a5, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x33d4abb, (q31_t)0x800a7edb, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2d8ca16, (q31_t)0x80081b00, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x27447b0, (q31_t)0x80060614, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x20fc3c6, (q31_t)0x8004401a, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1ab3e97, (q31_t)0x8002c912, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x146b860, (q31_t)0x8001a0fd, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0xe23160, (q31_t)0x8000c7dc, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x7da9d4, (q31_t)0x80003daf, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x1921fb, (q31_t)0x80000278 +}; + const q31_t cos_factorsQ31_2048[2048] = { + (q31_t)0x7fffff62, (q31_t)0x7ffffa73, (q31_t)0x7ffff094, (q31_t)0x7fffe1c6, (q31_t)0x7fffce09, (q31_t)0x7fffb55c, + (q31_t)0x7fff97c1, (q31_t)0x7fff7536, + (q31_t)0x7fff4dbb, (q31_t)0x7fff2151, (q31_t)0x7ffeeff8, (q31_t)0x7ffeb9b0, (q31_t)0x7ffe7e79, (q31_t)0x7ffe3e52, + (q31_t)0x7ffdf93c, (q31_t)0x7ffdaf37, + (q31_t)0x7ffd6042, (q31_t)0x7ffd0c5f, (q31_t)0x7ffcb38c, (q31_t)0x7ffc55ca, (q31_t)0x7ffbf319, (q31_t)0x7ffb8b78, + (q31_t)0x7ffb1ee9, (q31_t)0x7ffaad6a, + (q31_t)0x7ffa36fc, (q31_t)0x7ff9bba0, (q31_t)0x7ff93b54, (q31_t)0x7ff8b619, (q31_t)0x7ff82bef, (q31_t)0x7ff79cd6, + (q31_t)0x7ff708ce, (q31_t)0x7ff66fd7, + (q31_t)0x7ff5d1f1, (q31_t)0x7ff52f1d, (q31_t)0x7ff48759, (q31_t)0x7ff3daa6, (q31_t)0x7ff32905, (q31_t)0x7ff27275, + (q31_t)0x7ff1b6f6, (q31_t)0x7ff0f688, + (q31_t)0x7ff0312c, (q31_t)0x7fef66e1, (q31_t)0x7fee97a7, (q31_t)0x7fedc37e, (q31_t)0x7fecea67, (q31_t)0x7fec0c62, + (q31_t)0x7feb296d, (q31_t)0x7fea418b, + (q31_t)0x7fe954ba, (q31_t)0x7fe862fa, (q31_t)0x7fe76c4c, (q31_t)0x7fe670b0, (q31_t)0x7fe57025, (q31_t)0x7fe46aac, + (q31_t)0x7fe36045, (q31_t)0x7fe250ef, + (q31_t)0x7fe13cac, (q31_t)0x7fe0237a, (q31_t)0x7fdf055a, (q31_t)0x7fdde24d, (q31_t)0x7fdcba51, (q31_t)0x7fdb8d67, + (q31_t)0x7fda5b8f, (q31_t)0x7fd924ca, + (q31_t)0x7fd7e917, (q31_t)0x7fd6a875, (q31_t)0x7fd562e7, (q31_t)0x7fd4186a, (q31_t)0x7fd2c900, (q31_t)0x7fd174a8, + (q31_t)0x7fd01b63, (q31_t)0x7fcebd31, + (q31_t)0x7fcd5a11, (q31_t)0x7fcbf203, (q31_t)0x7fca8508, (q31_t)0x7fc91320, (q31_t)0x7fc79c4b, (q31_t)0x7fc62089, + (q31_t)0x7fc49fda, (q31_t)0x7fc31a3d, + (q31_t)0x7fc18fb4, (q31_t)0x7fc0003e, (q31_t)0x7fbe6bdb, (q31_t)0x7fbcd28b, (q31_t)0x7fbb344e, (q31_t)0x7fb99125, + (q31_t)0x7fb7e90f, (q31_t)0x7fb63c0d, + (q31_t)0x7fb48a1e, (q31_t)0x7fb2d343, (q31_t)0x7fb1177b, (q31_t)0x7faf56c7, (q31_t)0x7fad9127, (q31_t)0x7fabc69b, + (q31_t)0x7fa9f723, (q31_t)0x7fa822bf, + (q31_t)0x7fa6496e, (q31_t)0x7fa46b32, (q31_t)0x7fa2880b, (q31_t)0x7fa09ff7, (q31_t)0x7f9eb2f8, (q31_t)0x7f9cc10d, + (q31_t)0x7f9aca37, (q31_t)0x7f98ce76, + (q31_t)0x7f96cdc9, (q31_t)0x7f94c831, (q31_t)0x7f92bdad, (q31_t)0x7f90ae3f, (q31_t)0x7f8e99e6, (q31_t)0x7f8c80a1, + (q31_t)0x7f8a6272, (q31_t)0x7f883f58, + (q31_t)0x7f861753, (q31_t)0x7f83ea64, (q31_t)0x7f81b88a, (q31_t)0x7f7f81c6, (q31_t)0x7f7d4617, (q31_t)0x7f7b057e, + (q31_t)0x7f78bffb, (q31_t)0x7f76758e, + (q31_t)0x7f742637, (q31_t)0x7f71d1f6, (q31_t)0x7f6f78cb, (q31_t)0x7f6d1ab6, (q31_t)0x7f6ab7b8, (q31_t)0x7f684fd0, + (q31_t)0x7f65e2ff, (q31_t)0x7f637144, + (q31_t)0x7f60faa0, (q31_t)0x7f5e7f13, (q31_t)0x7f5bfe9d, (q31_t)0x7f59793e, (q31_t)0x7f56eef5, (q31_t)0x7f545fc5, + (q31_t)0x7f51cbab, (q31_t)0x7f4f32a9, + (q31_t)0x7f4c94be, (q31_t)0x7f49f1eb, (q31_t)0x7f474a30, (q31_t)0x7f449d8c, (q31_t)0x7f41ec01, (q31_t)0x7f3f358d, + (q31_t)0x7f3c7a31, (q31_t)0x7f39b9ee, + (q31_t)0x7f36f4c3, (q31_t)0x7f342ab1, (q31_t)0x7f315bb7, (q31_t)0x7f2e87d6, (q31_t)0x7f2baf0d, (q31_t)0x7f28d15d, + (q31_t)0x7f25eec7, (q31_t)0x7f230749, + (q31_t)0x7f201ae5, (q31_t)0x7f1d299a, (q31_t)0x7f1a3368, (q31_t)0x7f173850, (q31_t)0x7f143852, (q31_t)0x7f11336d, + (q31_t)0x7f0e29a3, (q31_t)0x7f0b1af2, + (q31_t)0x7f08075c, (q31_t)0x7f04eedf, (q31_t)0x7f01d17d, (q31_t)0x7efeaf36, (q31_t)0x7efb8809, (q31_t)0x7ef85bf7, + (q31_t)0x7ef52b00, (q31_t)0x7ef1f524, + (q31_t)0x7eeeba62, (q31_t)0x7eeb7abc, (q31_t)0x7ee83632, (q31_t)0x7ee4ecc3, (q31_t)0x7ee19e6f, (q31_t)0x7ede4b38, + (q31_t)0x7edaf31c, (q31_t)0x7ed7961c, + (q31_t)0x7ed43438, (q31_t)0x7ed0cd70, (q31_t)0x7ecd61c5, (q31_t)0x7ec9f137, (q31_t)0x7ec67bc5, (q31_t)0x7ec3016f, + (q31_t)0x7ebf8237, (q31_t)0x7ebbfe1c, + (q31_t)0x7eb8751e, (q31_t)0x7eb4e73d, (q31_t)0x7eb1547a, (q31_t)0x7eadbcd4, (q31_t)0x7eaa204c, (q31_t)0x7ea67ee2, + (q31_t)0x7ea2d896, (q31_t)0x7e9f2d68, + (q31_t)0x7e9b7d58, (q31_t)0x7e97c867, (q31_t)0x7e940e94, (q31_t)0x7e904fe0, (q31_t)0x7e8c8c4b, (q31_t)0x7e88c3d5, + (q31_t)0x7e84f67e, (q31_t)0x7e812447, + (q31_t)0x7e7d4d2f, (q31_t)0x7e797136, (q31_t)0x7e75905d, (q31_t)0x7e71aaa4, (q31_t)0x7e6dc00c, (q31_t)0x7e69d093, + (q31_t)0x7e65dc3b, (q31_t)0x7e61e303, + (q31_t)0x7e5de4ec, (q31_t)0x7e59e1f5, (q31_t)0x7e55da20, (q31_t)0x7e51cd6c, (q31_t)0x7e4dbbd9, (q31_t)0x7e49a567, + (q31_t)0x7e458a17, (q31_t)0x7e4169e9, + (q31_t)0x7e3d44dd, (q31_t)0x7e391af3, (q31_t)0x7e34ec2b, (q31_t)0x7e30b885, (q31_t)0x7e2c8002, (q31_t)0x7e2842a2, + (q31_t)0x7e240064, (q31_t)0x7e1fb94a, + (q31_t)0x7e1b6d53, (q31_t)0x7e171c7f, (q31_t)0x7e12c6ce, (q31_t)0x7e0e6c42, (q31_t)0x7e0a0cd9, (q31_t)0x7e05a894, + (q31_t)0x7e013f74, (q31_t)0x7dfcd178, + (q31_t)0x7df85ea0, (q31_t)0x7df3e6ee, (q31_t)0x7def6a60, (q31_t)0x7deae8f7, (q31_t)0x7de662b3, (q31_t)0x7de1d795, + (q31_t)0x7ddd479d, (q31_t)0x7dd8b2ca, + (q31_t)0x7dd4191d, (q31_t)0x7dcf7a96, (q31_t)0x7dcad736, (q31_t)0x7dc62efc, (q31_t)0x7dc181e8, (q31_t)0x7dbccffc, + (q31_t)0x7db81936, (q31_t)0x7db35d98, + (q31_t)0x7dae9d21, (q31_t)0x7da9d7d2, (q31_t)0x7da50dab, (q31_t)0x7da03eab, (q31_t)0x7d9b6ad3, (q31_t)0x7d969224, + (q31_t)0x7d91b49e, (q31_t)0x7d8cd240, + (q31_t)0x7d87eb0a, (q31_t)0x7d82fefe, (q31_t)0x7d7e0e1c, (q31_t)0x7d791862, (q31_t)0x7d741dd2, (q31_t)0x7d6f1e6c, + (q31_t)0x7d6a1a31, (q31_t)0x7d65111f, + (q31_t)0x7d600338, (q31_t)0x7d5af07b, (q31_t)0x7d55d8e9, (q31_t)0x7d50bc82, (q31_t)0x7d4b9b46, (q31_t)0x7d467536, + (q31_t)0x7d414a51, (q31_t)0x7d3c1a98, + (q31_t)0x7d36e60b, (q31_t)0x7d31acaa, (q31_t)0x7d2c6e76, (q31_t)0x7d272b6e, (q31_t)0x7d21e393, (q31_t)0x7d1c96e5, + (q31_t)0x7d174564, (q31_t)0x7d11ef11, + (q31_t)0x7d0c93eb, (q31_t)0x7d0733f3, (q31_t)0x7d01cf29, (q31_t)0x7cfc658d, (q31_t)0x7cf6f720, (q31_t)0x7cf183e1, + (q31_t)0x7cec0bd1, (q31_t)0x7ce68ef0, + (q31_t)0x7ce10d3f, (q31_t)0x7cdb86bd, (q31_t)0x7cd5fb6a, (q31_t)0x7cd06b48, (q31_t)0x7ccad656, (q31_t)0x7cc53c94, + (q31_t)0x7cbf9e03, (q31_t)0x7cb9faa2, + (q31_t)0x7cb45272, (q31_t)0x7caea574, (q31_t)0x7ca8f3a7, (q31_t)0x7ca33d0c, (q31_t)0x7c9d81a3, (q31_t)0x7c97c16b, + (q31_t)0x7c91fc66, (q31_t)0x7c8c3294, + (q31_t)0x7c8663f4, (q31_t)0x7c809088, (q31_t)0x7c7ab84e, (q31_t)0x7c74db48, (q31_t)0x7c6ef976, (q31_t)0x7c6912d7, + (q31_t)0x7c63276d, (q31_t)0x7c5d3737, + (q31_t)0x7c574236, (q31_t)0x7c514869, (q31_t)0x7c4b49d2, (q31_t)0x7c45466f, (q31_t)0x7c3f3e42, (q31_t)0x7c39314b, + (q31_t)0x7c331f8a, (q31_t)0x7c2d08ff, + (q31_t)0x7c26edab, (q31_t)0x7c20cd8d, (q31_t)0x7c1aa8a6, (q31_t)0x7c147ef6, (q31_t)0x7c0e507e, (q31_t)0x7c081d3d, + (q31_t)0x7c01e534, (q31_t)0x7bfba863, + (q31_t)0x7bf566cb, (q31_t)0x7bef206b, (q31_t)0x7be8d544, (q31_t)0x7be28556, (q31_t)0x7bdc30a1, (q31_t)0x7bd5d726, + (q31_t)0x7bcf78e5, (q31_t)0x7bc915dd, + (q31_t)0x7bc2ae10, (q31_t)0x7bbc417e, (q31_t)0x7bb5d026, (q31_t)0x7baf5a09, (q31_t)0x7ba8df28, (q31_t)0x7ba25f82, + (q31_t)0x7b9bdb18, (q31_t)0x7b9551ea, + (q31_t)0x7b8ec3f8, (q31_t)0x7b883143, (q31_t)0x7b8199ca, (q31_t)0x7b7afd8f, (q31_t)0x7b745c91, (q31_t)0x7b6db6d0, + (q31_t)0x7b670c4d, (q31_t)0x7b605d09, + (q31_t)0x7b59a902, (q31_t)0x7b52f03a, (q31_t)0x7b4c32b1, (q31_t)0x7b457068, (q31_t)0x7b3ea95d, (q31_t)0x7b37dd92, + (q31_t)0x7b310d07, (q31_t)0x7b2a37bc, + (q31_t)0x7b235db2, (q31_t)0x7b1c7ee8, (q31_t)0x7b159b5f, (q31_t)0x7b0eb318, (q31_t)0x7b07c612, (q31_t)0x7b00d44d, + (q31_t)0x7af9ddcb, (q31_t)0x7af2e28b, + (q31_t)0x7aebe28d, (q31_t)0x7ae4ddd2, (q31_t)0x7addd45b, (q31_t)0x7ad6c626, (q31_t)0x7acfb336, (q31_t)0x7ac89b89, + (q31_t)0x7ac17f20, (q31_t)0x7aba5dfc, + (q31_t)0x7ab3381d, (q31_t)0x7aac0d82, (q31_t)0x7aa4de2d, (q31_t)0x7a9daa1d, (q31_t)0x7a967153, (q31_t)0x7a8f33d0, + (q31_t)0x7a87f192, (q31_t)0x7a80aa9c, + (q31_t)0x7a795eec, (q31_t)0x7a720e84, (q31_t)0x7a6ab963, (q31_t)0x7a635f8a, (q31_t)0x7a5c00f9, (q31_t)0x7a549db0, + (q31_t)0x7a4d35b0, (q31_t)0x7a45c8f9, + (q31_t)0x7a3e578b, (q31_t)0x7a36e166, (q31_t)0x7a2f668c, (q31_t)0x7a27e6fb, (q31_t)0x7a2062b5, (q31_t)0x7a18d9b9, + (q31_t)0x7a114c09, (q31_t)0x7a09b9a4, + (q31_t)0x7a02228a, (q31_t)0x79fa86bc, (q31_t)0x79f2e63a, (q31_t)0x79eb4105, (q31_t)0x79e3971c, (q31_t)0x79dbe880, + (q31_t)0x79d43532, (q31_t)0x79cc7d31, + (q31_t)0x79c4c07e, (q31_t)0x79bcff19, (q31_t)0x79b53903, (q31_t)0x79ad6e3c, (q31_t)0x79a59ec3, (q31_t)0x799dca9a, + (q31_t)0x7995f1c1, (q31_t)0x798e1438, + (q31_t)0x798631ff, (q31_t)0x797e4b16, (q31_t)0x79765f7f, (q31_t)0x796e6f39, (q31_t)0x79667a44, (q31_t)0x795e80a1, + (q31_t)0x79568250, (q31_t)0x794e7f52, + (q31_t)0x794677a6, (q31_t)0x793e6b4e, (q31_t)0x79365a49, (q31_t)0x792e4497, (q31_t)0x79262a3a, (q31_t)0x791e0b31, + (q31_t)0x7915e77c, (q31_t)0x790dbf1d, + (q31_t)0x79059212, (q31_t)0x78fd605d, (q31_t)0x78f529fe, (q31_t)0x78eceef6, (q31_t)0x78e4af44, (q31_t)0x78dc6ae8, + (q31_t)0x78d421e4, (q31_t)0x78cbd437, + (q31_t)0x78c381e2, (q31_t)0x78bb2ae5, (q31_t)0x78b2cf41, (q31_t)0x78aa6ef5, (q31_t)0x78a20a03, (q31_t)0x7899a06a, + (q31_t)0x7891322a, (q31_t)0x7888bf45, + (q31_t)0x788047ba, (q31_t)0x7877cb89, (q31_t)0x786f4ab4, (q31_t)0x7866c53a, (q31_t)0x785e3b1c, (q31_t)0x7855ac5a, + (q31_t)0x784d18f4, (q31_t)0x784480ea, + (q31_t)0x783be43e, (q31_t)0x783342ef, (q31_t)0x782a9cfe, (q31_t)0x7821f26b, (q31_t)0x78194336, (q31_t)0x78108f60, + (q31_t)0x7807d6e9, (q31_t)0x77ff19d1, + (q31_t)0x77f65819, (q31_t)0x77ed91c0, (q31_t)0x77e4c6c9, (q31_t)0x77dbf732, (q31_t)0x77d322fc, (q31_t)0x77ca4a27, + (q31_t)0x77c16cb4, (q31_t)0x77b88aa3, + (q31_t)0x77afa3f5, (q31_t)0x77a6b8a9, (q31_t)0x779dc8c0, (q31_t)0x7794d43b, (q31_t)0x778bdb19, (q31_t)0x7782dd5c, + (q31_t)0x7779db03, (q31_t)0x7770d40f, + (q31_t)0x7767c880, (q31_t)0x775eb857, (q31_t)0x7755a394, (q31_t)0x774c8a36, (q31_t)0x77436c40, (q31_t)0x773a49b0, + (q31_t)0x77312287, (q31_t)0x7727f6c6, + (q31_t)0x771ec66e, (q31_t)0x7715917d, (q31_t)0x770c57f5, (q31_t)0x770319d6, (q31_t)0x76f9d721, (q31_t)0x76f08fd5, + (q31_t)0x76e743f4, (q31_t)0x76ddf37c, + (q31_t)0x76d49e70, (q31_t)0x76cb44cf, (q31_t)0x76c1e699, (q31_t)0x76b883d0, (q31_t)0x76af1c72, (q31_t)0x76a5b082, + (q31_t)0x769c3ffe, (q31_t)0x7692cae8, + (q31_t)0x7689513f, (q31_t)0x767fd304, (q31_t)0x76765038, (q31_t)0x766cc8db, (q31_t)0x76633ced, (q31_t)0x7659ac6f, + (q31_t)0x76501760, (q31_t)0x76467dc2, + (q31_t)0x763cdf94, (q31_t)0x76333cd8, (q31_t)0x7629958c, (q31_t)0x761fe9b3, (q31_t)0x7616394c, (q31_t)0x760c8457, + (q31_t)0x7602cad5, (q31_t)0x75f90cc7, + (q31_t)0x75ef4a2c, (q31_t)0x75e58305, (q31_t)0x75dbb753, (q31_t)0x75d1e715, (q31_t)0x75c8124d, (q31_t)0x75be38fa, + (q31_t)0x75b45b1d, (q31_t)0x75aa78b6, + (q31_t)0x75a091c6, (q31_t)0x7596a64d, (q31_t)0x758cb64c, (q31_t)0x7582c1c2, (q31_t)0x7578c8b0, (q31_t)0x756ecb18, + (q31_t)0x7564c8f8, (q31_t)0x755ac251, + (q31_t)0x7550b725, (q31_t)0x7546a772, (q31_t)0x753c933a, (q31_t)0x75327a7d, (q31_t)0x75285d3b, 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(q31_t)0x169bb4b7, (q31_t)0x1682f774, (q31_t)0x166a3953, (q31_t)0x16517a55, (q31_t)0x1638ba7a, (q31_t)0x161ff9c4, + (q31_t)0x16073834, (q31_t)0x15ee75cb, + (q31_t)0x15d5b288, (q31_t)0x15bcee6f, (q31_t)0x15a4297f, (q31_t)0x158b63b9, (q31_t)0x15729d1f, (q31_t)0x1559d5b1, + (q31_t)0x15410d70, (q31_t)0x1528445d, + (q31_t)0x150f7a7a, (q31_t)0x14f6afc7, (q31_t)0x14dde445, (q31_t)0x14c517f4, (q31_t)0x14ac4ad7, (q31_t)0x14937cee, + (q31_t)0x147aae3a, (q31_t)0x1461debc, + (q31_t)0x14490e74, (q31_t)0x14303d65, (q31_t)0x14176b8e, (q31_t)0x13fe98f1, (q31_t)0x13e5c58e, (q31_t)0x13ccf167, + (q31_t)0x13b41c7d, (q31_t)0x139b46d0, + (q31_t)0x13827062, (q31_t)0x13699933, (q31_t)0x1350c144, (q31_t)0x1337e897, (q31_t)0x131f0f2c, (q31_t)0x13063505, + (q31_t)0x12ed5a21, (q31_t)0x12d47e83, + (q31_t)0x12bba22b, (q31_t)0x12a2c51b, (q31_t)0x1289e752, (q31_t)0x127108d2, (q31_t)0x1258299c, (q31_t)0x123f49b2, + (q31_t)0x12266913, (q31_t)0x120d87c1, + (q31_t)0x11f4a5bd, (q31_t)0x11dbc307, (q31_t)0x11c2dfa2, (q31_t)0x11a9fb8d, (q31_t)0x119116c9, (q31_t)0x11783159, + (q31_t)0x115f4b3c, (q31_t)0x11466473, + (q31_t)0x112d7d00, (q31_t)0x111494e4, (q31_t)0x10fbac1e, (q31_t)0x10e2c2b2, (q31_t)0x10c9d89e, (q31_t)0x10b0ede5, + (q31_t)0x10980287, (q31_t)0x107f1686, + (q31_t)0x106629e1, (q31_t)0x104d3c9b, (q31_t)0x10344eb4, (q31_t)0x101b602d, (q31_t)0x10027107, (q31_t)0xfe98143, + (q31_t)0xfd090e1, (q31_t)0xfb79fe4, + (q31_t)0xf9eae4c, (q31_t)0xf85bc19, (q31_t)0xf6cc94e, (q31_t)0xf53d5ea, (q31_t)0xf3ae1ee, (q31_t)0xf21ed5d, (q31_t)0xf08f836, + (q31_t)0xef0027b, + (q31_t)0xed70c2c, (q31_t)0xebe154b, (q31_t)0xea51dd8, (q31_t)0xe8c25d5, (q31_t)0xe732d42, (q31_t)0xe5a3421, (q31_t)0xe413a72, + (q31_t)0xe284036, + (q31_t)0xe0f456f, (q31_t)0xdf64a1c, (q31_t)0xddd4e40, (q31_t)0xdc451dc, (q31_t)0xdab54ef, (q31_t)0xd92577b, (q31_t)0xd795982, + (q31_t)0xd605b03, + (q31_t)0xd475c00, (q31_t)0xd2e5c7b, (q31_t)0xd155c73, (q31_t)0xcfc5bea, (q31_t)0xce35ae1, (q31_t)0xcca5959, (q31_t)0xcb15752, + (q31_t)0xc9854cf, + (q31_t)0xc7f51cf, (q31_t)0xc664e53, (q31_t)0xc4d4a5d, (q31_t)0xc3445ee, (q31_t)0xc1b4107, (q31_t)0xc023ba7, (q31_t)0xbe935d2, + (q31_t)0xbd02f87, + (q31_t)0xbb728c7, (q31_t)0xb9e2193, (q31_t)0xb8519ed, (q31_t)0xb6c11d5, (q31_t)0xb53094d, (q31_t)0xb3a0055, (q31_t)0xb20f6ee, + (q31_t)0xb07ed19, + (q31_t)0xaeee2d7, (q31_t)0xad5d829, (q31_t)0xabccd11, (q31_t)0xaa3c18e, (q31_t)0xa8ab5a2, (q31_t)0xa71a94f, (q31_t)0xa589c94, + (q31_t)0xa3f8f73, + (q31_t)0xa2681ed, (q31_t)0xa0d7403, (q31_t)0x9f465b5, (q31_t)0x9db5706, (q31_t)0x9c247f5, (q31_t)0x9a93884, (q31_t)0x99028b3, + (q31_t)0x9771884, + (q31_t)0x95e07f8, (q31_t)0x944f70f, (q31_t)0x92be5ca, (q31_t)0x912d42c, (q31_t)0x8f9c233, (q31_t)0x8e0afe2, (q31_t)0x8c79d3a, + (q31_t)0x8ae8a3a, + (q31_t)0x89576e5, (q31_t)0x87c633c, (q31_t)0x8634f3e, (q31_t)0x84a3aee, (q31_t)0x831264c, (q31_t)0x8181159, (q31_t)0x7fefc16, + (q31_t)0x7e5e685, + (q31_t)0x7ccd0a5, (q31_t)0x7b3ba78, (q31_t)0x79aa400, (q31_t)0x7818d3c, (q31_t)0x768762e, (q31_t)0x74f5ed7, (q31_t)0x7364738, + (q31_t)0x71d2f52, + (q31_t)0x7041726, (q31_t)0x6eafeb4, (q31_t)0x6d1e5fe, (q31_t)0x6b8cd05, (q31_t)0x69fb3c9, (q31_t)0x6869a4c, (q31_t)0x66d808f, + (q31_t)0x6546692, + (q31_t)0x63b4c57, (q31_t)0x62231de, (q31_t)0x6091729, (q31_t)0x5effc38, (q31_t)0x5d6e10c, (q31_t)0x5bdc5a7, (q31_t)0x5a4aa09, + (q31_t)0x58b8e34, + (q31_t)0x5727228, (q31_t)0x55955e6, (q31_t)0x540396f, (q31_t)0x5271cc4, (q31_t)0x50dffe7, (q31_t)0x4f4e2d8, (q31_t)0x4dbc597, + (q31_t)0x4c2a827, + (q31_t)0x4a98a88, (q31_t)0x4906cbb, (q31_t)0x4774ec1, (q31_t)0x45e309a, (q31_t)0x4451249, (q31_t)0x42bf3cd, (q31_t)0x412d528, + (q31_t)0x3f9b65b, + (q31_t)0x3e09767, (q31_t)0x3c7784d, (q31_t)0x3ae590d, (q31_t)0x39539a9, (q31_t)0x37c1a22, (q31_t)0x362fa78, (q31_t)0x349daac, + (q31_t)0x330bac1, + (q31_t)0x3179ab5, (q31_t)0x2fe7a8c, (q31_t)0x2e55a44, (q31_t)0x2cc39e1, (q31_t)0x2b31961, (q31_t)0x299f8c7, (q31_t)0x280d813, + (q31_t)0x267b747, + (q31_t)0x24e9662, (q31_t)0x2357567, (q31_t)0x21c5457, (q31_t)0x2033331, (q31_t)0x1ea11f7, (q31_t)0x1d0f0ab, (q31_t)0x1b7cf4d, + (q31_t)0x19eaddd, + (q31_t)0x1858c5e, (q31_t)0x16c6ad0, (q31_t)0x1534934, (q31_t)0x13a278a, (q31_t)0x12105d5, (q31_t)0x107e414, (q31_t)0xeec249, + (q31_t)0xd5a075, + (q31_t)0xbc7e99, (q31_t)0xa35cb5, (q31_t)0x8a3acb, (q31_t)0x7118dc, (q31_t)0x57f6e9, (q31_t)0x3ed4f2, (q31_t)0x25b2f8, + (q31_t)0xc90fe +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + const q31_t WeightsQ31_8192[16384] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffffd9, (q31_t)0xfff9b781, (q31_t)0x7fffff62, (q31_t)0xfff36f02, (q31_t)0x7ffffe9d, (q31_t)0xffed2684, + (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffffc25, (q31_t)0xffe09586, (q31_t)0x7ffffa73, (q31_t)0xffda4d08, (q31_t)0x7ffff872, (q31_t)0xffd40489, + (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7ffff382, (q31_t)0xffc7738c, (q31_t)0x7ffff094, (q31_t)0xffc12b0e, (q31_t)0x7fffed57, (q31_t)0xffbae290, + (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, (q31_t)0x7fffe5f0, (q31_t)0xffae5195, (q31_t)0x7fffe1c6, (q31_t)0xffa80917, (q31_t)0x7fffdd4d, (q31_t)0xffa1c09a, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffd36f, (q31_t)0xff952fa0, (q31_t)0x7fffce09, (q31_t)0xff8ee724, (q31_t)0x7fffc854, (q31_t)0xff889ea7, + (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffbbfe, (q31_t)0xff7c0db0, (q31_t)0x7fffb55c, (q31_t)0xff75c535, (q31_t)0x7fffae6c, (q31_t)0xff6f7cba, + (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff9f9e, (q31_t)0xff62ebc5, (q31_t)0x7fff97c1, (q31_t)0xff5ca34b, (q31_t)0x7fff8f94, (q31_t)0xff565ad1, + (q31_t)0x7fff8719, (q31_t)0xff501258, (q31_t)0x7fff7e4f, (q31_t)0xff49c9df, (q31_t)0x7fff7536, (q31_t)0xff438167, (q31_t)0x7fff6bcd, (q31_t)0xff3d38ef, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff5810, (q31_t)0xff30a801, (q31_t)0x7fff4dbb, (q31_t)0xff2a5f8b, (q31_t)0x7fff4317, (q31_t)0xff241715, + (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff2ce2, (q31_t)0xff17862b, (q31_t)0x7fff2151, (q31_t)0xff113db7, (q31_t)0x7fff1572, (q31_t)0xff0af543, + (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffefcc5, (q31_t)0xfefe645e, (q31_t)0x7ffeeff8, (q31_t)0xfef81bec, (q31_t)0x7ffee2dd, (q31_t)0xfef1d37b, + (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, (q31_t)0x7ffec7b9, (q31_t)0xfee5429a, (q31_t)0x7ffeb9b0, (q31_t)0xfedefa2b, (q31_t)0x7ffeab59, (q31_t)0xfed8b1bd, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe8dbd, (q31_t)0xfecc20e2, (q31_t)0x7ffe7e79, (q31_t)0xfec5d876, (q31_t)0x7ffe6ee5, (q31_t)0xfebf900a, + (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe4ed2, (q31_t)0xfeb2ff36, (q31_t)0x7ffe3e52, (q31_t)0xfeacb6cc, (q31_t)0x7ffe2d83, (q31_t)0xfea66e64, + (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffe0af8, (q31_t)0xfe99dd96, (q31_t)0x7ffdf93c, (q31_t)0xfe939530, (q31_t)0x7ffde731, (q31_t)0xfe8d4ccb, + (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, (q31_t)0x7ffdc22e, (q31_t)0xfe80bc04, (q31_t)0x7ffdaf37, (q31_t)0xfe7a73a2, (q31_t)0x7ffd9bf0, (q31_t)0xfe742b41, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd7476, (q31_t)0xfe679a81, (q31_t)0x7ffd6042, (q31_t)0xfe615223, (q31_t)0x7ffd4bc0, (q31_t)0xfe5b09c5, + (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffd21ce, (q31_t)0xfe4e790d, (q31_t)0x7ffd0c5f, (q31_t)0xfe4830b3, (q31_t)0x7ffcf6a0, (q31_t)0xfe41e85a, + (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffcca37, (q31_t)0xfe3557ab, (q31_t)0x7ffcb38c, (q31_t)0xfe2f0f55, (q31_t)0x7ffc9c92, (q31_t)0xfe28c700, + (q31_t)0x7ffc8549, (q31_t)0xfe227eac, (q31_t)0x7ffc6db1, (q31_t)0xfe1c365a, (q31_t)0x7ffc55ca, (q31_t)0xfe15ee09, (q31_t)0x7ffc3d94, (q31_t)0xfe0fa5b8, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffc0c3b, (q31_t)0xfe03151c, (q31_t)0x7ffbf319, (q31_t)0xfdfccccf, (q31_t)0x7ffbd9a7, (q31_t)0xfdf68484, + (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffba5d7, (q31_t)0xfde9f3f1, (q31_t)0x7ffb8b78, (q31_t)0xfde3aba9, (q31_t)0x7ffb70cb, (q31_t)0xfddd6363, + (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffb3a83, (q31_t)0xfdd0d2db, (q31_t)0x7ffb1ee9, (q31_t)0xfdca8a99, (q31_t)0x7ffb0300, (q31_t)0xfdc44258, + (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, (q31_t)0x7ffaca40, (q31_t)0xfdb7b1da, (q31_t)0x7ffaad6a, (q31_t)0xfdb1699e, (q31_t)0x7ffa9045, (q31_t)0xfdab2162, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ffa550e, (q31_t)0xfd9e90f0, (q31_t)0x7ffa36fc, (q31_t)0xfd9848b9, (q31_t)0x7ffa189c, (q31_t)0xfd920084, + (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff9daed, (q31_t)0xfd85701e, (q31_t)0x7ff9bba0, (q31_t)0xfd7f27ed, (q31_t)0x7ff99c03, (q31_t)0xfd78dfbd, + (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff95bdd, (q31_t)0xfd6c4f64, (q31_t)0x7ff93b54, (q31_t)0xfd660739, (q31_t)0x7ff91a7b, (q31_t)0xfd5fbf10, + (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, (q31_t)0x7ff8d7de, (q31_t)0xfd532ec3, (q31_t)0x7ff8b619, (q31_t)0xfd4ce69f, (q31_t)0x7ff89405, (q31_t)0xfd469e7c, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff84ef0, (q31_t)0xfd3a0e3d, (q31_t)0x7ff82bef, (q31_t)0xfd33c61f, (q31_t)0x7ff8089f, (q31_t)0xfd2d7e04, + (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff7c113, (q31_t)0xfd20edd2, (q31_t)0x7ff79cd6, (q31_t)0xfd1aa5bc, (q31_t)0x7ff7784a, (q31_t)0xfd145da7, + (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff72e46, (q31_t)0xfd07cd83, (q31_t)0x7ff708ce, (q31_t)0xfd018574, (q31_t)0x7ff6e307, (q31_t)0xfcfb3d67, + (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, (q31_t)0x7ff6968b, (q31_t)0xfceead52, (q31_t)0x7ff66fd7, (q31_t)0xfce8654b, (q31_t)0x7ff648d4, (q31_t)0xfce21d45, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff5f9e1, (q31_t)0xfcd58d3f, (q31_t)0x7ff5d1f1, (q31_t)0xfccf453f, (q31_t)0x7ff5a9b2, (q31_t)0xfcc8fd41, + (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff55848, (q31_t)0xfcbc6d4c, (q31_t)0x7ff52f1d, (q31_t)0xfcb62554, (q31_t)0x7ff505a2, (q31_t)0xfcafdd5e, + (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4b1c0, (q31_t)0xfca34d78, (q31_t)0x7ff48759, (q31_t)0xfc9d0588, (q31_t)0x7ff45ca3, (q31_t)0xfc96bd9b, + (q31_t)0x7ff4319d, (q31_t)0xfc9075af, (q31_t)0x7ff40649, (q31_t)0xfc8a2dc6, (q31_t)0x7ff3daa6, (q31_t)0xfc83e5de, (q31_t)0x7ff3aeb4, (q31_t)0xfc7d9df9, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff355e4, (q31_t)0xfc710e36, (q31_t)0x7ff32905, (q31_t)0xfc6ac657, (q31_t)0x7ff2fbd7, (q31_t)0xfc647e7b, + (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff2a08f, (q31_t)0xfc57eec9, (q31_t)0x7ff27275, (q31_t)0xfc51a6f3, (q31_t)0x7ff2440b, (q31_t)0xfc4b5f20, + (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1e64c, (q31_t)0xfc3ecf80, (q31_t)0x7ff1b6f6, (q31_t)0xfc3887b3, (q31_t)0x7ff18751, (q31_t)0xfc323fe9, + (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, (q31_t)0x7ff1271a, (q31_t)0xfc25b05c, (q31_t)0x7ff0f688, (q31_t)0xfc1f6899, (q31_t)0x7ff0c5a7, (q31_t)0xfc1920d8, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7ff062f9, (q31_t)0xfc0c915e, (q31_t)0x7ff0312c, (q31_t)0xfc0649a5, (q31_t)0x7fefff0f, (q31_t)0xfc0001ee, + (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7fef99ea, (q31_t)0xfbf37287, (q31_t)0x7fef66e1, (q31_t)0xfbed2ad8, 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(q31_t)0x4f4e2d8, (q31_t)0x801893b4, (q31_t)0x4ee9b8c, (q31_t)0x80185592, + (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4e20cec, (q31_t)0x8017da3b, (q31_t)0x4dbc597, (q31_t)0x80179d06, (q31_t)0x4d57e40, (q31_t)0x80176020, + (q31_t)0x4cf36e5, (q31_t)0x80172388, (q31_t)0x4c8ef88, (q31_t)0x8016e740, (q31_t)0x4c2a827, (q31_t)0x8016ab46, (q31_t)0x4bc60c4, (q31_t)0x80166f9c, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x4afd1f4, (q31_t)0x8015f933, (q31_t)0x4a98a88, (q31_t)0x8015be75, (q31_t)0x4a34319, (q31_t)0x80158406, + (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x496b432, (q31_t)0x80151015, (q31_t)0x4906cbb, (q31_t)0x8014d693, (q31_t)0x48a2540, (q31_t)0x80149d5f, + (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x47d9643, (q31_t)0x80142be5, (q31_t)0x4774ec1, (q31_t)0x8013f39e, (q31_t)0x471073b, (q31_t)0x8013bba7, + (q31_t)0x46abfb3, (q31_t)0x801383fe, (q31_t)0x4647828, (q31_t)0x80134ca4, (q31_t)0x45e309a, (q31_t)0x80131599, (q31_t)0x457e90a, (q31_t)0x8012dedd, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x44b59e1, (q31_t)0x80127251, (q31_t)0x4451249, (q31_t)0x80123c82, (q31_t)0x43ecaae, (q31_t)0x80120701, + (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x4323b70, (q31_t)0x80119ced, (q31_t)0x42bf3cd, (q31_t)0x80116859, (q31_t)0x425ac28, (q31_t)0x80113414, + (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x4191cd5, (q31_t)0x8010cc78, (q31_t)0x412d528, (q31_t)0x8010991f, (q31_t)0x40c8d79, (q31_t)0x80106616, + (q31_t)0x40645c7, (q31_t)0x8010335c, (q31_t)0x3fffe12, (q31_t)0x801000f1, (q31_t)0x3f9b65b, (q31_t)0x800fced4, (q31_t)0x3f36ea2, (q31_t)0x800f9d07, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3e6df28, (q31_t)0x800f3a59, (q31_t)0x3e09767, (q31_t)0x800f0978, (q31_t)0x3da4fa4, (q31_t)0x800ed8e6, + (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3cdc017, (q31_t)0x800e78af, (q31_t)0x3c7784d, (q31_t)0x800e490a, (q31_t)0x3c13080, (q31_t)0x800e19b4, + (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3b4a0e0, (q31_t)0x800dbbf5, (q31_t)0x3ae590d, (q31_t)0x800d8d8b, (q31_t)0x3a81137, (q31_t)0x800d5f71, + (q31_t)0x3a1c960, (q31_t)0x800d31a5, (q31_t)0x39b8185, (q31_t)0x800d0429, (q31_t)0x39539a9, (q31_t)0x800cd6fb, (q31_t)0x38ef1ca, (q31_t)0x800caa1c, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x3826207, (q31_t)0x800c514c, (q31_t)0x37c1a22, (q31_t)0x800c255a, (q31_t)0x375d23a, (q31_t)0x800bf9b7, + (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3694265, (q31_t)0x800ba35d, (q31_t)0x362fa78, (q31_t)0x800b78a7, (q31_t)0x35cb288, (q31_t)0x800b4e40, + (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x35022a2, (q31_t)0x800afa5e, (q31_t)0x349daac, (q31_t)0x800ad0e3, (q31_t)0x34392b4, (q31_t)0x800aa7b8, + (q31_t)0x33d4abb, (q31_t)0x800a7edb, (q31_t)0x33702bf, (q31_t)0x800a564e, (q31_t)0x330bac1, (q31_t)0x800a2e0f, (q31_t)0x32a72c1, (q31_t)0x800a061f, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x31de2bb, (q31_t)0x8009b72c, (q31_t)0x3179ab5, (q31_t)0x80099029, (q31_t)0x31152ae, (q31_t)0x80096975, + (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x304c299, (q31_t)0x80091cf9, (q31_t)0x2fe7a8c, (q31_t)0x8008f732, (q31_t)0x2f8327d, (q31_t)0x8008d1ba, + (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2eba259, (q31_t)0x800887b6, (q31_t)0x2e55a44, (q31_t)0x8008632a, (q31_t)0x2df122e, (q31_t)0x80083eed, + (q31_t)0x2d8ca16, (q31_t)0x80081b00, (q31_t)0x2d281fc, (q31_t)0x8007f761, (q31_t)0x2cc39e1, (q31_t)0x8007d411, (q31_t)0x2c5f1c3, (q31_t)0x8007b110, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2b96184, (q31_t)0x80076bfb, (q31_t)0x2b31961, (q31_t)0x800749e7, (q31_t)0x2acd13d, (q31_t)0x80072822, + (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x2a040f0, (q31_t)0x8006e585, (q31_t)0x299f8c7, (q31_t)0x8006c4ac, (q31_t)0x293b09c, (q31_t)0x8006a423, + (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x2872043, (q31_t)0x800663fd, (q31_t)0x280d813, (q31_t)0x80064460, (q31_t)0x27a8fe2, (q31_t)0x80062513, + (q31_t)0x27447b0, (q31_t)0x80060614, (q31_t)0x26dff7c, (q31_t)0x8005e764, (q31_t)0x267b747, (q31_t)0x8005c904, (q31_t)0x2616f10, (q31_t)0x8005aaf2, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x254de9e, (q31_t)0x80056fbb, (q31_t)0x24e9662, (q31_t)0x80055296, (q31_t)0x2484e26, (q31_t)0x800535c0, + (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x23bbda8, (q31_t)0x8004fd00, (q31_t)0x2357567, (q31_t)0x8004e117, (q31_t)0x22f2d25, (q31_t)0x8004c57d, + (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x2229c9d, (q31_t)0x80048f35, (q31_t)0x21c5457, (q31_t)0x80047488, (q31_t)0x2160c0f, (q31_t)0x80045a29, + (q31_t)0x20fc3c6, (q31_t)0x8004401a, (q31_t)0x2097b7c, (q31_t)0x80042659, (q31_t)0x2033331, (q31_t)0x80040ce7, (q31_t)0x1fceae4, (q31_t)0x8003f3c5, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1f05a48, (q31_t)0x8003c26c, (q31_t)0x1ea11f7, (q31_t)0x8003aa36, (q31_t)0x1e3c9a6, (q31_t)0x8003924f, + (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1d73900, (q31_t)0x8003636e, (q31_t)0x1d0f0ab, (q31_t)0x80034c74, (q31_t)0x1caa855, (q31_t)0x800335c9, + (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1be17a6, (q31_t)0x80030960, (q31_t)0x1b7cf4d, (q31_t)0x8002f3a1, (q31_t)0x1b186f3, (q31_t)0x8002de32, + (q31_t)0x1ab3e97, (q31_t)0x8002c912, (q31_t)0x1a4f63b, (q31_t)0x8002b440, (q31_t)0x19eaddd, (q31_t)0x80029fbe, (q31_t)0x198657f, (q31_t)0x80028b8a, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x18bd4bf, (q31_t)0x80026410, (q31_t)0x1858c5e, (q31_t)0x800250c9, (q31_t)0x17f43fc, (q31_t)0x80023dd2, + (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x172b335, (q31_t)0x800218cf, (q31_t)0x16c6ad0, (q31_t)0x800206c4, (q31_t)0x166226a, (q31_t)0x8001f508, + (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x159919c, (q31_t)0x8001d27d, (q31_t)0x1534934, (q31_t)0x8001c1ae, (q31_t)0x14d00ca, (q31_t)0x8001b12e, + (q31_t)0x146b860, (q31_t)0x8001a0fd, (q31_t)0x1406ff6, (q31_t)0x8001911b, (q31_t)0x13a278a, (q31_t)0x80018187, (q31_t)0x133df1e, (q31_t)0x80017243, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x1274e43, (q31_t)0x800154a7, (q31_t)0x12105d5, (q31_t)0x80014650, (q31_t)0x11abd66, (q31_t)0x80013847, + (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x10e2c85, (q31_t)0x80011d23, (q31_t)0x107e414, (q31_t)0x80011008, (q31_t)0x1019ba2, (q31_t)0x8001033b, + (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0x0f50abd, (q31_t)0x8000ea8e, (q31_t)0x0eec249, (q31_t)0x8000deaf, (q31_t)0x0e879d5, (q31_t)0x8000d31e, + (q31_t)0x0e23160, (q31_t)0x8000c7dc, (q31_t)0x0dbe8eb, (q31_t)0x8000bce9, (q31_t)0x0d5a075, (q31_t)0x8000b245, (q31_t)0x0cf57ff, (q31_t)0x8000a7f0, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0c2c711, (q31_t)0x80009433, (q31_t)0x0bc7e99, (q31_t)0x80008aca, (q31_t)0x0b63621, (q31_t)0x800081b1, + (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x0a9a52f, (q31_t)0x8000706c, (q31_t)0x0a35cb5, (q31_t)0x8000683f, (q31_t)0x09d143b, (q31_t)0x80006062, + (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x0908346, (q31_t)0x80005194, (q31_t)0x08a3acb, (q31_t)0x80004aa4, (q31_t)0x083f250, (q31_t)0x80004402, + (q31_t)0x07da9d4, (q31_t)0x80003daf, (q31_t)0x0776159, (q31_t)0x800037ac, (q31_t)0x07118dc, (q31_t)0x800031f7, (q31_t)0x06ad060, (q31_t)0x80002c91, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x05e3f66, (q31_t)0x800022b3, (q31_t)0x057f6e9, (q31_t)0x80001e3a, (q31_t)0x051ae6b, (q31_t)0x80001a10, + (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x0451d70, (q31_t)0x800012a9, (q31_t)0x03ed4f2, (q31_t)0x80000f6c, (q31_t)0x0388c74, (q31_t)0x80000c7e, + (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x02bfb77, (q31_t)0x8000078e, (q31_t)0x025b2f8, (q31_t)0x8000058d, (q31_t)0x01f6a7a, (q31_t)0x800003db, + (q31_t)0x01921fb, (q31_t)0x80000278, (q31_t)0x012d97c, (q31_t)0x80000163, (q31_t)0x00c90fe, (q31_t)0x8000009e, (q31_t)0x006487f, (q31_t)0x80000027 +}; + const q31_t cos_factorsQ31_8192[8192] = { + (q31_t)0x7ffffff6, (q31_t)0x7fffffa7, (q31_t)0x7fffff09, (q31_t)0x7ffffe1c, (q31_t)0x7ffffce1, (q31_t)0x7ffffb56, (q31_t)0x7ffff97c, (q31_t)0x7ffff753, + (q31_t)0x7ffff4dc, (q31_t)0x7ffff215, (q31_t)0x7fffef00, (q31_t)0x7fffeb9b, (q31_t)0x7fffe7e8, (q31_t)0x7fffe3e5, (q31_t)0x7fffdf94, (q31_t)0x7fffdaf3, + (q31_t)0x7fffd604, (q31_t)0x7fffd0c6, (q31_t)0x7fffcb39, (q31_t)0x7fffc55c, (q31_t)0x7fffbf31, (q31_t)0x7fffb8b7, (q31_t)0x7fffb1ee, (q31_t)0x7fffaad6, + (q31_t)0x7fffa36f, (q31_t)0x7fff9bb9, (q31_t)0x7fff93b4, (q31_t)0x7fff8b61, (q31_t)0x7fff82be, (q31_t)0x7fff79cc, (q31_t)0x7fff708b, (q31_t)0x7fff66fc, + (q31_t)0x7fff5d1d, (q31_t)0x7fff52ef, (q31_t)0x7fff4873, (q31_t)0x7fff3da8, (q31_t)0x7fff328d, (q31_t)0x7fff2724, (q31_t)0x7fff1b6b, (q31_t)0x7fff0f64, + (q31_t)0x7fff030e, (q31_t)0x7ffef669, (q31_t)0x7ffee975, (q31_t)0x7ffedc31, (q31_t)0x7ffece9f, (q31_t)0x7ffec0be, (q31_t)0x7ffeb28e, (q31_t)0x7ffea40f, + (q31_t)0x7ffe9542, (q31_t)0x7ffe8625, (q31_t)0x7ffe76b9, (q31_t)0x7ffe66fe, (q31_t)0x7ffe56f5, (q31_t)0x7ffe469c, (q31_t)0x7ffe35f4, (q31_t)0x7ffe24fe, + (q31_t)0x7ffe13b8, (q31_t)0x7ffe0224, (q31_t)0x7ffdf040, (q31_t)0x7ffdde0e, (q31_t)0x7ffdcb8d, (q31_t)0x7ffdb8bc, (q31_t)0x7ffda59d, (q31_t)0x7ffd922f, + (q31_t)0x7ffd7e72, (q31_t)0x7ffd6a66, (q31_t)0x7ffd560b, (q31_t)0x7ffd4161, (q31_t)0x7ffd2c68, (q31_t)0x7ffd1720, (q31_t)0x7ffd0189, (q31_t)0x7ffceba4, + (q31_t)0x7ffcd56f, (q31_t)0x7ffcbeeb, (q31_t)0x7ffca819, (q31_t)0x7ffc90f7, (q31_t)0x7ffc7987, (q31_t)0x7ffc61c7, (q31_t)0x7ffc49b9, (q31_t)0x7ffc315b, + (q31_t)0x7ffc18af, (q31_t)0x7ffbffb4, (q31_t)0x7ffbe66a, (q31_t)0x7ffbccd0, (q31_t)0x7ffbb2e8, (q31_t)0x7ffb98b1, (q31_t)0x7ffb7e2b, (q31_t)0x7ffb6356, + (q31_t)0x7ffb4833, (q31_t)0x7ffb2cc0, (q31_t)0x7ffb10fe, (q31_t)0x7ffaf4ed, (q31_t)0x7ffad88e, (q31_t)0x7ffabbdf, (q31_t)0x7ffa9ee2, (q31_t)0x7ffa8195, + (q31_t)0x7ffa63fa, (q31_t)0x7ffa460f, (q31_t)0x7ffa27d6, (q31_t)0x7ffa094e, (q31_t)0x7ff9ea76, (q31_t)0x7ff9cb50, (q31_t)0x7ff9abdb, (q31_t)0x7ff98c17, + (q31_t)0x7ff96c04, (q31_t)0x7ff94ba2, (q31_t)0x7ff92af1, (q31_t)0x7ff909f2, (q31_t)0x7ff8e8a3, (q31_t)0x7ff8c705, (q31_t)0x7ff8a519, (q31_t)0x7ff882dd, + (q31_t)0x7ff86053, (q31_t)0x7ff83d79, (q31_t)0x7ff81a51, (q31_t)0x7ff7f6da, (q31_t)0x7ff7d313, (q31_t)0x7ff7aefe, (q31_t)0x7ff78a9a, (q31_t)0x7ff765e7, + (q31_t)0x7ff740e5, (q31_t)0x7ff71b94, (q31_t)0x7ff6f5f4, (q31_t)0x7ff6d005, (q31_t)0x7ff6a9c8, (q31_t)0x7ff6833b, (q31_t)0x7ff65c5f, (q31_t)0x7ff63535, + (q31_t)0x7ff60dbb, (q31_t)0x7ff5e5f3, (q31_t)0x7ff5bddc, (q31_t)0x7ff59576, (q31_t)0x7ff56cc0, (q31_t)0x7ff543bc, (q31_t)0x7ff51a69, (q31_t)0x7ff4f0c7, + (q31_t)0x7ff4c6d6, (q31_t)0x7ff49c96, (q31_t)0x7ff47208, (q31_t)0x7ff4472a, (q31_t)0x7ff41bfd, (q31_t)0x7ff3f082, (q31_t)0x7ff3c4b7, (q31_t)0x7ff3989e, + (q31_t)0x7ff36c36, (q31_t)0x7ff33f7e, (q31_t)0x7ff31278, (q31_t)0x7ff2e523, (q31_t)0x7ff2b77f, (q31_t)0x7ff2898c, (q31_t)0x7ff25b4a, (q31_t)0x7ff22cb9, + (q31_t)0x7ff1fdd9, (q31_t)0x7ff1ceab, (q31_t)0x7ff19f2d, (q31_t)0x7ff16f61, (q31_t)0x7ff13f45, (q31_t)0x7ff10edb, (q31_t)0x7ff0de22, (q31_t)0x7ff0ad19, + (q31_t)0x7ff07bc2, (q31_t)0x7ff04a1c, (q31_t)0x7ff01827, (q31_t)0x7fefe5e4, (q31_t)0x7fefb351, (q31_t)0x7fef806f, (q31_t)0x7fef4d3e, (q31_t)0x7fef19bf, + (q31_t)0x7feee5f0, (q31_t)0x7feeb1d3, (q31_t)0x7fee7d67, (q31_t)0x7fee48ac, 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(q31_t)0x93b90a0, + (q31_t)0x9354c4f, (q31_t)0x92f07f8, (q31_t)0x928c39b, (q31_t)0x9227f39, (q31_t)0x91c3ad2, (q31_t)0x915f664, (q31_t)0x90fb1f1, (q31_t)0x9096d79, + (q31_t)0x90328fb, (q31_t)0x8fce477, (q31_t)0x8f69fee, (q31_t)0x8f05b5f, (q31_t)0x8ea16cb, (q31_t)0x8e3d231, (q31_t)0x8dd8d92, (q31_t)0x8d748ed, + (q31_t)0x8d10443, (q31_t)0x8cabf93, (q31_t)0x8c47ade, (q31_t)0x8be3624, (q31_t)0x8b7f164, (q31_t)0x8b1ac9f, (q31_t)0x8ab67d4, (q31_t)0x8a52304, + (q31_t)0x89ede2f, (q31_t)0x8989955, (q31_t)0x8925475, (q31_t)0x88c0f90, (q31_t)0x885caa5, (q31_t)0x87f85b5, (q31_t)0x87940c1, (q31_t)0x872fbc6, + (q31_t)0x86cb6c7, (q31_t)0x86671c2, (q31_t)0x8602cb9, (q31_t)0x859e7aa, (q31_t)0x853a296, (q31_t)0x84d5d7d, (q31_t)0x847185e, (q31_t)0x840d33b, + (q31_t)0x83a8e12, (q31_t)0x83448e5, (q31_t)0x82e03b2, (q31_t)0x827be7a, (q31_t)0x821793e, (q31_t)0x81b33fc, (q31_t)0x814eeb5, (q31_t)0x80ea969, + (q31_t)0x8086419, (q31_t)0x8021ec3, (q31_t)0x7fbd968, (q31_t)0x7f59409, (q31_t)0x7ef4ea4, (q31_t)0x7e9093b, (q31_t)0x7e2c3cd, (q31_t)0x7dc7e5a, + (q31_t)0x7d638e2, (q31_t)0x7cff365, (q31_t)0x7c9ade4, (q31_t)0x7c3685d, (q31_t)0x7bd22d2, (q31_t)0x7b6dd42, (q31_t)0x7b097ad, (q31_t)0x7aa5214, + (q31_t)0x7a40c76, (q31_t)0x79dc6d3, (q31_t)0x797812b, (q31_t)0x7913b7f, (q31_t)0x78af5ce, (q31_t)0x784b019, (q31_t)0x77e6a5e, (q31_t)0x77824a0, + (q31_t)0x771dedc, (q31_t)0x76b9914, (q31_t)0x7655347, (q31_t)0x75f0d76, (q31_t)0x758c7a1, (q31_t)0x75281c6, (q31_t)0x74c3be7, (q31_t)0x745f604, + (q31_t)0x73fb01c, (q31_t)0x7396a30, (q31_t)0x733243f, (q31_t)0x72cde4a, (q31_t)0x7269851, (q31_t)0x7205253, (q31_t)0x71a0c50, (q31_t)0x713c64a, + (q31_t)0x70d803f, (q31_t)0x7073a2f, (q31_t)0x700f41b, (q31_t)0x6faae03, (q31_t)0x6f467e7, (q31_t)0x6ee21c6, (q31_t)0x6e7dba1, (q31_t)0x6e19578, + (q31_t)0x6db4f4a, (q31_t)0x6d50919, (q31_t)0x6cec2e3, (q31_t)0x6c87ca9, (q31_t)0x6c2366a, (q31_t)0x6bbf028, (q31_t)0x6b5a9e1, (q31_t)0x6af6396, + (q31_t)0x6a91d47, (q31_t)0x6a2d6f4, (q31_t)0x69c909d, (q31_t)0x6964a42, (q31_t)0x69003e3, (q31_t)0x689bd80, (q31_t)0x6837718, (q31_t)0x67d30ad, + (q31_t)0x676ea3d, (q31_t)0x670a3ca, (q31_t)0x66a5d53, (q31_t)0x66416d8, (q31_t)0x65dd058, (q31_t)0x65789d5, (q31_t)0x651434e, (q31_t)0x64afcc3, + (q31_t)0x644b634, (q31_t)0x63e6fa2, (q31_t)0x638290b, (q31_t)0x631e271, (q31_t)0x62b9bd3, (q31_t)0x6255531, (q31_t)0x61f0e8b, (q31_t)0x618c7e1, + (q31_t)0x6128134, (q31_t)0x60c3a83, (q31_t)0x605f3ce, (q31_t)0x5ffad15, (q31_t)0x5f96659, (q31_t)0x5f31f99, (q31_t)0x5ecd8d6, (q31_t)0x5e6920e, + (q31_t)0x5e04b43, (q31_t)0x5da0475, (q31_t)0x5d3bda3, (q31_t)0x5cd76cd, (q31_t)0x5c72ff4, (q31_t)0x5c0e917, (q31_t)0x5baa237, (q31_t)0x5b45b53, + (q31_t)0x5ae146b, (q31_t)0x5a7cd80, (q31_t)0x5a18692, (q31_t)0x59b3fa0, (q31_t)0x594f8aa, (q31_t)0x58eb1b2, (q31_t)0x5886ab5, (q31_t)0x58223b6, + (q31_t)0x57bdcb3, (q31_t)0x57595ac, (q31_t)0x56f4ea2, (q31_t)0x5690795, (q31_t)0x562c085, (q31_t)0x55c7971, (q31_t)0x556325a, (q31_t)0x54feb3f, + (q31_t)0x549a422, (q31_t)0x5435d01, (q31_t)0x53d15dd, (q31_t)0x536ceb5, (q31_t)0x530878a, (q31_t)0x52a405d, (q31_t)0x523f92c, (q31_t)0x51db1f7, + (q31_t)0x5176ac0, (q31_t)0x5112385, (q31_t)0x50adc48, (q31_t)0x5049507, (q31_t)0x4fe4dc3, (q31_t)0x4f8067c, (q31_t)0x4f1bf32, (q31_t)0x4eb77e5, + (q31_t)0x4e53095, (q31_t)0x4dee942, (q31_t)0x4d8a1ec, (q31_t)0x4d25a93, (q31_t)0x4cc1337, (q31_t)0x4c5cbd8, (q31_t)0x4bf8476, (q31_t)0x4b93d11, + (q31_t)0x4b2f5a9, (q31_t)0x4acae3e, (q31_t)0x4a666d1, (q31_t)0x4a01f60, (q31_t)0x499d7ed, (q31_t)0x4939077, (q31_t)0x48d48fe, (q31_t)0x4870182, + (q31_t)0x480ba04, (q31_t)0x47a7282, (q31_t)0x4742afe, (q31_t)0x46de377, (q31_t)0x4679bee, (q31_t)0x4615461, (q31_t)0x45b0cd2, (q31_t)0x454c541, + (q31_t)0x44e7dac, (q31_t)0x4483615, (q31_t)0x441ee7c, (q31_t)0x43ba6df, (q31_t)0x4355f40, (q31_t)0x42f179f, (q31_t)0x428cffb, (q31_t)0x4228854, + (q31_t)0x41c40ab, (q31_t)0x415f8ff, (q31_t)0x40fb151, (q31_t)0x40969a0, (q31_t)0x40321ed, (q31_t)0x3fcda37, (q31_t)0x3f6927f, (q31_t)0x3f04ac4, + (q31_t)0x3ea0307, (q31_t)0x3e3bb48, (q31_t)0x3dd7386, (q31_t)0x3d72bc2, (q31_t)0x3d0e3fb, (q31_t)0x3ca9c32, (q31_t)0x3c45467, (q31_t)0x3be0c99, + (q31_t)0x3b7c4c9, (q31_t)0x3b17cf7, (q31_t)0x3ab3523, (q31_t)0x3a4ed4c, (q31_t)0x39ea573, (q31_t)0x3985d97, (q31_t)0x39215ba, (q31_t)0x38bcdda, + (q31_t)0x38585f8, (q31_t)0x37f3e14, (q31_t)0x378f62e, (q31_t)0x372ae46, (q31_t)0x36c665b, (q31_t)0x3661e6f, (q31_t)0x35fd680, (q31_t)0x3598e8f, + (q31_t)0x353469c, (q31_t)0x34cfea8, (q31_t)0x346b6b1, (q31_t)0x3406eb8, (q31_t)0x33a26bd, (q31_t)0x333dec0, (q31_t)0x32d96c1, (q31_t)0x3274ec0, + (q31_t)0x32106bd, (q31_t)0x31abeb9, (q31_t)0x31476b2, (q31_t)0x30e2ea9, (q31_t)0x307e69f, (q31_t)0x3019e93, (q31_t)0x2fb5684, (q31_t)0x2f50e74, + (q31_t)0x2eec663, (q31_t)0x2e87e4f, (q31_t)0x2e2363a, (q31_t)0x2dbee22, (q31_t)0x2d5a609, (q31_t)0x2cf5def, (q31_t)0x2c915d2, (q31_t)0x2c2cdb4, + (q31_t)0x2bc8594, (q31_t)0x2b63d73, (q31_t)0x2aff54f, (q31_t)0x2a9ad2a, (q31_t)0x2a36504, (q31_t)0x29d1cdc, (q31_t)0x296d4b2, (q31_t)0x2908c87, + (q31_t)0x28a445a, (q31_t)0x283fc2b, (q31_t)0x27db3fb, (q31_t)0x2776bc9, (q31_t)0x2712396, (q31_t)0x26adb62, (q31_t)0x264932b, (q31_t)0x25e4af4, + (q31_t)0x25802bb, (q31_t)0x251ba80, (q31_t)0x24b7244, (q31_t)0x2452a07, (q31_t)0x23ee1c8, (q31_t)0x2389988, (q31_t)0x2325147, (q31_t)0x22c0904, + (q31_t)0x225c0bf, (q31_t)0x21f787a, (q31_t)0x2193033, (q31_t)0x212e7eb, (q31_t)0x20c9fa1, (q31_t)0x2065757, (q31_t)0x2000f0b, (q31_t)0x1f9c6be, + (q31_t)0x1f37e6f, (q31_t)0x1ed3620, (q31_t)0x1e6edcf, (q31_t)0x1e0a57d, (q31_t)0x1da5d2a, (q31_t)0x1d414d6, (q31_t)0x1cdcc80, (q31_t)0x1c7842a, + (q31_t)0x1c13bd2, (q31_t)0x1baf37a, (q31_t)0x1b4ab20, (q31_t)0x1ae62c5, (q31_t)0x1a81a69, (q31_t)0x1a1d20c, (q31_t)0x19b89ae, (q31_t)0x1954150, + (q31_t)0x18ef8f0, (q31_t)0x188b08f, (q31_t)0x182682d, (q31_t)0x17c1fcb, (q31_t)0x175d767, (q31_t)0x16f8f03, (q31_t)0x169469d, (q31_t)0x162fe37, + (q31_t)0x15cb5d0, (q31_t)0x1566d68, (q31_t)0x15024ff, (q31_t)0x149dc96, (q31_t)0x143942b, (q31_t)0x13d4bc0, (q31_t)0x1370354, (q31_t)0x130bae7, + (q31_t)0x12a727a, (q31_t)0x1242a0c, (q31_t)0x11de19d, (q31_t)0x117992e, (q31_t)0x11150be, (q31_t)0x10b084d, (q31_t)0x104bfdb, (q31_t)0xfe7769, + (q31_t)0xf82ef6, (q31_t)0xf1e683, (q31_t)0xeb9e0f, (q31_t)0xe5559b, (q31_t)0xdf0d26, (q31_t)0xd8c4b0, (q31_t)0xd27c3a, (q31_t)0xcc33c3, + (q31_t)0xc5eb4c, (q31_t)0xbfa2d5, (q31_t)0xb95a5d, (q31_t)0xb311e4, (q31_t)0xacc96b, (q31_t)0xa680f2, (q31_t)0xa03878, (q31_t)0x99effe, + (q31_t)0x93a784, (q31_t)0x8d5f09, (q31_t)0x87168e, (q31_t)0x80ce12, (q31_t)0x7a8597, (q31_t)0x743d1a, (q31_t)0x6df49e, (q31_t)0x67ac21, + (q31_t)0x6163a5, (q31_t)0x5b1b27, (q31_t)0x54d2aa, (q31_t)0x4e8a2c, (q31_t)0x4841af, (q31_t)0x41f931, (q31_t)0x3bb0b3, (q31_t)0x356835, + (q31_t)0x2f1fb6, (q31_t)0x28d738, (q31_t)0x228eb9, (q31_t)0x1c463b, (q31_t)0x15fdbc, (q31_t)0xfb53d, (q31_t)0x96cbe, (q31_t)0x3243f +}; + #endif + +/** + @} end of DCT4_IDCT4_Table group + */ + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) +/** + @brief Q15 table for reciprocal +*/ +const q15_t __ALIGNED(4) armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + +/** + @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +/** + @par + Example code for the generation of the floating-point sine table: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ @par + where PI value is 3.14159265358979 + */ +const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = { + 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, + 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, + 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, + 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, + 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, + 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, + 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, + 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, + 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, + 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, + 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, + 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f, + 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f, + 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f, + 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f, + 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f, + 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f, + 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f, + 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f, + 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f, + 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f, + 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f, + 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f, + 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f, + 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f, + 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f, + 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f, + 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f, + 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f, + 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f, + 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f, + 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f, + 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f, + 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f, + 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f, + 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f, + 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, + 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, + 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, + 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, + 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, + 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, + 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, + -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, + -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, + -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, + -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, + -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, + -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, + -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, + -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, + -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, + -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, + -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, + -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, + -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, + -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, + -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, + -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, + -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, + -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, + -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, + -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, + -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, + -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, + -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, + -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, + -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, + -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, + -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, + -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, + -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, + -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, + -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, + -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, + -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, + -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, + -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, + -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, + -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, + -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, + -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, + -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, + -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, + -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, + -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, + -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, + -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, + -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, + -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, + -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, + -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, + -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, + -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +/** + @par + Table values are in Q31 (1.31 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q31 (Fixed point): + (sinTable[i] * pow(2, 31)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 : -0.5); + */ +const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = { + 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L, + 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L, + 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L, + 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L, + 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L, + 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L, + 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L, + 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L, + 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L, + 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L, + 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L, + 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L, + 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L, + 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L, + 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L, + 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L, + 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L, + 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L, + 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L, + 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L, + 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L, + 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L, + 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L, + 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L, + 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L, + 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L, + 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L, + 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L, + 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L, + 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L, + 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L, + 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L, + 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L, + 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L, + 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L, + 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L, + 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L, + 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L, + 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L, + 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L, + 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L, + 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L, + 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L, + -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L, + -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L, + -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L, + -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L, + -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L, + -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L, + -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L, + -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L, + -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L, + -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L, + -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L, + -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L, + -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L, + -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L, + -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L, + -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L, + -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L, + -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L, + -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L, + -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L, + -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L, + -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L, + -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L, + -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L, + -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L, + -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L, + -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L, + -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L, + -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L, + -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L, + -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L, + -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L, + -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L, + -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L, + -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L, + -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L, + -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L, + -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L, + -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L, + -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L, + -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L, + -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L, + -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L, + -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L, + -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L, + -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L, + -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L, + -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0 +}; + +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +/** + @par + Table values are in Q15 (1.15 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q15 (Fixed point): + (sinTable[i] * pow(2, 15)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); + */ +const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = { + 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808, + 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512, + 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279, + 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846, + 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160, + 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170, + 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833, + 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106, + 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957, + 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357, + 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286, + 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729, + 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679, + 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138, + 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114, + 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622, + 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684, + 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330, + 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595, + 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520, + 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151, + 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540, + 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351, + 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612, + 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206, + -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205, + -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127, + -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540, + -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800, + -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868, + -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706, + -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279, + -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557, + -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511, + -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118, + -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357, + -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214, + -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679, + -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746, + -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413, + -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686, + -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572, + -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086, + -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246, + -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073, + -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595, + -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841, + -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846, + -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646, + -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279, + -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393, + -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411, + -2009, -1608, -1206, -804, -402, 0 +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +const q31_t sqrtTable_Q31[256] = { + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5ffffffe, 0x7ffffffa, 0x5e88c596, 0x7a39e2ff, + 0x5d2238d8, 0x74dfa6b1, 0x5bcb268e, 0x6fe69562, + 0x5a827998, 0x6b454dba, 0x5947373a, 0x66f39063, + 0x58187bf8, 0x62ea1669, 0x56f578e6, 0x5f226e5f, + 0x55dd714e, 0x5b96df40, 0x54cfb8b0, 0x58424fca, + 0x53cbb102, 0x552031c7, 0x52d0c92c, 0x522c7048, + 0x51de7bb2, 0x4f6360a9, 0x50f44d86, 0x4cc1b594, + 0x5011cd0a, 0x4a4473f6, 0x4f36911a, 0x47e8e962, + 0x4e62384e, 0x45aca3d0, 0x4d946838, 0x438d6a6a, + 0x4cccccca, 0x41893746, 0x4c0b17c0, 0x3f9e31fa, + 0x4b4f0022, 0x3dcaaac3, 0x4a9841ce, 0x3c0d1660, + 0x49e69d14, 0x3a640a53, 0x4939d654, 0x38ce39a6, + 0x4891b5b2, 0x374a720b, 0x47ee06ba, 0x35d7993c, + 0x474e9830, 0x3474aacc, 0x46b33bc0, 0x3320b60c, + 0x461bc5d2, 0x31dadc4f, 0x45880d4c, 0x30a24f3c, + 0x44f7eb6a, 0x2f764f6a, 0x446b3b92, 0x2e562b0b, + 0x43e1db32, 0x2d413cc9, 0x435ba98a, 0x2c36eab0, + 0x42d887a4, 0x2b36a542, 0x42585824, 0x2a3fe69b, + 0x41daff34, 0x295231b0, 0x41606266, 0x286d118d, + 0x40e868a4, 0x279018c3, 0x4072fa10, 0x26bae0c8, + 0x3ffffffe, 0x25ed0979, 0x3f8f64d2, 0x25263894, + 0x3f2113f8, 0x24661958, 0x3eb4f9d8, 0x23ac5c10, + 0x3e4b03ba, 0x22f8b5bb, 0x3de31fc4, 0x224adfba, + 0x3d7d3cee, 0x21a2977a, 0x3d194ae8, 0x20ff9e30, + 0x3cb73a24, 0x2061b89a, 0x3c56fbba, 0x1fc8aebb, + 0x3bf88166, 0x1f344ba6, 0x3b9bbd80, 0x1ea45d4b, + 0x3b40a2f0, 0x1e18b448, 0x3ae7252e, 0x1d9123b9, + 0x3a8f382c, 0x1d0d8113, 0x3a38d062, 0x1c8da3fb, + 0x39e3e2b6, 0x1c116628, 0x39906482, 0x1b98a33c, + 0x393e4b8a, 0x1b2338aa, 0x38ed8df6, 0x1ab1059a, + 0x389e2250, 0x1a41eace, 0x384fff7a, 0x19d5ca89, + 0x38031cb2, 0x196c887b, 0x37b77184, 0x190609a9, + 0x376cf5ce, 0x18a2345b, 0x3723a1ba, 0x1840f00a, + 0x36db6db6, 0x17e22550, 0x36945276, 0x1785bdd2, + 0x364e48f4, 0x172ba43e, 0x36094a64, 0x16d3c42c, + 0x35c55036, 0x167e0a1f, 0x35825414, 0x162a6372, + 0x35404fde, 0x15d8be4d, 0x34ff3dac, 0x1589099d, + 0x34bf17c4, 0x153b3508, 0x347fd89e, 0x14ef30e4, + 0x34417ade, 0x14a4ee2a, 0x3403f956, 0x145c5e76, + 0x33c74f02, 0x141573fa, 0x338b7706, 0x13d02171, + 0x33506cae, 0x138c5a28, 0x33162b6a, 0x134a11e6, + 0x32dcaed0, 0x13093cee, 0x32a3f294, 0x12c9cffa, + 0x326bf292, 0x128bc034, 0x3234aac0, 0x124f0330, + 0x31fe1736, 0x12138ee5, 0x31c83428, 0x11d959b0, + 0x3192fde6, 0x11a05a45, 0x315e70de, 0x116887b5, + 0x312a8994, 0x1131d960, 0x30f744aa, 0x10fc46fd, + 0x30c49ed6, 0x10c7c88b, 0x309294ea, 0x10945653, + 0x306123cc, 0x1061e8e6, 0x30304878, 0x10307919 +}; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +const q15_t sqrtTable_Q15[256] = { + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5fff, 0x7fff, 0x5e88, 0x7a39, + 0x5d22, 0x74df, 0x5bcb, 0x6fe6, + 0x5a82, 0x6b45, 0x5947, 0x66f3, + 0x5818, 0x62ea, 0x56f5, 0x5f22, + 0x55dd, 0x5b96, 0x54cf, 0x5842, + 0x53cb, 0x5520, 0x52d0, 0x522c, + 0x51de, 0x4f63, 0x50f4, 0x4cc1, + 0x5011, 0x4a44, 0x4f36, 0x47e8, + 0x4e62, 0x45ac, 0x4d94, 0x438d, + 0x4ccc, 0x4189, 0x4c0b, 0x3f9e, + 0x4b4f, 0x3dca, 0x4a98, 0x3c0d, + 0x49e6, 0x3a64, 0x4939, 0x38ce, + 0x4891, 0x374a, 0x47ee, 0x35d7, + 0x474e, 0x3474, 0x46b3, 0x3320, + 0x461b, 0x31da, 0x4588, 0x30a2, + 0x44f7, 0x2f76, 0x446b, 0x2e56, + 0x43e1, 0x2d41, 0x435b, 0x2c36, + 0x42d8, 0x2b36, 0x4258, 0x2a3f, + 0x41da, 0x2952, 0x4160, 0x286d, + 0x40e8, 0x2790, 0x4072, 0x26ba, + 0x3fff, 0x25ed, 0x3f8f, 0x2526, + 0x3f21, 0x2466, 0x3eb4, 0x23ac, + 0x3e4b, 0x22f8, 0x3de3, 0x224a, + 0x3d7d, 0x21a2, 0x3d19, 0x20ff, + 0x3cb7, 0x2061, 0x3c56, 0x1fc8, + 0x3bf8, 0x1f34, 0x3b9b, 0x1ea4, + 0x3b40, 0x1e18, 0x3ae7, 0x1d91, + 0x3a8f, 0x1d0d, 0x3a38, 0x1c8d, + 0x39e3, 0x1c11, 0x3990, 0x1b98, + 0x393e, 0x1b23, 0x38ed, 0x1ab1, + 0x389e, 0x1a41, 0x384f, 0x19d5, + 0x3803, 0x196c, 0x37b7, 0x1906, + 0x376c, 0x18a2, 0x3723, 0x1840, + 0x36db, 0x17e2, 0x3694, 0x1785, + 0x364e, 0x172b, 0x3609, 0x16d3, + 0x35c5, 0x167e, 0x3582, 0x162a, + 0x3540, 0x15d8, 0x34ff, 0x1589, + 0x34bf, 0x153b, 0x347f, 0x14ef, + 0x3441, 0x14a4, 0x3403, 0x145c, + 0x33c7, 0x1415, 0x338b, 0x13d0, + 0x3350, 0x138c, 0x3316, 0x134a, + 0x32dc, 0x1309, 0x32a3, 0x12c9, + 0x326b, 0x128b, 0x3234, 0x124f, + 0x31fe, 0x1213, 0x31c8, 0x11d9, + 0x3192, 0x11a0, 0x315e, 0x1168, + 0x312a, 0x1131, 0x30f7, 0x10fc, + 0x30c4, 0x10c7, 0x3092, 0x1094, + 0x3061, 0x1061, 0x3030, 0x1030 +}; + #endif +#endif /* defined(ARM_MATH_MVEI) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) +/* +ClearAll[tofix]; +tofix[q_][a_] := With[{r = Round[a*2^q]}, + If[r > (2^q - 1), 2^q - 1, r] + ]; + +(* For q = format, 2^nb is length of the table *) +With[{q = 15, nb = 4, q12quarter = 16^^2000}, + With[{shift = Echo[q - nb]}, + Table[tofix[q][1.0/Sqrt[1.0*i/2^q]/8.0], {i, 2^(q - 2), + 2^q + q12quarter - 1, 2^shift}]] + ] // CopyToClipboard + +*/ +const q31_t sqrt_initial_lut_q31[32]={536870912, 506166750, 480191942, 457845052, 438353264, 421156193, \ +405836263, 392075079, 379625062, 368290407, 357913941, 348367849, \ +339546978, 331363921, 323745341, 316629190, 309962566, 303700050, \ +297802400, 292235509, 286969573, 281978417, 277238947, 272730696, \ +268435456, 264336964, 260420644, 256673389, 253083375, 249639903, \ +246333269, 243154642}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) +const q15_t sqrt_initial_lut_q15[16]={8192, 7327, 6689, 6193, 5793, 5461, 5181, 4940, 4730, 4544, 4379, \ +4230, 4096, 3974, 3862, 3759}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) */ + + +#endif /* #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +const float32_t exp_tab[8] = { + (1.f), + (0.0416598916054f), + (0.500000596046f), + (0.0014122662833f), + (1.00000011921f), + (0.00833693705499f), + (0.166665703058f), + (0.000195780929062f), +}; + +const float32_t __logf_lut_f32[8] = { + -2.295614848256274, /*p0*/ + -2.470711633419806, /*p4*/ + -5.686926051100417, /*p2*/ + -0.165253547131978, /*p6*/ + +5.175912446351073, /*p1*/ + +0.844006986174912, /*p5*/ + +4.584458825456749, /*p3*/ + +0.014127821926000 /*p7*/ +}; + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +/* haming weight LUT for bytes */ +#define B2(n) n, n + 1, n + 1, n + 2 +#define B4(n) B2(n) , B2(n + 1), B2(n + 1), B2(n + 2) +#define B6(n) B4(n) , B4(n + 1), B4(n + 1), B4(n + 2) + +// Lookup table that store the reverse of each table +const unsigned char hwLUT[256] = { B6(0), B6(1), B6(1), B6(2) }; + +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c new file mode 100644 index 0000000..d71efb8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c @@ -0,0 +1,12590 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + + +/** + @brief Floating-point Twiddle factors Table Generation +*/ + +/* F16 */ +#if !defined(__CC_ARM) + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h" + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 16 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_16[32] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.923879533f, (float16_t)-0.382683432f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 32 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_32[64] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.980785280f, (float16_t)-0.195090322f +}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 64 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_64[128] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.995184727f, (float16_t)-0.098017140f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 128 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ + +const float16_t twiddleCoefF16_128[256] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.998795456f, (float16_t)-0.049067674f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 256 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_256[512] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999698819f, (float16_t)-0.024541229f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 512 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_512[1024] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + 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(float16_t)-0.985277642f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999924702f, (float16_t)-0.012271538f +}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 1024 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_1024[2048] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + 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(float16_t)-0.242980180f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999981175f, (float16_t)-0.006135885f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 2048 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_2048[4096] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + 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(float16_t)-0.545324988f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999995294f, (float16_t)-0.003067957f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_4096[8192] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999998823f, (float16_t)0.001533980f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999989411f, (float16_t)0.004601926f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999970586f, (float16_t)0.007669829f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999942350f, (float16_t)0.010737659f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999904701f, (float16_t)0.013805389f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999857641f, (float16_t)0.016872988f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999801170f, (float16_t)0.019940429f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999735288f, (float16_t)0.023007681f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999659997f, (float16_t)0.026074718f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999575296f, (float16_t)0.029141509f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999481187f, (float16_t)0.032208025f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999377670f, (float16_t)0.035274239f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999264747f, (float16_t)0.038340120f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999142419f, (float16_t)0.041405641f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999010686f, (float16_t)0.044470772f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998869550f, (float16_t)0.047535484f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998719012f, (float16_t)0.050599749f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998559074f, (float16_t)0.053663538f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998389737f, (float16_t)0.056726821f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998211003f, (float16_t)0.059789571f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998022874f, (float16_t)0.062851758f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997825350f, (float16_t)0.065913353f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997618435f, (float16_t)0.068974328f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997402130f, (float16_t)0.072034653f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997176437f, (float16_t)0.075094301f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996941358f, (float16_t)0.078153242f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996696895f, (float16_t)0.081211447f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996443051f, (float16_t)0.084268888f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996179829f, (float16_t)0.087325535f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.995907229f, (float16_t)0.090381361f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995625256f, (float16_t)0.093436336f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995333912f, (float16_t)0.096490431f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995033199f, (float16_t)0.099543619f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.994723121f, (float16_t)0.102595869f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994403680f, (float16_t)0.105647154f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.994074879f, (float16_t)0.108697444f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993736722f, (float16_t)0.111746711f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993389211f, (float16_t)0.114794927f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993032350f, (float16_t)0.117842062f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.992666142f, (float16_t)0.120888087f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992290591f, (float16_t)0.123932975f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.991905700f, (float16_t)0.126976696f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991511473f, (float16_t)0.130019223f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.991107914f, (float16_t)0.133060525f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990695025f, (float16_t)0.136100575f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990272812f, (float16_t)0.139139344f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989841278f, (float16_t)0.142176804f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989400428f, (float16_t)0.145212925f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988950265f, (float16_t)0.148247679f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988490793f, (float16_t)0.151281038f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.988022017f, (float16_t)0.154312973f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.987543942f, (float16_t)0.157343456f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.987056571f, (float16_t)0.160372457f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.986559910f, (float16_t)0.163399949f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.986053963f, (float16_t)0.166425904f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.985538735f, (float16_t)0.169450291f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.985014231f, (float16_t)0.172473084f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.984480455f, (float16_t)0.175494253f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983937413f, (float16_t)0.178513771f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983385110f, (float16_t)0.181531608f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.982823551f, (float16_t)0.184547737f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.982252741f, (float16_t)0.187562129f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.981672686f, (float16_t)0.190574755f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.981083391f, (float16_t)0.193585587f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.980484862f, (float16_t)0.196594598f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.979877104f, (float16_t)0.199601758f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.979260123f, (float16_t)0.202607039f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.978633924f, (float16_t)0.205610413f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977998515f, (float16_t)0.208611852f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977353900f, (float16_t)0.211611327f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.976700086f, (float16_t)0.214608811f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.976037079f, (float16_t)0.217604275f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.975364885f, (float16_t)0.220597690f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.974683511f, (float16_t)0.223589029f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.973992962f, (float16_t)0.226578264f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.973293246f, (float16_t)0.229565366f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.972584369f, (float16_t)0.232550307f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.971866337f, (float16_t)0.235533059f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.971139158f, (float16_t)0.238513595f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.970402839f, (float16_t)0.241491885f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.969657385f, (float16_t)0.244467903f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.968902805f, (float16_t)0.247441619f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.968139105f, (float16_t)0.250413007f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.967366292f, (float16_t)0.253382037f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.966584374f, (float16_t)0.256348682f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.965793359f, (float16_t)0.259312915f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.964993253f, (float16_t)0.262274707f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.964184064f, (float16_t)0.265234030f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.963365800f, (float16_t)0.268190857f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.962538468f, (float16_t)0.271145160f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.961702077f, (float16_t)0.274096910f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.960856633f, (float16_t)0.277046080f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.960002146f, (float16_t)0.279992643f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.959138622f, (float16_t)0.282936570f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.958266071f, (float16_t)0.285877835f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.957384501f, (float16_t)0.288816408f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.956493919f, (float16_t)0.291752263f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.955594334f, (float16_t)0.294685372f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.954685755f, (float16_t)0.297615707f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.953768190f, (float16_t)0.300543241f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.952841648f, (float16_t)0.303467947f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.951906137f, (float16_t)0.306389795f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.950961666f, (float16_t)0.309308760f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.950008245f, (float16_t)0.312224814f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.949045882f, (float16_t)0.315137929f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.948074586f, (float16_t)0.318048077f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.947094366f, (float16_t)0.320955232f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.946105232f, (float16_t)0.323859367f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.945107193f, (float16_t)0.326760452f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.944100258f, (float16_t)0.329658463f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.943084437f, (float16_t)0.332553370f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.942059740f, (float16_t)0.335445147f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + 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(float16_t)-0.032208025f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999575296f, (float16_t)-0.029141509f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999659997f, (float16_t)-0.026074718f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999735288f, (float16_t)-0.023007681f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999801170f, (float16_t)-0.019940429f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999857641f, (float16_t)-0.016872988f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999904701f, (float16_t)-0.013805389f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999942350f, (float16_t)-0.010737659f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999970586f, (float16_t)-0.007669829f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999989411f, (float16_t)-0.004601926f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999998823f, (float16_t)-0.001533980f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const float16_t twiddleCoefF16_rfft_32[32] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.195090322f, (float16_t)-0.980785280f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64) +const float16_t twiddleCoefF16_rfft_64[64] = { + (float16_t)0.000000000000000f, (float16_t)1.000000000000000f, + (float16_t)0.098017140329561f, (float16_t)0.995184726672197f, + (float16_t)0.195090322016128f, (float16_t)0.980785280403230f, + (float16_t)0.290284677254462f, (float16_t)0.956940335732209f, + (float16_t)0.382683432365090f, (float16_t)0.923879532511287f, + (float16_t)0.471396736825998f, (float16_t)0.881921264348355f, + (float16_t)0.555570233019602f, (float16_t)0.831469612302545f, + (float16_t)0.634393284163645f, (float16_t)0.773010453362737f, + (float16_t)0.707106781186547f, (float16_t)0.707106781186548f, + (float16_t)0.773010453362737f, (float16_t)0.634393284163645f, + (float16_t)0.831469612302545f, (float16_t)0.555570233019602f, + (float16_t)0.881921264348355f, (float16_t)0.471396736825998f, + (float16_t)0.923879532511287f, (float16_t)0.382683432365090f, + (float16_t)0.956940335732209f, (float16_t)0.290284677254462f, + (float16_t)0.980785280403230f, (float16_t)0.195090322016128f, + (float16_t)0.995184726672197f, (float16_t)0.098017140329561f, + (float16_t)1.000000000000000f, (float16_t)0.000000000000000f, + (float16_t)0.995184726672197f, (float16_t)-0.098017140329561f, + (float16_t)0.980785280403230f, (float16_t)-0.195090322016128f, + (float16_t)0.956940335732209f, (float16_t)-0.290284677254462f, + (float16_t)0.923879532511287f, (float16_t)-0.382683432365090f, + (float16_t)0.881921264348355f, (float16_t)-0.471396736825998f, + (float16_t)0.831469612302545f, (float16_t)-0.555570233019602f, + (float16_t)0.773010453362737f, (float16_t)-0.634393284163645f, + (float16_t)0.707106781186548f, (float16_t)-0.707106781186547f, + (float16_t)0.634393284163645f, (float16_t)-0.773010453362737f, + (float16_t)0.555570233019602f, (float16_t)-0.831469612302545f, + (float16_t)0.471396736825998f, (float16_t)-0.881921264348355f, + (float16_t)0.382683432365090f, (float16_t)-0.923879532511287f, + (float16_t)0.290284677254462f, (float16_t)-0.956940335732209f, + (float16_t)0.195090322016129f, (float16_t)-0.980785280403230f, + (float16_t)0.098017140329561f, (float16_t)-0.995184726672197f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128) +const float16_t twiddleCoefF16_rfft_128[128] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.049067674f, (float16_t)-0.998795456f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256) +const float16_t twiddleCoefF16_rfft_256[256] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.024541229f, (float16_t)-0.999698819f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512) +const float16_t twiddleCoefF16_rfft_512[512] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.012271538f, (float16_t)-0.999924702f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024) +const float16_t twiddleCoefF16_rfft_1024[1024] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + 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(float16_t)-0.873094978f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.006135885f, (float16_t)-0.999981175f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048) +const float16_t twiddleCoefF16_rfft_2048[2048] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.357030961f, 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(float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.003067957f, (float16_t)-0.999995294f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096) +const float16_t twiddleCoefF16_rfft_4096[4096] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.001533980f, (float16_t)0.999998823f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.004601926f, (float16_t)0.999989411f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.007669829f, (float16_t)0.999970586f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.010737659f, (float16_t)0.999942350f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.013805389f, (float16_t)0.999904701f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.016872988f, (float16_t)0.999857641f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.019940429f, (float16_t)0.999801170f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.023007681f, (float16_t)0.999735288f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.026074718f, (float16_t)0.999659997f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.029141509f, (float16_t)0.999575296f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.032208025f, (float16_t)0.999481187f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.035274239f, (float16_t)0.999377670f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.038340120f, (float16_t)0.999264747f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.041405641f, (float16_t)0.999142419f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.044470772f, (float16_t)0.999010686f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.047535484f, (float16_t)0.998869550f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.050599749f, (float16_t)0.998719012f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.053663538f, (float16_t)0.998559074f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.056726821f, (float16_t)0.998389737f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.059789571f, (float16_t)0.998211003f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.062851758f, (float16_t)0.998022874f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.065913353f, (float16_t)0.997825350f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.068974328f, (float16_t)0.997618435f, + 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(float16_t)0.136100575f, (float16_t)-0.990695025f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.133060525f, (float16_t)-0.991107914f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.130019223f, (float16_t)-0.991511473f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.126976696f, (float16_t)-0.991905700f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.123932975f, (float16_t)-0.992290591f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.120888087f, (float16_t)-0.992666142f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.117842062f, (float16_t)-0.993032350f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.114794927f, (float16_t)-0.993389211f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.111746711f, (float16_t)-0.993736722f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.108697444f, (float16_t)-0.994074879f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.105647154f, (float16_t)-0.994403680f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.102595869f, (float16_t)-0.994723121f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.099543619f, (float16_t)-0.995033199f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.096490431f, (float16_t)-0.995333912f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.093436336f, (float16_t)-0.995625256f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.090381361f, (float16_t)-0.995907229f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.087325535f, (float16_t)-0.996179829f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.084268888f, (float16_t)-0.996443051f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.081211447f, (float16_t)-0.996696895f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.078153242f, (float16_t)-0.996941358f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.075094301f, (float16_t)-0.997176437f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.072034653f, (float16_t)-0.997402130f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.068974328f, (float16_t)-0.997618435f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.065913353f, (float16_t)-0.997825350f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.062851758f, (float16_t)-0.998022874f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.059789571f, (float16_t)-0.998211003f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.056726821f, (float16_t)-0.998389737f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.053663538f, (float16_t)-0.998559074f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.050599749f, (float16_t)-0.998719012f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.047535484f, (float16_t)-0.998869550f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.044470772f, (float16_t)-0.999010686f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.041405641f, (float16_t)-0.999142419f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.038340120f, (float16_t)-0.999264747f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.035274239f, (float16_t)-0.999377670f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.032208025f, (float16_t)-0.999481187f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.029141509f, (float16_t)-0.999575296f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.026074718f, (float16_t)-0.999659997f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.023007681f, (float16_t)-0.999735288f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.019940429f, (float16_t)-0.999801170f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.016872988f, (float16_t)-0.999857641f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.013805389f, (float16_t)-0.999904701f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.010737659f, (float16_t)-0.999942350f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.007669829f, (float16_t)-0.999970586f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.004601926f, (float16_t)-0.999989411f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.001533980f, (float16_t)-0.999998823f +}; + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALL_TABLES) */ + +#endif /*!defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)*/ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +const float16_t exp_tab_f16[8] = { + (1.f16), + (0.0416598916054f16), + (0.500000596046f16), + (0.00138889f16), + (1.00000011921f16), + (0.00833693705499f16), + (0.166665703058f16), + (0.000195780929062f16), +}; + +const float16_t __logf_lut_f16[8] = { + -2.295614848256274f16, /*p0*/ + -2.470711633419806f16, /*p4*/ + -5.686926051100417f16, /*p2*/ + -0.165253547131978f16, /*p6*/ + +5.175912446351073f16, /*p1*/ + +0.844006986174912f16, /*p5*/ + +4.584458825456749f16, /*p3*/ + +0.014127821926000f16 /*p7*/ +}; + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif /* Not ARM AC5 */ + + +/** + @} end of CFFT_CIFFT group +*/ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs.c new file mode 100644 index 0000000..30b810a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs.c @@ -0,0 +1,658 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +/* Floating-point structs */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len16 = { + 16, (const float64_t *)twiddleCoefF64_16, armBitRevIndexTableF64_16, ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len32 = { + 32, (const float64_t *)twiddleCoefF64_32, armBitRevIndexTableF64_32, ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len64 = { + 64, (const float64_t *)twiddleCoefF64_64, armBitRevIndexTableF64_64, ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len128 = { + 128, (const float64_t *)twiddleCoefF64_128, armBitRevIndexTableF64_128, ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len256 = { + 256, (const float64_t *)twiddleCoefF64_256, armBitRevIndexTableF64_256, ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len512 = { + 512, (const float64_t *)twiddleCoefF64_512, armBitRevIndexTableF64_512, ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024 = { + 1024, (const float64_t *)twiddleCoefF64_1024, armBitRevIndexTableF64_1024, ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048 = { + 2048, (const float64_t *)twiddleCoefF64_2048, armBitRevIndexTableF64_2048, ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT64_4096)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096 = { + 4096, (const float64_t *)twiddleCoefF64_4096, armBitRevIndexTableF64_4096, ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH +}; +#endif + +/* Floating-point structs */ +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH +}; +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH +}; +#endif + +#endif /* !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + +/* Fixed-point structs */ + +#if !defined(ARM_MATH_MVEI) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f32 must be used. + + +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = { + 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = { + 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = { + 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = { + 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = { + 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = { + 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = { + 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = { + 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = { + 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = { + 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = { + 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = { + 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = { + 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = { + 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = { + 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = { + 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = { + 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = { + 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + +#endif /* !defined(ARM_MATH_MVEI) */ + +/* Structure for real-value inputs */ +/* Double precision strucs */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len32 = { + { 16, (const float64_t *)twiddleCoefF64_16, armBitRevIndexTableF64_16, ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH }, + 32U, + (float64_t *)twiddleCoefF64_rfft_32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len64 = { + { 32, (const float64_t *)twiddleCoefF64_32, armBitRevIndexTableF64_32, ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH }, + 64U, + (float64_t *)twiddleCoefF64_rfft_64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len128 = { + { 64, (const float64_t *)twiddleCoefF64_64, armBitRevIndexTableF64_64, ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH }, + 128U, + (float64_t *)twiddleCoefF64_rfft_128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len256 = { + { 128, (const float64_t *)twiddleCoefF64_128, armBitRevIndexTableF64_128, ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH }, + 256U, + (float64_t *)twiddleCoefF64_rfft_256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len512 = { + { 256, (const float64_t *)twiddleCoefF64_256, armBitRevIndexTableF64_256, ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH }, + 512U, + (float64_t *)twiddleCoefF64_rfft_512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len1024 = { + { 512, (const float64_t *)twiddleCoefF64_512, armBitRevIndexTableF64_512, ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH }, + 1024U, + (float64_t *)twiddleCoefF64_rfft_1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len2048 = { + { 1024, (const float64_t *)twiddleCoefF64_1024, armBitRevIndexTableF64_1024, ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH }, + 2048U, + (float64_t *)twiddleCoefF64_rfft_2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT64_4096) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len4096 = { + { 2048, (const float64_t *)twiddleCoefF64_2048, armBitRevIndexTableF64_2048, ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH }, + 4096U, + (float64_t *)twiddleCoefF64_rfft_4096 +}; +#endif + +/* Floating-point structs */ + +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = { + { 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH }, + 32U, + (float32_t *)twiddleCoef_rfft_32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = { + { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH }, + 64U, + (float32_t *)twiddleCoef_rfft_64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = { + { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH }, + 128U, + (float32_t *)twiddleCoef_rfft_128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = { + { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH }, + 256U, + (float32_t *)twiddleCoef_rfft_256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = { + { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH }, + 512U, + (float32_t *)twiddleCoef_rfft_512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = { + { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH }, + 1024U, + (float32_t *)twiddleCoef_rfft_1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = { + { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH }, + 2048U, + (float32_t *)twiddleCoef_rfft_2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = { + { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH }, + 4096U, + (float32_t *)twiddleCoef_rfft_4096 +}; +#endif + +#endif /* #if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + +/* Fixed-point structs */ +/* q31_t */ + +#if !defined(ARM_MATH_MVEI) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f32 must be used. + + +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = { + 32U, + 0, + 1, + 256U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = { + 64U, + 0, + 1, + 128U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = { + 128U, + 0, + 1, + 64U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = { + 256U, + 0, + 1, + 32U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = { + 512U, + 0, + 1, + 16U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = { + 1024U, + 0, + 1, + 8U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = { + 2048U, + 0, + 1, + 4U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = { + 4096U, + 0, + 1, + 2U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = { + 8192U, + 0, + 1, + 1U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len4096 +}; +#endif + + + +/* q15_t */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = { + 32U, + 0, + 1, + 256U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = { + 64U, + 0, + 1, + 128U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = { + 128U, + 0, + 1, + 64U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = { + 256U, + 0, + 1, + 32U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = { + 512U, + 0, + 1, + 16U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = { + 1024U, + 0, + 1, + 8U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = { + 2048U, + 0, + 1, + 4U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = { + 4096U, + 0, + 1, + 2U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = { + 8192U, + 0, + 1, + 1U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len4096 +}; +#endif + +#endif /* !defined(ARM_MATH_MVEI) */ + + +#endif + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c new file mode 100644 index 0000000..603e423 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c @@ -0,0 +1,124 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs_f16.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h" + + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +/* Floating-point structs */ +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) + + +/* + +Those structures cannot be used to initialize the MVE version of the FFT F32 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f16 must be used. + + +*/ + +#if !defined(__CC_ARM) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len16 = { + 16, twiddleCoefF16_16, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len32 = { + 32, twiddleCoefF16_32, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len64 = { + 64, twiddleCoefF16_64, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len128 = { + 128, twiddleCoefF16_128, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len256 = { + 256, twiddleCoefF16_256, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len512 = { + 512, twiddleCoefF16_512, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024 = { + 1024, twiddleCoefF16_1024, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048 = { + 2048, twiddleCoefF16_2048, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096 = { + 4096, twiddleCoefF16_4096, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif +#endif + +#endif /* !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + + +#endif + +#endif + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c new file mode 100644 index 0000000..ba5aa16 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c @@ -0,0 +1,6537 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types.h" + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]={ +0,0,}; + +float32_t rearranged_twiddle_stride1_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.92387950420379638672f, +0.38268342614173889160f,0.70710676908493041992f,0.70710676908493041992f, +0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.70710676908493041992f, +0.70710676908493041992f,0.00000000000000006123f,1.00000000000000000000f, +-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.38268342614173889160f, +0.92387950420379638672f,-0.70710676908493041992f,0.70710676908493041992f, +-0.92387950420379638672f,-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]={ +0,32,0,}; + +float32_t rearranged_twiddle_stride1_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.99518471956253051758f, +0.09801714122295379639f,0.98078525066375732422f,0.19509032368659973145f, +0.95694035291671752930f,0.29028466343879699707f,0.92387950420379638672f, +0.38268342614173889160f,0.88192129135131835938f,0.47139674425125122070f, +0.83146959543228149414f,0.55557024478912353516f,0.77301043272018432617f, +0.63439327478408813477f,0.70710676908493041992f,0.70710676908493041992f, +0.63439327478408813477f,0.77301043272018432617f,0.55557024478912353516f, +0.83146959543228149414f,0.47139674425125122070f,0.88192129135131835938f, +0.38268342614173889160f,0.92387950420379638672f,0.29028466343879699707f, +0.95694035291671752930f,0.19509032368659973145f,0.98078525066375732422f, +0.09801714122295379639f,0.99518471956253051758f,1.00000000000000000000f, +0.00000000000000000000f,0.92387950420379638672f,0.38268342614173889160f, +0.70710676908493041992f,0.70710676908493041992f,0.38268342614173889160f, +0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.98078525066375732422f, +0.19509032368659973145f,0.92387950420379638672f,0.38268342614173889160f, +0.83146959543228149414f,0.55557024478912353516f,0.70710676908493041992f, +0.70710676908493041992f,0.55557024478912353516f,0.83146959543228149414f, +0.38268342614173889160f,0.92387950420379638672f,0.19509032368659973145f, +0.98078525066375732422f,0.00000000000000006123f,1.00000000000000000000f, +-0.19509032368659973145f,0.98078525066375732422f,-0.38268342614173889160f, +0.92387950420379638672f,-0.55557024478912353516f,0.83146959543228149414f, +-0.70710676908493041992f,0.70710676908493041992f,-0.83146959543228149414f, +0.55557024478912353516f,-0.92387950420379638672f,0.38268342614173889160f, +-0.98078525066375732422f,0.19509032368659973145f,1.00000000000000000000f, +0.00000000000000000000f,0.70710676908493041992f,0.70710676908493041992f, +0.00000000000000006123f,1.00000000000000000000f,-0.70710676908493041992f, +0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.95694035291671752930f, +0.29028466343879699707f,0.83146959543228149414f,0.55557024478912353516f, +0.63439327478408813477f,0.77301043272018432617f,0.38268342614173889160f, +0.92387950420379638672f,0.09801714122295379639f,0.99518471956253051758f, +-0.19509032368659973145f,0.98078525066375732422f,-0.47139674425125122070f, +0.88192129135131835938f,-0.70710676908493041992f,0.70710676908493041992f, +-0.88192129135131835938f,0.47139674425125122070f,-0.98078525066375732422f, +0.19509032368659973145f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.29028466343879699707f,-0.95694035291671752930f,1.00000000000000000000f, +0.00000000000000000000f,0.38268342614173889160f,0.92387950420379638672f, +-0.70710676908493041992f,0.70710676908493041992f,-0.92387950420379638672f, +-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]={ +0,128,160,0,}; + +float32_t rearranged_twiddle_stride1_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99969881772994995117f, +0.02454122900962829590f,0.99879544973373413086f,0.04906767606735229492f, +0.99729043245315551758f,0.07356456667184829712f,0.99518471956253051758f, +0.09801714122295379639f,0.99247956275939941406f,0.12241067737340927124f, +0.98917651176452636719f,0.14673046767711639404f,0.98527765274047851562f, +0.17096188664436340332f,0.98078525066375732422f,0.19509032368659973145f, +0.97570210695266723633f,0.21910123527050018311f,0.97003126144409179688f, +0.24298018217086791992f,0.96377605199813842773f,0.26671275496482849121f, +0.95694035291671752930f,0.29028466343879699707f,0.94952815771102905273f, +0.31368175148963928223f,0.94154405593872070312f,0.33688986301422119141f, +0.93299281597137451172f,0.35989505052566528320f,0.92387950420379638672f, +0.38268342614173889160f,0.91420978307723999023f,0.40524131059646606445f, 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+0.78834640979766845703f,0.59569931030273437500f,0.80320751667022705078f, +0.57580816745758056641f,0.81758481264114379883f,0.55557024478912353516f, +0.83146959543228149414f,0.53499764204025268555f,0.84485357999801635742f, +0.51410275697708129883f,0.85772860050201416016f,0.49289819598197937012f, +0.87008696794509887695f,0.47139674425125122070f,0.88192129135131835938f, +0.44961133599281311035f,0.89322429895401000977f,0.42755508422851562500f, +0.90398931503295898438f,0.40524131059646606445f,0.91420978307723999023f, +0.38268342614173889160f,0.92387950420379638672f,0.35989505052566528320f, +0.93299281597137451172f,0.33688986301422119141f,0.94154405593872070312f, +0.31368175148963928223f,0.94952815771102905273f,0.29028466343879699707f, +0.95694035291671752930f,0.26671275496482849121f,0.96377605199813842773f, +0.24298018217086791992f,0.97003126144409179688f,0.21910123527050018311f, +0.97570210695266723633f,0.19509032368659973145f,0.98078525066375732422f, +0.17096188664436340332f,0.98527765274047851562f,0.14673046767711639404f, +0.98917651176452636719f,0.12241067737340927124f,0.99247956275939941406f, +0.09801714122295379639f,0.99518471956253051758f,0.07356456667184829712f, +0.99729043245315551758f,0.04906767606735229492f,0.99879544973373413086f, +0.02454122900962829590f,0.99969881772994995117f,1.00000000000000000000f, +0.00000000000000000000f,0.99518471956253051758f,0.09801714122295379639f, +0.98078525066375732422f,0.19509032368659973145f,0.95694035291671752930f, +0.29028466343879699707f,0.92387950420379638672f,0.38268342614173889160f, +0.88192129135131835938f,0.47139674425125122070f,0.83146959543228149414f, +0.55557024478912353516f,0.77301043272018432617f,0.63439327478408813477f, +0.70710676908493041992f,0.70710676908493041992f,0.63439327478408813477f, +0.77301043272018432617f,0.55557024478912353516f,0.83146959543228149414f, +0.47139674425125122070f,0.88192129135131835938f,0.38268342614173889160f, +0.92387950420379638672f,0.29028466343879699707f,0.95694035291671752930f, +0.19509032368659973145f,0.98078525066375732422f,0.09801714122295379639f, +0.99518471956253051758f,1.00000000000000000000f,0.00000000000000000000f, +0.92387950420379638672f,0.38268342614173889160f,0.70710676908493041992f, +0.70710676908493041992f,0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99879544973373413086f, +0.04906767606735229492f,0.99518471956253051758f,0.09801714122295379639f, +0.98917651176452636719f,0.14673046767711639404f,0.98078525066375732422f, +0.19509032368659973145f,0.97003126144409179688f,0.24298018217086791992f, +0.95694035291671752930f,0.29028466343879699707f,0.94154405593872070312f, +0.33688986301422119141f,0.92387950420379638672f,0.38268342614173889160f, +0.90398931503295898438f,0.42755508422851562500f,0.88192129135131835938f, +0.47139674425125122070f,0.85772860050201416016f,0.51410275697708129883f, +0.83146959543228149414f,0.55557024478912353516f,0.80320751667022705078f, +0.59569931030273437500f,0.77301043272018432617f,0.63439327478408813477f, +0.74095112085342407227f,0.67155897617340087891f,0.70710676908493041992f, +0.70710676908493041992f,0.67155897617340087891f,0.74095112085342407227f, +0.63439327478408813477f,0.77301043272018432617f,0.59569931030273437500f, +0.80320751667022705078f,0.55557024478912353516f,0.83146959543228149414f, +0.51410275697708129883f,0.85772860050201416016f,0.47139674425125122070f, +0.88192129135131835938f,0.42755508422851562500f,0.90398931503295898438f, +0.38268342614173889160f,0.92387950420379638672f,0.33688986301422119141f, +0.94154405593872070312f,0.29028466343879699707f,0.95694035291671752930f, +0.24298018217086791992f,0.97003126144409179688f,0.19509032368659973145f, +0.98078525066375732422f,0.14673046767711639404f,0.98917651176452636719f, +0.09801714122295379639f,0.99518471956253051758f,0.04906767606735229492f, +0.99879544973373413086f,0.00000000000000006123f,1.00000000000000000000f, +-0.04906767606735229492f,0.99879544973373413086f,-0.09801714122295379639f, +0.99518471956253051758f,-0.14673046767711639404f,0.98917651176452636719f, +-0.19509032368659973145f,0.98078525066375732422f,-0.24298018217086791992f, +0.97003126144409179688f,-0.29028466343879699707f,0.95694035291671752930f, +-0.33688986301422119141f,0.94154405593872070312f,-0.38268342614173889160f, +0.92387950420379638672f,-0.42755508422851562500f,0.90398931503295898438f, +-0.47139674425125122070f,0.88192129135131835938f,-0.51410275697708129883f, +0.85772860050201416016f,-0.55557024478912353516f,0.83146959543228149414f, +-0.59569931030273437500f,0.80320751667022705078f,-0.63439327478408813477f, +0.77301043272018432617f,-0.67155897617340087891f,0.74095112085342407227f, +-0.70710676908493041992f,0.70710676908493041992f,-0.74095112085342407227f, +0.67155897617340087891f,-0.77301043272018432617f,0.63439327478408813477f, +-0.80320751667022705078f,0.59569931030273437500f,-0.83146959543228149414f, +0.55557024478912353516f,-0.85772860050201416016f,0.51410275697708129883f, +-0.88192129135131835938f,0.47139674425125122070f,-0.90398931503295898438f, +0.42755508422851562500f,-0.92387950420379638672f,0.38268342614173889160f, +-0.94154405593872070312f,0.33688986301422119141f,-0.95694035291671752930f, +0.29028466343879699707f,-0.97003126144409179688f,0.24298018217086791992f, +-0.98078525066375732422f,0.19509032368659973145f,-0.98917651176452636719f, +0.14673046767711639404f,-0.99518471956253051758f,0.09801714122295379639f, +-0.99879544973373413086f,0.04906767606735229492f,1.00000000000000000000f, +0.00000000000000000000f,0.98078525066375732422f,0.19509032368659973145f, +0.92387950420379638672f,0.38268342614173889160f,0.83146959543228149414f, +0.55557024478912353516f,0.70710676908493041992f,0.70710676908493041992f, +0.55557024478912353516f,0.83146959543228149414f,0.38268342614173889160f, +0.92387950420379638672f,0.19509032368659973145f,0.98078525066375732422f, +0.00000000000000006123f,1.00000000000000000000f,-0.19509032368659973145f, +0.98078525066375732422f,-0.38268342614173889160f,0.92387950420379638672f, +-0.55557024478912353516f,0.83146959543228149414f,-0.70710676908493041992f, +0.70710676908493041992f,-0.83146959543228149414f,0.55557024478912353516f, +-0.92387950420379638672f,0.38268342614173889160f,-0.98078525066375732422f, +0.19509032368659973145f,1.00000000000000000000f,0.00000000000000000000f, +0.70710676908493041992f,0.70710676908493041992f,0.00000000000000006123f, +1.00000000000000000000f,-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99729043245315551758f, +0.07356456667184829712f,0.98917651176452636719f,0.14673046767711639404f, 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+-0.99879544973373413086f,0.04906767606735229492f,-0.99969881772994995117f, +-0.02454122900962829590f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.98527765274047851562f,-0.17096188664436340332f,-0.97003126144409179688f, +-0.24298018217086791992f,-0.94952815771102905273f,-0.31368175148963928223f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.89322429895401000977f, +-0.44961133599281311035f,-0.85772860050201416016f,-0.51410275697708129883f, +-0.81758481264114379883f,-0.57580816745758056641f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.72424709796905517578f,-0.68954056501388549805f, +-0.67155897617340087891f,-0.74095112085342407227f,-0.61523157358169555664f, +-0.78834640979766845703f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.49289819598197937012f,-0.87008696794509887695f,-0.42755508422851562500f, +-0.90398931503295898438f,-0.35989505052566528320f,-0.93299281597137451172f, +-0.29028466343879699707f,-0.95694035291671752930f,-0.21910123527050018311f, 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+0.19509032368659973145f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.29028466343879699707f,-0.95694035291671752930f,1.00000000000000000000f, +0.00000000000000000000f,0.38268342614173889160f,0.92387950420379638672f, +-0.70710676908493041992f,0.70710676908493041992f,-0.92387950420379638672f, +-0.38268342614173889160f,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]={ +0,0,}; + +q31_t rearranged_twiddle_stride1_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D, +0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666, +0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3, +0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]={ +0,32,0,}; + +q31_t rearranged_twiddle_stride1_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40,0xE70747C4,0x7A7D055B, +0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590,0x6A6D98A4,0xB8E31319, +0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94,0x9D0DFE54,0x471CECE7, +0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3,0x25280C5E,0x8582FAA5, +0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF,0x00000000,0x7641AF3D, +0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D,0xCF043AB3,0x6A6D98A4, +0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C,0x30FBC54D,0x89BE50C3, +0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4,0x8275A0C0,0xCF043AB3, +0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666,0x9592675C,0xB8E31319, +0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF,0x00000000,0x5A82799A, +0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4,0xB8E31319,0x5133CC94, +0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971,0xE70747C4,0x8275A0C0, +0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A,0xC3A94590,0x8275A0C0, +0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D,0x9D0DFE54,0x5133CC94, +0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF,0x00000000,0x30FBC54D, +0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]={ +0,128,160,0,}; + +q31_t rearranged_twiddle_stride1_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684,0x7FA736B4, +0xF6956FB7,0x7F62368F,0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC,0xED37EF91, +0x7E1D93EA,0xEA1DEBBB,0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96,0x7C29FBEE, +0xE0E60685,0x7B5D039E,0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1,0xD7D946D8, +0x78848414,0xD4E0CB15,0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3,0x7504D345, +0xCC210D79,0x73B5EBD1,0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6,0xC3A94590, +0x6F5F02B2,0xC0E8B648,0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0,0x6A6D98A4, +0xB8E31319,0x68A69E81,0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926,0xB140175B, +0x62F201AC,0xAECC336C,0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E,0x5CB420E0, +0xA7BD22AC,0x5A82799A,0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2,0xA1288376, +0x539B2AF0,0x9F13C7D0,0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA,0x4C3FDFF4, +0x99307EE0,0x49B41533,0x9759617F,0x471CECE7,0x9592675C,0x447ACD50,0x93DBD6A0, +0x41CE1E65,0x9235F2EC,0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A,0x398CDD32, +0x8DAAD37B,0x36BA2014,0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D,0x89BE50C3, +0x2E110A62,0x8893B125,0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F,0x25280C5E, +0x8582FAA5,0x2223A4C5,0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A,0x831C314E, +0x18F8B83C,0x8275A0C0,0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04,0x0FAB272B, +0x80F66E3C,0x0C8BD35E,0x809DC971,0x096A9049,0x8058C94C,0x0647D97C,0x80277872, +0x03242ABF,0x8009DE7E,0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40, +0xE70747C4,0x7A7D055B,0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590, +0x6A6D98A4,0xB8E31319,0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94, +0x9D0DFE54,0x471CECE7,0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3, +0x25280C5E,0x8582FAA5,0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF, +0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2,0x7E9D55FC, +0xED37EF91,0x7D8A5F40,0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B,0xDAD7F3A2, +0x78848414,0xD4E0CB15,0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC,0x70E2CBC6, +0xC3A94590,0x6DCA0D14,0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120,0xB3C0200C, +0x62F201AC,0xAECC336C,0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666,0x55F5A4D2, +0xA1288376,0x5133CC94,0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7,0x9592675C, +0x41CE1E65,0x9235F2EC,0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F,0x30FBC54D, +0x89BE50C3,0x2B1F34EB,0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B,0x83D60412, +0x18F8B83C,0x8275A0C0,0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971,0x0647D97C, +0x80277872,0x00000000,0x80000000,0xF9B82684,0x80277872,0xF3742CA2,0x809DC971, +0xED37EF91,0x8162AA04,0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412,0xDAD7F3A2, +0x8582FAA5,0xD4E0CB15,0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC,0x8C4A142F, +0xC3A94590,0x8F1D343A,0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C,0xB3C0200C, +0x99307EE0,0xAECC336C,0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666,0xA57D8666, +0xA1288376,0xAA0A5B2E,0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C,0x9592675C, +0xB8E31319,0x9235F2EC,0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F,0xC945DFEC, +0x89BE50C3,0xCF043AB3,0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2,0x83D60412, +0xE0E60685,0x8275A0C0,0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971,0xF3742CA2, +0x80277872,0xF9B82684,0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D, +0xCF043AB3,0x6A6D98A4,0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C, +0x30FBC54D,0x89BE50C3,0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4, +0x8275A0C0,0xCF043AB3,0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666, +0x9592675C,0xB8E31319,0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF, +0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91,0x7CE3CEB2, +0xE3F47D96,0x7A7D055B,0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1,0xC945DFEC, +0x6F5F02B2,0xC0E8B648,0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B,0x5ED77C8A, +0xAA0A5B2E,0x5842DD54,0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533,0x9759617F, +0x41CE1E65,0x9235F2EC,0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3,0x2826B928, +0x8675DC4F,0x1F19F97B,0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E,0x809DC971, +0x03242ABF,0x8009DE7E,0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C,0xE70747C4, +0x8275A0C0,0xDDDC5B3B,0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79,0x8AFB2CBB, +0xC3A94590,0x8F1D343A,0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0,0xAC64D510, +0x9F13C7D0,0xA57D8666,0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0,0xB3C0200C, +0x93DBD6A0,0xBB8532B0,0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79,0x877B7BEC, +0xD4E0CB15,0x84A2FC62,0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C,0xF054D8D5, +0x80277872,0xF9B82684,0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E,0x81E26C16, +0x15E21445,0x83D60412,0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3,0x30FBC54D, +0x8DAAD37B,0x398CDD32,0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533,0x9D0DFE54, +0x5133CC94,0xA34BDF20,0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B,0x64E88926, +0xB8E31319,0x6A6D98A4,0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1,0xD1EEF59E, +0x776C4EDB,0xDAD7F3A2,0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91,0x7E9D55FC, +0xF6956FB7,0x7FA736B4,0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4, +0xB8E31319,0x5133CC94,0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971, +0xE70747C4,0x8275A0C0,0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A, +0xC3A94590,0x8275A0C0,0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D, +0x9D0DFE54,0x5133CC94,0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF, +0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]={ +0,512,640,672,0,}; + +q31_t rearranged_twiddle_stride1_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFF6216,0xFF36F078,0x7FFD885A,0xFE6DE2E0,0x7FFA72D1, +0xFDA4D929,0x7FF62182,0xFCDBD541,0x7FF09478,0xFC12D91A,0x7FE9CBC0,0xFB49E6A3, +0x7FE1C76B,0xFA80FFCB,0x7FD8878E,0xF9B82684,0x7FCE0C3E,0xF8EF5CBB,0x7FC25596, +0xF826A462,0x7FB563B3,0xF75DFF66,0x7FA736B4,0xF6956FB7,0x7F97CEBD,0xF5CCF743, +0x7F872BF3,0xF50497FB,0x7F754E80,0xF43C53CB,0x7F62368F,0xF3742CA2,0x7F4DE451, +0xF2AC246E,0x7F3857F6,0xF1E43D1C,0x7F2191B4,0xF11C789A,0x7F0991C4,0xF054D8D5, +0x7EF05860,0xEF8D5FB8,0x7ED5E5C6,0xEEC60F31,0x7EBA3A39,0xEDFEE92B,0x7E9D55FC, +0xED37EF91,0x7E7F3957,0xEC71244F,0x7E5FE493,0xEBAA894F,0x7E3F57FF,0xEAE4207A, +0x7E1D93EA,0xEA1DEBBB,0x7DFA98A8,0xE957ECFB,0x7DD6668F,0xE8922622,0x7DB0FDF8, +0xE7CC9917,0x7D8A5F40,0xE70747C4,0x7D628AC6,0xE642340D,0x7D3980EC,0xE57D5FDA, +0x7D0F4218,0xE4B8CD11,0x7CE3CEB2,0xE3F47D96,0x7CB72724,0xE330734D,0x7C894BDE, +0xE26CB01B,0x7C5A3D50,0xE1A935E2,0x7C29FBEE,0xE0E60685,0x7BF88830,0xE02323E5, +0x7BC5E290,0xDF608FE4,0x7B920B89,0xDE9E4C60,0x7B5D039E,0xDDDC5B3B,0x7B26CB4F, +0xDD1ABE51,0x7AEF6323,0xDC597781,0x7AB6CBA4,0xDB9888A8,0x7A7D055B,0xDAD7F3A2, +0x7A4210D8,0xDA17BA4A,0x7A05EEAD,0xD957DE7A,0x79C89F6E,0xD898620C,0x798A23B1, +0xD7D946D8,0x794A7C12,0xD71A8EB5,0x7909A92D,0xD65C3B7B,0x78C7ABA2,0xD59E4EFF, +0x78848414,0xD4E0CB15,0x78403329,0xD423B191,0x77FAB989,0xD3670446,0x77B417DF, +0xD2AAC504,0x776C4EDB,0xD1EEF59E,0x77235F2D,0xD13397E2,0x76D94989,0xD078AD9E, +0x768E0EA6,0xCFBE389F,0x7641AF3D,0xCF043AB3,0x75F42C0B,0xCE4AB5A2,0x75A585CF, +0xCD91AB39,0x7555BD4C,0xCCD91D3D,0x7504D345,0xCC210D79,0x74B2C884,0xCB697DB0, +0x745F9DD1,0xCAB26FA9,0x740B53FB,0xC9FBE527,0x73B5EBD1,0xC945DFEC,0x735F6626, +0xC89061BA,0x7307C3D0,0xC7DB6C50,0x72AF05A7,0xC727016D,0x72552C85,0xC67322CE, +0x71FA3949,0xC5BFD22E,0x719E2CD2,0xC50D1149,0x71410805,0xC45AE1D7,0x70E2CBC6, +0xC3A94590,0x708378FF,0xC2F83E2A,0x7023109A,0xC247CD5A,0x6FC19385,0xC197F4D4, +0x6F5F02B2,0xC0E8B648,0x6EFB5F12,0xC03A1368,0x6E96A99D,0xBF8C0DE3,0x6E30E34A, +0xBEDEA765,0x6DCA0D14,0xBE31E19B,0x6D6227FA,0xBD85BE30,0x6CF934FC,0xBCDA3ECB, +0x6C8F351C,0xBC2F6513,0x6C242960,0xBB8532B0,0x6BB812D1,0xBADBA943,0x6B4AF279, +0xBA32CA71,0x6ADCC964,0xB98A97D8,0x6A6D98A4,0xB8E31319,0x69FD614A,0xB83C3DD1, +0x698C246C,0xB796199B,0x6919E320,0xB6F0A812,0x68A69E81,0xB64BEACD,0x683257AB, +0xB5A7E362,0x67BD0FBD,0xB5049368,0x6746C7D8,0xB461FC70,0x66CF8120,0xB3C0200C, +0x66573CBB,0xB31EFFCC,0x65DDFBD3,0xB27E9D3C,0x6563BF92,0xB1DEF9E9,0x64E88926, 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+0x812A1A3A,0x1072A048,0x810FA7A0,0x0FAB272B,0x80F66E3C,0x0EE38766,0x80DE6E4C, +0x0E1BC2E4,0x80C7A80A,0x0D53DB92,0x80B21BAF,0x0C8BD35E,0x809DC971,0x0BC3AC35, +0x808AB180,0x0AFB6805,0x8078D40D,0x0A3308BD,0x80683143,0x096A9049,0x8058C94C, +0x08A2009A,0x804A9C4D,0x07D95B9E,0x803DAA6A,0x0710A345,0x8031F3C2,0x0647D97C, +0x80277872,0x057F0035,0x801E3895,0x04B6195D,0x80163440,0x03ED26E6,0x800F6B88, +0x03242ABF,0x8009DE7E,0x025B26D7,0x80058D2F,0x01921D20,0x800277A6,0x00C90F88, +0x80009DEA,0x7FFFFFFF,0x00000000,0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684, +0x7FA736B4,0xF6956FB7,0x7F62368F,0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC, +0xED37EF91,0x7E1D93EA,0xEA1DEBBB,0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96, +0x7C29FBEE,0xE0E60685,0x7B5D039E,0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1, +0xD7D946D8,0x78848414,0xD4E0CB15,0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3, +0x7504D345,0xCC210D79,0x73B5EBD1,0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6, +0xC3A94590,0x6F5F02B2,0xC0E8B648,0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0, +0x6A6D98A4,0xB8E31319,0x68A69E81,0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926, +0xB140175B,0x62F201AC,0xAECC336C,0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E, +0x5CB420E0,0xA7BD22AC,0x5A82799A,0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2, +0xA1288376,0x539B2AF0,0x9F13C7D0,0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA, +0x4C3FDFF4,0x99307EE0,0x49B41533,0x9759617F,0x471CECE7,0x9592675C,0x447ACD50, +0x93DBD6A0,0x41CE1E65,0x9235F2EC,0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A, +0x398CDD32,0x8DAAD37B,0x36BA2014,0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D, +0x89BE50C3,0x2E110A62,0x8893B125,0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F, +0x25280C5E,0x8582FAA5,0x2223A4C5,0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A, +0x831C314E,0x18F8B83C,0x8275A0C0,0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04, +0x0FAB272B,0x80F66E3C,0x0C8BD35E,0x809DC971,0x096A9049,0x8058C94C,0x0647D97C, +0x80277872,0x03242ABF,0x8009DE7E,0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2, +0x7D8A5F40,0xE70747C4,0x7A7D055B,0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6, +0xC3A94590,0x6A6D98A4,0xB8E31319,0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666, +0x5133CC94,0x9D0DFE54,0x471CECE7,0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D, +0x89BE50C3,0x25280C5E,0x8582FAA5,0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971, +0x7FFFFFFF,0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D, +0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFD885A,0xFE6DE2E0,0x7FF62182,0xFCDBD541,0x7FE9CBC0, +0xFB49E6A3,0x7FD8878E,0xF9B82684,0x7FC25596,0xF826A462,0x7FA736B4,0xF6956FB7, +0x7F872BF3,0xF50497FB,0x7F62368F,0xF3742CA2,0x7F3857F6,0xF1E43D1C,0x7F0991C4, +0xF054D8D5,0x7ED5E5C6,0xEEC60F31,0x7E9D55FC,0xED37EF91,0x7E5FE493,0xEBAA894F, +0x7E1D93EA,0xEA1DEBBB,0x7DD6668F,0xE8922622,0x7D8A5F40,0xE70747C4,0x7D3980EC, +0xE57D5FDA,0x7CE3CEB2,0xE3F47D96,0x7C894BDE,0xE26CB01B,0x7C29FBEE,0xE0E60685, +0x7BC5E290,0xDF608FE4,0x7B5D039E,0xDDDC5B3B,0x7AEF6323,0xDC597781,0x7A7D055B, +0xDAD7F3A2,0x7A05EEAD,0xD957DE7A,0x798A23B1,0xD7D946D8,0x7909A92D,0xD65C3B7B, +0x78848414,0xD4E0CB15,0x77FAB989,0xD3670446,0x776C4EDB,0xD1EEF59E,0x76D94989, +0xD078AD9E,0x7641AF3D,0xCF043AB3,0x75A585CF,0xCD91AB39,0x7504D345,0xCC210D79, +0x745F9DD1,0xCAB26FA9,0x73B5EBD1,0xC945DFEC,0x7307C3D0,0xC7DB6C50,0x72552C85, +0xC67322CE,0x719E2CD2,0xC50D1149,0x70E2CBC6,0xC3A94590,0x7023109A,0xC247CD5A, +0x6F5F02B2,0xC0E8B648,0x6E96A99D,0xBF8C0DE3,0x6DCA0D14,0xBE31E19B,0x6CF934FC, +0xBCDA3ECB,0x6C242960,0xBB8532B0,0x6B4AF279,0xBA32CA71,0x6A6D98A4,0xB8E31319, +0x698C246C,0xB796199B,0x68A69E81,0xB64BEACD,0x67BD0FBD,0xB5049368,0x66CF8120, +0xB3C0200C,0x65DDFBD3,0xB27E9D3C,0x64E88926,0xB140175B,0x63EF3290,0xB0049AB3, +0x62F201AC,0xAECC336C,0x61F1003F,0xAD96ED92,0x60EC3830,0xAC64D510,0x5FE3B38D, +0xAB35F5B5,0x5ED77C8A,0xAA0A5B2E,0x5DC79D7C,0xA8E21106,0x5CB420E0,0xA7BD22AC, +0x5B9D1154,0xA69B9B68,0x5A82799A,0xA57D8666,0x59646498,0xA462EEAC,0x5842DD54, +0xA34BDF20,0x571DEEFA,0xA2386284,0x55F5A4D2,0xA1288376,0x54CA0A4B,0xA01C4C73, +0x539B2AF0,0x9F13C7D0,0x5269126E,0x9E0EFFC1,0x5133CC94,0x9D0DFE54,0x4FFB654D, +0x9C10CD70,0x4EBFE8A5,0x9B1776DA,0x4D8162C4,0x9A22042D,0x4C3FDFF4,0x99307EE0, +0x4AFB6C98,0x9842F043,0x49B41533,0x9759617F,0x4869E665,0x9673DB94,0x471CECE7, +0x9592675C,0x45CD358F,0x94B50D87,0x447ACD50,0x93DBD6A0,0x4325C135,0x9306CB04, +0x41CE1E65,0x9235F2EC,0x4073F21D,0x91695663,0x3F1749B8,0x90A0FD4E,0x3DB832A6, +0x8FDCEF66,0x3C56BA70,0x8F1D343A,0x3AF2EEB7,0x8E61D32E,0x398CDD32,0x8DAAD37B, +0x382493B0,0x8CF83C30,0x36BA2014,0x8C4A142F,0x354D9057,0x8BA0622F,0x33DEF287, +0x8AFB2CBB,0x326E54C7,0x8A5A7A31,0x30FBC54D,0x89BE50C3,0x2F875262,0x8926B677, +0x2E110A62,0x8893B125,0x2C98FBBA,0x88054677,0x2B1F34EB,0x877B7BEC,0x29A3C485, +0x86F656D3,0x2826B928,0x8675DC4F,0x26A82186,0x85FA1153,0x25280C5E,0x8582FAA5, +0x23A6887F,0x85109CDD,0x2223A4C5,0x84A2FC62,0x209F701C,0x843A1D70,0x1F19F97B, +0x83D60412,0x1D934FE5,0x8376B422,0x1C0B826A,0x831C314E,0x1A82A026,0x82C67F14, +0x18F8B83C,0x8275A0C0,0x176DD9DE,0x82299971,0x15E21445,0x81E26C16,0x145576B1, +0x81A01B6D,0x12C8106F,0x8162AA04,0x1139F0CF,0x812A1A3A,0x0FAB272B,0x80F66E3C, +0x0E1BC2E4,0x80C7A80A,0x0C8BD35E,0x809DC971,0x0AFB6805,0x8078D40D,0x096A9049, +0x8058C94C,0x07D95B9E,0x803DAA6A,0x0647D97C,0x80277872,0x04B6195D,0x80163440, +0x03242ABF,0x8009DE7E,0x01921D20,0x800277A6,0x00000000,0x80000000,0xFE6DE2E0, +0x800277A6,0xFCDBD541,0x8009DE7E,0xFB49E6A3,0x80163440,0xF9B82684,0x80277872, +0xF826A462,0x803DAA6A,0xF6956FB7,0x8058C94C,0xF50497FB,0x8078D40D,0xF3742CA2, +0x809DC971,0xF1E43D1C,0x80C7A80A,0xF054D8D5,0x80F66E3C,0xEEC60F31,0x812A1A3A, +0xED37EF91,0x8162AA04,0xEBAA894F,0x81A01B6D,0xEA1DEBBB,0x81E26C16,0xE8922622, +0x82299971,0xE70747C4,0x8275A0C0,0xE57D5FDA,0x82C67F14,0xE3F47D96,0x831C314E, +0xE26CB01B,0x8376B422,0xE0E60685,0x83D60412,0xDF608FE4,0x843A1D70,0xDDDC5B3B, +0x84A2FC62,0xDC597781,0x85109CDD,0xDAD7F3A2,0x8582FAA5,0xD957DE7A,0x85FA1153, +0xD7D946D8,0x8675DC4F,0xD65C3B7B,0x86F656D3,0xD4E0CB15,0x877B7BEC,0xD3670446, +0x88054677,0xD1EEF59E,0x8893B125,0xD078AD9E,0x8926B677,0xCF043AB3,0x89BE50C3, +0xCD91AB39,0x8A5A7A31,0xCC210D79,0x8AFB2CBB,0xCAB26FA9,0x8BA0622F,0xC945DFEC, +0x8C4A142F,0xC7DB6C50,0x8CF83C30,0xC67322CE,0x8DAAD37B,0xC50D1149,0x8E61D32E, +0xC3A94590,0x8F1D343A,0xC247CD5A,0x8FDCEF66,0xC0E8B648,0x90A0FD4E,0xBF8C0DE3, +0x91695663,0xBE31E19B,0x9235F2EC,0xBCDA3ECB,0x9306CB04,0xBB8532B0,0x93DBD6A0, +0xBA32CA71,0x94B50D87,0xB8E31319,0x9592675C,0xB796199B,0x9673DB94,0xB64BEACD, +0x9759617F,0xB5049368,0x9842F043,0xB3C0200C,0x99307EE0,0xB27E9D3C,0x9A22042D, +0xB140175B,0x9B1776DA,0xB0049AB3,0x9C10CD70,0xAECC336C,0x9D0DFE54,0xAD96ED92, +0x9E0EFFC1,0xAC64D510,0x9F13C7D0,0xAB35F5B5,0xA01C4C73,0xAA0A5B2E,0xA1288376, +0xA8E21106,0xA2386284,0xA7BD22AC,0xA34BDF20,0xA69B9B68,0xA462EEAC,0xA57D8666, +0xA57D8666,0xA462EEAC,0xA69B9B68,0xA34BDF20,0xA7BD22AC,0xA2386284,0xA8E21106, +0xA1288376,0xAA0A5B2E,0xA01C4C73,0xAB35F5B5,0x9F13C7D0,0xAC64D510,0x9E0EFFC1, +0xAD96ED92,0x9D0DFE54,0xAECC336C,0x9C10CD70,0xB0049AB3,0x9B1776DA,0xB140175B, +0x9A22042D,0xB27E9D3C,0x99307EE0,0xB3C0200C,0x9842F043,0xB5049368,0x9759617F, +0xB64BEACD,0x9673DB94,0xB796199B,0x9592675C,0xB8E31319,0x94B50D87,0xBA32CA71, +0x93DBD6A0,0xBB8532B0,0x9306CB04,0xBCDA3ECB,0x9235F2EC,0xBE31E19B,0x91695663, +0xBF8C0DE3,0x90A0FD4E,0xC0E8B648,0x8FDCEF66,0xC247CD5A,0x8F1D343A,0xC3A94590, +0x8E61D32E,0xC50D1149,0x8DAAD37B,0xC67322CE,0x8CF83C30,0xC7DB6C50,0x8C4A142F, +0xC945DFEC,0x8BA0622F,0xCAB26FA9,0x8AFB2CBB,0xCC210D79,0x8A5A7A31,0xCD91AB39, +0x89BE50C3,0xCF043AB3,0x8926B677,0xD078AD9E,0x8893B125,0xD1EEF59E,0x88054677, +0xD3670446,0x877B7BEC,0xD4E0CB15,0x86F656D3,0xD65C3B7B,0x8675DC4F,0xD7D946D8, +0x85FA1153,0xD957DE7A,0x8582FAA5,0xDAD7F3A2,0x85109CDD,0xDC597781,0x84A2FC62, +0xDDDC5B3B,0x843A1D70,0xDF608FE4,0x83D60412,0xE0E60685,0x8376B422,0xE26CB01B, +0x831C314E,0xE3F47D96,0x82C67F14,0xE57D5FDA,0x8275A0C0,0xE70747C4,0x82299971, +0xE8922622,0x81E26C16,0xEA1DEBBB,0x81A01B6D,0xEBAA894F,0x8162AA04,0xED37EF91, +0x812A1A3A,0xEEC60F31,0x80F66E3C,0xF054D8D5,0x80C7A80A,0xF1E43D1C,0x809DC971, +0xF3742CA2,0x8078D40D,0xF50497FB,0x8058C94C,0xF6956FB7,0x803DAA6A,0xF826A462, +0x80277872,0xF9B82684,0x80163440,0xFB49E6A3,0x8009DE7E,0xFCDBD541,0x800277A6, +0xFE6DE2E0,0x7FFFFFFF,0x00000000,0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2, +0x7E9D55FC,0xED37EF91,0x7D8A5F40,0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B, +0xDAD7F3A2,0x78848414,0xD4E0CB15,0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC, +0x70E2CBC6,0xC3A94590,0x6DCA0D14,0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120, +0xB3C0200C,0x62F201AC,0xAECC336C,0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666, +0x55F5A4D2,0xA1288376,0x5133CC94,0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7, +0x9592675C,0x41CE1E65,0x9235F2EC,0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F, +0x30FBC54D,0x89BE50C3,0x2B1F34EB,0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B, +0x83D60412,0x18F8B83C,0x8275A0C0,0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971, +0x0647D97C,0x80277872,0x00000000,0x80000000,0xF9B82684,0x80277872,0xF3742CA2, +0x809DC971,0xED37EF91,0x8162AA04,0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412, +0xDAD7F3A2,0x8582FAA5,0xD4E0CB15,0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC, +0x8C4A142F,0xC3A94590,0x8F1D343A,0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C, +0xB3C0200C,0x99307EE0,0xAECC336C,0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666, +0xA57D8666,0xA1288376,0xAA0A5B2E,0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C, +0x9592675C,0xB8E31319,0x9235F2EC,0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F, +0xC945DFEC,0x89BE50C3,0xCF043AB3,0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2, +0x83D60412,0xE0E60685,0x8275A0C0,0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971, +0xF3742CA2,0x80277872,0xF9B82684,0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4, +0x7641AF3D,0xCF043AB3,0x6A6D98A4,0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7, +0x9592675C,0x30FBC54D,0x89BE50C3,0x18F8B83C,0x8275A0C0,0x00000000,0x80000000, +0xE70747C4,0x8275A0C0,0xCF043AB3,0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666, +0xA57D8666,0x9592675C,0xB8E31319,0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4, +0x7FFFFFFF,0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666, +0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFA72D1,0xFDA4D929,0x7FE9CBC0,0xFB49E6A3,0x7FCE0C3E, +0xF8EF5CBB,0x7FA736B4,0xF6956FB7,0x7F754E80,0xF43C53CB,0x7F3857F6,0xF1E43D1C, +0x7EF05860,0xEF8D5FB8,0x7E9D55FC,0xED37EF91,0x7E3F57FF,0xEAE4207A,0x7DD6668F, +0xE8922622,0x7D628AC6,0xE642340D,0x7CE3CEB2,0xE3F47D96,0x7C5A3D50,0xE1A935E2, +0x7BC5E290,0xDF608FE4,0x7B26CB4F,0xDD1ABE51,0x7A7D055B,0xDAD7F3A2,0x79C89F6E, +0xD898620C,0x7909A92D,0xD65C3B7B,0x78403329,0xD423B191,0x776C4EDB,0xD1EEF59E, +0x768E0EA6,0xCFBE389F,0x75A585CF,0xCD91AB39,0x74B2C884,0xCB697DB0,0x73B5EBD1, +0xC945DFEC,0x72AF05A7,0xC727016D,0x719E2CD2,0xC50D1149,0x708378FF,0xC2F83E2A, +0x6F5F02B2,0xC0E8B648,0x6E30E34A,0xBEDEA765,0x6CF934FC,0xBCDA3ECB,0x6BB812D1, +0xBADBA943,0x6A6D98A4,0xB8E31319,0x6919E320,0xB6F0A812,0x67BD0FBD,0xB5049368, +0x66573CBB,0xB31EFFCC,0x64E88926,0xB140175B,0x637114CC,0xAF6803A2,0x61F1003F, +0xAD96ED92,0x60686CCF,0xABCCFD83,0x5ED77C8A,0xAA0A5B2E,0x5D3E5237,0xA84F2DAA, +0x5B9D1154,0xA69B9B68,0x59F3DE12,0xA4EFCA31,0x5842DD54,0xA34BDF20,0x568A34A9, +0xA1AFFEA3,0x54CA0A4B,0xA01C4C73,0x53028518,0x9E90EB94,0x5133CC94,0x9D0DFE54, +0x4F5E08E3,0x9B93A641,0x4D8162C4,0x9A22042D,0x4B9E0390,0x98B93828,0x49B41533, +0x9759617F,0x47C3C22F,0x96029EB6,0x45CD358F,0x94B50D87,0x43D09AED,0x9370CAE4, +0x41CE1E65,0x9235F2EC,0x3FC5EC98,0x9104A0EE,0x3DB832A6,0x8FDCEF66,0x3BA51E29, +0x8EBEF7FB,0x398CDD32,0x8DAAD37B,0x376F9E46,0x8CA099DA,0x354D9057,0x8BA0622F, +0x3326E2C3,0x8AAA42B4,0x30FBC54D,0x89BE50C3,0x2ECC681E,0x88DCA0D3,0x2C98FBBA, +0x88054677,0x2A61B101,0x8738545E,0x2826B928,0x8675DC4F,0x25E845B6,0x85BDEF28, +0x23A6887F,0x85109CDD,0x2161B3A0,0x846DF477,0x1F19F97B,0x83D60412,0x1CCF8CB3, +0x8348D8DC,0x1A82A026,0x82C67F14,0x183366E9,0x824F0208,0x15E21445,0x81E26C16, +0x138EDBB1,0x8180C6A9,0x1139F0CF,0x812A1A3A,0x0EE38766,0x80DE6E4C,0x0C8BD35E, +0x809DC971,0x0A3308BD,0x80683143,0x07D95B9E,0x803DAA6A,0x057F0035,0x801E3895, +0x03242ABF,0x8009DE7E,0x00C90F88,0x80009DEA,0xFE6DE2E0,0x800277A6,0xFC12D91A, +0x800F6B88,0xF9B82684,0x80277872,0xF75DFF66,0x804A9C4D,0xF50497FB,0x8078D40D, +0xF2AC246E,0x80B21BAF,0xF054D8D5,0x80F66E3C,0xEDFEE92B,0x8145C5C7,0xEBAA894F, +0x81A01B6D,0xE957ECFB,0x82056758,0xE70747C4,0x8275A0C0,0xE4B8CD11,0x82F0BDE8, +0xE26CB01B,0x8376B422,0xE02323E5,0x840777D0,0xDDDC5B3B,0x84A2FC62,0xDB9888A8, +0x8549345C,0xD957DE7A,0x85FA1153,0xD71A8EB5,0x86B583EE,0xD4E0CB15,0x877B7BEC, +0xD2AAC504,0x884BE821,0xD078AD9E,0x8926B677,0xCE4AB5A2,0x8A0BD3F5,0xCC210D79, +0x8AFB2CBB,0xC9FBE527,0x8BF4AC05,0xC7DB6C50,0x8CF83C30,0xC5BFD22E,0x8E05C6B7, +0xC3A94590,0x8F1D343A,0xC197F4D4,0x903E6C7B,0xBF8C0DE3,0x91695663,0xBD85BE30, +0x929DD806,0xBB8532B0,0x93DBD6A0,0xB98A97D8,0x9523369C,0xB796199B,0x9673DB94, +0xB5A7E362,0x97CDA855,0xB3C0200C,0x99307EE0,0xB1DEF9E9,0x9A9C406E,0xB0049AB3, +0x9C10CD70,0xAE312B92,0x9D8E0597,0xAC64D510,0x9F13C7D0,0xAA9FBF1E,0xA0A1F24D, +0xA8E21106,0xA2386284,0xA72BF174,0xA3D6F534,0xA57D8666,0xA57D8666,0xA3D6F534, +0xA72BF174,0xA2386284,0xA8E21106,0xA0A1F24D,0xAA9FBF1E,0x9F13C7D0,0xAC64D510, +0x9D8E0597,0xAE312B92,0x9C10CD70,0xB0049AB3,0x9A9C406E,0xB1DEF9E9,0x99307EE0, +0xB3C0200C,0x97CDA855,0xB5A7E362,0x9673DB94,0xB796199B,0x9523369C,0xB98A97D8, +0x93DBD6A0,0xBB8532B0,0x929DD806,0xBD85BE30,0x91695663,0xBF8C0DE3,0x903E6C7B, +0xC197F4D4,0x8F1D343A,0xC3A94590,0x8E05C6B7,0xC5BFD22E,0x8CF83C30,0xC7DB6C50, +0x8BF4AC05,0xC9FBE527,0x8AFB2CBB,0xCC210D79,0x8A0BD3F5,0xCE4AB5A2,0x8926B677, +0xD078AD9E,0x884BE821,0xD2AAC504,0x877B7BEC,0xD4E0CB15,0x86B583EE,0xD71A8EB5, +0x85FA1153,0xD957DE7A,0x8549345C,0xDB9888A8,0x84A2FC62,0xDDDC5B3B,0x840777D0, +0xE02323E5,0x8376B422,0xE26CB01B,0x82F0BDE8,0xE4B8CD11,0x8275A0C0,0xE70747C4, +0x82056758,0xE957ECFB,0x81A01B6D,0xEBAA894F,0x8145C5C7,0xEDFEE92B,0x80F66E3C, +0xF054D8D5,0x80B21BAF,0xF2AC246E,0x8078D40D,0xF50497FB,0x804A9C4D,0xF75DFF66, +0x80277872,0xF9B82684,0x800F6B88,0xFC12D91A,0x800277A6,0xFE6DE2E0,0x80009DEA, +0x00C90F88,0x8009DE7E,0x03242ABF,0x801E3895,0x057F0035,0x803DAA6A,0x07D95B9E, +0x80683143,0x0A3308BD,0x809DC971,0x0C8BD35E,0x80DE6E4C,0x0EE38766,0x812A1A3A, +0x1139F0CF,0x8180C6A9,0x138EDBB1,0x81E26C16,0x15E21445,0x824F0208,0x183366E9, +0x82C67F14,0x1A82A026,0x8348D8DC,0x1CCF8CB3,0x83D60412,0x1F19F97B,0x846DF477, +0x2161B3A0,0x85109CDD,0x23A6887F,0x85BDEF28,0x25E845B6,0x8675DC4F,0x2826B928, +0x8738545E,0x2A61B101,0x88054677,0x2C98FBBA,0x88DCA0D3,0x2ECC681E,0x89BE50C3, +0x30FBC54D,0x8AAA42B4,0x3326E2C3,0x8BA0622F,0x354D9057,0x8CA099DA,0x376F9E46, +0x8DAAD37B,0x398CDD32,0x8EBEF7FB,0x3BA51E29,0x8FDCEF66,0x3DB832A6,0x9104A0EE, +0x3FC5EC98,0x9235F2EC,0x41CE1E65,0x9370CAE4,0x43D09AED,0x94B50D87,0x45CD358F, +0x96029EB6,0x47C3C22F,0x9759617F,0x49B41533,0x98B93828,0x4B9E0390,0x9A22042D, +0x4D8162C4,0x9B93A641,0x4F5E08E3,0x9D0DFE54,0x5133CC94,0x9E90EB94,0x53028518, +0xA01C4C73,0x54CA0A4B,0xA1AFFEA3,0x568A34A9,0xA34BDF20,0x5842DD54,0xA4EFCA31, +0x59F3DE12,0xA69B9B68,0x5B9D1154,0xA84F2DAA,0x5D3E5237,0xAA0A5B2E,0x5ED77C8A, +0xABCCFD83,0x60686CCF,0xAD96ED92,0x61F1003F,0xAF6803A2,0x637114CC,0xB140175B, +0x64E88926,0xB31EFFCC,0x66573CBB,0xB5049368,0x67BD0FBD,0xB6F0A812,0x6919E320, +0xB8E31319,0x6A6D98A4,0xBADBA943,0x6BB812D1,0xBCDA3ECB,0x6CF934FC,0xBEDEA765, +0x6E30E34A,0xC0E8B648,0x6F5F02B2,0xC2F83E2A,0x708378FF,0xC50D1149,0x719E2CD2, +0xC727016D,0x72AF05A7,0xC945DFEC,0x73B5EBD1,0xCB697DB0,0x74B2C884,0xCD91AB39, +0x75A585CF,0xCFBE389F,0x768E0EA6,0xD1EEF59E,0x776C4EDB,0xD423B191,0x78403329, +0xD65C3B7B,0x7909A92D,0xD898620C,0x79C89F6E,0xDAD7F3A2,0x7A7D055B,0xDD1ABE51, +0x7B26CB4F,0xDF608FE4,0x7BC5E290,0xE1A935E2,0x7C5A3D50,0xE3F47D96,0x7CE3CEB2, +0xE642340D,0x7D628AC6,0xE8922622,0x7DD6668F,0xEAE4207A,0x7E3F57FF,0xED37EF91, +0x7E9D55FC,0xEF8D5FB8,0x7EF05860,0xF1E43D1C,0x7F3857F6,0xF43C53CB,0x7F754E80, +0xF6956FB7,0x7FA736B4,0xF8EF5CBB,0x7FCE0C3E,0xFB49E6A3,0x7FE9CBC0,0xFDA4D929, +0x7FFA72D1,0x7FFFFFFF,0x00000000,0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91, +0x7CE3CEB2,0xE3F47D96,0x7A7D055B,0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1, +0xC945DFEC,0x6F5F02B2,0xC0E8B648,0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B, +0x5ED77C8A,0xAA0A5B2E,0x5842DD54,0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533, +0x9759617F,0x41CE1E65,0x9235F2EC,0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3, +0x2826B928,0x8675DC4F,0x1F19F97B,0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E, +0x809DC971,0x03242ABF,0x8009DE7E,0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C, +0xE70747C4,0x8275A0C0,0xDDDC5B3B,0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79, +0x8AFB2CBB,0xC3A94590,0x8F1D343A,0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0, +0xAC64D510,0x9F13C7D0,0xA57D8666,0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0, +0xB3C0200C,0x93DBD6A0,0xBB8532B0,0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79, +0x877B7BEC,0xD4E0CB15,0x84A2FC62,0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C, +0xF054D8D5,0x80277872,0xF9B82684,0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E, +0x81E26C16,0x15E21445,0x83D60412,0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3, +0x30FBC54D,0x8DAAD37B,0x398CDD32,0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533, +0x9D0DFE54,0x5133CC94,0xA34BDF20,0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B, +0x64E88926,0xB8E31319,0x6A6D98A4,0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1, +0xD1EEF59E,0x776C4EDB,0xDAD7F3A2,0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91, +0x7E9D55FC,0xF6956FB7,0x7FA736B4,0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2, +0x6A6D98A4,0xB8E31319,0x5133CC94,0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E, +0x809DC971,0xE70747C4,0x8275A0C0,0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666, +0x8F1D343A,0xC3A94590,0x8275A0C0,0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3, +0x30FBC54D,0x9D0DFE54,0x5133CC94,0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B, +0x7FFFFFFF,0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3, +0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +q31_t rearranged_twiddle_stride1_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFF621,0xFFCDBC0B,0x7FFFD886,0xFF9B781D,0x7FFFA72C, +0xFF69343F,0x7FFF6216,0xFF36F078,0x7FFF0943,0xFF04ACD0,0x7FFE9CB2,0xFED2694F, +0x7FFE1C65,0xFEA025FD,0x7FFD885A,0xFE6DE2E0,0x7FFCE093,0xFE3BA002,0x7FFC250F, +0xFE095D69,0x7FFB55CE,0xFDD71B1E,0x7FFA72D1,0xFDA4D929,0x7FF97C18,0xFD729790, +0x7FF871A2,0xFD40565C,0x7FF75370,0xFD0E1594,0x7FF62182,0xFCDBD541,0x7FF4DBD9, +0xFCA9956A,0x7FF38274,0xFC775616,0x7FF21553,0xFC45174E,0x7FF09478,0xFC12D91A, +0x7FEEFFE1,0xFBE09B80,0x7FED5791,0xFBAE5E89,0x7FEB9B85,0xFB7C223D,0x7FE9CBC0, +0xFB49E6A3,0x7FE7E841,0xFB17ABC2,0x7FE5F108,0xFAE571A4,0x7FE3E616,0xFAB3384F, +0x7FE1C76B,0xFA80FFCB,0x7FDF9508,0xFA4EC821,0x7FDD4EEC,0xFA1C9157,0x7FDAF519, +0xF9EA5B75,0x7FD8878E,0xF9B82684,0x7FD6064C,0xF985F28A,0x7FD37153,0xF953BF91, +0x7FD0C8A3,0xF9218D9E,0x7FCE0C3E,0xF8EF5CBB,0x7FCB3C23,0xF8BD2CEF,0x7FC85854, +0xF88AFE42,0x7FC560CF,0xF858D0BB,0x7FC25596,0xF826A462,0x7FBF36AA,0xF7F4793E, +0x7FBC040A,0xF7C24F59,0x7FB8BDB8,0xF79026B9,0x7FB563B3,0xF75DFF66,0x7FB1F5FC, +0xF72BD967,0x7FAE7495,0xF6F9B4C6,0x7FAADF7C,0xF6C79188,0x7FA736B4,0xF6956FB7, +0x7FA37A3C,0xF6634F59,0x7F9FAA15,0xF6313077,0x7F9BC640,0xF5FF1318,0x7F97CEBD, +0xF5CCF743,0x7F93C38C,0xF59ADD02,0x7F8FA4B0,0xF568C45B,0x7F8B7227,0xF536AD56, +0x7F872BF3,0xF50497FB,0x7F82D214,0xF4D28451,0x7F7E648C,0xF4A07261,0x7F79E35A, +0xF46E6231,0x7F754E80,0xF43C53CB,0x7F70A5FE,0xF40A4735,0x7F6BE9D4,0xF3D83C77, +0x7F671A05,0xF3A63398,0x7F62368F,0xF3742CA2,0x7F5D3F75,0xF342279B,0x7F5834B7, +0xF310248A,0x7F531655,0xF2DE2379,0x7F4DE451,0xF2AC246E,0x7F489EAA,0xF27A2771, +0x7F434563,0xF2482C8A,0x7F3DD87C,0xF21633C0,0x7F3857F6,0xF1E43D1C,0x7F32C3D1, +0xF1B248A5,0x7F2D1C0E,0xF1805662,0x7F2760AF,0xF14E665C,0x7F2191B4,0xF11C789A, +0x7F1BAF1E,0xF0EA8D24,0x7F15B8EE,0xF0B8A401,0x7F0FAF25,0xF086BD39,0x7F0991C4, +0xF054D8D5,0x7F0360CB,0xF022F6DA,0x7EFD1C3C,0xEFF11753,0x7EF6C418,0xEFBF3A45, +0x7EF05860,0xEF8D5FB8,0x7EE9D914,0xEF5B87B5,0x7EE34636,0xEF29B243,0x7EDC9FC6, +0xEEF7DF6A,0x7ED5E5C6,0xEEC60F31,0x7ECF1837,0xEE9441A0,0x7EC8371A,0xEE6276BF, +0x7EC14270,0xEE30AE96,0x7EBA3A39,0xEDFEE92B,0x7EB31E78,0xEDCD2687,0x7EABEF2C, +0xED9B66B2,0x7EA4AC58,0xED69A9B3,0x7E9D55FC,0xED37EF91,0x7E95EC1A,0xED063856, +0x7E8E6EB2,0xECD48407,0x7E86DDC6,0xECA2D2AD,0x7E7F3957,0xEC71244F,0x7E778166, +0xEC3F78F6,0x7E6FB5F4,0xEC0DD0A8,0x7E67D703,0xEBDC2B6E,0x7E5FE493,0xEBAA894F, +0x7E57DEA7,0xEB78EA52,0x7E4FC53E,0xEB474E81,0x7E47985B,0xEB15B5E1,0x7E3F57FF, +0xEAE4207A,0x7E37042A,0xEAB28E56,0x7E2E9CDF,0xEA80FF7A,0x7E26221F,0xEA4F73EE, +0x7E1D93EA,0xEA1DEBBB,0x7E14F242,0xE9EC66E8,0x7E0C3D29,0xE9BAE57D,0x7E0374A0, +0xE9896781,0x7DFA98A8,0xE957ECFB,0x7DF1A942,0xE92675F4,0x7DE8A670,0xE8F50273, +0x7DDF9034,0xE8C39280,0x7DD6668F,0xE8922622,0x7DCD2981,0xE860BD61,0x7DC3D90D, +0xE82F5844,0x7DBA7534,0xE7FDF6D4,0x7DB0FDF8,0xE7CC9917,0x7DA77359,0xE79B3F16, +0x7D9DD55A,0xE769E8D8,0x7D9423FC,0xE7389665,0x7D8A5F40,0xE70747C4,0x7D808728, +0xE6D5FCFC,0x7D769BB5,0xE6A4B616,0x7D6C9CE9,0xE6737319,0x7D628AC6,0xE642340D, +0x7D58654D,0xE610F8F9,0x7D4E2C7F,0xE5DFC1E5,0x7D43E05E,0xE5AE8ED8,0x7D3980EC, +0xE57D5FDA,0x7D2F0E2B,0xE54C34F3,0x7D24881B,0xE51B0E2A,0x7D19EEBF,0xE4E9EB87, +0x7D0F4218,0xE4B8CD11,0x7D048228,0xE487B2D0,0x7CF9AEF0,0xE4569CCB,0x7CEEC873, +0xE4258B0A,0x7CE3CEB2,0xE3F47D96,0x7CD8C1AE,0xE3C37474,0x7CCDA169,0xE3926FAD, +0x7CC26DE5,0xE3616F48,0x7CB72724,0xE330734D,0x7CABCD28,0xE2FF7BC3,0x7CA05FF1, +0xE2CE88B3,0x7C94DF83,0xE29D9A23,0x7C894BDE,0xE26CB01B,0x7C7DA505,0xE23BCAA2, +0x7C71EAF9,0xE20AE9C1,0x7C661DBC,0xE1DA0D7E,0x7C5A3D50,0xE1A935E2,0x7C4E49B7, +0xE17862F3,0x7C4242F2,0xE14794BA,0x7C362904,0xE116CB3D,0x7C29FBEE,0xE0E60685, +0x7C1DBBB3,0xE0B54698,0x7C116853,0xE0848B7F,0x7C0501D2,0xE053D541,0x7BF88830, +0xE02323E5,0x7BEBFB70,0xDFF27773,0x7BDF5B94,0xDFC1CFF3,0x7BD2A89E,0xDF912D6B, +0x7BC5E290,0xDF608FE4,0x7BB9096B,0xDF2FF764,0x7BAC1D31,0xDEFF63F4,0x7B9F1DE6, +0xDECED59B,0x7B920B89,0xDE9E4C60,0x7B84E61F,0xDE6DC84B,0x7B77ADA8,0xDE3D4964, +0x7B6A6227,0xDE0CCFB1,0x7B5D039E,0xDDDC5B3B,0x7B4F920E,0xDDABEC08,0x7B420D7A, +0xDD7B8220,0x7B3475E5,0xDD4B1D8C,0x7B26CB4F,0xDD1ABE51,0x7B190DBC,0xDCEA6478, +0x7B0B3D2C,0xDCBA1008,0x7AFD59A4,0xDC89C109,0x7AEF6323,0xDC597781,0x7AE159AE, +0xDC293379,0x7AD33D45,0xDBF8F4F8,0x7AC50DEC,0xDBC8BC06,0x7AB6CBA4,0xDB9888A8, +0x7AA8766F,0xDB685AE9,0x7A9A0E50,0xDB3832CD,0x7A8B9348,0xDB08105E,0x7A7D055B, +0xDAD7F3A2,0x7A6E648A,0xDAA7DCA1,0x7A5FB0D8,0xDA77CB63,0x7A50EA47,0xDA47BFEE, +0x7A4210D8,0xDA17BA4A,0x7A332490,0xD9E7BA7F,0x7A24256F,0xD9B7C094,0x7A151378, +0xD987CC90,0x7A05EEAD,0xD957DE7A,0x79F6B711,0xD927F65B,0x79E76CA7,0xD8F81439, +0x79D80F6F,0xD8C8381D,0x79C89F6E,0xD898620C,0x79B91CA4,0xD868920F,0x79A98715, +0xD838C82D,0x7999DEC4,0xD809046E,0x798A23B1,0xD7D946D8,0x797A55E0,0xD7A98F73, +0x796A7554,0xD779DE47,0x795A820E,0xD74A335B,0x794A7C12,0xD71A8EB5,0x793A6361, +0xD6EAF05F,0x792A37FE,0xD6BB585E,0x7919F9EC,0xD68BC6BA,0x7909A92D,0xD65C3B7B, +0x78F945C3,0xD62CB6A8,0x78E8CFB2,0xD5FD3848,0x78D846FB,0xD5CDC062,0x78C7ABA2, +0xD59E4EFF,0x78B6FDA8,0xD56EE424,0x78A63D11,0xD53F7FDA,0x789569DF,0xD5102228, +0x78848414,0xD4E0CB15,0x78738BB3,0xD4B17AA8,0x786280BF,0xD48230E9,0x7851633B, +0xD452EDDF,0x78403329,0xD423B191,0x782EF08B,0xD3F47C06,0x781D9B65,0xD3C54D47, +0x780C33B8,0xD396255A,0x77FAB989,0xD3670446,0x77E92CD9,0xD337EA12,0x77D78DAA, +0xD308D6C7,0x77C5DC01,0xD2D9CA6A,0x77B417DF,0xD2AAC504,0x77A24148,0xD27BC69C, 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+0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96,0x7C29FBEE,0xE0E60685,0x7B5D039E, +0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1,0xD7D946D8,0x78848414,0xD4E0CB15, +0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3,0x7504D345,0xCC210D79,0x73B5EBD1, +0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6,0xC3A94590,0x6F5F02B2,0xC0E8B648, +0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0,0x6A6D98A4,0xB8E31319,0x68A69E81, +0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926,0xB140175B,0x62F201AC,0xAECC336C, +0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E,0x5CB420E0,0xA7BD22AC,0x5A82799A, +0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2,0xA1288376,0x539B2AF0,0x9F13C7D0, +0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA,0x4C3FDFF4,0x99307EE0,0x49B41533, +0x9759617F,0x471CECE7,0x9592675C,0x447ACD50,0x93DBD6A0,0x41CE1E65,0x9235F2EC, +0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A,0x398CDD32,0x8DAAD37B,0x36BA2014, +0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D,0x89BE50C3,0x2E110A62,0x8893B125, +0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F,0x25280C5E,0x8582FAA5,0x2223A4C5, +0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A,0x831C314E,0x18F8B83C,0x8275A0C0, +0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04,0x0FAB272B,0x80F66E3C,0x0C8BD35E, +0x809DC971,0x096A9049,0x8058C94C,0x0647D97C,0x80277872,0x03242ABF,0x8009DE7E, +0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40,0xE70747C4,0x7A7D055B, +0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590,0x6A6D98A4,0xB8E31319, +0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94,0x9D0DFE54,0x471CECE7, +0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3,0x25280C5E,0x8582FAA5, +0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF,0x00000000,0x7641AF3D, +0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFD886,0xFF9B781D,0x7FFF6216,0xFF36F078,0x7FFE9CB2, +0xFED2694F,0x7FFD885A,0xFE6DE2E0,0x7FFC250F,0xFE095D69,0x7FFA72D1,0xFDA4D929, +0x7FF871A2,0xFD40565C,0x7FF62182,0xFCDBD541,0x7FF38274,0xFC775616,0x7FF09478, +0xFC12D91A,0x7FED5791,0xFBAE5E89,0x7FE9CBC0,0xFB49E6A3,0x7FE5F108,0xFAE571A4, +0x7FE1C76B,0xFA80FFCB,0x7FDD4EEC,0xFA1C9157,0x7FD8878E,0xF9B82684,0x7FD37153, +0xF953BF91,0x7FCE0C3E,0xF8EF5CBB,0x7FC85854,0xF88AFE42,0x7FC25596,0xF826A462, +0x7FBC040A,0xF7C24F59,0x7FB563B3,0xF75DFF66,0x7FAE7495,0xF6F9B4C6,0x7FA736B4, +0xF6956FB7,0x7F9FAA15,0xF6313077,0x7F97CEBD,0xF5CCF743,0x7F8FA4B0,0xF568C45B, +0x7F872BF3,0xF50497FB,0x7F7E648C,0xF4A07261,0x7F754E80,0xF43C53CB,0x7F6BE9D4, +0xF3D83C77,0x7F62368F,0xF3742CA2,0x7F5834B7,0xF310248A,0x7F4DE451,0xF2AC246E, +0x7F434563,0xF2482C8A,0x7F3857F6,0xF1E43D1C,0x7F2D1C0E,0xF1805662,0x7F2191B4, +0xF11C789A,0x7F15B8EE,0xF0B8A401,0x7F0991C4,0xF054D8D5,0x7EFD1C3C,0xEFF11753, +0x7EF05860,0xEF8D5FB8,0x7EE34636,0xEF29B243,0x7ED5E5C6,0xEEC60F31,0x7EC8371A, +0xEE6276BF,0x7EBA3A39,0xEDFEE92B,0x7EABEF2C,0xED9B66B2,0x7E9D55FC,0xED37EF91, +0x7E8E6EB2,0xECD48407,0x7E7F3957,0xEC71244F,0x7E6FB5F4,0xEC0DD0A8,0x7E5FE493, +0xEBAA894F,0x7E4FC53E,0xEB474E81,0x7E3F57FF,0xEAE4207A,0x7E2E9CDF,0xEA80FF7A, +0x7E1D93EA,0xEA1DEBBB,0x7E0C3D29,0xE9BAE57D,0x7DFA98A8,0xE957ECFB,0x7DE8A670, +0xE8F50273,0x7DD6668F,0xE8922622,0x7DC3D90D,0xE82F5844,0x7DB0FDF8,0xE7CC9917, +0x7D9DD55A,0xE769E8D8,0x7D8A5F40,0xE70747C4,0x7D769BB5,0xE6A4B616,0x7D628AC6, +0xE642340D,0x7D4E2C7F,0xE5DFC1E5,0x7D3980EC,0xE57D5FDA,0x7D24881B,0xE51B0E2A, +0x7D0F4218,0xE4B8CD11,0x7CF9AEF0,0xE4569CCB,0x7CE3CEB2,0xE3F47D96,0x7CCDA169, +0xE3926FAD,0x7CB72724,0xE330734D,0x7CA05FF1,0xE2CE88B3,0x7C894BDE,0xE26CB01B, +0x7C71EAF9,0xE20AE9C1,0x7C5A3D50,0xE1A935E2,0x7C4242F2,0xE14794BA,0x7C29FBEE, +0xE0E60685,0x7C116853,0xE0848B7F,0x7BF88830,0xE02323E5,0x7BDF5B94,0xDFC1CFF3, +0x7BC5E290,0xDF608FE4,0x7BAC1D31,0xDEFF63F4,0x7B920B89,0xDE9E4C60,0x7B77ADA8, +0xDE3D4964,0x7B5D039E,0xDDDC5B3B,0x7B420D7A,0xDD7B8220,0x7B26CB4F,0xDD1ABE51, +0x7B0B3D2C,0xDCBA1008,0x7AEF6323,0xDC597781,0x7AD33D45,0xDBF8F4F8,0x7AB6CBA4, +0xDB9888A8,0x7A9A0E50,0xDB3832CD,0x7A7D055B,0xDAD7F3A2,0x7A5FB0D8,0xDA77CB63, +0x7A4210D8,0xDA17BA4A,0x7A24256F,0xD9B7C094,0x7A05EEAD,0xD957DE7A,0x79E76CA7, +0xD8F81439,0x79C89F6E,0xD898620C,0x79A98715,0xD838C82D,0x798A23B1,0xD7D946D8, +0x796A7554,0xD779DE47,0x794A7C12,0xD71A8EB5,0x792A37FE,0xD6BB585E,0x7909A92D, +0xD65C3B7B,0x78E8CFB2,0xD5FD3848,0x78C7ABA2,0xD59E4EFF,0x78A63D11,0xD53F7FDA, +0x78848414,0xD4E0CB15,0x786280BF,0xD48230E9,0x78403329,0xD423B191,0x781D9B65, +0xD3C54D47,0x77FAB989,0xD3670446,0x77D78DAA,0xD308D6C7,0x77B417DF,0xD2AAC504, +0x7790583E,0xD24CCF39,0x776C4EDB,0xD1EEF59E,0x7747FBCE,0xD191386E,0x77235F2D, +0xD13397E2,0x76FE790E,0xD0D61434,0x76D94989,0xD078AD9E,0x76B3D0B4,0xD01B6459, +0x768E0EA6,0xCFBE389F,0x76680376,0xCF612AAA,0x7641AF3D,0xCF043AB3,0x761B1211, +0xCEA768F2,0x75F42C0B,0xCE4AB5A2,0x75CCFD42,0xCDEE20FC,0x75A585CF,0xCD91AB39, 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+0x75A585CF,0xCD91AB39,0x7504D345,0xCC210D79,0x745F9DD1,0xCAB26FA9,0x73B5EBD1, +0xC945DFEC,0x7307C3D0,0xC7DB6C50,0x72552C85,0xC67322CE,0x719E2CD2,0xC50D1149, +0x70E2CBC6,0xC3A94590,0x7023109A,0xC247CD5A,0x6F5F02B2,0xC0E8B648,0x6E96A99D, +0xBF8C0DE3,0x6DCA0D14,0xBE31E19B,0x6CF934FC,0xBCDA3ECB,0x6C242960,0xBB8532B0, +0x6B4AF279,0xBA32CA71,0x6A6D98A4,0xB8E31319,0x698C246C,0xB796199B,0x68A69E81, +0xB64BEACD,0x67BD0FBD,0xB5049368,0x66CF8120,0xB3C0200C,0x65DDFBD3,0xB27E9D3C, +0x64E88926,0xB140175B,0x63EF3290,0xB0049AB3,0x62F201AC,0xAECC336C,0x61F1003F, +0xAD96ED92,0x60EC3830,0xAC64D510,0x5FE3B38D,0xAB35F5B5,0x5ED77C8A,0xAA0A5B2E, +0x5DC79D7C,0xA8E21106,0x5CB420E0,0xA7BD22AC,0x5B9D1154,0xA69B9B68,0x5A82799A, +0xA57D8666,0x59646498,0xA462EEAC,0x5842DD54,0xA34BDF20,0x571DEEFA,0xA2386284, +0x55F5A4D2,0xA1288376,0x54CA0A4B,0xA01C4C73,0x539B2AF0,0x9F13C7D0,0x5269126E, +0x9E0EFFC1,0x5133CC94,0x9D0DFE54,0x4FFB654D,0x9C10CD70,0x4EBFE8A5,0x9B1776DA, +0x4D8162C4,0x9A22042D,0x4C3FDFF4,0x99307EE0,0x4AFB6C98,0x9842F043,0x49B41533, +0x9759617F,0x4869E665,0x9673DB94,0x471CECE7,0x9592675C,0x45CD358F,0x94B50D87, +0x447ACD50,0x93DBD6A0,0x4325C135,0x9306CB04,0x41CE1E65,0x9235F2EC,0x4073F21D, +0x91695663,0x3F1749B8,0x90A0FD4E,0x3DB832A6,0x8FDCEF66,0x3C56BA70,0x8F1D343A, +0x3AF2EEB7,0x8E61D32E,0x398CDD32,0x8DAAD37B,0x382493B0,0x8CF83C30,0x36BA2014, +0x8C4A142F,0x354D9057,0x8BA0622F,0x33DEF287,0x8AFB2CBB,0x326E54C7,0x8A5A7A31, +0x30FBC54D,0x89BE50C3,0x2F875262,0x8926B677,0x2E110A62,0x8893B125,0x2C98FBBA, +0x88054677,0x2B1F34EB,0x877B7BEC,0x29A3C485,0x86F656D3,0x2826B928,0x8675DC4F, +0x26A82186,0x85FA1153,0x25280C5E,0x8582FAA5,0x23A6887F,0x85109CDD,0x2223A4C5, +0x84A2FC62,0x209F701C,0x843A1D70,0x1F19F97B,0x83D60412,0x1D934FE5,0x8376B422, +0x1C0B826A,0x831C314E,0x1A82A026,0x82C67F14,0x18F8B83C,0x8275A0C0,0x176DD9DE, +0x82299971,0x15E21445,0x81E26C16,0x145576B1,0x81A01B6D,0x12C8106F,0x8162AA04, +0x1139F0CF,0x812A1A3A,0x0FAB272B,0x80F66E3C,0x0E1BC2E4,0x80C7A80A,0x0C8BD35E, +0x809DC971,0x0AFB6805,0x8078D40D,0x096A9049,0x8058C94C,0x07D95B9E,0x803DAA6A, +0x0647D97C,0x80277872,0x04B6195D,0x80163440,0x03242ABF,0x8009DE7E,0x01921D20, +0x800277A6,0x00000000,0x80000000,0xFE6DE2E0,0x800277A6,0xFCDBD541,0x8009DE7E, +0xFB49E6A3,0x80163440,0xF9B82684,0x80277872,0xF826A462,0x803DAA6A,0xF6956FB7, +0x8058C94C,0xF50497FB,0x8078D40D,0xF3742CA2,0x809DC971,0xF1E43D1C,0x80C7A80A, +0xF054D8D5,0x80F66E3C,0xEEC60F31,0x812A1A3A,0xED37EF91,0x8162AA04,0xEBAA894F, +0x81A01B6D,0xEA1DEBBB,0x81E26C16,0xE8922622,0x82299971,0xE70747C4,0x8275A0C0, +0xE57D5FDA,0x82C67F14,0xE3F47D96,0x831C314E,0xE26CB01B,0x8376B422,0xE0E60685, +0x83D60412,0xDF608FE4,0x843A1D70,0xDDDC5B3B,0x84A2FC62,0xDC597781,0x85109CDD, +0xDAD7F3A2,0x8582FAA5,0xD957DE7A,0x85FA1153,0xD7D946D8,0x8675DC4F,0xD65C3B7B, +0x86F656D3,0xD4E0CB15,0x877B7BEC,0xD3670446,0x88054677,0xD1EEF59E,0x8893B125, +0xD078AD9E,0x8926B677,0xCF043AB3,0x89BE50C3,0xCD91AB39,0x8A5A7A31,0xCC210D79, +0x8AFB2CBB,0xCAB26FA9,0x8BA0622F,0xC945DFEC,0x8C4A142F,0xC7DB6C50,0x8CF83C30, +0xC67322CE,0x8DAAD37B,0xC50D1149,0x8E61D32E,0xC3A94590,0x8F1D343A,0xC247CD5A, +0x8FDCEF66,0xC0E8B648,0x90A0FD4E,0xBF8C0DE3,0x91695663,0xBE31E19B,0x9235F2EC, +0xBCDA3ECB,0x9306CB04,0xBB8532B0,0x93DBD6A0,0xBA32CA71,0x94B50D87,0xB8E31319, +0x9592675C,0xB796199B,0x9673DB94,0xB64BEACD,0x9759617F,0xB5049368,0x9842F043, +0xB3C0200C,0x99307EE0,0xB27E9D3C,0x9A22042D,0xB140175B,0x9B1776DA,0xB0049AB3, +0x9C10CD70,0xAECC336C,0x9D0DFE54,0xAD96ED92,0x9E0EFFC1,0xAC64D510,0x9F13C7D0, +0xAB35F5B5,0xA01C4C73,0xAA0A5B2E,0xA1288376,0xA8E21106,0xA2386284,0xA7BD22AC, +0xA34BDF20,0xA69B9B68,0xA462EEAC,0xA57D8666,0xA57D8666,0xA462EEAC,0xA69B9B68, +0xA34BDF20,0xA7BD22AC,0xA2386284,0xA8E21106,0xA1288376,0xAA0A5B2E,0xA01C4C73, +0xAB35F5B5,0x9F13C7D0,0xAC64D510,0x9E0EFFC1,0xAD96ED92,0x9D0DFE54,0xAECC336C, +0x9C10CD70,0xB0049AB3,0x9B1776DA,0xB140175B,0x9A22042D,0xB27E9D3C,0x99307EE0, +0xB3C0200C,0x9842F043,0xB5049368,0x9759617F,0xB64BEACD,0x9673DB94,0xB796199B, +0x9592675C,0xB8E31319,0x94B50D87,0xBA32CA71,0x93DBD6A0,0xBB8532B0,0x9306CB04, +0xBCDA3ECB,0x9235F2EC,0xBE31E19B,0x91695663,0xBF8C0DE3,0x90A0FD4E,0xC0E8B648, +0x8FDCEF66,0xC247CD5A,0x8F1D343A,0xC3A94590,0x8E61D32E,0xC50D1149,0x8DAAD37B, +0xC67322CE,0x8CF83C30,0xC7DB6C50,0x8C4A142F,0xC945DFEC,0x8BA0622F,0xCAB26FA9, +0x8AFB2CBB,0xCC210D79,0x8A5A7A31,0xCD91AB39,0x89BE50C3,0xCF043AB3,0x8926B677, +0xD078AD9E,0x8893B125,0xD1EEF59E,0x88054677,0xD3670446,0x877B7BEC,0xD4E0CB15, +0x86F656D3,0xD65C3B7B,0x8675DC4F,0xD7D946D8,0x85FA1153,0xD957DE7A,0x8582FAA5, +0xDAD7F3A2,0x85109CDD,0xDC597781,0x84A2FC62,0xDDDC5B3B,0x843A1D70,0xDF608FE4, +0x83D60412,0xE0E60685,0x8376B422,0xE26CB01B,0x831C314E,0xE3F47D96,0x82C67F14, +0xE57D5FDA,0x8275A0C0,0xE70747C4,0x82299971,0xE8922622,0x81E26C16,0xEA1DEBBB, +0x81A01B6D,0xEBAA894F,0x8162AA04,0xED37EF91,0x812A1A3A,0xEEC60F31,0x80F66E3C, +0xF054D8D5,0x80C7A80A,0xF1E43D1C,0x809DC971,0xF3742CA2,0x8078D40D,0xF50497FB, +0x8058C94C,0xF6956FB7,0x803DAA6A,0xF826A462,0x80277872,0xF9B82684,0x80163440, +0xFB49E6A3,0x8009DE7E,0xFCDBD541,0x800277A6,0xFE6DE2E0,0x7FFFFFFF,0x00000000, +0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2,0x7E9D55FC,0xED37EF91,0x7D8A5F40, +0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B,0xDAD7F3A2,0x78848414,0xD4E0CB15, +0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC,0x70E2CBC6,0xC3A94590,0x6DCA0D14, +0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120,0xB3C0200C,0x62F201AC,0xAECC336C, +0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666,0x55F5A4D2,0xA1288376,0x5133CC94, +0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7,0x9592675C,0x41CE1E65,0x9235F2EC, +0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F,0x30FBC54D,0x89BE50C3,0x2B1F34EB, +0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B,0x83D60412,0x18F8B83C,0x8275A0C0, +0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971,0x0647D97C,0x80277872,0x00000000, +0x80000000,0xF9B82684,0x80277872,0xF3742CA2,0x809DC971,0xED37EF91,0x8162AA04, +0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412,0xDAD7F3A2,0x8582FAA5,0xD4E0CB15, +0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC,0x8C4A142F,0xC3A94590,0x8F1D343A, +0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C,0xB3C0200C,0x99307EE0,0xAECC336C, +0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666,0xA57D8666,0xA1288376,0xAA0A5B2E, +0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C,0x9592675C,0xB8E31319,0x9235F2EC, +0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F,0xC945DFEC,0x89BE50C3,0xCF043AB3, +0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2,0x83D60412,0xE0E60685,0x8275A0C0, +0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971,0xF3742CA2,0x80277872,0xF9B82684, +0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D,0xCF043AB3,0x6A6D98A4, +0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C,0x30FBC54D,0x89BE50C3, +0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4,0x8275A0C0,0xCF043AB3, +0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666,0x9592675C,0xB8E31319, +0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF,0x00000000,0x5A82799A, +0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFA72C,0xFF69343F,0x7FFE9CB2,0xFED2694F,0x7FFCE093, +0xFE3BA002,0x7FFA72D1,0xFDA4D929,0x7FF75370,0xFD0E1594,0x7FF38274,0xFC775616, +0x7FEEFFE1,0xFBE09B80,0x7FE9CBC0,0xFB49E6A3,0x7FE3E616,0xFAB3384F,0x7FDD4EEC, +0xFA1C9157,0x7FD6064C,0xF985F28A,0x7FCE0C3E,0xF8EF5CBB,0x7FC560CF,0xF858D0BB, +0x7FBC040A,0xF7C24F59,0x7FB1F5FC,0xF72BD967,0x7FA736B4,0xF6956FB7,0x7F9BC640, +0xF5FF1318,0x7F8FA4B0,0xF568C45B,0x7F82D214,0xF4D28451,0x7F754E80,0xF43C53CB, +0x7F671A05,0xF3A63398,0x7F5834B7,0xF310248A,0x7F489EAA,0xF27A2771,0x7F3857F6, +0xF1E43D1C,0x7F2760AF,0xF14E665C,0x7F15B8EE,0xF0B8A401,0x7F0360CB,0xF022F6DA, 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+0xB5049368,0x67BD0FBD,0xB6F0A812,0x6919E320,0xB8E31319,0x6A6D98A4,0xBADBA943, +0x6BB812D1,0xBCDA3ECB,0x6CF934FC,0xBEDEA765,0x6E30E34A,0xC0E8B648,0x6F5F02B2, +0xC2F83E2A,0x708378FF,0xC50D1149,0x719E2CD2,0xC727016D,0x72AF05A7,0xC945DFEC, +0x73B5EBD1,0xCB697DB0,0x74B2C884,0xCD91AB39,0x75A585CF,0xCFBE389F,0x768E0EA6, +0xD1EEF59E,0x776C4EDB,0xD423B191,0x78403329,0xD65C3B7B,0x7909A92D,0xD898620C, +0x79C89F6E,0xDAD7F3A2,0x7A7D055B,0xDD1ABE51,0x7B26CB4F,0xDF608FE4,0x7BC5E290, +0xE1A935E2,0x7C5A3D50,0xE3F47D96,0x7CE3CEB2,0xE642340D,0x7D628AC6,0xE8922622, +0x7DD6668F,0xEAE4207A,0x7E3F57FF,0xED37EF91,0x7E9D55FC,0xEF8D5FB8,0x7EF05860, +0xF1E43D1C,0x7F3857F6,0xF43C53CB,0x7F754E80,0xF6956FB7,0x7FA736B4,0xF8EF5CBB, +0x7FCE0C3E,0xFB49E6A3,0x7FE9CBC0,0xFDA4D929,0x7FFA72D1,0x7FFFFFFF,0x00000000, +0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91,0x7CE3CEB2,0xE3F47D96,0x7A7D055B, +0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1,0xC945DFEC,0x6F5F02B2,0xC0E8B648, +0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B,0x5ED77C8A,0xAA0A5B2E,0x5842DD54, +0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533,0x9759617F,0x41CE1E65,0x9235F2EC, +0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3,0x2826B928,0x8675DC4F,0x1F19F97B, +0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E,0x809DC971,0x03242ABF,0x8009DE7E, +0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C,0xE70747C4,0x8275A0C0,0xDDDC5B3B, +0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79,0x8AFB2CBB,0xC3A94590,0x8F1D343A, +0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0,0xAC64D510,0x9F13C7D0,0xA57D8666, +0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0,0xB3C0200C,0x93DBD6A0,0xBB8532B0, +0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79,0x877B7BEC,0xD4E0CB15,0x84A2FC62, +0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C,0xF054D8D5,0x80277872,0xF9B82684, +0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E,0x81E26C16,0x15E21445,0x83D60412, +0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3,0x30FBC54D,0x8DAAD37B,0x398CDD32, +0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533,0x9D0DFE54,0x5133CC94,0xA34BDF20, +0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B,0x64E88926,0xB8E31319,0x6A6D98A4, +0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1,0xD1EEF59E,0x776C4EDB,0xDAD7F3A2, +0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91,0x7E9D55FC,0xF6956FB7,0x7FA736B4, +0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4,0xB8E31319,0x5133CC94, +0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971,0xE70747C4,0x8275A0C0, +0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A,0xC3A94590,0x8275A0C0, +0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D,0x9D0DFE54,0x5133CC94, +0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF,0x00000000,0x30FBC54D, +0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]={ +0,0,}; + +q15_t rearranged_twiddle_stride1_16_q15[8]={ +0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_16_q15[8]={ +0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_16_q15[8]={ +0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]={ +0,32,0,}; + +q15_t rearranged_twiddle_stride1_64_q15[40]={ +0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642,0xCF04,0x70E3, +0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E,0x5134,0x9D0E,0x471D,0x9592, +0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9,0x8276,0x0C8C,0x809E,0x7FFF, +0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_64_q15[40]={ +0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82,0xA57E,0x471D, +0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000,0xE707,0x8276,0xCF04,0x89BE, +0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE,0xCF04,0x8276,0xE707,0x7FFF, +0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_64_q15[40]={ +0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC,0x89BE,0x0C8C, +0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9,0x8276,0xE707, +0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8,0x7A7D,0x7FFF, +0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]={ +0,128,160,0,}; + +q15_t rearranged_twiddle_stride1_256_q15[168]={ +0x7FFF,0x0000,0x7FF6,0xFCDC,0x7FD9,0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A, +0xF055,0x7E9D,0xED38,0x7E1E,0xEA1E,0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6, +0x7B5D,0xDDDC,0x7A7D,0xDAD8,0x798A,0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642, +0xCF04,0x7505,0xCC21,0x73B6,0xC946,0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9, +0x6DCA,0xBE32,0x6C24,0xBB85,0x6A6E,0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9, +0xB140,0x62F2,0xAECC,0x60EC,0xAC65,0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E, +0x5843,0xA34C,0x55F6,0xA129,0x539B,0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40, +0x9930,0x49B4,0x9759,0x471D,0x9592,0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1, +0x3C57,0x8F1D,0x398D,0x8DAB,0x36BA,0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11, +0x8894,0x2B1F,0x877B,0x2827,0x8676,0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6, +0x1C0C,0x831C,0x18F9,0x8276,0x15E2,0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C, +0x809E,0x096B,0x8059,0x0648,0x8027,0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374, +0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642,0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2, +0xAECC,0x5A82,0xA57E,0x5134,0x9D0E,0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE, +0x2528,0x8583,0x18F9,0x8276,0x0C8C,0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82, +0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_256_q15[168]={ +0x7FFF,0x0000,0x7FD9,0xF9B8,0x7F62,0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A, +0xE0E6,0x7A7D,0xDAD8,0x7885,0xD4E1,0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9, +0x6DCA,0xBE32,0x6A6E,0xB8E3,0x66D0,0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82, +0xA57E,0x55F6,0xA129,0x5134,0x9D0E,0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236, +0x3C57,0x8F1D,0x36BA,0x8C4A,0x30FC,0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A, +0x83D6,0x18F9,0x8276,0x12C8,0x8163,0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000, +0xF9B8,0x8027,0xF374,0x809E,0xED38,0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8, +0x8583,0xD4E1,0x877B,0xCF04,0x89BE,0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236, +0xB8E3,0x9592,0xB3C0,0x9930,0xAECC,0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129, +0xAA0A,0x9D0E,0xAECC,0x9930,0xB3C0,0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9, +0x8C4A,0xC946,0x89BE,0xCF04,0x877B,0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276, +0xE707,0x8163,0xED38,0x809E,0xF374,0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707, +0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82,0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9, +0x8276,0x0000,0x8000,0xE707,0x8276,0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E, +0x9592,0xB8E3,0x89BE,0xCF04,0x8276,0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000, +0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_256_q15[168]={ +0x7FFF,0x0000,0x7FA7,0xF695,0x7E9D,0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C, +0xD1EF,0x73B6,0xC946,0x6F5F,0xC0E9,0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A, +0x5843,0xA34C,0x5134,0x9D0E,0x49B4,0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC, +0x89BE,0x2827,0x8676,0x1F1A,0x83D6,0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A, +0xF9B8,0x8027,0xF055,0x80F6,0xE707,0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21, +0x8AFB,0xC3A9,0x8F1D,0xBB85,0x93DC,0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E, +0x9F14,0xAC65,0x9930,0xB3C0,0x93DC,0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B, +0xD4E1,0x84A3,0xDDDC,0x8276,0xE707,0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324, +0x809E,0x0C8C,0x81E2,0x15E2,0x83D6,0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB, +0x398D,0x9236,0x41CE,0x9759,0x49B4,0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7, +0xB140,0x64E9,0xB8E3,0x6A6E,0xC0E9,0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8, +0x7A7D,0xE3F4,0x7CE4,0xED38,0x7E9D,0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8, +0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC,0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9, +0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9,0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC, +0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8,0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E, +0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]={ +0,512,640,672,0,}; + +q15_t rearranged_twiddle_stride1_1024_q15[680]={ +0x7FFF,0x0000,0x7FFF,0xFF37,0x7FFE,0xFE6E,0x7FFA,0xFDA5,0x7FF6,0xFCDC,0x7FF1, +0xFC13,0x7FEA,0xFB4A,0x7FE2,0xFA81,0x7FD9,0xF9B8,0x7FCE,0xF8EF,0x7FC2,0xF827, +0x7FB5,0xF75E,0x7FA7,0xF695,0x7F98,0xF5CD,0x7F87,0xF505,0x7F75,0xF43C,0x7F62, +0xF374,0x7F4E,0xF2AC,0x7F38,0xF1E4,0x7F22,0xF11C,0x7F0A,0xF055,0x7EF0,0xEF8D, +0x7ED6,0xEEC6,0x7EBA,0xEDFF,0x7E9D,0xED38,0x7E7F,0xEC71,0x7E60,0xEBAB,0x7E3F, +0xEAE4,0x7E1E,0xEA1E,0x7DFB,0xE958,0x7DD6,0xE892,0x7DB1,0xE7CD,0x7D8A,0xE707, +0x7D63,0xE642,0x7D3A,0xE57D,0x7D0F,0xE4B9,0x7CE4,0xE3F4,0x7CB7,0xE330,0x7C89, +0xE26D,0x7C5A,0xE1A9,0x7C2A,0xE0E6,0x7BF9,0xE023,0x7BC6,0xDF61,0x7B92,0xDE9E, +0x7B5D,0xDDDC,0x7B27,0xDD1B,0x7AEF,0xDC59,0x7AB7,0xDB99,0x7A7D,0xDAD8,0x7A42, +0xDA18,0x7A06,0xD958,0x79C9,0xD898,0x798A,0xD7D9,0x794A,0xD71B,0x790A,0xD65C, +0x78C8,0xD59E,0x7885,0xD4E1,0x7840,0xD424,0x77FB,0xD367,0x77B4,0xD2AB,0x776C, +0xD1EF,0x7723,0xD134,0x76D9,0xD079,0x768E,0xCFBE,0x7642,0xCF04,0x75F4,0xCE4B, +0x75A6,0xCD92,0x7556,0xCCD9,0x7505,0xCC21,0x74B3,0xCB69,0x7460,0xCAB2,0x740B, +0xC9FC,0x73B6,0xC946,0x735F,0xC890,0x7308,0xC7DB,0x72AF,0xC727,0x7255,0xC673, +0x71FA,0xC5C0,0x719E,0xC50D,0x7141,0xC45B,0x70E3,0xC3A9,0x7083,0xC2F8,0x7023, +0xC248,0x6FC2,0xC198,0x6F5F,0xC0E9,0x6EFB,0xC03A,0x6E97,0xBF8C,0x6E31,0xBEDF, +0x6DCA,0xBE32,0x6D62,0xBD86,0x6CF9,0xBCDA,0x6C8F,0xBC2F,0x6C24,0xBB85,0x6BB8, +0xBADC,0x6B4B,0xBA33,0x6ADD,0xB98B,0x6A6E,0xB8E3,0x69FD,0xB83C,0x698C,0xB796, +0x691A,0xB6F1,0x68A7,0xB64C,0x6832,0xB5A8,0x67BD,0xB505,0x6747,0xB462,0x66D0, +0xB3C0,0x6657,0xB31F,0x65DE,0xB27F,0x6564,0xB1DF,0x64E9,0xB140,0x646C,0xB0A2, +0x63EF,0xB005,0x6371,0xAF68,0x62F2,0xAECC,0x6272,0xAE31,0x61F1,0xAD97,0x616F, +0xACFD,0x60EC,0xAC65,0x6068,0xABCD,0x5FE4,0xAB36,0x5F5E,0xAAA0,0x5ED7,0xAA0A, +0x5E50,0xA976,0x5DC8,0xA8E2,0x5D3E,0xA84F,0x5CB4,0xA7BD,0x5C29,0xA72C,0x5B9D, +0xA69C,0x5B10,0xA60C,0x5A82,0xA57E,0x59F4,0xA4F0,0x5964,0xA463,0x58D4,0xA3D7, +0x5843,0xA34C,0x57B1,0xA2C2,0x571E,0xA238,0x568A,0xA1B0,0x55F6,0xA129,0x5560, +0xA0A2,0x54CA,0xA01C,0x5433,0x9F98,0x539B,0x9F14,0x5303,0x9E91,0x5269,0x9E0F, +0x51CF,0x9D8E,0x5134,0x9D0E,0x5098,0x9C8F,0x4FFB,0x9C11,0x4F5E,0x9B94,0x4EC0, +0x9B17,0x4E21,0x9A9C,0x4D81,0x9A22,0x4CE1,0x99A9,0x4C40,0x9930,0x4B9E,0x98B9, +0x4AFB,0x9843,0x4A58,0x97CE,0x49B4,0x9759,0x490F,0x96E6,0x486A,0x9674,0x47C4, +0x9603,0x471D,0x9592,0x4675,0x9523,0x45CD,0x94B5,0x4524,0x9448,0x447B,0x93DC, +0x43D1,0x9371,0x4326,0x9307,0x427A,0x929E,0x41CE,0x9236,0x4121,0x91CF,0x4074, +0x9169,0x3FC6,0x9105,0x3F17,0x90A1,0x3E68,0x903E,0x3DB8,0x8FDD,0x3D08,0x8F7D, +0x3C57,0x8F1D,0x3BA5,0x8EBF,0x3AF3,0x8E62,0x3A40,0x8E06,0x398D,0x8DAB,0x38D9, +0x8D51,0x3825,0x8CF8,0x3770,0x8CA1,0x36BA,0x8C4A,0x3604,0x8BF5,0x354E,0x8BA0, +0x3497,0x8B4D,0x33DF,0x8AFB,0x3327,0x8AAA,0x326E,0x8A5A,0x31B5,0x8A0C,0x30FC, +0x89BE,0x3042,0x8972,0x2F87,0x8927,0x2ECC,0x88DD,0x2E11,0x8894,0x2D55,0x884C, +0x2C99,0x8805,0x2BDC,0x87C0,0x2B1F,0x877B,0x2A62,0x8738,0x29A4,0x86F6,0x28E5, +0x86B6,0x2827,0x8676,0x2768,0x8637,0x26A8,0x85FA,0x25E8,0x85BE,0x2528,0x8583, +0x2467,0x8549,0x23A7,0x8511,0x22E5,0x84D9,0x2224,0x84A3,0x2162,0x846E,0x209F, +0x843A,0x1FDD,0x8407,0x1F1A,0x83D6,0x1E57,0x83A6,0x1D93,0x8377,0x1CD0,0x8349, +0x1C0C,0x831C,0x1B47,0x82F1,0x1A83,0x82C6,0x19BE,0x829D,0x18F9,0x8276,0x1833, +0x824F,0x176E,0x822A,0x16A8,0x8205,0x15E2,0x81E2,0x151C,0x81C1,0x1455,0x81A0, +0x138F,0x8181,0x12C8,0x8163,0x1201,0x8146,0x113A,0x812A,0x1073,0x8110,0x0FAB, +0x80F6,0x0EE4,0x80DE,0x0E1C,0x80C8,0x0D54,0x80B2,0x0C8C,0x809E,0x0BC4,0x808B, +0x0AFB,0x8079,0x0A33,0x8068,0x096B,0x8059,0x08A2,0x804B,0x07D9,0x803E,0x0711, +0x8032,0x0648,0x8027,0x057F,0x801E,0x04B6,0x8016,0x03ED,0x800F,0x0324,0x800A, +0x025B,0x8006,0x0192,0x8002,0x00C9,0x8001,0x7FFF,0x0000,0x7FF6,0xFCDC,0x7FD9, +0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A,0xF055,0x7E9D,0xED38,0x7E1E,0xEA1E, +0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6,0x7B5D,0xDDDC,0x7A7D,0xDAD8,0x798A, +0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642,0xCF04,0x7505,0xCC21,0x73B6,0xC946, +0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9,0x6DCA,0xBE32,0x6C24,0xBB85,0x6A6E, +0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9,0xB140,0x62F2,0xAECC,0x60EC,0xAC65, +0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E,0x5843,0xA34C,0x55F6,0xA129,0x539B, +0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40,0x9930,0x49B4,0x9759,0x471D,0x9592, +0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1,0x3C57,0x8F1D,0x398D,0x8DAB,0x36BA, +0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11,0x8894,0x2B1F,0x877B,0x2827,0x8676, +0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6,0x1C0C,0x831C,0x18F9,0x8276,0x15E2, +0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C,0x809E,0x096B,0x8059,0x0648,0x8027, +0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642, +0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E,0x5134,0x9D0E, +0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9,0x8276,0x0C8C, +0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_1024_q15[680]={ +0x7FFF,0x0000,0x7FFE,0xFE6E,0x7FF6,0xFCDC,0x7FEA,0xFB4A,0x7FD9,0xF9B8,0x7FC2, +0xF827,0x7FA7,0xF695,0x7F87,0xF505,0x7F62,0xF374,0x7F38,0xF1E4,0x7F0A,0xF055, +0x7ED6,0xEEC6,0x7E9D,0xED38,0x7E60,0xEBAB,0x7E1E,0xEA1E,0x7DD6,0xE892,0x7D8A, +0xE707,0x7D3A,0xE57D,0x7CE4,0xE3F4,0x7C89,0xE26D,0x7C2A,0xE0E6,0x7BC6,0xDF61, +0x7B5D,0xDDDC,0x7AEF,0xDC59,0x7A7D,0xDAD8,0x7A06,0xD958,0x798A,0xD7D9,0x790A, +0xD65C,0x7885,0xD4E1,0x77FB,0xD367,0x776C,0xD1EF,0x76D9,0xD079,0x7642,0xCF04, +0x75A6,0xCD92,0x7505,0xCC21,0x7460,0xCAB2,0x73B6,0xC946,0x7308,0xC7DB,0x7255, +0xC673,0x719E,0xC50D,0x70E3,0xC3A9,0x7023,0xC248,0x6F5F,0xC0E9,0x6E97,0xBF8C, +0x6DCA,0xBE32,0x6CF9,0xBCDA,0x6C24,0xBB85,0x6B4B,0xBA33,0x6A6E,0xB8E3,0x698C, +0xB796,0x68A7,0xB64C,0x67BD,0xB505,0x66D0,0xB3C0,0x65DE,0xB27F,0x64E9,0xB140, +0x63EF,0xB005,0x62F2,0xAECC,0x61F1,0xAD97,0x60EC,0xAC65,0x5FE4,0xAB36,0x5ED7, +0xAA0A,0x5DC8,0xA8E2,0x5CB4,0xA7BD,0x5B9D,0xA69C,0x5A82,0xA57E,0x5964,0xA463, +0x5843,0xA34C,0x571E,0xA238,0x55F6,0xA129,0x54CA,0xA01C,0x539B,0x9F14,0x5269, +0x9E0F,0x5134,0x9D0E,0x4FFB,0x9C11,0x4EC0,0x9B17,0x4D81,0x9A22,0x4C40,0x9930, +0x4AFB,0x9843,0x49B4,0x9759,0x486A,0x9674,0x471D,0x9592,0x45CD,0x94B5,0x447B, +0x93DC,0x4326,0x9307,0x41CE,0x9236,0x4074,0x9169,0x3F17,0x90A1,0x3DB8,0x8FDD, +0x3C57,0x8F1D,0x3AF3,0x8E62,0x398D,0x8DAB,0x3825,0x8CF8,0x36BA,0x8C4A,0x354E, +0x8BA0,0x33DF,0x8AFB,0x326E,0x8A5A,0x30FC,0x89BE,0x2F87,0x8927,0x2E11,0x8894, +0x2C99,0x8805,0x2B1F,0x877B,0x29A4,0x86F6,0x2827,0x8676,0x26A8,0x85FA,0x2528, +0x8583,0x23A7,0x8511,0x2224,0x84A3,0x209F,0x843A,0x1F1A,0x83D6,0x1D93,0x8377, +0x1C0C,0x831C,0x1A83,0x82C6,0x18F9,0x8276,0x176E,0x822A,0x15E2,0x81E2,0x1455, +0x81A0,0x12C8,0x8163,0x113A,0x812A,0x0FAB,0x80F6,0x0E1C,0x80C8,0x0C8C,0x809E, +0x0AFB,0x8079,0x096B,0x8059,0x07D9,0x803E,0x0648,0x8027,0x04B6,0x8016,0x0324, +0x800A,0x0192,0x8002,0x0000,0x8000,0xFE6E,0x8002,0xFCDC,0x800A,0xFB4A,0x8016, +0xF9B8,0x8027,0xF827,0x803E,0xF695,0x8059,0xF505,0x8079,0xF374,0x809E,0xF1E4, +0x80C8,0xF055,0x80F6,0xEEC6,0x812A,0xED38,0x8163,0xEBAB,0x81A0,0xEA1E,0x81E2, +0xE892,0x822A,0xE707,0x8276,0xE57D,0x82C6,0xE3F4,0x831C,0xE26D,0x8377,0xE0E6, +0x83D6,0xDF61,0x843A,0xDDDC,0x84A3,0xDC59,0x8511,0xDAD8,0x8583,0xD958,0x85FA, +0xD7D9,0x8676,0xD65C,0x86F6,0xD4E1,0x877B,0xD367,0x8805,0xD1EF,0x8894,0xD079, +0x8927,0xCF04,0x89BE,0xCD92,0x8A5A,0xCC21,0x8AFB,0xCAB2,0x8BA0,0xC946,0x8C4A, +0xC7DB,0x8CF8,0xC673,0x8DAB,0xC50D,0x8E62,0xC3A9,0x8F1D,0xC248,0x8FDD,0xC0E9, +0x90A1,0xBF8C,0x9169,0xBE32,0x9236,0xBCDA,0x9307,0xBB85,0x93DC,0xBA33,0x94B5, +0xB8E3,0x9592,0xB796,0x9674,0xB64C,0x9759,0xB505,0x9843,0xB3C0,0x9930,0xB27F, +0x9A22,0xB140,0x9B17,0xB005,0x9C11,0xAECC,0x9D0E,0xAD97,0x9E0F,0xAC65,0x9F14, +0xAB36,0xA01C,0xAA0A,0xA129,0xA8E2,0xA238,0xA7BD,0xA34C,0xA69C,0xA463,0xA57E, +0xA57E,0xA463,0xA69C,0xA34C,0xA7BD,0xA238,0xA8E2,0xA129,0xAA0A,0xA01C,0xAB36, +0x9F14,0xAC65,0x9E0F,0xAD97,0x9D0E,0xAECC,0x9C11,0xB005,0x9B17,0xB140,0x9A22, +0xB27F,0x9930,0xB3C0,0x9843,0xB505,0x9759,0xB64C,0x9674,0xB796,0x9592,0xB8E3, +0x94B5,0xBA33,0x93DC,0xBB85,0x9307,0xBCDA,0x9236,0xBE32,0x9169,0xBF8C,0x90A1, +0xC0E9,0x8FDD,0xC248,0x8F1D,0xC3A9,0x8E62,0xC50D,0x8DAB,0xC673,0x8CF8,0xC7DB, +0x8C4A,0xC946,0x8BA0,0xCAB2,0x8AFB,0xCC21,0x8A5A,0xCD92,0x89BE,0xCF04,0x8927, +0xD079,0x8894,0xD1EF,0x8805,0xD367,0x877B,0xD4E1,0x86F6,0xD65C,0x8676,0xD7D9, +0x85FA,0xD958,0x8583,0xDAD8,0x8511,0xDC59,0x84A3,0xDDDC,0x843A,0xDF61,0x83D6, +0xE0E6,0x8377,0xE26D,0x831C,0xE3F4,0x82C6,0xE57D,0x8276,0xE707,0x822A,0xE892, +0x81E2,0xEA1E,0x81A0,0xEBAB,0x8163,0xED38,0x812A,0xEEC6,0x80F6,0xF055,0x80C8, +0xF1E4,0x809E,0xF374,0x8079,0xF505,0x8059,0xF695,0x803E,0xF827,0x8027,0xF9B8, +0x8016,0xFB4A,0x800A,0xFCDC,0x8002,0xFE6E,0x7FFF,0x0000,0x7FD9,0xF9B8,0x7F62, +0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A,0xE0E6,0x7A7D,0xDAD8,0x7885,0xD4E1, +0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9,0x6DCA,0xBE32,0x6A6E,0xB8E3,0x66D0, +0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82,0xA57E,0x55F6,0xA129,0x5134,0x9D0E, +0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236,0x3C57,0x8F1D,0x36BA,0x8C4A,0x30FC, +0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A,0x83D6,0x18F9,0x8276,0x12C8,0x8163, +0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000,0xF9B8,0x8027,0xF374,0x809E,0xED38, +0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8,0x8583,0xD4E1,0x877B,0xCF04,0x89BE, +0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236,0xB8E3,0x9592,0xB3C0,0x9930,0xAECC, +0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129,0xAA0A,0x9D0E,0xAECC,0x9930,0xB3C0, +0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9,0x8C4A,0xC946,0x89BE,0xCF04,0x877B, +0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276,0xE707,0x8163,0xED38,0x809E,0xF374, +0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82, +0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000,0xE707,0x8276, +0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE,0xCF04,0x8276, +0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_1024_q15[680]={ +0x7FFF,0x0000,0x7FFA,0xFDA5,0x7FEA,0xFB4A,0x7FCE,0xF8EF,0x7FA7,0xF695,0x7F75, +0xF43C,0x7F38,0xF1E4,0x7EF0,0xEF8D,0x7E9D,0xED38,0x7E3F,0xEAE4,0x7DD6,0xE892, +0x7D63,0xE642,0x7CE4,0xE3F4,0x7C5A,0xE1A9,0x7BC6,0xDF61,0x7B27,0xDD1B,0x7A7D, +0xDAD8,0x79C9,0xD898,0x790A,0xD65C,0x7840,0xD424,0x776C,0xD1EF,0x768E,0xCFBE, +0x75A6,0xCD92,0x74B3,0xCB69,0x73B6,0xC946,0x72AF,0xC727,0x719E,0xC50D,0x7083, +0xC2F8,0x6F5F,0xC0E9,0x6E31,0xBEDF,0x6CF9,0xBCDA,0x6BB8,0xBADC,0x6A6E,0xB8E3, +0x691A,0xB6F1,0x67BD,0xB505,0x6657,0xB31F,0x64E9,0xB140,0x6371,0xAF68,0x61F1, +0xAD97,0x6068,0xABCD,0x5ED7,0xAA0A,0x5D3E,0xA84F,0x5B9D,0xA69C,0x59F4,0xA4F0, +0x5843,0xA34C,0x568A,0xA1B0,0x54CA,0xA01C,0x5303,0x9E91,0x5134,0x9D0E,0x4F5E, +0x9B94,0x4D81,0x9A22,0x4B9E,0x98B9,0x49B4,0x9759,0x47C4,0x9603,0x45CD,0x94B5, +0x43D1,0x9371,0x41CE,0x9236,0x3FC6,0x9105,0x3DB8,0x8FDD,0x3BA5,0x8EBF,0x398D, +0x8DAB,0x3770,0x8CA1,0x354E,0x8BA0,0x3327,0x8AAA,0x30FC,0x89BE,0x2ECC,0x88DD, +0x2C99,0x8805,0x2A62,0x8738,0x2827,0x8676,0x25E8,0x85BE,0x23A7,0x8511,0x2162, +0x846E,0x1F1A,0x83D6,0x1CD0,0x8349,0x1A83,0x82C6,0x1833,0x824F,0x15E2,0x81E2, +0x138F,0x8181,0x113A,0x812A,0x0EE4,0x80DE,0x0C8C,0x809E,0x0A33,0x8068,0x07D9, +0x803E,0x057F,0x801E,0x0324,0x800A,0x00C9,0x8001,0xFE6E,0x8002,0xFC13,0x800F, +0xF9B8,0x8027,0xF75E,0x804B,0xF505,0x8079,0xF2AC,0x80B2,0xF055,0x80F6,0xEDFF, +0x8146,0xEBAB,0x81A0,0xE958,0x8205,0xE707,0x8276,0xE4B9,0x82F1,0xE26D,0x8377, +0xE023,0x8407,0xDDDC,0x84A3,0xDB99,0x8549,0xD958,0x85FA,0xD71B,0x86B6,0xD4E1, +0x877B,0xD2AB,0x884C,0xD079,0x8927,0xCE4B,0x8A0C,0xCC21,0x8AFB,0xC9FC,0x8BF5, +0xC7DB,0x8CF8,0xC5C0,0x8E06,0xC3A9,0x8F1D,0xC198,0x903E,0xBF8C,0x9169,0xBD86, +0x929E,0xBB85,0x93DC,0xB98B,0x9523,0xB796,0x9674,0xB5A8,0x97CE,0xB3C0,0x9930, +0xB1DF,0x9A9C,0xB005,0x9C11,0xAE31,0x9D8E,0xAC65,0x9F14,0xAAA0,0xA0A2,0xA8E2, +0xA238,0xA72C,0xA3D7,0xA57E,0xA57E,0xA3D7,0xA72C,0xA238,0xA8E2,0xA0A2,0xAAA0, +0x9F14,0xAC65,0x9D8E,0xAE31,0x9C11,0xB005,0x9A9C,0xB1DF,0x9930,0xB3C0,0x97CE, +0xB5A8,0x9674,0xB796,0x9523,0xB98B,0x93DC,0xBB85,0x929E,0xBD86,0x9169,0xBF8C, +0x903E,0xC198,0x8F1D,0xC3A9,0x8E06,0xC5C0,0x8CF8,0xC7DB,0x8BF5,0xC9FC,0x8AFB, +0xCC21,0x8A0C,0xCE4B,0x8927,0xD079,0x884C,0xD2AB,0x877B,0xD4E1,0x86B6,0xD71B, +0x85FA,0xD958,0x8549,0xDB99,0x84A3,0xDDDC,0x8407,0xE023,0x8377,0xE26D,0x82F1, +0xE4B9,0x8276,0xE707,0x8205,0xE958,0x81A0,0xEBAB,0x8146,0xEDFF,0x80F6,0xF055, +0x80B2,0xF2AC,0x8079,0xF505,0x804B,0xF75E,0x8027,0xF9B8,0x800F,0xFC13,0x8002, +0xFE6E,0x8001,0x00C9,0x800A,0x0324,0x801E,0x057F,0x803E,0x07D9,0x8068,0x0A33, +0x809E,0x0C8C,0x80DE,0x0EE4,0x812A,0x113A,0x8181,0x138F,0x81E2,0x15E2,0x824F, +0x1833,0x82C6,0x1A83,0x8349,0x1CD0,0x83D6,0x1F1A,0x846E,0x2162,0x8511,0x23A7, +0x85BE,0x25E8,0x8676,0x2827,0x8738,0x2A62,0x8805,0x2C99,0x88DD,0x2ECC,0x89BE, +0x30FC,0x8AAA,0x3327,0x8BA0,0x354E,0x8CA1,0x3770,0x8DAB,0x398D,0x8EBF,0x3BA5, +0x8FDD,0x3DB8,0x9105,0x3FC6,0x9236,0x41CE,0x9371,0x43D1,0x94B5,0x45CD,0x9603, +0x47C4,0x9759,0x49B4,0x98B9,0x4B9E,0x9A22,0x4D81,0x9B94,0x4F5E,0x9D0E,0x5134, +0x9E91,0x5303,0xA01C,0x54CA,0xA1B0,0x568A,0xA34C,0x5843,0xA4F0,0x59F4,0xA69C, +0x5B9D,0xA84F,0x5D3E,0xAA0A,0x5ED7,0xABCD,0x6068,0xAD97,0x61F1,0xAF68,0x6371, +0xB140,0x64E9,0xB31F,0x6657,0xB505,0x67BD,0xB6F1,0x691A,0xB8E3,0x6A6E,0xBADC, +0x6BB8,0xBCDA,0x6CF9,0xBEDF,0x6E31,0xC0E9,0x6F5F,0xC2F8,0x7083,0xC50D,0x719E, +0xC727,0x72AF,0xC946,0x73B6,0xCB69,0x74B3,0xCD92,0x75A6,0xCFBE,0x768E,0xD1EF, +0x776C,0xD424,0x7840,0xD65C,0x790A,0xD898,0x79C9,0xDAD8,0x7A7D,0xDD1B,0x7B27, +0xDF61,0x7BC6,0xE1A9,0x7C5A,0xE3F4,0x7CE4,0xE642,0x7D63,0xE892,0x7DD6,0xEAE4, +0x7E3F,0xED38,0x7E9D,0xEF8D,0x7EF0,0xF1E4,0x7F38,0xF43C,0x7F75,0xF695,0x7FA7, +0xF8EF,0x7FCE,0xFB4A,0x7FEA,0xFDA5,0x7FFA,0x7FFF,0x0000,0x7FA7,0xF695,0x7E9D, +0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C,0xD1EF,0x73B6,0xC946,0x6F5F,0xC0E9, +0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A,0x5843,0xA34C,0x5134,0x9D0E,0x49B4, +0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC,0x89BE,0x2827,0x8676,0x1F1A,0x83D6, +0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A,0xF9B8,0x8027,0xF055,0x80F6,0xE707, +0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21,0x8AFB,0xC3A9,0x8F1D,0xBB85,0x93DC, +0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E,0x9F14,0xAC65,0x9930,0xB3C0,0x93DC, +0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B,0xD4E1,0x84A3,0xDDDC,0x8276,0xE707, +0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324,0x809E,0x0C8C,0x81E2,0x15E2,0x83D6, +0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB,0x398D,0x9236,0x41CE,0x9759,0x49B4, +0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7,0xB140,0x64E9,0xB8E3,0x6A6E,0xC0E9, +0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8,0x7A7D,0xE3F4,0x7CE4,0xED38,0x7E9D, +0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC, +0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9, +0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8, +0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +q15_t rearranged_twiddle_stride1_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFFCE,0x7FFF,0xFF9B,0x7FFF,0xFF69,0x7FFF,0xFF37,0x7FFF, +0xFF05,0x7FFF,0xFED2,0x7FFE,0xFEA0,0x7FFE,0xFE6E,0x7FFD,0xFE3C,0x7FFC,0xFE09, +0x7FFB,0xFDD7,0x7FFA,0xFDA5,0x7FF9,0xFD73,0x7FF8,0xFD40,0x7FF7,0xFD0E,0x7FF6, +0xFCDC,0x7FF5,0xFCAA,0x7FF4,0xFC77,0x7FF2,0xFC45,0x7FF1,0xFC13,0x7FEF,0xFBE1, +0x7FED,0xFBAE,0x7FEC,0xFB7C,0x7FEA,0xFB4A,0x7FE8,0xFB18,0x7FE6,0xFAE5,0x7FE4, +0xFAB3,0x7FE2,0xFA81,0x7FE0,0xFA4F,0x7FDD,0xFA1D,0x7FDB,0xF9EA,0x7FD9,0xF9B8, +0x7FD6,0xF986,0x7FD3,0xF954,0x7FD1,0xF922,0x7FCE,0xF8EF,0x7FCB,0xF8BD,0x7FC8, +0xF88B,0x7FC5,0xF859,0x7FC2,0xF827,0x7FBF,0xF7F4,0x7FBC,0xF7C2,0x7FB9,0xF790, +0x7FB5,0xF75E,0x7FB2,0xF72C,0x7FAE,0xF6FA,0x7FAB,0xF6C8,0x7FA7,0xF695,0x7FA3, +0xF663,0x7FA0,0xF631,0x7F9C,0xF5FF,0x7F98,0xF5CD,0x7F94,0xF59B,0x7F90,0xF569, +0x7F8B,0xF537,0x7F87,0xF505,0x7F83,0xF4D3,0x7F7E,0xF4A0,0x7F7A,0xF46E,0x7F75, +0xF43C,0x7F71,0xF40A,0x7F6C,0xF3D8,0x7F67,0xF3A6,0x7F62,0xF374,0x7F5D,0xF342, +0x7F58,0xF310,0x7F53,0xF2DE,0x7F4E,0xF2AC,0x7F49,0xF27A,0x7F43,0xF248,0x7F3E, +0xF216,0x7F38,0xF1E4,0x7F33,0xF1B2,0x7F2D,0xF180,0x7F27,0xF14E,0x7F22,0xF11C, +0x7F1C,0xF0EB,0x7F16,0xF0B9,0x7F10,0xF087,0x7F0A,0xF055,0x7F03,0xF023,0x7EFD, +0xEFF1,0x7EF7,0xEFBF,0x7EF0,0xEF8D,0x7EEA,0xEF5C,0x7EE3,0xEF2A,0x7EDD,0xEEF8, +0x7ED6,0xEEC6,0x7ECF,0xEE94,0x7EC8,0xEE62,0x7EC1,0xEE31,0x7EBA,0xEDFF,0x7EB3, +0xEDCD,0x7EAC,0xED9B,0x7EA5,0xED6A,0x7E9D,0xED38,0x7E96,0xED06,0x7E8E,0xECD5, +0x7E87,0xECA3,0x7E7F,0xEC71,0x7E78,0xEC3F,0x7E70,0xEC0E,0x7E68,0xEBDC,0x7E60, +0xEBAB,0x7E58,0xEB79,0x7E50,0xEB47,0x7E48,0xEB16,0x7E3F,0xEAE4,0x7E37,0xEAB3, +0x7E2F,0xEA81,0x7E26,0xEA4F,0x7E1E,0xEA1E,0x7E15,0xE9EC,0x7E0C,0xE9BB,0x7E03, +0xE989,0x7DFB,0xE958,0x7DF2,0xE926,0x7DE9,0xE8F5,0x7DE0,0xE8C4,0x7DD6,0xE892, +0x7DCD,0xE861,0x7DC4,0xE82F,0x7DBA,0xE7FE,0x7DB1,0xE7CD,0x7DA7,0xE79B,0x7D9E, +0xE76A,0x7D94,0xE739,0x7D8A,0xE707,0x7D81,0xE6D6,0x7D77,0xE6A5,0x7D6D,0xE673, +0x7D63,0xE642,0x7D58,0xE611,0x7D4E,0xE5E0,0x7D44,0xE5AF,0x7D3A,0xE57D,0x7D2F, +0xE54C,0x7D25,0xE51B,0x7D1A,0xE4EA,0x7D0F,0xE4B9,0x7D05,0xE488,0x7CFA,0xE457, +0x7CEF,0xE426,0x7CE4,0xE3F4,0x7CD9,0xE3C3,0x7CCE,0xE392,0x7CC2,0xE361,0x7CB7, +0xE330,0x7CAC,0xE2FF,0x7CA0,0xE2CF,0x7C95,0xE29E,0x7C89,0xE26D,0x7C7E,0xE23C, +0x7C72,0xE20B,0x7C66,0xE1DA,0x7C5A,0xE1A9,0x7C4E,0xE178,0x7C42,0xE148,0x7C36, +0xE117,0x7C2A,0xE0E6,0x7C1E,0xE0B5,0x7C11,0xE085,0x7C05,0xE054,0x7BF9,0xE023, +0x7BEC,0xDFF2,0x7BDF,0xDFC2,0x7BD3,0xDF91,0x7BC6,0xDF61,0x7BB9,0xDF30,0x7BAC, +0xDEFF,0x7B9F,0xDECF,0x7B92,0xDE9E,0x7B85,0xDE6E,0x7B78,0xDE3D,0x7B6A,0xDE0D, +0x7B5D,0xDDDC,0x7B50,0xDDAC,0x7B42,0xDD7C,0x7B34,0xDD4B,0x7B27,0xDD1B,0x7B19, +0xDCEA,0x7B0B,0xDCBA,0x7AFD,0xDC8A,0x7AEF,0xDC59,0x7AE1,0xDC29,0x7AD3,0xDBF9, +0x7AC5,0xDBC9,0x7AB7,0xDB99,0x7AA8,0xDB68,0x7A9A,0xDB38,0x7A8C,0xDB08,0x7A7D, +0xDAD8,0x7A6E,0xDAA8,0x7A60,0xDA78,0x7A51,0xDA48,0x7A42,0xDA18,0x7A33,0xD9E8, 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+0xCF04,0x877B,0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276,0xE707,0x8163,0xED38, +0x809E,0xF374,0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E, +0xB8E3,0x5A82,0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000, +0xE707,0x8276,0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE, +0xCF04,0x8276,0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFF69,0x7FFF,0xFED2,0x7FFD,0xFE3C,0x7FFA,0xFDA5,0x7FF7, +0xFD0E,0x7FF4,0xFC77,0x7FEF,0xFBE1,0x7FEA,0xFB4A,0x7FE4,0xFAB3,0x7FDD,0xFA1D, +0x7FD6,0xF986,0x7FCE,0xF8EF,0x7FC5,0xF859,0x7FBC,0xF7C2,0x7FB2,0xF72C,0x7FA7, +0xF695,0x7F9C,0xF5FF,0x7F90,0xF569,0x7F83,0xF4D3,0x7F75,0xF43C,0x7F67,0xF3A6, +0x7F58,0xF310,0x7F49,0xF27A,0x7F38,0xF1E4,0x7F27,0xF14E,0x7F16,0xF0B9,0x7F03, +0xF023,0x7EF0,0xEF8D,0x7EDD,0xEEF8,0x7EC8,0xEE62,0x7EB3,0xEDCD,0x7E9D,0xED38, +0x7E87,0xECA3,0x7E70,0xEC0E,0x7E58,0xEB79,0x7E3F,0xEAE4,0x7E26,0xEA4F,0x7E0C, +0xE9BB,0x7DF2,0xE926,0x7DD6,0xE892,0x7DBA,0xE7FE,0x7D9E,0xE76A,0x7D81,0xE6D6, +0x7D63,0xE642,0x7D44,0xE5AF,0x7D25,0xE51B,0x7D05,0xE488,0x7CE4,0xE3F4,0x7CC2, +0xE361,0x7CA0,0xE2CF,0x7C7E,0xE23C,0x7C5A,0xE1A9,0x7C36,0xE117,0x7C11,0xE085, +0x7BEC,0xDFF2,0x7BC6,0xDF61,0x7B9F,0xDECF,0x7B78,0xDE3D,0x7B50,0xDDAC,0x7B27, +0xDD1B,0x7AFD,0xDC8A,0x7AD3,0xDBF9,0x7AA8,0xDB68,0x7A7D,0xDAD8,0x7A51,0xDA48, +0x7A24,0xD9B8,0x79F7,0xD928,0x79C9,0xD898,0x799A,0xD809,0x796A,0xD77A,0x793A, +0xD6EB,0x790A,0xD65C,0x78D8,0xD5CE,0x78A6,0xD53F,0x7874,0xD4B1,0x7840,0xD424, +0x780C,0xD396,0x77D8,0xD309,0x77A2,0xD27C,0x776C,0xD1EF,0x7736,0xD162,0x76FE, +0xD0D6,0x76C7,0xD04A,0x768E,0xCFBE,0x7655,0xCF33,0x761B,0xCEA7,0x75E1,0xCE1C, +0x75A6,0xCD92,0x756A,0xCD07,0x752D,0xCC7D,0x74F0,0xCBF3,0x74B3,0xCB69,0x7475, +0xCAE0,0x7436,0xCA57,0x73F6,0xC9CE,0x73B6,0xC946,0x7375,0xC8BE,0x7334,0xC836, +0x72F2,0xC7AE,0x72AF,0xC727,0x726C,0xC6A0,0x7228,0xC619,0x71E3,0xC593,0x719E, +0xC50D,0x7158,0xC487,0x7112,0xC402,0x70CB,0xC37D,0x7083,0xC2F8,0x703B,0xC274, +0x6FF2,0xC1F0,0x6FA9,0xC16C,0x6F5F,0xC0E9,0x6F14,0xC066,0x6EC9,0xBFE3,0x6E7D, +0xBF61,0x6E31,0xBEDF,0x6DE4,0xBE5D,0x6D96,0xBDDC,0x6D48,0xBD5B,0x6CF9,0xBCDA, +0x6CAA,0xBC5A,0x6C5A,0xBBDA,0x6C09,0xBB5B,0x6BB8,0xBADC,0x6B66,0xBA5D,0x6B14, +0xB9DF,0x6AC1,0xB961,0x6A6E,0xB8E3,0x6A1A,0xB866,0x69C5,0xB7E9,0x6970,0xB76D, +0x691A,0xB6F1,0x68C4,0xB675,0x686D,0xB5FA,0x6815,0xB57F,0x67BD,0xB505,0x6764, +0xB48B,0x670B,0xB411,0x66B2,0xB398,0x6657,0xB31F,0x65FC,0xB2A7,0x65A1,0xB22F, +0x6545,0xB1B7,0x64E9,0xB140,0x648B,0xB0C9,0x642E,0xB053,0x63D0,0xAFDD,0x6371, +0xAF68,0x6312,0xAEF3,0x62B2,0xAE7F,0x6252,0xAE0B,0x61F1,0xAD97,0x6190,0xAD24, +0x612E,0xACB1,0x60CB,0xAC3F,0x6068,0xABCD,0x6005,0xAB5C,0x5FA1,0xAAEB,0x5F3C, +0xAA7A,0x5ED7,0xAA0A,0x5E72,0xA99B,0x5E0C,0xA92C,0x5DA5,0xA8BD,0x5D3E,0xA84F, +0x5CD7,0xA7E2,0x5C6F,0xA774,0x5C06,0xA708,0x5B9D,0xA69C,0x5B34,0xA630,0x5AC9, +0xA5C5,0x5A5F,0xA55A,0x59F4,0xA4F0,0x5988,0xA486,0x591C,0xA41D,0x58B0,0xA3B4, +0x5843,0xA34C,0x57D5,0xA2E4,0x5767,0xA27D,0x56F9,0xA216,0x568A,0xA1B0,0x561B, +0xA14A,0x55AB,0xA0E5,0x553B,0xA080,0x54CA,0xA01C,0x5459,0x9FB9,0x53E7,0x9F56, +0x5375,0x9EF3,0x5303,0x9E91,0x5290,0x9E2F,0x521C,0x9DCE,0x51A8,0x9D6E,0x5134, +0x9D0E,0x50BF,0x9CAF,0x504A,0x9C50,0x4FD4,0x9BF1,0x4F5E,0x9B94,0x4EE8,0x9B36, +0x4E71,0x9ADA,0x4DF9,0x9A7E,0x4D81,0x9A22,0x4D09,0x99C7,0x4C91,0x996D,0x4C17, +0x9913,0x4B9E,0x98B9,0x4B24,0x9860,0x4AAA,0x9808,0x4A2F,0x97B0,0x49B4,0x9759, +0x4939,0x9703,0x48BD,0x96AD,0x4840,0x9657,0x47C4,0x9603,0x4747,0x95AE,0x46C9, +0x955B,0x464B,0x9508,0x45CD,0x94B5,0x454F,0x9463,0x44D0,0x9412,0x4450,0x93C1, +0x43D1,0x9371,0x4351,0x9321,0x42D0,0x92D2,0x424F,0x9284,0x41CE,0x9236,0x414D, +0x91E9,0x40CB,0x919C,0x4048,0x9150,0x3FC6,0x9105,0x3F43,0x90BA,0x3EC0,0x9070, +0x3E3C,0x9026,0x3DB8,0x8FDD,0x3D34,0x8F95,0x3CAF,0x8F4D,0x3C2A,0x8F06,0x3BA5, +0x8EBF,0x3B20,0x8E79,0x3A9A,0x8E34,0x3A13,0x8DEF,0x398D,0x8DAB,0x3906,0x8D67, +0x387F,0x8D24,0x37F7,0x8CE2,0x3770,0x8CA1,0x36E8,0x8C60,0x365F,0x8C1F,0x35D7, +0x8BDF,0x354E,0x8BA0,0x34C4,0x8B62,0x343B,0x8B24,0x33B1,0x8AE7,0x3327,0x8AAA, +0x329D,0x8A6E,0x3212,0x8A33,0x3187,0x89F8,0x30FC,0x89BE,0x3070,0x8985,0x2FE5, +0x894C,0x2F59,0x8914,0x2ECC,0x88DD,0x2E40,0x88A6,0x2DB3,0x8870,0x2D26,0x883A, +0x2C99,0x8805,0x2C0C,0x87D1,0x2B7E,0x879D,0x2AF0,0x876B,0x2A62,0x8738,0x29D3, +0x8707,0x2945,0x86D6,0x28B6,0x86A5,0x2827,0x8676,0x2797,0x8647,0x2708,0x8619, +0x2678,0x85EB,0x25E8,0x85BE,0x2558,0x8592,0x24C8,0x8566,0x2437,0x853B,0x23A7, +0x8511,0x2316,0x84E7,0x2284,0x84BE,0x21F3,0x8496,0x2162,0x846E,0x20D0,0x8447, +0x203E,0x8421,0x1FAC,0x83FB,0x1F1A,0x83D6,0x1E88,0x83B2,0x1DF5,0x838E,0x1D62, +0x836B,0x1CD0,0x8349,0x1C3D,0x8327,0x1BA9,0x8306,0x1B16,0x82E6,0x1A83,0x82C6, +0x19EF,0x82A8,0x195B,0x8289,0x18C7,0x826C,0x1833,0x824F,0x179F,0x8233,0x170B, +0x8217,0x1677,0x81FD,0x15E2,0x81E2,0x154D,0x81C9,0x14B9,0x81B0,0x1424,0x8198, +0x138F,0x8181,0x12FA,0x816A,0x1265,0x8154,0x11CF,0x813F,0x113A,0x812A,0x10A4, +0x8116,0x100F,0x8103,0x0F79,0x80F0,0x0EE4,0x80DE,0x0E4E,0x80CD,0x0DB8,0x80BD, +0x0D22,0x80AD,0x0C8C,0x809E,0x0BF6,0x808F,0x0B60,0x8082,0x0AC9,0x8075,0x0A33, +0x8068,0x099D,0x805D,0x0906,0x8052,0x0870,0x8047,0x07D9,0x803E,0x0743,0x8035, +0x06AC,0x802D,0x0616,0x8025,0x057F,0x801E,0x04E8,0x8018,0x0452,0x8013,0x03BB, +0x800E,0x0324,0x800A,0x028D,0x8007,0x01F7,0x8004,0x0160,0x8002,0x00C9,0x8001, +0x0032,0x8000,0xFF9B,0x8000,0xFF05,0x8001,0xFE6E,0x8002,0xFDD7,0x8005,0xFD40, +0x8008,0xFCAA,0x800B,0xFC13,0x800F,0xFB7C,0x8014,0xFAE5,0x801A,0xFA4F,0x8020, +0xF9B8,0x8027,0xF922,0x802F,0xF88B,0x8038,0xF7F4,0x8041,0xF75E,0x804B,0xF6C8, +0x8055,0xF631,0x8060,0xF59B,0x806C,0xF505,0x8079,0xF46E,0x8086,0xF3D8,0x8094, +0xF342,0x80A3,0xF2AC,0x80B2,0xF216,0x80C2,0xF180,0x80D3,0xF0EB,0x80E4,0xF055, +0x80F6,0xEFBF,0x8109,0xEF2A,0x811D,0xEE94,0x8131,0xEDFF,0x8146,0xED6A,0x815B, +0xECD5,0x8172,0xEC3F,0x8188,0xEBAB,0x81A0,0xEB16,0x81B8,0xEA81,0x81D1,0xE9EC, +0x81EB,0xE958,0x8205,0xE8C4,0x8220,0xE82F,0x823C,0xE79B,0x8259,0xE707,0x8276, +0xE673,0x8293,0xE5E0,0x82B2,0xE54C,0x82D1,0xE4B9,0x82F1,0xE426,0x8311,0xE392, +0x8332,0xE2FF,0x8354,0xE26D,0x8377,0xE1DA,0x839A,0xE148,0x83BE,0xE0B5,0x83E2, +0xE023,0x8407,0xDF91,0x842D,0xDEFF,0x8454,0xDE6E,0x847B,0xDDDC,0x84A3,0xDD4B, +0x84CC,0xDCBA,0x84F5,0xDC29,0x851F,0xDB99,0x8549,0xDB08,0x8574,0xDA78,0x85A0, +0xD9E8,0x85CD,0xD958,0x85FA,0xD8C8,0x8628,0xD839,0x8656,0xD7AA,0x8686,0xD71B, +0x86B6,0xD68C,0x86E6,0xD5FD,0x8717,0xD56F,0x8749,0xD4E1,0x877B,0xD453,0x87AF, +0xD3C5,0x87E2,0xD338,0x8817,0xD2AB,0x884C,0xD21E,0x8882,0xD191,0x88B8,0xD105, +0x88EF,0xD079,0x8927,0xCFED,0x895F,0xCF61,0x8998,0xCED6,0x89D2,0xCE4B,0x8A0C, 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+0x8EBF,0x3BA5,0x8FDD,0x3DB8,0x9105,0x3FC6,0x9236,0x41CE,0x9371,0x43D1,0x94B5, +0x45CD,0x9603,0x47C4,0x9759,0x49B4,0x98B9,0x4B9E,0x9A22,0x4D81,0x9B94,0x4F5E, +0x9D0E,0x5134,0x9E91,0x5303,0xA01C,0x54CA,0xA1B0,0x568A,0xA34C,0x5843,0xA4F0, +0x59F4,0xA69C,0x5B9D,0xA84F,0x5D3E,0xAA0A,0x5ED7,0xABCD,0x6068,0xAD97,0x61F1, +0xAF68,0x6371,0xB140,0x64E9,0xB31F,0x6657,0xB505,0x67BD,0xB6F1,0x691A,0xB8E3, +0x6A6E,0xBADC,0x6BB8,0xBCDA,0x6CF9,0xBEDF,0x6E31,0xC0E9,0x6F5F,0xC2F8,0x7083, +0xC50D,0x719E,0xC727,0x72AF,0xC946,0x73B6,0xCB69,0x74B3,0xCD92,0x75A6,0xCFBE, +0x768E,0xD1EF,0x776C,0xD424,0x7840,0xD65C,0x790A,0xD898,0x79C9,0xDAD8,0x7A7D, +0xDD1B,0x7B27,0xDF61,0x7BC6,0xE1A9,0x7C5A,0xE3F4,0x7CE4,0xE642,0x7D63,0xE892, +0x7DD6,0xEAE4,0x7E3F,0xED38,0x7E9D,0xEF8D,0x7EF0,0xF1E4,0x7F38,0xF43C,0x7F75, +0xF695,0x7FA7,0xF8EF,0x7FCE,0xFB4A,0x7FEA,0xFDA5,0x7FFA,0x7FFF,0x0000,0x7FA7, +0xF695,0x7E9D,0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C,0xD1EF,0x73B6,0xC946, +0x6F5F,0xC0E9,0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A,0x5843,0xA34C,0x5134, +0x9D0E,0x49B4,0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC,0x89BE,0x2827,0x8676, +0x1F1A,0x83D6,0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A,0xF9B8,0x8027,0xF055, +0x80F6,0xE707,0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21,0x8AFB,0xC3A9,0x8F1D, +0xBB85,0x93DC,0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E,0x9F14,0xAC65,0x9930, +0xB3C0,0x93DC,0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B,0xD4E1,0x84A3,0xDDDC, +0x8276,0xE707,0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324,0x809E,0x0C8C,0x81E2, +0x15E2,0x83D6,0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB,0x398D,0x9236,0x41CE, +0x9759,0x49B4,0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7,0xB140,0x64E9,0xB8E3, +0x6A6E,0xC0E9,0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8,0x7A7D,0xE3F4,0x7CE4, +0xED38,0x7E9D,0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134, +0x9D0E,0x30FC,0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E, +0x8F1D,0xC3A9,0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3, +0x6A6E,0xDAD8,0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEI) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c new file mode 100644 index 0000000..56e3acd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c @@ -0,0 +1,5580 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math_types_f16.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2]={ +0,0,}; + +float16_t rearranged_twiddle_stride1_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3]={ +0,32,0,}; + +float16_t rearranged_twiddle_stride1_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4]={ +0,128,160,0,}; + +float16_t rearranged_twiddle_stride1_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5]={ +0,512,640,672,0,}; + +float16_t rearranged_twiddle_stride1_1024_f16[680]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, 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+uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +float16_t rearranged_twiddle_stride1_4096_f16[2728]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0015335083008f, +(float16_t)1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)1.0000000000000f,(float16_t)0.0046005249023f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0076713562012f, +(float16_t)1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)1.0000000000000f,(float16_t)0.0107345581055f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0138015747070f, +(float16_t)1.0000000000000f,(float16_t)0.0153427124023f, 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+(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#endif /* if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c new file mode 100644 index 0000000..9b10a4a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c @@ -0,0 +1,167 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f16.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + static const float16_t cmplx_conj_sign[8] = { 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f }; + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f16x8_t vecSrc; + f16x8_t vecSign; + + /* + * load sign vector + */ + vecSign = *(f16x8_t *) cmplx_conj_sign; + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + vst1q(pDst,vmulq(vecSrc, vecSign)); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt--; + } + + /* Tail */ + blkCnt = (blockSize & 0x7) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_conj group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 0000000..89cbe5b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,217 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f32.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + static const float32_t cmplx_conj_sign[4] = { 1.0f, -1.0f, 1.0f, -1.0f }; + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f32x4_t vecSrc; + f32x4_t vecSign; + + /* + * load sign vector + */ + vecSign = *(f32x4_t *) cmplx_conj_sign; + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + vst1q(pDst,vmulq(vecSrc, vecSign)); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt--; + } + + /* Tail */ + blkCnt = (blockSize & 0x3) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4_t zero; + float32x4x2_t vec; + + zero = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0]+jC[1] = A[0]+(-1)*jA[1] */ + /* Calculate Complex Conjugate and then store the results in the destination buffer. */ + vec = vld2q_f32(pSrc); + vec.val[1] = vsubq_f32(zero,vec.val[1]); + vst2q_f32(pDst,vec); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined (ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_conj group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c new file mode 100644 index 0000000..b13e16d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c @@ -0,0 +1,211 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q15.c + * Description: Q15 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q15 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31_t in1; + + q15x8x2_t vecSrc; + q15x8_t zero; + + zero = vdupq_n_s16(0); + + /* Compute 8 real samples at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vecSrc.val[1] = vqsubq(zero, vecSrc.val[1]); + vst2q(pDst,vecSrc); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSize & 0xF) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = __SSAT(-in1, 16); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in1; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in2, in3, in4; /* Temporary input variables */ +#endif + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + +#if defined (ARM_MATH_DSP) + in1 = read_q15x2_ia (&pSrc); + in2 = read_q15x2_ia (&pSrc); + in3 = read_q15x2_ia (&pSrc); + in4 = read_q15x2_ia (&pSrc); + +#ifndef ARM_MATH_BIG_ENDIAN + in1 = __QASX(0, in1); + in2 = __QASX(0, in2); + in3 = __QASX(0, in3); + in4 = __QASX(0, in4); +#else + in1 = __QSAX(0, in1); + in2 = __QSAX(0, in2); + in3 = __QSAX(0, in3); + in4 = __QSAX(0, in4); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16); + in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16); + in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16); + in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16); + + write_q15x2_ia (&pDst, in1); + write_q15x2_ia (&pDst, in2); + write_q15x2_ia (&pDst, in3); + write_q15x2_ia (&pDst, in4); +#else + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __SSAT(-in1, 16); +#else + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_conj group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c new file mode 100644 index 0000000..879d679 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c @@ -0,0 +1,197 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q31.c + * Description: Q31 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q31 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31x4x2_t vecSrc; + q31_t in; /* Temporary input variable */ + q31x4_t zero; + + zero = vdupq_n_s32(0); + + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vld2q(pSrc); + vecSrc.val[1] = vqsubq(zero, vecSrc.val[1]); + vst2q(pDst,vecSrc); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSize & 0x7) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; + *pDst++ = __QSUB(0, in); + + /* Decrement loop counter */ + blkCnt--; + } + + +} +#else + +void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_conj group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c new file mode 100644 index 0000000..6066f61 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c @@ -0,0 +1,266 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_f16.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupCmplxMath + */ + + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult) +{ + int32_t blkCnt; + float16_t real_sum, imag_sum; + f16x8_t vecSrcA, vecSrcB; + f16x8_t vec_acc = vdupq_n_f16(0.0f16); + f16x8_t vecSrcC, vecSrcD; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q( pSrcA); + vecSrcB = vld1q( pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + blkCnt -= 8; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f16(0.0f16); + + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + } + + /* Sum the partial parts */ + mve_cmplx_sum_intra_r_i_f16(vec_acc, real_sum, imag_sum); + + /* + * Store the real and imaginary results in the destination buffers + */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +#else +void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + _Float16 a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_dot_prod group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c new file mode 100644 index 0000000..8282d6f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c @@ -0,0 +1,344 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_f32.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + + 
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ + int32_t blkCnt; + float32_t real_sum, imag_sum; + f32x4_t vecSrcA, vecSrcB; + f32x4_t vec_acc = vdupq_n_f32(0.0f); + f32x4_t vecSrcC, vecSrcD; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + pSrcA += 4; + pSrcB += 4; + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + blkCnt -= 4; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f32(0.0f); + + do { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + } + + real_sum = vgetq_lane(vec_acc, 0) + vgetq_lane(vec_acc, 2); + imag_sum = vgetq_lane(vec_acc, 1) + vgetq_lane(vec_acc, 3); + + /* + * Store the real and imaginary results in the destination buffers + */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +#else +void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + float32_t a0,b0,c0,d0; + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t vec1,vec2,vec3,vec4; + float32x4_t accR,accI; + float32x2_t accum = vdup_n_f32(0); + + accR = vdupq_n_f32(0.0f); + accI = vdupq_n_f32(0.0f); + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3U; + + while (blkCnt > 0U) + { + /* C = (A[0]+jA[1])*(B[0]+jB[1]) + ... */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + vec1 = vld2q_f32(pSrcA); + vec2 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec1.val[0],vec2.val[0]); + accR = vmlsq_f32(accR,vec1.val[1],vec2.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec1.val[1],vec2.val[0]); + accI = vmlaq_f32(accI,vec1.val[0],vec2.val[1]); + + vec3 = vld2q_f32(pSrcA); + vec4 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec3.val[0],vec4.val[0]); + accR = vmlsq_f32(accR,vec3.val[1],vec4.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec3.val[1],vec4.val[0]); + accI = vmlaq_f32(accI,vec3.val[0],vec4.val[1]); + + /* Decrement the loop counter */ + blkCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR), vget_high_f32(accR)); + real_sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI), vget_high_f32(accI)); + imag_sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* Tail */ + blkCnt = numSamples & 0x7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_dot_prod group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c new file mode 100644 index 0000000..2c93864 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c @@ -0,0 +1,260 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q15.c + * Description: Processing function for the Q15 Complex Dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q15 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned her + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. + These are accumulated in a 64-bit accumulator with 34.30 precision. + As a final step, the accumulators are converted to 8.24 format. + The return results realResult and imagResult are in 8.24 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + int32_t blkCnt; + q63_t accReal = 0LL; + q63_t accImag = 0LL; + q15x8_t vecSrcA, vecSrcB; + q15x8_t vecSrcC, vecSrcD; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + + accReal = vmlsldavaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + accImag = vmlaldavaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + accReal = vmlsldavaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + accImag = vmlaldavaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + accReal = vmlsldavaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + accImag = vmlaldavaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + accReal = vmlsldavaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + + accImag = vmlaldavaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + do { + mve_pred16_t p = vctp16q(blkCnt); + + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + accReal = vmlsldavaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vmlaldavaxq_p(accImag, vecSrcA, vecSrcB, p); + + blkCnt -= 8; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + accReal = vmlsldavaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vmlaldavaxq_p(accImag, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + } + *realResult = asrl(accReal, (14 - 8)); + *imagResult = asrl(accImag, (14 - 8)); +} +#else +void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q15_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 8.24 format */ + /* Convert real data in 34.30 to 8.24 by 6 right shifts */ + *realResult = (q31_t) (real_sum >> 6); + /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */ + *imagResult = (q31_t) (imag_sum >> 6); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_dot_prod group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c new file mode 100644 index 0000000..bd5e894 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c @@ -0,0 +1,263 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q31.c + * Description: Q31 complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q31 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. + The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. + Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. + The return results realResult and imagResult are in 16.48 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ + int32_t blkCnt; + q63_t accReal = 0LL; + q63_t accImag = 0LL; + q31x4_t vecSrcA, vecSrcB; + q31x4_t vecSrcC, vecSrcD; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + + accReal = vrmlsldavhaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + accImag = vrmlaldavhaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + accReal = vrmlsldavhaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + accImag = vrmlaldavhaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + accReal = vrmlsldavhaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + accImag = vrmlaldavhaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + accReal = vrmlsldavhaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + + accImag = vrmlaldavhaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + do { + mve_pred16_t p = vctp32q(blkCnt); + + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + accReal = vrmlsldavhaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vrmlaldavhaxq_p(accImag, vecSrcA, vecSrcB, p); + + blkCnt -= 4; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + accReal = vrmlsldavhaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vrmlaldavhaxq_p(accImag, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + } + *realResult = asrl(accReal, (14 - 8)); + *imagResult = asrl(accImag, (14 - 8)); + +} + +#else +void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q31_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 16.48 format */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_dot_prod group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c new file mode 100644 index 0000000..a4c859d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c @@ -0,0 +1,223 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f16.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + + + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f16x8x2_t vecSrc; + f16x8_t sum; + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + q15x8_t newtonStartVec; + f16x8_t sumHalf, invSqrt; + + vecSrc = vld2q(pSrc); + pSrc += 16; + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s16(INVSQRT_MAGIC_F16) - vshrq((q15x8_t) sum, 1); + sumHalf = sum * 0.5f; + /* + * compute 3 x iterations + * + * The more iterations, the more accuracy. + * If you need to trade a bit of accuracy for more performance, + * you can comment out the 3rd use of the macro. + */ + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, (f16x8_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, (float16_t)0.0f, vcmpltq(invSqrt, (float16_t)0.0f)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vstrhq_f16(pDst, sum); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + q15x8_t newtonStartVec; + f16x8_t sumHalf, invSqrt; + + vecSrc = vld2q((float16_t const *)pSrc); + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s16(INVSQRT_MAGIC_F16) - vshrq((q15x8_t) sum, 1); + sumHalf = vmulq(sum, (float16_t)0.5); + /* + * compute 2 x iterations + */ + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, (f16x8_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, (float16_t)0.0, vcmpltq(invSqrt, (float16_t)0.0)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vstrhq_p_f16(pDst, sum, p0); + } +} + +#else +void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + _Float16 real, imag; /* Temporary variables to hold input values */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c new file mode 100644 index 0000000..b2c9230 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c @@ -0,0 +1,277 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f32.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" +#endif + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f32x4x2_t vecSrc; + f32x4_t sum; + float32_t real, imag; /* Temporary variables to hold input values */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + q31x4_t newtonStartVec; + f32x4_t sumHalf, invSqrt; + + vecSrc = vld2q(pSrc); + pSrc += 8; + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s32(INVSQRT_MAGIC_F32) - vshrq((q31x4_t) sum, 1); + sumHalf = sum * 0.5f; + /* + * compute 3 x iterations + * + * The more iterations, the more accuracy. + * If you need to trade a bit of accuracy for more performance, + * you can comment out the 3rd use of the macro. + */ + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, (f32x4_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, invSqrt); + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, 0.0f, vcmpltq(invSqrt, 0.0f)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vst1q(pDst, sum); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + float32_t real, imag; /* Temporary variables to hold input values */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqA)); + pDst += 4; + + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqB)); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c new file mode 100644 index 0000000..2d651ac --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c @@ -0,0 +1,82 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f64.c + * Description: Floating-point complex magnitude + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + + + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ +void arm_cmplx_mag_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + float64_t real, imag; /* Temporary variables to hold input values */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = sqrt((real * real) + (imag * imag)); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c new file mode 100644 index 0000000..6a78a7e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c @@ -0,0 +1,227 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_fast_q15.c + * Description: Q15 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + Fast functions are less accurate. This function will tend to clamp to 0 + the too small values. So sqrt(x*x) = x will not always be true. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q15x8x2_t vecSrc; + q15x8_t sum; + q31_t in; + q31_t acc0; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + pSrc += 16; + sum = vqaddq(vmulhq(vecSrc.val[0], vecSrc.val[0]), + vmulhq(vecSrc.val[1], vecSrc.val[1])); + + sum = vshrq(sum, 1); + + sum = FAST_VSQRT_Q15(sum); + + vst1q(pDst, sum); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c new file mode 100644 index 0000000..9c06477 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c @@ -0,0 +1,272 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q15.c + * Description: Q15 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + */ + +/* Sqrt q31 is used otherwise accuracy is not good enough + for small values and for some applications it is + an issue. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q15x8x2_t vecSrc; + q31x4_t prod0; + q31x4_t prod1; + + q31_t in; + q31_t acc0; + q31x4_t acc0V; + q31x4_t acc1V; + + q31_t res; + q15x8_t resV; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + pSrc += 16; + + acc0V = vdupq_n_s32(0); + acc1V = vdupq_n_s32(0); + + prod0 = vmullbq_int_s16(vecSrc.val[0], vecSrc.val[0]); + acc0V = vqaddq_s32(acc0V,prod0); + + prod0 = vmullbq_int_s16(vecSrc.val[1], vecSrc.val[1]); + acc0V = vqaddq_s32(acc0V,prod0); + + + prod1 = vmulltq_int_s16(vecSrc.val[0], vecSrc.val[0]); + acc1V = vqaddq_s32(acc1V,prod1); + + prod1 = vmulltq_int_s16(vecSrc.val[1], vecSrc.val[1]); + acc1V = vqaddq_s32(acc1V,prod1); + + + + acc0V = vshrq(acc0V, 1); + acc1V = vshrq(acc1V, 1); + + acc0V = FAST_VSQRT_Q31(acc0V); + acc1V = FAST_VSQRT_Q31(acc1V); + + resV = vdupq_n_s16(0); + resV = vqshrnbq_n_s32(resV,acc0V,16); + resV = vqshrntq_n_s32(resV,acc1V,16); + + vst1q(pDst, resV); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + q31_t res; /* temporary result */ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c new file mode 100644 index 0000000..0041620 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c @@ -0,0 +1,205 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q31.c + * Description: Q31 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q31 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + + q31x4x2_t vecSrc; + q31x4_t sum; + + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + + sum = vqaddq(vmulhq(vecSrc.val[0], vecSrc.val[0]), + vmulhq(vecSrc.val[1], vecSrc.val[1])); + + sum = vshrq(sum, 1); + + /* + + This function is using a table. There are compilations flags to avoid + including this table (and in this case, arm_cmplx_maq_q31 must not + be built and linked.) + + */ + sum = FAST_VSQRT_Q31(sum); + + vst1q(pDst, sum); + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + pSrc += 8; + pDst += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c new file mode 100644 index 0000000..5fd3af1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c @@ -0,0 +1,155 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f16.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + f16x8x2_t vecSrc; + f16x8_t sum; + + /* Compute 4 complex samples at a time */ + while (blockSize > 0) + { + mve_pred16_t p = vctp16q(blockSize); + vecSrc = vld2q(pSrc); + sum = vmulq_m(vuninitializedq_f16(),vecSrc.val[0], vecSrc.val[0],p); + sum = vfmaq_m(sum, vecSrc.val[1], vecSrc.val[1],p); + vstrhq_p_f16(pDst, sum,p); + + pSrc += 16; + pDst += 8; + + /* + * Decrement the blockSize loop counter + */ + blockSize-= 8; + } + +} + +#else +void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real, imag; /* Temporary input variables */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag_squared group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c new file mode 100644 index 0000000..eaadf1c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c @@ -0,0 +1,239 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f32.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f32x4x2_t vecSrc; + f32x4_t sum; + float32_t real, imag; /* Temporary input variables */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + vst1q(pDst, sum); + + pSrc += 8; + pDst += 4; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real, imag; /* Temporary input variables */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, vMagSqA); + pDst += 4; + + vst1q_f32(pDst, vMagSqB); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag_squared group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c new file mode 100644 index 0000000..d2a2b36 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c @@ -0,0 +1,80 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f64.c + * Description: Floating-point complex magnitude squared + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ +void arm_cmplx_mag_squared_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t real, imag; /* Temporary input variables */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag_squared group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c new file mode 100644 index 0000000..0e2b2ec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c @@ -0,0 +1,225 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q15.c + * Description: Q15 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q15 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q31_t in; + q31_t acc0; /* Accumulators */ + q15x8x2_t vecSrc; + q15x8_t vReal, vImag; + q15x8_t vMagSq; + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vReal = vmulhq(vecSrc.val[0], vecSrc.val[0]); + vImag = vmulhq(vecSrc.val[1], vecSrc.val[1]); + vMagSq = vqaddq(vReal, vImag); + vMagSq = vshrq(vMagSq, 1); + + vst1q(pDst, vMagSq); + + pSrc += 16; + pDst += 8; + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + blkCnt --; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag_squared group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c new file mode 100644 index 0000000..b533a60 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c @@ -0,0 +1,191 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q31.c + * Description: Q31 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q31 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q31x4x2_t vecSrc; + q31x4_t vReal, vImag; + q31x4_t vMagSq; + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vReal = vmulhq(vecSrc.val[0], vecSrc.val[0]); + vImag = vmulhq(vecSrc.val[1], vecSrc.val[1]); + vMagSq = vqaddq(vReal, vImag); + vMagSq = vshrq(vMagSq, 1); + + vst1q(pDst, vMagSq); + + pSrc += 8; + pDst += 4; + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + blkCnt --; + } + + /* Tail */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + /* store the result in 3.29 format in the destination buffer. */ + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag_squared group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c new file mode 100644 index 0000000..75fefa3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c @@ -0,0 +1,255 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f16.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + + + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + f16x8_t vecSrcA, vecSrcB; + f16x8_t vecSrcC, vecSrcD; + f16x8_t vec_acc; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + vst1q(pDst, vec_acc); + pDst += 8; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + vst1q(pDst, vec_acc); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + vst1q(pDst, vec_acc); + pDst += 8; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vst1q(pDst, vec_acc); + pDst += 8; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + vec_acc = vcmulq_m(vuninitializedq_f16(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + vstrhq_p_f16(pDst, vec_acc, p); + pDst += 8; + + blkCnt -= 8; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + + vec_acc = vcmulq_m(vuninitializedq_f16(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + vstrhq_p_f16(pDst, vec_acc, p); + pDst += 8; + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + } + +} + + +#else +void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByCmplxMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c new file mode 100644 index 0000000..d6ec828 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c @@ -0,0 +1,309 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f32.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + f32x4_t vecSrcA, vecSrcB; + f32x4_t vecSrcC, vecSrcD; + f32x4_t vec_acc; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + vst1q(pDst, vec_acc); + pDst += 4; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + vst1q(pDst, vec_acc); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + vst1q(pDst, vec_acc); + pDst += 4; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vst1q(pDst, vec_acc); + pDst += 4; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + vec_acc = vcmulq_m(vuninitializedq_f32(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + vstrwq_p_f32(pDst, vec_acc, p); + pDst += 4; + + blkCnt -= 4; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f32(0.0f); + + do { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + + vec_acc = vcmulq_m(vuninitializedq_f32(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + vstrwq_p_f32(pDst, vec_acc, p); + pDst += 4; + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + } + +} + +#else +void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t va, vb; + float32x4x2_t outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + va = vld2q_f32(pSrcA); // load & separate real/imag pSrcA (de-interleave 2) + vb = vld2q_f32(pSrcB); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + outCplx.val[0] = vmulq_f32(va.val[0], vb.val[0]); + outCplx.val[0] = vmlsq_f32(outCplx.val[0], va.val[1], vb.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + outCplx.val[1] = vmulq_f32(va.val[0], vb.val[1]); + outCplx.val[1] = vmlaq_f32(outCplx.val[1], va.val[1], vb.val[0]); + + vst2q_f32(pDst, outCplx); + + /* Increment pointer */ + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByCmplxMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c new file mode 100644 index 0000000..603de64 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c @@ -0,0 +1,87 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f64.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void arm_cmplx_mult_cmplx_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByCmplxMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c new file mode 100644 index 0000000..0790341 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c @@ -0,0 +1,262 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q15.c + * Description: Q15 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q15 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + q15x8_t vecSrcA, vecSrcB; + q15x8_t vecSrcC, vecSrcD; + q15x8_t vecDst; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) + { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) + { + + /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcC, vecSrcD); + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + do + { + mve_pred16_t p = vctp16q(blkCnt); + + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s16(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s16(), vecDst, 2, p); + vstrhq_p_s16(pDst, vecDst, p); + pDst += 8; + + blkCnt -= 8; + } + while ((int32_t) blkCnt > 0); + } + else + { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s16(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s16(), vecDst, 2, p); + vstrhq_p_s16(pDst, vecDst, p); + + pDst += 8; + pSrcA += 8; + pSrcB += 8; + + blkCnt -= 8; + } + } +} +#else +void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByCmplxMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c new file mode 100644 index 0000000..cbfc505 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c @@ -0,0 +1,257 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q31.c + * Description: Q31 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q31 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + q31x4_t vecSrcA, vecSrcB; + q31x4_t vecSrcC, vecSrcD; + q31x4_t vecDst; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + + /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcC, vecSrcD); + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + do { + mve_pred16_t p = vctp32q(blkCnt); + + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s32(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s32(), vecDst, 2, p); + vstrwq_p_s32(pDst, vecDst, p); + pDst += 4; + + blkCnt -= 4; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s32(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s32(), vecDst, 2, p); + vstrwq_p_s32(pDst, vecDst, p); + + pDst += 4; + pSrcA += 4; + pSrcB += 4; + + blkCnt -= 4; + } + } +} +#else +void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByCmplxMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c new file mode 100644 index 0000000..740639e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c @@ -0,0 +1,176 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_f16.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint16_t stride_cmplx_x_real_16[8] = { + 0, 0, 1, 1, 2, 2, 3, 3 + }; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f16x8_t rVec; + f16x8_t cmplxVec; + f16x8_t dstVec; + uint16x8_t strideVec; + + + /* stride vector for pairs of real generation */ + strideVec = vld1q(stride_cmplx_x_real_16); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 3; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_f16(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 4; + pSrcCmplx += 8; + pCmplxDst += 8; + blkCnt--; + } + + blkCnt = blockSizeC & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_f16(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vstrhq_p_f16(pCmplxDst, dstVec, p0); + } +} + +#else +void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + in = *pSrcReal++; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + in = *pSrcReal++; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + in = *pSrcReal++; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByRealMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c new file mode 100644 index 0000000..af346be --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c @@ -0,0 +1,228 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_f32.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint32_t stride_cmplx_x_real_32[4] = { 0, 0, 1, 1 }; + + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f32x4_t rVec; + f32x4_t cmplxVec; + f32x4_t dstVec; + uint32x4_t strideVec; + float32_t in; + + + /* stride vector for pairs of real generation */ + strideVec = vld1q(stride_cmplx_x_real_32); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 2; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrwq_gather_shifted_offset_f32(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 2; + pSrcCmplx += 4; + pCmplxDst += 4; + blkCnt--; + } + + blkCnt = (blockSizeC & 3) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t in; /* Temporary variable */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4_t r; + float32x4x2_t ab,outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + ab = vld2q_f32(pSrcCmplx); // load & separate real/imag pSrcA (de-interleave 2) + r = vld1q_f32(pSrcReal); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcCmplx += 8; + pSrcReal += 4; + + outCplx.val[0] = vmulq_f32(ab.val[0], r); + outCplx.val[1] = vmulq_f32(ab.val[1], r); + + vst2q_f32(pCmplxDst, outCplx); + pCmplxDst += 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++* in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByRealMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c new file mode 100644 index 0000000..c2aab63 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c @@ -0,0 +1,242 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q15.c + * Description: Q15 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q15 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint16_t stride_cmplx_x_real_16[8] = { + 0, 0, 1, 1, 2, 2, 3, 3 + }; + q15x8_t rVec; + q15x8_t cmplxVec; + q15x8_t dstVec; + uint16x8_t strideVec; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q15_t in; + + /* + * stride vector for pairs of real generation + */ + strideVec = vld1q(stride_cmplx_x_real_16); + + blkCnt = blockSizeC >> 3; + + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_s16(pSrcReal, strideVec); + dstVec = vqdmulhq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 4; + pSrcCmplx += 8; + pCmplxDst += 8; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSizeC & 7) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; /* Temporary variables to hold input data */ + q31_t inB1; /* Temporary variables to hold input data */ + q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + +#if defined (ARM_MATH_DSP) + /* read 2 complex numbers both real and imaginary from complex input buffer */ + inA1 = read_q15x2_ia (&pSrcCmplx); + inA2 = read_q15x2_ia (&pSrcCmplx); + /* read 2 real values at a time from real input buffer */ + inB1 = read_q15x2_ia (&pSrcReal); + + /* multiply complex number with real numbers */ +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* saturate the result */ + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + /* pack real and imaginary outputs and store them to destination */ + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); + + inA1 = read_q15x2_ia (&pSrcCmplx); + inA2 = read_q15x2_ia (&pSrcCmplx); + inB1 = read_q15x2_ia (&pSrcReal); + +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); +#else + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByRealMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c new file mode 100644 index 0000000..700468d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c @@ -0,0 +1,208 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q31.c + * Description: Q31 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q31 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ + + static const uint32_t stride_cmplx_x_real_32[4] = { + 0, 0, 1, 1 + }; + q31x4_t rVec; + q31x4_t cmplxVec; + q31x4_t dstVec; + uint32x4_t strideVec; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31_t in; + + /* + * stride vector for pairs of real generation + */ + strideVec = vld1q(stride_cmplx_x_real_32); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 2; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrwq_gather_shifted_offset_s32(pSrcReal, strideVec); + dstVec = vqdmulhq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 2; + pSrcCmplx += 4; + pCmplxDst += 4; + blkCnt --; + } + + blkCnt = (blockSizeC & 3) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByRealMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c new file mode 100644 index 0000000..976e91f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_f32.c + * Description: Floating-point PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the floating-point PID Control. + @param[in,out] S points to an instance of the PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag) +{ + /* Derived coefficient A0 */ + S->A0 = S->Kp + S->Ki + S->Kd; + + /* Derived coefficient A1 */ + S->A1 = (-S->Kp) - ((float32_t) 2.0f * S->Kd); + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); + } + +} + +/** + @} end of PID group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c new file mode 100644 index 0000000..79f5f0d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c @@ -0,0 +1,99 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q15.c + * Description: Q15 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd); + + /* Derived coefficients and pack into A1 */ + +#ifndef ARM_MATH_BIG_ENDIAN + S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16); +#else + S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16); +#endif + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = S->Kp + S->Ki + S->Kd; + S->A0 = (q15_t) __SSAT(temp, 16); + + /* Derived coefficients and pack into A1 */ + temp = -(S->Kd + S->Kd + S->Kp); + S->A1 = (q15_t) __SSAT(temp, 16); + S->A2 = S->Kd; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); + } + +} + +/** + @} end of PID group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c new file mode 100644 index 0000000..df5415c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q31.c + * Description: Q31 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd); + + /* Derived coefficient A1 */ + S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp); + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki); + S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd); + + /* Derived coefficient A1 */ + temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd); + S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); + } + +} + +/** + @} end of PID group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c new file mode 100644 index 0000000..b0e6abb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c @@ -0,0 +1,58 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_f32.c + * Description: Floating-point PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the floating-point PID Control. + @param[in,out] S points to an instance of the floating-point PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_f32( + arm_pid_instance_f32 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); +} + +/** + @} end of PID group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c new file mode 100644 index 0000000..c42f45a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c @@ -0,0 +1,58 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q15.c + * Description: Q15 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q15( + arm_pid_instance_q15 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); +} + +/** + @} end of PID group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c new file mode 100644 index 0000000..472a2c1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c @@ -0,0 +1,58 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q31.c + * Description: Q31 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); +} + +/** + @} end of PID group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c new file mode 100644 index 0000000..4c85db6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c @@ -0,0 +1,118 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_f32.c + * Description: Sine and Cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Floating-point sin_cos function. + @param[in] theta input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + */ + +void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal) +{ + float32_t fract, in; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + float32_t f1, f2, d1, d2; /* Two nearest output values */ + float32_t Dn, Df; + float32_t temp, findex; + + /* input x is in degrees */ + /* Scale input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */ + in = theta * 0.00277777777778f; + + if (in < 0.0f) + { + in = -in; + } + + in = in - (int32_t)in; + + /* Calculate the nearest index */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + indexS = ((uint16_t)findex) & 0x1ff; + indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff; + + /* Calculation of fractional value */ + fract = findex - (float32_t) indexS; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexC ]; + f2 = sinTable_f32[indexC+1]; + d1 = -sinTable_f32[indexS ]; + d2 = -sinTable_f32[indexS+1]; + + Dn = 0.0122718463030f; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of cosine value */ + *pCosVal = fract * temp + f1; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexS ]; + f2 = sinTable_f32[indexS+1]; + d1 = sinTable_f32[indexC ]; + d2 = sinTable_f32[indexC+1]; + + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of sine value */ + *pSinVal = fract * temp + f1; + + if (theta < 0.0f) + { + *pSinVal = -*pSinVal; + } +} + +/** + @} end of SinCos group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c new file mode 100644 index 0000000..4198307 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c @@ -0,0 +1,114 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_q31.c + * Description: Cosine & Sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/controller_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Q31 sin_cos function. + @param[in] theta scaled input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + + The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179]. + */ + +void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal) +{ + q31_t fract; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + q31_t f1, f2, d1, d2; /* Two nearest output values */ + q31_t Dn, Df; + q63_t temp; + + /* Calculate the nearest index */ + indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT; + indexC = (indexS + 128) & 0x1ff; + + /* Calculation of fractional value */ + fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexC ]; + f2 = sinTable_q31[indexC+1]; + d1 = -sinTable_q31[indexS ]; + d2 = -sinTable_q31[indexS+1]; + + Dn = 0x1921FB5; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of cosine value */ + *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexS ]; + f2 = sinTable_q31[indexS+1]; + d1 = sinTable_q31[indexC ]; + d2 = sinTable_q31[indexC+1]; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of sine value */ + *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); +} + +/** + @} end of SinCos group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c new file mode 100644 index 0000000..921d039 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c @@ -0,0 +1,84 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +#endif + + +#define TT +#define TF +#define FT +#define EXT _TT_TF_FT +#include "edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TF +#define FT +#define EXT _TF_FT +#include "edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define FF +#define TF +#define FT +#define EXT _TT_FF_TF_FT +#include "edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define EXT _TT +#include "edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h" + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h new file mode 100755 index 0000000..b50c739 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h @@ -0,0 +1,551 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_boolean_distance.c + * Description: Templates for boolean distances + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + + +/** + * @defgroup DISTANCEF Distance Functions + * + * Computes Distances between vectors. + * + * Distance functions are useful in a lot of algorithms. + * + */ + + +/** + * @addtogroup DISTANCEF + * @{ + */ + + + + +#define _FUNC(A,B) A##B + +#define FUNC(EXT) _FUNC(arm_boolean_distance, EXT) + +/** + * @brief Elements of boolean distances + * + * Different values which are used to compute boolean distances + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return None + * + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ + +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t a, b, ba, bb; + int shift; + const uint8_t *pA8 = (const uint8_t *) pA; + const uint8_t *pB8 = (const uint8_t *) pB; + + /* handle vector blocks */ + uint32_t blkCnt = numberOfBools / 128; + + + + while (blkCnt > 0U) { + uint8x16_t vecA = vld1q((const uint8_t *) pA8); + uint8x16_t vecB = vld1q((const uint8_t *) pB8); + +#ifdef TT + uint8x16_t vecTT = vecA & vecB; + vecTT = vldrbq_gather_offset_u8(hwLUT, vecTT); + _ctt += vaddvq(vecTT); +#endif +#ifdef FF + uint8x16_t vecFF = vmvnq(vecA) & vmvnq(vecB); + vecFF = vldrbq_gather_offset_u8(hwLUT, vecFF); + _cff += vaddvq(vecFF); +#endif +#ifdef TF + uint8x16_t vecTF = vecA & vmvnq(vecB); + vecTF = vldrbq_gather_offset_u8(hwLUT, vecTF); + _ctf += vaddvq(vecTF); +#endif +#ifdef FT + uint8x16_t vecFT = vmvnq(vecA) & vecB; + vecFT = vldrbq_gather_offset_u8(hwLUT, vecFT); + _cft += vaddvq(vecFT); +#endif + + pA8 += 16; + pB8 += 16; + blkCnt--; + + } + + pA = (const uint32_t *)pA8; + pB = (const uint32_t *)pB8; + + blkCnt = numberOfBools & 0x7F; + while(blkCnt >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + blkCnt -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - blkCnt); + b = b >> (32 - blkCnt); + + while(blkCnt > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + blkCnt --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} + +#else +#if defined(ARM_MATH_NEON) + + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t nbBoolBlock; + uint32_t a,b,ba,bb; + int shift; + uint32x4_t aV, bV; +#ifdef TT + uint32x4_t cttV; +#endif +#ifdef FF + uint32x4_t cffV; +#endif +#ifdef TF + uint32x4_t ctfV; +#endif +#ifdef FT + uint32x4_t cftV; +#endif + uint8x16_t tmp; + uint16x8_t tmp2; + uint32x4_t tmp3; + uint64x2_t tmp4; +#ifdef TT + uint64x2_t tmp4tt; +#endif +#ifdef FF + uint64x2_t tmp4ff; +#endif +#ifdef TF + uint64x2_t tmp4tf; +#endif +#ifdef FT + uint64x2_t tmp4ft; +#endif + +#ifdef TT + tmp4tt = vdupq_n_u64(0); +#endif +#ifdef FF + tmp4ff = vdupq_n_u64(0); +#endif +#ifdef TF + tmp4tf = vdupq_n_u64(0); +#endif +#ifdef FT + tmp4ft = vdupq_n_u64(0); +#endif + + nbBoolBlock = numberOfBools >> 7; + while(nbBoolBlock > 0) + { + aV = vld1q_u32(pA); + bV = vld1q_u32(pB); + pA += 4; + pB += 4; + +#ifdef TT + cttV = vandq_u32(aV,bV); +#endif +#ifdef FF + cffV = vandq_u32(vmvnq_u32(aV),vmvnq_u32(bV)); +#endif +#ifdef TF + ctfV = vandq_u32(aV,vmvnq_u32(bV)); +#endif +#ifdef FT + cftV = vandq_u32(vmvnq_u32(aV),bV); +#endif + +#ifdef TT + tmp = vcntq_u8(vreinterpretq_u8_u32(cttV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4tt = vaddq_u64(tmp4tt, tmp4); +#endif + +#ifdef FF + tmp = vcntq_u8(vreinterpretq_u8_u32(cffV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4ff = vaddq_u64(tmp4ff, tmp4); +#endif + +#ifdef TF + tmp = vcntq_u8(vreinterpretq_u8_u32(ctfV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4tf = vaddq_u64(tmp4tf, tmp4); +#endif + +#ifdef FT + tmp = vcntq_u8(vreinterpretq_u8_u32(cftV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4ft = vaddq_u64(tmp4ft, tmp4); +#endif + + + nbBoolBlock --; + } + +#ifdef TT + _ctt += vgetq_lane_u64(tmp4tt, 0) + vgetq_lane_u64(tmp4tt, 1); +#endif +#ifdef FF + _cff +=vgetq_lane_u64(tmp4ff, 0) + vgetq_lane_u64(tmp4ff, 1); +#endif +#ifdef TF + _ctf += vgetq_lane_u64(tmp4tf, 0) + vgetq_lane_u64(tmp4tf, 1); +#endif +#ifdef FT + _cft += vgetq_lane_u64(tmp4ft, 0) + vgetq_lane_u64(tmp4ft, 1); +#endif + + nbBoolBlock = numberOfBools & 0x7F; + while(nbBoolBlock >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + nbBoolBlock -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - nbBoolBlock); + b = b >> (32 - nbBoolBlock); + + while(nbBoolBlock > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + nbBoolBlock --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} + +#else + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ + +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t a,b,ba,bb; + int shift; + + while(numberOfBools >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + numberOfBools -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - numberOfBools); + b = b >> (32 - numberOfBools); + + while(numberOfBools > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + numberOfBools --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} +#endif +#endif /* defined(ARM_MATH_MVEI) */ + + +/** + * @} end of DISTANCEF group + */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c new file mode 100644 index 0000000..1c056f2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c @@ -0,0 +1,162 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_braycurtis_distance_f16.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @ingroup groupDistance + */ + +/** + * @defgroup FloatDist Float Distances + * + * Distances between two vectors of float values. + */ + +/** + @ingroup FloatDist + */ + +/** + @defgroup braycurtis Bray-Curtis distance + + Bray-Curtis distance between two vectors + */ + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accumDiff = 0.0f, accumSum = 0.0f; + uint32_t blkCnt; + f16x8_t a, b, c, accumDiffV, accumSumV; + + + accumDiffV = vdupq_n_f16(0.0f); + accumSumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + accumDiffV = vaddq(accumDiffV, c); + + c = vaddq_f16(a, b); + c = vabsq_f16(c); + accumSumV = vaddq(accumSumV, c); + + pA += 8; + pB += 8; + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + c = vabdq(a, b); + accumDiffV = vaddq_m(accumDiffV, accumDiffV, c, p0); + + c = vaddq_f16(a, b); + c = vabsq_f16(c); + accumSumV = vaddq_m(accumSumV, accumSumV, c, p0); + } + + accumDiff = vecAddAcrossF16Mve(accumDiffV); + accumSum = vecAddAcrossF16Mve(accumSumV); + + /* + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + */ + return (accumDiff / accumSum); +} +#else + +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accumDiff=0.0f16, accumSum=0.0f16, tmpA, tmpB; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + accumSum += (_Float16)fabsf((float32_t)((_Float16)tmpA + (_Float16)tmpB)); + blockSize --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of braycurtis group + */ + + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c new file mode 100644 index 0000000..4a8fd6b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c @@ -0,0 +1,191 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_braycurtis_distance_f32.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff = 0.0f, accumSum = 0.0f; + uint32_t blkCnt; + f32x4_t a, b, c, accumDiffV, accumSumV; + + + accumDiffV = vdupq_n_f32(0.0f); + accumSumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + accumDiffV = vaddq(accumDiffV, c); + + c = vaddq_f32(a, b); + c = vabsq_f32(c); + accumSumV = vaddq(accumSumV, c); + + pA += 4; + pB += 4; + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + c = vabdq(a, b); + accumDiffV = vaddq_m(accumDiffV, accumDiffV, c, p0); + + c = vaddq_f32(a, b); + c = vabsq_f32(c); + accumSumV = vaddq_m(accumSumV, accumSumV, c, p0); + } + + accumDiff = vecAddAcrossF32Mve(accumDiffV); + accumSum = vecAddAcrossF32Mve(accumSumV); + + /* + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + */ + return (accumDiff / accumSum); +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff=0.0f, accumSum=0.0f; + uint32_t blkCnt; + float32x4_t a,b,c,accumDiffV, accumSumV; + float32x2_t accumV2; + + accumDiffV = vdupq_n_f32(0.0f); + accumSumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + c = vabdq_f32(a,b); + accumDiffV = vaddq_f32(accumDiffV,c); + + c = vaddq_f32(a,b); + c = vabsq_f32(c); + accumSumV = vaddq_f32(accumSumV,c); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumDiffV),vget_high_f32(accumDiffV)); + accumDiff = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + accumV2 = vpadd_f32(vget_low_f32(accumSumV),vget_high_f32(accumSumV)); + accumSum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accumDiff += fabsf(*pA - *pB); + accumSum += fabsf(*pA++ + *pB++); + blkCnt --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} + +#else +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff=0.0f, accumSum=0.0f, tmpA, tmpB; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += fabsf(tmpA - tmpB); + accumSum += fabsf(tmpA + tmpB); + blockSize --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of braycurtis group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c new file mode 100644 index 0000000..7cfffc1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c @@ -0,0 +1,175 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_canberra_distance_f16.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Canberra Canberra distance + + Canberra distance + */ + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum = 0.0f16; + uint32_t blkCnt; + f16x8_t a, b, c, accumV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_hiprec_f16(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f16(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq(accumV, c); + + pA += 8; + pB += 8; + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_hiprec_f16(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f16(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq_m(accumV, accumV, c, p0); + } + + accum = vecAddAcrossF16Mve(accumV); + + return (accum); +} + + +#else +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + sum = (_Float16)fabsf((float32_t)tmpA) + (_Float16)fabsf((float32_t)tmpB); + if (((_Float16)tmpA != 0.0f16) || ((_Float16)tmpB != 0.0f16)) + { + accum += ((_Float16)diff / (_Float16)sum); + } + blockSize --; + } + return(accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Canberra group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c new file mode 100644 index 0000000..78d1353 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c @@ -0,0 +1,226 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_canberra_distance_f32.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum = 0.0f; + uint32_t blkCnt; + f32x4_t a, b, c, accumV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_medprec_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f32(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq(accumV, c); + + pA += 4; + pB += 4; + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_medprec_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f32(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq_m(accumV, accumV, c, p0); + } + + accum = vecAddAcrossF32Mve(accumV); + + return (accum); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB,diff,sum; + uint32_t blkCnt; + float32x4_t a,b,c,accumV; + float32x2_t accumV2; + uint32x4_t isZeroV; + float32x4_t zeroV = vdupq_n_f32(0.0f); + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + c = vabdq_f32(a,b); + + a = vabsq_f32(a); + b = vabsq_f32(b); + a = vaddq_f32(a,b); + isZeroV = vceqq_f32(a,zeroV); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vinvq_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vreinterpretq_f32_s32(vbicq_s32(vreinterpretq_s32_f32(a),vreinterpretq_s32_u32(isZeroV))); + c = vmulq_f32(c,a); + accumV = vaddq_f32(accumV,c); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f) || (tmpB != 0.0f)) + { + accum += (diff / sum); + } + blkCnt --; + } + return(accum); +} + +#else +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f) || (tmpB != 0.0f)) + { + accum += (diff / sum); + } + blockSize --; + } + return(accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Canberra group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c new file mode 100644 index 0000000..bbf41dc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c @@ -0,0 +1,150 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f16.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Chebyshev Chebyshev distance + + Chebyshev distance + */ + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + f16x8_t vecA, vecB; + f16x8_t vecDiff = vdupq_n_f16(0.0); + float16_t maxValue = 0.0f16; + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + vecA = vld1q(pA); + pA += 8; + vecB = vld1q(pB); + pB += 8; + /* + * update per-lane max. + */ + vecDiff = vmaxnmaq(vsubq(vecA, vecB), vecDiff); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_z_f16(pA, p0); + vecB = vldrhq_z_f16(pB, p0); + + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + vecDiff = vmaxnmaq_m(vecDiff, vsubq(vecA, vecB), p0); + } + /* + * Get max value across the vector + */ + return vmaxnmavq(maxValue, vecDiff); +} + +#else +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + if ((_Float16)diff > (_Float16)maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Chebyshev group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c new file mode 100644 index 0000000..ee45e3d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c @@ -0,0 +1,217 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f32.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecA, vecB; + f32x4_t vecDiff = vdupq_n_f32(0.0); + float32_t maxValue = 0.0; + + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + vecA = vld1q(pA); + pA += 4; + vecB = vld1q(pB); + pB += 4; + /* + * update per-lane max. + */ + vecDiff = vmaxnmaq(vsubq(vecA, vecB), vecDiff); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_z_f32(pA, p0); + vecB = vldrwq_z_f32(pB, p0); + + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + vecDiff = vmaxnmaq_m(vecDiff, vsubq(vecA, vecB), p0); + } + /* + * Get max value across the vector + */ + return vmaxnmavq(maxValue, vecDiff); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t diff=0.0f, maxVal=0.0f, tmpA, tmpB; + uint32_t blkCnt; + float32x4_t a,b,diffV, maxValV; + float32x2_t maxValV2; + + if (blockSize <= 3) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + } + else + { + + a = vld1q_f32(pA); + b = vld1q_f32(pB); + pA += 4; + pB += 4; + + diffV = vabdq_f32(a,b); + + blockSize -= 4; + + maxValV = diffV; + + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + diffV = vabdq_f32(a,b); + maxValV = vmaxq_f32(maxValV, diffV); + + pA += 4; + pB += 4; + blkCnt --; + } + maxValV2 = vpmax_f32(vget_low_f32(maxValV),vget_high_f32(maxValV)); + maxValV2 = vpmax_f32(maxValV2,maxValV2); + maxVal = vget_lane_f32(maxValV2,0); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blkCnt --; + } + } + return(maxVal); +} + +#else +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Chebyshev group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c new file mode 100644 index 0000000..0b64f72 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c @@ -0,0 +1,80 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f64.c + * Description: Chebyshev distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t diff=0., maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabs(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabs(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} + +/** + * @} end of Chebyshev group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c new file mode 100644 index 0000000..0c9cc2f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c @@ -0,0 +1,132 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f16.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Manhattan Cityblock (Manhattan) distance + + Cityblock (Manhattan) distance + */ + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + f16x8_t a, b, accumV, tempV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vabdq(a, b); + accumV = vaddq(accumV, tempV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tempV = vabdq(a, b); + accumV = vaddq_m(accumV, accumV, tempV, p0); + } + + return vecAddAcrossF16Mve(accumV); +} + +#else +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum,tmpA, tmpB; + + accum = 0.0f16; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + + blockSize --; + } + + return(accum); +} +#endif + +/** + * @} end of Manhattan group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c new file mode 100644 index 0000000..a749055 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c @@ -0,0 +1,161 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f32.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + f32x4_t a, b, accumV, tempV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vabdq(a, b); + accumV = vaddq(accumV, tempV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tempV = vabdq(a, b); + accumV = vaddq_m(accumV, accumV, tempV, p0); + } + + return vecAddAcrossF32Mve(accumV); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB; + uint32_t blkCnt; + float32x4_t a,b,accumV, tempV; + float32x2_t accumV2; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + tempV = vabdq_f32(a,b); + accumV = vaddq_f32(accumV, tempV); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accumV2 = vpadd_f32(accumV2,accumV2); + accum = vget_lane_f32(accumV2,0); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabsf(tmpA - tmpB); + + blkCnt --; + } + return(accum); +} + +#else +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum,tmpA, tmpB; + + accum = 0.0f; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabsf(tmpA - tmpB); + + blockSize --; + } + + return(accum); +} +#endif +#endif + +/** + * @} end of Manhattan group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c new file mode 100644 index 0000000..e07e7a7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c @@ -0,0 +1,71 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f64.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t accum,tmpA, tmpB; + + accum = 0.; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabs(tmpA - tmpB); + + blockSize --; + } + + return(accum); +} + +/** + * @} end of Manhattan group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c new file mode 100644 index 0000000..715484b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c @@ -0,0 +1,103 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlation_distance_f16.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Correlation Correlation distance + + Correlation distance + */ + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize) +{ + float16_t ma,mb,pwra,pwrb,dot,tmp; + + arm_mean_f16(pA, blockSize, &ma); + arm_mean_f16(pB, blockSize, &mb); + + arm_offset_f16(pA, -(_Float16)ma, pA, blockSize); + arm_offset_f16(pB, -(_Float16)mb, pB, blockSize); + + arm_power_f16(pA, blockSize, &pwra); + arm_power_f16(pB, blockSize, &pwrb); + + arm_dot_prod_f16(pA,pB,blockSize,&dot); + + dot = (_Float16)dot / (_Float16)blockSize; + pwra = (_Float16)pwra / (_Float16)blockSize; + pwrb = (_Float16)pwrb / (_Float16)blockSize; + + arm_sqrt_f16((_Float16)pwra * (_Float16)pwrb,&tmp); + + return(1.0f16 - (_Float16)dot / (_Float16)tmp); + + +} + + + +/** + * @} end of Correlation group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c new file mode 100644 index 0000000..79d26a9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c @@ -0,0 +1,88 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlation_distance_f32.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize) +{ + float32_t ma,mb,pwra,pwrb,dot,tmp; + + arm_mean_f32(pA, blockSize, &ma); + arm_mean_f32(pB, blockSize, &mb); + + arm_offset_f32(pA, -ma, pA, blockSize); + arm_offset_f32(pB, -mb, pB, blockSize); + + arm_power_f32(pA, blockSize, &pwra); + arm_power_f32(pB, blockSize, &pwrb); + + arm_dot_prod_f32(pA,pB,blockSize,&dot); + + dot = dot / blockSize; + pwra = pwra / blockSize; + pwrb = pwrb / blockSize; + + arm_sqrt_f32(pwra * pwrb,&tmp); + + return(1.0f - dot / tmp); + + +} + + + +/** + * @} end of Correlation group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c new file mode 100644 index 0000000..453aebf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c @@ -0,0 +1,92 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f16.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup CosineDist Cosine distance + + Cosine distance + */ + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + * @par Description + * cosine_distance(u,v) is 1 - u . v / (Norm(u) Norm(v)) + */ + +float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + float16_t pwra,pwrb,dot,tmp; + + arm_power_f16(pA, blockSize, &pwra); + arm_power_f16(pB, blockSize, &pwrb); + + arm_dot_prod_f16(pA,pB,blockSize,&dot); + + arm_sqrt_f16((_Float16)pwra * (_Float16)pwrb, &tmp); + return(1.0f16 - (_Float16)dot / (_Float16)tmp); + +} + + + +/** + * @} end of CosineDist group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c new file mode 100644 index 0000000..871c7af --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c @@ -0,0 +1,76 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f32.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + * @par Description + * cosine_distance(u,v) is 1 - u . v / (Norm(u) Norm(v)) + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t pwra,pwrb,dot,tmp; + + arm_power_f32(pA, blockSize, &pwra); + arm_power_f32(pB, blockSize, &pwrb); + + arm_dot_prod_f32(pA,pB,blockSize,&dot); + + arm_sqrt_f32(pwra * pwrb, &tmp); + return(1.0f - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c new file mode 100644 index 0000000..ea5e654 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c @@ -0,0 +1,74 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f64.c + * Description: Cosine distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t pwra,pwrb,dot,tmp; + + arm_power_f64(pA, blockSize, &pwra); + arm_power_f64(pB, blockSize, &pwrb); + + arm_dot_prod_f64(pA,pB,blockSize,&dot); + + tmp = sqrt(pwra * pwrb); + return(1. - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c new file mode 100644 index 0000000..d27dfc9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dice_distance.c + * Description: Dice distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + * @ingroup groupDistance + * @{ + */ + +/** + * @defgroup BoolDist Boolean Distances + * + * Distances between two vectors of boolean values. + * + * Booleans are packed in 32 bit words. + * numberOfBooleans argument is the number of booleans and not the + * number of words. + * + * Bits are packed in big-endian mode (because of behavior of numpy packbits in + * in version < 1.17) + */ + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (2.0*ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ + +/** + * @} end of groupDistance group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c new file mode 100644 index 0000000..dd1d9ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c @@ -0,0 +1,135 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f16.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Euclidean Euclidean distance + + Euclidean distance + */ + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float16_t tmp; + f16x8_t a, b, accumV, tempV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vsubq(a, b); + accumV = vfmaq(accumV, tempV, tempV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tempV = vsubq(a, b); + accumV = vfmaq_m(accumV, tempV, tempV, p0); + } + + arm_sqrt_f16(vecAddAcrossF16Mve(accumV), &tmp); + return (tmp); +} + +#else +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f,tmp; + float16_t result; + + while(blockSize > 0) + { + tmp = (_Float16)*pA++ - (_Float16)*pB++; + accum += SQ(tmp); + blockSize --; + } + arm_sqrt_f16(accum,&result); + return(result); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Euclidean group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c new file mode 100644 index 0000000..ccbdc77 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c @@ -0,0 +1,156 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f32.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t tmp; + f32x4_t a, b, accumV, tempV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vsubq(a, b); + accumV = vfmaq(accumV, tempV, tempV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tempV = vsubq(a, b); + accumV = vfmaq_m(accumV, tempV, tempV, p0); + } + + arm_sqrt_f32(vecAddAcrossF32Mve(accumV), &tmp); + return (tmp); +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f,tmp; + uint32_t blkCnt; + float32x4_t a,b,accumV; + float32x2_t accumV2; + + accumV = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + a = vsubq_f32(a,b); + accumV = vmlaq_f32(accumV,a,a); + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blkCnt --; + } + arm_sqrt_f32(accum,&tmp); + return(tmp); +} + +#else +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f,tmp; + + while(blockSize > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blockSize --; + } + arm_sqrt_f32(accum,&tmp); + return(tmp); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Euclidean group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c new file mode 100644 index 0000000..04c42f7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c @@ -0,0 +1,70 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f64.c + * Description: Euclidean distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t accum=0.,tmp; + + while(blockSize > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blockSize --; + } + tmp = sqrt(accum); + return(tmp); +} + +/** + * @} end of Euclidean group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c new file mode 100644 index 0000000..28f2733 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c @@ -0,0 +1,74 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_hamming_distance.c + * Description: Hamming distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctf=0,cft=0; + + arm_boolean_distance_TF_FT(pA, pB, numberOfBools, &ctf, &cft); + + return(1.0*(ctf + cft) / numberOfBools); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c new file mode 100644 index 0000000..30d061b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c @@ -0,0 +1,76 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jaccard_distance.c + * Description: Jaccard distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c new file mode 100644 index 0000000..14bd4b0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c @@ -0,0 +1,181 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jensenshannon_distance_f16.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup JensenShannon Jensen-Shannon distance + + Jensen-Shannon distance + */ + + +/** + @addtogroup JensenShannon + @{ + */ + +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) +/// @private +__STATIC_INLINE float16_t rel_entr(float16_t x, float16_t y) +{ + return ((_Float16)x * (_Float16)logf((float32_t)((_Float16)x / (_Float16)y))); +} +#endif + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float16_t tmp; + f16x8_t a, b, t, tmpV, accumV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq(a, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq(accumV, a, tmpV); + + tmpV = vmulq_f16(b, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq(accumV, b, tmpV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq_f16(a, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq_m_f16(accumV, a, tmpV, p0); + + tmpV = vmulq_f16(b, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq_m_f16(accumV, b, tmpV, p0); + + } + + arm_sqrt_f16((_Float16)vecAddAcrossF16Mve(accumV) / 2.0f16, &tmp); + return (tmp); +} + +#else + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 left, right,sum, tmp; + float16_t result; + uint32_t i; + + left = 0.0f16; + right = 0.0f16; + for(i=0; i < blockSize; i++) + { + tmp = ((_Float16)pA[i] + (_Float16)pB[i]) / 2.0f16; + left += (_Float16)rel_entr(pA[i], tmp); + right += (_Float16)rel_entr(pB[i], tmp); + } + + + sum = left + right; + arm_sqrt_f16((_Float16)sum/2.0f16, &result); + return(result); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of JensenShannon group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c new file mode 100644 index 0000000..6aeb797 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c @@ -0,0 +1,251 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jensenshannon_distance_f32.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup JensenShannon + @{ + */ + +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) +/// @private +__STATIC_INLINE float32_t rel_entr(float32_t x, float32_t y) +{ + return (x * logf(x / y)); +} +#endif + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t tmp; + f32x4_t a, b, t, tmpV, accumV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq(a, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq(accumV, a, tmpV); + + tmpV = vmulq_f32(b, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq(accumV, b, tmpV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq_f32(a, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq_m_f32(accumV, a, tmpV, p0); + + tmpV = vmulq_f32(b, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq_m_f32(accumV, b, tmpV, p0); + + } + + arm_sqrt_f32(vecAddAcrossF32Mve(accumV) / 2.0f, &tmp); + return (tmp); +} + +#else + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum, result, tmp,a,b; + uint32_t blkCnt; + float32x4_t aV,bV,t, tmpV, accumV; + float32x2_t accumV2; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + aV = vld1q_f32(pA); + bV = vld1q_f32(pB); + t = vaddq_f32(aV,bV); + t = vmulq_n_f32(t, 0.5f); + + tmpV = vmulq_f32(aV, vinvq_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, aV, tmpV); + + + tmpV = vmulq_f32(bV, vinvq_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, bV, tmpV); + + pA += 4; + pB += 4; + + + blkCnt --; + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + a = *pA; + b = *pB; + tmp = (a + b) / 2.0f; + accum += rel_entr(a, tmp); + accum += rel_entr(b, tmp); + + pA++; + pB++; + + blkCnt --; + } + + + arm_sqrt_f32(accum/2.0f, &result); + return(result); + +} + +#else + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t left, right,sum, result, tmp; + uint32_t i; + + left = 0.0f; + right = 0.0f; + for(i=0; i < blockSize; i++) + { + tmp = (pA[i] + pB[i]) / 2.0f; + left += rel_entr(pA[i], tmp); + right += rel_entr(pB[i], tmp); + } + + + sum = left + right; + arm_sqrt_f32(sum/2.0f, &result); + return(result); + +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of JensenShannon group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c new file mode 100644 index 0000000..1bcb2ef --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c @@ -0,0 +1,77 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_kulsinski_distance.c + * Description: Kulsinski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft - ctt + numberOfBools) / (cft + ctf + numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c new file mode 100644 index 0000000..ae9c3cb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c @@ -0,0 +1,141 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_minkowski_distance_f16.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Minkowski Minkowski distance + + Minkowski distance + */ + +/** + @addtogroup Minkowski + @{ + */ + + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize) +{ + uint32_t blkCnt; + f16x8_t a, b, tmpV, sumV; + + sumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tmpV = vabdq(a, b); + tmpV = vpowq_f16(tmpV, vdupq_n_f16(order)); + sumV = vaddq(sumV, tmpV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tmpV = vabdq(a, b); + tmpV = vpowq_f16(tmpV, vdupq_n_f16(order)); + sumV = vaddq_m(sumV, sumV, tmpV, p0); + } + + return (powf((float32_t)vecAddAcrossF16Mve(sumV), (1.0f / (float32_t) order))); +} + + +#else + + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize) +{ + _Float16 sum; + uint32_t i; + + sum = 0.0f16; + for(i=0; i < blockSize; i++) + { + sum += (_Float16)powf(fabsf((float32_t)((_Float16)pA[i] - (_Float16)pB[i])),order); + } + + + return(_Float16)(powf((float32_t)sum,(1.0f/(float32_t)order))); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Minkowski group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c new file mode 100644 index 0000000..e29d8e1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c @@ -0,0 +1,192 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_minkowski_distance_f32.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Minkowski + @{ + */ + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) + +__attribute__((weak)) float __powisf2(float a, int b) +{ + const int recip = b < 0; + float r = 1; + while (1) + { + if (b & 1) + r *= a; + b /= 2; + if (b == 0) + break; + a *= a; + } + return recip ? 1/r : r; +} +#endif + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + uint32_t blkCnt; + f32x4_t a, b, tmpV, sumV; + + sumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tmpV = vabdq(a, b); + tmpV = vpowq_f32(tmpV, vdupq_n_f32(order)); + sumV = vaddq(sumV, tmpV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tmpV = vabdq(a, b); + tmpV = vpowq_f32(tmpV, vdupq_n_f32(order)); + sumV = vaddq_m(sumV, sumV, tmpV, p0); + } + + return (powf(vecAddAcrossF32Mve(sumV), (1.0f / (float32_t) order))); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + float32_t sum; + uint32_t blkCnt; + float32x4_t sumV,aV,bV, tmpV, n; + float32x2_t sumV2; + + sum = 0.0f; + sumV = vdupq_n_f32(0.0f); + n = vdupq_n_f32(order); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + aV = vld1q_f32(pA); + bV = vld1q_f32(pB); + pA += 4; + pB += 4; + + tmpV = vabdq_f32(aV,bV); + tmpV = vpowq_f32(tmpV,n); + sumV = vaddq_f32(sumV, tmpV); + + + blkCnt --; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + sum += powf(fabsf(*pA++ - *pB++),order); + + blkCnt --; + } + + + return(powf(sum,(1.0f/order))); + +} + +#else + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + float32_t sum; + uint32_t i; + + sum = 0.0f; + for(i=0; i < blockSize; i++) + { + sum += powf(fabsf(pA[i] - pB[i]),order); + } + + + return(powf(sum,(1.0f/order))); + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Minkowski group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c new file mode 100644 index 0000000..eb7820d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rogerstanimoto_distance.c + * Description: Roger Stanimoto distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Rogers Tanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf + cft); + + return(1.0*r / (r + ctt + cff)); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c new file mode 100644 index 0000000..0be143e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c @@ -0,0 +1,76 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_russellrao_distance.c + * Description: Russell-Rao distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0; + + + arm_boolean_distance_TT(pA, pB, numberOfBools, &ctt); + + + return(1.0f*(numberOfBools - ctt) / ((float32_t)numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c new file mode 100644 index 0000000..3b7fd14 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c @@ -0,0 +1,80 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sokalmichener_distance.c + * Description: Sokal-Michener distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,cft=0,ctf=0; + float32_t r,s; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt, &cff, &ctf, &cft); + + r = 2.0*(ctf + cft); + s = 1.0*(cff + ctt); + + return(r / (s+r)); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c new file mode 100644 index 0000000..707466e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c @@ -0,0 +1,78 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sokalsneath_distance.c + * Description: Sokal-Sneath distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cft=0,ctf=0; + float32_t r; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + r = 2.0*(ctf + cft); + + return(r / (r + ctt)); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c new file mode 100644 index 0000000..cf52c90 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c @@ -0,0 +1,78 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_yule_distance.c + * Description: Yule distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf * cft); + + return(1.0*r / (r/2.0 + ctt * cff)); +} + + +/** + * @} end of BoolDist group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c new file mode 100644 index 0000000..93c898c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c @@ -0,0 +1,175 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_f16.c + * Description: float16 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/* + +atan for argument between in [0, 1.0] + + +*/ + +#define PIF16 3.14f16 +#define PI16HALF 1.571f16 + +#define ATANHALFF16 0.463648f16 + +#define ATAN2_NB_COEFS_F16 5 + +static const float16_t atan2_coefs_f16[ATAN2_NB_COEFS_F16]={0.f16 +,1.f16 +,0.f16 +,-0.367f16 +,0.152f16 +}; + +__STATIC_FORCEINLINE float16_t arm_atan_limited_f16(float16_t x) +{ + float16_t res=atan2_coefs_f16[ATAN2_NB_COEFS_F16-1]; + int i=1; + for(i=1;i 1.0f16) + { + x = 1.0f16 / (_Float16)x; + res = (_Float16)PI16HALF - (_Float16)arm_atan_limited_f16(x); + } + else + { + res += (_Float16)arm_atan_limited_f16(x); + } + + + if (sign) + { + res = -(_Float16)res; + } + + return(res); +} + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. + +*/ +arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result) +{ + if ((_Float16)x > 0.0f16) + { + *result=arm_atan_f16((_Float16)y/(_Float16)x); + return(ARM_MATH_SUCCESS); + } + if ((_Float16)x < 0.0f16) + { + if ((_Float16)y > 0.0f16) + { + *result=(_Float16)arm_atan_f16((_Float16)y/(_Float16)x) + (_Float16)PIF16; + } + else if ((_Float16)y < 0.0f16) + { + *result=(_Float16)arm_atan_f16((_Float16)y/(_Float16)x) - (_Float16)PIF16; + } + else + { + if (signbit((float)y)) + { + *result= -(_Float16)PIF16; + } + else + { + *result= PIF16; + } + } + return(ARM_MATH_SUCCESS); + } + if ((_Float16)x == 0.0f16) + { + if ((_Float16)y > 0.0f16) + { + *result=PI16HALF; + return(ARM_MATH_SUCCESS); + } + if ((_Float16)y < 0.0f16) + { + *result=-(_Float16)PI16HALF; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of atan2 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c new file mode 100644 index 0000000..51f6812 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c @@ -0,0 +1,187 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_f32.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +/* + +atan for argument between in [0, 1.0] + + +*/ + +#define ATANHALFF32 0.463648f +#define PIHALFF32 1.5707963267948966192313f + +#define ATAN2_NB_COEFS_F32 10 + +static const float32_t atan2_coefs_f32[ATAN2_NB_COEFS_F32]={0.0f +,1.0000001638308195518f +,-0.0000228941363602264f +,-0.3328086544578890873f +,-0.004404814619311061f +,0.2162217461808173258f +,-0.0207504842057097504f +,-0.1745263362250363339f +,0.1340557235283553386f +,-0.0323664125927477625f +}; + +__STATIC_FORCEINLINE float32_t arm_atan_limited_f32(float32_t x) +{ + float32_t res=atan2_coefs_f32[ATAN2_NB_COEFS_F32-1]; + int i=1; + for(i=1;i 1.0f) + { + x = 1.0f / x; + res = PIHALFF32 - arm_atan_limited_f32(x); + } + else + { + res += arm_atan_limited_f32(x); + } + + + if (sign) + { + res = -res; + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + +/** + @defgroup atan2 ArcTan2 + + Computing Arc tangent only using the ratio y/x is not enough to determine the angle + since there is an indeterminacy. Opposite quadrants are giving the same ratio. + + ArcTan2 is not using y/x to compute the angle but y and x and use the sign of y and x + to determine the quadrant. + + */ + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result) +{ + if (x > 0.0f) + { + *result=arm_atan_f32(y/x); + return(ARM_MATH_SUCCESS); + } + if (x < 0.0f) + { + if (y > 0.0f) + { + *result=arm_atan_f32(y/x) + PI; + } + else if (y < 0.0f) + { + *result=arm_atan_f32(y/x) - PI; + } + else + { + if (signbit(y)) + { + *result= -PI; + } + else + { + *result= PI; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0.0f) + { + if (y > 0.0f) + { + *result=PIHALFF32; + return(ARM_MATH_SUCCESS); + } + if (y < 0.0f) + { + *result=-PIHALFF32; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c new file mode 100644 index 0000000..c334bee --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c @@ -0,0 +1,239 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_q15.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +/* + +atan for argument between in [0, 1.0] + +*/ + + +/* Q2.13 */ +#define ATANHALFQ13 0xed6 +#define PIHALFQ13 0x3244 +#define PIQ13 0x6488 + +#define ATAN2_NB_COEFS_Q15 10 + +static const q15_t atan2_coefs_q15[ATAN2_NB_COEFS_Q15]={0x0000 +,0x7fff +,0xffff +,0xd567 +,0xff70 +,0x1bad +,0xfd58 +,0xe9a9 +,0x1129 +,0xfbdb +}; + +__STATIC_FORCEINLINE q15_t arm_atan_limited_q15(q15_t x) +{ + q31_t res=(q31_t)atan2_coefs_q15[ATAN2_NB_COEFS_Q15-1]; + int i=1; + for(i=1;i> 15U; + res = res + ((q31_t) atan2_coefs_q15[ATAN2_NB_COEFS_Q15-1-i]) ; + } + + res = __SSAT(res>>2,16); + + + return(res); +} + + +__STATIC_FORCEINLINE q15_t arm_atan_q15(q15_t y,q15_t x) +{ + int sign=0; + q15_t res=0; + + if (y<0) + { + /* Negate y */ +#if defined (ARM_MATH_DSP) + y = __QSUB16(0, y); +#else + y = (y == (q15_t) 0x8000) ? (q15_t) 0x7fff : -y; +#endif + + sign=1-sign; + } + + if (x < 0) + { + sign=1 - sign; + + /* Negate x */ +#if defined (ARM_MATH_DSP) + x = __QSUB16(0, x); +#else + x = (x == (q15_t) 0x8000) ? (q15_t) 0x7fff : -x; +#endif + } + + if (y > x) + { + q15_t ratio; + int16_t shift; + + arm_divide_q15(x,y,&ratio,&shift); + + /* Shift ratio by shift */ + if (shift >=0) + { + ratio = __SSAT(((q31_t) ratio << shift), 16); + } + else + { + ratio = (ratio >> -shift); + } + + res = PIHALFQ13 - arm_atan_limited_q15(ratio); + + } + else + { + q15_t ratio; + int16_t shift; + + arm_divide_q15(y,x,&ratio,&shift); + + /* Shift ratio by shift */ + if (shift >=0) + { + ratio = __SSAT(((q31_t) ratio << shift), 16); + } + else + { + ratio = (ratio >> -shift); + } + + + res = arm_atan_limited_q15(ratio); + + } + + + if (sign) + { + /* Negate res */ +#if defined (ARM_MATH_DSP) + res = __QSUB16(0, res); +#else + res = (res == (q15_t) 0x8000) ? (q15_t) 0x7fff : -res; +#endif + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.13 + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result) +{ + if (x > 0) + { + *result=arm_atan_q15(y,x); + return(ARM_MATH_SUCCESS); + } + if (x < 0) + { + if (y > 0) + { + *result=arm_atan_q15(y,x) + PIQ13; + } + else if (y < 0) + { + *result=arm_atan_q15(y,x) - PIQ13; + } + else + { + if (y<0) + { + *result= -PIQ13; + } + else + { + *result= PIQ13; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0) + { + if (y > 0) + { + *result=PIHALFQ13; + return(ARM_MATH_SUCCESS); + } + if (y < 0) + { + *result=-PIHALFQ13; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c new file mode 100644 index 0000000..6eba0ce --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c @@ -0,0 +1,240 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_q31.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/utils.h" + +/* + +atan for argument between in [0, 1.0] + +*/ + + +/* Q2.29 */ +#define ATANHALF_Q29 0xed63383 +#define PIHALF_Q29 0x3243f6a9 +#define PIQ29 0x6487ed51 + +#define ATAN2_NB_COEFS_Q31 13 + +static const q31_t atan2_coefs_q31[ATAN2_NB_COEFS_Q31]={0x00000000 +,0x7ffffffe +,0x000001b6 +,0xd555158e +,0x00036463 +,0x1985f617 +,0x001992ae +,0xeed53a7f +,0xf8f15245 +,0x2215a3a4 +,0xe0fab004 +,0x0cdd4825 +,0xfddbc054 +}; + + +__STATIC_FORCEINLINE q31_t arm_atan_limited_q31(q31_t x) +{ + q63_t res=(q63_t)atan2_coefs_q31[ATAN2_NB_COEFS_Q31-1]; + int i=1; + for(i=1;i> 31U; + res = res + ((q63_t) atan2_coefs_q31[ATAN2_NB_COEFS_Q31-1-i]) ; + } + + return(clip_q63_to_q31(res>>2)); +} + + +__STATIC_FORCEINLINE q31_t arm_atan_q31(q31_t y,q31_t x) +{ + int sign=0; + q31_t res=0; + + if (y<0) + { + /* Negate y */ +#if defined (ARM_MATH_DSP) + y = __QSUB(0, y); +#else + y = (y == INT32_MIN) ? INT32_MAX : -y; +#endif + + sign=1-sign; + } + + if (x < 0) + { + sign=1 - sign; + + /* Negate x */ +#if defined (ARM_MATH_DSP) + x = __QSUB(0, x); +#else + x = (x == INT32_MIN) ? INT32_MAX : -x; +#endif + } + + if (y > x) + { + q31_t ratio; + int16_t shift; + + arm_divide_q31(x,y,&ratio,&shift); + + /* Shift ratio by shift */ + if (shift >= 0) + { + ratio = clip_q63_to_q31((q63_t) ratio << shift); + } + else + { + ratio = (ratio >> -shift); + } + + res = PIHALF_Q29 - arm_atan_limited_q31(ratio); + + } + else + { + q31_t ratio; + int16_t shift; + + arm_divide_q31(y,x,&ratio,&shift); + + /* Shift ratio by shift */ + if (shift >= 0) + { + ratio = clip_q63_to_q31((q63_t) ratio << shift); + } + else + { + ratio = (ratio >> -shift); + } + + + res = arm_atan_limited_q31(ratio); + + } + + + if (sign) + { + /* Negate res */ +#if defined (ARM_MATH_DSP) + res = __QSUB(0, res); +#else + res = (res == INT32_MIN) ? INT32_MAX : -res; +#endif + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.29 + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result) +{ + if (x > 0) + { + *result=arm_atan_q31(y,x); + return(ARM_MATH_SUCCESS); + } + if (x < 0) + { + if (y > 0) + { + *result=arm_atan_q31(y,x) + PIQ29; + } + else if (y < 0) + { + *result=arm_atan_q31(y,x) - PIQ29; + } + else + { + if (y<0) + { + *result= -PIQ29; + } + else + { + *result= PIQ29; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0) + { + if (y > 0) + { + *result=PIHALF_Q29; + return(ARM_MATH_SUCCESS); + } + if (y < 0) + { + *result=-PIHALF_Q29; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c new file mode 100644 index 0000000..ac428dc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c @@ -0,0 +1,125 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_f32.c + * Description: Fast cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup cos Cosine + + Computes the trigonometric cosine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     a = Table[index];
+     b = Table[index+1];
+
+ */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for floating-point data. + @param[in] x input value in radians + @return cos(x) + */ +float32_t arm_cos_f32( + float32_t x) +{ + float32_t cosVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */ + in = x * 0.159154943092f + 0.25f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the cos table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + cosVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (cosVal); +} + +/** + @} end of cos group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c new file mode 100644 index 0000000..c423b06 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c @@ -0,0 +1,88 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q15 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_cos_q15( + q15_t x) +{ + q15_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint16_t)x + 0x2000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + cosVal = (q31_t) (0x8000 - fract) * a >> 16; + cosVal = (q15_t) ((((q31_t) cosVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c new file mode 100644 index 0000000..749dd0e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c @@ -0,0 +1,88 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q31 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_cos_q31( + q31_t x) +{ + q31_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint32_t)x + 0x20000000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + cosVal = (q63_t) (0x80000000 - fract) * a >> 32; + cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c new file mode 100644 index 0000000..c53a379 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c @@ -0,0 +1,114 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#include + +/** + @ingroup groupFastMath + */ + +/** + @defgroup divide Fixed point division + + */ + +/** + @addtogroup divide + @{ + */ + +/** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q31_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>15) ^ (denominator>>15); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x8000; + } + else + { + *quotient = 0x7FFF; + } + return(ARM_MATH_NANINF); + } + + arm_abs_q15(&numerator,&numerator,1); + arm_abs_q15(&denominator,&denominator,1); + + temp = ((q31_t)numerator << 15) / ((q31_t)denominator); + + shiftForNormalizing= 17 - __CLZ(temp); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=temp; + + return(ARM_MATH_SUCCESS); +} + +/** + @} end of divide group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c new file mode 100644 index 0000000..b1ae866 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c @@ -0,0 +1,109 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#include + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup divide + @{ + */ + +/** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q31(q31_t numerator, + q31_t denominator, + q31_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q63_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>31) ^ (denominator>>31); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x80000000; + } + else + { + *quotient = 0x7FFFFFFF; + } + return(ARM_MATH_NANINF); + } + + arm_abs_q31(&numerator,&numerator,1); + arm_abs_q31(&denominator,&denominator,1); + + temp = ((q63_t)numerator << 31) / ((q63_t)denominator); + + shiftForNormalizing= 32 - __CLZ(temp >> 31); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=(q31_t)temp; + + return(ARM_MATH_SUCCESS); +} + +/** + @} end of divide group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c new file mode 100644 index 0000000..89cc8b1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c @@ -0,0 +1,126 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_f32.c + * Description: Fast sine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup sin Sine + + Computes the trigonometric sine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     b = Table[index];
+     c = Table[index+1];
+
+ */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for floating-point data. + @param[in] x input value in radians. + @return sin(x) + */ + +float32_t arm_sin_f32( + float32_t x) +{ + float32_t sinVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi */ + in = x * 0.159154943092f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + sinVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (sinVal); +} + +/** + @} end of sin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c new file mode 100644 index 0000000..7d99d9f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c @@ -0,0 +1,87 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q15.c + * Description: Fast sine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q15 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_sin_q15( + q15_t x) +{ + q15_t sinVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + sinVal = (q31_t) (0x8000 - fract) * a >> 16; + sinVal = (q15_t) ((((q31_t) sinVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c new file mode 100644 index 0000000..92f2ba6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c @@ -0,0 +1,86 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q31.c + * Description: Fast sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q31 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_sin_q31( + q31_t x) +{ + q31_t sinVal; /* Temporary variables for input, output */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + sinVal = (q63_t) (0x80000000 - fract) * a >> 32; + sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c new file mode 100644 index 0000000..bfcb9b2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c @@ -0,0 +1,128 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q15.c + * Description: Q15 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#define Q12QUARTER 0x2000 + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut) +{ + q15_t number, var1, signBits1,temp; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 17; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + /* Start value for 1/sqrt(x) for the Newton iteration */ + var1 = sqrt_initial_lut_q15[(number>> 11) - (Q12QUARTER >> 11)]; + + /* 0.5 var1 * (3 - number * var1 * var1) */ + /* 1st iteration */ + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + /* Multiply the inverse square root with the original value */ + + var1 = ((q15_t) (((q31_t) number * var1) >> 12)); + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c new file mode 100644 index 0000000..0b8954a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c @@ -0,0 +1,131 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q31.c + * Description: Q31 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#define Q28QUARTER 0x20000000 + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut) +{ + q31_t number, var1, signBits1 ,temp; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 1; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + + /* Start value for 1/sqrt(x) for the Newton iteration */ + var1 = sqrt_initial_lut_q31[(number>> 26) - (Q28QUARTER >> 26)]; + + /* 0.5 var1 * (3 - number * var1 * var1) */ + + /* 1st iteration */ + + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + + /* 2nd iteration */ + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + /* 3nd iteration */ + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + /* Multiply the inverse square root with the original value */ + var1 = ((q31_t) (((q63_t) number * var1) >> 28)); + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c new file mode 100644 index 0000000..dffb4de --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c @@ -0,0 +1,99 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +/** + @addtogroup vexp + @{ + */ + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vexpq_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = (_Float16)expf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +/** + @} end of vexp group + */ +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c new file mode 100644 index 0000000..3f23825 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c @@ -0,0 +1,126 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM) || defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" +#endif + +/** + @ingroup groupFastMath + */ + +/** + @defgroup vexp Vector Exponential + + Compute the exp values of a vector of samples. +*/ + +/** + @addtogroup vexp + @{ + */ + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vexpq_f32(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q_f32(pSrc); + dst = vexpq_f32(src); + vst1q_f32(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else + blkCnt = blockSize; +#endif +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = expf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vexp group + */ +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c new file mode 100644 index 0000000..950c0a5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c @@ -0,0 +1,70 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f64.c + * Description: Fast vectorized log + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @addtogroup vexp + @{ + */ + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_vexp_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = exp(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vexp group + */ +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c new file mode 100644 index 0000000..ec9e842 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c @@ -0,0 +1,83 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vinverse_f16.c + * Description: Fast vectorized inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +void arm_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vrecip_hiprec_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + + *pDst++ = 1.0f16 / (_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c new file mode 100644 index 0000000..60b4af3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c @@ -0,0 +1,226 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/* Degree of the polynomial approximation */ +#define NB_DEG_LOGF16 3 + +/* +Related to the Log2 of the number of approximations. +For instance, with 3 there are 1 + 2^3 polynomials +*/ +#define NB_DIV_LOGF16 3 + +/* Length of the LUT table */ +#define NB_LUT_LOGF16 (NB_DEG_LOGF16+1)*(1 + (1< 1000][[2, 1]], {i, 1, 2, (1.0/2^nb)}]; +coefs = Chop@Flatten[CoefficientList[lut, x]]; + +*/ +static float16_t lut_logf16[NB_LUT_LOGF16]={ + 0,0.125,-0.00781197,0.00063974,0.117783, + 0.111111,-0.00617212,0.000447935,0.223144, + 0.1,-0.00499952,0.000327193,0.318454,0.0909091, + -0.00413191,0.000246234,0.405465,0.0833333, + -0.00347199,0.000189928,0.485508,0.0769231, + -0.00295841,0.00014956,0.559616,0.0714286, + -0.0025509,0.000119868,0.628609,0.0666667, + -0.00222213,0.0000975436,0.693147, + 0.0625,-0.00195305,0.0000804357}; + + +float16_t logf16_scalar(float16_t x) +{ + int16_t i = arm_typecast_s16_f16(x); + + int32_t vecExpUnBiased = (i >> 10) - 15; + i = i - (vecExpUnBiased << 10); + float16_t vecTmpFlt1 = arm_typecast_f16_s16(i); + + float16_t *lut; + int n; + float16_t tmp,v; + + tmp = ((_Float16)vecTmpFlt1 - 1.0f16) * (1 << NB_DIV_LOGF16); + n = (int)floor((double)tmp); + v = (_Float16)tmp - (_Float16)n; + + lut = lut_logf16 + n * (1+NB_DEG_LOGF16); + + float16_t res = lut[NB_DEG_LOGF16-1]; + for(int j=NB_DEG_LOGF16-2; j >=0 ; j--) + { + res = (_Float16)lut[j] + (_Float16)v * (_Float16)res; + } + + res = (_Float16)res + 0.693147f16 * (_Float16)vecExpUnBiased; + + + return(res); +} + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + + +float16x8_t vlogq_lut_f16(float16x8_t vecIn) +{ + int16x8_t i = vreinterpretq_s16_f16(vecIn); + + int16x8_t vecExpUnBiased = vsubq_n_s16(vshrq_n_s16(i,10), 15); + i = vsubq_s16(i,vshlq_n_s16(vecExpUnBiased,10)); + float16x8_t vecTmpFlt1 = vreinterpretq_f16_s16(i); + + + float16x8_t lutV; + int16x8_t n; + int16x8_t offset; + + float16x8_t tmp,v,res; + + tmp = vmulq_n_f16(vsubq_n_f16(vecTmpFlt1,1.0f16),(_Float16)(1 << NB_DIV_LOGF16)); + + n = vcvtq_s16_f16(tmp); + v = vsubq_f16(tmp,vcvtq_f16_s16(n)); + + + offset = vmulq_n_s16(n,(1+NB_DEG_LOGF16)); + offset = vaddq_n_s16(offset,NB_DEG_LOGF16-1); + + res = vldrhq_gather_shifted_offset_f16(lut_logf16,(uint16x8_t)offset); + offset = vsubq_n_s16(offset,1); + + for(int j=NB_DEG_LOGF16-2; j >=0 ; j--) + { + lutV = vldrhq_gather_shifted_offset_f16(lut_logf16,(uint16x8_t)offset); + res = vfmaq_f16(lutV,v,res); + offset = vsubq_n_s16(offset,1); + + } + + res = vfmaq_n_f16(res,vcvtq_f16_s16(vecExpUnBiased),0.693147f16); + + + return(res); + +} + +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +void arm_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_lut_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf16_scalar(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + + + +/** + @} end of vlog group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c new file mode 100644 index 0000000..7c59553 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c @@ -0,0 +1,123 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + + +/** + @ingroup groupFastMath + */ + + +/** + @defgroup vlog Vector Log + + Compute the log values of a vector of samples. + + */ + +/** + @addtogroup vlog + @{ + */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM) || defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" +#endif + +void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_f32(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q_f32(pSrc); + dst = vlogq_f32(src); + vst1q_f32(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else + blkCnt = blockSize; +#endif +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vlog group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c new file mode 100644 index 0000000..fae58bb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c @@ -0,0 +1,55 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f64.c + * Description: Fast vectorized log + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +void arm_vlog_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = log(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c new file mode 100644 index 0000000..15d332e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c @@ -0,0 +1,268 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_q15 + * Description: Q15 vector log + * + * $Date: 19 July 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + + +#define LOG_Q15_ACCURACY 15 + +/* Bit to represent the normalization factor + It is Ceiling[Log2[LOG_Q15_ACCURACY]] of the previous value. + The Log2 algorithm is assuming that the value x is + 1 <= x < 2. + + But input value could be as small a 2^-LOG_Q15_ACCURACY + which would give an integer part of -15. +*/ +#define LOG_Q15_INTEGER_PART 4 + +/* 2.0 in q14 */ +#define LOQ_Q15_THRESHOLD (1u << LOG_Q15_ACCURACY) + +/* HALF */ +#define LOQ_Q15_Q16_HALF LOQ_Q15_THRESHOLD +#define LOQ_Q15_Q14_HALF (LOQ_Q15_Q16_HALF >> 2) + + +/* 1.0 / Log2[Exp[1]] in q15 */ +#define LOG_Q15_INVLOG2EXP 0x58b9u + + +/* Clay Turner algorithm */ +static uint16_t arm_scalar_log_q15(uint16_t src) +{ + int i; + + int16_t c = __CLZ(src)-16; + int16_t normalization=0; + + /* 0.5 in q11 */ + uint16_t inc = LOQ_Q15_Q16_HALF >> (LOG_Q15_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint16_t x; + + /* q11 */ + uint16_t y=0; + + /* q11 */ + int16_t tmp; + + + /* Normalize and convert to q14 format */ + x = src; + if ((c-1) < 0) + { + x = x >> (1-c); + } + else + { + x = x << (c-1); + } + normalization = c; + + + + /* Compute the Log2. Result is in q11 instead of q16 + because we know 0 <= y < 1.0 but + we want a result allowing to do a + product on int16 rather than having to go + through int32 + */ + for(i = 0; i < LOG_Q15_ACCURACY ; i++) + { + x = (((int32_t)x*x)) >> (LOG_Q15_ACCURACY - 1); + + if (x >= LOQ_Q15_THRESHOLD) + { + y += inc ; + x = x >> 1; + } + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + //tmp = y - ((int32_t)normalization << (LOG_Q15_ACCURACY + 1)); + tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + + /* q4.11 */ + y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + + return(y); + +} + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + +q15x8_t vlogq_q15(q15x8_t src) +{ + + int i; + + int16x8_t c = vclzq_s16(src); + int16x8_t normalization = c; + + + /* 0.5 in q11 */ + uint16_t inc = LOQ_Q15_Q16_HALF >> (LOG_Q15_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint16x8_t x; + + + /* q11 */ + uint16x8_t y = vdupq_n_u16(0); + + + /* q11 */ + int16x8_t vtmp; + + + mve_pred16_t p; + + /* Normalize and convert to q14 format */ + + + vtmp = vsubq_n_s16(c,1); + x = vshlq_u16((uint16x8_t)src,vtmp); + + + /* Compute the Log2. Result is in q11 instead of q16 + because we know 0 <= y < 1.0 but + we want a result allowing to do a + product on int16 rather than having to go + through int32 + */ + for(i = 0; i < LOG_Q15_ACCURACY ; i++) + { + x = vmulhq_u16(x,x); + x = vshlq_n_u16(x,2); + + + p = vcmphiq_u16(x,vdupq_n_u16(LOQ_Q15_THRESHOLD)); + y = vaddq_m_n_u16(y, y,inc,p); + x = vshrq_m_n_u16(x,x,1,p); + + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + // tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + vtmp = vshlq_n_s16(normalization,LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART); + vtmp = vsubq_s16((int16x8_t)y,vtmp); + + + + /* q4.11 */ + // y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + vtmp = vqdmulhq_n_s16(vtmp,LOG_Q15_INVLOG2EXP); + + return(vtmp); +} +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief q15 vector of log values. + @param[in] pSrc points to the input vector in q15 + @param[out] pDst points to the output vector in q4.11 + @param[in] blockSize number of samples in each vector + @return none + + */ + +void arm_vlog_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + q15x8_t src; + q15x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_q15(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; + #else + blkCnt = blockSize; + #endif + + while (blkCnt > 0U) + { + *pDst++ = arm_scalar_log_q15(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vlog group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c new file mode 100644 index 0000000..5be5b72 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c @@ -0,0 +1,262 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_q31 + * Description: Q31 vector log + * + * $Date: 19 July 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#define LOG_Q31_ACCURACY 31 + +/* Bit to represent the normalization factor + It is Ceiling[Log2[LOG_Q31_ACCURACY]] of the previous value. + The Log2 algorithm is assuming that the value x is + 1 <= x < 2. + + But input value could be as small a 2^-LOG_Q31_ACCURACY + which would give an integer part of -31. +*/ +#define LOG_Q31_INTEGER_PART 5 + +/* 2.0 in Q30 */ +#define LOQ_Q31_THRESHOLD (1u << LOG_Q31_ACCURACY) + +/* HALF */ +#define LOQ_Q31_Q32_HALF LOQ_Q31_THRESHOLD +#define LOQ_Q31_Q30_HALF (LOQ_Q31_Q32_HALF >> 2) + + +/* 1.0 / Log2[Exp[1]] in Q31 */ +#define LOG_Q31_INVLOG2EXP 0x58b90bfbuL + +/* Clay Turner algorithm */ +static uint32_t arm_scalar_log_q31(uint32_t src) +{ + int32_t i; + + int32_t c = __CLZ(src); + int32_t normalization=0; + + /* 0.5 in q26 */ + uint32_t inc = LOQ_Q31_Q32_HALF >> (LOG_Q31_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint32_t x; + + /* q26 */ + uint32_t y=0; + + /* q26 */ + int32_t tmp; + + + /* Normalize and convert to q30 format */ + x = src; + if ((c-1) < 0) + { + x = x >> (1-c); + } + else + { + x = x << (c-1); + } + normalization = c; + + /* Compute the Log2. Result is in q26 + because we know 0 <= y < 1.0 but + do not want to use q32 to allow + following computation with less instructions. + */ + for(i = 0; i < LOG_Q31_ACCURACY ; i++) + { + x = ((int64_t)x*x) >> (LOG_Q31_ACCURACY - 1); + + if (x >= LOQ_Q31_THRESHOLD) + { + y += inc ; + x = x >> 1; + } + inc = inc >> 1; + } + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q26 */ + tmp = (int32_t)y - (normalization << (LOG_Q31_ACCURACY - LOG_Q31_INTEGER_PART)); + + + /* q5.26 */ + y = ((int64_t)tmp * LOG_Q31_INVLOG2EXP) >> 31; + + + + return(y); + +} + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + +q31x4_t vlogq_q31(q31x4_t src) +{ + + int32_t i; + + int32x4_t c = vclzq_s32(src); + int32x4_t normalization = c; + + + /* 0.5 in q11 */ + uint32_t inc = LOQ_Q31_Q32_HALF >> (LOG_Q31_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint32x4_t x; + + + /* q11 */ + uint32x4_t y = vdupq_n_u32(0); + + + /* q11 */ + int32x4_t vtmp; + + + mve_pred16_t p; + + /* Normalize and convert to q14 format */ + + + vtmp = vsubq_n_s32(c,1); + x = vshlq_u32((uint32x4_t)src,vtmp); + + + /* Compute the Log2. Result is in Q26 + because we know 0 <= y < 1.0 but + do not want to use Q32 to allow + following computation with less instructions. + */ + for(i = 0; i < LOG_Q31_ACCURACY ; i++) + { + x = vmulhq_u32(x,x); + x = vshlq_n_u32(x,2); + + + p = vcmphiq_u32(x,vdupq_n_u32(LOQ_Q31_THRESHOLD)); + y = vaddq_m_n_u32(y, y,inc,p); + x = vshrq_m_n_u32(x,x,1,p); + + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + // tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + vtmp = vshlq_n_s32(normalization,LOG_Q31_ACCURACY - LOG_Q31_INTEGER_PART); + vtmp = vsubq_s32((int32x4_t)y,vtmp); + + + + /* q4.11 */ + // y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + vtmp = vqdmulhq_n_s32(vtmp,LOG_Q31_INVLOG2EXP); + + return(vtmp); +} +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief q31 vector of log values. + @param[in] pSrc points to the input vector in q31 + @param[out] pDst points to the output vector q5.26 + @param[in] blockSize number of samples in each vector + @return none + + */ +void arm_vlog_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + q31x4_t src; + q31x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_q31(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; + #else + blkCnt = blockSize; + #endif + + while (blkCnt > 0U) + { + *pDst++=arm_scalar_log_q31(*pSrc++); + + blkCnt--; + } + +} + +/** + @} end of vlog group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c new file mode 100644 index 0000000..64d61f1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c @@ -0,0 +1,98 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_init_q31.c + * Description: High precision Q31 Biquad cascade filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade 32x64 filter. + @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array and size of each state variable is 1.63 format. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the state array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1_32x64 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c new file mode 100644 index 0000000..1111311 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c @@ -0,0 +1,811 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_q31.c + * Description: High precision Q31 Biquad cascade filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter + + This function implements a high precision Biquad cascade filter which operates on + Q31 data values. The filter coefficients are in 1.31 format and the state variables + are in 1.63 format. The double precision state variables reduce quantization noise + in the filter and provide a cleaner output. + These filters are particularly useful when implementing filters in which the + singularities are close to the unit circle. This is common for low pass or high + pass filters with very low cutoff frequencies. + + The function operates on blocks of input and output data + and each call to the function processes blockSize samples through + the filter. pSrc and pDst points to input and output arrays + containing blockSize Q31 values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages + with the coefficients for one of the stages configured as a first order filter + (b2=0 and a2=0). + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. + The state variables are arranged in the array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values of data in 1.63 format. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Function + There is also an associated initialization function which performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the filter instance structure use + 
+      arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied which is described in detail below. + @par Fixed-Point Behavior + Care must be taken while using Biquad Cascade 32x64 filter function. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par + Filter coefficients are represented as fractional values and + restricted to lie in the range [-1 +1). + The processing function has an additional scaling parameter postShift + which allows the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the Coefficient array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + @par + The second thing to keep in mind is the gain through the filter. + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the + filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 + and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 + or the input signal must be scaled down so that the combination of input and filter are never overflowed. + @par + The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. + This is described in the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade 32x64 filter. + @param[in] S points to an instance of the high precision Q31 Biquad cascade filter + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Details + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @par + Two related functions are provided in the CMSIS DSP library. + - \ref arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. + - \ref arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +static void arm_biquad_cas_df1_32x64_q31_scalar(const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} + +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31x4_t vecCoef = { 0 }, vecIn; + q63_t acc; + + if (blockSize <= 3) + { + arm_biquad_cas_df1_32x64_q31_scalar(S,pSrc,pDst,blockSize); + } + else + { + do + { + uint32_t i; + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + vecCoef[0] = 0; + vecCoef[1] = b2; + vecCoef[2] = b1; + vecCoef[3] = b0; + /* + * Reading the state values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* + * append history with initial samples + */ + q31_t hist[6]; + hist[0] = 0; + hist[1] = Xn2; + hist[2] = Xn1; + hist[3] = pIn[0]; + hist[4] = pIn[1]; + hist[5] = pIn[2]; + + const q31_t *pIn1 = hist; + q31x4_t vecIn0 = *(q31x4_t *) & pIn[0]; + q31x4_t vecIn1 = *(q31x4_t *) & pIn[1]; + q31x4_t vecIn2 = *(q31x4_t *) & pIn[2]; + + i = 3; + do + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + vecIn = vld1q(pIn1); + pIn1 += 1; + Yn1 = vmlaldavaq(Yn1, vecIn, vecCoef); + Yn1 = asrl(Yn1, -shift); + /* + * Store the output in the destination buffer in 1.31 format. + */ + *pOut++ = (q31_t) (Yn1 >> 32); + } + while (--i); + + sample = blockSize - 3; + pIn1 = pIn + 3; + + i = sample / 4; + while (i > 0U) + { + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + vecIn = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + /* + * Store the output in the destination buffer in 1.31 format. + */ + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + vecIn0 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn2, vecCoef); + vecIn1 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn, vecCoef); + vecIn2 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * Decrement the loop counter + */ + i--; + } + /* + * save input state + */ + Xn2 = vecIn[2]; + Xn1 = vecIn[3]; + + int loopRemainder = blockSize - 3 - 4 * ((blockSize - 3) / 4); + if (loopRemainder == 1) + { + /* + * remainder + */ + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn0[2]; + Xn1 = vecIn0[3]; + + } + else if (loopRemainder == 2) + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn1[2]; + Xn1 = vecIn1[3]; + + } + else if (loopRemainder == 3) + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn2, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn2[2]; + Xn1 = vecIn2[3]; + + } + + /* + * The first stage output is given as input to the second stage. + */ + pIn = pDst; + /* + * Reset to destination buffer working pointer + */ + pOut = pDst; + /* + * Store the updated state variables back into the pState array + */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + } + while (--stage); + } +} +#else +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output value that is being computed and stored in destination buffer + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut = acc_h; + + /* Read the second input into Xn2, to reuse the value */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc += b1 * x[n-1] */ + acc = (q63_t) Xn * b1; + + /* acc = b0 * x[n] */ + acc += (q63_t) Xn2 * b0; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn1 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Read the third input into Xn1, to reuse the value */ + Xn1 = *pIn++; + + /* The result is converted to 1.31 */ + /* Store the output in the destination buffer. */ + *(pOut + 1U) = acc_h; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn1 * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn2 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 2U) = acc_h; + + /* Read the fourth input into Xn, to reuse the value */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 3U) = acc_h; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* update output pointer */ + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1_32x64 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c new file mode 100644 index 0000000..c38e37b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c @@ -0,0 +1,495 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_f16.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* pState pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float16_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float16_t X0, X1, X2, X3; /* temporary input */ + float16_t X4, X5, X6, X7 = 0; /* temporary input */ + _Float16 lastX, lastY; /* X,Y history for tail handling */ + f16x8_t coeffs; + f16x8_t accVec; /* accumultor vector */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* + * Reading the pState values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize >> 3U; + + /* + * First part of the processing with loop unrolling. Compute 8 outputs at a time. + */ + while (sample > 0U) + { + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + X4 = *pIn++; + X5 = *pIn++; + X6 = *pIn++; + X7 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X7); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X6); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, X5); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, X4); + + coeffs = vld1q(&pCoeffs[32]); + accVec = vfmaq(accVec, coeffs, X3); + + coeffs = vld1q(&pCoeffs[40]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[48]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[56]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[64]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[72]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[80]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[88]); + accVec = vfmaq(accVec, coeffs, Yn2); + /* + * Store the result in the accumulator in the destination buffer. + */ + vst1q(pOut, accVec); + pOut += 8; + + /* + * update recurrence + */ + Xn1 = X7; + Xn2 = X6; + Yn1 = vgetq_lane(accVec, 7); + Yn2 = vgetq_lane(accVec, 6); + /* + * decrement the loop counter + */ + sample--; + } + + /* + * If the blockSize is not a multiple of 8, + * compute any remaining output samples here. + */ + sample = blockSize & 0x7U; + if (sample) + { + /* save previous X, Y for modulo 1 length case */ + lastX = X7; + lastY = Yn1; + + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + X4 = *pIn++; + X5 = *pIn++; + X6 = *pIn++; + X7 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X7); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X6); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, X5); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, X4); + + coeffs = vld1q(&pCoeffs[32]); + accVec = vfmaq(accVec, coeffs, X3); + + coeffs = vld1q(&pCoeffs[40]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[48]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[56]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[64]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[72]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[80]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[88]); + accVec = vfmaq(accVec, coeffs, Yn2); + + switch(sample) + { + case 1: + *pOut++ = vgetq_lane(accVec, 0); + Xn1 = X0; + Xn2 = lastX; + Yn1 = vgetq_lane(accVec, 0); + Yn2 = lastY; + break; + case 2: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + Xn1 = X1; + Xn2 = X0; + Yn1 = vgetq_lane(accVec, 1); + Yn2 = vgetq_lane(accVec, 0); + break; + case 3: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + Xn1 = X2; + Xn2 = X1; + Yn1 = vgetq_lane(accVec, 2); + Yn2 = vgetq_lane(accVec, 1); + break; + + case 4: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + Xn1 = X3; + Xn2 = X2; + Yn1 = vgetq_lane(accVec, 3); + Yn2 = vgetq_lane(accVec, 2); + break; + + case 5: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + Xn1 = X4; + Xn2 = X3; + Yn1 = vgetq_lane(accVec, 4); + Yn2 = vgetq_lane(accVec, 3); + break; + + case 6: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + *pOut++ = vgetq_lane(accVec, 5); + Xn1 = X5; + Xn2 = X4; + Yn1 = vgetq_lane(accVec, 5); + Yn2 = vgetq_lane(accVec, 4); + break; + + case 7: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + *pOut++ = vgetq_lane(accVec, 5); + *pOut++ = vgetq_lane(accVec, 6); + Xn1 = X6; + Xn2 = X5; + Yn1 = vgetq_lane(accVec, 6); + Yn2 = vgetq_lane(accVec, 5); + break; + } + } + /* + * Store the updated state variables back into the pState array + */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + pCoeffs += sizeof(arm_biquad_mod_coef_f16) / sizeof(float16_t); + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent numStages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset the output pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} + +#else +void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* pState pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + _Float16 Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +/** + @} end of BiquadCascadeDF1 group + */ +#endif /* #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#endif /*#if defined(ARM_FLOAT16_SUPPORTED)*/ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c new file mode 100644 index 0000000..931a6f0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c @@ -0,0 +1,688 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_f32.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure + + This set of functions implements arbitrary order recursive (IIR) filters. + The filters are implemented as a cascade of second order Biquad sections. + The functions support Q15, Q31 and floating-point data types. + Fast version of Q15 and Q31 also available. + + The functions operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 + must be negated when used with the CMSIS DSP Library. + + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ + @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Init Function + There is also an associated initialization function for each data type. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+      arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par Scaling of coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift + which allow the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the pCoeffs array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + + @par Filter gain + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed. + + @par Overflow and saturation + For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t lastX, lastY; /* X,Y history for tail handling */ + float32_t X0, X1, X2, X3 = 0; /* temporary input */ + f32x4_t coeffs; + f32x4_t accVec; /* accumultor vector */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* + * Reading the pState values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize >> 2U; + + /* + * First part of the processing with loop unrolling. Compute 4 outputs at a time. + * second loop below computes the remaining 1 to 3 samples. + */ + while (sample > 0U) + { + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X3); + + coeffs = vld1q(&pCoeffs[4]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[12]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[20]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[28]); + accVec = vfmaq(accVec, coeffs, Yn2); + /* + * Store the result in the accumulator in the destination buffer. + */ + vst1q(pOut, accVec); + pOut += 4; + + /* + * update recurrence + */ + Xn1 = X3; + Xn2 = X2; + Yn1 = vgetq_lane(accVec, 3); + Yn2 = vgetq_lane(accVec, 2); + /* + * decrement the loop counter + */ + sample--; + } + + /* + * If the blockSize is not a multiple of 4, + * compute any remaining output samples here. + */ + sample = blockSize & 0x3U; + if (sample) + { + /* save previous X, Y for modulo 1 length case */ + lastX = X3; + lastY = Yn1; + + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X3); + + coeffs = vld1q(&pCoeffs[4]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[12]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[20]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[28]); + accVec = vfmaq(accVec, coeffs, Yn2); + + if (sample == 1) + { + *pOut++ = vgetq_lane(accVec, 0); + Xn1 = X0; + Xn2 = lastX; + Yn1 = vgetq_lane(accVec, 0); + Yn2 = lastY; + } + else if (sample == 2) + { + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + Xn1 = X1; + Xn2 = X0; + Yn1 = vgetq_lane(accVec, 1); + Yn2 = vgetq_lane(accVec, 0); + } + else + { + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + Xn1 = X2; + Xn2 = X1; + Yn1 = vgetq_lane(accVec, 2); + Yn2 = vgetq_lane(accVec, 1); + } + } + /* + * Store the updated state variables back into the pState array + */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + pCoeffs += sizeof(arm_biquad_mod_coef_f32) / sizeof(float32_t); + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent numStages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset the output pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + + uint32_t sample, stage = S->numStages; /* loop counters */ + + float32x4_t Xn; + float32x2_t Yn; + float32x2_t a; + float32x4_t b; + + float32x4_t x,tmp; + float32x2_t t; + float32x2x2_t y; + + float32_t Xns; + + while (stage > 0U) + { + /* Reading the coefficients */ + Xn = vdupq_n_f32(0.0f); + + Xn = vsetq_lane_f32(pState[0],Xn,2); + Xn = vsetq_lane_f32(pState[1],Xn,3); + Yn = vset_lane_f32(pState[2],Yn,0); + Yn = vset_lane_f32(pState[3],Yn,1); + + b = vld1q_f32(pCoeffs); + b = vrev64q_f32(b); + b = vcombine_f32(vget_high_f32(b), vget_low_f32(b)); + + a = vld1_f32(pCoeffs + 3); + a = vrev64_f32(a); + b = vsetq_lane_f32(0.0f,b,0); + pCoeffs += 5; + + /* Reading the pState values */ + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first 4 inputs */ + x = vld1q_f32(pIn); + + pIn += 4; + + tmp = vextq_f32(Xn, x, 1); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + tmp = vextq_f32(Xn, x, 2); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[0] = Yn; + + tmp = vextq_f32(Xn, x, 3); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + Xn = x; + t = vmul_f32(vget_high_f32(b), vget_high_f32(Xn)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(Xn)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[1] = Yn; + + tmp = vcombine_f32(y.val[0], y.val[1]); + + /* Store the 4 outputs and increment the pointer */ + vst1q_f32(pOut, tmp); + pOut += 4; + + /* Decrement the loop counter */ + sample--; + } + + + /* If the block size is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + sample = blockSize & 0x3U; + + while (sample > 0U) + { + /* Read the input */ + Xns = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (vgetq_lane_f32(b, 1) * vgetq_lane_f32(Xn, 2)) + + (vgetq_lane_f32(b, 2) * vgetq_lane_f32(Xn, 3)) + + (vgetq_lane_f32(b, 3) * Xns) + + (vget_lane_f32(a, 0) * vget_lane_f32(Yn, 0)) + + (vget_lane_f32(a, 1) * vget_lane_f32(Yn, 1)); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn = vsetq_lane_f32(vgetq_lane_f32(Xn, 3),Xn,2); + Xn = vsetq_lane_f32(Xns,Xn,3); + Yn = vset_lane_f32(vget_lane_f32(Yn, 1),Yn,0); + Yn = vset_lane_f32(acc,Yn,1); + + /* Decrement the loop counter */ + sample--; + + } + + vst1q_f32(pState,vcombine_f32((vget_high_f32(Xn)),(Yn))); + pState += 4; + /* Store the updated state variables back into the pState array */ + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + } +} + +#else +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c new file mode 100644 index 0000000..f6d7243 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c @@ -0,0 +1,254 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q15.c + * Description: Fast processing function for the Q15 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). + The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_q15() for a slower implementation of this function + which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q15() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc; /* Accumulator */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia (&pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia (&pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia (&pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 2 outputs at a time */ + sample = blockSize >> 1U; + + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia (&pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x1U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent (numStages - 1) occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia(&pState, state_in); + write_q15x2_ia(&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); +} + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c new file mode 100644 index 0000000..1ddff4d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c @@ -0,0 +1,300 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q31.c + * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function + arm_biquad_cascade_df1_init_q31() to initialize filter structure. + @remark + Refer to \ref arm_biquad_cascade_df1_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q31() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc = 0; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variables acc ... acc3 hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/ + mult_32x32_keep32_R(acc, b1, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b0, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the second input */ + Xn2 = *(pIn + 1U); + + /* Store the output in the destination buffer. */ + *pOut = Yn2; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn2); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn1); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Read the third input */ + Xn1 = *(pIn + 2U); + + /* Store the output in the destination buffer. */ + *(pOut + 1U) = Yn1; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn2); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the forth input */ + Xn = *(pIn + 3U); + + /* Store the output in the destination buffer. */ + *(pOut + 2U) = Yn2; + pIn += 4U; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + Xn2 = Xn1; + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Xn1 = Xn */ + Xn1 = Xn; + + /* Store the output in the destination buffer. */ + *(pOut + 3U) = Yn1; + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x3U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc = acc << shift; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c new file mode 100644 index 0000000..0cbe6f6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c @@ -0,0 +1,170 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_f16.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type arm_biquad_mod_coef_f16. + So, its total size is 96*numStages float16_t elements. + + The initialization function which must be used is arm_biquad_cascade_df1_mve_init_f16. + */ + + +void arm_biquad_cascade_df1_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +/* + +The computation of the coefficients is done in float32 otherwise the +resulting filter is too different from the expected one. + +*/ +static void generateCoefsFastBiquadF16(float16_t b0, float16_t b1, float16_t b2, float16_t a1, float16_t a2, + arm_biquad_mod_coef_f16 * newCoef) +{ + float32_t coeffs[8][12] = { + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, (float32_t)a1, (float32_t)a2}, + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, (float32_t)a2, 0.0f}, + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {(float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f} + }; + + for (int i = 0; i < 12; i++) + { + coeffs[1][i] += ((float32_t)a1 * coeffs[0][i]); + coeffs[2][i] += ((float32_t)a1 * coeffs[1][i]) + ((float32_t)a2 * coeffs[0][i]); + coeffs[3][i] += ((float32_t)a1 * coeffs[2][i]) + ((float32_t)a2 * coeffs[1][i]); + coeffs[4][i] += ((float32_t)a1 * coeffs[3][i]) + ((float32_t)a2 * coeffs[2][i]); + coeffs[5][i] += ((float32_t)a1 * coeffs[4][i]) + ((float32_t)a2 * coeffs[3][i]); + coeffs[6][i] += ((float32_t)a1 * coeffs[5][i]) + ((float32_t)a2 * coeffs[4][i]); + coeffs[7][i] += ((float32_t)a1 * coeffs[6][i]) + ((float32_t)a2 * coeffs[5][i]); + + /* + * transpose + */ + newCoef->coeffs[i][0] = (float16_t) coeffs[0][i]; + newCoef->coeffs[i][1] = (float16_t) coeffs[1][i]; + newCoef->coeffs[i][2] = (float16_t) coeffs[2][i]; + newCoef->coeffs[i][3] = (float16_t) coeffs[3][i]; + newCoef->coeffs[i][4] = (float16_t) coeffs[4][i]; + newCoef->coeffs[i][5] = (float16_t) coeffs[5][i]; + newCoef->coeffs[i][6] = (float16_t) coeffs[6][i]; + newCoef->coeffs[i][7] = (float16_t) coeffs[7][i]; + + } +} + +void arm_biquad_cascade_df1_mve_init_f16(arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + arm_biquad_mod_coef_f16 * pCoeffsMod, + float16_t * pState) +{ + arm_biquad_cascade_df1_init_f16(S, numStages, (float16_t *)pCoeffsMod, pState); + + /* Generate SIMD friendly modified coefs */ + for (int i = 0; i < numStages; i++) + { + generateCoefsFastBiquadF16(pCoeffs[0], pCoeffs[1], pCoeffs[2], pCoeffs[3], pCoeffs[4], pCoeffsMod); + pCoeffs += 5; + pCoeffsMod++; + } +} + +#endif + +/** + @} end of BiquadCascadeDF1 group + */ +#endif /* #if defined(ARMfloat16_t_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c new file mode 100644 index 0000000..91b079b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c @@ -0,0 +1,150 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_f32.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type arm_biquad_mod_coef_f32. + So, its total size is 32*numStages float32_t elements. + + The initialization function which must be used is arm_biquad_cascade_df1_mve_init_f32. + */ + + +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +static void generateCoefsFastBiquadF32(float32_t b0, float32_t b1, float32_t b2, float32_t a1, float32_t a2, + arm_biquad_mod_coef_f32 * newCoef) +{ + float32_t coeffs[4][8] = { + {0, 0, 0, b0, b1, b2, a1, a2}, + {0, 0, b0, b1, b2, 0, a2, 0}, + {0, b0, b1, b2, 0, 0, 0, 0}, + {b0, b1, b2, 0, 0, 0, 0, 0}, + }; + + for (int i = 0; i < 8; i++) + { + coeffs[1][i] += a1 * coeffs[0][i]; + coeffs[2][i] += a1 * coeffs[1][i] + a2 * coeffs[0][i]; + coeffs[3][i] += a1 * coeffs[2][i] + a2 * coeffs[1][i]; + + /* + * transpose + */ + newCoef->coeffs[i][0] = (float32_t) coeffs[0][i]; + newCoef->coeffs[i][1] = (float32_t) coeffs[1][i]; + newCoef->coeffs[i][2] = (float32_t) coeffs[2][i]; + newCoef->coeffs[i][3] = (float32_t) coeffs[3][i]; + } +} + +void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState) +{ + arm_biquad_cascade_df1_init_f32(S, numStages, (float32_t *)pCoeffsMod, pState); + + /* Generate SIMD friendly modified coefs */ + for (int i = 0; i < numStages; i++) + { + generateCoefsFastBiquadF32(pCoeffs[0], pCoeffs[1], pCoeffs[2], pCoeffs[3], pCoeffs[4], pCoeffsMod); + pCoeffs += 5; + pCoeffsMod++; + } +} +#endif + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c new file mode 100644 index 0000000..8f3020e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c @@ -0,0 +1,100 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q15.c + * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q15 Biquad cascade filter. + @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 6*numStages values. + The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4. + @par + The state variables are stored in the array pState. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c new file mode 100644 index 0000000..0cc7acc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c @@ -0,0 +1,99 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q31.c + * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade filter. + @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c new file mode 100644 index 0000000..df7d114 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c @@ -0,0 +1,622 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q15.c + * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter. + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the location where the output result is written + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. + Finally, the result is saturated to 1.15 format. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* input pointer initialization */ + q15_t *pOut = pDst; /* output pointer initialization */ + int shift; + uint32_t sample, stages = S->numStages; /* loop counters */ + int postShift = S->postShift; + q15x8_t bCoeffs0, bCoeffs1, bCoeffs2, bCoeffs3; /* Coefficients vector */ + q15_t *pState = S->pState; /* pState pointer initialization */ + q15x8_t inVec0; + int64_t acc; + const q15_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t out, out1; + + shift = (15 - postShift) - 32; + + do { + q15_t a2 = pCoeffs[5]; + q15_t a1 = pCoeffs[4]; + + bCoeffs0 = vdupq_n_s16(0); + bCoeffs0[0] = pCoeffs[3]; // b2 + bCoeffs0[1] = pCoeffs[2]; // b1 + bCoeffs0[2] = pCoeffs[0]; // b0 + + uint32_t zero = 0; + bCoeffs1 = bCoeffs0; + bCoeffs1 = vshlcq_s16(bCoeffs1, &zero, 16); + + bCoeffs2 = bCoeffs1; + bCoeffs2 = vshlcq_s16(bCoeffs2, &zero, 16); + + bCoeffs3 = bCoeffs2; + bCoeffs3 = vshlcq_s16(bCoeffs3, &zero, 16); + + bCoeffs0[6] = a2; + bCoeffs0[7] = a1; + bCoeffs1[7] = a2; + bCoeffs1[6] = a1; + + bCoeffs2 = + vsetq_lane_s32(vgetq_lane_s32((q31x4_t) bCoeffs0, 3), (q31x4_t) bCoeffs2, 3); + bCoeffs3 = + vsetq_lane_s32(vgetq_lane_s32((q31x4_t) bCoeffs1, 3), (q31x4_t) bCoeffs3, 3); + + + /* 2 first elements are garbage, will be updated with history */ + inVec0 = vld1q(pIn - 2); + pIn += 2; + + inVec0[0] = pState[1]; + inVec0[1] = pState[0]; + inVec0[6] = pState[3]; + inVec0[7] = pState[2]; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0[6] = out1; + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0[7] = out; + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + + inVec0[6] = out1; + acc = vmlaldavq(bCoeffs3, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + /* + * main loop + */ + sample = (blockSize - 4) >> 2U; + /* preload (efficient scheduling) */ + inVec0 = vld1q(pIn); + pIn += 4; + + /* + * Compute 4 outputs at a time. + */ + while (sample > 0U) { + + inVec0[6] = out1; + inVec0[7] = out; + + /* store */ + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* + * in { x0 x1 x2 x3 x4 x5 yn2 yn1 } + * x + * bCoeffs0 { b2 b1 b0 0 0 0 a2 a1 } + * + */ + acc = vmlaldavq(bCoeffs0, inVec0); + /* shift + saturate to 16 bit */ + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + /* + * in { x0 x1 x2 x3 x4 x5 y0 yn1 } + * x + * bCoeffs1 { 0 b2 b1 b0 0 0 a1 a2 } + */ + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + + inVec0[7] = out; + /* + * in { x0 x1 x2 x3 x4 x5 y0 yp1 } + * x + * bCoeffs2 { 0 0 b2 b1 b0 0 a2 a1 } + */ + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + /* + * in { x0 x1 x2 x3 x4 x5 y0 yp1 } + * x + * bCoeffs2 { 0 0 0 b2 b1 b0 a1 a2 } + */ + acc = vmlaldavq(bCoeffs3, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0 = vld1q(pIn); + pIn += 4; + + /* decrement the loop counter */ + sample--; + } + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* + * Tail handling + */ + int32_t loopRemainder = blockSize & 3; + + if (loopRemainder == 3) { + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + inVec0[7] = out; + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + *pOut++ = (q15_t) out1; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 4); + pState[1] = vgetq_lane_s16(inVec0, 3); + pState[3] = out; + pState[2] = out1; + + } else if (loopRemainder == 2) { + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 3); + pState[1] = vgetq_lane_s16(inVec0, 2); + pState[3] = out1; + pState[2] = out; + } else if (loopRemainder == 1) { + + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + *pOut++ = (q15_t) out1; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 2); + pState[1] = vgetq_lane_s16(inVec0, 1); + pState[3] = out; + pState[2] = out1; + + + } else { + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 1); + pState[1] = vgetq_lane_s16(inVec0, 0); + pState[3] = out1; + pState[2] = out; + } + + pState += 4; + pCoeffs += 6; + + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent stages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset to destination pointer + */ + pOut = pDst; + } + while (--stages); +} +#else +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + q31_t acc_l, acc_h; + q63_t acc; /* Accumulator */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + int32_t uShift = (32 - lShift); + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + sample = blockSize >> 1U; + + /* First part of the processing with loop unrolling. Compute 2 outputs at a time. + ** a second loop below computes the remaining 1 sample. */ + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* If the blockSize is not a multiple of 2, compute any remaining output samples here. + ** No loop unrolling is used. */ + + if ((blockSize & 0x1U) != 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + } + + /* The first stage goes from the input wire to the output wire. */ + /* Subsequent numStages occur in-place in the output wire */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia (&pState, state_in); + write_q15x2_ia (&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); + +#else + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q31_t) b0 *Xn; + + /* acc += b1 * x[n-1] */ + acc += (q31_t) b1 *Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q31_t) b2 *Xn2; + /* acc += a1 * y[n-1] */ + acc += (q31_t) a1 *Yn1; + /* acc += a2 * y[n-2] */ + acc += (q31_t) a2 *Yn2; + + /* The result is converted to 1.31 */ + acc = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c new file mode 100644 index 0000000..ca2fce9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c @@ -0,0 +1,514 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q31.c + * Description: Processing function for the Q31 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter. + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + int shift; + uint32_t stages = S->numStages; /* loop counters */ + int postShift = S->postShift; + q31x4_t b0Coeffs, b1Coeffs, a0Coeffs, a1Coeffs; /* Coefficients vector */ + q31x4_t stateVec = { 0 }; + q31_t *pState = S->pState; /* pState pointer initialization */ + q31x4_t inVec0; + int64_t acc; + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t out, out1; + + + shift = (postShift + 1 + 8); + + do { + /* + * Reading the coefficients + * generates : + * Fwd0 { b2 b1 b0 0 } + * Fwd1 { 0 b2 b1 b0 } + * Bwd0 { 0 0 a2 a1 } + * Bwd0 { 0 0 a1 a2 } + * (can be moved in init) + */ + b0Coeffs = vdupq_n_s32(0); + a0Coeffs = vdupq_n_s32(0); + + b0Coeffs[0] = pCoeffs[2]; // b2 + b0Coeffs[1] = pCoeffs[1]; // b1 + b0Coeffs[2] = pCoeffs[0]; // b0 + + b1Coeffs = b0Coeffs; + uint32_t zero = 0; + b1Coeffs = vshlcq_s32(b1Coeffs, &zero, 32); + + a0Coeffs[2] = pCoeffs[4]; + a0Coeffs[3] = pCoeffs[3]; + a1Coeffs = vrev64q_s32(a0Coeffs); + + + /* + * prologue consumes history samples + */ + + /* 2 first elements are garbage, will be updated with history */ + inVec0 = vld1q(pIn - 2); + + inVec0[0] = pState[1]; + inVec0[1] = pState[0]; + + stateVec[2] = pState[3]; + stateVec[3] = pState[2]; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + + inVec0 = vld1q(pIn); + pIn += 2; + + /* + * main loop + */ + uint32_t sample = (blockSize - 2) >> 2U; + /* + * First part of the processing with loop unrolling. + * Compute 4 outputs at a time. + */ + while (sample > 0U) { + + stateVec[3] = out1; + + *pOut++ = out; + *pOut++ = out1; + + /* + * in { x0 x1 x2 x3 } + * x + * b0Coeffs { b2 b1 b0 0 } + */ + acc = vrmlaldavhq(b0Coeffs, inVec0); + /* + * out { 0 0 yn2 yn1 } + * x + * a0Coeffs { 0 0 a2 a1 } + */ + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + /* + * in { x0 x1 x2 x3 } + * x + * b0Coeffs { 0 b2 b1 b0 } + */ + acc = vrmlaldavhq(b1Coeffs, inVec0); + /* + * out { 0 0 y0 yn1 } + * x + * a0Coeffs { 0 0 a1 a2 } + */ + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[3] = out1; + + inVec0 = vld1q(pIn); + pIn += 2; + + /* unrolled part */ + *pOut++ = out; + *pOut++ = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0 = vld1q(pIn); + pIn += 2; + + sample--; + } + + *pOut++ = out; + *pOut++ = out1; + + /* + * Tail handling + */ + int32_t loopRemainder = blockSize & 3; + if (loopRemainder == 2) { + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[1]; + pState[1] = inVec0[0]; + pState[3] = out; + pState[2] = out1; + } else if (loopRemainder == 1) { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[3] = out1; + + inVec0 = vld1q(pIn); + pIn += 2; + + *pOut++ = out; + *pOut++ = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[2]; + pState[1] = inVec0[1]; + pState[3] = out1; + pState[2] = out; + } else if (loopRemainder == 0) { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + *pOut++ = out1; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[3]; + pState[1] = inVec0[2]; + pState[3] = out; + pState[2] = out1; + } else { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[2]; + pState[1] = inVec0[1]; + pState[3] = out1; + pState[2] = out; + } + + + pCoeffs += 5; + pState += 4; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + } + while (--stages); +} +#else +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q63_t acc; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc_l, acc_h; /* temporary output variables */ +#endif + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn2) + ((q63_t) b1 * Xn) + ((q63_t) b2 * Xn1) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn1) + ((q63_t) b1 * Xn2) + ((q63_t) b2 * Xn) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Store output in destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t) acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c new file mode 100644 index 0000000..a9ef2e7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c @@ -0,0 +1,498 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if (defined(ARM_MATH_MVE_FLOAT16) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t Xn0, Xn1; + float16_t acc0, acc1; + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float16_t const *pCurCoeffs = /* coefficient pointer */ + (float16_t const *) S->pCoeffs; + f16x8_t b0Coeffs, a0Coeffs; /* Coefficients vector */ + f16x8_t b1Coeffs, a1Coeffs; /* Modified coef. vector */ + f16x8_t state; /* State vector */ + + do + { + /* + * temporary carry variable for feeding the 128-bit vector shifter + */ + uint32_t tmp = 0; + /* + * Reading the coefficients + * b0Coeffs = {b0, b1, b2, x, x, x, x, x} + * a0Coeffs = { x, a1, a2, x, x, x, x, x} + */ + b0Coeffs = vld1q(pCurCoeffs); pCurCoeffs += 2; + a0Coeffs = vld1q(pCurCoeffs); pCurCoeffs += 3; + /* + * Reading the state values + * state = {d1, d2, 0, 0, x, x, x, x} + */ + state = *(f16x8_t *) pState; + state = vsetq_lane((float16_t)0.0, state, 2); + state = vsetq_lane((float16_t)0.0, state, 3); + + /* b1Coeffs = {0, b0, b1, b2, x, x, x, x} */ + /* b1Coeffs = { x, x, a1, a2, x, x, x, x} */ + b1Coeffs = (f16x8_t)vshlcq_s16((int16x8_t)b0Coeffs, &tmp, 16); + a1Coeffs = (f16x8_t)vshlcq_s16((int16x8_t)a0Coeffs, &tmp, 16); + + sample = blockSize / 2; + + /* unrolled 2 x */ + while (sample > 0U) + { + /* + * Read 2 inputs + */ + Xn0 = *pIn++; + Xn1 = *pIn++; + + /* + * 1st half: + * / acc1 \ / b0 \ / d1 \ / 0 \ + * | d1 | | b1 | | d2 | | a1 | + * | d2 | | b2 | | 0 | | a2 | + * | x | = | x | * Xn1 + | x | + | x | x acc1 + * ... ... ... ... + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + state = vfmaq(state, a0Coeffs, acc0); + state = vsetq_lane((float16_t)0.0, state, 3); + + /* + * 2nd half: + * same as 1st half, but all vector elements shifted down. + * / x \ / x \ / x \ / x \ + * | acc1 | | b0 | | d1 | | 0 | + * | d1 | | b1 | | d2 | | a1 | + * | d2 | | b2 | | 0 | | a2 | + * | x | = | x | * Xn1 + | x | + | x | x acc1 + * ... ... ... ... + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b1Coeffs, Xn1); + acc1 = vgetq_lane(state, 1); + state = vfmaq(state, a1Coeffs, acc1); + + /* move d1, d2 up + clearing */ + /* expect dual move or long move */ + state = vsetq_lane(vgetq_lane(state, 2), state, 0); + state = vsetq_lane(vgetq_lane(state, 3), state, 1); + state = vsetq_lane((float16_t)0.0, state, 2); + /* + * Store the results in the destination buffer. + */ + *pOut++ = acc0; + *pOut++ = acc1; + /* + * decrement the loop counter + */ + sample--; + } + + /* compiler does not come back when enabled */ + /* + * tail handling + */ + if (blockSize & 1) + { + Xn0 = *pIn++; + state = vfmaq_n_f16(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + + state = vfmaq_n_f16(state, a0Coeffs, acc0); + *pOut++ = acc0; + *pState++ = vgetq_lane(state, 1); + *pState++ = vgetq_lane(state, 2); + } + else + { + *pState++ = vgetq_lane(state, 0); + *pState++ = vgetq_lane(state, 1); + } + /* + * The current stage input is given as the output to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else + +void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1; /* Temporary input */ + _Float16 d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +#endif /* #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c new file mode 100644 index 0000000..f75a614 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c @@ -0,0 +1,656 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if (defined(ARM_MATH_MVEF) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t Xn0, Xn1; + float32_t acc0, acc1; + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float32_t const *pCurCoeffs = /* coefficient pointer */ + (float32_t const *) S->pCoeffs; + f32x4_t b0Coeffs, a0Coeffs; /* Coefficients vector */ + f32x4_t b1Coeffs, a1Coeffs; /* Modified coef. vector */ + f32x4_t state; /* State vector */ + + do + { + /* + * temporary carry variable for feeding the 128-bit vector shifter + */ + uint32_t tmp = 0; + /* + * Reading the coefficients + * b0Coeffs = {b0, b1, b2, x} + * a0Coeffs = { x, a1, a2, x} + */ + b0Coeffs = vld1q(pCurCoeffs); pCurCoeffs+= 2; + a0Coeffs = vld1q(pCurCoeffs); pCurCoeffs+= 3; + /* + * Reading the state values + * state = {d1, d2, 0, 0} + */ + state = *(f32x4_t *) pState; + state = vsetq_lane(0.0f, state, 2); + state = vsetq_lane(0.0f, state, 3); + + /* b1Coeffs = {b0, b1, b2, x} */ + /* b1Coeffs = { x, x, a1, a2} */ + b1Coeffs = (f32x4_t)vshlcq_s32((int32x4_t)b0Coeffs, &tmp, 32); + a1Coeffs = (f32x4_t)vshlcq_s32((int32x4_t)a0Coeffs, &tmp, 32); + + sample = blockSize / 2; + + /* unrolled 2 x */ + while (sample > 0U) + { + /* + * Read 2 inputs + */ + Xn0 = *pIn++; + Xn1 = *pIn++; + + /* + * 1st half: + * / acc0 \ / b0 \ / d1 \ / 0 \ + * | d1 | = | b1 | * Xn0 + | d2 | + | a1 | x acc0 + * | d2 | | b2 | | 0 | | a2 | + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + state = vfmaq(state, a0Coeffs, acc0); + state = vsetq_lane(0.0f, state, 3); + + /* + * 2nd half: + * same as 1st half, but all vector elements shifted down. + * / x \ / x \ / x \ / x \ + * | acc1 | = | b0 | * Xn1 + | d1 | + | 0 | x acc1 + * | d1 | | b1 | | d2 | | a1 | + * \ d2 / \ b2 / \ 0 / \ a2 / + */ + + state = vfmaq(state, b1Coeffs, Xn1); + acc1 = vgetq_lane(state, 1); + state = vfmaq(state, a1Coeffs, acc1); + + /* move d1, d2 up + clearing */ + /* expect dual move or long move */ + state = vsetq_lane(vgetq_lane(state, 2), state, 0); + state = vsetq_lane(vgetq_lane(state, 3), state, 1); + state = vsetq_lane(0.0f, state, 2); + /* + * Store the results in the destination buffer. + */ + *pOut++ = acc0; + *pOut++ = acc1; + /* + * decrement the loop counter + */ + sample--; + } + + /* + * tail handling + */ + if (blockSize & 1) + { + Xn0 = *pIn++; + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + + state = vfmaq(state, a0Coeffs, acc0); + *pOut++ = acc0; + *pState++ = vgetq_lane(state, 1); + *pState++ = vgetq_lane(state, 2); + } + else + { + *pState++ = vgetq_lane(state, 0); + *pState++ = vgetq_lane(state, 1); + } + /* + * The current stage output is given as the input to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else +#if defined(ARM_MATH_NEON) + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stageCnt,stage = S->numStages; /* loop counters */ + + + float32x4_t XnV, YnV; + float32x4x2_t dV; + float32x4_t zeroV = vdupq_n_f32(0.0); + float32x4_t t1,t2,t3,t4,b1V,b2V,a1V,a2V,s; + + /* Loop unrolling. Compute 4 outputs at a time */ + stageCnt = stage >> 2; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + t1 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t2 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t3 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t4 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + /* Reading the state values */ + dV = vld2q_f32(pState); + + sample = blockSize; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + + XnV = vdupq_n_f32(*pIn++); + + s = dV.val[0]; + YnV = s; + + s = vextq_f32(zeroV,dV.val[0],3); + YnV = vmlaq_f32(YnV, t1, s); + + s = vextq_f32(zeroV,dV.val[0],2); + YnV = vmlaq_f32(YnV, t2, s); + + s = vextq_f32(zeroV,dV.val[0],1); + YnV = vmlaq_f32(YnV, t3, s); + + YnV = vmlaq_f32(YnV, t4, XnV); + + s = vextq_f32(XnV,YnV,3); + + dV.val[0] = vmlaq_f32(dV.val[1], s, b1V); + dV.val[0] = vmlaq_f32(dV.val[0], YnV, a1V); + + dV.val[1] = vmulq_f32(s, b2V); + dV.val[1] = vmlaq_f32(dV.val[1], YnV, a2V); + + *pOut++ = vgetq_lane_f32(YnV, 3) ; + + sample--; + } + + /* Store the updated state variables back into the state array */ + vst2q_f32(pState,dV); + pState += 8; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + + } + + /* Tail */ + stageCnt = stage & 3; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn1 = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc1 = (b0 * Xn1) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = ((b1 * Xn1) + (a1 * acc1)) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn1) + (a2 * acc1); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + } +} +#else + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* Temporary input */ + float32_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c new file mode 100644 index 0000000..6d72a5a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c @@ -0,0 +1,453 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f64.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure + + This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. + The filters are implemented as a cascade of second order Biquad sections. + These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. + Only floating-point data is supported. + + This function operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+     y[n] = b0 * x[n] + d1
+     d1 = b1 * x[n] + a1 * y[n] + d2
+     d2 = b2 * x[n] + a2 * y[n]
+
+ where d1 and d2 represent the two state values. + @par + A Biquad filter using a transposed Direct Form II structure is shown below. + \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad" + Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools flip the sign of the feedback coefficients: + 
+     y[n] = b0 * x[n] + d1;
+     d1 = b1 * x[n] - a1 * y[n] + d2;
+     d2 = b2 * x[n] - a2 * y[n];
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + A 9th order filter would be realized with numStages=5 second order stages with the + coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + @par + pState points to the state variable array. + Each Biquad stage has 2 state variables d1 and d2. + The state variables are arranged in the pState array as: + 
+      {d11, d12, d21, d22, ...}
+
+ where d1x refers to the state variables for the first Biquad and + d2x refers to the state variables for the second Biquad. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + @par + The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. + The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. + That is why the Direct Form I structure supports Q15 and Q31 data types. + The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. + Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. + The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Functions + There is also an associated initialization function. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional except for the vectorized versions (Helium and Neon). + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the instance structure use + 
+      arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer. + pCoeffs is the address of the coefficient buffer; + @par Neon version + For Neon version, the function arm_biquad_cascade_df2T_compute_coefs_x must be + used in addition to arm_biquad_cascade_df2T_init_x. + + See the documentation of arm_biquad_cascade_df2T_init_x for more details. + +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + + +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + + const float64_t *pIn = pSrc; /* Source pointer */ + float64_t *pOut = pDst; /* Destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + const float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t acc1; /* Accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn1; /* Temporary input */ + float64_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c new file mode 100644 index 0000000..fa07f91 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c @@ -0,0 +1,118 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + arm_biquad_cascade_df2T_compute_coefs_f16 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: + 
+                   arm_biquad_cascade_df2T_init_f16(&SNeon, nbCascade, neonCoefs, stateNeon);
+                   arm_biquad_cascade_df2T_compute_coefs_f16(&SNeon,nbCascade,coefs);
+
+ + @par In this example, neonCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df2T_init_f16( + arm_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c new file mode 100644 index 0000000..988d6ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c @@ -0,0 +1,218 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + + + +#if defined(ARM_MATH_NEON) +/** + @brief Compute new coefficient arrays for use in vectorized filter (Neon only). + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the original filter coefficients. + @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized Neon version. + @return none + + @par Size of coefficient arrays: + pCoeffs has size 5 * numStages + + pComputedCoeffs has size 8 * numStages + + pComputedCoeffs is the array to be used in arm_biquad_cascade_df2T_init_f32. + +*/ +void arm_biquad_cascade_df2T_compute_coefs_f32( + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pComputedCoeffs) +{ + uint8_t cnt; + float32_t b0[4],b1[4],b2[4],a1[4],a2[4]; + + cnt = numStages >> 2; + while(cnt > 0) + { + for(int i=0;i<4;i++) + { + b0[i] = pCoeffs[0]; + b1[i] = pCoeffs[1]; + b2[i] = pCoeffs[2]; + a1[i] = pCoeffs[3]; + a2[i] = pCoeffs[4]; + pCoeffs += 5; + } + + /* Vec 1 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1]; + *pComputedCoeffs++ = b0[2]; + *pComputedCoeffs++ = b0[3]; + + /* Vec 2 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1] * b0[2]; + *pComputedCoeffs++ = b0[2] * b0[3]; + + /* Vec 3 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1] * b0[2] * b0[3]; + + /* Vec 4 */ + *pComputedCoeffs++ = b0[0]; + *pComputedCoeffs++ = b0[0] * b0[1]; + *pComputedCoeffs++ = b0[0] * b0[1] * b0[2]; + *pComputedCoeffs++ = b0[0] * b0[1] * b0[2] * b0[3]; + + /* Vec 5 */ + *pComputedCoeffs++ = b1[0]; + *pComputedCoeffs++ = b1[1]; + *pComputedCoeffs++ = b1[2]; + *pComputedCoeffs++ = b1[3]; + + /* Vec 6 */ + *pComputedCoeffs++ = b2[0]; + *pComputedCoeffs++ = b2[1]; + *pComputedCoeffs++ = b2[2]; + *pComputedCoeffs++ = b2[3]; + + /* Vec 7 */ + *pComputedCoeffs++ = a1[0]; + *pComputedCoeffs++ = a1[1]; + *pComputedCoeffs++ = a1[2]; + *pComputedCoeffs++ = a1[3]; + + /* Vec 8 */ + *pComputedCoeffs++ = a2[0]; + *pComputedCoeffs++ = a2[1]; + *pComputedCoeffs++ = a2[2]; + *pComputedCoeffs++ = a2[3]; + + cnt--; + } + + cnt = numStages & 0x3; + while(cnt > 0) + { + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + cnt--; + } + +} +#endif + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + arm_biquad_cascade_df2T_compute_coefs_f32 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: + 
+                   arm_biquad_cascade_df2T_compute_coefs_f32(nbCascade,coefs,computedCoefs);
+                   arm_biquad_cascade_df2T_init_f32(&SNeon, nbCascade, computedCoefs, stateNeon);
+
+ + @par In this example, computedCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c new file mode 100644 index 0000000..e06f35e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c @@ -0,0 +1,90 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f64.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c new file mode 100644 index 0000000..ef6b4cb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c @@ -0,0 +1,438 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_biquad_cascade_stereo_df2T_f16 built. Helium version has build issues with gcc." +#endif + +#if (defined(ARM_MATH_MVE_FLOAT16) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) +void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float16_t b0, b1, b2, a1, a2; /* Filter coefficients */ + uint32_t sample, stage = S->numStages; /* loop counters */ + static const uint16_t idx2[] = {2, 3, 8, 9, 2, 3, 8, 9}; + f16x8_t aCoeffs, bCoeffs; + float16_t scratch[16]; + uint16x8_t loadIdxVec; + uint16x8_t reshufledIdxVec; + uint16_t startIdx = 0; + f16x8_t stateVec0, stateVec1; + f16x8_t inVec; + + /* + * {0, 1, 0, 1, 0, 1, 0, 1} generator + */ + loadIdxVec = viwdupq_u16(startIdx, 2, 1); + reshufledIdxVec = *(uint16x8_t *)&idx2; + + /* + * scratch top clearing + * layout : [d1a d1b d2a d2b d1a d1b d2a d2b 0 0] + */ + scratch[8] = (float16_t)0.0; + scratch[9] = (float16_t)0.0; + + do + { + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* aCoeffs = {a1 a1 a2 a2 a1 a1 a2 a2} */ + aCoeffs = vdupq_n_f16(a1); + aCoeffs = vsetq_lane(a2, aCoeffs, 2); + aCoeffs = vsetq_lane(a2, aCoeffs, 3); + aCoeffs = vsetq_lane(a2, aCoeffs, 6); + aCoeffs = vsetq_lane(a2, aCoeffs, 7); + + /* bCoeffs = {b1 b1 b2 b2 b1 b1 b2 b2} */ + bCoeffs = vdupq_n_f16(b1); + bCoeffs = vsetq_lane(b2, bCoeffs, 2); + bCoeffs = vsetq_lane(b2, bCoeffs, 3); + bCoeffs = vsetq_lane(b2, bCoeffs, 6); + bCoeffs = vsetq_lane(b2, bCoeffs, 7); + + /* + * Reading the state values + * Save into scratch + */ + *(f16x8_t *) scratch = *(f16x8_t *) pState; + + sample = blockSize; + + while (sample > 0U) + { + /* + * step 1 + * + * 0 | acc1a = xn1a * b0 + d1a + * 1 | acc1b = xn1b * b0 + d1b + * 2 | acc1a = xn1a * b0 + d1a + * 3 | acc1b = xn1b * b0 + d1b + * 4 | + * 5 | ... + */ + + /* + * load {d1a, d1b, d1a, d1b, d1a, d1b, d1a, d1b} + */ + stateVec0 = vldrhq_gather_shifted_offset((float16_t const *) scratch, loadIdxVec); + /* + * load {in0 in1 in0 in1 in0 in1 in0 in1} + */ + inVec = vldrhq_gather_shifted_offset_f16(pIn, loadIdxVec); + + stateVec0 = vfmaq(stateVec0, inVec, b0); + *pOut++ = vgetq_lane(stateVec0, 0); + *pOut++ = vgetq_lane(stateVec0, 1); + + /* + * step 2 + * + * 0 | d1a = b1 * xn1a + a1 * acc1a + d2a + * 1 | d1b = b1 * xn1b + a1 * acc1b + d2b + * 2 | d2a = b2 * xn1a + a2 * acc1a + 0 + * 3 | d2b = b2 * xn1b + a2 * acc1b + 0 + * 4 | + * 5 | ... + */ + + /* + * load {d2a, d2b, 0, 0, d2a, d2b, 0, 0} + */ + stateVec1 = vldrhq_gather_shifted_offset((float16_t const *) scratch, reshufledIdxVec); + stateVec1 = vfmaq(stateVec1, stateVec0, aCoeffs); + stateVec1 = vfmaq(stateVec1, inVec, bCoeffs); + *(f16x8_t *) scratch = stateVec1; + + pIn = pIn + 2; + sample--; + } + + /* + * Store the updated state variables back into the state array + */ + *pState++ = vgetq_lane(stateVec1, 0); + *pState++ = vgetq_lane(stateVec1, 1); + *pState++ = vgetq_lane(stateVec1, 2); + *pState++ = vgetq_lane(stateVec1, 3); + + /* + * The current stage input is given as the output to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else + +void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1a, acc1b; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1a, Xn1b; /* Temporary input */ + _Float16 d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c new file mode 100644 index 0000000..e0a5d03 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c @@ -0,0 +1,424 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if (defined(ARM_MATH_MVEF) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float32_t scratch[6]; + uint32x4_t loadIdxVec; + f32x4_t aCoeffs, bCoeffs; + f32x4_t stateVec0, stateVec1; + f32x4_t inVec; + uint32_t startIdx = 0; + + /* + * {0, 1, 0, 1} generator + */ + loadIdxVec = viwdupq_u32(&startIdx, 2, 1); + + /* + * scratch top clearing + * layout : [d1a d1b d2a d2b 0 0] + */ + scratch[4] = 0.0f; + scratch[5] = 0.0f; + + do + { + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* + * aCoeffs = {a1 a1 a2 a2} + */ + aCoeffs = vdupq_n_f32(a1); + aCoeffs = vsetq_lane(a2, aCoeffs, 2); + aCoeffs = vsetq_lane(a2, aCoeffs, 3); + + /* + * bCoeffs = {b1 b1 b2 b2} + */ + bCoeffs = vdupq_n_f32(b1); + bCoeffs = vsetq_lane(b2, bCoeffs, 2); + bCoeffs = vsetq_lane(b2, bCoeffs, 3); + + /* + * Reading the state values + * Save into scratch + */ + *(f32x4_t *) scratch = *(f32x4_t *) pState; + + sample = blockSize; + + while (sample > 0U) + { + /* + * step 1 + * + * 0 | acc1a = xn1a * b0 + d1a + * 1 | acc1b = xn1b * b0 + d1b + * 2 | acc1a = xn1a * b0 + d1a + * 3 | acc1b = xn1b * b0 + d1b + */ + /* + * load {d1a, d1b, d1a, d1b} + */ + stateVec0 = (f32x4_t)vldrwq_gather_shifted_offset((uint32_t const *) scratch, loadIdxVec); + /* + * load {in0 in1 in0 in1} + */ + inVec = (f32x4_t)vldrwq_gather_shifted_offset((uint32_t const *) pIn, loadIdxVec); + + stateVec0 = vfmaq(stateVec0, inVec, b0); + *pOut++ = vgetq_lane(stateVec0, 0); + *pOut++ = vgetq_lane(stateVec0, 1); + + /* + * step 2 + * + * 0 | d1a = b1 * xn1a + a1 * acc1a + d2a + * 1 | d1b = b1 * xn1b + a1 * acc1b + d2b + * 2 | d2a = b2 * xn1a + a2 * acc1a + 0 + * 3 | d2b = b2 * xn1b + a2 * acc1b + 0 + */ + + /* + * load {d2a, d2b, 0, 0} + */ + stateVec1 = *(f32x4_t *) & scratch[2]; + stateVec1 = vfmaq(stateVec1, stateVec0, aCoeffs); + stateVec1 = vfmaq(stateVec1, inVec, bCoeffs); + *(f32x4_t *) scratch = stateVec1; + + pIn = pIn + 2; + sample--; + } + + /* + * Store the updated state variables back into the state array + */ + vst1q(pState, stateVec1); + pState += 4; + + /* + * The current stage output is given as the input to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} + +#else + +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1a, acc1b; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* Temporary input */ + float32_t d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c new file mode 100644 index 0000000..3277519 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c @@ -0,0 +1,94 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_stereo_df2T_init_f16( + arm_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c new file mode 100644 index 0000000..f7dd819 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c @@ -0,0 +1,90 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c new file mode 100644 index 0000000..5e123e4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c @@ -0,0 +1,976 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_f32.c + * Description: Convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Conv Convolution + + Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. + Convolution is similar to correlation and is frequently used in filtering and data analysis. + The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. + The library also provides fast versions of the Q15 and Q31 functions. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and + srcBLen samples respectively. Then the convolution + \f[ + c[n] = a[n] * b[n] + \f] + @par + is defined as + \f[ + c[n] = \sum_{k=0}^{srcALen} a[k] b[n-k] + \f] + @par + Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. + pSrcA points to the first input vector of length srcALen and + pSrcB points to the second input vector of length srcBLen. + The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result. + @par + Conceptually, when two signals a[n] and b[n] are convolved, + the signal b[n] slides over a[n]. + For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together. + @par + Note that convolution is a commutative operation: + \f[ + a[n] * b[n] = b[n] * a[n]. + \f] + @par + This means that switching the A and B arguments to the convolution functions has no effect. + + @par Fixed-Point Behavior + Convolution requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions + + @par Long versions: + For convolution of long vectors, those functions are + no more adapted and will be very slow. + An implementation based upon FFTs should be used. + + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" + + +void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const float32_t *pX; + const float32_t *pY; + const float32_t *pA; + const float32_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint32_t vddupStartIdx = 3; + uint32x4_t decrIdxVec = vddupq_u32(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 3; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is incrementing for successive accumulators + * Y pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst++ = acc0; + *pDst++ = acc1; + pB += 2; + } + + for (; i < block1; i++) + { + uint32_t count = i + 1; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pB++; + } + + for (i = 0; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + float32_t acc0 = 0; + float32_t acc1 = 0; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count); + *pDst++ = acc0; + *pDst++ = acc1; + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + float32_t acc = 0; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pA++; + } + + for (i = block3; i >= 2; i -= 2) + { + int32_t count = i; + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for successive accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst++ = acc0; + *pDst++ = acc1; + pA += 2; + } + for (; i >= 1; i--) + { + int32_t count = i; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pA++; + } +} +#else +void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(ARM_MATH_DSP) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3, c0; /* Accumulators */ +#if !defined(ARM_MATH_NEON) + float32_t x0, x1, x2, x3; /* Temporary variables to hold state and coefficient values */ +#endif +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); +#endif /* #if defined(ARM_MATH_NEON) */ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + accum = vdup_n_f32(0); + + /* Compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + + while (k > 0U) + { + vec1 = vld1q_f32(px); + vec2 = vld1q_f32(py-3); + vec2 = vrev64q_f32(vec2); + vec2 = vcombine_f32(vget_high_f32(vec2), vget_low_f32(vec2)); + + res = vmlaq_f32(res,vec1, vec2); + + /* Increment pointers */ + px += 4; + py -= 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count & 3; +#else + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ + +#else /* defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + float32x4_t x; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + x2v = vld1q_f32(px+4); + + do + { + c = vld1q_f32(py-3); + + px += 4; + x = x1v; + res = vmlaq_n_f32(res,x,c[3]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[0]); + + py -= 4; + + x1v = x2v ; + x2v = vld1q_f32(px+4); + + } while (--k); + + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + x1v = vld1q_f32(px); + px += 4; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py--); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; + +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *(px + 3U); + px += 4U; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined (ARM_MATH_NEON)*/ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined (ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3U; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#endif /* if defined (ARM_MATH_NEON) */ +#else + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined (ARM_MATH_NEON) */ + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL)*/ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c new file mode 100644 index 0000000..62b1c95 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c @@ -0,0 +1,370 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_opt_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c new file mode 100644 index 0000000..d00ad65 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c @@ -0,0 +1,667 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + /* Read y[srcBLen - 7] */ + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD(x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((acc0 >> 15), (acc1 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc2 >> 15), (acc3 >> 15), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((acc1 >> 15), (acc0 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc3 >> 15), (acc2 >> 15), 16)); +#endif /*#ifndef ARM_MATH_BIG_ENDIAN*/ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c new file mode 100644 index 0000000..569e484 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c @@ -0,0 +1,562 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q31.c + * Description: Fast Q31 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + @remark + Refer to \ref arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c new file mode 100644 index 0000000..6230627 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c @@ -0,0 +1,366 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + */ + +void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q63_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c new file mode 100644 index 0000000..1afdb5d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c @@ -0,0 +1,364 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + const q7_t *px; /* Temporary input1 pointer */ + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + /* Actual convolution process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2U; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c new file mode 100644 index 0000000..1ce871c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c @@ -0,0 +1,688 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_f32.c + * Description: Partial convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup PartialConv Partial Convolution + + Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. + Each function has two additional arguments. + firstIndex specifies the starting index of the subset of output samples. + numPoints is the number of output samples to compute. + The function computes the output in the range + [firstIndex, ..., firstIndex+numPoints-1]. + The output array pDst contains numPoints values. + + The allowable range of output indices is [0 srcALen+srcBLen-2]. + If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. + Otherwise the functions return ARM_MATH_SUCCESS. + \note Refer to \ref arm_conv_f32() for details on fixed point behavior. + + @par Fast Versions + Fast versions are supported for Q31 and Q15 of partial convolution. + Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of partial convolution + + @par Long versions: + For convolution of long vectors, those functions are + no more adapted and will be very slow. + An implementation based upon FFTs should be used. + + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ +#if defined (ARM_MATH_DSP) + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; /* Accumulator */ + float32_t x0, x1, x2, x3, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = ((int32_t) check - blockSize3) - (blockSize1 + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + firstIndex; + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc1; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + + /* Set status as ARM_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* defined(ARM_MATH_DSP) */ +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c new file mode 100644 index 0000000..d181f6e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c @@ -0,0 +1,391 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_opt_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q31_t acc0; /* Accumulator */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c new file mode 100644 index 0000000..96cfe1c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c @@ -0,0 +1,711 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(acc0 >> 15, acc1 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc2 >> 15, acc3 >> 15, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(acc1 >> 15, acc0 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc3 >> 15, acc2 >> 15, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c new file mode 100644 index 0000000..4f7a01a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c @@ -0,0 +1,629 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q31.c + * Description: Fast Q31 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + */ + +arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t j, k, count, check, blkCnt; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c new file mode 100644 index 0000000..1296674 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c @@ -0,0 +1,390 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + */ + +arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q63_t acc0; /* Accumulator */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + acc0 = __SMLALD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c new file mode 100644 index 0000000..1b0527d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c @@ -0,0 +1,394 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */ + q15_t x4; /* Temporary input variable */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + const q7_t *px; /* Temporary input1 pointer */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + arm_status status; + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2; + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + pOut = pDst + firstIndex; + + pScratch1 += firstIndex; + + /* Actual convolution process starts here */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialize temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumulators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (numPoints) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c new file mode 100644 index 0000000..41cd5c9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c @@ -0,0 +1,763 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers. + */ + +arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt, check; + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c new file mode 100644 index 0000000..887aa71 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c @@ -0,0 +1,644 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q31.c + * Description: Partial convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q31() for a faster but less precise implementation of this function. + */ + +arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined(ARM_MATH_DSP) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulator */ + q31_t x0, x1, x2, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll over blkCnt */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += (q63_t) x2 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += (q63_t) x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += (q63_t) x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += (q63_t) x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += (q63_t) x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += (q63_t) x0 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += (q63_t) x1 * c0; + + + px += 3U; + + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += (q63_t) x2 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c new file mode 100644 index 0000000..3589f63 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c @@ -0,0 +1,763 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_opt_q7() for a faster implementation of this function. + */ + +arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined(ARM_MATH_DSP) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; /* Loop counters */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q31_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q31_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q31_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q31_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * (pIn2[i - j])); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c new file mode 100644 index 0000000..38e652c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c @@ -0,0 +1,862 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_opt_q15() for a faster implementation of this function using scratch buffers. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" + +void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1 = pSrcA; /* inputA pointer */ + const q15_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q15_t *pX; + const q15_t *pY; + const q15_t *pA; + const q15_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + + + uint16x8_t decrIdxVec = vddupq_u16(7, 1); + + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 7; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + *pDst++ = (q15_t) acc2; + *pDst++ = (q15_t) acc3; + + pA += 4; + } + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pA++; + } + + for (i = block3; i >= 1; i -= 2) + { + uint32_t count = i; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + pA += 2; + } + for (; i >= 1; i--) + { + uint32_t count = i; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pA++; + } +} +#else +void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD(x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + blockSize3 = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of values */ + for (i = 0; i < (srcALen + srcBLen - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c new file mode 100644 index 0000000..9d2dd29 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c @@ -0,0 +1,749 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q31.c + * Description: Convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_conv_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" + +void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1 = pSrcA; /* inputA pointer */ + const q31_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q31_t *pX; + const q31_t *pY; + const q31_t *pA; + const q31_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint32_t vddupStartIdx = 3; + uint32x4_t decrIdxVec = vddupq_u32(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 3; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + + *pDst++ = (q31_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + *pDst++ = (q31_t) acc3; + + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + *pDst++ = (q31_t) acc; + pA++; + } + + for (i = block3; i >= 2; i -= 2) + { + uint32_t count = i; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + pA += 2; + } + + for (; i >= 1; i--) + { + uint32_t count = i; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + *pDst++ = (q31_t) acc; + pA++; + } + +} + +#else +void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + /* Read x[3] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c new file mode 100644 index 0000000..a0f96dd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c @@ -0,0 +1,864 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + @remark + Refer to \ref arm_conv_opt_q7() for a faster implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" + +void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + const q7_t *pIn1 = pSrcA; /* inputA pointer */ + const q7_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q7_t *pX; + const q7_t *pY; + const q7_t *pA; + const q7_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint8_t vddupStartIdx = 15; + uint8x16_t decrIdxVec = vddupq_u8(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 15; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int32_t acc0 = 0; + int32_t acc1 = 0; + int32_t acc2 = 0; + int32_t acc3 = 0; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + *pDst++ = (q7_t) acc2; + *pDst++ = (q7_t) acc3; + pA += 4; + } + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pA++; + } + + for (i = block3; i >= 1; i -= 2) + { + uint32_t count = i; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pA += 2; + } + for (; i >= 1; i--) + { + uint32_t count = i; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pA++; + } +} + +#else +void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c new file mode 100644 index 0000000..d584c25 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c @@ -0,0 +1,1119 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f16.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_f16(&pSrcY[-1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_f16(&pSrcY[-1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec,p0); \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t accVec, xVec, yVec; \ + uint16_t k; \ + \ + accVec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + accVec = vfmaq(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + accVec = vfmaq_m(accVec, xVec, yVec, p0); \ + } \ + \ + acc = vecAddAcrossF16Mve(accVec); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F16(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, acc2Vec, acc3Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + acc2Vec = vdupq_n_f16(0.0f); \ + acc3Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vldrhq_f16(&pSrcX[2]); \ + acc2Vec = vfmaq_f16(acc2Vec, xVec, yVec); \ + xVec = vldrhq_f16(&pSrcX[3]); \ + acc3Vec = vfmaq_f16(acc3Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + xVec = vldrhq_f16(&pSrcX[2]); \ + acc2Vec = vfmaq_m_f16(acc2Vec, xVec, yVec, p0); \ + xVec = vldrhq_f16(&pSrcX[3]); \ + acc3Vec = vfmaq_m_f16(acc3Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ + acc2 = vecAddAcrossF16Mve(acc2Vec); \ + acc3 = vecAddAcrossF16Mve(acc3Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8;; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x8U; \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + + + +void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst) +{ + float16_t *pIn1 = (float16_t *)pSrcA; /* inputA pointer */ + float16_t *pIn2 = (float16_t *)pSrcB + (srcBLen - 1U); /* inputB pointer */ + float16_t *pX; + float16_t *pY; + float16_t *pA; + float16_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 2U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = (float16_t *)pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = (float16_t *)pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -2; + + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 2; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + _Float16 acc0; + _Float16 acc1; + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F16(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + _Float16 acc0; + _Float16 acc1; + _Float16 acc2; + _Float16 acc3; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F16(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + *pDst = acc2; + pDst += incr; + *pDst = acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + _Float16 acc0; + _Float16 acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F16(acc0, acc1, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, srcBLen); + + *pDst = acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + _Float16 acc0; + _Float16 acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F16(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_AUTOVECTORIZE) + + const float16_t *pIn1; /* InputA pointer */ + const float16_t *pIn2; /* InputB pointer */ + float16_t *pOut = pDst; /* Output pointer */ + const float16_t *px; /* Intermediate inputA pointer */ + const float16_t *py; /* Intermediate inputB pointer */ + const float16_t *pSrc1; + _Float16 sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 acc0, acc1, acc2, acc3,c0; /* Accumulators */ + _Float16 x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[1] * y[srcBLen - 3] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[2] * y[srcBLen - 2] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[3] * y[srcBLen - 1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + acc3 = 0.0f16; + + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += (_Float16)x0 * (_Float16)c0; + /* acc1 += x[1] * y[0] */ + acc1 += (_Float16)x1 * (_Float16)c0; + /* acc2 += x[2] * y[0] */ + acc2 += (_Float16)x2 * (_Float16)c0; + /* acc3 += x[3] * y[0] */ + acc3 += (_Float16)x3 * (_Float16)c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += (_Float16)x1 * (_Float16)c0; + /* acc1 += x[2] * y[1] */ + acc1 += (_Float16)x2 * (_Float16)c0; + /* acc2 += x[3] * y[1] */ + acc2 += (_Float16)x3 * (_Float16)c0; + /* acc3 += x[4] * y[1] */ + acc3 += (_Float16)x0 * (_Float16)c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += (_Float16)x2 * (_Float16)c0; + /* acc1 += x[3] * y[2] */ + acc1 += (_Float16)x3 * (_Float16)c0; + /* acc2 += x[4] * y[2] */ + acc2 += (_Float16)x0 * (_Float16)c0; + /* acc3 += x[5] * y[2] */ + acc3 += (_Float16)x1 * (_Float16)c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += (_Float16)x3 * (_Float16)c0; + /* acc1 += x[4] * y[3] */ + acc1 += (_Float16)x0 * (_Float16)c0; + /* acc2 += x[5] * y[3] */ + acc2 += (_Float16)x1 * (_Float16)c0; + /* acc3 += x[6] * y[3] */ + acc3 += (_Float16)x2 * (_Float16)c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += (_Float16)x0 * (_Float16)c0; + /* acc1 += x[5] * y[4] */ + acc1 += (_Float16)x1 * (_Float16)c0; + /* acc2 += x[6] * y[4] */ + acc2 += (_Float16)x2 * (_Float16)c0; + /* acc3 += x[7] * y[4] */ + acc3 += (_Float16)x3 * (_Float16)c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float16_t *pIn1 = pSrcA; /* inputA pointer */ + const float16_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + _Float16 sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f16; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += (_Float16)pIn1[j] * (_Float16)pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Corr group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c new file mode 100644 index 0000000..7d4880e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c @@ -0,0 +1,1108 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f32.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by + \f[ + c[n] = a[n] * b[n] + \f] + + In correlation, one of the signals is flipped in time + + \f[ + c[n] = a[n] * b[-n] + \f] + @par + and this is mathematically defined as + \f[ + c[n] = \sum_{k=0}^{srcALen} a[k] b[k-n] + \f] + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + + @par Long versions: + For convolution of long vectors, those functions are + no more adapted and will be very slow. + An implementation based upon FFTs should be used. + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" + + +void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + const float32_t *pX, *pY; + const float32_t *pA, *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 4U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -4; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 4; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + float32_t acc0; + float32_t acc1; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + float32_t acc0; + float32_t acc1; + float32_t acc2; + float32_t acc3; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F32(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + *pDst = acc2; + pDst += incr; + *pDst = acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, srcBLen); + + *pDst = acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_AUTOVECTORIZE) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1; + float32_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3,c0; /* Accumulators */ +#if !defined(ARM_MATH_NEON) + float32_t x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + k = count & 0x3; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += *px++ * *py++; + + /* x[1] * y[srcBLen - 3] */ + sum += *px++ * *py++; + + /* x[2] * y[srcBLen - 2] */ + sum += *px++ * *py++; + + /* x[3] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + float32x4_t x; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + +#if defined(ARM_MATH_NEON) + /* Compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + px += 4; + do + { + x2v = vld1q_f32(px); + c = vld1q_f32(py); + + py += 4; + + x = x1v; + res = vmlaq_n_f32(res,x,c[0]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[3]); + + x1v = x2v; + px+=4; + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py++); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + px-=1; + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[0] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[0] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[0] */ + acc3 += x3 * c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[1] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[1] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[1] */ + acc3 += x0 * c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[2] */ + acc3 += x1 * c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[3] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[3] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[3] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[4] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[4] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[4] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + +#endif /* #if defined (ARM_MATH_NEON) */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c new file mode 100644 index 0000000..e0e9ba6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c @@ -0,0 +1,369 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f64.c + * Description: Correlation of floating-point sequences + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +void arm_correlate_f64( + const float64_t * pSrcA, + uint32_t srcALen, + const float64_t * pSrcB, + uint32_t srcBLen, + float64_t * pDst) +{ + const float64_t *pIn1; /* InputA pointer */ + const float64_t *pIn2; /* InputB pointer */ + float64_t *pOut = pDst; /* Output pointer */ + const float64_t *px; /* Intermediate inputA pointer */ + const float64_t *py; /* Intermediate inputB pointer */ + const float64_t *pSrc1; + float64_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize k with number of samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize blkCnt with number of samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } +} + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c new file mode 100644 index 0000000..2f655d7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c @@ -0,0 +1,349 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_opt_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q31_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch; /* Temporary pointer for scratch */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c new file mode 100644 index 0000000..ecb26da --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c @@ -0,0 +1,618 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + + c0 = (*py); + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (acc0 >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (acc1 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc2 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc3 >> 15); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) * px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c new file mode 100644 index 0000000..5747e13 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c @@ -0,0 +1,605 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q31.c + * Description: Fast Q31 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + + @remark + Refer to \ref arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[1] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[3] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[0] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[0] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[0] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[1] sample */ + c0 = *py++; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[2] sample */ + c0 = *py++; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[3] sample */ + c0 = *py++; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 << 1); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 << 1); + pOut += inc; + + *pOut = (q31_t) (acc2 << 1); + pOut += inc; + + *pOut = (q31_t) (acc3 << 1); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1U; + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c new file mode 100644 index 0000000..5283f24 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c @@ -0,0 +1,345 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + */ + +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + q63_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1; /* Temporary pointer for scratch1 */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t tapCnt; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input1 and input2 values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c new file mode 100644 index 0000000..0cab9f2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c @@ -0,0 +1,392 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t outBlockSize; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + q7_t *pOut = pDst; /* Output pointer */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + + /* Copy (srcBLen) samples in scratch buffer */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pScr2 pointer */ + pScr2 = pScratch2; + + /* Actual correlation process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc1 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc2 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc3 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c new file mode 100644 index 0000000..aa8bc35 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c @@ -0,0 +1,907 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" + +void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1 = pSrcA; /* inputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q15_t *pX; + const q15_t *pY; + const q15_t *pA; + const q15_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 2U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -2; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 2; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count); + + *pDst = (q15_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + *pDst = (q15_t) acc2; + pDst += incr; + *pDst = (q15_t) acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, srcBLen); + + *pDst = (q15_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count); + + *pDst = (q15_t) acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLALD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLALD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLALD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLALD(x1, c0, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + + c0 = (*py); + + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(acc0 >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc1 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc2 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc3 >> 15, 16)); + pOut += inc; + + /* Increment the count by 4 as 4 output values are computed */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment count by 1, as one output value is computed */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of values */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) __SSAT((sum >> 15U), 16U); + else + *pDst++ = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c new file mode 100644 index 0000000..4aa50da --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c @@ -0,0 +1,883 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q31.c + * Description: Correlation of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_correlate_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" +void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1 = pSrcA; /* inputA pointer */ + const q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q31_t *pX; + const q31_t *pY; + const q31_t *pA; + const q31_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 4; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialization of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -4; + + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + pA = pIn1; + pB = pIn2; + incr = inv / 4; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + /* compute 2 accumulators per loop */ + /* size is incrementing for second accumulator */ + /* Y pointer is decrementing for second accumulator */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count); + + *pDst = (q31_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* compute 4 accumulators per loop */ + /* size is fixed for all accumulators */ + /* X pointer is incrementing for successive accumulators */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + *pDst = (q31_t) acc2; + pDst += incr; + *pDst = (q31_t) acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* compute 2 accumulators per loop */ + /* size is fixed for all accumulators */ + /* X pointer is incrementing for second accumulator */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, srcBLen); + + *pDst = (q31_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* compute 2 accumulators per loop */ + /* size is decrementing for second accumulator */ + /* X pointer is incrementing for second accumulator */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count); + + *pDst = (q31_t) acc; + pDst += incr; + pA++; + } +} +#else +void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py++); + + /* x[1] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py++); + + /* x[2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py++); + + /* x[3] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py); + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[0] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[0] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[1] sample */ + c0 = *(py + 1U); + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[1] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[1] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[2] sample */ + c0 = *(py + 2U); + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py += 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + + /* Read x[7] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 >> 31); + pOut += inc; + + *pOut = (q31_t) (acc2 >> 31); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using correlation but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t) (sum >> 31U); + else + *pDst++ = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c new file mode 100644 index 0000000..095ec99 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c @@ -0,0 +1,1006 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. + + @remark + Refer to \ref arm_correlate_opt_q7() for a faster implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_filtering.h" +void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + const q7_t *pIn1 = pSrcA; /* inputA pointer */ + const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + const q7_t *pX, *pY; + const q7_t *pA, *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 1U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -1; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int32_t acc0 = 0; + int32_t acc1 = 0; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int32_t acc = 0; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count); + + *pDst = (q7_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int32_t acc0 = 0; + int32_t acc1 = 0; + int32_t acc2 = 0; + int32_t acc3 = 0; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + *pDst = (q7_t) acc2; + pDst += incr; + *pDst = (q7_t) acc3; + pDst += incr; + + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int32_t acc0 = 0LL; + int32_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int32_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, srcBLen); + + *pDst = (q7_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + uint32_t count = (i + 1); + int32_t acc0 = 0LL; + int32_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count); + + *pDst = (q7_t) acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 4] , y[srcBLen - 3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 4] */ + /* x[1] * y[srcBLen - 3] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 2] , y[srcBLen - 1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 2] */ + /* x[3] * y[srcBLen - 1] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q31_t) ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read y[1] sample */ + c1 = *py++; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] and y[1] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[2] sample */ + c0 = *py++; + /* Read y[3] sample */ + c1 = *py++; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] and y[3] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[4] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc1 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc2 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc3 >> 7, 8)); + pOut += inc; + + count += 4U; + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] , y[1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = __SMLAD(input1, input2, sum); + + /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] , y[3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U); + else + *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c new file mode 100644 index 0000000..cf641ec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c @@ -0,0 +1,955 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_f32.c + * Description: FIR decimation for floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator + + These functions combine an FIR filter together with a decimator. + They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRDecimator.gif "Components included in the FIR Decimator functions" + When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized + cutoff frequency of 1/M in order to prevent aliasing distortion. + The user of the function is responsible for providing the filter coefficients. + + The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. + Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the + samples output by the decimator are computed. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize/M output values. + In order to have an integer number of output samples blockSize + must always be a multiple of the decimation factor M. + + The library provides separate functions for Q15, Q31 and floating-point data types. + + @par Algorithm: + The FIR portion of the algorithm uses the standard form filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ where, b[n] are the filter coefficients. + @par + The pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the size of the input is a multiple of the decimation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+
+ where M is the decimation factor; numTaps is the number of filter coefficients in the filter; + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR decimate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const float32_t *px0, *px1, *px2, *px3; + f32x4_t accv = { 0 }, acc0v, acc1v, acc2v, acc3v; + f32x4_t x0v, x1v, x2v, x3v; + f32x4_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 2; + do + { + vst1q(pStateCurnt, vld1q((const float32_t *)pSrc)); + pSrc += 4; + pStateCurnt += 4; + i--; + } + while (i > 0U); + + /* + * Set accumulators to zero + */ + acc0v = vdupq_n_f32(0.0f); + acc1v = vdupq_n_f32(0.0f); + acc2v = vdupq_n_f32(0.0f); + acc3v = vdupq_n_f32(0.0f); + + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vld1q((const float32_t *)pb); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vfmaq(acc0v, x0v, c0v); + acc1v = vfmaq(acc1v, x1v, c0v); + acc2v = vfmaq(acc2v, x2v, c0v); + acc3v = vfmaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_z_f32(pb, p0); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vfmaq_f32(acc0v, x0v, c0v); + acc1v = vfmaq_f32(acc1v, x1v, c0v); + acc2v = vfmaq_f32(acc2v, x2v, c0v); + acc3v = vfmaq_f32(acc3v, x3v, c0v); + } + + /* reduction */ + accv[0] = vecAddAcrossF32Mve(acc0v); + accv[1] = vecAddAcrossF32Mve(acc1v); + accv[2] = vecAddAcrossF32Mve(acc2v); + accv[3] = vecAddAcrossF32Mve(acc3v); + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + vst1q(pDst, accv); + pDst += 4; + + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = vdupq_n_f32(0.0f); + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + c0v = vldrwq_f32(pb); + x0v = vldrwq_f32(px); + pb += 4; + px += 4; + acc0v = vfmaq_f32(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + c0v = vldrwq_z_f32(pb, p0); + x0v = vldrwq_f32(px); + acc0v = vfmaq_f32(acc0v, x0v, c0v); + } + accv[0] = vecAddAcrossF32Mve(acc0v); + + /* + * Advance the state pointer by the decimation factor + * * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = accv[0]; + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + + pStateCurnt = S->pState; + blkCnt =(numTaps - 1) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (numTaps - 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulator */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + uint32_t blkCntN4; + float32_t *px0, *px1, *px2, *px3; + float32_t x1, x2, x3; + + float32x4_t accv,acc0v,acc1v,acc2v,acc3v; + float32x4_t x0v, x1v, x2v, x3v; + float32x4_t c0v; + float32x2_t temp; + float32x4_t sum0v; + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = 4 * S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0v = vdupq_n_f32(0.0); + acc1v = vdupq_n_f32(0.0); + acc2v = vdupq_n_f32(0.0); + acc3v = vdupq_n_f32(0.0); + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0v = vld1q_f32(pb); + pb += 4; + + /* Read x[n-numTaps-1] sample for acc0 */ + x0v = vld1q_f32(px0); + x1v = vld1q_f32(px1); + x2v = vld1q_f32(px2); + x3v = vld1q_f32(px3); + + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vmlaq_f32(acc0v, x0v, c0v); + acc1v = vmlaq_f32(acc1v, x1v, c0v); + acc2v = vmlaq_f32(acc2v, x2v, c0v); + acc3v = vmlaq_f32(acc3v, x3v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(acc0v),vget_high_f32(acc0v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,0); + + temp = vpadd_f32(vget_low_f32(acc1v),vget_high_f32(acc1v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,1); + + temp = vpadd_f32(vget_low_f32(acc2v),vget_high_f32(acc2v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,2); + + temp = vpadd_f32(vget_low_f32(acc3v),vget_high_f32(acc3v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,3); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 0) + x0 * c0,accv,0); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 1) + x1 * c0,accv,1); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 2) + x2 * c0,accv,2); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 3) + x3 * c0,accv,3); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + 4 * S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + vst1q_f32(pDst,accv); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + c0v = vld1q_f32(pb); + pb += 4; + + x0v = vld1q_f32(px); + px += 4; + + sum0v = vmlaq_f32(sum0v, x0v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = (numTaps - 1U) >> 2; + + /* Copy data */ + while (i > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} +#else +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *px0; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t *px1, *px2, *px3; + float32_t x1, x2, x3; + float32_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +#endif /*defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c new file mode 100644 index 0000000..66f0e90 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c @@ -0,0 +1,599 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q15.c + * Description: Fast Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator (fast variant). + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + @remark + Refer to \ref arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q15() to initialize the filter structure. + */ + +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ + +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c new file mode 100644 index 0000000..6aa1a23 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c @@ -0,0 +1,394 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q31.c + * Description: Fast Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator (fast variant). + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + + @remark + Refer to \ref arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q31() to initialize the filter structure. + */ + +void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c new file mode 100644 index 0000000..c67b49c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c @@ -0,0 +1,109 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_f32.c + * Description: Floating-point FIR Decimator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c new file mode 100644 index 0000000..9c4913f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c @@ -0,0 +1,110 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q15.c + * Description: Initialization function for the Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR decimator. + @param[in,out] S points to an instance of the Q15 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples + to the call arm_fir_decimate_q15(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c new file mode 100644 index 0000000..a4bb036 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c @@ -0,0 +1,109 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q31.c + * Description: Initialization function for Q31 FIR Decimation filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR decimator. + @param[in,out] S points to an instance of the Q31 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c new file mode 100644 index 0000000..cd03e0c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c @@ -0,0 +1,855 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q15.c + * Description: Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator. + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + const q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const q15_t *px0, *px1, *px2, *px3; + q63_t acc0v, acc1v, acc2v, acc3v; + q15x8_t x0v, x1v, x2v, x3v; + q15x8_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Need extra temp variables as 4 * S->M is not necessarily a multiple of 8 + * and cause final tail predicated post incremented pointers to jump ahead + */ + const q15_t *pSrcTmp = pSrc; + q15_t *pStateCurntTmp = pStateCurnt; + + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 3; + while (i > 0U) + { + vstrhq_s16(pStateCurntTmp, vldrhq_s16(pSrcTmp)); + pSrcTmp += 8; + pStateCurntTmp += 8; + i--; + } + i = (4 * S->M) & 7; + if (i > 0U) + { + mve_pred16_t p0 = vctp16q(i); + vstrhq_p_s16(pStateCurntTmp, vldrhq_s16(pSrcTmp), p0); + } + + pSrc += (4 * S->M); + pStateCurnt += (4 * S->M); + + /* + * Clear all accumulators + */ + acc0v = 0LL; + acc1v = 0LL; + acc2v = 0LL; + acc3v = 0LL; + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + + tapCnt = numTaps >> 3; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrhq_s16(pb); + pb += 8; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 8; + px1 += 8; + px2 += 8; + px3 += 8; + + acc0v = vmlaldavaq(acc0v, x0v, c0v); + acc1v = vmlaldavaq(acc1v, x1v, c0v); + acc2v = vmlaldavaq(acc2v, x2v, c0v); + acc3v = vmlaldavaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrhq_z_s16(pb, p0); + pb += 8; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 8; + px1 += 8; + px2 += 8; + px3 += 8; + + acc0v = vmlaldavaq(acc0v, x0v, c0v); + acc1v = vmlaldavaq(acc1v, x1v, c0v); + acc2v = vmlaldavaq(acc2v, x2v, c0v); + acc3v = vmlaldavaq(acc3v, x3v, c0v); + } + + acc0v = asrl(acc0v, 15); + acc1v = asrl(acc1v, 15); + acc2v = asrl(acc2v, 15); + acc3v = asrl(acc3v, 15); + /* + * store in the destination buffer. + */ + *pDst++ = (q15_t) __SSAT((q31_t) acc0v, 16); + *pDst++ = (q15_t) __SSAT((q31_t) acc1v, 16);; + *pDst++ = (q15_t) __SSAT((q31_t) acc2v, 16);; + *pDst++ = (q15_t) __SSAT((q31_t) acc3v, 16);; + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = 0LL; + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + + tapCnt = numTaps >> 3; + while (tapCnt > 0U) + { + c0v = vldrhq_s16(pb); + x0v = vldrhq_s16(px); + pb += 8; + px += 8; + acc0v = vmlaldavaq(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = numTaps & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + c0v = vldrhq_z_s16(pb, p0); + x0v = vldrhq_z_s16(px, p0); + acc0v = vmlaldavaq_p(acc0v, x0v, c0v, p0); + } + + acc0v = asrl(acc0v, 15); + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = (q15_t) __SSAT((q31_t) acc0v, 16); + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + + pStateCurnt = S->pState; + blkCnt = (numTaps - 1) >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pStateCurnt, vldrhq_s16(pState)); + pState += 8; + pStateCurnt += 8; + blkCnt--; + } + blkCnt = (numTaps - 1) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pStateCurnt, vldrhq_s16(pState), p0); + } +} +#else +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c new file mode 100644 index 0000000..d104b35 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c @@ -0,0 +1,638 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q31.c + * Description: Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator. + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + const q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const q31_t *px0, *px1, *px2, *px3; + q63_t acc0v, acc1v, acc2v, acc3v; + q31x4_t x0v, x1v, x2v, x3v; + q31x4_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 2; + do + { + vst1q(pStateCurnt, vldrwq_s32(pSrc)); + pSrc += 4; + pStateCurnt += 4; + i--; + } + while (i > 0U); + + /* + * Clear all accumulators + */ + acc0v = 0LL; + acc1v = 0LL; + acc2v = 0LL; + acc3v = 0LL; + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_s32(pb); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + acc1v = vrmlaldavhaq(acc1v, x1v, c0v); + acc2v = vrmlaldavhaq(acc2v, x2v, c0v); + acc3v = vrmlaldavhaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_z_s32(pb, p0); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + acc1v = vrmlaldavhaq(acc1v, x1v, c0v); + acc2v = vrmlaldavhaq(acc2v, x2v, c0v); + acc3v = vrmlaldavhaq(acc3v, x3v, c0v); + } + + acc0v = asrl(acc0v, 31 - 8); + acc1v = asrl(acc1v, 31 - 8); + acc2v = asrl(acc2v, 31 - 8); + acc3v = asrl(acc3v, 31 - 8); + /* + * store in the destination buffer. + */ + *pDst++ = (q31_t) acc0v; + *pDst++ = (q31_t) acc1v; + *pDst++ = (q31_t) acc2v; + *pDst++ = (q31_t) acc3v; + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = 0LL; + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + c0v = vldrwq_s32(pb); + x0v = vldrwq_s32(px); + pb += 4; + px += 4; + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + c0v = vldrwq_z_s32(pb, p0); + x0v = vldrwq_z_s32(px, p0); + acc0v = vrmlaldavhaq_p(acc0v, x0v, c0v, p0); + } + acc0v = asrl(acc0v, 31 - 8); + + /* + * Advance the state pointer by the decimation factor + * * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = (q31_t) acc0v; + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + pStateCurnt = S->pState; + blkCnt = (numTaps - 1) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_s32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (numTaps - 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pStateCurnt, vldrwq_s32(pState), p0); + } +} +#else +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + *pDst++ = (q31_t) (acc1 >> 31); + *pDst++ = (q31_t) (acc2 >> 31); + *pDst++ = (q31_t) (acc3 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_decimate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c new file mode 100644 index 0000000..28a974e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c @@ -0,0 +1,944 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f16.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_F32_MAX_COEF_BLK 8 + +#define FIR_F16_CORE(pSamples, c, NB_TAPS) \ + vecAcc0 = vdupq_n_f16(0.0f16); \ + for (int i = 0; i < NB_TAPS; i++) { \ + vecIn0 = vld1q(&pSamples[i]); \ + vecAcc0 = vfmaq(vecAcc0, vecIn0, c[i]); \ + } + +#define NB_TAPS 4 +__STATIC_INLINE void arm_fir_f16_1_4_mve(const arm_fir_instance_f16 * S, + const float16_t * __restrict pSrc, + float16_t * __restrict pDst, uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCur; /* Points to the current sample of the state */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float16x8_t vecIn0; + float16x8_t vecAcc0; + float16_t c[NB_TAPS]; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + /* + * Copy new data into state so that we obtain a continuous sample buffer + * containing both the tail end of the old data and the new data. + */ + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = pCoeffs[i]; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 8; + pSamples += 8; + + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vstrhq_p_f16(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } + +} +#undef NB_TAPS + +#define NB_TAPS 8 +__STATIC_INLINE void arm_fir_f16_5_8_mve(const arm_fir_instance_f16 * S, + const float16_t * __restrict pSrc, + float16_t * __restrict pDst, uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCur; /* Points to the current sample of the state */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float16x8_t vecIn0; + float16x8_t vecAcc0; + float16_t c[NB_TAPS]; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + /* + * Copy new data into state so that we obtain a continuous sample buffer + * containing both the tail end of the old data and the new data. + */ + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = pCoeffs[i]; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 8; + pSamples += 8; + + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vstrhq_p_f16(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } + +} +#undef NB_TAPS + +void arm_fir_f16(const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pRefStatePtr = S->pState + ROUND_UP(blockSize, 8); + float16_t *pState = pRefStatePtr ; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + float16_t c0, c1, c2, c3; + float16_t c4, c5, c6, c7; + + /* + * [1 to 8 taps] specialized routines + */ + if (numTaps <= 4) { + arm_fir_f16_1_4_mve(S, pSrc, pDst, blockSize); + return; + } else if (numTaps <= 8) { + arm_fir_f16_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp16q(cnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 8; + pTempSrc += 8; + cnt -= 8; + } while (cnt > 0); + + float16_t *partial_accu_ptr = S->pState; + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrhq_p_f16(partial_accu_ptr, vecAcc0,p0); + } + + int localTaps = numTaps - FIR_F32_MAX_COEF_BLK; + int sample_offset = FIR_F32_MAX_COEF_BLK; + while (localTaps > FIR_F32_MAX_COEF_BLK) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + partial_accu_ptr = S->pState; + pSamples = pState + sample_offset; + int cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + vecAcc0 += vld1q_f16(partial_accu_ptr); + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vecAcc0 += vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(partial_accu_ptr, vecAcc0,p0); + } + + localTaps -= FIR_F32_MAX_COEF_BLK; + sample_offset += FIR_F32_MAX_COEF_BLK; + } + + pSamples = pState + sample_offset; + + if (localTaps > 4) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vst1q(pOutput, vecAcc0 + pap); + cnt--; + partial_accu_ptr += 8; + pOutput += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(pOutput, vecAcc0 + pap, p0); + pOutput += cnt; + } + + } else { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + pSamples += 8; + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vst1q(pOutput, vecAcc0 + pap); + cnt--; + partial_accu_ptr += 8; + pOutput += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(pOutput, vecAcc0 + pap, p0); + pOutput += cnt; + } + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0U) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else + +void arm_fir_f16( + const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCurnt; /* Points to the current sample of the state */ + float16_t *px; /* Temporary pointer for state buffer */ + const float16_t *pb; /* Temporary pointer for coefficient buffer */ + _Float16 acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + _Float16 x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + _Float16 c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (_Float16)*px++ * (_Float16)*pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +#endif /* #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** +* @} end of FIR group +*/ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c new file mode 100644 index 0000000..8fcc5ae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c @@ -0,0 +1,1289 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f32.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR Finite Impulse Response (FIR) Filters + + This set of functions implements Finite Impulse Response (FIR) filters + for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays containing blockSize values. + + @par Algorithm + The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. + Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ @par + \image html FIR.GIF "Finite Impulse Response filter" + @par + pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the following order. + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[n](==pSrc[0]), x[n+1](==pSrc[1]), ..., x[n+blockSize-1](==pSrc[blockSize-1])}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. + The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + @par Initialization of Helium version + For Helium version the array of coefficients must be padded with zero to contain + a full number of lanes. + + The array length L must be a multiple of x. L = x * a : + - x is 4 for f32 + - x is 4 for q31 + - x is 4 for f16 (so managed like the f32 version and not like the q15 one) + - x is 8 for q15 + - x is 16 for q7 + + The additional coefficients + (x * a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first A samples are temporary data. + The remaining samples are the state of the FIR filter. + @par + So the state buffer has size numTaps + A + blockSize - 1 : + - A is blockSize for f32 + - A is 8*ceil(blockSize/8) for f16 + - A is 8*ceil(blockSize/4) for q31 + - A is 0 for other datatypes (q15 and q7) + + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_F32_MAX_COEF_BLK 8 + +#define FIR_F32_CORE(pSamples, c, NB_TAPS) \ + vecAcc0 = vdupq_n_f32(0.0f); \ + for (int i = 0; i < NB_TAPS; i++) { \ + vecIn0 = vld1q(&pSamples[i]); \ + vecAcc0 = vfmaq(vecAcc0, vecIn0, c[i]); \ + } + + +#define NB_TAPS 4 +__STATIC_INLINE void arm_fir_f32_1_4_mve(const arm_fir_instance_f32 * S, + const float32_t * __restrict pSrc, + float32_t * __restrict pDst, uint32_t blockSize) +{ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + float32_t *pOutput; /* Temporary pointer to the output buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float32x4_t vecIn0; + float32x4_t vecAcc0; + float32_t c[NB_TAPS]; + const float32_t *pCoeffsCur = pCoeffs; + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + + pSamples = pState; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = *pCoeffsCur++; + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + FIR_F32_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 4; + pSamples += 4; + + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + FIR_F32_CORE(pSamples, c, NB_TAPS); + + vstrwq_p_f32(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps - 1; + do { + mve_pred16_t p = vctp32q(blkCnt); + + vstrwq_p_f32(pTempDest, vldrwq_z_f32(pTempSrc, p), p); + pTempSrc += 4; + pTempDest += 4; + blkCnt -= 4; + } + while (blkCnt > 0); +} +#undef NB_TAPS + +__STATIC_INLINE void arm_fir_f32_5_8_mve(const arm_fir_instance_f32 * S, + const float32_t * __restrict pSrc, + float32_t * __restrict pDst, uint32_t blockSize) +{ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float32_t c0, c1, c2, c3; + float32_t c4, c5, c6, c7; + + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp32q(cnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 4; + pTempSrc += 4; + cnt -= 4; + } while(cnt > 0); + + + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 2; + while(cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vst1q(pDst, vecAcc0); + cnt--; + pDst += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrwq_p_f32(pDst, vecAcc0,p0); + } + + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + blkCnt = numTaps; + while (blkCnt > 0) + { + *pTempDest++ = *pTempSrc++; + blkCnt--; + } +} + + + +void arm_fir_f32( +const arm_fir_instance_f32 * S, +const float32_t * pSrc, +float32_t * pDst, +uint32_t blockSize) +{ + /* + S->pState is the arm_fir_partial_accu + S->pState + blockSize is the FIR state + */ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr ; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + float32_t *pOutput; /* Temporary pointer to the output buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + float32_t c0, c1, c2, c3; + float32_t c4, c5, c6, c7; + + /* + * [1 to 8 taps] specialized routines + */ + if (numTaps <= 4) + { + arm_fir_f32_1_4_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 8) + { + arm_fir_f32_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp32q(cnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 4; + pTempSrc += 4; + cnt -= 4; + } while(cnt > 0); + + float32_t *partial_accu_ptr = S->pState; + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrwq_p_f32(partial_accu_ptr, vecAcc0,p0); + } + + int localTaps = numTaps - FIR_F32_MAX_COEF_BLK; + int sample_offset = FIR_F32_MAX_COEF_BLK; + while (localTaps > FIR_F32_MAX_COEF_BLK) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + partial_accu_ptr = S->pState; + pSamples = pState + sample_offset; + int cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vecAcc0 += vld1q_f32(partial_accu_ptr); + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vecAcc0 += vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(partial_accu_ptr, vecAcc0,p0); + } + + localTaps -= FIR_F32_MAX_COEF_BLK; + sample_offset += FIR_F32_MAX_COEF_BLK; + } + + pSamples = pState + sample_offset; + + if (localTaps > 4) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vst1q(pOutput, vecAcc0+pap); + cnt--; + partial_accu_ptr += 4; + pOutput += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(pOutput, vecAcc0+pap,p0); + pOutput += cnt; + } + } + else { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + pSamples += 4; + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vst1q(pOutput, vecAcc0+pap); + cnt--; + partial_accu_ptr += 4; + pOutput += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(pOutput, vecAcc0+pap,p0); + pOutput += cnt; + } + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pRefStatePtr[blockSize]; + pTempDest = pRefStatePtr; + + blkCnt = numTaps >> 2; + while (blkCnt > 0) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = numTaps & 3; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +#if defined(ARM_MATH_NEON) + +void arm_fir_f32( +const arm_fir_instance_f32 * S, +const float32_t * pSrc, +float32_t * pDst, +uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointers for state buffer */ + const float32_t *pb; /* Temporary pointers for coefficient buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + + float32x4_t accv0,accv1,samples0,samples1,x0,x1,x2,xa,xb,b; + float32_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop unrolling */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + /* Copy 8 samples at a time into state buffers */ + samples0 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples0); + + pStateCurnt += 4; + pSrc += 4 ; + + samples1 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples1); + + pStateCurnt += 4; + pSrc += 4 ; + + /* Set the accumulators to zero */ + accv0 = vdupq_n_f32(0); + accv1 = vdupq_n_f32(0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Loop unroling */ + i = numTaps >> 2; + + /* Perform the multiply-accumulates */ + x0 = vld1q_f32(px); + x1 = vld1q_f32(px + 4); + + while(i > 0) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + x2 = vld1q_f32(px + 8); + b = vld1q_f32(pb); + xa = x0; + xb = x1; + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 0)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 0)); + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 1)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 1)); + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 2)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 2)); + + xa = vextq_f32(x0,x1,3); + xb = vextq_f32(x1,x2,3); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 3)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 3)); + + pb += 4; + x0 = x1; + x1 = x2; + px += 4; + i--; + + } + + /* Tail */ + i = numTaps & 3; + x2 = vld1q_f32(px + 8); + + /* Perform the multiply-accumulates */ + switch(i) + { + case 3: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + pb++; + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 2: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 1: + { + + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + } + break; + default: + break; + } + + /* The result is stored in the destination buffer. */ + vst1q_f32(pDst,accv0); + pDst += 4; + vst1q_f32(pDst,accv1); + pDst += 4; + + /* Advance state pointer by 8 for the next 8 samples */ + pState = pState + 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc += *px++ * *pb++; + i--; + + } while (i > 0U); + + /* The result is stored in the destination buffer. */ + *pDst++ = acc; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy numTaps number of values */ + tapCnt = numTaps - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + float32_t x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + float32_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** +* @} end of FIR group +*/ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c new file mode 100644 index 0000000..2aaa4fb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c @@ -0,0 +1,133 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f64.c + * Description: Floating-point FIR filter processing function + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_f64( + const arm_fir_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + float64_t *pState = S->pState; /* State pointer */ + const float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t *pStateCurnt; /* Points to the current sample of the state */ + float64_t *px; /* Temporary pointer for state buffer */ + const float64_t *pb; /* Temporary pointer for coefficient buffer */ + float64_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** +* @} end of FIR group +*/ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c new file mode 100644 index 0000000..d33fb86 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c @@ -0,0 +1,336 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q15.c + * Description: Q15 Fast FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter (fast version). + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + + @remark + Refer to \ref arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q15() to initialize the filter structure. + */ + +void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc2 = __SMLAD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLADX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + do + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + while (tapCnt > 0U); + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c new file mode 100644 index 0000000..d50f463 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c @@ -0,0 +1,326 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q31.c + * Description: Processing function for the Q31 Fast FIR filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q31 FIR filter (fast version). + @param[in] S points to an instance of the Q31 structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + + @remark + Refer to \ref arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q31() to initialize the filter structure. + */ + +void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + multAcc_32x32_keep32_R(acc0, x0, c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + multAcc_32x32_keep32_R(acc1, x1, c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + multAcc_32x32_keep32_R(acc2, x2, c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x1, c0); + multAcc_32x32_keep32_R(acc1, x2, c0); + multAcc_32x32_keep32_R(acc2, x3, c0); + multAcc_32x32_keep32_R(acc3, x0, c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x2, c0); + multAcc_32x32_keep32_R(acc1, x3, c0); + multAcc_32x32_keep32_R(acc2, x0, c0); + multAcc_32x32_keep32_R(acc3, x1, c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x3, c0); + multAcc_32x32_keep32_R(acc1, x0, c0); + multAcc_32x32_keep32_R(acc2, x1, c0); + multAcc_32x32_keep32_R(acc3, x2, c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x0, c0); + multAcc_32x32_keep32_R(acc1, x1, c0); + multAcc_32x32_keep32_R(acc2, x2, c0); + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + multAcc_32x32_keep32_R(acc0, (*px++), (*pb++)); + i--; + } while (i > 0U); + + /* The result is in 2.30 format. Convert to 1.31 + Then store the output in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c new file mode 100644 index 0000000..2bc43b5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c @@ -0,0 +1,109 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f16.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f16(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 8*ceil(blockSize/8) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/8) + blockSize - 1 + + */ + +void arm_fir_init_f16( + arm_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + ROUND_UP(blockSize, 8)) * sizeof(float16_t)); +#else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float16_t)); +#endif + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c new file mode 100644 index 0000000..cbc3989 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c @@ -0,0 +1,103 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f32.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables and some working memory for the Helium version. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f32(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first blockSize samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 2 * blockSize - 1 + + */ + +void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + blockSize) * sizeof(float32_t)); +#else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); +#endif + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c new file mode 100644 index 0000000..16ca036 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c @@ -0,0 +1,88 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f64.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f64(). + + @par + There is no Helium version of the fir F64. + + */ + +void arm_fir_init_f64( + arm_fir_instance_f64 * S, + uint16_t numTaps, + const float64_t * pCoeffs, + float64_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float64_t)); + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c new file mode 100644 index 0000000..6853f1f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c @@ -0,0 +1,149 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q15.c + * Description: Q15 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q15 FIR filter. + @param[in,out] S points to an instance of the Q15 FIR filter structure. + @param[in] numTaps number of filter coefficients in the filter. Must be even and greater than or equal to 4. + @param[in] pCoeffs points to the filter coefficients buffer. + @param[in] pState points to the state buffer. + @param[in] blockSize number of samples processed per call. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : numTaps is not greater than or equal to 4 and even + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ Note that numTaps must be even and greater than or equal to 4. + To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. + For example, to implement a filter with numTaps=3 and coefficients + 
+      {0.3, -0.8, 0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.8, 0.3, 0}.
+
+ Similarly, to implement a two point filter + 
+      {0.3, -0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.3, 0, 0}.
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 8 (8a) even if less + then 8a coefficients are defined in the FIR. The additional coefficients + (8a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + */ + +arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + +#if defined (ARM_MATH_DSP) + + /* The Number of filter coefficients in the filter must be even and at least 4 */ + if (numTaps & 0x1U) + { + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps ) */ + memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +#else + + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c new file mode 100644 index 0000000..de44f74 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c @@ -0,0 +1,104 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q31.c + * Description: Q31 FIR filter initialization function. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q31 FIR filter. + @param[in,out] S points to an instance of the Q31 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_q31(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 2*4*ceil(blockSize/4) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/4) + blockSize - 1 + + */ + +void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + 2*ROUND_UP(blockSize, 4)) * sizeof(q31_t)); + #else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + #endif + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c new file mode 100644 index 0000000..db14670 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c @@ -0,0 +1,94 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q7.c + * Description: Q7 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q7 FIR filter. + @param[in,out] S points to an instance of the Q7 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 16 (16a) even if less + then 16a coefficients are defined in the FIR. The additional coefficients + (16a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + */ + +void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c new file mode 100644 index 0000000..ddff5c2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c @@ -0,0 +1,1256 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_f32.c + * Description: Floating-point FIR interpolation sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator + + These functions combine an upsampler (zero stuffer) and an FIR filter. + They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions" + After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized + cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. + The user of the function is responsible for providing the filter coefficients. + + The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. + The upsampler inserts L-1 zeros between each sample. + Instead of multiplying by these zero values, the FIR filter is designed to skip them. + This leads to an efficient implementation without any wasted effort. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize*L output values. + + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Algorithm + The functions use a polyphase filter structure: + 
+      y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+      y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+      ...
+      y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+
+ This approach is more efficient than straightforward upsample-then-filter algorithms. + With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. + @par + pCoeffs points to a coefficient array of size numTaps. + numTaps must be a multiple of the interpolation factor L and this is checked by the + initialization functions. + Internally, the function divides the FIR filter's impulse response into shorter filters of length + phaseLength=numTaps/L. + Coefficients are stored in time reversed order. + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size blockSize + phaseLength - 1. + Samples in the state buffer are stored in the order: + 
+     {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the length of the filter is a multiple of the interpolation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+
+ @par + where L is the interpolation factor; phaseLength=numTaps/L is the + length of each of the shorter FIR filters used internally, + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for floating-point FIR interpolator. + @param[in] S points to an instance of the floating-point FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +static void arm_fir_interpolate2_f32_mve( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + uint32_t tapCnt; + uint32_t blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * 2, 2 * 2, 3 * 2 }; + uint32x4_t vec_strides0 = vld1q_u32(strides); + uint32x4_t vec_strides1 = vec_strides0 + 1; + f32x4_t acc0, acc1; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (phaseLen - 1U); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Initialize state pointer + */ + ptr1 = pState; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs; + + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef, vecState; + + vecState = vldrwq_f32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides1); + acc1 = vfmaq_f32(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides0); + acc0 = vfmaq_f32(acc0, vecState, vecCoef); + + ptr2 += 4 * 2; + ptr1 += 4; + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef, vecState; + + vecState = vldrwq_z_f32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides1, p0); + acc1 = vfmaq_f32(acc1, vecState, vecCoef); + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides0, p0); + acc0 = vfmaq_f32(acc0, vecState, vecCoef); + + } + *pDst++ = vecAddAcrossF32Mve(acc1); + *pDst++ = vecAddAcrossF32Mve(acc0); + + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + uint32_t tapCnt; + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * S->L, 2 * S->L, 3 * S->L }; + uint32_t stridesM[4] = { 4, 3, 2, 1 }; + uint32x4_t vec_stridesM = vld1q_u32(stridesM); + uint32x4_t vec_strides = vld1q_u32(strides); + f32x4_t acc; + + + if ( S->L == 2 ) { + arm_fir_interpolate2_f32_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + */ + /* + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (phaseLen - 1U); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + float32_t state0, state1, state2, state3; + acc = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U) - 4; + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef; + const float32_t *pCoef = ptr2; + + state0 = ptr1[0]; + state1 = ptr1[1]; + state2 = ptr1[2]; + state3 = ptr1[3]; + ptr1 += 4; + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state0); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state1); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state2); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state3); + + ptr2 = ptr2 + 4 * S->L; + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef; + const float32_t *pCoef = ptr2; + + state0 = ptr1[0]; + state1 = ptr1[1]; + state2 = ptr1[2]; + state3 = ptr1[3]; + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state1); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state2); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state3); + } + + vst1q(pDst, acc); + pDst += 4; + i -= 4; + } + else + { + acc = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef, vecState; + + vecState = vldrwq_f32(ptr1); + ptr1 += 4; + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides); + ptr2 += 4 * S->L; + acc = vfmaq_f32(acc, vecState, vecCoef); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef, vecState; + + vecState = vldrwq_z_f32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides, p0); + acc = vfmaq_f32(acc, vecState, vecCoef); + } + *pDst++ = vecAddAcrossF32Mve(acc); + /* + * Decrement the loop counter + */ + i--; + } + } + + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} + +#else +#if defined(ARM_MATH_NEON) +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointers for state buffer */ + const float32_t *ptr2; /* Temporary pointers for coefficient buffer */ + float32_t sum0; /* Accumulators */ + float32_t c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt, j; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + uint32_t blkCntN4; + float32_t c1, c2, c3; + + float32x4_t sum0v; + float32x4_t accV0,accV1; + float32x4_t x0v,x1v,x2v,xa,xb; + float32x2_t tempV; + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (phaseLen - 1U); + + /* Initialise blkCnt */ + blkCnt = blockSize >> 3; + blkCntN4 = blockSize & 7; + + /* Loop unrolling */ + while (blkCnt > 0U) + { + /* Copy new input samples into the state buffer */ + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + accV0 = vdupq_n_f32(0.0); + accV1 = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0v = vld1q_f32(ptr1); + x1v = vld1q_f32(ptr1 + 4); + + while (tapCnt > 0U) + { + /* Read the input samples */ + x2v = vld1q_f32(ptr1 + 8); + + /* Read the coefficients */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c1 = *(ptr2 + S->L); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c1); + accV1 = vmlaq_n_f32(accV1,xb,c1); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c2 = *(ptr2 + S->L * 2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c2); + accV1 = vmlaq_n_f32(accV1,xb,c2); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c3 = *(ptr2 + S->L * 3); + + xa = vextq_f32(x0v,x1v,3); + xb = vextq_f32(x1v,x2v,3); + + accV0 = vmlaq_n_f32(accV0,xa,c3); + accV1 = vmlaq_n_f32(accV1,xb,c3); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + ptr1 += 4; + x0v = x1v; + x1v = x2v; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + x2v = vld1q_f32(ptr1 + 8); + + switch (tapCnt) + { + case 3: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 2: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 1: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + break; + + default: + break; + + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst = vgetq_lane_f32(accV0, 0); + *(pDst + S->L) = vgetq_lane_f32(accV0, 1); + *(pDst + 2 * S->L) = vgetq_lane_f32(accV0, 2); + *(pDst + 3 * S->L) = vgetq_lane_f32(accV0, 3); + + *(pDst + 4 * S->L) = vgetq_lane_f32(accV1, 0); + *(pDst + 5 * S->L) = vgetq_lane_f32(accV1, 1); + *(pDst + 6 * S->L) = vgetq_lane_f32(accV1, 2); + *(pDst + 7 * S->L) = vgetq_lane_f32(accV1, 3); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 8; + + pDst += S->L * 7; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + + while (blkCntN4 > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,0); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0v = vld1q_f32(ptr1); + ptr1 += 4; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,1); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,3); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0v = vmlaq_f32(sum0v,x0v,x1v); + + /* Decrement the loop counter */ + tapCnt--; + } + + tempV = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *(ptr1++) * (*ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = (phaseLen - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (phaseLen - 1U) % 0x04U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; + float32_t x0, x1, x2, x3; + float32_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c1; + acc1 += x2 * c1; + acc2 += x3 * c1; + acc3 += x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x2 * c2; + acc1 += x3 * c2; + acc2 += x0 * c2; + acc3 += x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x3 * c3; + acc1 += x0 * c3; + acc2 += x1 * c3; + acc3 += x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = acc0; + *(pDst + S->L) = acc1; + *(pDst + 2 * S->L) = acc2; + *(pDst + 3 * S->L) = acc3; + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of FIR_Interpolate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c new file mode 100644 index 0000000..cfbf102 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c @@ -0,0 +1,110 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_f32.c + * Description: Floating-point FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR interpolator. + @param[in,out] S points to an instance of the floating-point FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ @par + The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). + */ + +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c new file mode 100644 index 0000000..f016592 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c @@ -0,0 +1,110 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q15.c + * Description: Q15 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR interpolator. + @param[in,out] S points to an instance of the Q15 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). + */ + +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c new file mode 100644 index 0000000..cd40905 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c @@ -0,0 +1,109 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q31.c + * Description: Q31 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR interpolator. + @param[in,out] S points to an instance of the Q31 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). + */ + +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c new file mode 100644 index 0000000..21691ee --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c @@ -0,0 +1,778 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q15.c + * Description: Q15 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q15 FIR interpolator. + @param[in] S points to an instance of the Q15 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + const q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint16_t strides[8] = { + 0, 1 * S->L, 2 * S->L, 3 * S->L, + 4 * S->L, 5 * S->L, 6 * S->L, 7 * S->L + }; + uint16x8_t vec_strides0 = *(uint16x8_t *) strides; + uint16x8_t vec_strides1 = vec_strides0 + 1; + uint16x8_t vec_strides2 = vec_strides0 + 2; + uint16x8_t vec_strides3 = vec_strides0 + 3; + q15x8_t vecState, vecCoef; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + ((q15_t) phaseLen - 1); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1 - 3U); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + q63_t acc3 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides3); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides2); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc3 = vmlaldavaq(acc3, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides3, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides2, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc3 = vmlaldavaq(acc3, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16); + *pDst++ = (q15_t) __SSAT(acc1, 16); + *pDst++ = (q15_t) __SSAT(acc2, 16); + *pDst++ = (q15_t) __SSAT(acc3, 16); + i -= 4; + } + else if (i >= 3) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 2); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides2); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides2, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16);; + *pDst++ = (q15_t) __SSAT(acc1, 16);; + *pDst++ = (q15_t) __SSAT(acc2, 16);; + i -= 3; + } + else if (i >= 2) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 1); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16); + *pDst++ = (q15_t) __SSAT(acc1, 16); + i -= 2; + } + else + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + q63_t acc0 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + *pDst++ = (q15_t) __SSAT(acc0, 16); + /* + * Decrement the loop counter + */ + i--; + } + } + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + * This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pStateCurnt, vldrhq_s16(pState)); + pState += 8; + pStateCurnt += 8; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pStateCurnt, vldrhq_s16(pState), p0); + } +} +#else +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q15_t x0, x1, x2, x3; + q15_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q15_t) (__SSAT((acc0 >> 15), 16)); + *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16)); + *(pDst + 2 * S->L) = (q15_t) (__SSAT((acc2 >> 15), 16)); + *(pDst + 3 * S->L) = (q15_t) (__SSAT((acc3 >> 15), 16)); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result after converting to 1.15 format in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI)*/ +/** + @} end of FIR_Interpolate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c new file mode 100644 index 0000000..edd0c70 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c @@ -0,0 +1,777 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q31.c + * Description: Q31 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q31 FIR interpolator. + @param[in] S points to an instance of the Q31 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). + since numTaps/L additions occur per output sample. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + const q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * S->L, 2 * S->L, 3 * S->L }; + uint32x4_t vec_strides0 = vld1q_u32(strides); + uint32x4_t vec_strides1 = vec_strides0 + 1; + uint32x4_t vec_strides2 = vec_strides0 + 2; + uint32x4_t vec_strides3 = vec_strides0 + 3; + q31x4_t vecState, vecCoef; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + ((q31_t) phaseLen - 1); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1 - 3U); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + q63_t acc3 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides3); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides2); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc3 = vrmlaldavhaq(acc3, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides3, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides2, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc3 = vrmlaldavhaq(acc3, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + acc2 = asrl(acc2, 31 - 8); + acc3 = asrl(acc3, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + *pDst++ = (q31_t) acc3; + i -= 4; + } + else if (i >= 3) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 2); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides2); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides2, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + acc2 = asrl(acc2, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + i -= 3; + } + else if (i >= 2) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 1); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + i -= 2; + } + else + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + q63_t acc0 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + *pDst++ = (q31_t) acc0; + /* + * Decrement the loop counter + */ + i--; + } + } + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_s32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pStateCurnt, vldrwq_s32(pState), p0); + } +} +#else +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q31_t x0, x1, x2, x3; + q31_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q31_t) (acc0 >> 31); + *(pDst + S->L) = (q31_t) (acc1 >> 31); + *(pDst + 2 * S->L) = (q31_t) (acc2 >> 31); + *(pDst + 3 * S->L) = (q31_t) (acc3 >> 31); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_Interpolate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c new file mode 100644 index 0000000..9655bb0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c @@ -0,0 +1,460 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_f32.c + * Description: Processing function for floating-point FIR Lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters + + @deprecated Those functions are no more tested nor maintained and will be removed in + a future version. + + This set of functions implements Finite Impulse Response (FIR) lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure is feedforward and + the net impulse response is finite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html FIRLattice.gif "Finite Impulse Response Lattice filter" + The following difference equation is implemented: + @par + 
+      f0[n] = g0[n] = x[n]
+      fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+      gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+      y[n] = fM[n]
+
+ @par + pCoeffs points to tha array of reflection coefficients of size numStages. + Reflection Coefficients are stored in the following order. + @par + 
+      {k1, k2, ..., kM}
+
+ where M is number of stages + @par + pState points to a state array of size numStages. + The state variables (g values) hold previous inputs and are stored in the following order. + 
+    {g0[n], g1[n], g2[n] ...gM-1[n]}
+
+ The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+
+ @par + where numStages is the number of stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Temporary state pointer */ + const float32_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + float32_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + float32_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + float32_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk)) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (fcurr0 * (*pk)) + fcurr1; + gnext1 = (fcurr1 * (*pk)) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (fcurr1 * (*pk)) + fcurr2; + gnext2 = (fcurr2 * (*pk)) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (fcurr2 * (*pk )) + fcurr3; + gnext3 = (fcurr3 * (*pk++)) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g2(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g3(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + fnext1 = (gnext0 * (*pk)) + fcurr1; + + fnext2 = (gnext1 * (*pk)) + fcurr2; + + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +} + +/** + @} end of FIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c new file mode 100644 index 0000000..2e7b6a4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c @@ -0,0 +1,74 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_f32.c + * Description: Floating-point FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c new file mode 100644 index 0000000..27fe5ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c @@ -0,0 +1,74 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q15.c + * Description: Q15 FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c new file mode 100644 index 0000000..c2f29d2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c @@ -0,0 +1,74 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q31.c + * Description: Q31 FIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c new file mode 100644 index 0000000..dbb91c2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c @@ -0,0 +1,510 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q15.c + * Description: Q15 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary state pointer */ + const q15_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Process second sample for first tap */ + fnext1 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr0; + gnext1 = __SSAT(gnext1, 16); + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + fcurr1; + gnext2 = __SSAT(gnext2, 16); + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) ((fcurr2 * (*pk )) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + gnext3 = (q31_t) ((fcurr3 * (*pk++)) >> 15U) + fcurr2; + gnext3 = __SSAT(gnext3, 16); + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = (q15_t) fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(fcurr0, fcurr1, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr2, fcurr3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(fcurr1, fcurr0, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr3, fcurr2, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save g1(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save f0(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c new file mode 100644 index 0000000..e5de1f7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c @@ -0,0 +1,509 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q31.c + * Description: Q31 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. + */ + +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Temporary state pointer */ + const q31_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk )) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk++)) >> 32U); + gnext3 = (gnext3 << 1U) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save f0(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c new file mode 100644 index 0000000..f197d15 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c @@ -0,0 +1,736 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q15.c + * Description: Q15 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter. + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_fast_q15() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + + +#define FIR_Q15_CORE(pOutput, nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q15_t *pSmp = &pSample[j]; \ + q63_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 8 * i); \ + acc[j] = vmlaldavaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc[j], 15); \ + } + +#define FIR_Q15_MAIN_CORE() \ +{ \ + q15_t *pState = S->pState; /* State pointer */ \ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q15_t *pStateCur; /* Points to the current sample of the state */ \ + const q15_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q15_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q15_t *pTempSrc; /* Temporary pointer to the source data */ \ + q15_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + q15x8_t vecIn0; \ + \ + /* \ + * load coefs \ + */ \ + q15x8_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vldrhq_s16(pCoeffs + 8 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrhq_s32(pStateCur, vldrhq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q15_CORE(pOutput, 4, NBVECTAPS, pSamples, vecCoeffs); \ + pSamples += 4; \ + \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q15_CORE(pOutput, residual, NBVECTAPS, pSamples, vecCoeffs); \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + \ + /* current compiler limitation */ \ + blkCnt = (numTaps - 1) >> 3; \ + while (blkCnt > 0) \ + { \ + vstrhq_s16(pTempDest, vldrhq_s16(pTempSrc)); \ + pTempSrc += 8; \ + pTempDest += 8; \ + blkCnt--; \ + } \ + blkCnt = (numTaps - 1) & 7; \ + if (blkCnt > 0) \ + { \ + mve_pred16_t p = vctp16q(blkCnt); \ + vstrhq_p_s16(pTempDest, vldrhq_z_s16(pTempSrc, p), p); \ + } \ +} + +static void arm_fir_q15_25_32_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 32 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q15_17_24_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 24 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q15_9_16_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q15_1_8_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 8 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + const q15_t *pSamples; /* Temporary pointer to the sample buffer */ + q15_t *pOutput; /* Temporary pointer to the output buffer */ + const q15_t *pTempSrc; /* Temporary pointer to the source data */ + q15_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q15x8_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 7) / 8; + q63_t acc0, acc1, acc2, acc3; + + +int32_t nbTaps = (numTaps + 7) >> 3; + +switch(nbTaps) { + + case 1: + arm_fir_q15_1_8_mve(S, pSrc, pDst, blockSize); + return; + case 2: + arm_fir_q15_9_16_mve(S, pSrc, pDst, blockSize); + return; + case 3: + arm_fir_q15_17_24_mve(S, pSrc, pDst, blockSize); + return; + case 4: + arm_fir_q15_25_32_mve(S, pSrc, pDst, blockSize); + return; + } + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + pOutput = pDst; + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vmlaldavaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vmlaldavaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc3, 15); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + *(q15x8_t *) pStateCur = *(q15x8_t *) pTempSrc; + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc2 = vmlaldavaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + } + break; + + case 2: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + } + break; + + case 1: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia (&pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia (&pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia (&pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLALD(x0, c0, acc0); + acc2 = __SMLALD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLALDX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + while (tapCnt > 0U) + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c new file mode 100644 index 0000000..16bd7e9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c @@ -0,0 +1,1166 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q31.c + * Description: Q31 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q31 FIR filter. + @param[in] S points to an instance of the Q31 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_fir_fast_q31() for a faster but less precise implementation of this filter. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +#define FIR_Q31_CORE(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + q63_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q31_t)asrl(acc[j], 23); \ + } + + +#define FIR_Q31_CORE_STR_PARTIAL(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *arm_fir_partial_accu_ptr++ = acc[j]; \ + } + + +#define FIR_Q31_CORE_LD_PARTIAL(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + \ + acc[j] = *arm_fir_partial_accu_ptr++; \ + \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q31_t)asrl(acc[j], 23); \ + } + + +#define FIR_Q31_MAIN_CORE() \ +{ \ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); \ + q31_t *pState = pRefStatePtr; /* State pointer */ \ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q31_t *pStateCur; /* Points to the current sample of the state */ \ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q31_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ \ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + \ + /* \ + * load coefs \ + */ \ + q31x4_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vld1q(pCoeffs + 4 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrwq_s32(pStateCur, vldrwq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q31_CORE(4, NBVECTAPS, pSamples, vecCoeffs); \ + \ + pSamples += 4; \ + /* \ + * Decrement the sample block loop counter \ + */ \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + switch (residual) { \ + case 3: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(3, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + \ + case 2: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(2, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + \ + case 1: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(1, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + } \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + \ + blkCnt =(numTaps - 1) >> 2; \ + while (blkCnt > 0) \ + { \ + vstrwq_s32(pTempDest, vldrwq_s32(pTempSrc)); \ + pTempSrc += 4; \ + pTempDest += 4; \ + blkCnt--; \ + } \ + blkCnt = (numTaps - 1) & 3; \ + if (blkCnt > 0) \ + { \ + mve_pred16_t p0 = vctp32q(blkCnt); \ + vstrwq_p_s32(pTempDest, vldrwq_z_s32(pTempSrc, p0), p0); \ + } \ +} + +static void arm_fir_q31_1_4_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q31x4_t vecIn0; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + pOutput = pDst; + + q63_t acc0=0, acc1=0, acc2=0, acc3=0; + /* + * load 4 coefs + */ + q31x4_t vecCoeffs = *(q31x4_t *) pCoeffs; + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + const q31_t *pSamplesTmp = pSamples; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + *pOutput++ = (q31_t) acc3; + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + /* + * Save 4 input samples in the history buffer + */ + *(q31x4_t *) pStateCur = *(q31x4_t *) pTempSrc; + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[2]); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + } + break; + + case 2: + { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + } + break; + + case 1: + { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + + *pOutput++ = (q31_t) acc0; + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = (numTaps-1) >> 2; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = (numTaps-1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pTempDest, vld1q(pTempSrc), p0); + } +} + + + +static void arm_fir_q31_5_8_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 8 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_9_12_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 12 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_13_16_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_17_20_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 20 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_21_24_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 24 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_25_28_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 28 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q31_29_32_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, + uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + q63_t acc0, acc1, acc2, acc3; + +#define MAX_VECT_BATCH 7 + + /* + * pre-load 28 1st coefs + */ + q31x4_t vecCoeffs0 = vld1q(pCoeffs + 4 * 0); + q31x4_t vecCoeffs1 = vld1q(pCoeffs + 4 * 1); + q31x4_t vecCoeffs2 = vld1q(pCoeffs + 4 * 2); + q31x4_t vecCoeffs3 = vld1q(pCoeffs + 4 * 3); + q31x4_t vecCoeffs4 = vld1q(pCoeffs + 4 * 4); + q31x4_t vecCoeffs5 = vld1q(pCoeffs + 4 * 5); + q31x4_t vecCoeffs6 = vld1q(pCoeffs + 4 * 6); + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + + q63_t *arm_fir_partial_accu_ptr = (q63_t*)S->pState; + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + /* + * Save 4 input samples in the history buffer + */ + vstrwq_s32(pStateCur, vldrwq_s32(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + const q31_t *pSmp; + q31x4_t vecIn0; + + pSmp = &pSamples[0]; + + vecIn0 = vld1q(pSmp); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc0; + + pSmp = &pSamples[1]; + + vecIn0 = vld1q(pSmp); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc1; + + pSmp = &pSamples[2]; + + vecIn0 = vld1q(pSmp); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs6); + *arm_fir_partial_accu_ptr++ = acc2; + + pSmp = &pSamples[3]; + + vecIn0 = vld1q(pSmp); + acc3 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc3; + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + + /* reminder */ + + /* load last 4 coef */ + vecCoeffs0 = vld1q(pCoeffs + 4 * MAX_VECT_BATCH); + arm_fir_partial_accu_ptr = (q63_t*)S->pState; + pOutput = pDst; + pSamples = pState + (MAX_VECT_BATCH * 4); + + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + q31x4_t vecIn0; + + /* reload intermediate MAC */ + acc0 = *arm_fir_partial_accu_ptr++; + acc1 = *arm_fir_partial_accu_ptr++; + acc2 = *arm_fir_partial_accu_ptr++; + acc3 = *arm_fir_partial_accu_ptr++; + + + vecIn0 = vld1q(&pSamples[0]); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[3]); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs0); + + *pOutput++ = asrl(acc0, 23); + *pOutput++ = asrl(acc1, 23); + *pOutput++ = asrl(acc2, 23); + *pOutput++ = asrl(acc3, 23); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps - 1; + do { + mve_pred16_t p = vctp32q(blkCnt); + + vstrwq_p_s32(pTempDest, vldrwq_z_s32(pTempSrc, p), p); + pTempSrc += 4; + pTempDest += 4; + blkCnt -= 4; + } + while (blkCnt > 0); +} + + + +void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q31x4_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 3) / 4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecCoeffs; + + + /* + * [1 to 32 taps] specialized routines + */ + if (numTaps <= 4) + { + arm_fir_q31_1_4_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 8) + { + arm_fir_q31_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 12) + { + arm_fir_q31_9_12_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 16) + { + arm_fir_q31_13_16_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 20) + { + arm_fir_q31_17_20_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 24) + { + arm_fir_q31_21_24_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 28) + { + arm_fir_q31_25_28_mve(S, pSrc, pDst, blockSize); + return; + } + else if ((numTaps <= 32) && (blockSize >= 32)) + { + arm_fir_q31_29_32_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 4 coefs + */ + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + /* + * Decrement the taps block loop counter + */ + i--; + } + + /* .54-> .31 conversion and store accumulators */ + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + *pOutput++ = (q31_t) acc3; + + pSamples += 4; + + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + int32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + *(q31x4_t *) pStateCur = *(q31x4_t *) pTempSrc; + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + } + break; + + case 2: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + } + break; + + case 1: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + + *pOutput++ = (q31_t) acc0; + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = (numTaps - 1U) >> 2; + while (blkCnt > 0) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = (numTaps - 1U) & 3; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2; /* Temporary variables to hold state values */ + q31_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize / 3; + + while (blkCnt > 0U) + { + /* Copy 3 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 2 samples from the state buffer: x[n-numTaps], x[n-numTaps-1] */ + x0 = *px++; + x1 = *px++; + + /* Loop unrolling: process 3 taps at a time. */ + tapCnt = numTaps / 3; + + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-2] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 1U); + x0 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x1 * c0); + acc1 += ((q63_t) x2 * c0); + acc2 += ((q63_t) x0 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 2U); + x1 = *(px++); + + /* update coefficient pointer */ + pb += 3U; + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x2 * c0); + acc1 += ((q63_t) x0 * c0); + acc2 += ((q63_t) x1 * c0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x3U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 3 to process the next group of 3 samples */ + pState = pState + 3; + + /* The result is in 2.30 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + *pDst++ = (q31_t) (acc1 >> 31U); + *pDst++ = (q31_t) (acc2 >> 31U); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x3U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (q63_t) *px++ * *pb++; + + i--; + } while (i > 0U); + + /* Result is in 2.62 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c new file mode 100644 index 0000000..5966646 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c @@ -0,0 +1,718 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q7.c + * Description: Q7 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q7 FIR filter. + @param[in] S points to an instance of the Q7 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_Q7_CORE(pOutput, nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q7_t *pSmp = &pSample[j]; \ + q31_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 16 * i); \ + acc[j] = vmladavaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q7_t) __SSAT((acc[j] >> 7U), 8); \ + } + +#define FIR_Q7_MAIN_CORE() \ +{ \ + q7_t *pState = S->pState; /* State pointer */ \ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q7_t *pStateCur; /* Points to the current sample of the state */ \ + const q7_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q7_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q7_t *pTempSrc; /* Temporary pointer to the source data */ \ + q7_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + q7x16_t vecIn0; \ + \ + /* \ + * load coefs \ + */ \ + q7x16_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vldrbq_s8(pCoeffs + 16 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrbq_s32(pStateCur, vldrbq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q7_CORE(pOutput, 4, NBVECTAPS, pSamples, vecCoeffs); \ + pSamples += 4; \ + \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q7_CORE(pOutput, residual, NBVECTAPS, pSamples, vecCoeffs); \ + \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + blkCnt = numTaps - 1; \ + do { \ + mve_pred16_t p = vctp8q(blkCnt); \ + \ + vstrbq_p_s8(pTempDest, vldrbq_z_s8(pTempSrc, p), p); \ + pTempSrc += 16; \ + pTempDest += 16; \ + blkCnt -= 16; \ + } \ + while (blkCnt > 0); \ +} + + +static void arm_fir_q7_49_64_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 64 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q7_33_48_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 48 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q7_17_32_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 32 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q7_1_16_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCur; /* Points to the current sample of the state */ + const q7_t *pSamples; /* Temporary pointer to the sample buffer */ + q7_t *pOutput; /* Temporary pointer to the output buffer */ + const q7_t *pTempSrc; /* Temporary pointer to the source data */ + q7_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q7x16_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 15) / 16; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecCoeffs; + + if (numTaps <= 16) + { + /* + * [1 to 16 taps] specialized routine + */ + arm_fir_q7_1_16_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 32) + { + /* + * [17 to 32 taps] specialized routine + */ + arm_fir_q7_17_32_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 48) + { + /* + * [33 to 48 taps] specialized routine + */ + arm_fir_q7_33_48_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 64) + { + /* + * [49 to 64 taps] specialized routine + */ + arm_fir_q7_49_64_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + blkCnt = blockSize >> 2; + + /* + * outer samples loop + */ + while (blkCnt > 0U) + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + /* + * inner coefficients loop + */ + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 16 coefs + */ + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vmladavaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vmladavaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + /* + * Decrement the taps block loop counter + */ + i--; + } + /* + * Store the 1.7 format filter output in destination buffer + */ + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc2 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc3 >> 7U), 8); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + acc2 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[8]); + acc2 = vmladavaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc2 >> 7U), 8); + } + break; + + case 2: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + } + break; + + case 1: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 4; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 16; + pTempDest += 16; + blkCnt--; + } + blkCnt = numTaps & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vstrbq_p_s8(pTempDest, vld1q(pTempSrc), p0); + } +} +#else +void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + q7_t *px; /* Temporary pointer for state buffer */ + const q7_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q7_t x0, x1, x2, x3, c0; /* Temporary variables to hold state */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + acc0 += ((q15_t) x0 * c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + acc1 += ((q15_t) x1 * c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + acc2 += ((q15_t) x2 * c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + acc3 += ((q15_t) x3 * c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x1 * c0); + acc1 += ((q15_t) x2 * c0); + acc2 += ((q15_t) x3 * c0); + acc3 += ((q15_t) x0 * c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x2 * c0); + acc1 += ((q15_t) x3 * c0); + acc2 += ((q15_t) x0 * c0); + acc3 += ((q15_t) x1 * c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x3 * c0); + acc1 += ((q15_t) x0 * c0); + acc2 += ((q15_t) x1 * c0); + acc3 += ((q15_t) x2 * c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x0 * c0); + acc1 += ((q15_t) x1 * c0); + acc2 += ((q15_t) x2 * c0); + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + acc0 = __SSAT((acc0 >> 7U), 8); + *pDst++ = acc0; + acc1 = __SSAT((acc1 >> 7U), 8); + *pDst++ = acc1; + acc2 = __SSAT((acc2 >> 7U), 8); + *pDst++ = acc2; + acc3 = __SSAT((acc3 >> 7U), 8); + *pDst++ = acc3; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + acc0 += (q15_t) * (px++) * (*(pb++)); + i--; + } + + /* The result is in 2.14 format. Convert to 1.7 + Then store the output in the destination buffer. */ + *pDst++ = __SSAT((acc0 >> 7U), 8); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c new file mode 100644 index 0000000..b95ec65 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c @@ -0,0 +1,348 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_f32.c + * Description: Floating-point sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters + + @deprecated Those functions are no more tested nor maintained and will be removed in + a future version. + + This group of functions implements sparse FIR filters. + Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. + Sparse filters are used for simulating reflections in communications and audio applications. + + There are separate functions for Q7, Q15, Q31, and floating-point data types. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays respectively containing blockSize values. + + @par Algorithm + The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. + This is in addition to the coefficient array b. + The implementation essentially skips the multiplications by zero and leads to an efficient realization. + 
+      y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+
+ @par + \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients" + @par + pCoeffs points to a coefficient array of size numTaps; + pTapDelay points to an array of nonzero indices and is also of size numTaps; + pState points to a state array of size maxDelay + blockSize, where + maxDelay is the largest offset value that is ever used in the pTapDelay array. + Some of the processing functions also require temporary working buffers. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+
+ + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the sparse FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the floating-point sparse FIR filter. + @param[in] S points to an instance of the floating-point sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + */ + +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c new file mode 100644 index 0000000..963c050 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c @@ -0,0 +1,97 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_f32.c + * Description: Floating-point sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the floating-point sparse FIR filter. + @param[in,out] S points to an instance of the floating-point sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_f32() function. + */ + +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c new file mode 100644 index 0000000..72ec65a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c @@ -0,0 +1,97 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q15.c + * Description: Q15 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q15 sparse FIR filter. + @param[in,out] S points to an instance of the Q15 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of words processed by arm_fir_sparse_q15() function. + */ + +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c new file mode 100644 index 0000000..509c85e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q31.c + * Description: Q31 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q31 sparse FIR filter. + @param[in,out] S points to an instance of the Q31 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the number of words processed by arm_fir_sparse_q31() function. + */ + +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c new file mode 100644 index 0000000..4f0f793 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c @@ -0,0 +1,97 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q7.c + * Description: Q7 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q7 sparse FIR filter. + @param[in,out] S points to an instance of the Q7 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_q7() function. + */ + +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c new file mode 100644 index 0000000..8784737 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c @@ -0,0 +1,345 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q15.c + * Description: Q15 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q15 sparse FIR filter. + @param[in] S points to an instance of the Q15 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. + Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. + If the accumulator result overflows it will wrap around rather than saturate. + After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *pOut = pDst; /* Working pointer for output */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; /* Temporary variables */ +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q15(py, (int32_t) delaySize, &S->stateIndex, 1,pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c new file mode 100644 index 0000000..6524e26 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c @@ -0,0 +1,361 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q31.c + * Description: Q31 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q31 sparse FIR filter. + @param[in] S points to an instance of the Q31 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.31 x 1.31 multiplications are truncated to 2.30 format. + This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. + If the accumulator result overflows, it wraps around rather than saturate. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + q63_t out; /* Temporary output variable */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c new file mode 100644 index 0000000..85ec295 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c @@ -0,0 +1,345 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q7.c + * Description: Q7 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q7 sparse FIR filter. + @param[in] S points to an instance of the Q7 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q7_t in1, in2, in3, in4; +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + write_q7x4_ia (&pOut, __PACKq7(in1, in2, in3, in4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c new file mode 100644 index 0000000..4c48c85 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c @@ -0,0 +1,358 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_f32.c + * Description: Floating-point IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters + + This set of functions implements lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure has feedforward and + feedback components and the net impulse response is infinite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html IIRLattice.gif "Infinite Impulse Response Lattice filter" + @par + 
+      fN(n)   = x(n)
+      fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ..., 1
+      gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ..., 1
+      y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+
+ @par + pkCoeffs points to array of reflection coefficients of size numStages. + Reflection Coefficients are stored in time-reversed order. + @par + 
+     {kN, kN-1, ..., k1}
+
+ @par + pvCoeffs points to the array of ladder coefficients of size (numStages+1). + Ladder coefficients are stored in time-reversed order. + 
+      {vN, vN-1, ..., v0}
+
+ @par + pState points to a state array of size numStages + blockSize. + The state variables shown in the figure above (the g values) are stored in the pState array. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+
+ @par + where numStages is the number of stages in the filter; pState points to the state buffer array; + pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the IIR lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pStateCur; /* State current pointer */ + float32_t acc; /* Accumlator */ + float32_t fnext1, fnext2, gcurr1, gnext; /* Temporary variables for lattice stages */ + float32_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t gcurr2; /* Temporary variables for lattice stages */ + float32_t k1, k2; + float32_t v1, v2, v3, v4; +#endif + + /* initialise loop count */ + blkCnt = blockSize; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fnext2 = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0.0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages) >> 2U; + + while (tapCnt > 0U) + { + /* Read gN-1(n-1) from state buffer */ + gcurr1 = *px1; + + /* read reflection coefficient kN */ + k1 = *pk; + + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* read ladder coefficient vN */ + v1 = *pv; + + /* read next reflection coefficient kN-1 */ + k2 = *(pk + 1U); + + /* Read gN-2(n-1) from state buffer */ + gcurr2 = *(px1 + 1U); + + /* read next ladder coefficient vN-1 */ + v2 = *(pv + 1U); + + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read reflection coefficient kN-2 */ + k1 = *(pk + 2U); + + /* write gN(n) into state for next sample processing */ + *px2++ = gnext; + + /* Read gN-3(n-1) from state buffer */ + gcurr1 = *(px1 + 2U); + + /* y(n) += gN(n) * vN */ + acc += (gnext * v1); + + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = gcurr2 + (k2 * fnext2); + + /* Read gN-4(n-1) from state buffer */ + gcurr2 = *(px1 + 3U); + + /* y(n) += gN-1(n) * vN-1 */ + acc += (gnext * v2); + + /* read reflection coefficient kN-3 */ + k2 = *(pk + 3U); + + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read ladder coefficient vN-2 */ + v3 = *(pv + 2U); + + /* y(n) += gN-2(n) * vN-2 */ + acc += (gnext * v3); + + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointer */ + pk += 4U; + + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = (fnext2 * k2) + gcurr2; + + /* read next ladder coefficient vN-3 */ + v4 = *(pv + 3U); + + /* y(n) += gN-4(n) * vN-4 */ + acc += (gnext * v4); + + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointers */ + px1 += 4U; + pv += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr1 = *px1++; + /* Process sample for last taps */ + fnext1 = fnext2 - ((*pk) * gcurr1); + gnext = (fnext1 * (*pk++)) + gcurr1; + /* Output samples for last taps */ + acc += (gnext * (*pv++)); + *px2++ = gnext; + fnext2 = fnext1; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (fnext2 * (*pv)); + + *px2++ = fnext2; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of IIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c new file mode 100644 index 0000000..d9922ec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c @@ -0,0 +1,81 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_f32.c + * Description: Floating-point IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c new file mode 100644 index 0000000..1dae546 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c @@ -0,0 +1,81 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q15.c + * Description: Q15 IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c new file mode 100644 index 0000000..779d09e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c @@ -0,0 +1,81 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q31.c + * Description: Initialization function for the Q31 IIR lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c new file mode 100644 index 0000000..2768ffa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c @@ -0,0 +1,400 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q15.c + * Description: Q15 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q15_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t out; /* Temporary variable for output */ + +#if defined (ARM_MATH_DSP) && defined (ARM_MATH_LOOPUNROLL) + q15_t gnext1, gnext2; /* Temporary variables for lattice stages */ + q31_t v; /* Temporary variable for ladder coefficient */ +#endif + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-1(n) into state for next sample processing */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-2(n) into state */ + *px2++ = (q15_t) gnext2; + + /* Read vN-1 and vN-2 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-1(n) and gN-2(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-3(n) for the next sample process */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-4(n) for the next sample process */ + *px2++ = (q15_t) gnext2; + + /* Read vN-3 and vN-4 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-3(n) and gN-4(n) */ +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples for last taps */ + acc += (q31_t) (((q31_t) gnext * (*pv++))); + *px2++ = (q15_t) gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) (((q31_t) fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) ((fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c new file mode 100644 index 0000000..430c090 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c @@ -0,0 +1,360 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q31.c + * Description: Q31 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. + */ + +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-4(n) into state for next sample processing */ + *px2++ = gnext; + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* Output samples for last taps */ + acc += ((q63_t) gnext * *pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = clip_q63_to_q31(((q63_t) fcurr - ((q31_t) (((q63_t) gcurr * (*pk )) >> 31)))); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = clip_q63_to_q31(((q63_t) gcurr + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31)))); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c new file mode 100644 index 0000000..5129666 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c @@ -0,0 +1,277 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_f16.c + * Description: f16 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions_f16.h" + +/** + @ingroup groupFilters + */ + + + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define LANE4567_MASK 0xFF00 + +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs) +{ + _Float16 e; + static const uint16_t revOffsetArray[8] = {7,6,5,4,3,2,1,0}; + + a[0] = (_Float16)phi[1] / (_Float16)phi[0]; + + e = (_Float16)phi[0] - (_Float16)phi[1] * (_Float16)a[0]; + for(int p=1; p < nbCoefs; p++) + { + _Float16 suma = 0.0f16; + _Float16 sumb = 0.0f16; + f16x8_t vecA,vecRevPhi,vecPhi,vecSumA, vecSumB; + _Float16 k; + uint32_t blkCnt; + const float16_t *pPhi,*pRevPhi,*pA; + uint16x8_t revOffset; + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + vecSumA = vdupq_n_f16(0.0f16); + vecSumB = vdupq_n_f16(0.0f16); + + pRevPhi = &phi[p-7]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 3; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 8; + + vecPhi = vld1q(pPhi); + pPhi += 8; + + vecRevPhi = vldrhq_gather_shifted_offset_f16(pRevPhi,revOffset); + pRevPhi -= 8; + + vecSumA = vfmaq(vecSumA,vecA,vecRevPhi); + vecSumB = vfmaq(vecSumB,vecA,vecPhi); + + i += 8; + blkCnt--; + + } + + suma = vecAddAcrossF16Mve(vecSumA); + sumb = vecAddAcrossF16Mve(vecSumB); + + blkCnt = p & 7; + while(blkCnt > 0) + { + suma += (_Float16)a[i] * (_Float16)phi[p - i]; + sumb += (_Float16)a[i] * (_Float16)phi[i + 1]; + + i++; + blkCnt--; + } + + k = ((_Float16)phi[p+1] - suma)/((_Float16)phi[0] - sumb); + + f16x8_t vecRevA,tmp; + static int16_t orgOffsetArray[8]={0,1,2,3,-1,-2,-3,-4}; + static const int16_t offsetIncArray[8]={4,4,4,4,-4,-4,-4,-4}; + + uint16x8_t offset,offsetInc,vecTmp; + + + offset = vld1q_u16((uint16_t*)orgOffsetArray); + vecTmp = vdupq_n_u16(p); + + offset = vaddq_m_u16(offset,offset,vecTmp,LANE4567_MASK); + offsetInc = vld1q_u16((uint16_t*)offsetIncArray); + + nb = p >> 3; + j=0; + for(int i = 0; i < nb ; i++) + { + + /* + x0=a[j] - k * a[p-1-j]; + x1=a[j+1] - k * a[p-2-j]; + x3=a[p-1-j] - k * a[j]; + x4=a[p-2-j] - k * a[j+1]; + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrhq_gather_shifted_offset_f16(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (f16x8_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (f16x8_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vmulq_n_f16(vecRevA,k)); + vstrhq_scatter_shifted_offset_f16(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=4; + + } + + blkCnt = p & 7; + + if (blkCnt) + { + nb = blkCnt >> 1; + for(int i =0;i < nb ; i++) + { + _Float16 x,y; + + x=(_Float16)a[j] - (_Float16)k * (_Float16)a[p-1-j]; + y=(_Float16)a[p-1-j] - (_Float16)k * (_Float16)a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = blkCnt & 1; + if (nb) + { + a[j]=(_Float16)a[j]- (_Float16)k * (_Float16)a[p-1-j]; + } + } + + + a[p] = k; + e = e * (1.0f16 - k*k); + + + } + *err = e; +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs) +{ + _Float16 e; + + a[0] = (_Float16)phi[1] / (_Float16)phi[0]; + + e = (_Float16)phi[0] - (_Float16)phi[1] * (_Float16)a[0]; + for(int p=1; p < nbCoefs; p++) + { + _Float16 suma=0.0f16; + _Float16 sumb=0.0f16; + _Float16 k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += (_Float16)a[i] * (_Float16)phi[p - i]; + sumb += (_Float16)a[i] * (_Float16)phi[i + 1]; + } + + k = ((_Float16)phi[p+1]-suma)/((_Float16)phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(int i =0;i < nb ; i++) + { + _Float16 x,y; + + x=(_Float16)a[j] - (_Float16)k * (_Float16)a[p-1-j]; + y=(_Float16)a[p-1-j] - (_Float16)k * (_Float16)a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=(_Float16)a[j]- (_Float16)k * (_Float16)a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f16 - k*k); + + + } + *err = e; +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of LD group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c new file mode 100644 index 0000000..0c4e650 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c @@ -0,0 +1,283 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_f32.c + * Description: f32 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_f32 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define LANE23_MASK 0xFF00 + +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + static const uint32_t revOffsetArray[4] = {3,2,1,0}; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(int p=1; p < nbCoefs; p++) + { + float32_t suma = 0.0f; + float32_t sumb = 0.0f; + f32x4_t vecA,vecRevPhi,vecPhi,vecSumA, vecSumB; + float32_t k; + uint32_t blkCnt; + const float32_t *pPhi,*pRevPhi,*pA; + uint32x4_t revOffset; + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + vecSumA = vdupq_n_f32(0.0f); + vecSumB = vdupq_n_f32(0.0f); + + pRevPhi = &phi[p-3]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 2; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 4; + + vecPhi = vld1q(pPhi); + pPhi += 4; + + vecRevPhi = vldrwq_gather_shifted_offset_f32(pRevPhi,revOffset); + pRevPhi -= 4; + + vecSumA = vfmaq(vecSumA,vecA,vecRevPhi); + vecSumB = vfmaq(vecSumB,vecA,vecPhi); + + i += 4; + blkCnt--; + + } + + suma = vecAddAcrossF32Mve(vecSumA); + sumb = vecAddAcrossF32Mve(vecSumB); + + blkCnt = p & 3; + while(blkCnt > 0) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + + i++; + blkCnt--; + } + + k = (phi[p+1] - suma)/(phi[0] - sumb); + + f32x4_t vecRevA,tmp; + static int32_t orgOffsetArray[4]={0,1,-1,-2}; + static const int32_t offsetIncArray[4]={2,2,-2,-2}; + + uint32x4_t offset,offsetInc,vecTmp; + + + offset = vld1q_u32((uint32_t*)orgOffsetArray); + vecTmp = vdupq_n_u32(p); + + offset = vaddq_m_u32(offset,offset,vecTmp,LANE23_MASK); + offsetInc = vld1q_u32((uint32_t*)offsetIncArray); + + nb = p >> 2; + j=0; + for(int i = 0; i < nb ; i++) + { + + /* + x0=a[j] - k * a[p-1-j]; + x1=a[j+1] - k * a[p-2-j]; + x3=a[p-1-j] - k * a[j]; + x4=a[p-2-j] - k * a[j+1]; + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrwq_gather_shifted_offset_f32(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (f32x4_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (f32x4_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vmulq_n_f32(vecRevA,k)); + vstrwq_scatter_shifted_offset_f32(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=2; + + } + + switch(p & 3) + { + case 3: + { + float32_t x,y; + x = a[j] - k * a[p-1-j]; + y = a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + a[j+1] = a[j+1] - k * a[p-1-(j+1)]; + } + break; + + case 2: + { + float32_t x,y; + x = a[j] - k * a[p-1-j]; + y = a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + } + break; + + case 1: + a[j] = a[j]- k * a[p-1-j]; + break; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} + +#else +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + int p; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(p=1; p < nbCoefs; p++) + { + float32_t suma=0.0f; + float32_t sumb=0.0f; + float32_t k; + int nb,j,i; + + for(i=0; i < p; i++) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + } + + k = (phi[p+1]-suma)/(phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(i =0; i < nb ; i++) + { + float32_t x,y; + + x=a[j] - k * a[p-1-j]; + y=a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=a[j]- k * a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of LD group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c new file mode 100644 index 0000000..b38b792 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c @@ -0,0 +1,380 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_q31.c + * Description: q31 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +#define ONE_Q31 0x7FFFFFFFL +#define TWO_Q30 0x7FFFFFFFL + +#define HALF_Q31 0x00008000L +#define ONE_Q15 0x7FFF +#define HALF_Q15 0x3FFF +#define LOWPART_MASK 0x07FFF + +__STATIC_FORCEINLINE q31_t mul32x16(q31_t a, q15_t b) +{ + q31_t r = ((q63_t)a * (q63_t)b) >> 15; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t mul32x32(q31_t a, q31_t b) +{ + //q31_t r = __SSAT(((q63_t)a * b) >> 31,31); + q31_t r = ((q63_t)a * b) >> 31; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t divide(q31_t n, q31_t d) +{ + arm_status status; + int16_t shift; + q15_t inverse; + q31_t r; + // We are computing: + // n / d = n / (h + l) where h and l are the high end and low end part. + // 1 / (h + l) = 1 / h (1 - l / h) + // Our division algorithm has a shift. So it is returning a scaled value sh. + // So we need a << shift to convert 1/ sh to 1/h. + // In below code, we are organizing the computation differently. Instead of computing: + // 1 / h (1 - l / h) + // we are computing + // 1 / h (2 - (l + h) / h) + // 1 / h (2 - d / h) + // Also, we are not computing 1/h in Q15 but in Q14. + // 2 is expressed in Q30. + // So at the end of all computation we need a << 2 + + // Result is in Q14 because of use of HALF_Q15 instead of ONE_Q15. + status=arm_divide_q15(HALF_Q15,d>>16,&inverse,&shift); + (void)status; + + // d is used instead of l + // So we will need to substract to 2 instead of 1. + r = mul32x16(d,inverse); + r = TWO_Q30 - (r << shift); + r = mul32x16(r, inverse); + r = mul32x32(r,n) ; + r = r << (shift + 2); + + return(r); + +} + +/** + @ingroup groupFilters + */ + + + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_q31 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#define LANE23_MASK 0xFF00 + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + + static const uint32_t revOffsetArray[4] = {3,2,1,0}; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(int p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31x4_t vecA,vecRevPhi,vecPhi; + q31_t k; + uint32_t blkCnt; + const q31_t *pPhi,*pRevPhi,*pA; + uint32x4_t revOffset; + + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + + pRevPhi = &phi[p-3]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 2; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 4; + + vecPhi = vld1q(pPhi); + pPhi += 4; + + vecRevPhi = vldrwq_gather_shifted_offset_s32(pRevPhi,revOffset); + pRevPhi -= 4; + + suma = vmlaldavaq(suma,vecA,vecRevPhi); + sumb = vmlaldavaq(sumb,vecA,vecPhi); + + i += 4; + blkCnt--; + } + + + blkCnt = p & 3; + while(blkCnt > 0) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + + i++; + blkCnt--; + } + + suma = asrl(suma, 31); + sumb = asrl(sumb, 31); + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + q31x4_t vecRevA,tmp; + static int32_t orgOffsetArray[4]={0,1,-1,-2}; + static const int32_t offsetIncArray[4]={2,2,-2,-2}; + + uint32x4_t offset,offsetInc,vecTmp; + + + offset = vld1q_u32((uint32_t*)orgOffsetArray); + vecTmp = vdupq_n_u32(p); + + offset = vaddq_m_u32(offset,offset,vecTmp,LANE23_MASK); + offsetInc = vld1q_u32((uint32_t*)offsetIncArray); + + + nb = p >> 2; + j=0; + for(int i =0;i < nb ; i++) + { + /* + q31_t x0,x1,x2,x3; + + //x = a[j] - k * a[p-1-j]; + x0 = a[j] - mul32x32(k,a[p-1-j]); + x1 = a[j+1] - mul32x32(k,a[p-2-j]); + + //y = a[p-1-j] - k * a[j]; + x2 = a[p-1-j] - mul32x32(k , a[j]); + x3 = a[p-2-j] - mul32x32(k , a[j+1]); + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrwq_gather_shifted_offset_s32(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (q31x4_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (q31x4_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vqdmulhq_n_s32(vecRevA,k)); + vstrwq_scatter_shifted_offset_s32(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=2; + } + + switch(p & 3) + { + case 3: + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + //a[j] = a[j]- k * a[p-1-j]; + a[j+1] = a[j+1] - mul32x32(k,a[p-2-j]); + } + break; + + case 2: + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + } + break; + + case 1: + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + break; + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} + +#else + +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + int p; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31_t k; + int nb,j,i; + + for(i=0; i < p; i++) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + } + + suma = suma >> 31; + sumb = sumb >> 31; + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + + nb = p >> 1; + j=0; + for(i =0;i < nb ; i++) + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of LD group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c new file mode 100644 index 0000000..865999f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c @@ -0,0 +1,537 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_f32.c + * Description: Processing function for the floating-point LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS Least Mean Square (LMS) Filters + + LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. + LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. + Adaptive filters are often used in communication systems, equalizers, and noise removal. + The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. + The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal. + + An LMS filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The LMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the Least Mean Square filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+     arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+     arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+     arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(tempV2, 0) + vget_lane_f32(tempV2, 1); + + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for the updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb = *pb + (w * (*px++)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U) samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + + +} +#else +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of LMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c new file mode 100644 index 0000000..8d8e144 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c @@ -0,0 +1,85 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_f32.c + * Description: Floating-point LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). + */ + +void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps */ + memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; +} + +/** + @} end of LMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c new file mode 100644 index 0000000..871caa0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q15.c + * Description: Q15 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for the Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of + input samples processed by each call to arm_lms_q15(). + */ + +void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c new file mode 100644 index 0000000..f4482d3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q31.c + * Description: Q31 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @param[in] postShift bit shift applied to coefficients + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to + arm_lms_q31(). + */ + +void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c new file mode 100644 index 0000000..0e99319 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c @@ -0,0 +1,568 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_f32.c + * Description: Processing function for the floating-point NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS_NORM Normalized LMS Filters + + This set of functions implements a commonly used adaptive filter. + It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization + factor which increases the adaptation rate of the filter. + The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types. + + A normalized least mean square (NLMS) filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The NLMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the NLMS adaptive filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: + 
+     E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+
+ The filter coefficients b[k] are then updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. + For Q7, Q15, and Q31 the following fields must also be initialized; + recipTable, postShift + @par + Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients (fixed point versions) + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation (fixed point versions) + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_NEON) +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(tempV2, 0) + vget_lane_f32(tempV2, 1); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U)/4 samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t x0, in; /* Temporary variable to hold input sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of LMS_NORM group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c new file mode 100644 index 0000000..949f6c3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_f32.c + * Description: Floating-point NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). + */ + +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialise Energy to zero */ + S->energy = 0.0f; + + /* Initialise x0 to zero */ + S->x0 = 0.0f; +} + +/** + @} end of LMS_NORM group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c new file mode 100644 index 0000000..aa05875 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c @@ -0,0 +1,102 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q15.c + * Description: Q15 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of input samples processed + by each call to arm_lms_norm_q15(). + */ + +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q15_t *) armRecipTableQ15; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c new file mode 100644 index 0000000..28e3c5b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c @@ -0,0 +1,101 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q31.c + * Description: Q31 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). + */ + +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q31_t *) armRecipTableQ31; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c new file mode 100644 index 0000000..2e4befd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c @@ -0,0 +1,301 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q15.c + * Description: Processing function for Q15 normalized LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and + multiplications yield a 2.30 result. The 2.30 intermediate results are + accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full + precision of intermediate multiplications is preserved. After all additions + have been performed, the accumulator is truncated to 34.15 format by + discarding low 15 bits. Lastly, the accumulator is saturated to yield a + result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t energy; /* Energy of the input */ + q15_t e = 0, d = 0; /* Error, reference data sample */ + q15_t w = 0, in; /* Weight factor and state */ + q15_t x0; /* Temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t) x0 * (x0)) >> 15); + energy += (((q31_t) in * (in)) >> 15); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t) acc; + *pErr++ = e; + + /* Calculation of 1/energy */ + postShift = arm_recip_q15((q15_t) energy + DELTA_Q15, &oneByEnergy, S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t) (((q31_t) e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = (q15_t) __SSAT((q31_t) acc, 16); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c new file mode 100644 index 0000000..322219d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c @@ -0,0 +1,315 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q31.c + * Description: Processing function for the Q31 NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q63_t energy; /* Energy of the input */ + q31_t e = 0; /* Error data sample */ + q31_t w = 0, in; /* Weight factor and state */ + q31_t x0; /* Temporary variable to hold input sample */ + q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32); + energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Calculates the reciprocal of energy */ + postShift = arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]); + + /* Calculation of product of (e * mu) */ + errorXmu = (q31_t) (((q63_t) e * mu) >> 31); + + /* Weighting factor for the normalized version */ + w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c new file mode 100644 index 0000000..b165d7f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c @@ -0,0 +1,266 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q15.c + * Description: Processing function for Q15 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* Error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t) acc; + *pErr++ = (q15_t) e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t) (((q31_t) e * (mu)) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c new file mode 100644 index 0000000..fedf570 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c @@ -0,0 +1,287 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q31.c + * Description: Processing function for the Q31 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure. + @param[in] pSrc points to the block of input data. + @param[in] pRef points to the block of reference data. + @param[out] pOut points to the block of output data. + @param[out] pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clips. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. + The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* Error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q31_t) (((q63_t) e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c new file mode 100644 index 0000000..d9a7d7c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c @@ -0,0 +1,121 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bilinear_interp_f16.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t arm_bilinear_interp_f16( + const arm_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y) + { + float16_t out; + float16_t f00, f01, f10, f11; + float16_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float16_t xdiff, ydiff; + float16_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = (_Float16)f01 - (_Float16)f00; + b3 = (_Float16)f10 - (_Float16)f00; + b4 = (_Float16)f00 - (_Float16)f01 - (_Float16)f10 + (_Float16)f11; + + /* Calculation of fractional part in X */ + xdiff = (_Float16)X - (_Float16)xIndex; + + /* Calculation of fractional part in Y */ + ydiff = (_Float16)Y - (_Float16)yIndex; + + /* Calculation of bi-linear interpolated output */ + out = (_Float16)b1 + (_Float16)b2 * (_Float16)xdiff + + (_Float16)b3 * (_Float16)ydiff + (_Float16)b4 * (_Float16)xdiff * (_Float16)ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c new file mode 100644 index 0000000..3008a7a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c @@ -0,0 +1,165 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bilinear_interp_f32.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c new file mode 100644 index 0000000..bc92417 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c @@ -0,0 +1,125 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @} end of BilinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c new file mode 100644 index 0000000..2375763 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c @@ -0,0 +1,123 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + + /** + * @} end of BilinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c new file mode 100644 index 0000000..0a78876 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c @@ -0,0 +1,121 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c new file mode 100644 index 0000000..c25a217 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c @@ -0,0 +1,105 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_f16.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t arm_linear_interp_f16( + arm_linear_interp_instance_f16 * S, + float16_t x) + { + float16_t y; + float16_t x0, x1; /* Nearest input values */ + float16_t y0, y1; /* Nearest output values */ + float16_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float16_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) (((_Float16)x - (_Float16)S->x1) / (_Float16)xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = (_Float16)S->x1 + (_Float16)i * (_Float16)xSpacing; + x1 = (_Float16)S->x1 + (_Float16)(i + 1) * (_Float16)xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = (_Float16)y0 + ((_Float16)x - (_Float16)x0) * + (((_Float16)y1 - (_Float16)y0) / ((_Float16)x1 - (_Float16)x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c new file mode 100644 index 0000000..834d54e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c @@ -0,0 +1,129 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_f32.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c new file mode 100644 index 0000000..f2cfc80 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c @@ -0,0 +1,105 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t arm_linear_interp_q15( + const q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * @} end of LinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c new file mode 100644 index 0000000..bdeefb8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c @@ -0,0 +1,107 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t arm_linear_interp_q31( + const q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + + /** + * @} end of LinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c new file mode 100644 index 0000000..bde5678 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c @@ -0,0 +1,103 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + q7_t arm_linear_interp_q7( + const q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + /** + * @} end of LinearInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c new file mode 100644 index 0000000..21a5edb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c @@ -0,0 +1,287 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_spline_interp_f32.c + * Description: Floating-point cubic spline interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @defgroup SplineInterpolate Cubic Spline Interpolation + + Spline interpolation is a method of interpolation where the interpolant + is a piecewise-defined polynomial called "spline". + + @par Introduction + + Given a function f defined on the interval [a,b], a set of n nodes x(i) + where a=x(1) + S1(x) x(1) < x < x(2) + S(x) = ... + Sn-1(x) x(n-1) < x < x(n) + + + where + + 
 
+  Si(x) = a_i+b_i(x-xi)+c_i(x-xi)^2+d_i(x-xi)^3    i=1, ..., n-1
+
+ + @par Algorithm + + Having defined h(i) = x(i+1) - x(i) + + 
+  h(i-1)c(i-1)+2[h(i-1)+h(i)]c(i)+h(i)c(i+1) = 3/h(i)*[a(i+1)-a(i)]-3/h(i-1)*[a(i)-a(i-1)]    i=2, ..., n-1
+
+ + It is possible to write the previous conditions in matrix form (Ax=B). + In order to solve the system two boundary conidtions are needed. + - Natural spline: S1''(x1)=2*c(1)=0 ; Sn''(xn)=2*c(n)=0 + In matrix form: + + 
+  |  1        0         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0         0           1     ||  c(n)  | |                        0                        |
+
+ + - Parabolic runout spline: S1''(x1)=2*c(1)=S2''(x2)=2*c(2) ; Sn-1''(xn-1)=2*c(n-1)=Sn''(xn)=2*c(n) + In matrix form: + + 
+  |  1       -1         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0        -1           1     ||  c(n)  | |                        0                        |
+
+ + A is a tridiagonal matrix (a band matrix of bandwidth 3) of size N=n+1. The factorization + algorithms (A=LU) can be simplified considerably because a large number of zeros appear + in regular patterns. The Crout method has been used: + 1) Solve LZ=B + + 
+  u(1,2) = A(1,2)/A(1,1)
+  z(1)   = B(1)/l(11)
+ 
+  FOR i=2, ..., N-1
+    l(i,i)   = A(i,i)-A(i,i-1)u(i-1,i)
+    u(i,i+1) = a(i,i+1)/l(i,i)
+    z(i)     = [B(i)-A(i,i-1)z(i-1)]/l(i,i)
+  
+  l(N,N) = A(N,N)-A(N,N-1)u(N-1,N)
+  z(N)   = [B(N)-A(N,N-1)z(N-1)]/l(N,N)
+
+ + 2) Solve UX=Z + + 
+  c(N)=z(N)
+  
+  FOR i=N-1, ..., 1
+    c(i)=z(i)-u(i,i+1)c(i+1) 
+
+ + c(i) for i=1, ..., n-1 are needed to compute the n-1 polynomials. + b(i) and d(i) are computed as: + - b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 + - d(i) = [c(i+1)-c(i)]/[3*h(i)] + Moreover, a(i)=y(i). + + @par Behaviour outside the given intervals + + It is possible to compute the interpolated vector for x values outside the + input range (xqx(n)). The coefficients used to compute the y values for + xqx(n) the + coefficients used for the last interval. + + */ + +/** + @addtogroup SplineInterpolate + @{ + */ + +/** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values of the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + +void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t * x = S->x; + const float32_t * y = S->y; + int32_t n = S->n_x; + + /* Coefficients (a==y for i<=n-1) */ + float32_t * b = (S->coeffs); + float32_t * c = (S->coeffs)+(n-1); + float32_t * d = (S->coeffs)+(2*(n-1)); + + const float32_t * pXq = xq; + int32_t blkCnt = (int32_t)blockSize; + int32_t blkCnt2; + int32_t i; + float32_t x_sc; + +#ifdef ARM_MATH_NEON + float32x4_t xiv; + float32x4_t aiv; + float32x4_t biv; + float32x4_t civ; + float32x4_t div; + + float32x4_t xqv; + + float32x4_t temp; + float32x4_t diff; + float32x4_t yv; +#endif + + /* Create output for x(i) 4 ) + { + /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */ + xqv = vld1q_f32(pXq); + pXq+=4; + + /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */ + diff = vsubq_f32(xqv, xiv); + temp = diff; + + /* y(i) = a(i) + ... */ + yv = aiv; + /* ... + b(i)*(x-x(i)) + ... */ + yv = vmlaq_f32(yv, biv, temp); + /* ... + c(i)*(x-x(i))^2 + ... */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, civ, temp); + /* ... + d(i)*(x-x(i))^3 */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, div, temp); + + /* Store [y(k) y(k+1) y(k+2) y(k+3)] */ + vst1q_f32(pDst, yv); + pDst+=4; + + blkCnt-=4; + } +#endif + while( *pXq <= x[i+1] && blkCnt > 0 ) + { + x_sc = *pXq++; + + *pDst = y[i]+b[i]*(x_sc-x[i])+c[i]*(x_sc-x[i])*(x_sc-x[i])+d[i]*(x_sc-x[i])*(x_sc-x[i])*(x_sc-x[i]); + + pDst++; + blkCnt--; + } + } + + /* Create output for remaining samples (x>=x(n)) */ +#ifdef ARM_MATH_NEON + /* Compute 4 outputs at a time */ + blkCnt2 = blkCnt >> 2; + + while(blkCnt2 > 0) + { + /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */ + xqv = vld1q_f32(pXq); + pXq+=4; + + /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */ + diff = vsubq_f32(xqv, xiv); + temp = diff; + + /* y(i) = a(i) + ... */ + yv = aiv; + /* ... + b(i)*(x-x(i)) + ... */ + yv = vmlaq_f32(yv, biv, temp); + /* ... + c(i)*(x-x(i))^2 + ... */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, civ, temp); + /* ... + d(i)*(x-x(i))^3 */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, div, temp); + + /* Store [y(k) y(k+1) y(k+2) y(k+3)] */ + vst1q_f32(pDst, yv); + pDst+=4; + + blkCnt2--; + } + + /* Tail */ + blkCnt2 = blkCnt & 3; +#else + blkCnt2 = blkCnt; +#endif + + while(blkCnt2 > 0) + { + x_sc = *pXq++; + + *pDst = y[i-1]+b[i-1]*(x_sc-x[i-1])+c[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])+d[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])*(x_sc-x[i-1]); + + pDst++; + blkCnt2--; + } +} + +/** + @} end of SplineInterpolate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c new file mode 100644 index 0000000..80e4d76 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c @@ -0,0 +1,179 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_spline_interp_init_f32.c + * Description: Floating-point cubic spline initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @addtogroup SplineInterpolate + @{ + + @par Initialization function + + The initialization function takes as input two arrays that the user has to allocate: + coeffs will contain the b, c, and d coefficients for the (n-1) intervals + (n is the number of known points), hence its size must be 3*(n-1); tempBuffer + is temporally used for internal computations and its size is n+n-1. + + @par + + The x input array must be strictly sorted in ascending order and it must + not contain twice the same value (x(i)x = x; + S->y = y; + S->n_x = n; + + /* == Solve LZ=B to obtain z(i) and u(i) == */ + + /* -- Row 1 -- */ + /* B(0) = 0, not computed */ + /* u(1,2) = a(1,2)/a(1,1) = a(1,2) */ + if(type == ARM_SPLINE_NATURAL) + u[0] = 0; /* a(1,2) = 0 */ + else if(type == ARM_SPLINE_PARABOLIC_RUNOUT) + u[0] = -1; /* a(1,2) = -1 */ + + z[0] = 0; /* z(1) = B(1)/a(1,1) = 0 always */ + + /* -- Rows 2 to N-1 (N=n+1) -- */ + hm1 = x[1] - x[0]; /* Initialize h(i-1) = h(1) = x(2)-x(1) */ + + for (i=1; i<(int32_t)n-1; i++) + { + /* Compute B(i) */ + hi = x[i+1]-x[i]; + Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1; + + /* l(i) = a(i)-a(i,i-1)*u(i-1) = 2[h(i-1)+h(i)]-h(i-1)*u(i-1) */ + li = 2*(hi+hm1) - hm1*u[i-1]; + + /* u(i) = a(i,i+1)/l(i) = h(i)/l(i) */ + u[i] = hi/li; + + /* z(i) = [B(i)-h(i-1)*z(i-1)]/l(i) */ + z[i] = (Bi-hm1*z[i-1])/li; + + /* Update h(i-1) for next iteration */ + hm1 = hi; + } + + /* -- Row N -- */ + /* l(N) = a(N,N)-a(N,N-1)u(N-1) */ + /* z(N) = [-a(N,N-1)z(N-1)]/l(N) */ + if(type == ARM_SPLINE_NATURAL) + { + /* li = 1; a(N,N) = 1; a(N,N-1) = 0 */ + z[n-1] = 0; /* a(N,N-1) = 0 */ + } + else if(type == ARM_SPLINE_PARABOLIC_RUNOUT) + { + li = 1+u[n-2]; /* a(N,N) = 1; a(N,N-1) = -1 */ + z[n-1] = z[n-2]/li; /* a(N,N-1) = -1 */ + } + + /* == Solve UX = Z to obtain c(i) and */ + /* compute b(i) and d(i) from c(i) == */ + + cp1 = z[n-1]; /* Initialize c(i+1) = c(N) = z(N) */ + + for (i=n-2; i>=0; i--) + { + /* c(i) = z(i)-u(i+1)c(i+1) */ + c[i] = z[i]-u[i]*cp1; + + hi = x[i+1]-x[i]; + /* b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 */ + b[i] = (y[i+1]-y[i])/hi-hi*(cp1+2*c[i])/3; + + /* d(i) = [c(i+1)-c(i)]/[3*h(i)] */ + d[i] = (cp1-c[i])/(3*hi); + + /* Update c(i+1) for next iteration */ + cp1 = c[i]; + } + + /* == Finally, store the coefficients in the instance == */ + + S->coeffs = coeffs; +} + +/** + @} end of SplineInterpolate group + */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f16.c new file mode 100644 index 0000000..e9f15bc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f16.c @@ -0,0 +1,125 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_householder_f16.c + * Description: Half floating-point Householder transform + * + * $Date: 15 June 2022 + * $Revision: V1.11.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + + +#include + + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixHouseholder + @{ + */ + +/** + @brief Householder transform of a half floating point vector. + @param[in] pSrc points to the input vector. + @param[in] threshold norm2 threshold. + @param[in] blockSize dimension of the vector space. + @param[out] pOut points to the output vector. + @return beta return the scaling factor beta + */ + + +#if defined(ARM_FLOAT16_SUPPORTED) + + + +float16_t arm_householder_f16( + const float16_t * pSrc, + const float16_t threshold, + uint32_t blockSize, + float16_t * pOut + ) + +{ + uint32_t i; + float16_t epsilon; + float16_t x1norm2,alpha; + float16_t beta,tau,r; + + epsilon = threshold; + + alpha = pSrc[0]; + + for(i=1; i < blockSize; i++) + { + pOut[i] = pSrc[i]; + } + pOut[0] = 1.0f16; + + arm_dot_prod_f16(pSrc+1,pSrc+1,blockSize-1,&x1norm2); + + if ((_Float16)x1norm2<=(_Float16)epsilon) + { + tau = 0.0f16; + memset(pOut,0,blockSize * sizeof(float16_t)); + } + else + { + beta = (_Float16)alpha * (_Float16)alpha + (_Float16)x1norm2; + (void)arm_sqrt_f16(beta,&beta); + + if ((_Float16)alpha > 0.0f16) + { + beta = -(_Float16)beta; + } + + r = 1.0f16 / ((_Float16)alpha -(_Float16)beta); + arm_scale_f16(pOut,r,pOut,blockSize); + pOut[0] = 1.0f16; + + + tau = ((_Float16)beta - (_Float16)alpha) / (_Float16)beta; + + } + + return(tau); + +} + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MatrixHouseholder group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f32.c new file mode 100644 index 0000000..c1510bc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f32.c @@ -0,0 +1,196 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_householder_f32.c + * Description: Floating-point Householder transform + * + * $Date: 15 June 2022 + * $Revision: V1.11.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +#include + + + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixHouseholder Householder transform of a vector + + Computes the Householder transform of a vector x. + + The Householder transform of x is a vector v with + + \f[ + v_0 = 1 + \f] + + and a scalar \f$\beta\f$ such that: + + \f[ + P = I - \beta v v^T + \f] + + is an orthogonal matrix and + + \f[ + P x = ||x||_2 e_1 + \f] + + So P is an hyperplane reflection such that the image of x + is proportional to \f$e_1\f$. + + \f$e_1\f$ is the vector of coordinates: + + \f[ + \begin{pmatrix} + 1 \\ + 0 \\ + \vdots \\ + \end{pmatrix} + \f] + + If x is already proportional to \f$e_1\f$ then + the matrix P should be the identity. + + Thus, \f$\beta\f$ should be 0 and in this case the vector v + can also be null. + + But how do we detect that x is already proportional to + \f$e_1\f$. + + If x + \f[ + x = + \begin{pmatrix} + x_0 \\ + xr \\ + \end{pmatrix} + \f] + + where \f$xr\f$ is a vector. + + The algorithm is computing the norm squared of this vector: + + \f[ + ||xr||^2 + \f] + + and this value is compared to a `threshold`. If the value + is smaller than the `threshold`, the algorithm is + returning 0 for \f$\beta\f$ and the householder vector. + + This `threshold` is an argument of the function. + + Default values are provided in the header + `dsp/matrix_functions.h` like for instance + `DEFAULT_HOUSEHOLDER_THRESHOLD_F32` + + + + */ + +/** + @addtogroup MatrixHouseholder + @{ + */ + +/** + @brief Householder transform of a floating point vector. + @param[in] pSrc points to the input vector. + @param[in] threshold norm2 threshold. + @param[in] blockSize dimension of the vector space. + @param[out] pOut points to the output vector. + @return beta return the scaling factor beta + */ + + + + +float32_t arm_householder_f32( + const float32_t * pSrc, + const float32_t threshold, + uint32_t blockSize, + float32_t * pOut + ) + +{ + uint32_t i; + float32_t epsilon; + float32_t x1norm2,alpha; + float32_t beta,tau,r; + + epsilon = threshold; + + alpha = pSrc[0]; + + for(i=1; i < blockSize; i++) + { + pOut[i] = pSrc[i]; + } + pOut[0] = 1.0f; + + arm_dot_prod_f32(pSrc+1,pSrc+1,blockSize-1,&x1norm2); + + if (x1norm2<=epsilon) + { + tau = 0.0f; + memset(pOut,0,blockSize * sizeof(float32_t)); + } + else + { + beta = alpha * alpha + x1norm2; + (void)arm_sqrt_f32(beta,&beta); + + if (alpha > 0.0f) + { + beta = -beta; + } + + r = 1.0f / (alpha -beta); + arm_scale_f32(pOut,r,pOut,blockSize); + pOut[0] = 1.0f; + + + tau = (beta - alpha) / beta; + + } + + return(tau); + +} + + +/** + @} end of MatrixHouseholder group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f64.c new file mode 100644 index 0000000..3f41011 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_householder_f64.c @@ -0,0 +1,121 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_householder_f64.c + * Description: Double floating-point Householder transform + * + * $Date: 15 June 2022 + * $Revision: V1.11.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +#include + + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixHouseholder + @{ + */ + +/** + @brief Householder transform of a double floating point vector. + @param[in] pSrc points to the input vector. + @param[in] threshold norm2 threshold. + @param[in] blockSize dimension of the vector space. + @param[out] pOut points to the output vector. + @return beta return the scaling factor beta + */ + + + + +float64_t arm_householder_f64( + const float64_t * pSrc, + const float64_t threshold, + uint32_t blockSize, + float64_t * pOut + ) + +{ + uint32_t i; + float64_t epsilon; + float64_t x1norm2,alpha; + float64_t beta,tau,r; + + epsilon = threshold; + + alpha = pSrc[0]; + + for(i=1; i < blockSize; i++) + { + pOut[i] = pSrc[i]; + } + pOut[0] = 1.0; + + arm_dot_prod_f64(pSrc+1,pSrc+1,blockSize-1,&x1norm2); + + if (x1norm2<=epsilon) + { + tau = 0.0; + memset(pOut,0,blockSize * sizeof(float64_t)); + } + else + { + beta = alpha * alpha + x1norm2; + beta=sqrt(beta); + + if (alpha > 0.0) + { + beta = -beta; + } + + r = 1.0 / (alpha -beta); + arm_scale_f64(pOut,r,pOut,blockSize); + pOut[0] = 1.0; + + + tau = (beta - alpha) / beta; + + } + + return(tau); + +} + + +/** + @} end of MatrixHouseholder group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c new file mode 100644 index 0000000..77b4fab --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c @@ -0,0 +1,221 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_f16.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; + uint32_t numSamples; /* total number of elements in the matrix */ + float16_t *pDataA, *pDataB, *pDataDst; + f16x8_t vecA, vecB, vecDst = { 0 }; + float16_t const *pSrcAVec; + float16_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float16_t const *) pDataA; + pSrcBVec = (float16_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + vecDst = vaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vaddq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + return (status); +} +#else + +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixAdd group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c new file mode 100644 index 0000000..b777249 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c @@ -0,0 +1,328 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_f32.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixAdd Matrix Addition + + Adds two matrices. + @par Addition of two 3 x 3 matrices + + \f[ + \begin{pmatrix} + a_{1,1} & a_{1,2} & a_{1,3} \\ + a_{2,1} & a_{2,2} & a_{2,3} \\ + a_{3,1} & a_{3,2} & a_{3,3} \\ + \end{pmatrix} + + + \begin{pmatrix} + b_{1,1} & b_{1,2} & b_{1,3} \\ + b_{2,1} & b_{2,2} & b_{2,3} \\ + b_{3,1} & b_{3,2} & b_{3,3} \\ + \end{pmatrix} + = + \begin{pmatrix} + a_{1,1}+b_{1,1} & a_{1,2}+b_{1,2} & a_{1,3}+b_{1,3} \\ + a_{2,1}+b_{2,1} & a_{2,2}+b_{2,2} & a_{2,3}+b_{2,3} \\ + a_{3,1}+b_{3,1} & a_{3,2}+b_{3,2} & a_{3,3}+b_{3,3} \\ + \end{pmatrix} + \f] + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; + uint32_t numSamples; /* total number of elements in the matrix */ + float32_t *pDataA, *pDataB, *pDataDst; + f32x4_t vecA, vecB, vecDst = { 0 }; + float32_t const *pSrcAVec; + float32_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float32_t const *) pDataA; + pSrcBVec = (float32_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vaddq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + return (status); +} +#else +#if defined(ARM_MATH_NEON) +/* + +Neon version is assuming the matrix is small enough. +So no blocking is used for taking into account cache effects. +For big matrix, there exist better libraries for Neon. + +*/ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) + (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c new file mode 100644 index 0000000..9a1dfa0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c @@ -0,0 +1,231 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q15.c + * Description: Q15 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q15 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q15_t *pDataA, *pDataB, *pDataDst; + q15x8_t vecA, vecB, vecDst = { 0 }; + q15_t const *pSrcAVec; + q15_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q15_t const *) pDataA; + pSrcBVec = (q15_t const *) pDataB; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqaddq(vecA, vecB); + vst1q(pDataDst, vecDst); pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqaddq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c new file mode 100644 index 0000000..7b08dbf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c @@ -0,0 +1,220 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q31.c + * Description: Q31 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q31 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + arm_status status; /* status of matrix addition */ + uint32_t numSamples; /* total number of elements in the matrix */ + q31_t *pDataA, *pDataB, *pDataDst; + q31x4_t vecA, vecB, vecDst = { 0 }; + q31_t const *pSrcAVec; + q31_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q31_t const *) pDataA; + pSrcBVec = (q31_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqaddq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixAdd group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c new file mode 100644 index 0000000..31b245e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c @@ -0,0 +1,256 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f16.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = L L^t + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + _Float16 invSqrtVj; + float16_t *pA,*pG; + int kCnt; + + mve_pred16_t p0; + + f16x8_t acc, acc0, acc1, acc2, acc3; + f16x8_t vecGi; + f16x8_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + acc0 = vdupq_n_f16(0.0f16); + acc0[0]=pA[(j + 0) * n + i]; + + acc1 = vdupq_n_f16(0.0f16); + acc1[0]=pA[(j + 1) * n + i]; + + acc2 = vdupq_n_f16(0.0f16); + acc2[0]=pA[(j + 2) * n + i]; + + acc3 = vdupq_n_f16(0.0f16); + acc3[0]=pA[(j + 3) * n + i]; + + kCnt = i; + for(k=0; k < i ; k+=8) + { + p0 = vctp16q(kCnt); + + vecGi=vldrhq_z_f16(&pG[i * n + k],p0); + + vecGj0=vldrhq_z_f16(&pG[(j + 0) * n + k],p0); + vecGj1=vldrhq_z_f16(&pG[(j + 1) * n + k],p0); + vecGj2=vldrhq_z_f16(&pG[(j + 2) * n + k],p0); + vecGj3=vldrhq_z_f16(&pG[(j + 3) * n + k],p0); + + acc0 = vfmsq_m(acc0, vecGi, vecGj0, p0); + acc1 = vfmsq_m(acc1, vecGi, vecGj1, p0); + acc2 = vfmsq_m(acc2, vecGi, vecGj2, p0); + acc3 = vfmsq_m(acc3, vecGi, vecGj3, p0); + + kCnt -= 8; + } + pG[(j + 0) * n + i] = vecAddAcrossF16Mve(acc0); + pG[(j + 1) * n + i] = vecAddAcrossF16Mve(acc1); + pG[(j + 2) * n + i] = vecAddAcrossF16Mve(acc2); + pG[(j + 3) * n + i] = vecAddAcrossF16Mve(acc3); + } + + for(; j < n ; j++) + { + + kCnt = i; + acc = vdupq_n_f16(0.0f16); + acc[0] = pA[j * n + i]; + + for(k=0; k < i ; k+=8) + { + p0 = vctp16q(kCnt); + + vecGi=vldrhq_z_f16(&pG[i * n + k],p0); + vecGj=vldrhq_z_f16(&pG[j * n + k],p0); + + acc = vfmsq_m(acc, vecGi, vecGj,p0); + + kCnt -= 8; + } + pG[j * n + i] = vecAddAcrossF16Mve(acc); + } + + if ((_Float16)pG[i * n + i] <= 0.0f16) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f16/(_Float16)sqrtf((float32_t)pG[i * n + i]); + SCALE_COL_F16(pDst,i,invSqrtVj,i); + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float16_t invSqrtVj; + float16_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = (_Float16)pG[j * n + i] - (_Float16)pG[i * n + k] * (_Float16)pG[j * n + k]; + } + } + + if ((_Float16)pG[i * n + i] <= 0.0f16) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + /* The division is done in float32 for accuracy reason and + because doing it in f16 would not have any impact on the performances. + */ + invSqrtVj = 1.0f/sqrtf((float32_t)pG[i * n + i]); + SCALE_COL_F16(pDst,i,invSqrtVj,i); + + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c new file mode 100644 index 0000000..77890a4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c @@ -0,0 +1,435 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f32.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 05 October 2021 + * $Revision: V1.9.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixChol Cholesky and LDLT decompositions + + Computes the Cholesky or LL^t decomposition of a matrix. + + + If the input matrix does not have a decomposition, then the + algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix L such that A = L L^t + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + int kCnt; + + mve_pred16_t p0; + + f32x4_t acc, acc0, acc1, acc2, acc3; + f32x4_t vecGi; + f32x4_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + pG[(j + 0) * n + i] = pA[(j + 0) * n + i]; + pG[(j + 1) * n + i] = pA[(j + 1) * n + i]; + pG[(j + 2) * n + i] = pA[(j + 2) * n + i]; + pG[(j + 3) * n + i] = pA[(j + 3) * n + i]; + + kCnt = i; + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + for(k=0; k < i ; k+=4) + { + p0 = vctp32q(kCnt); + + vecGi=vldrwq_z_f32(&pG[i * n + k],p0); + + vecGj0=vldrwq_z_f32(&pG[(j + 0) * n + k],p0); + vecGj1=vldrwq_z_f32(&pG[(j + 1) * n + k],p0); + vecGj2=vldrwq_z_f32(&pG[(j + 2) * n + k],p0); + vecGj3=vldrwq_z_f32(&pG[(j + 3) * n + k],p0); + + acc0 = vfmaq_m(acc0, vecGi, vecGj0, p0); + acc1 = vfmaq_m(acc1, vecGi, vecGj1, p0); + acc2 = vfmaq_m(acc2, vecGi, vecGj2, p0); + acc3 = vfmaq_m(acc3, vecGi, vecGj3, p0); + + kCnt -= 4; + } + pG[(j + 0) * n + i] -= vecAddAcrossF32Mve(acc0); + pG[(j + 1) * n + i] -= vecAddAcrossF32Mve(acc1); + pG[(j + 2) * n + i] -= vecAddAcrossF32Mve(acc2); + pG[(j + 3) * n + i] -= vecAddAcrossF32Mve(acc3); + } + + for(; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + kCnt = i; + acc = vdupq_n_f32(0.0f); + + for(k=0; k < i ; k+=4) + { + p0 = vctp32q(kCnt); + + vecGi=vldrwq_z_f32(&pG[i * n + k],p0); + vecGj=vldrwq_z_f32(&pG[j * n + k],p0); + + acc = vfmaq_m(acc, vecGi, vecGj,p0); + + kCnt -= 4; + } + pG[j * n + i] -= vecAddAcrossF32Mve(acc); + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + SCALE_COL_F32(pDst,i,invSqrtVj,i); + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + int kCnt; + + + f32x4_t acc, acc0, acc1, acc2, acc3; + f32x4_t vecGi; + f32x4_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0); +#endif + float32_t sum=0.0f; + float32_t sum0=0.0f,sum1=0.0f,sum2=0.0f,sum3=0.0f; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + pG[(j + 0) * n + i] = pA[(j + 0) * n + i]; + pG[(j + 1) * n + i] = pA[(j + 1) * n + i]; + pG[(j + 2) * n + i] = pA[(j + 2) * n + i]; + pG[(j + 3) * n + i] = pA[(j + 3) * n + i]; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + kCnt = i >> 2; + k=0; + while(kCnt > 0) + { + + vecGi=vld1q_f32(&pG[i * n + k]); + + vecGj0=vld1q_f32(&pG[(j + 0) * n + k]); + vecGj1=vld1q_f32(&pG[(j + 1) * n + k]); + vecGj2=vld1q_f32(&pG[(j + 2) * n + k]); + vecGj3=vld1q_f32(&pG[(j + 3) * n + k]); + + acc0 = vfmaq_f32(acc0, vecGi, vecGj0); + acc1 = vfmaq_f32(acc1, vecGi, vecGj1); + acc2 = vfmaq_f32(acc2, vecGi, vecGj2); + acc3 = vfmaq_f32(acc3, vecGi, vecGj3); + + kCnt--; + k+=4; + } + +#if defined(__aarch64__) + sum0 = vpadds_f32(vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0))); + sum1 = vpadds_f32(vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1))); + sum2 = vpadds_f32(vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2))); + sum3 = vpadds_f32(vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3))); + +#else + tmp = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum0 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1)); + sum1 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2)); + sum2 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3)); + sum3 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); +#endif + + kCnt = i & 3; + while(kCnt > 0) + { + + sum0 = sum0 + pG[i * n + k] * pG[(j + 0) * n + k]; + sum1 = sum1 + pG[i * n + k] * pG[(j + 1) * n + k]; + sum2 = sum2 + pG[i * n + k] * pG[(j + 2) * n + k]; + sum3 = sum3 + pG[i * n + k] * pG[(j + 3) * n + k]; + kCnt--; + k++; + } + + pG[(j + 0) * n + i] -= sum0; + pG[(j + 1) * n + i] -= sum1; + pG[(j + 2) * n + i] -= sum2; + pG[(j + 3) * n + i] -= sum3; + } + + for(; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + acc = vdupq_n_f32(0.0f); + + kCnt = i >> 2; + k=0; + while(kCnt > 0) + { + + vecGi=vld1q_f32(&pG[i * n + k]); + vecGj=vld1q_f32(&pG[j * n + k]); + + acc = vfmaq_f32(acc, vecGi, vecGj); + + kCnt--; + k+=4; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(acc), vget_high_f32(acc))); +#else + tmp = vpadd_f32(vget_low_f32(acc), vget_high_f32(acc)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); +#endif + + kCnt = i & 3; + while(kCnt > 0) + { + sum = sum + pG[i * n + k] * pG[(j + 0) * n + k]; + + + kCnt--; + k++; + } + + pG[j * n + i] -= sum; + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + SCALE_COL_F32(pDst,i,invSqrtVj,i); + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + SCALE_COL_F32(pDst,i,invSqrtVj,i); + + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c new file mode 100644 index 0000000..b42f296 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c @@ -0,0 +1,125 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f64.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix L such that A = L L^t + */ + + +arm_status arm_mat_cholesky_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float64_t invSqrtVj; + float64_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0/sqrt(pG[i * n + i]); + SCALE_COL_F64(pDst,i,invSqrtVj,i); + + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c new file mode 100644 index 0000000..3822659 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c @@ -0,0 +1,939 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_mat_cmplx_mult_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define DONTCARE 0 /* inactive lane content */ + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_2x2_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 2 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0,vecColAOffs0,vecColAOffs1; + float16_t *pInA0 = pInA; + f16x8_t acc0, acc1; + f16x8_t vecB, vecA0, vecA1; + f16x8_t vecTmp; + uint16_t tmp; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2, 3, + MATRIX_DIM * CMPLX_DIM + 2 , MATRIX_DIM * CMPLX_DIM + 3, + }; + + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + tmp = 0; + vecColAOffs0 = viwdupq_u16(tmp, 4, 1); + + tmp = (CMPLX_DIM * MATRIX_DIM); + vecColAOffs1 = vecColAOffs0 + (uint16_t)(CMPLX_DIM * MATRIX_DIM); + + + pInB = (float16_t const *)pSrcB->pData; + + vecA0 = vldrhq_gather_shifted_offset_f16(pInA0, vecColAOffs0); + vecA1 = vldrhq_gather_shifted_offset_f16(pInA0, vecColAOffs1); + + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + + /* + * Compute + * re0+re1 | im0+im1 | re0+re1 | im0+im1 + * re2+re3 | im2+im3 | re2+re3 | im2+im3 + */ + + vecTmp = (f16x8_t) vrev64q_s32((int32x4_t) acc0); + vecTmp = vaddq(vecTmp, acc0); + + + *(float32_t *)(&pOut[0 * CMPLX_DIM * MATRIX_DIM]) = ((f32x4_t)vecTmp)[0]; + *(float32_t *)(&pOut[0 * CMPLX_DIM * MATRIX_DIM + CMPLX_DIM]) = ((f32x4_t)vecTmp)[2]; + + vecTmp = (f16x8_t) vrev64q_s32((int32x4_t) acc1); + vecTmp = vaddq(vecTmp, acc1); + + *(float32_t *)(&pOut[1 * CMPLX_DIM * MATRIX_DIM]) = ((f32x4_t)vecTmp)[0]; + *(float32_t *)(&pOut[1 * CMPLX_DIM * MATRIX_DIM + CMPLX_DIM]) = ((f32x4_t)vecTmp)[2]; + + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_3x3_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 3 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0; + float16_t *pInA0 = pInA; + float16_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM; + f16x8_t acc0, acc1, acc2; + f16x8_t vecB, vecA0, vecA1, vecA2; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2 * MATRIX_DIM * CMPLX_DIM, 2 * MATRIX_DIM * CMPLX_DIM + 1, + DONTCARE, DONTCARE + }; + + + /* enable predication to disable upper half complex vector element */ + mve_pred16_t p0 = vctp16q(MATRIX_DIM * CMPLX_DIM); + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + pInB = (float16_t const *)pSrcB->pData; + + vecA0 = vldrhq_f16(pInA0); + vecA1 = vldrhq_f16(pInA1); + vecA2 = vldrhq_f16(pInA2); + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_4x4_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 4 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0; + float16_t *pInA0 = pInA; + float16_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM; + f16x8_t acc0, acc1, acc2, acc3; + f16x8_t vecB, vecA; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2 * MATRIX_DIM * CMPLX_DIM, 2 * MATRIX_DIM * CMPLX_DIM + 1, + 3 * MATRIX_DIM * CMPLX_DIM, 3 * MATRIX_DIM * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + pInB = (float16_t const *)pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t const *pInB = (float16_t const *) pSrcB->pData; /* input data matrix pointer B */ + float16_t const *pInA = (float16_t const *) pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint16x8_t vecOffs, vecColBOffs; + uint32_t blkCnt,rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ +if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + pOut[0] = (_Float16)pInA[0] * (_Float16)pInB[0] - (_Float16)pInA[1] * (_Float16)pInB[1]; + pOut[1] = (_Float16)pInA[0] * (_Float16)pInB[1] + (_Float16)pInA[1] * (_Float16)pInB[0]; + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_f16_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_f16_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_f16_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + vecColBOffs[4] = 2*numColsB * CMPLX_DIM; + vecColBOffs[5] = 2*(numColsB * CMPLX_DIM) + 1; + vecColBOffs[6] = 3*numColsB * CMPLX_DIM; + vecColBOffs[7] = 3*(numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float16_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + float16_t const *pInA0 = pInA; + float16_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + float16_t const *pInA2 = pInA1 + numColsA * CMPLX_DIM; + float16_t const *pInA3 = pInA2 + numColsA * CMPLX_DIM; + f16x8_t acc0, acc1, acc2, acc3; + + acc0 = vdupq_n_f16(0.0f16); + acc1 = vdupq_n_f16(0.0f16); + acc2 = vdupq_n_f16(0.0f16); + acc3 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = (float16_t const *) pInA0; + pSrcA1Vec = (float16_t const *) pInA1; + pSrcA2Vec = (float16_t const *) pInA2; + pSrcA3Vec = (float16_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_f16(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs , (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 8; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 8; + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 8; + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 8; + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + blkCnt--; + } + /* + * Unsupported addressing mode compiler crash + */ + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_z_f16(pInB, vecOffs, p0); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vld1q(pSrcA1Vec); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vld1q(pSrcA2Vec); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vld1q(pSrcA3Vec); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + } + + + mve_cmplx_sum_intra_vec_f16(acc0, &px[0 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc1, &px[1 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc2, &px[2 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc3, &px[3 * CMPLX_DIM * numColsB + 0]); + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float16_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 3; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float16_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float16_t const *pSrcA0Vec; + float16_t const *pInA0 = pInA; + f16x8_t acc0; + + acc0 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = (float16_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (4*numColsB * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecOffs, p0); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + } + + mve_cmplx_sum_intra_vec_f16(acc0, &px[0]); + + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float16_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + /* + * set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + } + /* + * Return to application + */ + return (status); +} +#else + +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + _Float16 sumReal, sumImag; /* Accumulator */ + _Float16 a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f16; + sumImag = 0.0f16; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c new file mode 100644 index 0000000..941849d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c @@ -0,0 +1,1411 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup CmplxMatrixMult Complex Matrix Multiplication + + Complex Matrix multiplication is only defined if the number of columns of the + first matrix equals the number of rows of the second matrix. + Multiplying an M x N matrix with an N x P matrix results + in an M x P matrix. + @par + When matrix size checking is enabled, the functions check: + - that the inner dimensions of pSrcA and pSrcB are equal; + - that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_2x2_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM2; + f32x4_t acc0, acc1; + f32x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM2 * CMPLX_DIM, MATRIX_DIM2 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc1[1] + acc1[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc1[1] + acc1[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_3x3_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM3; + float32_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM3; + f32x4_t acc0, acc1, acc2; + f32x4_t vecB, vecA; + /* enable predication to disable upper half complex vector element */ + mve_pred16_t p0 = vctp32q(CMPLX_DIM); + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM3 * CMPLX_DIM, MATRIX_DIM3 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { 2 * MATRIX_DIM3 * CMPLX_DIM, 2 * MATRIX_DIM3 * CMPLX_DIM + 1, + INACTIVELANE, INACTIVELANE + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + vecColBOffs1 = vldrwq_u32((uint32_t const *) offsetB1); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_4x4_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM4; + float32_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM4; + float32_t *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM4; + f32x4_t acc0, acc1, acc2, acc3; + f32x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM4 * CMPLX_DIM, MATRIX_DIM4 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { 2 * MATRIX_DIM4 * CMPLX_DIM, 2 * MATRIX_DIM4 * CMPLX_DIM + 1, + 3 * MATRIX_DIM4 * CMPLX_DIM, 3 * MATRIX_DIM4 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + vecColBOffs1 = vldrwq_u32((uint32_t const *) offsetB1); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = (float32_t const *) pSrcB->pData; /* input data matrix pointer B */ + float32_t const *pInA = (float32_t const *) pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + pOut[0] = pInA[0] * pInB[0] - pInA[1] * pInB[1]; + pOut[1] = pInA[0] * pInB[1] + pInA[1] * pInB[0]; + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_f32_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_f32_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_f32_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float32_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + float32_t const *pInA0 = pInA; + float32_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + float32_t const *pInA2 = pInA1 + numColsA * CMPLX_DIM; + float32_t const *pInA3 = pInA2 + numColsA * CMPLX_DIM; + f32x4_t acc0, acc1, acc2, acc3; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = (float32_t const *) pInA0; + pSrcA1Vec = (float32_t const *) pInA1; + pSrcA2Vec = (float32_t const *) pInA2; + pSrcA3Vec = (float32_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + blkCnt--; + } + + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + } + + px[0 * CMPLX_DIM * numColsB + 0] = acc0[0] + acc0[2]; + px[0 * CMPLX_DIM * numColsB + 1] = acc0[1] + acc0[3]; + px[1 * CMPLX_DIM * numColsB + 0] = acc1[0] + acc1[2]; + px[1 * CMPLX_DIM * numColsB + 1] = acc1[1] + acc1[3]; + px[2 * CMPLX_DIM * numColsB + 0] = acc2[0] + acc2[2]; + px[2 * CMPLX_DIM * numColsB + 1] = acc2[1] + acc2[3]; + px[3 * CMPLX_DIM * numColsB + 0] = acc3[0] + acc3[2]; + px[3 * CMPLX_DIM * numColsB + 1] = acc3[1] + acc3[3]; + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float32_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 3; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float32_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float32_t const *pSrcA0Vec; + float32_t const *pInA0 = pInA; + f32x4_t acc0; + + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = (float32_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + } + + px[0] = acc0[0] + acc0[2]; + px[1] = acc0[1] + acc0[3]; + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float32_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + float32_t sumReal1, sumImag1; /* accumulator */ + float32_t a1, a1B,b1, b1B, c1, d1; + float32_t sumReal2, sumImag2; /* accumulator */ + + + float32x4x2_t a0V, a1V; + float32x4_t accR0,accI0, accR1,accI1,tempR, tempI; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + + uint16_t col, i = 0U, j, rowCnt, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + float32_t sumReal1B, sumImag1B; + float32_t sumReal2B, sumImag2B; + float32_t *pxB; + +#ifdef ARM_MATH_MATRIX_CHECK + + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + + rowCnt = row >> 1; + + /* Row loop */ + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + pxB = px + 2 * numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + sumReal1B = 0.0f; + sumImag1B = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + sumReal2B = 0.0f; + sumImag2B = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + 2*numColsA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + accR1 = vdupq_n_f32(0.0); + accI1 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + a1V = vld2q_f32(pIn1B); // load & separate real/imag pSrcA (de-interleave 2) + + pIn1 += 8; + pIn1B += 8; + + tempR = vsetq_lane_f32(*pIn2,tempR,0); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,0); + pIn2 += 2 * numColsB; + + + tempR = vsetq_lane_f32(*pIn2,tempR,1); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,1); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,2); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,2); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,3); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,3); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + accR1 = vmlaq_f32(accR1,a1V.val[0],tempR); + accR1 = vmlsq_f32(accR1,a1V.val[1],tempI); + + accI1 = vmlaq_f32(accI1,a1V.val[1],tempR); + accI1 = vmlaq_f32(accI1,a1V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accR1), vget_high_f32(accR1)); + sumReal1B += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI1), vget_high_f32(accI1)); + sumImag1B += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + a1B = *pIn1B; + + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + b1B = *(pIn1B + 1U); + + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + sumReal1B += a1B * c1; + sumImag1B += b1B * c1; + + pIn1 += 2U; + pIn1B += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + sumReal2B -= b1B * d1; + sumImag2B += a1B * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + sumReal1B += sumReal2B; + sumImag1B += sumImag2B; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + *pxB++ = sumReal1B; + *pxB++ = sumImag1B; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + } + + /* Update the pointer pInA to point to the starting address of the next 2 row */ + i = i + 2*numColsB; + pInA = pInA + 4 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + rowCnt = row & 1; + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 8; + + tempR = vsetq_lane_f32(*pIn2,tempR,0); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,0); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,1); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,1); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,2); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,2); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,3); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,3); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + pIn1 += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + + } + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + float32_t sumReal, sumImag; /* Accumulator */ + float32_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f; + sumImag = 0.0f; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c new file mode 100644 index 0000000..09f457f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c @@ -0,0 +1,599 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mat_mult_q15.c + * Description: Q15 complex matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q15 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @param[in] pScratch points to an array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Conditions for optimum performance + Input, output and state buffers should be aligned by 32-bit + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then + truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t const *pInA = (q15_t const *) pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t const *pInB = (q15_t const *) pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t const *pInB2; + q15_t *px; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + uint16x8_t vecOffs, vecColBOffs; + arm_status status; /* Status of matrix multiplication */ + (void)pScratch; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + vecColBOffs[4] = 2 * numColsB * CMPLX_DIM; + vecColBOffs[5] = 2 * (numColsB * CMPLX_DIM) + 1; + vecColBOffs[6] = 3 * numColsB * CMPLX_DIM; + vecColBOffs[7] = 3 * (numColsB * CMPLX_DIM) + 1; + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA; + px = pDst->pData; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) + { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + j = 0; + /* + * column loop + */ + while (col > 0u) + { + q15_t const *pSrcAVec; + //, *pSrcBVec, *pSrcB2Vec; + q15x8_t vecA, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInB2 = pInB + CMPLX_DIM; + + j += 2 * CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + + /* + * Initiate the pointers + * - current Matrix A rows + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pSrcAVec = (q15_t const *) pInA; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + vecOffs = vecColBOffs; + + + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + vecB2 = vldrhq_gather_shifted_offset(pInB2, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + acc2 = vmlsldavaq_s16(acc2, vecA, vecB2); + acc3 = vmlaldavaxq_s16(acc3, vecA, vecB2); + + blkCnt--; + } + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + vecA = vldrhq_z_s16(pSrcAVec, p0); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + vecB2 = vldrhq_gather_shifted_offset(pInB2, vecOffs); + + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + acc2 = vmlsldavaq_s16(acc2, vecA, vecB2); + acc3 = vmlaldavaxq_s16(acc3, vecA, vecB2); + + } + /* + * Convert to 1.15, Store the results (1 x 2 block) in the destination buffer + */ + *px++ = (q15_t)MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc1, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc2, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc3, 15); + } + + col = numColsB & 1; + /* + * column loop + */ + while (col > 0u) + { + + q15_t const *pSrcAVec; + //, *pSrcBVec, *pSrcB2Vec; + q15x8_t vecA, vecB; + q63_t acc0, acc1; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + + j += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + + /* + * Initiate the pointers + * - current Matrix A rows + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pSrcAVec = (q15_t const *) pInA; + + acc0 = 0LL; + acc1 = 0LL; + + + vecOffs = vecColBOffs; + + + + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + blkCnt--; + } + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + vecA = vldrhq_z_s16(pSrcAVec, p0); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + + } + /* + * Convert to 1.15, Store the results (1 x 2 block) in the destination buffer + */ + *px++ = (q15_t)MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc1, 15); + + } + + i = i + numColsA * CMPLX_DIM; + + /* + * Decrement the row loop counter + */ + row--; + } + + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + q63_t sumReal, sumImag; /* accumulator */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t prod1, prod2; + q31_t pSourceA, pSourceB; +#else + q15_t a, b, c, d; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and exchange the columns with row elements */ + col = numColsB >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + col = numColsB; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + 2U; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sumReal = 0; + sumImag = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i * 2; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 1U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA buffer */ + a = *pInA; + b = *(pInA + 1U); + /* read real and imag values from pSrcB buffer */ + c = *pInB; + d = *(pInB + 1U); + + /* Multiply and Accumlates */ + sumReal += (q31_t) a *c; + sumImag += (q31_t) a *d; + sumReal -= (q31_t) b *d; + sumImag += (q31_t) b *c; + + /* read next real and imag values from pSrcA buffer */ + a = *(pInA + 2U); + b = *(pInA + 3U); + /* read next real and imag values from pSrcB buffer */ + c = *(pInB + 2U); + d = *(pInB + 3U); + + /* update pointer */ + pInA += 4U; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + /* update pointer */ + pInB += 4U; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ + if ((numColsA & 0x1U) > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a = *pInA++; + b = *pInA++; + c = *pInB++; + d = *pInB++; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + +#endif /* #if defined (ARM_MATH_DSP) */ + + } + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (__SSAT(sumReal >> 15, 16)); + *px++ = (q15_t) (__SSAT(sumImag >> 15, 16)); + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c new file mode 100644 index 0000000..9933865 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c @@ -0,0 +1,1065 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_q31.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q31 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM2; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM2 * CMPLX_DIM, MATRIX_DIM2 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc3, 31); + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + pOut += CMPLX_DIM; + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc3, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM3; + q31_t const *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM3; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecB1, vecA; + /* + * enable predication to disable upper half complex vector element + */ + mve_pred16_t p0 = vctp32q(CMPLX_DIM); + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM3 * CMPLX_DIM, MATRIX_DIM3 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { + 2 * MATRIX_DIM3 * CMPLX_DIM, 2 * MATRIX_DIM3 * CMPLX_DIM + 1, + INACTIVELANE, INACTIVELANE + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + vecColBOffs1 = vldrwq_u32(offsetB1); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM4; + q31_t const *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM4; + q31_t const *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecB1, vecA; + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM4 * CMPLX_DIM, MATRIX_DIM4 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { + 2 * MATRIX_DIM4 * CMPLX_DIM, 2 * MATRIX_DIM4 * CMPLX_DIM + 1, + 3 * MATRIX_DIM4 * CMPLX_DIM, 3 * MATRIX_DIM4 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + vecColBOffs1 = vldrwq_u32(offsetB1); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = (q31_t const *) pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = (q31_t const *) pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + q63_t sumReal = (q63_t) pInA[0] * pInB[0]; + sumReal -= (q63_t) pInA[1] * pInB[1]; + + q63_t sumImag = (q63_t) pInA[0] * pInB[1]; + sumImag += (q63_t) pInA[1] * pInB[0]; + + /* Store result in destination buffer */ + pOut[0] = (q31_t) clip_q63_to_q31(sumReal >> 31); + pOut[1] = (q31_t) clip_q63_to_q31(sumImag >> 31); + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 1; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 2 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec, *pSrcA1Vec; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + q63_t acc0, acc1, acc2, acc3; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + pSrcA1Vec = (q31_t const *) pInA1; + + + vecOffs = vecColBOffs; + + /* + * process 1 x 2 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + + acc2 = vmlsldavaq(acc2, vecA, vecB); + acc3 = vmlaldavaxq(acc3, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + + vecA = vld1q(pSrcA0Vec); + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + vecA = vld1q(pSrcA1Vec); + acc2 = vmlsldavaq(acc2, vecA, vecB); + acc3 = vmlaldavaxq(acc3, vecA, vecB); + + + } + + px[0 * CMPLX_DIM * numColsB + 0] = (q31_t) clip_q63_to_q31(acc0 >> 31); + px[0 * CMPLX_DIM * numColsB + 1] = (q31_t) clip_q63_to_q31(acc1 >> 31); + px[1 * CMPLX_DIM * numColsB + 0] = (q31_t) clip_q63_to_q31(acc2 >> 31); + px[1 * CMPLX_DIM * numColsB + 1] = (q31_t) clip_q63_to_q31(acc3 >> 31); + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 2) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 1; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec; + q31_t const *pInA0 = pInA; + q63_t acc0,acc1; + + acc0 = 0LL; + acc1 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 2 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + + + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + } + + px[0] = (q31_t) clip_q63_to_q31(acc0 >> 31); + px[1] = (q31_t) clip_q63_to_q31(acc1 >> 31); + + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + q63_t sumReal, sumImag; /* Accumulator */ + q31_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0; + sumImag = 0.0; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q31_t) clip_q63_to_q31(sumReal >> 31); + *px++ = (q31_t) clip_q63_to_q31(sumImag >> 31); + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c new file mode 100644 index 0000000..3e96414 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c @@ -0,0 +1,135 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_f16.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_f16(const arm_matrix_instance_f16 * pSrc, arm_matrix_instance_f16 * pDst) +{ + return arm_mat_cmplx_trans_16bit(pSrc->numRows, pSrc->numCols, (uint16_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint16_t *) pDst->pData); +} + +#else +arm_status arm_mat_cmplx_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c new file mode 100644 index 0000000..e551d07 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c @@ -0,0 +1,153 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_f32.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixComplexTrans Complex Matrix Transpose + + Tranposes a complex matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + + @par Transpose of a 3 x 3 matrix + + \f[ + \begin{pmatrix} + a_{1,1} & a_{1,2} & a_{1,3} \\ + a_{2,1} & a_{2,2} & a_{2,3} \\ + a_{3,1} & a_{3,2} & a_{3,3} \\ + \end{pmatrix}^T + = + \begin{pmatrix} + a_{1,1} & a_{2,1} & a_{3,1} \\ + a_{1,2} & a_{2,2} & a_{3,2} \\ + a_{1,3} & a_{2,3} & a_{3,3} \\ + \end{pmatrix} + \f] + + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_f32(const arm_matrix_instance_f32 * pSrc, arm_matrix_instance_f32 * pDst) +{ + return arm_mat_cmplx_trans_32bit(pSrc->numRows, pSrc->numCols, (uint32_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint32_t *) pDst->pData); +} + +#else +arm_status arm_mat_cmplx_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c new file mode 100644 index 0000000..1f80f12 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c @@ -0,0 +1,128 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_q31.c + * Description: Q15 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q15 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_q15(const arm_matrix_instance_q15 * pSrc, arm_matrix_instance_q15 * pDst) +{ + return arm_mat_cmplx_trans_16bit(pSrc->numRows, pSrc->numCols, (uint16_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint16_t *) pDst->pData); +} + + +#else +arm_status arm_mat_cmplx_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + pOut[0] = *pSrcA++; //real + pOut[1] = *pSrcA++; //imag + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += CMPLX_DIM *nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c new file mode 100644 index 0000000..ba38341 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c @@ -0,0 +1,133 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_q31.c + * Description: Q31 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q31 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +arm_status arm_mat_cmplx_trans_q31(const arm_matrix_instance_q31 * pSrc, arm_matrix_instance_q31 * pDst) +{ + return arm_mat_cmplx_trans_32bit(pSrc->numRows, pSrc->numCols, (uint32_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint32_t *) pDst->pData); +} + + +#else +arm_status arm_mat_cmplx_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } + while (row > 0U); /* row loop end */ + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c new file mode 100644 index 0000000..e5a7aa2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c @@ -0,0 +1,78 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_f16.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_f16( + arm_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c new file mode 100644 index 0000000..c9348fd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c @@ -0,0 +1,80 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_f32.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + Initializes the underlying matrix data structure. + The functions set the numRows, + numCols, and pData fields + of the matrix data structure. + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c new file mode 100644 index 0000000..bd2a7c2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c @@ -0,0 +1,71 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q15.c + * Description: Q15 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q15 matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c new file mode 100644 index 0000000..a9bcb52 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c @@ -0,0 +1,73 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q31.c + * Description: Q31 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q31 matrix initialization. + @param[in,out] S points to an instance of the Q31 matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c new file mode 100644 index 0000000..27ad218 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c @@ -0,0 +1,273 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f16.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + float16_t *pTmp; + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + + float16_t pivot = 0.0f16, newPivot=0.0f16; /* Temporary input values */ + uint32_t selectedRow,pivotRow,i, rowNb, rowCnt, flag = 0U, j,column; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pTmp = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pTmp++ = 0.0f16; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pTmp++ = 1.0f16; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pTmp++ = 0.0f16; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + + /* Index modifier to navigate through the columns */ + for(column = 0U; column < numCols; column++) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + pivotRow = column; + + /* Temporary variable to hold the pivot value */ + pTmp = ELEM(pSrc,column,column) ; + pivot = *pTmp; + selectedRow = column; + + + /* Loop over the number rows present below */ + + for (rowNb = column+1; rowNb < numRows; rowNb++) + { + /* Update the input and destination pointers */ + pTmp = ELEM(pSrc,rowNb,column); + newPivot = *pTmp; + if (fabsf((float32_t)newPivot) > fabsf((float32_t)pivot)) + { + selectedRow = rowNb; + pivot = newPivot; + } + + } + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (((_Float16)pivot != 0.0f16) && (selectedRow != column)) + { + /* Loop over number of columns + * to the right of the pilot element */ + + SWAP_ROWS_F16(pSrc,column, pivotRow,selectedRow); + SWAP_ROWS_F16(pDst,0, pivotRow,selectedRow); + + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && ((_Float16)pivot == 0.0f16)) + { + return ARM_MATH_SINGULAR; + } + + + /* Pivot element of the row */ + pivot = 1.0f16 / (_Float16)pivot; + + SCALE_ROW_F16(pSrc,column,pivot,pivotRow); + SCALE_ROW_F16(pDst,0,pivot,pivotRow); + + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + rowNb = 0; + for (;rowNb < pivotRow; rowNb++) + { + pTmp = ELEM(pSrc,rowNb,column) ; + pivot = *pTmp; + + MAS_ROW_F16(column,pSrc,rowNb,pivot,pSrc,pivotRow); + MAS_ROW_F16(0 ,pDst,rowNb,pivot,pDst,pivotRow); + + + } + + for (rowNb = pivotRow + 1; rowNb < numRows; rowNb++) + { + pTmp = ELEM(pSrc,rowNb,column) ; + pivot = *pTmp; + + MAS_ROW_F16(column,pSrc,rowNb,pivot,pSrc,pivotRow); + MAS_ROW_F16(0 ,pDst,rowNb,pivot,pDst,pivotRow); + + } + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && ((_Float16)pivot == 0.0f16)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if ((_Float16)pIn[i] != 0.0f16) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixInv group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c new file mode 100644 index 0000000..83e8577 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c @@ -0,0 +1,303 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f32.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInv Matrix Inverse + + Computes the inverse of a matrix. + + The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). + The function checks that the input and output matrices are square and of the same size. + + Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix + inversion of floating-point matrices. + + @par Algorithm + The Gauss-Jordan method is used to find the inverse. + The algorithm performs a sequence of elementary row-operations until it + reduces the input matrix to an identity matrix. Applying the same sequence + of elementary row-operations to an identity matrix yields the inverse matrix. + If the input matrix is singular, then the algorithm terminates and returns error status + ARM_MATH_SINGULAR. + + @par Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method + + \f[ + \begin{pmatrix} + a_{1,1} & a_{1,2} & a_{1,3} & | & 1 & 0 & 0\\ + a_{2,1} & a_{2,2} & a_{2,3} & | & 0 & 1 & 0\\ + a_{3,1} & a_{3,2} & a_{3,3} & | & 0 & 0 & 1\\ + \end{pmatrix} + \rightarrow + \begin{pmatrix} + 1 & 0 & 0 & | & x_{1,1} & x_{2,1} & x_{3,1} \\ + 0 & 1 & 0 & | & x_{1,2} & x_{2,2} & x_{3,2} \\ + 0 & 0 & 1 & | & x_{1,3} & x_{2,3} & x_{3,3} \\ + \end{pmatrix} + \f] + */ + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + float32_t *pTmp; + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + + float32_t pivot = 0.0f, newPivot=0.0f; /* Temporary input values */ + uint32_t selectedRow,pivotRow,i, rowNb, rowCnt, flag = 0U, j,column; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pTmp = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pTmp++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pTmp++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pTmp++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + + /* Index modifier to navigate through the columns */ + for(column = 0U; column < numCols; column++) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + pivotRow = column; + + /* Temporary variable to hold the pivot value */ + pTmp = ELEM(pSrc,column,column) ; + pivot = *pTmp; + selectedRow = column; + + /* Find maximum pivot in column */ + + /* Loop over the number rows present below */ + + for (rowNb = column+1; rowNb < numRows; rowNb++) + { + /* Update the input and destination pointers */ + pTmp = ELEM(pSrc,rowNb,column); + newPivot = *pTmp; + if (fabsf(newPivot) > fabsf(pivot)) + { + selectedRow = rowNb; + pivot = newPivot; + } + } + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if ((pivot != 0.0f) && (selectedRow != column)) + { + + SWAP_ROWS_F32(pSrc,column, pivotRow,selectedRow); + SWAP_ROWS_F32(pDst,0, pivotRow,selectedRow); + + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + } + + + + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (pivot == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + + /* Pivot element of the row */ + pivot = 1.0f / pivot; + + SCALE_ROW_F32(pSrc,column,pivot,pivotRow); + SCALE_ROW_F32(pDst,0,pivot,pivotRow); + + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + rowNb = 0; + for (;rowNb < pivotRow; rowNb++) + { + pTmp = ELEM(pSrc,rowNb,column) ; + pivot = *pTmp; + + MAS_ROW_F32(column,pSrc,rowNb,pivot,pSrc,pivotRow); + MAS_ROW_F32(0 ,pDst,rowNb,pivot,pDst,pivotRow); + + + } + + for (rowNb = pivotRow + 1; rowNb < numRows; rowNb++) + { + pTmp = ELEM(pSrc,rowNb,column) ; + pivot = *pTmp; + + MAS_ROW_F32(column,pSrc,rowNb,pivot,pSrc,pivotRow); + MAS_ROW_F32(0 ,pDst,rowNb,pivot,pDst,pivotRow); + + } + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (pivot == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixInv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c new file mode 100644 index 0000000..9b13e3b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c @@ -0,0 +1,267 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f64.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point (64 bit) matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + + float64_t *pTmp; + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + + float64_t pivot = 0.0, newPivot=0.0; /* Temporary input values */ + uint32_t selectedRow,pivotRow,i, rowNb, rowCnt, flag = 0U, j,column; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pTmp = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pTmp++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pTmp++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pTmp++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + + /* Index modifier to navigate through the columns */ + for(column = 0U; column < numCols; column++) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + pivotRow = column; + + /* Temporary variable to hold the pivot value */ + pTmp = ELEM(pSrc,column,column) ; + pivot = *pTmp; + selectedRow = column; + + + /* Loop over the number rows present below */ + + for (rowNb = column+1; rowNb < numRows; rowNb++) + { + /* Update the input and destination pointers */ + pTmp = ELEM(pSrc,rowNb,column); + newPivot = *pTmp; + if (fabs(newPivot) > fabs(pivot)) + { + selectedRow = rowNb; + pivot = newPivot; + } + } + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if ((pivot != 0.0) && (selectedRow != column)) + { + /* Loop over number of columns + * to the right of the pilot element */ + + SWAP_ROWS_F64(pSrc,column, pivotRow,selectedRow); + SWAP_ROWS_F64(pDst,0, pivotRow,selectedRow); + + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (pivot == 0.0)) + { + return ARM_MATH_SINGULAR; + } + + + /* Pivot element of the row */ + pivot = 1.0 / pivot; + + SCALE_ROW_F64(pSrc,column,pivot,pivotRow); + SCALE_ROW_F64(pDst,0,pivot,pivotRow); + + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + rowNb = 0; + for (;rowNb < pivotRow; rowNb++) + { + pTmp = ELEM(pSrc,rowNb,column) ; + pivot = *pTmp; + + MAS_ROW_F64(column,pSrc,rowNb,pivot,pSrc,pivotRow); + MAS_ROW_F64(0 ,pDst,rowNb,pivot,pDst,pivotRow); + + + } + + for (rowNb = pivotRow + 1; rowNb < numRows; rowNb++) + { + pTmp = ELEM(pSrc,rowNb,column) ; + pivot = *pTmp; + + MAS_ROW_F64(column,pSrc,rowNb,pivot,pSrc,pivotRow); + MAS_ROW_F64(0 ,pDst,rowNb,pivot,pDst,pivotRow); + + } + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (pivot == 0.0)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixInv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c new file mode 100644 index 0000000..3fa0b43 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c @@ -0,0 +1,462 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_ldl_f32.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ +arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pl, + arm_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + + memset(pd->pData,0,sizeof(float32_t)*n*n); + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + int cnt = n; + uint16x8_t vecP; + + for(int k=0;k < n; k+=8) + { + mve_pred16_t p0; + p0 = vctp16q(cnt); + + vecP = vidupq_u16((uint16_t)k, 1); + + vstrhq_p(&pp[k], vecP, p0); + + cnt -= 8; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + for(int r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pl,0,k,j); + SWAP_COLS_F32(pl,0,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabsf(a) < 1.0e-8f) + { + + fullRank = 0; + break; + } + + float32_t invA; + + invA = 1.0f / a; + + int32x4_t vecOffs; + int w; + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vmulq_n_s32(vecOffs,n); + + for(w=k+1; wpData[row*n+col], zero, p0); + + cnt -= 4; + } + } + } + + for(int row=0; row < n;row++) + { + mve_pred16_t p0; + int cnt= n-row-1; + f32x4_t zero=vdupq_n_f32(0.0f); + + for(int col=row+1; col < n;col+=4) + { + p0 = vctp32q(cnt); + + vstrwq_p(&pl->pData[row*n+col], zero, p0); + + cnt -= 4; + } + } + + for(int d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#else + + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ +arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pl, + arm_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + int row,d; + + memset(pd->pData,0,sizeof(float32_t)*n*n); + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + for(k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + int r; + int w; + + for(r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pl,0,k,j); + SWAP_COLS_F32(pl,0,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabsf(a) < 1.0e-8f) + { + + fullRank = 0; + break; + } + + for(w=k+1;wpData[row*n+col]=0.0; + } + } + } + + for(row=0; row < n;row++) + { + int col; + for(col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + + for(d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c new file mode 100644 index 0000000..55b131a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c @@ -0,0 +1,208 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_ldl_f64.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + +#include + + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ + +arm_status arm_mat_ldlt_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pl, + arm_matrix_instance_f64 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float64_t *pA; + + memset(pd->pData,0,sizeof(float64_t)*n*n); + + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float64_t)); + pA = pl->pData; + + for(k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float64_t m=F64_MIN,a; + int w,r,j=k; + + + for(r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F64(pl,0,k,j); + SWAP_COLS_F64(pl,0,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabs(a) < 1.0e-18) + { + + fullRank = 0; + break; + } + + for(w=k+1;wpData[row*n+col]=0.0; + } + } + } + } + + { + int row; + for(row=0; row < n;row++) + { + int col; + for(col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + } + + { + int d; + for(d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c new file mode 100644 index 0000000..45c6570 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c @@ -0,0 +1,767 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_2x2_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + static const uint16_t offsetA[8] = { 0, 0, 2, 2, 0, 0, 2, 2 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 0, 1, 0, 1, 0, 1 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + /* + * load {a00 a00 a10 a10 x x x x } + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b00 b01 x x x x } + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 + * a10 b00 a10 b01 + * x x + * x x } + */ + vecDst = vmulq(vecInA, vecInB); + /* + * move to 2nd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a01 a01 a11 a11 x x x x} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 2); + /* + * load {b10, b11, b10, b11, x x x x } + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 + * a10 b00 + a11 b10 a10 b01 + a11 b11 + * x x + * x x } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + + mve_pred16_t p0 = vctp16q(2*2); + /* + * Store the result in the destination buffer + * (lower half of the vector) + */ + vstrhq_p(pOut, vecDst, p0); + + return (ARM_MATH_SUCCESS); +} + + + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_3x3_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + static const uint16_t offsetA[8] = { 0, 0, 0, 3, 3, 3, 6, 6 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 2, 0, 1, 2, 0, 1 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + + /* + * load {a00 a00 a00 a10 a10 a10 a20 a20} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b02 b00 b01 b02 b00 b01} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 a00 b02 + * a10 b00 a10 b01 a10 b02 + * a20 b00 a20 b01} + */ + vecDst = vmulq(vecInA, vecInB); + + /* + * move to 2nd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a01 a01 a01 a11 a11 a11 a21 a21} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 3); + /* + * load {b10, b11, b12, b10, b11, b12, b10, b11} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 a00 b02 + a01 b12 + * a10 b00 + a11 b10 a10 b01 + a11 b11 a10 b02 + a11 b12 + * a20 b00 + a21 b10 a20 b01 + a21 b11 } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + /* + * move to 3rd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a02 a02 a02 a12 a12 a12 a22 a22} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 3); + /* + * load {b20, b21, b22, b20, b21, b22, b20, b21} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * {a00 b00 + a01 b10 + a02 b20 a00 b01 + a01 b11 + a02 b21 a00 b02 + a01 b12 + a02 b22}, + * a10 b00 + a11 b10 + a12 b20 a10 b01 + a11 b11 + a12 b21 a10 b02 + a11 b12 + a12 b22}, + * a20 b00 + a21 b10 + a22 b20 a20 b01 + a21 b11 + a22 b21 } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + + /* + * Store the result in the destination buffer + */ + vst1q(pOut, vecDst); pOut += 8; + + /* last element computed in scalar mode + * a20 b02 + a21 b12 + a22 b22 + */ + _Float16 * pA = (_Float16 *)pSrcA->pData; + _Float16 * pB = (_Float16 *)pSrcB->pData; + *pOut = pA[2*3] * pB[2] + pA[2*3+1] * pB[3+2] + pA[2*3+2] * pB[2*3+2]; + + return (ARM_MATH_SUCCESS); +} + + + + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_4x4_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + /* offsetA allows to read and duplicate 2 successive column elements of A */ + static const uint16_t offsetA[8] = { 0, 0, 0, 0, 4, 4, 4, 4 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 2, 3, 0, 1, 2, 3 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst0, vecDst1; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + + /* + * load {a00 a00 a00 a00 a10 a10 a10 a10} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b02 b03 b00 b01 b02 b03} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 a00 b02 a00 b03 + * a10 b00 a10 b01 a10 b02 a10 b03 } + */ + vecDst0 = vmulq(vecInA, vecInB); + /* + * jump 2 x A rows (2nd half of matrix) + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a20 a20 a20 a20 a30 a30 a30 a30} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * { a20 b00 a20 b01 a20 b02 a20 b03 + * a30 b00 a30 b01 a30 b02 + a31 b12 } + */ + vecDst1 = vmulq(vecInA, vecInB); + /* + * rewind back to top half of the A matrix (2nd column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a01 a01 a01 a01 a11 a11 a11 a11} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b10, b11, b12, b13, b10, b11, b12, b13} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 a00 b02 + a01 b12 a00 b03 + a01 b13 + * a10 b00 + a11 b10 a10 b01 + a11 b11 a10 b02 + a11 b12 a10 b03 + a11 b13 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows (2nd half of matrix) + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a21 a21 a21 a21 a31 a31 a31 a31} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 + a21 b10 a20 b01 + a21 b11 a20 b02 + a21 b12 a20 b03 + a21 b13 + * a30 b00 + a31 b10 a30 b01 + a31 b11 a30 b02 + a31 b12 a30 b03 + a31 b13 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * rewind back to top half of the A matrix (3rd column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a02 a02 a02 a02 a12 a12 a12 a12} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b20, b21, b22, b23, b20, b21, b22, b23} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 + a02 b20 a00 b01 + a01 b11 + a02 b21 a00 b02 + a01 b12 + a02 b22 a00 b03 + a01 b13 + a02 b23 + * a10 b00 + a11 b10 + a12 b20 a10 b01 + a11 b11 + a12 b21 a10 b02 + a11 b12 + a12 b22 a10 b03 + a11 b13 + a12 b23 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + + /* + * load {a22 a22 a22 a22 a32 a32 a32 a32} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 + a21 b10 + a22 b20 a20 b01 + a21 b11 + a22 b21 a20 b02 + a21 b12 + a22 b22 a20 b03 + a21 b13 + a22 b23 + * a30 b00 + a31 b10 + a32 b20 a30 b01 + a31 b11 + a32 b21 a30 b02 + a31 b12 + a32 b22 a30 b03 + a31 b13 + a32 b23 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * rewind back to top half of the A matrix (4th column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a03 a03 a03 a03 a13 a13 a13 a13} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b30, b31, b32, b33, b30, b31, b32, b33} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 +...+ a03 b30, a00 b01 +...+ a03 b31, a00 b02 +...+ a03 b32, a00 b03 +...+ a03 b33 + * a10 b00 +...+ a13 b30, a10 b01 +...+ a13 b31, a10 b02 +...+ a13 b32, a10 b03 +...+ a13 b33 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a23 a23 a23 a23 a33 a33 a33 a33} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 +...+ a23 b30, a20 b01 +...+ a23 b31, a20 b02 +...+ a23 b32, a20 b03 +...+ a23 b33 + * a30 b00 +...+ a33 b30, a30 b01 +...+ a33 b31, a30 b02 +...+ a33 b32, a30 b03 +...+ a33 b33 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * Store the result in the destination buffer + */ + vst1q(pOut, vecDst0); pOut += 8; + vst1q(pOut, vecDst1); + + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + int numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + int numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + int numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t blkCnt; /* loop counters */ + int i; + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + return(ARM_MATH_SIZE_MISMATCH); + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ +{ + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if(numRowsA == 2) + return arm_mat_mult_f16_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_f16_3x3_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 4) + return arm_mat_mult_f16_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* main loop process 4 rows */ + i = numRowsA / 4; + while(i > 0) + { + float16_t *pInA0, *pInA1, *pInA2, *pInA3; + float16_t *pInB0; + float16_t *pOut0, *pOut1, *pOut2, *pOut3; + f16x8_t vecMac0, vecMac1, vecMac2, vecMac3; + f16x8_t vecInB; + + /* pointers to 4 consecutive output rows */ + pOut0 = pOut; + pOut1 = pOut0 + numColsB; + pOut2 = pOut1 + numColsB; + pOut3 = pOut2 + numColsB; + pInB0 = pInB; + + int k = numColsB >> 3; + while(k > 0) + { + /* pointers to 4 consecutive Matrix A rows */ + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + + vecMac0 = vdupq_n_f16(0.0f16); + vecMac1 = vdupq_n_f16(0.0f16); + vecMac2 = vdupq_n_f16(0.0f16); + vecMac3 = vdupq_n_f16(0.0f16); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3..., bi,4n+7} + */ + vecInB = *(f16x8_t *)pInB0; /* vldrhq_f16(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x 8 block) in the destination buffer */ + vst1q(pOut0, vecMac0); pOut0 += 8; + vst1q(pOut1, vecMac1); pOut1 += 8; + vst1q(pOut2, vecMac2); pOut2 += 8; + vst1q(pOut3, vecMac3); pOut3 += 8; + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 8; + k--; + } + + int colBLeft = numColsB & 7; + if (colBLeft) + { + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + mve_pred16_t p0 = vctp16q(colBLeft); + + vecMac0 = vdupq_n_f16(0.0f16); + vecMac1 = vdupq_n_f16(0.0f16); + vecMac2 = vdupq_n_f16(0.0f16); + vecMac3 = vdupq_n_f16(0.0f16); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, ..bi,4n+colBLeft-1, 0, ..} + */ + vecInB = vldrhq_z_f16(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x colBLeft block) in the destination buffer */ + vstrhq_p_f16(pOut0, vecMac0, p0); + vstrhq_p_f16(pOut1, vecMac1, p0); + vstrhq_p_f16(pOut2, vecMac2, p0); + vstrhq_p_f16(pOut3, vecMac3, p0); + } + + pInA += 4 * numColsA; + pOut += 4 * numColsB; + i--; + } + + /* + * non multiple of 4 rows for Matrix A + * process single row + */ + if (numRowsA & 3) + { + i = numRowsA & 3; + do + { + float16_t *pInA0; + float16_t *pInB0; + float16_t *pOut0; + f16x8_t vecInB; + f16x8_t vecMac0; + + pOut0 = pOut; + pInB0 = pInB; + + int k = numColsB >> 3; + while(k > 0) + { + pInA0 = pInA; + + vecMac0 = vdupq_n_f16(0.0f16); + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3, ...bi,4n+7} + */ + vecInB = *(f16x8_t *)pInB0; /* vldrhq_f16(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x 8 block) in the destination buffer */ + vst1q(pOut0, vecMac0); pOut0 += 8; + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 8; + k--; + } + + int colBLeft = numColsB & 7; + if (colBLeft) + { + pInA0 = pInA; + mve_pred16_t p0 = vctp16q(colBLeft); + + vecMac0 = vdupq_n_f16(0.0f16); + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, ..., bi,4n+colBLeft, 0, ...} + */ + vecInB = vldrhq_z_f16(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x colBLeft block) in the destination buffer */ + vstrhq_p_f16(pOut0, vecMac0, p0); + } + + pInA += 1 * numColsA; + pOut += 1 * numColsB; + } + while (--i); + } + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); + } +} +#else + + +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + _Float16 sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f16; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c new file mode 100644 index 0000000..ed1fe6e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c @@ -0,0 +1,1025 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +#if defined(ARM_MATH_NEON) +#define GROUPOFROWS 8 +#endif + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * @par Multiplication of two 3x3 matrices: + * + * \f[ + * \begin{pmatrix} + * a_{1,1} & a_{1,2} & a_{1,3} \\ + * a_{2,1} & a_{2,2} & a_{2,3} \\ + * a_{3,1} & a_{3,2} & a_{3,3} \\ + * \end{pmatrix} + * + * \begin{pmatrix} + * b_{1,1} & b_{1,2} & b_{1,3} \\ + * b_{2,1} & b_{2,2} & b_{2,3} \\ + * b_{3,1} & b_{3,2} & b_{3,3} \\ + * \end{pmatrix} + * = + * \begin{pmatrix} + * a_{1,1} b_{1,1}+a_{1,2} b_{2,1}+a_{1,3} b_{3,1} & a_{1,1} b_{1,2}+a_{1,2} b_{2,2}+a_{1,3} b_{3,2} & a_{1,1} b_{1,3}+a_{1,2} b_{2,3}+a_{1,3} b_{3,3} \\ + * a_{2,1} b_{1,1}+a_{2,2} b_{2,1}+a_{2,3} b_{3,1} & a_{2,1} b_{1,2}+a_{2,2} b_{2,2}+a_{2,3} b_{3,2} & a_{2,1} b_{1,3}+a_{2,2} b_{2,3}+a_{2,3} b_{3,3} \\ + * a_{3,1} b_{1,1}+a_{3,2} b_{2,1}+a_{3,3} b_{3,1} & a_{3,1} b_{1,2}+a_{3,2} b_{2,2}+a_{3,3} b_{3,2} & a_{3,1} b_{1,3}+a_{3,2} b_{2,3}+a_{3,3} b_{3,3} \\ + * \end{pmatrix} + * \f] + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_f32_2x2_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + /* {a00, a00, a10, a10} */ + static const uint32_t offsetA0[4] = { 0, 0, 2, 2 }; + /* {b00, b01, b00, b01} */ + static const uint32_t offsetB0[4] = { 0, 1, 0, 1 }; + /* {a01, a01, a11, a11} */ + static const uint32_t offsetA1[4] = { 1, 1, 3, 3 }; + /* {b10, b11, b10, b11} */ + static const uint32_t offsetB1[4] = { 2, 3, 2, 3 }; + + uint32x4_t vecOffsA, vecOffsB; + f32x4_t vecInA, vecInB, vecDst; + + vecOffsA = vldrwq_u32((uint32_t const *) offsetA0); + vecOffsB = vldrwq_u32((uint32_t const *) offsetB0); + + vecInA = vldrwq_gather_shifted_offset((float32_t const *) pSrcA->pData, vecOffsA); + vecInB = vldrwq_gather_shifted_offset((float32_t const *) pSrcB->pData, vecOffsB); + + vecDst = vmulq(vecInA, vecInB); + + vecOffsA = vldrwq_u32((uint32_t const *) offsetA1); + vecOffsB = vldrwq_u32((uint32_t const *) offsetB1); + + vecInA = vldrwq_gather_shifted_offset((float32_t const *) pSrcA->pData, vecOffsA); + vecInB = vldrwq_gather_shifted_offset((float32_t const *) pSrcB->pData, vecOffsB); + + vecDst = vfmaq(vecDst, vecInA, vecInB); + + vstrwq_f32(pDst->pData, vecDst); + + return (ARM_MATH_SUCCESS); + +} + + +/* + * A = {{a00, a01, a02}, + * {a10, a11, a12}, + * {a20, a21, a22}} + * B = {{b00, b01, b02}, + * {b10, b11, b12}, + * {b20, b21, b22}} + * + * Dst = {{a00 b00 + a01 b10 + a02 b20, a00 b01 + a01 b11 + a02 b21, a00 b02 + a01 b12 + a02 b22}, + * {a10 b00 + a11 b10 + a12 b20, a10 b01 + a11 b11 + a12 b21, a10 b02 + a11 b12 + a12 b22}, + * {a20 b00 + a21 b10 + a22 b20, a20 b01 + a21 b11 + a22 b21, a20 b02 + a21 b12 + a22 b22}} + */ +__STATIC_INLINE arm_status arm_mat_mult_f32_3x3_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInA0, *pInA1, *pInA2; + f32x4_t vecMac0, vecMac1, vecMac2; + f32x4_t vecInB; + float32_t const *pSrBVec; + + pSrBVec = (float32_t const *) pInB; + + pInA0 = pInA; + pInA1 = pInA0 + MATRIX_DIM3; + pInA2 = pInA1 + MATRIX_DIM3; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + /* + * load {b0,0, b0,1, b0,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vmulq(vecInB, *pInA0++); + vecMac1 = vmulq(vecInB, *pInA1++); + vecMac2 = vmulq(vecInB, *pInA2++); + /* + * load {b1,0, b1,1, b1,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + /* + * load {b2,0, b2,1 , b2,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + + /* partial vector stores */ + vstrwq_p_f32(pOut, vecMac0, p0); + pOut += MATRIX_DIM3; + vstrwq_p_f32(pOut, vecMac1, p0); + pOut += MATRIX_DIM3; + vstrwq_p_f32(pOut, vecMac2, p0); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + + +__STATIC_INLINE arm_status arm_mat_mult_f32_4x4_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + float32_t const *pSrBVec; + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInA0, *pInA1, *pInA2, *pInA3; + f32x4_t vecMac0, vecMac1, vecMac2, vecMac3; + f32x4_t vecInB; + + pSrBVec = (float32_t const *) pInB; + + pInA0 = pInA; + pInA1 = pInA0 + MATRIX_DIM4; + pInA2 = pInA1 + MATRIX_DIM4; + pInA3 = pInA2 + MATRIX_DIM4; + /* + * load {b0,0, b0,1, b0,2, b0,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vmulq(vecInB, *pInA0++); + vecMac1 = vmulq(vecInB, *pInA1++); + vecMac2 = vmulq(vecInB, *pInA2++); + vecMac3 = vmulq(vecInB, *pInA3++); + /* + * load {b1,0, b1,1, b1,2, b1,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + /* + * load {b2,0, b2,1, b2,2, b2,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + /* + * load {b3,0, b3,1, b3,2, b3,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + vst1q(pOut, vecMac0); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac1); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac2); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac3); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + int numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + int numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + int numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t blkCnt; /* loop counters */ + uint32_t i; + arm_status status; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + pOut[0] = pInA[0] * pInB[0]; + return(ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_f32_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_f32_3x3_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 4) + return arm_mat_mult_f32_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* main loop process 4 rows */ + i = numRowsA >> 2; + while (i > 0U) + { + float32_t *pInA0, *pInA1, *pInA2, *pInA3; + float32_t *pInB0; + float32_t *pOut0, *pOut1, *pOut2, *pOut3; + f32x4_t vecMac0, vecMac1, vecMac2, vecMac3; + f32x4_t vecInB; + + /* pointers to 4 consecutive output rows */ + pOut0 = pOut; + pOut1 = pOut0 + numColsB; + pOut2 = pOut1 + numColsB; + pOut3 = pOut2 + numColsB; + pInB0 = pInB; + + uint32_t k = numColsB >> 2; + while (k > 0U) + { + /* pointers to 4 consecutive Matrix A rows */ + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + + vecMac0 = vdupq_n_f32(0.0f); + vecMac1 = vdupq_n_f32(0.0f); + vecMac2 = vdupq_n_f32(0.0f); + vecMac3 = vdupq_n_f32(0.0f); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = *(f32x4_t *)pInB0; /* vldrwq_f32(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x 4 block) in the destination buffer */ + vst1q(pOut0, vecMac0); + pOut0 += 4; + vst1q(pOut1, vecMac1); + pOut1 += 4; + vst1q(pOut2, vecMac2); + pOut2 += 4; + vst1q(pOut3, vecMac3); + pOut3 += 4; + + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 4; + k--; + } + + int colBLeft = numColsB & 3; + if (colBLeft) + { + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + mve_pred16_t p0 = vctp32q(colBLeft); + + vecMac0 = vdupq_n_f32(0.0f); + vecMac1 = vdupq_n_f32(0.0f); + vecMac2 = vdupq_n_f32(0.0f); + vecMac3 = vdupq_n_f32(0.0f); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = vldrwq_z_f32(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x colBLeft block) in the destination buffer */ + vstrwq_p_f32(pOut0, vecMac0, p0); + vstrwq_p_f32(pOut1, vecMac1, p0); + vstrwq_p_f32(pOut2, vecMac2, p0); + vstrwq_p_f32(pOut3, vecMac3, p0); + } + + /* move to next rows */ + pInA += 4 * numColsA; + pOut += 4 * numColsB; + i--; + } + + /* + * non multiple of 4 rows for Matrix A + * process single row + */ + if (numRowsA & 3) + { + i = numRowsA & 3; + while (i > 0U) + { + float32_t *pInA0; + float32_t *pInB0; + float32_t *pOut0; + f32x4_t vecInB; + f32x4_t vecMac0; + + pOut0 = pOut; + pInB0 = pInB; + + uint32_t k = numColsB >> 2; + while (k > 0U) + { + pInA0 = pInA; + + vecMac0 = vdupq_n_f32(0.0f); + blkCnt = numColsA; + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = *(f32x4_t *)pInB0; /* vldrwq_f32(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (1 x 4 block) in the destination buffer */ + vst1q(pOut0, vecMac0); + pOut0 += 4; + + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 4; + k--; + } + + int colBLeft = numColsB & 3; + if (colBLeft) + { + pInA0 = pInA; + mve_pred16_t p0 = vctp32q(colBLeft); + + vecMac0 = vdupq_n_f32(0.0f); + blkCnt = numColsA; + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = vldrwq_z_f32(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x colBLeft block) in the destination buffer */ + vstrwq_p_f32(pOut0, vecMac0, p0); + } + + /* move to next row */ + pInA += 1 * numColsA; + pOut += 1 * numColsB; + i--; + } + + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else + +#if defined(ARM_MATH_NEON) +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + + + uint16_t col, i = 0U, j, row = numRowsA, rowCnt, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + + float32x4_t a0V, a1V, a2V, a3V, a4V, a5V, a6V, a7V; + float32x4_t acc0,acc1,acc2,acc3,acc4,acc5,acc6,acc7,temp; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + float32_t *pIn1C = pSrcA->pData; + float32_t *pIn1D = pSrcA->pData; + float32_t *pIn1E = pSrcA->pData; + float32_t *pIn1F = pSrcA->pData; + float32_t *pIn1G = pSrcA->pData; + float32_t *pIn1H = pSrcA->pData; + + float32_t *pxB,*pxC, *pxD, *pxE, *pxF, *pxG, *pxH; /* Temporary output data matrix pointer */ + float32_t sum0,sum1, sum2,sum3, sum4, sum5 , sum6, sum7; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* Row loop */ + rowCnt = row >> 3; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + GROUPOFROWS*i; + pxB = px + numColsB; + pxC = px + 2*numColsB; + pxD = px + 3*numColsB; + pxE = px + 4*numColsB; + pxF = px + 5*numColsB; + pxG = px + 6*numColsB; + pxH = px + 7*numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum0 = 0.0f; + sum1 = 0.0f; + sum2 = 0.0f; + sum3 = 0.0f; + sum4 = 0.0f; + sum5 = 0.0f; + sum6 = 0.0f; + sum7 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + numColsA; + pIn1C = pIn1 + 2*numColsA; + pIn1D = pIn1 + 3*numColsA; + pIn1E = pIn1 + 4*numColsA; + pIn1F = pIn1 + 5*numColsA; + pIn1G = pIn1 + 6*numColsA; + pIn1H = pIn1 + 7*numColsA; + + acc0 = vdupq_n_f32(0.0); + acc1 = vdupq_n_f32(0.0); + acc2 = vdupq_n_f32(0.0); + acc3 = vdupq_n_f32(0.0); + acc4 = vdupq_n_f32(0.0); + acc5 = vdupq_n_f32(0.0); + acc6 = vdupq_n_f32(0.0); + acc7 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); + a1V = vld1q_f32(pIn1B); + a2V = vld1q_f32(pIn1C); + a3V = vld1q_f32(pIn1D); + a4V = vld1q_f32(pIn1E); + a5V = vld1q_f32(pIn1F); + a6V = vld1q_f32(pIn1G); + a7V = vld1q_f32(pIn1H); + + pIn1 += 4; + pIn1B += 4; + pIn1C += 4; + pIn1D += 4; + pIn1E += 4; + pIn1F += 4; + pIn1G += 4; + pIn1H += 4; + + temp = vsetq_lane_f32(*pIn2,temp,0); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,1); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,2); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,3); + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + acc1 = vmlaq_f32(acc1,a1V,temp); + acc2 = vmlaq_f32(acc2,a2V,temp); + acc3 = vmlaq_f32(acc3,a3V,temp); + acc4 = vmlaq_f32(acc4,a4V,temp); + acc5 = vmlaq_f32(acc5,a5V,temp); + acc6 = vmlaq_f32(acc6,a6V,temp); + acc7 = vmlaq_f32(acc7,a7V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum0 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1)); + sum1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2)); + sum2 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3)); + sum3 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc4), vget_high_f32(acc4)); + sum4 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc5), vget_high_f32(acc5)); + sum5 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc6), vget_high_f32(acc6)); + sum6 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc7), vget_high_f32(acc7)); + sum7 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum0 += *pIn1++ * (*pIn2); + sum1 += *pIn1B++ * (*pIn2); + sum2 += *pIn1C++ * (*pIn2); + sum3 += *pIn1D++ * (*pIn2); + sum4 += *pIn1E++ * (*pIn2); + sum5 += *pIn1F++ * (*pIn2); + sum6 += *pIn1G++ * (*pIn2); + sum7 += *pIn1H++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum0; + *pxB++ = sum1; + *pxC++ = sum2; + *pxD++ = sum3; + *pxE++ = sum4; + *pxF++ = sum5; + *pxG++ = sum6; + *pxH++ = sum7; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + GROUPOFROWS*numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + /* + + i was the index of a group of rows computed by previous loop. + Now i is the index of a row since below code is computing row per row + and no more group of row per group of rows. + + */ + + i = GROUPOFROWS*i; + rowCnt = row & 7; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + acc0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 4; + + temp = vsetq_lane_f32(*pIn2,temp,0); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,1); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,2); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,3); + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum += *pIn1++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c new file mode 100644 index 0000000..08571c7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c @@ -0,0 +1,189 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f64.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + +arm_status arm_mat_mult_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* Output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + float64_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint64_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + + +/** + * @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c new file mode 100644 index 0000000..57eda5b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c @@ -0,0 +1,487 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q15.c + * Description: Q15 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q15() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.15 x 1.15 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.15 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 16 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q15() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q31_t sum; /* Accumulator */ + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t in; /* Temporary variable to hold the input value */ + q31_t inA1, inB1, inA2, inB2; + q31_t sum2, sum3, sum4; + q15_t *pInA2, *pInB2, *px2; + uint32_t j = 0; +#else + q15_t in; /* Temporary variable to hold the input value */ + q15_t inA1, inB1, inA2, inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + /* Apply loop unrolling and exchange columns with row elements */ + col = numColsB >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + +#if defined (ARM_MATH_DSP) + + /* Read two elements from row */ + in = read_q15x2_ia (&pInB); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = read_q15x2_ia (&pInB); +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Read one element from row */ + in = *pInB++; + + /* Store one element in destination */ + *px = in; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pInB++; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + +#if defined (ARM_MATH_DSP) + /* Process two rows from matrix A at a time and output two rows at a time */ + row = row >> 1U; + px2 = px + numColsB; +#endif + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + +#if defined (ARM_MATH_DSP) + /* Process two (transposed) columns from matrix B at a time */ + col = col >> 1U; + j = 0; +#endif + + /* column loop */ + while (col > 0U) + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + +#if defined (ARM_MATH_DSP) + sum2 = 0; + sum3 = 0; + sum4 = 0; + pInB = pSrcBT + j; + pInA2 = pInA + numColsA; + pInB2 = pInB + numRowsB; + + /* Read in two elements at once - allows dual MAC instruction */ + colCnt = numColsA >> 1U; +#else + colCnt = numColsA >> 2U; +#endif + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + + inA2 = read_q15x2_ia (&pInA2); + inB2 = read_q15x2_ia (&pInB2); + + /* Multiply and Accumulates */ + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); +#else + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = *pInA++; + inB1 = *pInB++; + /* Multiply and Accumulates */ + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; + + inA1 = *pInA++; + inB1 = *pInB++; + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ +#if defined (ARM_MATH_DSP) + if (numColsA & 1U) { + inA1 = *pInA++; + inB1 = *pInB++; + inA2 = *pInA2++; + inB2 = *pInB2++; + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + } +#else + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += (q31_t) *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + +#if defined (ARM_MATH_DSP) + *px++ = (q15_t) (sum2 >> 15); + *px2++ = (q15_t) (sum3 >> 15); + *px2++ = (q15_t) (sum4 >> 15); + j += numRowsB * 2; +#endif + + /* Decrement column loop counter */ + col--; + + } + + i = i + numColsA; + +#if defined (ARM_MATH_DSP) + i = i + numColsA; + px = px2 + (numColsB & 1U); + px2 = px + numColsB; +#endif + + /* Decrement row loop counter */ + row--; + + } + + /* Compute any remaining odd row/column below */ + +#if defined (ARM_MATH_DSP) + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~0x1); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcBT + numRowsB * (numColsB-1); + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia (&pInA); + inA2 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + inB2 = read_q15x2_ia (&pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA & 3U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + colCnt--; + } + + /* Store result in destination buffer */ + *px = (q15_t) (sum >> 15); + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + pInB = pSrcBT; + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia (&pInA); + inA2 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + inB2 = read_q15x2_ia (&pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA % 4U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + + /* Decrement column loop counter */ + col--; + } + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c new file mode 100644 index 0000000..1107562 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c @@ -0,0 +1,378 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q31.c + * Description: Q31 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q31() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.31 x 1.31 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; + q31_t sum1, sum2, sum3, sum4; /* Accumulator */ + q31_t inA1, inA2, inB1, inB2; + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + px = pDst->pData; + + row = row >> 1U; + px2 = px + numColsB; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pInB = pSrcB->pData; + + j = 0U; + + col = col >> 1U; + + /* column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum1 = 0; + sum2 = 0; + sum3 = 0; + sum4 = 0; + + /* Initiate data pointers */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInA2 = pInA + numColsA; + + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + inA1 = *pInA++; + inB1 = pInB[0]; + inA2 = *pInA2++; + inB2 = pInB[1]; + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum2 = __SMMLA(inA1, inB2, sum2); + sum3 = __SMMLA(inA2, inB1, sum3); + sum4 = __SMMLA(inA2, inB2, sum4); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum2 = (q31_t) ((((q63_t) sum2 << 32) + ((q63_t) inA1 * inB2)) >> 32); + sum3 = (q31_t) ((((q63_t) sum3 << 32) + ((q63_t) inA2 * inB1)) >> 32); + sum4 = (q31_t) ((((q63_t) sum4 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px++ = sum1 << 1; + *px++ = sum2 << 1; + *px2++ = sum3 << 1; + *px2++ = sum4 << 1; + + j += 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + (numColsA << 1U); + px = px2 + (numColsB & 1U); + px2 = px + numColsB; + + /* Decrement row loop counter */ + row--; + } + + /* Compute any remaining odd row/column below */ + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~1U); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcB->pData + numColsB-1; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px = sum1 << 1; + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + pInB = pSrcB->pData + i; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1 << 1; + i++; + + /* Decrement col loop counter */ + col--; + } + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c new file mode 100644 index 0000000..69e0142 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c @@ -0,0 +1,788 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_opt_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 3 Nov 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref arm_mat_mult_fast_q31() for a faster but less precise implementation of this function. + @remark + This function is a faster implementation of arm_mat_mult_q31 for MVE but it is requiring + additional storage for intermediate results. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q31x4_t vecB, vecA0, vecA1; + /* enable predication to disable half of vector elements */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM2); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM2; + + pInB = pSrcB->pData; + + /* load 1st B column (partial load) */ + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + /* load A rows */ + vecA0 = vldrwq_s32(pInA0); + vecA1 = vldrwq_s32(pInA1); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM3; + q31_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q31x4_t vecB, vecA; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM4; + q31_t *pInA2 = pInA1 + MATRIX_DIM4; + q31_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + vecColBOffs = vidupq_u32((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA2; + q31_t *pInB2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q31_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* Status of matrix multiplication */ + arm_matrix_instance_q31 BT; +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + q63_t sum = (q63_t) *pInA * *pInB; + pDst->pData[0] = (q31_t)(sum >> 31); + return (ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_opt_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_opt_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_opt_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + + /* + * Matrix transpose + */ + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q31(pSrcB, &BT); + + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * main loop + * compute 2 x 2 output blocks + * with dot products (Matrix A rows * Transposed MAtrix B rows) + */ + while (row > 0u) { + /* + * For every row wise process, the column loop counter is to be initiated + * Compute 2 columns and 2 rows in parrallel + */ + col = numColsB >> 1; + j = 0; + + /* + * column pair loop + */ + while (col > 0u) { + q31_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q31x4_t vecA, vecA2, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointers + * - 2 x consecutive Matrix A rows (i increment is 2 x numColsA) + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + + pSrcAVec = (q31_t const *) pInA; + pSrcA2Vec = (q31_t const *) pInA2; + pSrcBVec = (q31_t const *) pInB; + pSrcB2Vec = (q31_t const *) pInB2; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* load scheduling */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + acc3 = vrmlaldavhaq(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vrmlaldavhaq_p(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vrmlaldavhaq_p(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vrmlaldavhaq_p(acc3, vecA2, vecB2, p0); + } + + /* Convert to 1.31 */ + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + /* Store the results (2 x 2 block) in the destination buffer */ + *px++ = (q31_t) acc0; + *px++ = (q31_t) acc2; + *px2++ = (q31_t) acc1; + *px2++ = (q31_t) acc3; + + j += numRowsB * 2; + /* + * Decrement the column pair loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row pair loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + if (numColsB & 1u) { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) { + q31_t const *pSrcAVec, *pSrcBVec; + q31x4_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q31_t const *) pInA; + pSrcBVec = (q31_t const *) pInB; + + /* single dot-product */ + acc0 = 0LL; + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + } + + acc0 = asrl(acc0, 23); + *px = (q31_t) acc0; + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) { + q31_t const *pSrcAVec, *pSrcBVec; + q31x4_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q31_t const *) pInA; + pSrcBVec = (q31_t const *) pInB; + acc0 = 0LL; + + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + } + + acc0 = asrl(acc0, 23); + *px++ = (q31_t) acc0; + + i += numColsA; + /* + * Decrement the col loop counter + */ + col--; + } + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* + * Return to application + */ + return (status); +} + +#else +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + (void)pState; +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c new file mode 100644 index 0000000..026a993 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c @@ -0,0 +1,847 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q15.c + * Description: Q15 matrix multiplication + * + * $Date: 3 Nov 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits + and then saturated to 1.15 format. + @par + Refer to \ref arm_mat_mult_fast_q15() for a faster but less precise version of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_q15_2x2_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q15x8_t vecB, vecA0, vecA1; + mve_pred16_t p0 = vctp16q(MATRIX_DIM2); + + vecColBOffs = vidupq_u16((uint32_t)0, 2); /* MATRIX_DIM2 */ + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + pOut[0 * MATRIX_DIM2] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM2] = (q15_t) __SSAT(acc1, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + pOut[0 * MATRIX_DIM2] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM2] = (q15_t) __SSAT(acc1, 16); + + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_q15_3x3_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM3; + q15_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q15x8_t vecB, vecA0, vecA1, vecA2; + mve_pred16_t p0 = vctp16q(MATRIX_DIM3); + + vecColBOffs = vidupq_u16((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + vecA2 = vldrhq_s16(pInA2); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_mult_q15_4x4_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM4; + q15_t *pInA2 = pInA1 + MATRIX_DIM4; + q15_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q15x8_t vecB, vecA0, vecA1, vecA2, vecA3; + mve_pred16_t p0 = vctp16q(MATRIX_DIM4); + + vecColBOffs = vidupq_u16((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + vecA2 = vldrhq_s16(pInA2); + vecA3 = vldrhq_s16(pInA3); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA2; + q15_t *pInB2; + q15_t *px; /* Temporary output data matrix pointer */ + q15_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* Status of matrix multiplication */ + arm_matrix_instance_q15 BT; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* small squared matrix specialized routines */ + if (numRowsA == numColsB && numColsB == numColsA) { + + if (numRowsA == 1) { + q63_t sum; + sum = pInA[0] * pInB[0]; + pDst->pData[0] = (q15_t) __SSAT((sum >> 15), 16); + return (ARM_MATH_SUCCESS); + } else if (numRowsA == 2) + return arm_mat_mult_q15_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_mult_q15_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q15_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* + * Matrix transpose + */ + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q15(pSrcB, &BT); + + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + /* + * For every row wise process, the pIn2 pointer is set + * to the starting address of the transposed pSrcB data + */ + pInB = pSrcBT; + pInB2 = pInB + numRowsB; + j = 0; + + /* + * column loop + */ + while (col > 0u) { + q15_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q15x8_t vecA, vecA2, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + + pSrcAVec = (q15_t const *) pInA; + pSrcA2Vec = (q15_t const *) pInA2; + pSrcBVec = (q15_t const *) pInB; + pSrcB2Vec = (q15_t const *) pInB2; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + + blkCnt = numColsA / 8; + while (blkCnt > 0U) { + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc1 = vmlaldavaq(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 8; + acc2 = vmlaldavaq(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + acc3 = vmlaldavaq(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + */ + blkCnt = numColsA & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vmlaldavaq_p(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vmlaldavaq_p(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vmlaldavaq_p(acc3, vecA2, vecB2, p0); + } + + *px++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + *px2++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *px2++ = (q15_t) MVE_ASRL_SAT16(acc3, 15); + j += numRowsB * 2; + /* + * Decrement the column loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + + if (numColsB & 1u) { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) { + q15_t const *pSrcAVec, *pSrcBVec; + q15x8_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q15_t const *) pInA; + pSrcBVec = (q15_t const *) pInB; + + acc0 = 0LL; + blkCnt = (numColsA) / 8; + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + */ + blkCnt = (numColsA & 7); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + } + + *px = (q15_t) MVE_ASRL_SAT16(acc0, 15); + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) { + q15_t const *pSrcAVec, *pSrcBVec; + q15x8_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q15_t const *) pInA; + pSrcBVec = (q15_t const *) pInB; + acc0 = 0LL; + + blkCnt = ((numColsA) / 8); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + */ + blkCnt = (numColsA & 7); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + } + + *px++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + + i += numColsA; + + /* + * Decrement the col loop counter + */ + col--; + } + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q63_t sum; /* Accumulator */ + +#if defined (ARM_MATH_DSP) /* != CM0 */ + + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + q31_t inA1, inB1, inA2, inB2; + arm_matrix_instance_q15 BT; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q15(pSrcB,&BT); + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + + inA2 = read_q15x2_ia (&pInA); + inB2 = read_q15x2_ia (&pInB); + + /* Multiply and Accumulates */ + sum = __SMLALD(inA1, inB1, sum); + sum = __SMLALD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + /* process remaining column samples */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } + + /* Saturate and store result in destination buffer */ + *px = (q15_t) (__SSAT((sum >> 15), 16)); + px++; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q15_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + (void)pState; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pIn1 to point to starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform multiply-accumulates */ + sum += (q31_t) * pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 34.30 to 1.15 format and store saturated value in destination buffer */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) __SSAT((sum >> 15), 16); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pSrcA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c new file mode 100644 index 0000000..252eebf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c @@ -0,0 +1,765 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref arm_mat_mult_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q31x4_t vecB, vecA0, vecA1; + /* enable predication to disable half of vector elements */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM2); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM2; + + pInB = pSrcB->pData; + + /* load 1st B column (partial load) */ + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + /* load A rows */ + vecA0 = vldrwq_s32(pInA0); + vecA1 = vldrwq_s32(pInA1); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM3; + q31_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q31x4_t vecB, vecA; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_mult_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM4; + q31_t *pInA2 = pInA1 + MATRIX_DIM4; + q31_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + vecColBOffs = vidupq_u32((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = (q31_t const *)pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = (q31_t const *)pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + q63_t sum = (q63_t) *pInA * *pInB; + pOut[0] = (q31_t)(sum >> 31); + return (ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * (uint32_t) (numColsB); + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0U) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *)pSrcB->pData; + /* + * column loop + */ + while (col > 0U) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + numColsA; + q31_t const *pInA2 = pInA1 + numColsA; + q31_t const *pInA3 = pInA2 + numColsA; + q63_t acc0, acc1, acc2, acc3; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + pSrcA1Vec = (q31_t const *) pInA1; + pSrcA2Vec = (q31_t const *) pInA2; + pSrcA3Vec = (q31_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* process 1 x 4 block output */ + blkCnt = numColsA >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* move Matrix B read offsets, 4 rows down */ + vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vrmlaldavhaq(acc3, vecA, vecB); + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + //vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vrmlaldavhaq(acc3, vecA, vecB); + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + px[0] = (q31_t) acc0; + px[1 * numColsB] = (q31_t) acc1; + px[2 * numColsB] = (q31_t) acc2; + px[3 * numColsB] = (q31_t) acc3; + px++; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *)pSrcB->pData + (numColsB - col); + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4); + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + rowCnt = row & 3; + while (rowCnt > 0U) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *)pSrcB->pData; + /* + * column loop + */ + while (col > 0U) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec; + q31_t const *pInA0 = pInA; + q63_t acc0; + + acc0 = 0LL; + + + pSrcA0Vec = (q31_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* process 1 x 4 block output */ + blkCnt = numColsA >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* move Matrix B read offsets, 4 rows down */ + vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + //vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + } + + acc0 = asrl(acc0, 23); + + + px[0] = (q31_t) acc0; + px++; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *)pSrcB->pData + (numColsB - col); + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA; + /* + * Decrement the row loop counter + */ + rowCnt--; + } + + /* + * set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c new file mode 100644 index 0000000..e9541fa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c @@ -0,0 +1,682 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q7.c + * Description: Q15 matrix multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + * @brief Q7 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results (Unused in some versions) + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * Scaling and Overflow Behavior: + * + * \par + * The function is implemented using a 32-bit internal accumulator saturated to 1.7 format. + * + * + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_2x2_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint32_t MATRIX_DIM = 2; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q31_t acc0, acc1; + q7x16_t vecB, vecA0, vecA1; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 2); /* MATRIX_DIM */ + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_3x3_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint8_t MATRIX_DIM = 3; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q7_t *pInA2 = pInA1 + MATRIX_DIM; + q31_t acc0, acc1, acc2; + q7x16_t vecB, vecA0, vecA1, vecA2; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM; + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + vecA2 = vldrbq_s8(pInA2); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_4x4_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint32_t MATRIX_DIM = 4; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q7_t *pInA2 = pInA1 + MATRIX_DIM; + q7_t *pInA3 = pInA2 + MATRIX_DIM; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecB, vecA0, vecA1, vecA2, vecA3; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + vecA2 = vldrbq_s8(pInA2); + vecA3 = vldrbq_s8(pInA3); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_mult_q7( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst, + q7_t * pState) +{ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q7 type */ + q7_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q7 type */ + q7_t *pInA2; + q7_t *pInB2; + q7_t *px; /* Temporary output data matrix pointer */ + q7_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q7_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + arm_matrix_instance_q7 BT; + + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if(numRowsA == 2) + return arm_mat_mult_q7_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_q7_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q7_4x4_mve(pSrcA, pSrcB, pDst); + } + /* + * Matrix transpose + */ + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q7(pSrcB, &BT); + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) + { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + /* + * For every row wise process, the pIn2 pointer is set + * to the starting address of the transposed pSrcB data + */ + pInB = pSrcBT; + pInB2 = pInB + numRowsB; + j = 0; + + /* + * column loop + */ + while (col > 0u) + { + q7_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q7x16_t vecA, vecA2, vecB, vecB2; + q31_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + pSrcAVec = (q7_t const *) pInA; + pSrcA2Vec = (q7_t const *)pInA2; + pSrcBVec = (q7_t const *) pInB; + pSrcB2Vec = (q7_t const *)pInB2; + + acc0 = 0L; + acc1 = 0L; + acc2 = 0L; + acc3 = 0L; + + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + + blkCnt = numColsA >> 4; + while (blkCnt > 0U) + { + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 16; + acc1 = vmladavaq_s8(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 16; + acc2 = vmladavaq_s8(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + acc3 = vmladavaq_s8(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vmladavaq_p_s8(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vmladavaq_p_s8(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vmladavaq_p_s8(acc3, vecA2, vecB2, p0); + } + + *px++ = (q7_t) __SSAT(acc0 >> 7, 8); + *px++ = (q7_t) __SSAT(acc2 >> 7, 8); + *px2++ = (q7_t) __SSAT(acc1 >> 7, 8); + *px2++ = (q7_t) __SSAT(acc3 >> 7, 8); + j += numRowsB * 2; + /* + * Decrement the column loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + + if (numColsB & 1u) + { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) + { + q7_t const *pSrcAVec, *pSrcBVec; + q7x16_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q7_t const *) pInA; + pSrcBVec = (q7_t const *) pInB; + + acc0 = 0LL; + blkCnt = (numColsA) >> 4; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + } + + *px = (q7_t) __SSAT(acc0 >> 7, 8); + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) + { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) + { + q7_t const *pSrcAVec, *pSrcBVec; + q7x16_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q7_t const *) pInA; + pSrcBVec = (q7_t const *) pInB; + acc0 = 0LL; + + blkCnt = (numColsA) >> 4; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + } + + *px++ = (q7_t) __SSAT(acc0 >> 7, 8); + + i += numColsA; + + /* + * Decrement the col loop counter + */ + col--; + } + } + /* + * Return to application + */ + status = ARM_MATH_SUCCESS; + } + return(status); +} +#else +arm_status arm_mat_mult_q7(const arm_matrix_instance_q7 *pSrcA, const arm_matrix_instance_q7 *pSrcB, arm_matrix_instance_q7 *pDst, q7_t *pState) +{ + q31_t sum; /* accumulator */ + q7_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q7 type */ + q7_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q7 type */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + q7_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t col, i = 0U, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + + (void)pState; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate the pointer pIn1 to point to the starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */ + /* Perform the multiply-accumulates */ + sum += (q31_t)*pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */ + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)__SSAT((sum >> 7), 8); + + /* Decrement the column loop counter */ + col--; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update the pointer pSrcA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f16.c new file mode 100644 index 0000000..1e04295 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f16.c @@ -0,0 +1,784 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_qr_f16.c + * Description: Half floating-point matrix QR decomposition. + * + * $Date: 15 June 2022 + * $Revision: V1.11.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + + +#if !defined(ARM_MATH_AUTOVECTORIZE) +#if defined(ARM_MATH_MVE_FLOAT16) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#endif +#endif + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixQR + @{ + */ + +/** + @brief QR decomposition of a m x n half floating point matrix with m >= n. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[in] threshold norm2 threshold. + @param[out] pOutR points to output R matrix structure of dimension m x n + @param[out] pOutQ points to output Q matrix structure of dimension m x m (can be NULL) + @param[out] pOutTau points to Householder scaling factors of dimension n + @param[inout] pTmpA points to a temporary vector of dimension m. + @param[inout] pTmpB points to a temporary vector of dimension m. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par pOutQ is optional: + pOutQ can be a NULL pointer. + In this case, the argument will be ignored + and the output Q matrix won't be computed. + + @par f16 implementation + The f16 implementation is not very accurate. + + @par Norm2 threshold + For the meaning of this argument please + refer to the \ref MatrixHouseholder documentation + + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) +#if defined(ARM_MATH_MVE_FLOAT16) + +arm_status arm_mat_qr_f16( + const arm_matrix_instance_f16 * pSrc, + const float16_t threshold, + arm_matrix_instance_f16 * pOutR, + arm_matrix_instance_f16 * pOutQ, + float16_t * pOutTau, + float16_t *pTmpA, + float16_t *pTmpB + ) + +{ + int32_t col=0; + int32_t nb,pos; + float16_t *pa,*pc; + float16_t beta; + float16_t *pv; + float16_t *pdst; + float16_t *p; + + if (pSrc->numRows < pSrc->numCols) + { + return(ARM_MATH_SIZE_MISMATCH); + } + + memcpy(pOutR->pData,pSrc->pData,pSrc->numCols * pSrc->numRows*sizeof(float16_t)); + pOutR->numCols = pSrc->numCols; + pOutR->numRows = pSrc->numRows; + + p = pOutR->pData; + + pc = pOutTau; + for(col=0 ; col < pSrc->numCols; col++) + { + int32_t j,k,blkCnt,blkCnt2; + float16_t *pa0,*pa1,*pa2,*pa3,*ptemp; + float16_t temp; + float16x8_t v1,v2,vtemp; + + COPY_COL_F16(pOutR,col,col,pTmpA); + + beta = arm_householder_f16(pTmpA,threshold,pSrc->numRows - col,pTmpA); + *pc++ = beta; + + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + pv = pTmpA; + pa = p; + + temp = *pv; + blkCnt = (pSrc->numCols-col) >> 3; + while (blkCnt > 0) + { + v1 = vld1q_f16(pa); + v2 = vmulq_n_f16(v1,temp); + vst1q_f16(pdst,v2); + + pa += 8; + pdst += 8; + blkCnt--; + } + blkCnt = (pSrc->numCols-col) & 7; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt); + v1 = vld1q_f16(pa); + v2 = vmulq_n_f16(v1,temp); + vst1q_p_f16(pdst,v2,p0); + + pa += blkCnt; + } + + pa += col; + pv++; + pdst = pTmpB; + + pa0 = pa; + pa1 = pa0 + pSrc->numCols; + pa2 = pa1 + pSrc->numCols; + pa3 = pa2 + pSrc->numCols; + + /* Unrolled loop */ + blkCnt = (pSrc->numRows-col - 1) >> 2; + k=1; + while(blkCnt > 0) + { + vtemp=vld1q_f16(pv); + + blkCnt2 = (pSrc->numCols-col) >> 3; + while (blkCnt2 > 0) + { + v1 = vld1q_f16(pdst); + + v2 = vld1q_f16(pa0); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,0)); + + v2 = vld1q_f16(pa1); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,1)); + + v2 = vld1q_f16(pa2); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,2)); + + v2 = vld1q_f16(pa3); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,3)); + + vst1q_f16(pdst,v1); + + pdst += 8; + pa0 += 8; + pa1 += 8; + pa2 += 8; + pa3 += 8; + blkCnt2--; + } + blkCnt2 = (pSrc->numCols-col) & 7; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt2); + + v1 = vld1q_f16(pdst); + + v2 = vld1q_f16(pa0); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,0)); + + v2 = vld1q_f16(pa1); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,1)); + + v2 = vld1q_f16(pa2); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,2)); + + v2 = vld1q_f16(pa3); + v1 = vfmaq_n_f16(v1,v2,vgetq_lane(vtemp,3)); + + vst1q_p_f16(pdst,v1,p0); + + pa0 += blkCnt2; + pa1 += blkCnt2; + pa2 += blkCnt2; + pa3 += blkCnt2; + } + + pa0 += col + 3*pSrc->numCols; + pa1 += col + 3*pSrc->numCols; + pa2 += col + 3*pSrc->numCols; + pa3 += col + 3*pSrc->numCols; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-col; k++) + { + temp = *pv; + blkCnt2 = (pSrc->numCols-col) >> 3; + while (blkCnt2 > 0) + { + v1 = vld1q_f16(pa); + v2 = vld1q_f16(pdst); + v2 = vfmaq_n_f16(v2,v1,temp); + vst1q_f16(pdst,v2); + + pa += 8; + pdst += 8; + blkCnt2--; + } + blkCnt2 = (pSrc->numCols-col) & 7; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt2); + v1 = vld1q_f16(pa); + v2 = vld1q_f16(pdst); + v2 = vfmaq_n_f16(v2,v1,temp); + vst1q_p_f16(pdst,v2,p0); + + pa += blkCnt2; + } + + pa += col; + pv++; + pdst = pTmpB; + } + + /* A(col:,col:) - beta v tmpb */ + pa = p; + for(j=0;jnumRows-col; j++) + { + float16_t f = -(_Float16)beta * (_Float16)pTmpA[j]; + ptemp = pTmpB; + + blkCnt2 = (pSrc->numCols-col) >> 3; + while (blkCnt2 > 0) + { + v1 = vld1q_f16(pa); + v2 = vld1q_f16(ptemp); + v1 = vfmaq_n_f16(v1,v2,f); + vst1q_f16(pa,v1); + + pa += 8; + ptemp += 8; + + blkCnt2--; + } + blkCnt2 = (pSrc->numCols-col) & 7; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt2); + + v1 = vld1q_f16(pa); + v2 = vld1q_f16(ptemp); + v1 = vfmaq_n_f16(v1,v2,f); + vst1q_p_f16(pa,v1,p0); + + pa += blkCnt2; + } + + pa += col; + } + + /* Copy Householder reflectors into R matrix */ + pa = p + pOutR->numCols; + for(k=0;knumRows-col-1; k++) + { + *pa = pTmpA[k+1]; + pa += pOutR->numCols; + } + + p += 1 + pOutR->numCols; + } + + /* Generate Q if requested by user matrix */ + + if (pOutQ != NULL) + { + /* Initialize Q matrix to identity */ + memset(pOutQ->pData,0,sizeof(float16_t)*pOutQ->numRows*pOutQ->numRows); + + pa = pOutQ->pData; + for(col=0 ; col < pOutQ->numCols; col++) + { + *pa = 1.0f16; + pa += pOutQ->numCols+1; + } + + nb = pOutQ->numRows - pOutQ->numCols + 1; + + pc = pOutTau + pOutQ->numCols - 1; + for(col=0 ; col < pOutQ->numCols; col++) + { + int32_t j,k, blkCnt, blkCnt2; + float16_t *pa0,*pa1,*pa2,*pa3,*ptemp; + float16_t temp; + float16x8_t v1,v2,vtemp; + + pos = pSrc->numRows - nb; + p = pOutQ->pData + pos + pOutQ->numCols*pos ; + + + COPY_COL_F16(pOutR,pos,pos,pTmpA); + pTmpA[0] = 1.0f16; + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + + pv = pTmpA; + pa = p; + + temp = *pv; + blkCnt2 = (pOutQ->numRows-pos) >> 3; + while (blkCnt2 > 0) + { + v1 = vld1q_f16(pa); + v1 = vmulq_n_f16(v1, temp); + vst1q_f16(pdst,v1); + + pa += 8; + pdst += 8; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numRows-pos) & 7; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt2); + + v1 = vld1q_f16(pa); + v1 = vmulq_n_f16(v1, temp); + vst1q_p_f16(pdst,v1,p0); + + pa += blkCnt2; + } + + pa += pos; + pv++; + pdst = pTmpB; + pa0 = pa; + pa1 = pa0 + pOutQ->numRows; + pa2 = pa1 + pOutQ->numRows; + pa3 = pa2 + pOutQ->numRows; + + /* Unrolled loop */ + blkCnt = (pOutQ->numRows-pos - 1) >> 2; + k=1; + while(blkCnt > 0) + { + + vtemp = vld1q_f16(pv); + blkCnt2 = (pOutQ->numRows-pos) >> 3; + while (blkCnt2 > 0) + { + v1 = vld1q_f16(pdst); + + v2 = vld1q_f16(pa0); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,0)); + + v2 = vld1q_f16(pa1); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,1)); + + v2 = vld1q_f16(pa2); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,2)); + + v2 = vld1q_f16(pa3); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,3)); + + vst1q_f16(pdst,v1); + + pa0 += 8; + pa1 += 8; + pa2 += 8; + pa3 += 8; + pdst += 8; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numRows-pos) & 7; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt2); + + v1 = vld1q_f16(pdst); + + v2 = vld1q_f16(pa0); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,0)); + + v2 = vld1q_f16(pa1); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,1)); + + v2 = vld1q_f16(pa2); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,2)); + + v2 = vld1q_f16(pa3); + v1 = vfmaq_n_f16(v1, v2, vgetq_lane(vtemp,3)); + + vst1q_p_f16(pdst,v1,p0); + + pa0 += blkCnt2; + pa1 += blkCnt2; + pa2 += blkCnt2; + pa3 += blkCnt2; + + } + + pa0 += pos + 3*pOutQ->numRows; + pa1 += pos + 3*pOutQ->numRows; + pa2 += pos + 3*pOutQ->numRows; + pa3 += pos + 3*pOutQ->numRows; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-pos; k++) + { + temp = *pv; + blkCnt2 = (pOutQ->numRows-pos) >> 3; + while (blkCnt2 > 0) + { + v1 = vld1q_f16(pdst); + v2 = vld1q_f16(pa); + v1 = vfmaq_n_f16(v1, v2, temp); + vst1q_f16(pdst,v1); + + pdst += 8; + pa += 8; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numRows-pos) & 7; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt2); + v1 = vld1q_f16(pdst); + v2 = vld1q_f16(pa); + v1 = vfmaq_n_f16(v1, v2, temp); + vst1q_p_f16(pdst,v1,p0); + + pa += blkCnt2; + } + + pa += pos; + pv++; + pdst = pTmpB; + } + + pa = p; + beta = *pc--; + for(j=0;jnumRows-pos; j++) + { + float16_t f = -(_Float16)beta * (_Float16)pTmpA[j]; + ptemp = pTmpB; + + blkCnt2 = (pOutQ->numCols-pos) >> 3; + while (blkCnt2 > 0) + { + v1 = vld1q_f16(pa); + v2 = vld1q_f16(ptemp); + v1 = vfmaq_n_f16(v1,v2,f); + vst1q_f16(pa,v1); + + pa += 8; + ptemp += 8; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numCols-pos) & 7; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt2); + + v1 = vld1q_f16(pa); + v2 = vld1q_f16(ptemp); + v1 = vfmaq_n_f16(v1,v2,f); + vst1q_p_f16(pa,v1,p0); + + pa += blkCnt2; + } + + pa += pos; + } + + + nb++; + } + } + + arm_status status = ARM_MATH_SUCCESS; + /* Return to application */ + return (status); +} + +#endif /*#if !defined(ARM_MATH_MVEF)*/ + + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (!defined(ARM_MATH_MVE_FLOAT16)) || defined(ARM_MATH_AUTOVECTORIZE) + + +arm_status arm_mat_qr_f16( + const arm_matrix_instance_f16 * pSrc, + const float16_t threshold, + arm_matrix_instance_f16 * pOutR, + arm_matrix_instance_f16 * pOutQ, + float16_t * pOutTau, + float16_t *pTmpA, + float16_t *pTmpB + ) + +{ + int32_t col=0; + int32_t nb,pos; + float16_t *pa,*pc; + float16_t beta; + float16_t *pv; + float16_t *pdst; + float16_t *p; + + if (pSrc->numRows < pSrc->numCols) + { + return(ARM_MATH_SIZE_MISMATCH); + } + + memcpy(pOutR->pData,pSrc->pData,pSrc->numCols * pSrc->numRows*sizeof(float16_t)); + pOutR->numCols = pSrc->numCols; + pOutR->numRows = pSrc->numRows; + + p = pOutR->pData; + + pc = pOutTau; + for(col=0 ; col < pSrc->numCols; col++) + { + int32_t i,j,k,blkCnt; + float16_t *pa0,*pa1,*pa2,*pa3; + COPY_COL_F16(pOutR,col,col,pTmpA); + + beta = arm_householder_f16(pTmpA,threshold,pSrc->numRows - col,pTmpA); + *pc++ = beta; + + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + pv = pTmpA; + pa = p; + for(j=0;jnumCols-col; j++) + { + *pdst++ = (_Float16)*pv * (_Float16)*pa++; + } + pa += col; + pv++; + pdst = pTmpB; + + pa0 = pa; + pa1 = pa0 + pSrc->numCols; + pa2 = pa1 + pSrc->numCols; + pa3 = pa2 + pSrc->numCols; + + /* Unrolled loop */ + blkCnt = (pSrc->numRows-col - 1) >> 2; + k=1; + while(blkCnt > 0) + { + float16_t sum; + + for(j=0;jnumCols-col; j++) + { + sum = *pdst; + + sum += (_Float16)pv[0] * (_Float16)*pa0++; + sum += (_Float16)pv[1] * (_Float16)*pa1++; + sum += (_Float16)pv[2] * (_Float16)*pa2++; + sum += (_Float16)pv[3] * (_Float16)*pa3++; + + *pdst++ = sum; + } + pa0 += col + 3*pSrc->numCols; + pa1 += col + 3*pSrc->numCols; + pa2 += col + 3*pSrc->numCols; + pa3 += col + 3*pSrc->numCols; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-col; k++) + { + for(j=0;jnumCols-col; j++) + { + *pdst++ += (_Float16)*pv * (_Float16)*pa++; + } + pa += col; + pv++; + pdst = pTmpB; + } + + /* A(col:,col:) - beta v tmpb */ + pa = p; + for(j=0;jnumRows-col; j++) + { + float16_t f = (_Float16)beta * (_Float16)pTmpA[j]; + + for(i=0;inumCols-col; i++) + { + *pa = (_Float16)*pa - (_Float16)f * (_Float16)pTmpB[i] ; + pa++; + } + pa += col; + } + + /* Copy Householder reflectors into R matrix */ + pa = p + pOutR->numCols; + for(k=0;knumRows-col-1; k++) + { + *pa = pTmpA[k+1]; + pa += pOutR->numCols; + } + + p += 1 + pOutR->numCols; + } + + /* Generate Q if requested by user matrix */ + + if (pOutQ != NULL) + { + /* Initialize Q matrix to identity */ + memset(pOutQ->pData,0,sizeof(float16_t)*pOutQ->numRows*pOutQ->numRows); + + pa = pOutQ->pData; + for(col=0 ; col < pOutQ->numCols; col++) + { + *pa = 1.0f16; + pa += pOutQ->numCols+1; + } + + nb = pOutQ->numRows - pOutQ->numCols + 1; + + pc = pOutTau + pOutQ->numCols - 1; + for(col=0 ; col < pOutQ->numCols; col++) + { + int32_t i,j,k, blkCnt; + float16_t *pa0,*pa1,*pa2,*pa3; + pos = pSrc->numRows - nb; + p = pOutQ->pData + pos + pOutQ->numCols*pos ; + + + COPY_COL_F16(pOutR,pos,pos,pTmpA); + pTmpA[0] = 1.0f16; + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + + pv = pTmpA; + pa = p; + for(j=0;jnumRows-pos; j++) + { + *pdst++ = (_Float16)*pv * (_Float16)*pa++; + } + pa += pos; + pv++; + pdst = pTmpB; + pa0 = pa; + pa1 = pa0 + pOutQ->numRows; + pa2 = pa1 + pOutQ->numRows; + pa3 = pa2 + pOutQ->numRows; + + /* Unrolled loop */ + blkCnt = (pOutQ->numRows-pos - 1) >> 2; + k=1; + while(blkCnt > 0) + { + float16_t sum; + + for(j=0;jnumRows-pos; j++) + { + sum = *pdst; + + sum += (_Float16)pv[0] * (_Float16)*pa0++; + sum += (_Float16)pv[1] * (_Float16)*pa1++; + sum += (_Float16)pv[2] * (_Float16)*pa2++; + sum += (_Float16)pv[3] * (_Float16)*pa3++; + + *pdst++ = sum; + } + pa0 += pos + 3*pOutQ->numRows; + pa1 += pos + 3*pOutQ->numRows; + pa2 += pos + 3*pOutQ->numRows; + pa3 += pos + 3*pOutQ->numRows; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-pos; k++) + { + for(j=0;jnumRows-pos; j++) + { + *pdst++ += (_Float16)*pv * (_Float16)*pa++; + } + pa += pos; + pv++; + pdst = pTmpB; + } + + pa = p; + beta = *pc--; + for(j=0;jnumRows-pos; j++) + { + float16_t f = (_Float16)beta * (_Float16)pTmpA[j]; + + for(i=0;inumCols-pos; i++) + { + *pa = (_Float16)*pa - (_Float16)f * (_Float16)pTmpB[i] ; + pa++; + } + pa += pos; + } + + + nb++; + } + } + + arm_status status = ARM_MATH_SUCCESS; + /* Return to application */ + return (status); +} + +#endif /* end of test for Helium or Neon availability */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MatrixQR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f32.c new file mode 100644 index 0000000..3e3027e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f32.c @@ -0,0 +1,854 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_qr_f32.c + * Description: Floating-point matrix QR decomposition. + * + * $Date: 15 June 2022 + * $Revision: V1.11.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + + +#if !defined(ARM_MATH_AUTOVECTORIZE) +#if defined(ARM_MATH_MVEF) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#endif +#endif + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixQR QR decomposition of a Matrix + + Computes the QR decomposition of a matrix M using Householder algorithm. + + \f[ + M = Q R + \f] + + where Q is an orthogonal matrix and R is upper triangular. + No pivoting strategy is used. + + The returned value for R is using a format a bit similar + to LAPACK : it is not just containing the matrix R but + also the Householder reflectors. + + The function is also returning a vector \f$\tau\f$ + that is containing the scaling factor for the reflectors. + + Returned value R has the structure: + + \f[ + \begin{pmatrix} + r_{11} & r_{12} & \dots & r_{1n} \\ + v_{12} & r_{22} & \dots & r_{2n} \\ + v_{13} & v_{22} & \dots & r_{3n} \\ + \vdots & \vdots & \ddots & \vdots \\ + v_{1m} & v_{2(m-1)} & \dots & r_{mn} \\ + \end{pmatrix} + \f] + + where + + \f[ + v_1 = + \begin{pmatrix} + 1 \\ + v_{12} \\ + \vdots \\ + v_{1m} \\ + \end{pmatrix} + \f] + + is the first householder reflector. + + The Householder Matrix is given by \f$H_1\f$ + + \f[ + H_1 = I - \tau_1 v_1 v_1^T + \f] + + The Matrix Q is the product of the Householder matrices: + + \f[ + Q = H_1 H_2 \dots H_n + \f] + + The computation of the matrix Q by this function is + optional. + + And the matrix R, would be the returned value R without the + householder reflectors: + + \f[ + \begin{pmatrix} + r_{11} & r_{12} & \dots & r_{1n} \\ + 0 & r_{22} & \dots & r_{2n} \\ + 0 & 0 & \dots & r_{3n} \\ + \vdots & \vdots & \ddots & \vdots \\ + 0 & 0 & \dots & r_{mn} \\ + \end{pmatrix} + \f] + + + */ + +/** + @addtogroup MatrixQR + @{ + */ + +/** + @brief QR decomposition of a m x n floating point matrix with m >= n. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[in] threshold norm2 threshold. + @param[out] pOutR points to output R matrix structure of dimension m x n + @param[out] pOutQ points to output Q matrix structure of dimension m x m (can be NULL) + @param[out] pOutTau points to Householder scaling factors of dimension n + @param[inout] pTmpA points to a temporary vector of dimension m. + @param[inout] pTmpB points to a temporary vector of dimension m. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par pOutQ is optional: + pOutQ can be a NULL pointer. + In this case, the argument will be ignored + and the output Q matrix won't be computed. + + + @par Norm2 threshold + For the meaning of this argument please + refer to the \ref MatrixHouseholder documentation + + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) +#if defined(ARM_MATH_MVEF) + +arm_status arm_mat_qr_f32( + const arm_matrix_instance_f32 * pSrc, + const float32_t threshold, + arm_matrix_instance_f32 * pOutR, + arm_matrix_instance_f32 * pOutQ, + float32_t * pOutTau, + float32_t *pTmpA, + float32_t *pTmpB + ) + +{ + int32_t col=0; + int32_t nb,pos; + float32_t *pa,*pc; + float32_t beta; + float32_t *pv; + float32_t *pdst; + float32_t *p; + + if (pSrc->numRows < pSrc->numCols) + { + return(ARM_MATH_SIZE_MISMATCH); + } + + memcpy(pOutR->pData,pSrc->pData,pSrc->numCols * pSrc->numRows*sizeof(float32_t)); + pOutR->numCols = pSrc->numCols; + pOutR->numRows = pSrc->numRows; + + p = pOutR->pData; + + pc = pOutTau; + for(col=0 ; col < pSrc->numCols; col++) + { + int32_t j,k,blkCnt,blkCnt2; + float32_t *pa0,*pa1,*pa2,*pa3,*ptemp; + float32_t temp; + float32x4_t v1,v2,vtemp; + + COPY_COL_F32(pOutR,col,col,pTmpA); + + beta = arm_householder_f32(pTmpA,threshold,pSrc->numRows - col,pTmpA); + *pc++ = beta; + + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + pv = pTmpA; + pa = p; + + temp = *pv; + blkCnt = (pSrc->numCols-col) >> 2; + while (blkCnt > 0) + { + v1 = vld1q_f32(pa); + v2 = vmulq_n_f32(v1,temp); + vst1q_f32(pdst,v2); + + pa += 4; + pdst += 4; + blkCnt--; + } + blkCnt = (pSrc->numCols-col) & 3; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt); + v1 = vld1q_f32(pa); + v2 = vmulq_n_f32(v1,temp); + vst1q_p_f32(pdst,v2,p0); + + pa += blkCnt; + } + + pa += col; + pv++; + pdst = pTmpB; + + pa0 = pa; + pa1 = pa0 + pSrc->numCols; + pa2 = pa1 + pSrc->numCols; + pa3 = pa2 + pSrc->numCols; + + /* Unrolled loop */ + blkCnt = (pSrc->numRows-col - 1) >> 2; + k=1; + while(blkCnt > 0) + { + vtemp=vld1q_f32(pv); + + blkCnt2 = (pSrc->numCols-col) >> 2; + while (blkCnt2 > 0) + { + v1 = vld1q_f32(pdst); + + v2 = vld1q_f32(pa0); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,0)); + + v2 = vld1q_f32(pa1); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,1)); + + v2 = vld1q_f32(pa2); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,2)); + + v2 = vld1q_f32(pa3); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,3)); + + vst1q_f32(pdst,v1); + + pdst += 4; + pa0 += 4; + pa1 += 4; + pa2 += 4; + pa3 += 4; + blkCnt2--; + } + blkCnt2 = (pSrc->numCols-col) & 3; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt2); + + v1 = vld1q_f32(pdst); + + v2 = vld1q_f32(pa0); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,0)); + + v2 = vld1q_f32(pa1); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,1)); + + v2 = vld1q_f32(pa2); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,2)); + + v2 = vld1q_f32(pa3); + v1 = vfmaq_n_f32(v1,v2,vgetq_lane(vtemp,3)); + + vst1q_p_f32(pdst,v1,p0); + + pa0 += blkCnt2; + pa1 += blkCnt2; + pa2 += blkCnt2; + pa3 += blkCnt2; + } + + pa0 += col + 3*pSrc->numCols; + pa1 += col + 3*pSrc->numCols; + pa2 += col + 3*pSrc->numCols; + pa3 += col + 3*pSrc->numCols; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-col; k++) + { + temp = *pv; + blkCnt2 = (pSrc->numCols-col) >> 2; + while (blkCnt2 > 0) + { + v1 = vld1q_f32(pa); + v2 = vld1q_f32(pdst); + v2 = vfmaq_n_f32(v2,v1,temp); + vst1q_f32(pdst,v2); + + pa += 4; + pdst += 4; + blkCnt2--; + } + blkCnt2 = (pSrc->numCols-col) & 3; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt2); + v1 = vld1q_f32(pa); + v2 = vld1q_f32(pdst); + v2 = vfmaq_n_f32(v2,v1,temp); + vst1q_p_f32(pdst,v2,p0); + + pa += blkCnt2; + } + + pa += col; + pv++; + pdst = pTmpB; + } + + /* A(col:,col:) - beta v tmpb */ + pa = p; + for(j=0;jnumRows-col; j++) + { + float32_t f = -beta * pTmpA[j]; + ptemp = pTmpB; + + blkCnt2 = (pSrc->numCols-col) >> 2; + while (blkCnt2 > 0) + { + v1 = vld1q_f32(pa); + v2 = vld1q_f32(ptemp); + v1 = vfmaq_n_f32(v1,v2,f); + vst1q_f32(pa,v1); + + pa += 4; + ptemp += 4; + + blkCnt2--; + } + blkCnt2 = (pSrc->numCols-col) & 3; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt2); + + v1 = vld1q_f32(pa); + v2 = vld1q_f32(ptemp); + v1 = vfmaq_n_f32(v1,v2,f); + vst1q_p_f32(pa,v1,p0); + + pa += blkCnt2; + } + + pa += col; + } + + /* Copy Householder reflectors into R matrix */ + pa = p + pOutR->numCols; + for(k=0;knumRows-col-1; k++) + { + *pa = pTmpA[k+1]; + pa += pOutR->numCols; + } + + p += 1 + pOutR->numCols; + } + + /* Generate Q if requested by user matrix */ + + if (pOutQ != NULL) + { + /* Initialize Q matrix to identity */ + memset(pOutQ->pData,0,sizeof(float32_t)*pOutQ->numRows*pOutQ->numRows); + + pa = pOutQ->pData; + for(col=0 ; col < pOutQ->numCols; col++) + { + *pa = 1.0f; + pa += pOutQ->numCols+1; + } + + nb = pOutQ->numRows - pOutQ->numCols + 1; + + pc = pOutTau + pOutQ->numCols - 1; + for(col=0 ; col < pOutQ->numCols; col++) + { + int32_t j,k, blkCnt, blkCnt2; + float32_t *pa0,*pa1,*pa2,*pa3,*ptemp; + float32_t temp; + float32x4_t v1,v2,vtemp; + + pos = pSrc->numRows - nb; + p = pOutQ->pData + pos + pOutQ->numCols*pos ; + + + COPY_COL_F32(pOutR,pos,pos,pTmpA); + pTmpA[0] = 1.0f; + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + + pv = pTmpA; + pa = p; + + temp = *pv; + blkCnt2 = (pOutQ->numRows-pos) >> 2; + while (blkCnt2 > 0) + { + v1 = vld1q_f32(pa); + v1 = vmulq_n_f32(v1, temp); + vst1q_f32(pdst,v1); + + pa += 4; + pdst += 4; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numRows-pos) & 3; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt2); + + v1 = vld1q_f32(pa); + v1 = vmulq_n_f32(v1, temp); + vst1q_p_f32(pdst,v1,p0); + + pa += blkCnt2; + } + + pa += pos; + pv++; + pdst = pTmpB; + pa0 = pa; + pa1 = pa0 + pOutQ->numRows; + pa2 = pa1 + pOutQ->numRows; + pa3 = pa2 + pOutQ->numRows; + + /* Unrolled loop */ + blkCnt = (pOutQ->numRows-pos - 1) >> 2; + k=1; + while(blkCnt > 0) + { + + vtemp = vld1q_f32(pv); + blkCnt2 = (pOutQ->numRows-pos) >> 2; + while (blkCnt2 > 0) + { + v1 = vld1q_f32(pdst); + + v2 = vld1q_f32(pa0); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,0)); + + v2 = vld1q_f32(pa1); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,1)); + + v2 = vld1q_f32(pa2); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,2)); + + v2 = vld1q_f32(pa3); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,3)); + + vst1q_f32(pdst,v1); + + pa0 += 4; + pa1 += 4; + pa2 += 4; + pa3 += 4; + pdst += 4; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numRows-pos) & 3; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt2); + + v1 = vld1q_f32(pdst); + + v2 = vld1q_f32(pa0); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,0)); + + v2 = vld1q_f32(pa1); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,1)); + + v2 = vld1q_f32(pa2); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,2)); + + v2 = vld1q_f32(pa3); + v1 = vfmaq_n_f32(v1, v2, vgetq_lane(vtemp,3)); + + vst1q_p_f32(pdst,v1,p0); + + pa0 += blkCnt2; + pa1 += blkCnt2; + pa2 += blkCnt2; + pa3 += blkCnt2; + + } + + pa0 += pos + 3*pOutQ->numRows; + pa1 += pos + 3*pOutQ->numRows; + pa2 += pos + 3*pOutQ->numRows; + pa3 += pos + 3*pOutQ->numRows; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-pos; k++) + { + temp = *pv; + blkCnt2 = (pOutQ->numRows-pos) >> 2; + while (blkCnt2 > 0) + { + v1 = vld1q_f32(pdst); + v2 = vld1q_f32(pa); + v1 = vfmaq_n_f32(v1, v2, temp); + vst1q_f32(pdst,v1); + + pdst += 4; + pa += 4; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numRows-pos) & 3; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt2); + v1 = vld1q_f32(pdst); + v2 = vld1q_f32(pa); + v1 = vfmaq_n_f32(v1, v2, temp); + vst1q_p_f32(pdst,v1,p0); + + pa += blkCnt2; + } + + pa += pos; + pv++; + pdst = pTmpB; + } + + pa = p; + beta = *pc--; + for(j=0;jnumRows-pos; j++) + { + float32_t f = -beta * pTmpA[j]; + ptemp = pTmpB; + + blkCnt2 = (pOutQ->numCols-pos) >> 2; + while (blkCnt2 > 0) + { + v1 = vld1q_f32(pa); + v2 = vld1q_f32(ptemp); + v1 = vfmaq_n_f32(v1,v2,f); + vst1q_f32(pa,v1); + + pa += 4; + ptemp += 4; + + blkCnt2--; + } + blkCnt2 = (pOutQ->numCols-pos) & 3; + if (blkCnt2 > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt2); + + v1 = vld1q_f32(pa); + v2 = vld1q_f32(ptemp); + v1 = vfmaq_n_f32(v1,v2,f); + vst1q_p_f32(pa,v1,p0); + + pa += blkCnt2; + } + + pa += pos; + } + + + nb++; + } + } + + arm_status status = ARM_MATH_SUCCESS; + /* Return to application */ + return (status); +} + +#endif /*#if !defined(ARM_MATH_MVEF)*/ + + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + + +#if (!defined(ARM_MATH_MVEF)) || defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_qr_f32( + const arm_matrix_instance_f32 * pSrc, + const float32_t threshold, + arm_matrix_instance_f32 * pOutR, + arm_matrix_instance_f32 * pOutQ, + float32_t * pOutTau, + float32_t *pTmpA, + float32_t *pTmpB + ) + +{ + int32_t col=0; + int32_t nb,pos; + float32_t *pa,*pc; + float32_t beta; + float32_t *pv; + float32_t *pdst; + float32_t *p; + + if (pSrc->numRows < pSrc->numCols) + { + return(ARM_MATH_SIZE_MISMATCH); + } + + memcpy(pOutR->pData,pSrc->pData,pSrc->numCols * pSrc->numRows*sizeof(float32_t)); + pOutR->numCols = pSrc->numCols; + pOutR->numRows = pSrc->numRows; + + p = pOutR->pData; + + pc = pOutTau; + for(col=0 ; col < pSrc->numCols; col++) + { + int32_t i,j,k,blkCnt; + float32_t *pa0,*pa1,*pa2,*pa3; + COPY_COL_F32(pOutR,col,col,pTmpA); + + beta = arm_householder_f32(pTmpA,threshold,pSrc->numRows - col,pTmpA); + *pc++ = beta; + + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + pv = pTmpA; + pa = p; + for(j=0;jnumCols-col; j++) + { + *pdst++ = *pv * *pa++; + } + pa += col; + pv++; + pdst = pTmpB; + + pa0 = pa; + pa1 = pa0 + pSrc->numCols; + pa2 = pa1 + pSrc->numCols; + pa3 = pa2 + pSrc->numCols; + + /* Unrolled loop */ + blkCnt = (pSrc->numRows-col - 1) >> 2; + k=1; + while(blkCnt > 0) + { + float32_t sum; + + for(j=0;jnumCols-col; j++) + { + sum = *pdst; + + sum += pv[0] * *pa0++; + sum += pv[1] * *pa1++; + sum += pv[2] * *pa2++; + sum += pv[3] * *pa3++; + + *pdst++ = sum; + } + pa0 += col + 3*pSrc->numCols; + pa1 += col + 3*pSrc->numCols; + pa2 += col + 3*pSrc->numCols; + pa3 += col + 3*pSrc->numCols; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-col; k++) + { + for(j=0;jnumCols-col; j++) + { + *pdst++ += *pv * *pa++; + } + pa += col; + pv++; + pdst = pTmpB; + } + + /* A(col:,col:) - beta v tmpb */ + pa = p; + for(j=0;jnumRows-col; j++) + { + float32_t f = beta * pTmpA[j]; + + for(i=0;inumCols-col; i++) + { + *pa = *pa - f * pTmpB[i] ; + pa++; + } + pa += col; + } + + /* Copy Householder reflectors into R matrix */ + pa = p + pOutR->numCols; + for(k=0;knumRows-col-1; k++) + { + *pa = pTmpA[k+1]; + pa += pOutR->numCols; + } + + p += 1 + pOutR->numCols; + } + + /* Generate Q if requested by user matrix */ + + if (pOutQ != NULL) + { + /* Initialize Q matrix to identity */ + memset(pOutQ->pData,0,sizeof(float32_t)*pOutQ->numRows*pOutQ->numRows); + + pa = pOutQ->pData; + for(col=0 ; col < pOutQ->numCols; col++) + { + *pa = 1.0f; + pa += pOutQ->numCols+1; + } + + nb = pOutQ->numRows - pOutQ->numCols + 1; + + pc = pOutTau + pOutQ->numCols - 1; + for(col=0 ; col < pOutQ->numCols; col++) + { + int32_t i,j,k, blkCnt; + float32_t *pa0,*pa1,*pa2,*pa3; + pos = pSrc->numRows - nb; + p = pOutQ->pData + pos + pOutQ->numCols*pos ; + + + COPY_COL_F32(pOutR,pos,pos,pTmpA); + pTmpA[0] = 1.0f; + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + + pv = pTmpA; + pa = p; + for(j=0;jnumRows-pos; j++) + { + *pdst++ = *pv * *pa++; + } + pa += pos; + pv++; + pdst = pTmpB; + pa0 = pa; + pa1 = pa0 + pOutQ->numRows; + pa2 = pa1 + pOutQ->numRows; + pa3 = pa2 + pOutQ->numRows; + + /* Unrolled loop */ + blkCnt = (pOutQ->numRows-pos - 1) >> 2; + k=1; + while(blkCnt > 0) + { + float32_t sum; + + for(j=0;jnumRows-pos; j++) + { + sum = *pdst; + + sum += pv[0] * *pa0++; + sum += pv[1] * *pa1++; + sum += pv[2] * *pa2++; + sum += pv[3] * *pa3++; + + *pdst++ = sum; + } + pa0 += pos + 3*pOutQ->numRows; + pa1 += pos + 3*pOutQ->numRows; + pa2 += pos + 3*pOutQ->numRows; + pa3 += pos + 3*pOutQ->numRows; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-pos; k++) + { + for(j=0;jnumRows-pos; j++) + { + *pdst++ += *pv * *pa++; + } + pa += pos; + pv++; + pdst = pTmpB; + } + + pa = p; + beta = *pc--; + for(j=0;jnumRows-pos; j++) + { + float32_t f = beta * pTmpA[j]; + + for(i=0;inumCols-pos; i++) + { + *pa = *pa - f * pTmpB[i] ; + pa++; + } + pa += pos; + } + + + nb++; + } + } + + arm_status status = ARM_MATH_SUCCESS; + /* Return to application */ + return (status); +} + +#endif /* end of test for Helium or Neon availability */ + +/** + @} end of MatrixQR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f64.c new file mode 100644 index 0000000..84ce3fb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_qr_f64.c @@ -0,0 +1,311 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_qr_f64.c + * Description: Double floating-point matrix QR decomposition. + * + * $Date: 15 June 2022 + * $Revision: V1.11.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_utils.h" + + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixQR + @{ + */ + +/** + @brief QR decomposition of a m x n double floating point matrix with m >= n. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[in] threshold norm2 threshold. + @param[out] pOutR points to output R matrix structure of dimension m x n + @param[out] pOutQ points to output Q matrix structure of dimension m x m (can be NULL) + @param[out] pOutTau points to Householder scaling factors of dimension n + @param[inout] pTmpA points to a temporary vector of dimension m. + @param[inout] pTmpB points to a temporary vector of dimension m. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par pOutQ is optional: + pOutQ can be a NULL pointer. + In this case, the argument will be ignored + and the output Q matrix won't be computed. + + + @par Norm2 threshold + For the meaning of this argument please + refer to the \ref MatrixHouseholder documentation + + */ + + + + +arm_status arm_mat_qr_f64( + const arm_matrix_instance_f64 * pSrc, + const float64_t threshold, + arm_matrix_instance_f64 * pOutR, + arm_matrix_instance_f64 * pOutQ, + float64_t * pOutTau, + float64_t *pTmpA, + float64_t *pTmpB + ) + +{ + int32_t col=0; + int32_t nb,pos; + float64_t *pa,*pc; + float64_t beta; + float64_t *pv; + float64_t *pdst; + float64_t *p; + + if (pSrc->numRows < pSrc->numCols) + { + return(ARM_MATH_SIZE_MISMATCH); + } + + memcpy(pOutR->pData,pSrc->pData,pSrc->numCols * pSrc->numRows*sizeof(float64_t)); + pOutR->numCols = pSrc->numCols; + pOutR->numRows = pSrc->numRows; + + p = pOutR->pData; + + pc = pOutTau; + for(col=0 ; col < pSrc->numCols; col++) + { + int32_t i,j,k,blkCnt; + float64_t *pa0,*pa1,*pa2,*pa3; + COPY_COL_F64(pOutR,col,col,pTmpA); + + beta = arm_householder_f64(pTmpA,threshold,pSrc->numRows - col,pTmpA); + *pc++ = beta; + + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + pv = pTmpA; + pa = p; + for(j=0;jnumCols-col; j++) + { + *pdst++ = *pv * *pa++; + } + pa += col; + pv++; + pdst = pTmpB; + + pa0 = pa; + pa1 = pa0 + pSrc->numCols; + pa2 = pa1 + pSrc->numCols; + pa3 = pa2 + pSrc->numCols; + + /* Unrolled loop */ + blkCnt = (pSrc->numRows-col - 1) >> 2; + k=1; + while(blkCnt > 0) + { + float64_t sum; + + for(j=0;jnumCols-col; j++) + { + sum = *pdst; + + sum += pv[0] * *pa0++; + sum += pv[1] * *pa1++; + sum += pv[2] * *pa2++; + sum += pv[3] * *pa3++; + + *pdst++ = sum; + } + pa0 += col + 3*pSrc->numCols; + pa1 += col + 3*pSrc->numCols; + pa2 += col + 3*pSrc->numCols; + pa3 += col + 3*pSrc->numCols; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-col; k++) + { + for(j=0;jnumCols-col; j++) + { + *pdst++ += *pv * *pa++; + } + pa += col; + pv++; + pdst = pTmpB; + } + + /* A(col:,col:) - beta v tmpb */ + pa = p; + for(j=0;jnumRows-col; j++) + { + float64_t f = beta * pTmpA[j]; + + for(i=0;inumCols-col; i++) + { + *pa = *pa - f * pTmpB[i] ; + pa++; + } + pa += col; + } + + /* Copy Householder reflectors into R matrix */ + pa = p + pOutR->numCols; + for(k=0;knumRows-col-1; k++) + { + *pa = pTmpA[k+1]; + pa += pOutR->numCols; + } + + p += 1 + pOutR->numCols; + } + + /* Generate Q if requested by user matrix */ + + if (pOutQ != NULL) + { + /* Initialize Q matrix to identity */ + memset(pOutQ->pData,0,sizeof(float64_t)*pOutQ->numRows*pOutQ->numRows); + + pa = pOutQ->pData; + for(col=0 ; col < pOutQ->numCols; col++) + { + *pa = 1.0; + pa += pOutQ->numCols+1; + } + + nb = pOutQ->numRows - pOutQ->numCols + 1; + + pc = pOutTau + pOutQ->numCols - 1; + for(col=0 ; col < pOutQ->numCols; col++) + { + int32_t i,j,k, blkCnt; + float64_t *pa0,*pa1,*pa2,*pa3; + pos = pSrc->numRows - nb; + p = pOutQ->pData + pos + pOutQ->numCols*pos ; + + + COPY_COL_F64(pOutR,pos,pos,pTmpA); + pTmpA[0] = 1.0; + pdst = pTmpB; + + /* v.T A(col:,col:) -> tmpb */ + + pv = pTmpA; + pa = p; + for(j=0;jnumRows-pos; j++) + { + *pdst++ = *pv * *pa++; + } + pa += pos; + pv++; + pdst = pTmpB; + pa0 = pa; + pa1 = pa0 + pOutQ->numRows; + pa2 = pa1 + pOutQ->numRows; + pa3 = pa2 + pOutQ->numRows; + + /* Unrolled loop */ + blkCnt = (pOutQ->numRows-pos - 1) >> 2; + k=1; + while(blkCnt > 0) + { + float64_t sum; + + for(j=0;jnumRows-pos; j++) + { + sum = *pdst; + + sum += pv[0] * *pa0++; + sum += pv[1] * *pa1++; + sum += pv[2] * *pa2++; + sum += pv[3] * *pa3++; + + *pdst++ = sum; + } + pa0 += pos + 3*pOutQ->numRows; + pa1 += pos + 3*pOutQ->numRows; + pa2 += pos + 3*pOutQ->numRows; + pa3 += pos + 3*pOutQ->numRows; + pv += 4; + pdst = pTmpB; + k += 4; + blkCnt--; + } + + pa = pa0; + for(;knumRows-pos; k++) + { + for(j=0;jnumRows-pos; j++) + { + *pdst++ += *pv * *pa++; + } + pa += pos; + pv++; + pdst = pTmpB; + } + + pa = p; + beta = *pc--; + for(j=0;jnumRows-pos; j++) + { + float64_t f = beta * pTmpA[j]; + + for(i=0;inumCols-pos; i++) + { + *pa = *pa - f * pTmpB[i] ; + pa++; + } + pa += pos; + } + + + nb++; + } + } + + arm_status status = ARM_MATH_SUCCESS; + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixQR group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c new file mode 100644 index 0000000..3b14b51 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c @@ -0,0 +1,212 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_f16.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix scaling */ + #ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + f16x8_t vecIn, vecOut, vecScale; + float16_t const *pInVec; + + pInVec = (float16_t const *) pIn; + + vecScale = vdupq_n_f16(scale); + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 8; + + vecOut = vmulq_f16(vecIn, vecScale); + + vst1q(pOut, vecOut); + pOut += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vld1q(pInVec); + vecOut = vecIn * scale; + + vstrhq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} +#else + +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + arm_status status; /* Status of matrix scaling */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixScale group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c new file mode 100644 index 0000000..63aad92 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c @@ -0,0 +1,306 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_f32.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixScale Matrix Scale + + Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the + matrix by the scalar. For example: + + @par Matrix Scaling of a 3 x 3 matrix + + \f[ + \begin{pmatrix} + a_{1,1} & a_{1,2} & a_{1,3} \\ + a_{2,1} & a_{2,2} & a_{2,3} \\ + a_{3,1} & a_{3,2} & a_{3,3} \\ + \end{pmatrix} + * K = + \begin{pmatrix} + K a_{1,1} & K a_{1,2} & K a_{1,3} \\ + K a_{2,1} & K a_{2,2} & K a_{2,3} \\ + K a_{3,1} & K a_{3,2} & K a_{3,3} \\ + \end{pmatrix} + \f] + + The function checks to make sure that the input and output matrices are of the same size. + + In the fixed-point Q15 and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix scaling */ + #ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecIn, vecOut; + float32_t const *pInVec; + + pInVec = (float32_t const *) pIn; + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 4; + + vecOut = vecIn * scale; + + vst1q(pOut, vecOut); + pOut += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vld1q(pInVec); + vecOut = vecIn * scale; + + vstrwq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix scaling */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + blkCnt = numSamples >> 2; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* Scaling and results are stored in the destination buffer. */ + vec1 = vld1q_f32(pIn); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pOut, res); + + /* update pointers to process next sampels */ + pIn += 4U; + pOut += 4U; + + /* Decrement the numSamples loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* The results are stored in the destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + arm_status status; /* Status of matrix scaling */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c new file mode 100644 index 0000000..5d1ea8b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c @@ -0,0 +1,253 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q15.c + * Description: Multiplies a Q15 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q15 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + arm_status status; /* Status of matrix scaling */ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecIn, vecOut; + q15_t const *pInVec; + int32_t totShift = shift + 1; /* shift to apply after scaling */ + + pInVec = (q15_t const *) pIn; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); pInVec += 8; + + /* multiply input with scaler value */ + vecOut = vmulhq(vecIn, vdupq_n_s16(scaleFract)); + /* apply shifting */ + vecOut = vqshlq_r(vecOut, totShift); + + vst1q(pOut, vecOut); pOut += 8; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vld1q(pInVec); pInVec += 8; + vecOut = vmulhq(vecIn, vdupq_n_s16(scaleFract)); + vecOut = vqshlq_r(vecOut, totShift); + vstrhq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = 15 - shift; /* Total shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia (&pIn); + inA2 = read_q15x2_ia (&pIn); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pOut, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pOut, __PKHBT(in4, in3, 16)); + +#else + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c new file mode 100644 index 0000000..f4e87e6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c @@ -0,0 +1,246 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q31.c + * Description: Multiplies a Q31 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q31 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result which is shifted with saturation to 1.31 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecIn, vecOut; + q31_t const *pInVec; + int32_t totShift = shift + 1; /* shift to apply after scaling */ + arm_status status; /* Status of matrix scaling */ + + pInVec = (q31_t const *) pIn; + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 4; + /* multiply input with scaler value */ + vecOut = vmulhq(vecIn, vdupq_n_s32(scaleFract)); + /* apply shifting */ + vecOut = vqshlq_r(vecOut, totShift); + + vst1q(pOut, vecOut); + pOut += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vld1q(pInVec); + pInVec += 4; + vecOut = vmulhq(vecIn, vdupq_n_s32(scaleFract)); + vecOut = vqshlq_r(vecOut, totShift); + vstrwq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = shift + 1; /* Shift to apply after scaling */ + q31_t in, out; /* Temporary variabels */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the results. */ + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; /* Store result destination */ + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixScale group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c new file mode 100644 index 0000000..6b3de66 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c @@ -0,0 +1,238 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f16.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pLT = lt->pData; + float16_t *pA = a->pData; + + float16_t *lt_row; + float16_t *a_col; + + _Float16 invLT; + + f16x8_t vecA; + f16x8_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+7 < cols; j += 8) + { + vecA = vld1q_f16(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f16(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f16(pLT[n*i + k]),vecX); + } + + if ((_Float16)pLT[n*i + i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f16 / (_Float16)pLT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f16(invLT)); + vst1q(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + _Float16 tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= (_Float16)lt_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)lt_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / (_Float16)lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pLT = lt->pData; + float16_t *pA = a->pData; + + float16_t *lt_row; + float16_t *a_col; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float16_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= (_Float16)lt_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)lt_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = (_Float16)tmp / (_Float16)lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c new file mode 100644 index 0000000..3ffd076 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c @@ -0,0 +1,337 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f32.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + float32_t invLT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+3 < cols; j += 4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f32(pLT[n*i + k]),vecX); + } + + if (pLT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f / pLT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f32(invLT)); + vst1q(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + float32_t invLT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+3 < cols; j += 4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq_f32(vecA,vdupq_n_f32(pLT[n*i + k]),vecX); + } + + if (pLT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f / pLT[n*i + i]; + vecA = vmulq_f32(vecA,vdupq_n_f32(invLT)); + vst1q_f32(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#else + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + n = dst->numRows; + cols = dst -> numCols; + + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + float32_t tmp=a_col[i * cols]; + + lt_row = &pLT[n*i]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c new file mode 100644 index 0000000..cc73005 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c @@ -0,0 +1,128 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f64.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f64( + const arm_matrix_instance_f64 * lt, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + float64_t *pX = dst->pData; + float64_t *pLT = lt->pData; + float64_t *pA = a->pData; + + float64_t *lt_row; + float64_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + float64_t tmp=a_col[i * cols]; + + lt_row = &pLT[n*i]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixInv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c new file mode 100644 index 0000000..0f03eaa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c @@ -0,0 +1,230 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f16.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pUT = ut->pData; + float16_t *pA = a->pData; + + float16_t *ut_row; + float16_t *a_col; + + _Float16 invUT; + + f16x8_t vecA; + f16x8_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+7 < cols; j +=8) + { + vecA = vld1q_f16(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f16(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f16(pUT[n*i + k]),vecX); + } + + if ((_Float16)pUT[n*i + i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f16 / (_Float16)pUT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f16(invUT)); + + + vst1q(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + _Float16 tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= (_Float16)ut_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)ut_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / (_Float16)ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pUT = ut->pData; + float16_t *pA = a->pData; + + float16_t *ut_row; + float16_t *a_col; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float16_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= (_Float16)ut_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)ut_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = (_Float16)tmp / (_Float16)ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c new file mode 100644 index 0000000..4b3ef86 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c @@ -0,0 +1,323 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f32.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + float32_t invUT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+3 < cols; j +=4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f32(pUT[n*i + k]),vecX); + } + + if (pUT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f / pUT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f32(invUT)); + + + vst1q(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + float32_t invUT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+3 < cols; j +=4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq_f32(vecA,vdupq_n_f32(pUT[n*i + k]),vecX); + } + + if (pUT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f / pUT[n*i + i]; + vecA = vmulq_f32(vecA,vdupq_n_f32(invUT)); + + + vst1q_f32(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + float32_t tmp=a_col[i * cols]; + + ut_row = &pUT[n*i]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c new file mode 100644 index 0000000..ce6153b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c @@ -0,0 +1,124 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f64.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f64( + const arm_matrix_instance_f64 * ut, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + float64_t *pX = dst->pData; + float64_t *pUT = ut->pData; + float64_t *pA = a->pData; + + float64_t *ut_row; + float64_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + float64_t tmp=a_col[i * cols]; + + ut_row = &pUT[n*i]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixInv group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c new file mode 100644 index 0000000..2e07194 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c @@ -0,0 +1,219 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f16.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix subtraction */ + uint32_t numSamples; /* total number of elements in the matrix */ + float16_t *pDataA, *pDataB, *pDataDst; + f16x8_t vecA, vecB, vecDst = { 0 }; + float16_t const *pSrcAVec; + float16_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float16_t const *) pDataA; + pSrcBVec = (float16_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + vecDst = vsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vsubq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixSub group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c new file mode 100644 index 0000000..df58b98 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c @@ -0,0 +1,321 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f32.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + @par Subraction of two 3 x 3 matrices + + \f[ + \begin{pmatrix} + a_{1,1} & a_{1,2} & a_{1,3} \\ + a_{2,1} & a_{2,2} & a_{2,3} \\ + a_{3,1} & a_{3,2} & a_{3,3} \\ + \end{pmatrix} + - + \begin{pmatrix} + b_{1,1} & b_{1,2} & b_{1,3} \\ + b_{2,1} & b_{2,2} & b_{2,3} \\ + b_{3,1} & b_{3,2} & b_{3,3} \\ + \end{pmatrix} + = + \begin{pmatrix} + a_{1,1}-b_{1,1} & a_{1,2}-b_{1,2} & a_{1,3}-b_{1,3} \\ + a_{2,1}-b_{2,1} & a_{2,2}-b_{2,2} & a_{2,3}-b_{2,3} \\ + a_{3,1}-b_{3,1} & a_{3,2}-b_{3,2} & a_{3,3}-b_{3,3} \\ + \end{pmatrix} + \f] + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix subtraction */ + uint32_t numSamples; /* total number of elements in the matrix */ + float32_t *pDataA, *pDataB, *pDataDst; + f32x4_t vecA, vecB, vecDst = { 0 }; + float32_t const *pSrcAVec; + float32_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float32_t const *) pDataA; + pSrcBVec = (float32_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vsubq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + /* Read values from source A */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* Update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) - (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c new file mode 100644 index 0000000..3f405d6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c @@ -0,0 +1,137 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f64.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_sub_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint64_t numSamples; /* total number of elements in the matrix */ + uint64_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint64_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c new file mode 100644 index 0000000..e611663 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c @@ -0,0 +1,223 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q15.c + * Description: Q15 Matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q15 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q15_t *pDataA, *pDataB, *pDataDst; + q15x8_t vecA, vecB, vecDst = { 0 }; + q15_t const *pSrcAVec; + q15_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q15_t const *) pDataA; + pSrcBVec = (q15_t const *) pDataB; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqsubq(vecA, vecB); + vst1q(pDataDst, vecDst); pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqsubq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, Saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c new file mode 100644 index 0000000..9643bdc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c @@ -0,0 +1,222 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q31.c + * Description: Q31 matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q31 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q31_t *pDataA, *pDataB, *pDataDst; + q31x4_t vecA, vecB, vecDst = { 0 }; + q31_t const *pSrcAVec; + q31_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q31_t const *) pDataA; + pSrcBVec = (q31_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqsubq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and then store the results in the destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and store result in destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixSub group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c new file mode 100644 index 0000000..b162f2c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c @@ -0,0 +1,206 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f16.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 1) + { + pDst->pData[0] = pSrc->pData[0]; + return(ARM_MATH_SUCCESS); + } + if (pDst->numCols == 2) + return arm_mat_trans_16bit_2x2((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_16bit_3x3_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_16bit_4x4_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + } + + arm_mat_trans_16bit_generic(pSrc->numRows, pSrc->numCols, (uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c new file mode 100644 index 0000000..b2baa63 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c @@ -0,0 +1,345 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f32.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + + @par Transpose of a 3 x 3 matrix + + \f[ + \begin{pmatrix} + a_{1,1} & a_{1,2} & a_{1,3} \\ + a_{2,1} & a_{2,2} & a_{2,3} \\ + a_{3,1} & a_{3,2} & a_{3,3} \\ + \end{pmatrix}^T + = + \begin{pmatrix} + a_{1,1} & a_{2,1} & a_{3,1} \\ + a_{1,2} & a_{2,2} & a_{3,2} \\ + a_{1,3} & a_{2,3} & a_{3,3} \\ + \end{pmatrix} + \f] + + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 2) + return arm_mat_trans_32bit_2x2_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_32bit_3x3_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_32bit_4x4_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + } + + arm_mat_trans_32bit_generic_mve(pSrc->numRows, pSrc->numCols, (uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + + uint16_t blkCnt, rowCnt, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* Row loop */ + rowCnt = row >> 2; + while (rowCnt > 0U) + { + float32x4_t row0V,row1V,row2V,row3V; + float32x4x2_t ra0,ra1,rb0,rb1; + + blkCnt = nColumns >> 2; + + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) /* Column loop */ + { + row0V = vld1q_f32(pIn); + row1V = vld1q_f32(pIn + 1 * nColumns); + row2V = vld1q_f32(pIn + 2 * nColumns); + row3V = vld1q_f32(pIn + 3 * nColumns); + pIn += 4; + + ra0 = vzipq_f32(row0V,row2V); + ra1 = vzipq_f32(row1V,row3V); + + rb0 = vzipq_f32(ra0.val[0],ra1.val[0]); + rb1 = vzipq_f32(ra0.val[1],ra1.val[1]); + + vst1q_f32(px,rb0.val[0]); + px += nRows; + + vst1q_f32(px,rb0.val[1]); + px += nRows; + + vst1q_f32(px,rb1.val[0]); + px += nRows; + + vst1q_f32(px,rb1.val[1]); + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + + /* Perform matrix transpose for last 3 samples here. */ + blkCnt = nColumns % 0x4U; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px++ = *pIn; + *px++ = *(pIn + 1 * nColumns); + *px++ = *(pIn + 2 * nColumns); + *px++ = *(pIn + 3 * nColumns); + + px += (nRows - 4); + pIn++; + + /* Decrement the column loop counter */ + blkCnt--; + } + + i += 4; + pIn += 3 * nColumns; + + /* Decrement the row loop counter */ + rowCnt--; + + } /* Row loop end */ + + rowCnt = row & 3; + while (rowCnt > 0U) + { + blkCnt = nColumns ; + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px = *pIn++; + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + i++; + rowCnt -- ; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c new file mode 100644 index 0000000..d01ce3b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c @@ -0,0 +1,152 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f64.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint64_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c new file mode 100644 index 0000000..de00d1b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c @@ -0,0 +1,237 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q15.c + * Description: Q15 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q15 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + + +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 1) + { + pDst->pData[0] = pSrc->pData[0]; + return(ARM_MATH_SUCCESS); + } + if (pDst->numCols == 2) + return arm_mat_trans_16bit_2x2((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_16bit_3x3_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_16bit_4x4_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + } + + arm_mat_trans_16bit_generic(pSrc->numRows, pSrc->numCols, (uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; /* variable to hold temporary output */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer pOut is set to starting address of column being processed */ + pOut = pDst->pData + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read two elements from row */ + in = read_q15x2_ia (&pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Read two elements from row */ + in = read_q15x2_ia (&pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *pOut = *pIn++; + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c new file mode 100644 index 0000000..4f77a28 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c @@ -0,0 +1,195 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q31.c + * Description: Q31 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q31 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + arm_status status; /* status of matrix transpose */ + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 2) + return arm_mat_trans_32bit_2x2_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_32bit_3x3_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_32bit_4x4_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + } + + arm_mat_trans_32bit_generic_mve(pSrc->numRows, pSrc->numCols, (uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c new file mode 100644 index 0000000..666cdfa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c @@ -0,0 +1,175 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q7.c + * Description: Q7 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q7 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_trans_q7(const arm_matrix_instance_q7 *pSrc, arm_matrix_instance_q7 *pDst) +{ + + uint16x8_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint8_t const *pDataC; + uint8_t *pDataDestR; + uint16x8_t vecIn; + + const uint8_t * pDataSrc=(const uint8_t *)pSrc->pData; + uint8_t * pDataDst=(uint8_t *)pDst->pData; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + return ARM_MATH_SIZE_MISMATCH; + } +#endif + + vecOffs = vidupq_u16((uint32_t)0, 1); + vecOffs = vecOffs * pSrc->numCols; + + i = pSrc->numCols; + do + { + pDataC = (uint8_t const *) pDataSrc; + pDataDestR = (uint8_t*)pDataDst; + + blkCnt = pSrc->numRows >> 3; + while (blkCnt > 0U) + { + /* widened loads */ + vecIn = vldrbq_gather_offset_u16(pDataC, vecOffs); + vstrbq_u16(pDataDestR, vecIn); + pDataDestR += 8; + pDataC = pDataC + pSrc->numCols * 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = pSrc->numRows & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrbq_gather_offset_u16(pDataC, vecOffs); + vstrbq_p_u16(pDataDestR, vecIn, p0); + } + pDataSrc += 1; + pDataDst += pSrc->numRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} +#else +arm_status arm_mat_trans_q7(const arm_matrix_instance_q7 *pSrc, arm_matrix_instance_q7 *pDst) +{ + q7_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + i; + + /* Initialize column loop counter */ + col = nColumns; + + + while (col > 0U) { + /* Read and store the input element in the destination */ + *pOut = *pSrcA++; + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + + +/** + @} end of MatrixTrans group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c new file mode 100644 index 0000000..fb7e53c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c @@ -0,0 +1,400 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_f16.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mat_vec_mult_f16( + const arm_matrix_instance_f16 *pSrcMat, + const float16_t *pSrcVec, + float16_t *pDstVec) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float16_t *pSrcA = pSrcMat->pData; + const float16_t *pInA0; + const float16_t *pInA1; + float16_t *px; + int32_t row; + uint32_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4 rows in parallel + */ + while (row >= 4) + { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + *px++ = vecAddAcrossF16Mve(acc1); + *px++ = vecAddAcrossF16Mve(acc2); + *px++ = vecAddAcrossF16Mve(acc3); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) + { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + *px++ = vecAddAcrossF16Mve(acc1); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) + { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = pSrcVec; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + } +} +#else +void arm_mat_vec_mult_f16(const arm_matrix_instance_f16 *pSrcMat, const float16_t *pVec, float16_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float16_t *pSrcA = pSrcMat->pData; + const float16_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float16_t *pInVec; /* input data matrix pointer B of Q31 type */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float16_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + float16_t sum1 = 0.0f16; + float16_t sum2 = 0.0f16; + float16_t sum3 = 0.0f16; + float16_t sum4 = 0.0f16; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA2)++; + sum2 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA3)++; + sum3 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA4)++; + sum4 += (_Float16)matData * (_Float16)vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float16_t sum = 0.0f16; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += (_Float16)matData * (_Float16)vecData; + sum += (_Float16)matData2 * (_Float16)vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += (_Float16)*pInA1++ * (_Float16)*pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c new file mode 100644 index 0000000..145ec15 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c @@ -0,0 +1,403 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_f32.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixVectMult Matrix Vector Multiplication + * + * Multiplies a matrix and a vector. + * + */ + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mat_vec_mult_f32( + const arm_matrix_instance_f32 *pSrcMat, + const float32_t *pSrcVec, + float32_t *pDstVec) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float32_t *pSrcA = pSrcMat->pData; + const float32_t *pInA0; + const float32_t *pInA1; + float32_t *px; + int32_t row; + uint32_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4 rows in parallel + */ + while (row >= 4) + { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + *px++ = vecAddAcrossF32Mve(acc1); + *px++ = vecAddAcrossF32Mve(acc2); + *px++ = vecAddAcrossF32Mve(acc3); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parallel + */ + if (row >= 2) + { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + *px++ = vecAddAcrossF32Mve(acc1); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) + { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = pSrcVec; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + } +} +#else + +void arm_mat_vec_mult_f32(const arm_matrix_instance_f32 *pSrcMat, const float32_t *pVec, float32_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float32_t *pSrcA = pSrcMat->pData; + const float32_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float32_t *pInVec; /* input data matrix pointer B of Q31 type */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float32_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + float32_t sum1 = 0.0f; + float32_t sum2 = 0.0f; + float32_t sum3 = 0.0f; + float32_t sum4 = 0.0f; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += matData * vecData; + matData = *(pInA2)++; + sum2 += matData * vecData; + matData = *(pInA3)++; + sum3 += matData * vecData; + matData = *(pInA4)++; + sum4 += matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float32_t sum = 0.0f; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += matData * vecData; + sum += matData2 * vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + + + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c new file mode 100644 index 0000000..9d9b1b4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c @@ -0,0 +1,392 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q15.c + * Description: Q15 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q15 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mat_vec_mult_q15( + const arm_matrix_instance_q15 * pSrcMat, + const q15_t *pSrcVec, + q15_t *pDstVec) +{ + const q15_t *pMatSrc = pSrcMat->pData; + const q15_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q15_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 3x64-bit accumulators per loop + */ + while (row >= 3) + { + q15_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pVec; + const q15_t *pMat2; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1, acc2; + q15x8_t vecMatA0, vecMatA1, vecMatA2, vecIn; + + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 8; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecIn = vldrhq_z_s16(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + } + + *px++ = MVE_ASRL_SAT16(acc0, 15); + *px++ = MVE_ASRL_SAT16(acc1, 15); + *px++ = MVE_ASRL_SAT16(acc2, 15); + + pMatSrc += numCols * 3; + /* + * Decrement the row loop counter + */ + row -= 3; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q15_t const *pMat0Vec, *pMat1Vec, *pVec; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1; + q15x8_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrhq_z_s16(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + } + + *px++ = MVE_ASRL_SAT16(acc0, 15); + *px++ = MVE_ASRL_SAT16(acc1, 15); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q15_t const *pMat0Vec, *pVec; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0; + q15x8_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrhq_z_s16(pVec, p0); + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + } + *px++ = MVE_ASRL_SAT16(acc0, 15); + } +} + +#else +void arm_mat_vec_mult_q15(const arm_matrix_instance_q15 *pSrcMat, const q15_t *pVec, q15_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q15_t *pSrcA = pSrcMat->pData; + const q15_t *pInA1; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA2; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA3; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA4; /* input data matrix pointer A of Q15 type */ + const q15_t *pInVec; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols >> 1; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = read_q15x2_ia (&pInVec); + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = read_q15x2_ia (&pInA1); + sum1 = __SMLALD(matData, vecData, sum1); + matData = read_q15x2_ia (&pInA2); + sum2 = __SMLALD(matData, vecData, sum2); + matData = read_q15x2_ia (&pInA3); + sum3 = __SMLALD(matData, vecData, sum3); + matData = read_q15x2_ia (&pInA4); + sum4 = __SMLALD(matData, vecData, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + colCnt = numCols & 1u; + if (numCols & 1u) { + vecData = *pInVec++; + sum1 += (q63_t)*pInA1++ * vecData; + sum2 += (q63_t)*pInA2++ * vecData; + sum3 += (q63_t)*pInA3++ * vecData; + sum4 += (q63_t)*pInA4++ * vecData; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q15_t)(__SSAT((sum1 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum2 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum3 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum4 >> 15), 16)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q15x2_ia (&pInVec); + vecData2 = read_q15x2_ia (&pInVec); + matData = read_q15x2_ia (&pInA1); + matData2 = read_q15x2_ia (&pInA1); + sum = __SMLALD(matData, vecData, sum); + sum = __SMLALD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q15_t)(__SSAT((sum >> 15), 16)); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c new file mode 100644 index 0000000..6e0b855 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c @@ -0,0 +1,380 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q31.c + * Description: Q31 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q31 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mat_vec_mult_q31( + const arm_matrix_instance_q31 * pSrcMat, + const q31_t *pSrcVec, + q31_t *pDstVec) +{ + const q31_t *pMatSrc = pSrcMat->pData; + const q31_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q31_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 3x64-bit accumulators per loop + */ + while (row >= 3) + { + q31_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pVec; + const q31_t *pMat2; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1, acc2; + q31x4_t vecMatA0, vecMatA1, vecMatA2, vecIn; + + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 4; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecIn = vldrwq_z_s32(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + } + + *px++ = asrl(acc0, 31); + *px++ = asrl(acc1, 31); + *px++ = asrl(acc2, 31); + + pMatSrc += numCols * 3; + /* + * Decrement the row loop counter + */ + row -= 3; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q31_t const *pMat0Vec, *pMat1Vec, *pVec; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1; + q31x4_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrwq_z_s32(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + } + + *px++ = asrl(acc0, 31); + *px++ = asrl(acc1, 31); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q31_t const *pMat0Vec, *pVec; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0; + q31x4_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrwq_z_s32(pVec, p0); + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + } + + *px++ = asrl(acc0, 31); + } +} +#else +void arm_mat_vec_mult_q31(const arm_matrix_instance_q31 *pSrcMat, const q31_t *pVec, q31_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q31_t *pSrcA = pSrcMat->pData; + const q31_t *pInA1; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA2; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA3; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA4; /* input data matrix pointer A of Q31 type */ + const q31_t *pInVec; /* input data matrix pointer B of Q31 type */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += (q63_t)matData * vecData; + matData = *(pInA2)++; + sum2 += (q63_t)matData * vecData; + matData = *(pInA3)++; + sum3 += (q63_t)matData * vecData; + matData = *(pInA4)++; + sum4 += (q63_t)matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q31_t)(sum1 >> 31); + *px++ = (q31_t)(sum2 >> 31); + *px++ = (q31_t)(sum3 >> 31); + *px++ = (q31_t)(sum4 >> 31); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += (q63_t)matData * vecData; + sum += (q63_t)matData2 * vecData2; + colCnt--; + } + + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = (q31_t)(sum >> 31); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c new file mode 100644 index 0000000..5262ce3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c @@ -0,0 +1,424 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q7.c + * Description: Q7 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q7 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mat_vec_mult_q7( + const arm_matrix_instance_q7 * pSrcMat, + const q7_t *pSrcVec, + q7_t *pDstVec) +{ + const q7_t *pMatSrc = pSrcMat->pData; + const q7_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q7_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4x64-bit accumulators per loop + */ + while (row >= 4) + { + q7_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pMat3Vec, *pVec; + const q7_t *pMat2, *pMat3; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecMatA0, vecMatA1, vecMatA2, vecMatA3, vecIn; + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + pMat3 = pMat2 + numCols; + + acc0 = 0L; + acc1 = 0L; + acc2 = 0L; + acc3 = 0L; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pMat3Vec = pMat3; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 16; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 16; + vecMatA3 = vld1q(pMat3Vec); + pMat3Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + acc2 = vmladavaq(acc2, vecIn, vecMatA2); + acc3 = vmladavaq(acc3, vecIn, vecMatA3); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecMatA3 = vld1q(pMat3Vec); + vecIn = vldrbq_z_s8(pVec, p0); + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + acc2 = vmladavaq(acc2, vecIn, vecMatA2); + acc3 = vmladavaq(acc3, vecIn, vecMatA3); + } + + *px++ = __SSAT(acc0 >> 7, 8); + *px++ = __SSAT(acc1 >> 7, 8); + *px++ = __SSAT(acc2 >> 7, 8); + *px++ = __SSAT(acc3 >> 7, 8); + + pMatSrc += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q7_t const *pMat0Vec, *pMat1Vec, *pVec; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0, acc1; + q7x16_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0; + acc1 = 0; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrbq_z_s8(pVec, p0); + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + } + + *px++ = __SSAT(acc0 >> 7, 8); + *px++ = __SSAT(acc1 >> 7, 8); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q7_t const *pMat0Vec, *pVec; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0; + q7x16_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrbq_z_s8(pVec, p0); + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + } + *px++ = __SSAT(acc0 >> 7, 8); + } +} + +#else +void arm_mat_vec_mult_q7(const arm_matrix_instance_q7 *pSrcMat, const q7_t *pVec, q7_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q7_t *pSrcA = pSrcMat->pData; + const q7_t *pInA1; /* input data matrix pointer of Q7 type */ + const q7_t *pInA2; /* input data matrix pointer of Q7 type */ + const q7_t *pInA3; /* input data matrix pointer of Q7 type */ + const q7_t *pInA4; /* input data matrix pointer of Q7 type */ + const q7_t *pInVec; /* input data vector pointer of Q7 type */ + q7_t *px; /* output data pointer */ + uint32_t i, row, colCnt; /* loop counters */ + + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + while (row > 0) { + /* Initialize accumulators */ + q31_t sum1 = 0; + q31_t sum2 = 0; + q31_t sum3 = 0; + q31_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 4 columns per iteration */ + colCnt = numCols >> 2; + + /* Initialize row pointers so we can track 4 rows at once */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Inner loop: matrix-vector multiplication + + while (colCnt > 0u) { + // Read 4 values from vector + vecData = read_q7x4_ia (&pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + // Read 16 values from the matrix - 4 values from each of 4 rows, and do multiply accumulate + matData = read_q7x4_ia (&pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum1 = __SMLAD(matData, vecData, sum1); + sum1 = __SMLAD(matData2, vecData2, sum1); + matData = read_q7x4_ia (&pInA2); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum2 = __SMLAD(matData, vecData, sum2); + sum2 = __SMLAD(matData2, vecData2, sum2); + matData = read_q7x4_ia (&pInA3); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum3 = __SMLAD(matData, vecData, sum3); + sum3 = __SMLAD(matData2, vecData2, sum3); + matData = read_q7x4_ia (&pInA4); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum4 = __SMLAD(matData, vecData, sum4); + sum4 = __SMLAD(matData2, vecData2, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + + colCnt = numCols & 3u; + + while (colCnt > 0) { + vecData = *pInVec++; + sum1 += *pInA1++ * vecData; + sum2 += *pInA2++ * vecData; + sum3 += *pInA3++ * vecData; + sum4 += *pInA4++ * vecData; + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)(__SSAT((sum1 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum2 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum3 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum4 >> 7), 8)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q31_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q7x4_ia (&pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + matData = read_q7x4_ia (&pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum = __SMLAD(matData, vecData, sum); + sum = __SMLAD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q7_t)(__SSAT((sum >> 7), 8)); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c new file mode 100644 index 0000000..6d1ee09 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c @@ -0,0 +1,185 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion2rotation_f32.c + * Description: Floating-point quaternion 2 rotation conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConv Quaternion conversions + + Conversions between quaternion and rotation representations. + */ + +/** + @ingroup QuatConv + */ + +/** + @defgroup QuatRot Quaternion to Rotation + + Conversions from quaternion to rotation. + */ + +/** + @addtogroup QuatRot + @{ + */ + +/** + @brief Conversion of quaternion to equivalent rotation matrix. + @param[in] pInputQuaternions points to an array of normalized quaternions + @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + @param[in] nbQuaternions number of quaternions in the array + @return none. + + @par + Format of rotation matrix + + + The quaternion a + ib + jc + kd is converted into rotation matrix: + 
+     a^2 + b^2 - c^2 - d^2                 2bc - 2ad                 2bd + 2ac
+                 2bc + 2ad     a^2 - b^2 + c^2 - d^2                 2cd - 2ab
+                 2bd - 2ac                 2cd + 2ab     a^2 - b^2 - c^2 + d^2
+
+ Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ + f32x4_t vec0,vec1, vec2 ,vec3; + float32_t q2q3, tmp1, tmp2 ; + + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + + // q0 q1 q2 q3 + vec0 = vld1q(pInputQuaternions); + + // q0^2 q1^2 q2^2 q3^2 + vec1 = vmulq(vec0,vec0); + + // q0^2 q1q0 q2q0 q3q0 + vec2 = vmulq_n_f32(vec0, vgetq_lane(vec0,0)); + + // 2 (q0^2 q1q0 q2q0 q3q0) + vec2 = vmulq_n_f32(vec2, 2.0f); + + + // 2 q2q3 + q2q3 = vgetq_lane(vec0,2) * vgetq_lane(vec0,3); + q2q3 = q2q3 * 2.0f; + + // 2 (q0q1 q1^2 q2q1 q3q1) + vec3 = vmulq_n_f32(vec0, vgetq_lane(vec0,1)); + vec3 = vmulq_n_f32(vec3, 2.0f); + + + + vec0 = vsetq_lane(vgetq_lane(vec1,0) + vgetq_lane(vec1,1),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec0,0) - vgetq_lane(vec1,2),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec0,0) - vgetq_lane(vec1,3),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec3,2) - vgetq_lane(vec2,3),vec0,1); + vec0 = vsetq_lane(vgetq_lane(vec3,3) + vgetq_lane(vec2,2),vec0,2); + vec0 = vsetq_lane(vgetq_lane(vec3,2) + vgetq_lane(vec2,3),vec0,3); + + vst1q(pOutputRotations, vec0); + pOutputRotations += 4; + + tmp1 = vgetq_lane(vec1,0) - vgetq_lane(vec1,1); + tmp2 = vgetq_lane(vec1,2) - vgetq_lane(vec1,3); + + + vec0 = vsetq_lane(tmp1 + tmp2,vec0,0); + vec0 = vsetq_lane(q2q3 - vgetq_lane(vec2,1) ,vec0,1); + vec0 = vsetq_lane(vgetq_lane(vec3,3) - vgetq_lane(vec2,2),vec0,2); + vec0 = vsetq_lane(q2q3 + vgetq_lane(vec2,1) ,vec0,3); + + vst1q(pOutputRotations, vec0); + pOutputRotations += 4; + + *pOutputRotations = tmp1 - tmp2; + pOutputRotations ++; + + pInputQuaternions += 4; + } +} + +#else +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ + uint32_t nb; + for(nb=0; nb < nbQuaternions; nb++) + { + float32_t q00 = SQ(pInputQuaternions[0 + nb * 4]); + float32_t q11 = SQ(pInputQuaternions[1 + nb * 4]); + float32_t q22 = SQ(pInputQuaternions[2 + nb * 4]); + float32_t q33 = SQ(pInputQuaternions[3 + nb * 4]); + float32_t q01 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[1 + nb * 4]; + float32_t q02 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q03 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q12 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q13 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q23 = pInputQuaternions[2 + nb * 4]*pInputQuaternions[3 + nb * 4]; + + float32_t xx = q00 + q11 - q22 - q33; + float32_t yy = q00 - q11 + q22 - q33; + float32_t zz = q00 - q11 - q22 + q33; + float32_t xy = 2*(q12 - q03); + float32_t xz = 2*(q13 + q02); + float32_t yx = 2*(q12 + q03); + float32_t yz = 2*(q23 - q01); + float32_t zx = 2*(q13 - q02); + float32_t zy = 2*(q23 + q01); + + pOutputRotations[0 + nb * 9] = xx; pOutputRotations[1 + nb * 9] = xy; pOutputRotations[2 + nb * 9] = xz; + pOutputRotations[3 + nb * 9] = yx; pOutputRotations[4 + nb * 9] = yy; pOutputRotations[5 + nb * 9] = yz; + pOutputRotations[6 + nb * 9] = zx; pOutputRotations[7 + nb * 9] = zy; pOutputRotations[8 + nb * 9] = zz; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatRot group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c new file mode 100644 index 0000000..c3d80f9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c @@ -0,0 +1,102 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_conjugate_f32.c + * Description: Floating-point quaternion conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConjugate Quaternion Conjugate + + Compute the conjugate of a quaternion. + */ + +/** + @addtogroup QuatConjugate + @{ + */ + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + + + vec1 = vsetq_lane_f32(-vgetq_lane(vec1, 0),vec1,0); + vec1 = vnegq_f32(vec1); + + vst1q(pConjugateQuaternions, vec1); + + + pInputQuaternions += 4; + pConjugateQuaternions += 4; + } +} +#else +void arm_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + + pConjugateQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0]; + pConjugateQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1]; + pConjugateQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2]; + pConjugateQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3]; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatConjugate group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c new file mode 100644 index 0000000..d4227eb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c @@ -0,0 +1,118 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_inverse_f32.c + * Description: Floating-point quaternion inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatInverse Quaternion Inverse + + Compute the inverse of a quaternion. + */ + +/** + @addtogroup QuatInverse + @{ + */ + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1,vec2; + float32_t squaredSum; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + + vec1 = vld1q(pInputQuaternions); + vec2 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec2); + + + vec1 = vmulq_n_f32(vec1, 1.0f / squaredSum); + vec1 = vsetq_lane_f32(-vgetq_lane(vec1, 0),vec1,0); + vec1 = vnegq_f32(vec1); + + vst1q(pInverseQuaternions, vec1); + + + pInputQuaternions += 4; + pInverseQuaternions += 4; + + } +} + +#else +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + + pInverseQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pInverseQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1] / temp; + pInverseQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2] / temp; + pInverseQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3] / temp; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatInverse group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c new file mode 100644 index 0000000..e5a6130 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c @@ -0,0 +1,106 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_norm_f32.c + * Description: Floating-point quaternion Norm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNorm Quaternion Norm + + Compute the norm of a quaternion. + */ + +/** + @addtogroup QuatNorm + @{ + */ + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in the input vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + f32x4_t vec1; + float32_t squaredSum; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + vec1 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec1); + arm_sqrt_f32(squaredSum,pNorms); + + pInputQuaternions+= 4; + pNorms ++; + } + +} + +#else + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + float32_t temp; + uint32_t i; + + for(i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + pNorms[i] = sqrtf(temp); + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatNorm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c new file mode 100644 index 0000000..1380f6b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c @@ -0,0 +1,111 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_normalize_f32.c + * Description: Floating-point quaternion normalization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNormalized Quaternion normalization + + Compute a normalized quaternion. + */ + +/** + @addtogroup QuatNormalized + @{ + */ + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1,vec2; + float32_t squaredSum,norm; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + vec2 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec2); + arm_sqrt_f32(squaredSum,&norm); + vec1 = vmulq_n_f32(vec1, 1.0f / norm); + vst1q(pNormalizedQuaternions, vec1); + + pInputQuaternions += 4; + pNormalizedQuaternions += 4; + + } +} + +#else +void arm_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + temp = sqrtf(temp); + + pNormalizedQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pNormalizedQuaternions[4 * i + 1] = pInputQuaternions[4 * i + 1] / temp; + pNormalizedQuaternions[4 * i + 2] = pInputQuaternions[4 * i + 2] / temp; + pNormalizedQuaternions[4 * i + 3] = pInputQuaternions[4 * i + 3] / temp; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatNormalized group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c new file mode 100644 index 0000000..fef8388 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c @@ -0,0 +1,153 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_product_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatProd Quaternion Product + + Compute the product of quaternions. + */ + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdVect Elementwise Quaternion Product + + Compute the elementwise product of quaternions. + */ + +/** + @addtogroup QuatProdVect + @{ + */ + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa first array of quaternions + @param[in] qb second array of quaternions + @param[out] qr elementwise product of quaternions + @param[in] nbQuaternions number of quaternions in the array + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ + static uint32_t patternA[4] = { 0, 1, 0, 1 }; + static uint32_t patternB[4] = { 3, 2, 3, 2 }; + static uint32_t patternC[4] = { 3, 2, 1, 0 }; + static float32_t signA[4] = { -1, -1, 1, 1 }; + + uint32x4_t vecA = vld1q_u32(patternA); + uint32x4_t vecB = vld1q_u32(patternB); + uint32x4_t vecC = vld1q_u32(patternC); + f32x4_t vecSignA = vld1q_f32(signA); + + while (nbQuaternions > 0U) + { + f32x4_t vecTmpA, vecTmpB, vecAcc; + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecA); + vecTmpB = vld1q(qb); + /* + * vcmul(r, [a1, a2, a1, a2], [b1, b2, b3, b4], 0) + */ + vecAcc = vcmulq(vecTmpA, vecTmpB); + /* + * vcmla(r, [a1, a2, a1, a2], [b1, b2, b3, b4], 90) + */ + vecAcc = vcmlaq_rot90(vecAcc, vecTmpA, vecTmpB); + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecB); + vecTmpB = vldrwq_gather_shifted_offset_f32(qb, vecC); + /* + * build [-b4, -b3, b2, b1] + */ + vecTmpB = vecTmpB * vecSignA; + /* + * vcmla(r, [a4, a3, a4, a3], [-b4, -b3, b2, b1], 270) + */ + vecAcc = vcmlaq_rot270(vecAcc, vecTmpA, vecTmpB); + /* + * vcmla(r, [a4, a3, a4, a3], [-b4, -b3, b2, b1], 0) + */ + vecAcc = vcmlaq(vecAcc, vecTmpA, vecTmpB); + /* + * store accumulator + */ + vst1q_f32(qr, vecAcc); + + /* move to next quaternion */ + qa += 4; + qb += 4; + qr += 4; + + nbQuaternions--; + } +} + +#else + +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + arm_quaternion_product_single_f32(qa, qb, qr); + + qa += 4; + qb += 4; + qr += 4; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatProdVect group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c new file mode 100644 index 0000000..e8149fd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c @@ -0,0 +1,111 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_product_single_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdSingle Quaternion Product + + Compute the product of two quaternions. + */ + +/** + @addtogroup QuatProdSingle + @{ + */ + +/** + @brief Floating-point product of two quaternions. + @param[in] qa first quaternion + @param[in] qb second quaternion + @param[out] qr product of two quaternions + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + static uint32_t patternA[4] = { 0, 1, 0, 1 }; + static uint32_t patternB[4] = { 3, 2, 3, 2 }; + static uint32_t patternC[4] = { 3, 2, 1, 0 }; + static float32_t signA[4] = { -1, -1, 1, 1 }; + + uint32x4_t vecA = vld1q_u32(patternA); + uint32x4_t vecB = vld1q_u32(patternB); + uint32x4_t vecC = vld1q_u32(patternC); + f32x4_t vecSignA = vld1q_f32(signA); + + + f32x4_t vecTmpA, vecTmpB, vecAcc; + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecA); + vecTmpB = vld1q_f32(qb); + + vecAcc = vcmulq_f32(vecTmpA, vecTmpB); + vecAcc = vcmlaq_rot90_f32(vecAcc, vecTmpA, vecTmpB); + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecB); + vecTmpB = vldrwq_gather_shifted_offset_f32(qb, vecC); + + vecTmpB = vecTmpB * vecSignA; + + vecAcc = vcmlaq_rot270_f32(vecAcc, vecTmpA, vecTmpB); + vecAcc = vcmlaq_f32(vecAcc, vecTmpA, vecTmpB); + + vst1q_f32(qr, vecAcc); +} + +#else +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + qr[0] = qa[0] * qb[0] - qa[1] * qb[1] - qa[2] * qb[2] - qa[3] * qb[3]; + qr[1] = qa[0] * qb[1] + qa[1] * qb[0] + qa[2] * qb[3] - qa[3] * qb[2]; + qr[2] = qa[0] * qb[2] + qa[2] * qb[0] + qa[3] * qb[1] - qa[1] * qb[3]; + qr[3] = qa[0] * qb[3] + qa[3] * qb[0] + qa[1] * qb[2] - qa[2] * qb[1]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatProdSingle group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c new file mode 100644 index 0000000..54d56a1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c @@ -0,0 +1,229 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rotation2quaternion_f32.c + * Description: Floating-point rotation to quaternion conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/quaternion_math_functions.h" +#include + +#define RI(x,y) r[(3*(x) + (y))] + + +/** + @ingroup QuatConv + */ + +/** + @defgroup RotQuat Rotation to Quaternion + + Conversions from rotation to quaternion. + */ + +/** + @addtogroup RotQuat + @{ + */ + +/** + * @brief Conversion of a rotation matrix to an equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array quaternions + * @param[in] nbQuaternions number of quaternions in the array + * @return none. + * + * q and -q are representing the same rotation. This ambiguity must be taken into + * account when using the output of this function. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define R00 vgetq_lane(q1,0) +#define R01 vgetq_lane(q1,1) +#define R02 vgetq_lane(q1,2) +#define R10 vgetq_lane(q1,3) +#define R11 vgetq_lane(q2,0) +#define R12 vgetq_lane(q2,1) +#define R20 vgetq_lane(q2,2) +#define R21 vgetq_lane(q2,3) +#define R22 ro22 + +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + float32_t ro22, trace; + f32x4_t q1,q2, q; + + float32_t doubler; + float32_t s; + + q = vdupq_n_f32(0.0f); + + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + q1 = vld1q(pInputRotations); + pInputRotations += 4; + + q2 = vld1q(pInputRotations); + pInputRotations += 4; + + ro22 = *pInputRotations++; + + trace = R00 + R11 + R22; + + + if (trace > 0) + { + (void)arm_sqrt_f32(trace + 1.0f, &doubler) ; // invs=4*qw + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = 0.25f * doubler; + q[1] = R21 - R12; + q[2] = R02 - R20; + q[3] = R10 - R01; + } + else if ((R00 > R11) && (R00 > R22) ) + { + (void)arm_sqrt_f32(1.0f + R00 - R11 - R22,&doubler); // invs=4*qx + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R21 - R12; + q[1] = 0.25f * doubler; + q[2] = R01 + R10; + q[3] = R02 + R20; + } + else if (R11 > R22) + { + (void)arm_sqrt_f32(1.0f + R11 - R00 - R22,&doubler); // invs=4*qy + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R02 - R20; + q[1] = R01 + R10; + q[2] = 0.25f * doubler; + q[3] = R12 + R21; + } + else + { + (void)arm_sqrt_f32(1.0f + R22 - R00 - R11,&doubler); // invs=4*qz + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R10 - R01; + q[1] = R02 + R20; + q[2] = R12 + R21; + q[3] = 0.25f * doubler; + } + + vst1q(pOutputQuaternions, q); + pOutputQuaternions += 4; + + } +} + +#else +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + uint32_t nb; + for(nb=0; nb < nbQuaternions; nb++) + { + const float32_t *r=&pInputRotations[nb*9]; + float32_t *q=&pOutputQuaternions[nb*4]; + + float32_t trace = RI(0,0) + RI(1,1) + RI(2,2); + + float32_t doubler; + float32_t s; + + + + if (trace > 0.0f) + { + doubler = sqrtf(trace + 1.0f) * 2.0f; // invs=4*qw + s = 1.0f / doubler; + q[0] = 0.25f * doubler; + q[1] = (RI(2,1) - RI(1,2)) * s; + q[2] = (RI(0,2) - RI(2,0)) * s; + q[3] = (RI(1,0) - RI(0,1)) * s; + } + else if ((RI(0,0) > RI(1,1)) && (RI(0,0) > RI(2,2)) ) + { + doubler = sqrtf(1.0f + RI(0,0) - RI(1,1) - RI(2,2)) * 2.0f; // invs=4*qx + s = 1.0f / doubler; + q[0] = (RI(2,1) - RI(1,2)) * s; + q[1] = 0.25f * doubler; + q[2] = (RI(0,1) + RI(1,0)) * s; + q[3] = (RI(0,2) + RI(2,0)) * s; + } + else if (RI(1,1) > RI(2,2)) + { + doubler = sqrtf(1.0f + RI(1,1) - RI(0,0) - RI(2,2)) * 2.0f; // invs=4*qy + s = 1.0f / doubler; + q[0] = (RI(0,2) - RI(2,0)) * s; + q[1] = (RI(0,1) + RI(1,0)) * s; + q[2] = 0.25f * doubler; + q[3] = (RI(1,2) + RI(2,1)) * s; + } + else + { + doubler = sqrtf(1.0f + RI(2,2) - RI(0,0) - RI(1,1)) * 2.0f; // invs=4*qz + s = 1.0f / doubler; + q[0] = (RI(1,0) - RI(0,1)) * s; + q[1] = (RI(0,2) + RI(2,0)) * s; + q[2] = (RI(1,2) + RI(2,1)) * s; + q[3] = 0.25f * doubler; + } + + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RotQuat group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c new file mode 100644 index 0000000..71bb9cb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c @@ -0,0 +1,93 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f16.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup groupSVM + */ + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c new file mode 100644 index 0000000..4c92653 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + +/** + * @defgroup groupSVM SVM Functions + * + */ + +/** + @ingroup groupSVM + */ + +/** + @defgroup linearsvm Linear SVM + + Linear SVM classifier + */ + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c new file mode 100644 index 0000000..8e5a55c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c @@ -0,0 +1,318 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_predict_f16.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_svm_linear_predict_f16( + const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) + { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f16(acc0,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc2,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc3,*pDualCoef++); + + sum += (_Float16)vecAddAcrossF16Mve(acc0); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f16(acc0,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++); + + sum += (_Float16)vecAddAcrossF16Mve(acc0); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + sum += (_Float16)*pDualCoef++ * (_Float16)vecAddAcrossF16Mve(acc0); + + } + + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_linear_predict_f16( + const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = (_Float16)dot + (_Float16)in[j]* (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)dot; + } + *pResult=S->classes[STEP(sum)]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c new file mode 100644 index 0000000..8cf9678 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c @@ -0,0 +1,465 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_predict_f32.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) + { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + + acc0 = vmulq_n_f32(acc0,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc1,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc2,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc3,*pDualCoef++); + + sum += vecAddAcrossF32Mve(acc0); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f32(acc0,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc1,*pDualCoef++); + + sum += vecAddAcrossF32Mve(acc0); + + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + sum += *pDualCoef++ * vecAddAcrossF32Mve(acc0); + + } + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * dot; + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * dot; + } + *pResult=S->classes[STEP(sum)]; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of linearsvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c new file mode 100644 index 0000000..a2ed980 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c @@ -0,0 +1,102 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_init_f16.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c new file mode 100644 index 0000000..082399b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c @@ -0,0 +1,101 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_init_f32.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup polysvm Polynomial SVM + + Polynomial SVM classifier + */ + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c new file mode 100644 index 0000000..3cd6912 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c @@ -0,0 +1,373 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_predict_f16.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +_Float16 is not supported in g++ so we avoid putting _Float16 definitions +in the public headers. + +This function should at some point be moved in FastMath. + +*/ +__STATIC_INLINE float16_t arm_exponent_f16(float16_t x, int32_t nb) +{ + float16_t r = x; + nb --; + while(nb > 0) + { + r = (_Float16)r * (_Float16)x; + nb--; + } + return(r); +} +#endif + +/** + * @addtogroup polysvm + * @{ + */ + + + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f16( + const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), + S->degree),vctp16q(4)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), S->degree), + vctp16q(2)); + + pDualCoef += 2; + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), S->degree), + vctp16q(1)); + } + sum += (_Float16)vecAddAcrossF16Mve(vSum); + + + *pResult = S->classes[STEP(sum)]; +} + +#else + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f16( + const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = (_Float16)dot + (_Float16)in[j]* (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)arm_exponent_f16((_Float16)S->gamma * (_Float16)dot + (_Float16)S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c new file mode 100644 index 0000000..2d97e2b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c @@ -0,0 +1,494 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_predict_f32.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" +#endif + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = vfmaq_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = vfmaq_m_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree), + vctp32q(2)); + + pDualCoef += 2; + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vSum = vfmaq_m_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree), + vctp32q(1)); + } + sum += vecAddAcrossF32Mve(vSum); + + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + float32x4_t coef0 = vdupq_n_f32(S->coef0); + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, S->gamma); + dotV = vaddq_f32(dotV, coef0); + + dotV = arm_vec_exponent_f32(dotV,S->degree); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of polysvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c new file mode 100644 index 0000000..5b2492f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_init_f16.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c new file mode 100644 index 0000000..9fddb02 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c @@ -0,0 +1,95 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_init_f32.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup rbfsvm RBF SVM + + RBF SVM classifier + */ + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c new file mode 100644 index 0000000..15dd7e6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c @@ -0,0 +1,356 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_predict_f16.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +void arm_svm_rbf_predict_f16( + const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f16); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f16); + acc1 = vdupq_n_f16(0.0f16); + acc2 = vdupq_n_f16(0.0f16); + acc3 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA2Vec, p0);; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + + //sum += *pDualCoef++ * expf(-S->gamma * vecReduceF16Mve(acc0)); + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -(_Float16)S->gamma)),vctp16q(4)); + pDualCoef += 4; + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f16); + acc1 = vdupq_n_f16(0.0f16); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif);; + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA, vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -(_Float16)S->gamma)), vctp16q(2)); + pDualCoef += 2; + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA, vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA, vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -(_Float16)S->gamma)), vctp16q(1)); + + } + + + sum += (_Float16)vecAddAcrossF16Mve(vSum); + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_rbf_predict_f16( + const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=00.f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ((_Float16)in[j] - (_Float16) *pSupport); + pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)expf((float32_t)(-(_Float16)S->gamma * (_Float16)dot)); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c new file mode 100644 index 0000000..87d71e3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c @@ -0,0 +1,527 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_predict_f32.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA2Vec, p0);; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + + //sum += *pDualCoef++ * expf(-S->gamma * vecReduceF32Mve(acc0)); + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = + vfmaq_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma))); + pDualCoef += 4; + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif);; + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA, vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma)), vctp32q(2)); + pDualCoef += 2; + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA, vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA, vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma)), vctp32q(1)); + + } + + + sum += vecAddAcrossF32Mve(vSum); + *pResult = S->classes[STEP(sum)]; +} + + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t temp; + float32x4_t vec1; + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + temp = vsubq_f32(vec1, vec2a); + accuma = vmlaq_f32(accuma, temp, temp); + + temp = vsubq_f32(vec1, vec2b); + accumb = vmlaq_f32(accumb, temp, temp); + + temp = vsubq_f32(vec1, vec2c); + accumc = vmlaq_f32(accumc, temp, temp); + + temp = vsubq_f32(vec1, vec2d); + accumd = vmlaq_f32(accumd, temp, temp); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + SQ(*pIn - *pSupporta), dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + SQ(*pIn - *pSupportb), dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + SQ(*pIn - *pSupportc), dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + SQ(*pIn - *pSupportd), dotV,3); + + pSupporta++; + pSupportb++; + pSupportc++; + pSupportd++; + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, -S->gamma); + dotV = vexpq_f32(dotV); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + temp = vsubq_f32(vec1,vec2); + accum = vmlaq_f32(accum, temp,temp); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + + dot = dot + SQ(*pIn - *pSupport); + pIn++; + pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * expf(-S->gamma * dot); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ(in[j] - *pSupport); + pSupport++; + } + sum += S->dualCoefficients[i] * expf(-S->gamma * dot); + } + *pResult=S->classes[STEP(sum)]; +} +#endif + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of rbfsvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c new file mode 100644 index 0000000..33aaf42 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c @@ -0,0 +1,97 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c new file mode 100644 index 0000000..2274e72 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup sigmoidsvm Sigmoid SVM + + Sigmoid SVM classifier + */ + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c new file mode 100644 index 0000000..572bc83 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c @@ -0,0 +1,337 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +void arm_svm_sigmoid_predict_f16( + const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)),vctp16q(4)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)), + vctp16q(2)); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)), + vctp16q(1)); + } + sum += (_Float16)vecAddAcrossF16Mve(vSum); + + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_sigmoid_predict_f16( + const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0.0f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = (_Float16)dot + (_Float16)in[j] * (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)tanhf((float32_t)((_Float16)S->gamma * (_Float16)dot + (_Float16)S->coef0)); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c new file mode 100644 index 0000000..b607820 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c @@ -0,0 +1,491 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/svm_functions.h" +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = + vfmaq_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0))); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0)), + vctp32q(2)); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0)), + vctp32q(1)); + } + sum += vecAddAcrossF32Mve(vSum); + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +#include "NEMath.h" + +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + float32x4_t coef0 = vdupq_n_f32(S->coef0); + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, S->gamma); + dotV = vaddq_f32(dotV, coef0); + + dotV = vtanhq_f32(dotV); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * tanhf(S->gamma * dot + S->coef0); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * tanhf(S->gamma * dot + S->coef0); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of sigmoidsvm group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c new file mode 100644 index 0000000..2c50961 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c @@ -0,0 +1,278 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f16.c + * Description: Maximum value of a absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMIN); + float16_t maxValue = F16_ABSMIN; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c new file mode 100644 index 0000000..7ddc9ae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c @@ -0,0 +1,264 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f32.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMax Absolute Maximum + + Computes the maximum value of absolute values of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + int32_t blkSize = blockSize; + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMIN); + float32_t maxValue = F32_ABSMIN; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u32(&curIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + do { + mve_pred16_t p = vctp32q(blkSize); + + vecSrc = vldrwq_z_f32((float32_t const *) pSrc, p); + vecSrc = vabsq_m(vuninitializedq_f32(), vecSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(vecSrc, curExtremValVec, p); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + /* Does TP detection works here ?? */ + indexVec = vidupq_wb_u32(&curIdx, 1); + + blkSize -= 4; + pSrc += 4; + } + while (blkSize > 0); + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c new file mode 100644 index 0000000..23a4e4e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c @@ -0,0 +1,96 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f64.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void arm_absmax_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabs(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c new file mode 100644 index 0000000..d1c225c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c @@ -0,0 +1,232 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f16.c + * Description: Maximum value of a absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMIN); + float16_t maxValue = F16_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmavq(maxValue, curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c new file mode 100644 index 0000000..485ccd5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c @@ -0,0 +1,229 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f32.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMIN); + float32_t maxValue = F32_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmavq(maxValue, curExtremValVec); + *pResult = maxValue; +} + + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c new file mode 100644 index 0000000..017c588 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c @@ -0,0 +1,91 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f64.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +void arm_absmax_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabs(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} + +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c new file mode 100644 index 0000000..9c3a86a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c @@ -0,0 +1,224 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q15.c + * Description: Maximum value of absolute values of a Q15 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + uint16x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMIN); + q15_t maxValue = Q15_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q15x8_t)curExtremValVec); + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c new file mode 100644 index 0000000..5610a8a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c @@ -0,0 +1,224 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q31.c + * Description: Maximum value of absolute values of a Q31 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + uint32x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMIN); + q31_t maxValue = Q31_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q31x4_t)curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c new file mode 100644 index 0000000..26e1813 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c @@ -0,0 +1,228 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q7.c + * Description: Maximum value of absolute values of a Q7 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + + +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + uint8x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMIN); + q7_t maxValue = Q7_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q7x16_t)curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c new file mode 100644 index 0000000..656fcf9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c @@ -0,0 +1,240 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q15.c + * Description: Maximum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_ABSMIN); + q15_t maxValue = Q15_ABSMIN; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + + extremIdxVal = vqabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c new file mode 100644 index 0000000..d3cfa3c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c @@ -0,0 +1,240 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q31.c + * Description: Maximum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_ABSMIN); + q31_t maxValue = Q31_ABSMIN; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + + extremIdxVal = vqabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c new file mode 100644 index 0000000..30595de --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c @@ -0,0 +1,298 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q7.c + * Description: Maximum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define MAX_BLKSZ_S8 (UINT8_MAX+1) + +static void arm_small_blk_absmax_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t extremValVec = vdupq_n_s8(Q7_ABSMIN); + q7_t maxValue = Q7_ABSMIN; + uint8x16_t indexVec; + uint8x16_t extremIdxVec; + mve_pred16_t p0; + uint8_t extremIdxArr[16]; + + indexVec = vidupq_u8(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp8q(blkCnt); + q7x16_t extremIdxVal = vld1q_z_s8(pSrc, p); + + extremIdxVal = vqabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u8(extremIdxArr, indexVec, p0); + + indexVec += 16; + pSrc += 16; + blkCnt -= 16; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u8(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u8(blockSize - 1), p0); + *pIndex = vminvq_u8(blockSize - 1, indexVec); + *pResult = maxValue; +} + +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= MAX_BLKSZ_S8) + { + arm_small_blk_absmax_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MIN; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= MAX_BLKSZ_S8) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_absmax_q7(curSrc, MAX_BLKSZ_S8, pResult, pIndex); + if (*pResult > curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += MAX_BLKSZ_S8; + totalSize -= MAX_BLKSZ_S8; + } + /* + * remainder + */ + arm_small_blk_absmax_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult > curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * MAX_BLKSZ_S8 + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c new file mode 100644 index 0000000..335f502 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c @@ -0,0 +1,280 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f16.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMAX); + float16_t minValue = F16_ABSMAX; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + p0 = vctp16q(blkCnt); + + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c new file mode 100644 index 0000000..521093a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c @@ -0,0 +1,283 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f32.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMin Absolute Minimum + + Computes the minimum value of absolute values of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMAX); + float32_t minValue = F32_ABSMAX; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u32((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + p0 = vctp32q(blkCnt); + + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c new file mode 100644 index 0000000..518651a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c @@ -0,0 +1,94 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f64.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void arm_absmin_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabs(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c new file mode 100644 index 0000000..1e90c91 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c @@ -0,0 +1,234 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f16.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMAX); + float16_t minValue = F16_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmavq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c new file mode 100644 index 0000000..20aca41 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c @@ -0,0 +1,230 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f32.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMAX); + float32_t minValue = F32_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmavq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} + +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c new file mode 100644 index 0000000..143271d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c @@ -0,0 +1,88 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f64.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +void arm_absmin_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabs(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} + +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c new file mode 100644 index 0000000..c6dd15e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c @@ -0,0 +1,226 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q15.c + * Description: Minimum value of absolute values of a Q15 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + uint16x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMAX); + q15_t minValue = Q15_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q15x8_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c new file mode 100644 index 0000000..90281a4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c @@ -0,0 +1,225 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q31.c + * Description: Minimum value of absolute values of a Q31 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + uint32x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMAX); + q31_t minValue = Q31_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q31x4_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c new file mode 100644 index 0000000..e0f712b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c @@ -0,0 +1,227 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q7.c + * Description: Minimum value of absolute values of a Q7 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + + +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + uint8x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMAX); + q7_t minValue = Q7_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q7x16_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c new file mode 100644 index 0000000..ef389ba --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c @@ -0,0 +1,273 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q15.c + * Description: Minimum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMAX); + q15_t minValue = Q15_ABSMAX; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u16(&startIdx, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u16(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c new file mode 100644 index 0000000..0f28026 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c @@ -0,0 +1,273 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q31.c + * Description: Minimum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMAX); + q31_t minValue = Q31_ABSMAX; + uint16_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u32(&startIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u32(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c new file mode 100644 index 0000000..99bb473 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c @@ -0,0 +1,326 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q7.c + * Description: Minimum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +#define MAX_BLKSZ_S8 (UINT8_MAX+1) + +static void arm_small_blk_absmin_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult, + uint32_t *pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMAX); + q7_t minValue = Q7_ABSMAX; + uint16_t idx = blockSize - 1; + uint8x16_t indexVec; + uint8x16_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u8(&startIdx, 1); + curExtremIdxVec = vdupq_n_u8(0); + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u8(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + vecSrc = vabsq(vecSrc); + + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + idx = vminvq_p_u8(idx, curExtremIdxVec, p0); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + + +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= MAX_BLKSZ_S8) + { + arm_small_blk_absmin_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MAX; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= MAX_BLKSZ_S8) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_absmin_q7(curSrc, MAX_BLKSZ_S8, pResult, pIndex); + if (*pResult < curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += MAX_BLKSZ_S8; + totalSize -= MAX_BLKSZ_S8; + } + /* + * remainder + */ + arm_small_blk_absmin_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult < curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * MAX_BLKSZ_S8 + curBlkPos; + *pResult = curBlkExtr; + } +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f16.c new file mode 100644 index 0000000..71be5f1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f16.c @@ -0,0 +1,125 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_accumulate_f16.c + * Description: accumulation value of a floating-point vector + * + * $Date: 14 July 2022 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup Accumulation Accumulation functions + + Calculates the accumulation of the input vector. Sum is defined as the addition of the elements in the vector. + The underlying algorithm is used: + + 
+ Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]);
+
+ + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Accumulation + @{ + */ + +/** + @brief accumulate value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult sum of values in input vector. + @return none + */ + +void arm_accumulate_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t sum = 0.0f16; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += (_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + /* Store result to destination */ + *pResult = sum ; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Accumulation group + */ + + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f32.c new file mode 100644 index 0000000..353ab17 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f32.c @@ -0,0 +1,213 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_accumulate_f32.c + * Description: Sum value of a floating-point vector + * + * $Date: 14 July 2022 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Accumulation + @{ + */ + +/** + @brief Accumulation value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult sum of values in input vector. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_accumulate_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + f32x4_t vecA; + f32x4_t vecSum; + uint32_t blkCnt; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + * and advance vector source and destination pointers + */ + vecA = vld1q_f32(pSrc); + pSrc += 4; + + vecSum = vaddq_f32(vecSum, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrc); + vecSum = vaddq_m(vecSum,vecSum, vecA, p0); + } + + sum = vecAddAcrossF32Mve(vecSum); + + /* Store result in destination buffer */ + *pResult = sum; +} + +#else + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_accumulate_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + + uint32_t blkCnt; /* Loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + inV = vld1q_f32(pSrc); + sumV = vaddq_f32(sumV, inV); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + /* Store the result to the destination */ + *pResult = sum; +} + +#else +void arm_accumulate_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + /* Store result to destination */ + *pResult = sum ; +} +#endif /* #if defined(ARM_MATH_NEON) */ + +#endif /* #if defined(ARM_MATH_MVEF) */ +/** + @} end of Accumulation group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f64.c new file mode 100644 index 0000000..25420ac --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_accumulate_f64.c @@ -0,0 +1,131 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_accumulate_f64.c + * Description: Accumulation value of a floating-point vector + * + * $Date: 14 July 2022 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Accumulation + @{ + */ + +/** + @brief Accumulation value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult sum of values in input vector. + @return none + */ +#if defined(ARM_MATH_NEON) && defined(__aarch64__) +void arm_accumulate_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + + /*Neon buffers*/ + float64x2_t vSum = vdupq_n_f64(0.0); + float64x2_t afterLoad ; + + float64_t sum = 0.; /* Temporary result storage */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize >> 1U; + + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + afterLoad = vld1q_f64(pSrc); + vSum = vaddq_f64(vSum, afterLoad); + + /* Decrement loop counter */ + blkCnt--; + + pSrc += 2; + } + sum = vaddvq_f64(vSum); + + /* Tail */ + blkCnt = blockSize & 1 ; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + /* Store result to destination */ + *pResult = sum; +} +#else +void arm_accumulate_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + /* Store result to destination */ + *pResult = sum; +} + +#endif + + +/** + @} end of Accumulation group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c new file mode 100644 index 0000000..4e223c7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c @@ -0,0 +1,144 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Entropy Entropy + + Computes the entropy of a distribution + + */ + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize) +{ + uint32_t blkCnt; + _Float16 accum=0.0f16,p; + + + blkCnt = blockSize; + + f16x8_t vSum = vdupq_n_f16(0.0f); + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + f16x8_t vecIn = vld1q(pSrcA); + + vSum = vaddq_f16(vSum, vmulq(vecIn, vlogq_f16(vecIn))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + blkCnt --; + } + + accum = vecAddAcrossF16Mve(vSum); + + /* Tail */ + blkCnt = blockSize & 0x7; + while(blkCnt > 0) + { + p = *pSrcA++; + accum += p * (_Float16)logf((float32_t)p); + + blkCnt--; + + } + + return (-accum); +} + +#else + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize) +{ + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * (_Float16)logf((float32_t)p); + + blkCnt--; + + } + + return(-accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Entropy group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c new file mode 100644 index 0000000..290e5c1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c @@ -0,0 +1,178 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t accum=0.0f,p; + + + blkCnt = blockSize; + + f32x4_t vSum = vdupq_n_f32(0.0f); + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + f32x4_t vecIn = vld1q(pSrcA); + + vSum = vaddq_f32(vSum, vmulq(vecIn, vlogq_f32(vecIn))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + blkCnt --; + } + + accum = vecAddAcrossF32Mve(vSum); + + /* Tail */ + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + p = *pSrcA++; + accum += p * logf(p); + + blkCnt--; + + } + + return (-accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum, p; + + float32x4_t accumV; + float32x2_t accumV2; + float32x4_t tmpV, tmpV2; + + pIn = pSrcA; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + tmpV = vld1q_f32(pIn); + pIn += 4; + + tmpV2 = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, tmpV, tmpV2); + + blkCnt--; + + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} + +#else +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Entropy group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c new file mode 100644 index 0000000..5cb2ef5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c @@ -0,0 +1,77 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Entropy + * @{ + */ + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize) +{ + const float64_t *pIn; + uint32_t blkCnt; + float64_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0; + + while(blkCnt > 0) + { + p = *pIn++; + + accum += p * log(p); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Entropy group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c new file mode 100644 index 0000000..6c291fe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c @@ -0,0 +1,156 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Kullback-Leibler Kullback-Leibler divergence + + Computes the Kullback-Leibler divergence between two distributions + + */ + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA,const float16_t * pSrcB,uint32_t blockSize) +{ + uint32_t blkCnt; + _Float16 accum, pA,pB; + + + blkCnt = blockSize; + + accum = 0.0f16; + + f16x8_t vSum = vdupq_n_f16(0.0f16); + blkCnt = blockSize >> 3; + while(blkCnt > 0) + { + f16x8_t vecA = vld1q(pSrcA); + f16x8_t vecB = vld1q(pSrcB); + f16x8_t vRatio; + + vRatio = vdiv_f16(vecB, vecA); + vSum = vaddq_f16(vSum, vmulq(vecA, vlogq_f16(vRatio))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt --; + } + + accum = vecAddAcrossF16Mve(vSum); + + blkCnt = blockSize & 7; + while(blkCnt > 0) + { + pA = *pSrcA++; + pB = *pSrcB++; + accum += pA * (_Float16)logf((float32_t)pB / (float32_t)pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA,const float16_t * pSrcB,uint32_t blockSize) +{ + const float16_t *pInA, *pInB; + uint32_t blkCnt; + _Float16 accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * (_Float16)logf((float32_t)pB / (float32_t)pA); + + blkCnt--; + + } + + return(-accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Kullback-Leibler group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c new file mode 100644 index 0000000..993e102 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c @@ -0,0 +1,197 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t accum, pA,pB; + + + blkCnt = blockSize; + + accum = 0.0f; + + f32x4_t vSum = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + f32x4_t vecA = vld1q(pSrcA); + f32x4_t vecB = vld1q(pSrcB); + f32x4_t vRatio; + + vRatio = vdiv_f32(vecB, vecA); + vSum = vaddq_f32(vSum, vmulq(vecA, vlogq_f32(vRatio))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt --; + } + + accum = vecAddAcrossF32Mve(vSum); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + pA = *pSrcA++; + pB = *pSrcB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" + +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + const float32_t *pInA, *pInB; + uint32_t blkCnt; + float32_t accum, pA,pB; + + float32x4_t accumV; + float32x2_t accumV2; + float32x4_t tmpVA, tmpVB,tmpV; + + pInA = pSrcA; + pInB = pSrcB; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + tmpVA = vld1q_f32(pInA); + pInA += 4; + + tmpVB = vld1q_f32(pInB); + pInB += 4; + + tmpV = vinvq_f32(tmpVA); + tmpVB = vmulq_f32(tmpVB, tmpV); + tmpVB = vlogq_f32(tmpVB); + + accumV = vmlaq_f32(accumV, tmpVA, tmpVB); + + blkCnt--; + + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB/pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + const float32_t *pInA, *pInB; + uint32_t blkCnt; + float32_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Kullback-Leibler group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c new file mode 100644 index 0000000..8bde9c2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + +/** + * @brief Kullback-Leibler + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, const float64_t * pSrcB, uint32_t blockSize) +{ + const float64_t *pInA, *pInB; + uint32_t blkCnt; + float64_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + + accum += pA * log(pB / pA); + + blkCnt--; + } + + return(-accum); +} + +/** + * @} end of Kullback-Leibler group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c new file mode 100644 index 0000000..08fb197 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c @@ -0,0 +1,88 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup LogSumExp LogSumExp + + LogSumExp optimizations to compute sum of probabilities with Gaussian distributions + + */ + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer) +{ + float16_t result; + arm_add_f16((float16_t*)pSrcA, (float16_t*)pSrcB, pTmpBuffer, blockSize); + + result = arm_logsumexp_f16(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c new file mode 100644 index 0000000..bb5d90f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c @@ -0,0 +1,72 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer) +{ + float32_t result; + arm_add_f32((float32_t*)pSrcA, (float32_t*)pSrcB, pTmpBuffer, blockSize); + + result = arm_logsumexp_f32(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c new file mode 100644 index 0000000..dc151f7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c @@ -0,0 +1,176 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math_f16.h" + +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize) +{ + float16_t maxVal; + const float16_t *pIn; + int32_t blkCnt; + _Float16 accum=0.0f16; + _Float16 tmp; + + + arm_max_no_idx_f16((float16_t *) in, blockSize, &maxVal); + + + blkCnt = blockSize; + pIn = in; + + + f16x8_t vSum = vdupq_n_f16(0.0f16); + blkCnt = blockSize >> 3; + while(blkCnt > 0) + { + f16x8_t vecIn = vld1q(pIn); + f16x8_t vecExp; + + vecExp = vexpq_f16(vsubq_n_f16(vecIn, maxVal)); + + vSum = vaddq_f16(vSum, vecExp); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pIn += 8; + blkCnt --; + } + + /* sum + log */ + accum = vecAddAcrossF16Mve(vSum); + + blkCnt = blockSize & 0x7; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += (_Float16)expf((float32_t)((_Float16)tmp - (_Float16)maxVal)); + blkCnt--; + + } + + accum = (_Float16)maxVal + (_Float16)logf((float32_t)accum); + + return (accum); +} + +#else +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize) +{ + _Float16 maxVal; + _Float16 tmp; + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + + } + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += (_Float16)expf((float32_t)((_Float16)tmp - (_Float16)maxVal)); + blkCnt--; + + } + accum = (_Float16)maxVal + (_Float16)logf((float32_t)accum); + + return(accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c new file mode 100644 index 0000000..8f0cc74 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c @@ -0,0 +1,281 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_math.h" + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + const float32_t *pIn; + int32_t blkCnt; + float32_t accum=0.0f; + float32_t tmp; + + + arm_max_no_idx_f32((float32_t *) in, blockSize, &maxVal); + + + blkCnt = blockSize; + pIn = in; + + + f32x4_t vSum = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + f32x4_t vecIn = vld1q(pIn); + f32x4_t vecExp; + + vecExp = vexpq_f32(vsubq_n_f32(vecIn, maxVal)); + + vSum = vaddq_f32(vSum, vecExp); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pIn += 4; + blkCnt --; + } + + /* sum + log */ + accum = vecAddAcrossF32Mve(vSum); + + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + + accum = maxVal + logf(accum); + + return (accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + float32_t tmp; + float32x4_t tmpV, tmpVb; + float32x4_t maxValV; + uint32x4_t idxV; + float32x4_t accumV; + float32x2_t accumV2; + + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum; + + pIn = in; + + blkCnt = blockSize; + + if (blockSize <= 3) + { + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + } + } + else + { + maxValV = vld1q_f32(pIn); + pIn += 4; + blkCnt = (blockSize - 4) >> 2; + + while(blkCnt > 0) + { + tmpVb = vld1q_f32(pIn); + pIn += 4; + + idxV = vcgtq_f32(tmpVb, maxValV); + maxValV = vbslq_f32(idxV, tmpVb, maxValV ); + + blkCnt--; + } + + accumV2 = vpmax_f32(vget_low_f32(maxValV),vget_high_f32(maxValV)); + accumV2 = vpmax_f32(accumV2,accumV2); + maxVal = vget_lane_f32(accumV2, 0) ; + + blkCnt = (blockSize - 4) & 3; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + } + + } + + + + maxValV = vdupq_n_f32(maxVal); + pIn = in; + accum = 0; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + + while(blkCnt > 0) + { + tmpV = vld1q_f32(pIn); + pIn += 4; + tmpV = vsubq_f32(tmpV, maxValV); + tmpV = vexpq_f32(tmpV); + accumV = vaddq_f32(accumV, tmpV); + + blkCnt--; + + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + + accum = maxVal + logf(accum); + + return(accum); +} +#else +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + float32_t tmp; + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + + } + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + accum = maxVal + logf(accum); + + return(accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of LogSumExp group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c new file mode 100644 index 0000000..3fb0512 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c @@ -0,0 +1,250 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f16.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MIN); + float16_t maxValue = F16_MIN; + uint32_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + float16_t tmp; + + + indexVec = vidupq_wb_u16(&curIdx, 1); + curExtremIdxVec = vdupq_n_u16(0); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u16(&curIdx, 1); + + pSrc += 8; + /* Decrement the loop counter */ + blkCnt--; + } + + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* Tail */ + blkCnt = blockSize & 7; + + while (blkCnt > 0) + { + /* Initialize tmp to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)maxValue < (_Float16)tmp) + { + /* Update the maximum value and it's index */ + maxValue = tmp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + +#else +void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if ((_Float16)out < (_Float16)maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if ((_Float16)out < (_Float16)maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if ((_Float16)out < (_Float16)maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c new file mode 100644 index 0000000..4856c46 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c @@ -0,0 +1,369 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f32.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + +/** + @defgroup Max Maximum + + Computes the maximum value of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MIN); + float32_t maxValue = F32_MIN; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + float32_t tmp; + + + indexVec = vidupq_wb_u32(&curIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u32(&curIdx, 1); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* Initialize tmp to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < tmp) + { + /* Update the maximum value and it's index */ + maxValue = tmp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + uint32x4_t maxIdx; + static const uint32_t indexInit[4]={4,5,6,7}; + static const uint32_t countVInit[4]={0,1,2,3}; + + uint32x4_t index; + uint32x4_t delta; + uint32x4_t countV; + uint32x2_t countV2; + + maxIdx = vdupq_n_u32(UINT_MAX); + delta = vdupq_n_u32(4); + index = vld1q_u32(indexInit); + countV = vld1q_u32(countVInit); + + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcgtq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmax_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmax_f32(outV2,outV2); + out = vget_lane_f32(outV2, 0); + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = vget_lane_u32(countV2,0); + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c new file mode 100644 index 0000000..66cfd34 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c @@ -0,0 +1,94 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f64.c + * Description: Maximum value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void arm_max_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c new file mode 100644 index 0000000..a7232da --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c @@ -0,0 +1,148 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f16.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MIN); + float16_t maxValue = F16_MIN; + float16_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vldrhq_f16(pSrc); + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + blkCnt --; + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)maxValue < (_Float16)newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blkCnt --; + } + + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + float16_t maxValue = F16_MIN; + float16_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)maxValue < (_Float16)newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c new file mode 100644 index 0000000..c578e6b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c @@ -0,0 +1,142 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f32.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MIN); + float32_t maxValue = F32_MIN; + float32_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + blkCnt --; + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blkCnt --; + } + + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + float32_t maxValue = F32_MIN; + float32_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c new file mode 100644 index 0000000..dcb7afb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f64.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +void arm_max_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult) +{ + float64_t maxValue = F64_MIN; + float64_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c new file mode 100644 index 0000000..063a5e3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c @@ -0,0 +1,146 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q15.c + * Description: Maximum value of a q15 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q15 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_max_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_MIN); + q15_t maxValue = Q15_MIN; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else +void arm_max_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c new file mode 100644 index 0000000..cffdd13 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c @@ -0,0 +1,146 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q31.c + * Description: Maximum value of a q31 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q31 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_max_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_MIN); + q31_t maxValue = Q31_MIN; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else +void arm_max_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c new file mode 100644 index 0000000..059acf5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c @@ -0,0 +1,147 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q7.c + * Description: Maximum value of a q7 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q7 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_max_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MIN); + q7_t maxValue = Q7_MIN; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c new file mode 100644 index 0000000..9f30ece --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c @@ -0,0 +1,205 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q15.c + * Description: Maximum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_MIN); + q15_t maxValue = Q15_MIN; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c new file mode 100644 index 0000000..d0665a4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c @@ -0,0 +1,206 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q31.c + * Description: Maximum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_MIN); + q31_t maxValue = Q31_MIN; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c new file mode 100644 index 0000000..377db4a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c @@ -0,0 +1,260 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q7.c + * Description: Maximum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +static void arm_small_blk_max_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t extremValVec = vdupq_n_s8(Q7_MIN); + q7_t maxValue = Q7_MIN; + uint8x16_t indexVec; + uint8x16_t extremIdxVec; + mve_pred16_t p0; + uint8_t extremIdxArr[16]; + + indexVec = vidupq_u8(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp8q(blkCnt); + q7x16_t extremIdxVal = vld1q_z_s8(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u8(extremIdxArr, indexVec, p0); + + indexVec += 16; + pSrc += 16; + blkCnt -= 16; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u8(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u8(blockSize - 1), p0); + *pIndex = vminvq_u8(blockSize - 1, indexVec); + *pResult = maxValue; +} + +void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + const uint16_t sub_blk_sz = UINT8_MAX + 1; + + if (totalSize <= sub_blk_sz) + { + arm_small_blk_max_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MIN; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= sub_blk_sz) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_max_q7(curSrc, sub_blk_sz, pResult, pIndex); + if (*pResult > curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += sub_blk_sz; + totalSize -= sub_blk_sz; + } + /* + * remainder + */ + arm_small_blk_max_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult > curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * sub_blk_sz + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Max group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c new file mode 100644 index 0000000..19ded7d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c @@ -0,0 +1,156 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f16.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup mean Mean + + Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. + The underlying algorithm is used: + + 
+      Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+
+ + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f16); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + sumVec = vaddq_m_f16(sumVec, sumVec, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + *pResult = (_Float16)vecAddAcrossF16Mve(sumVec) / (_Float16) blockSize; +} + + +#else + +void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += (_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = ((_Float16)sum / (_Float16)blockSize); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of mean group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c new file mode 100644 index 0000000..99c6dbe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c @@ -0,0 +1,202 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f32.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t sum = 0.0f; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + sumVec = vaddq_f32(sumVec, vecSrc); + + blkCnt --; + pSrc += 4; + } + + sum = vecAddAcrossF32Mve(sumVec); + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum / (float32_t) blockSize; +} + + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + + uint32_t blkCnt; /* Loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + inV = vld1q_f32(pSrc); + sumV = vaddq_f32(sumV, inV); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = sum / (float32_t) blockSize; +} +#else +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of mean group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c new file mode 100644 index 0000000..cb91116 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f64.c + * Description: Mean value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +void arm_mean_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +} + +/** + @} end of mean group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c new file mode 100644 index 0000000..0eefbdb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c @@ -0,0 +1,160 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q15.c + * Description: Mean value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.15 format and is accumulated in a 32-bit + accumulator in 17.15 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q31_t sum = 0L; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* + * sum lanes + */ + sum = vaddvaq(sum, vecSrc); + + blkCnt--; + pSrc += 8; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +} +#else +void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q15x2_ia (&pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + in = read_q15x2_ia (&pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c new file mode 100644 index 0000000..1b95ce5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c @@ -0,0 +1,153 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q31.c + * Description: Mean value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format and is accumulated in a 64-bit + accumulator in 33.31 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.31 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sum = 0LL; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + + vecSrc = vldrwq_s32(pSrc); + /* + * sum lanes + */ + sum = vaddlvaq(sum, vecSrc); + + blkCnt --; + pSrc += 4; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + blkCnt --; + } + + *pResult = arm_div_int64_to_int32(sum, blockSize); +} +#else +void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q31_t) (sum / blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c new file mode 100644 index 0000000..5ac4517 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c @@ -0,0 +1,157 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q7.c + * Description: Mean value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format and is accumulated in a 32-bit + accumulator in 25.7 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q31_t sum = 0L; + + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + /* + * sum lanes + */ + sum = vaddvaq(sum, vecSrc); + + blkCnt--; + pSrc += 16; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +} +#else +void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q7x4_ia (&pSrc); + sum += ((in << 24U) >> 24U); + sum += ((in << 16U) >> 24U); + sum += ((in << 8U) >> 24U); + sum += (in >> 24U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c new file mode 100644 index 0000000..4e08799 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c @@ -0,0 +1,244 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f16.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MAX); + float16_t minValue = F16_MAX; + uint32_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); pSrcVec += 8; + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else + +void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if ((_Float16)out > (_Float16)minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if ((_Float16)out > (_Float16)minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if ((_Float16)out > (_Float16)minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c new file mode 100644 index 0000000..b581473 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c @@ -0,0 +1,367 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f32.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @defgroup Min Minimum + + Computes the minimum value of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MAX); + float32_t minValue = F32_MAX; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + float32_t tmp; + mve_pred16_t p0; + + indexVec = vidupq_u32((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (float32_t const *) pSrc; + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the minimum value */ + if (minValue > tmp) + { + /* Update the minimum value and it's index */ + minValue = tmp; + idx = blockSize - blkCnt; + } + blkCnt--; + } + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + static const uint32_t indexInit[4]={4,5,6,7}; + static const uint32_t countVInit[4]={0,1,2,3}; + uint32x4_t maxIdx; + uint32x4_t index; + uint32x4_t delta; + uint32x4_t countV; + uint32x2_t countV2; + + maxIdx = vdupq_n_u32(UINT_MAX); + delta = vdupq_n_u32(4); + index = vld1q_u32(indexInit); + countV = vld1q_u32(countVInit); + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcltq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmin_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmin_f32(outV2,outV2); + out = vget_lane_f32(outV2,0); + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = vget_lane_u32(countV2,0); + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c new file mode 100644 index 0000000..525470f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c @@ -0,0 +1,94 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f64.c + * Description: Minimum value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void arm_min_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c new file mode 100644 index 0000000..a2a64db --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c @@ -0,0 +1,148 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f16.c + * Description: Minimum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MAX); + float16_t minValue = F16_MAX; + float16_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vldrhq_f16(pSrc); + /* + * update per-lane min. + */ + curExtremValVec = vminnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + blkCnt --; + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)minValue > (_Float16)newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blkCnt --; + } + + *pResult = minValue; +} + +#else + +void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + float16_t minValue = F16_MAX; + float16_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)minValue > (_Float16)newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c new file mode 100644 index 0000000..eafae73 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c @@ -0,0 +1,142 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f32.c + * Description: Minimum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MAX); + float32_t minValue = F32_MAX; + float32_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * update per-lane min. + */ + curExtremValVec = vminnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + blkCnt --; + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blkCnt --; + } + + *pResult = minValue; +} + +#else + +void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + float32_t minValue = F32_MAX; + float32_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c new file mode 100644 index 0000000..5e3317e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f64.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +void arm_min_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult) +{ + float64_t minValue = F64_MAX; + float64_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c new file mode 100644 index 0000000..f588e70 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c @@ -0,0 +1,146 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q15.c + * Description: Minimum value of a q15 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q15 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_min_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_MAX); + q15_t minValue = Q15_MAX; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c new file mode 100644 index 0000000..b00a5ba --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c @@ -0,0 +1,145 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q31.c + * Description: Minimum value of a q31 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q31 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +void arm_min_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_MAX); + q31_t minValue = Q31_MAX; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c new file mode 100644 index 0000000..e0a8396 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c @@ -0,0 +1,145 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q7.c + * Description: Minimum value of a q7 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q7 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_min_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MAX); + q7_t minValue = Q7_MAX; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c new file mode 100644 index 0000000..3a4d99e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c @@ -0,0 +1,207 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q15.c + * Description: Minimum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_MAX); + q15_t minValue = Q15_MAX; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + /* Get min value across the vector */ + minValue = vminvq(minValue, extremValVec); + + /* set index for lower values to min possible index */ + p0 = vcmpleq(extremValVec, minValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = minValue; + +} +#else +void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c new file mode 100644 index 0000000..7c889e5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c @@ -0,0 +1,207 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q31.c + * Description: Minimum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_MAX); + q31_t minValue = Q31_MAX; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get min value across the vector */ + minValue = vminvq(minValue, extremValVec); + + /* set index for lower values to min possible index */ + p0 = vcmpleq(extremValVec, minValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = minValue; +} + +#else +void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c new file mode 100644 index 0000000..6d8451b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c @@ -0,0 +1,288 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q7.c + * Description: Minimum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +static void arm_small_blk_min_q7( + const q7_t * pSrc, + uint8_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MAX); + q7_t minValue = Q7_MAX,temp; + uint32_t idx = blockSize; + uint8x16_t indexVec; + uint8x16_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u8((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u8(0); + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + pSrc += 16; + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u8(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + temp = *pSrc++; + + /* compare for the minimum value */ + if (minValue > temp) + { + /* Update the minimum value and it's index */ + minValue = temp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= UINT8_MAX) + { + arm_small_blk_min_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MAX; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= UINT8_MAX) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_min_q7(curSrc, UINT8_MAX, pResult, pIndex); + if (*pResult < curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += UINT8_MAX; + totalSize -= UINT8_MAX; + } + /* + * remainder + */ + arm_small_blk_min_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult < curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * UINT8_MAX + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c new file mode 100644 index 0000000..20c8083 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c @@ -0,0 +1,207 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f16.c + * Description: Half floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two half floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) + +#if defined(ARM_MATH_MVE_FLOAT16) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) + +{ + float16x8_t vecA, vecB; + float16x8_t vecSum; + uint32_t blkCnt; + _Float16 sum = 0.0f16; + vecSum = vdupq_n_f16(0.0f16); + + blkCnt = (blockSize) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcA); + pSrcA += 8; + + vecB = vld1q(pSrcB); + pSrcB += 8; + + vecA = vsubq(vecA, vecB); + + vecSum = vfmaq(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = (blockSize) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + + vecA = vsubq(vecA, vecB); + vecSum = vfmaq_m(vecSum, vecA, vecA, p0); + } + + sum = vecAddAcrossF16Mve(vecSum); + + /* Store result in destination buffer */ + *result = (_Float16)sum / (_Float16)blockSize; + +} + +#endif + + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (!defined(ARM_MATH_MVE_FLOAT16)) || defined(ARM_MATH_AUTOVECTORIZE) + + + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 inA, inB; + _Float16 sum = 0.0f16; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + blkCnt = (blockSize) >> 3; + + + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = (_Float16)sum / (_Float16)blockSize; +} + +#endif /* end of test for vector instruction availability */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MSE group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c new file mode 100644 index 0000000..622abb5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c @@ -0,0 +1,251 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f32.c + * Description: Floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) + +#if defined(ARM_MATH_MVEF) +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + float32x4_t vecA, vecB; + float32x4_t vecSum; + uint32_t blkCnt; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcA); + pSrcA += 4; + + vecB = vld1q(pSrcB); + pSrcB += 4; + + vecA = vsubq(vecA, vecB); + + vecSum = vfmaq(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = (blockSize) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + + vecA = vsubq(vecA, vecB); + vecSum = vfmaq_m(vecSum, vecA, vecA, p0); + } + + sum = vecAddAcrossF32Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum / blockSize; + +} + +#endif + +#if defined(ARM_MATH_NEON) +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + float32x4_t vecA, vecB; + float32x4_t vecSum; + uint32_t blkCnt; + float32_t inA, inB; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0.0f); +#endif + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + while (blkCnt > 0U) + { + vecA = vld1q_f32(pSrcA); + pSrcA += 4; + + vecB = vld1q_f32(pSrcB); + pSrcB += 4; + + vecA = vsubq_f32(vecA, vecB); + + vecSum = vfmaq_f32(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(vecSum), vget_high_f32(vecSum))); +#else + tmp = vpadd_f32(vget_low_f32(vecSum), vget_high_f32(vecSum)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + +#endif + + blkCnt = (blockSize) & 3; + while (blkCnt > 0U) + { + /* Calculate dot product and store result in a temporary buffer. */ + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; + +} +#endif + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + + +#if (!defined(ARM_MATH_MVEF) && !defined(ARM_MATH_NEON)) || defined(ARM_MATH_AUTOVECTORIZE) + + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + float32_t inA, inB; + float32_t sum = 0.0f; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; +} + +#endif /* end of test for vector instruction availability */ + +/** + @} end of MSE group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c new file mode 100644 index 0000000..d63674b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c @@ -0,0 +1,114 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f64.c + * Description: Double floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two double floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + + + + + +void arm_mse_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + float64_t inA, inB; + float64_t sum = 0.0; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + blkCnt = (blockSize) >> 1; + + + while (blkCnt > 0U) + { + + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 1; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; +} + + +/** + @} end of MSE group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c new file mode 100644 index 0000000..3412a4f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c @@ -0,0 +1,179 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q15.c + * Description: Mean square error between two Q15 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrcA,vecSrcB; + q63_t sum = 0LL; + + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vmlaldavaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 8; + pSrcB += 8; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vmlaldavaq_p(sum, vecSrcA, vecSrcA, p0); + } + + + + *pResult = (q15_t) __SSAT((q31_t) (sum / blockSize)>>13, 16); +} +#else +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t inA,inB; /* Temporary variable to store input value */ + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q15 format */ + *pResult = (q15_t) __SSAT((q31_t) (sum / blockSize)>>13, 16); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c new file mode 100644 index 0000000..f89a768 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c @@ -0,0 +1,180 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q31.c + * Description: Mean square error between two Q31 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q31 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrcA,vecSrcB; + q63_t sum = 0LL; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vrmlaldavhaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 4; + pSrcB += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vrmlaldavhaq_p(sum, vecSrcA, vecSrcA, p0); + } + + + *pResult = (q31_t) ((sum / blockSize)>>21); + +} +#else +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + + q31_t inA32,inB32; /* Temporary variable to store packed input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q31 format */ + *pResult = (q31_t) ((sum / blockSize)>>15); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c new file mode 100644 index 0000000..fb28d90 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c @@ -0,0 +1,183 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q7.c + * Description: Mean square error between two Q7 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup MSE Mean Square Error + + Calculates the mean square error between two vectors. + + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrcA,vecSrcB; + q31_t sum = 0LL; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vmladavaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 16; + pSrcB += 16; + } + + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vmladavaq_p(sum, vecSrcA, vecSrcA, p0); + } + + *pResult = (q7_t) __SSAT((q15_t) (sum / blockSize)>>5, 8); +} +#else +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t inA,inB; /* Temporary variable to store input value */ + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q7 format */ + *pResult = (q7_t) __SSAT((q15_t) (sum / blockSize)>>5, 8);; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c new file mode 100644 index 0000000..f9833c0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c @@ -0,0 +1,156 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f16.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f); + + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + /* + * sum lanes + */ + sumVec = vfmaq_m(sumVec, vecSrc, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + *pResult = vecAddAcrossF16Mve(sumVec); +} +#else + +void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of power group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c new file mode 100644 index 0000000..ec07058 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c @@ -0,0 +1,233 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f32.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup power Power + + Calculates the sum of the squares of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + + Since the result is not divided by the length, those functions are in fact computing + something which is more an energy than a power. + + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t sum = 0.0f; + float32_t in; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + /* + * sum lanes + */ + sumVec = vfmaq(sumVec, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + sum = vecAddAcrossF32Mve(sumVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result to the destination */ + *pResult = sum; +} +#else +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of power group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c new file mode 100644 index 0000000..d2e1e03 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c @@ -0,0 +1,81 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f64.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +void arm_power_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + float64_t in; /* Temporary variable to store input value */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} + +/** + @} end of power group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c new file mode 100644 index 0000000..1cb3845 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c @@ -0,0 +1,181 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q15.c + * Description: Sum of the squares of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 34.30 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q63_t sum = 0LL; + q15_t in; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* + * sum lanes + */ + sum = vmlaldavaq(sum, vecSrc, vecSrc); + + blkCnt --; + pSrc += 8; + } + + /* + * tail + */ + blkCnt = blockSize & 0x7; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 34.30 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c new file mode 100644 index 0000000..db83d3b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c @@ -0,0 +1,169 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q31.c + * Description: Sum of the squares of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format. + Intermediate multiplication yields a 2.62 format, and this + result is truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + With 15 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 16.48 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sum = 0LL; + q31_t in; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrc); + /* + * sum lanes + */ + sum = vrmlaldavhaq(sum, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 8; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = asrl(sum, 6); +} +#else +void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and store result in a temporary variable sum, providing 15 guard bits. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store results in 16.48 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c new file mode 100644 index 0000000..7f74aa2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c @@ -0,0 +1,184 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q7.c + * Description: Sum of the squares of the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format. + Intermediate multiplication yields a 2.14 format, and this + result is added without saturation to an accumulator in 18.14 format. + With 17 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 18.14 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q31_t sum = 0LL; + q7_t in; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + /* + * sum lanes + */ + sum = vmladavaq(sum, vecSrc, vecSrc); + + blkCnt--; + pSrc += 16; + } + + /* + * tail + */ + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ + q31_t in1, in2; /* Temporary variables to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q7x4_ia (&pSrc); + + in1 = __SXTB16(__ROR(in32, 8)); + in2 = __SXTB16(in32); + + /* calculate power and accumulate to accumulator */ + sum = __SMLAD(in1, in1, sum); + sum = __SMLAD(in2, in2, sum); +#else + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 18.14 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c new file mode 100644 index 0000000..e2c878c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c @@ -0,0 +1,140 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_f16.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t pow = 0.0f; + + arm_power_f16(pSrc, blockSize, &pow); + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f16((_Float16)pow / (_Float16) blockSize, pResult); +} +#else + +void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + arm_sqrt_f16((_Float16)sum / (_Float16) blockSize, pResult); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RMS group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c new file mode 100644 index 0000000..7dadc34 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c @@ -0,0 +1,196 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_f32.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t pow = 0.0f; + + arm_power_f32(pSrc, blockSize, &pow); + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f32(pow / (float32_t) blockSize, pResult); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#else +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c new file mode 100644 index 0000000..2ed47f6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c @@ -0,0 +1,153 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q15.c + * Description: Root Mean Square of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q63_t pow = 0.0f; + q15_t normalizedPower; + + arm_power_q15(pSrc, blockSize, &pow); + + normalizedPower=__SSAT((pow / (q63_t) blockSize) >> 15,16); + arm_sqrt_q15(normalizedPower, pResult); +} +#else +void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Truncating and saturating the accumulator to 1.15 format */ + /* Store result in destination */ + arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of RMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c new file mode 100644 index 0000000..f334db8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c @@ -0,0 +1,145 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q31.c + * Description: Root Mean Square of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, and intermediate multiplication + yields a 2.62 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a single guard bit. + There is no saturation on intermediate additions. + If the accumulator overflows, it wraps around and distorts the result. + In order to avoid overflows completely, the input signal must be scaled down by + log2(blockSize) bits, as a total of blockSize additions are performed internally. + Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q63_t pow = 0.0f; + q31_t normalizedPower; + arm_power_q31(pSrc, blockSize, &pow); + + normalizedPower=clip_q63_to_q31((pow / (q63_t) blockSize) >> 17); + arm_sqrt_q31(normalizedPower, pResult); + +} + +#else +void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + uint64_t sum = 0; /* Temporary result storage (can get never negative. changed type from q63 to uint64 */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */ + /* Compute Rms and store result in destination vector */ + arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of RMS group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c new file mode 100644 index 0000000..b941f24 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c @@ -0,0 +1,71 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f16.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t var; + arm_var_f16(pSrc,blockSize,&var); + arm_sqrt_f16(var, pResult); +} + +/** + @} end of STD group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c new file mode 100644 index 0000000..ea60d3c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c @@ -0,0 +1,87 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f32.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup STD Standard deviation + + Calculates the standard deviation of the elements in the input vector. + + The float implementation is relying on arm_var_f32 which is using a two-pass algorithm + to avoid problem of numerical instabilities and cancellation errors. + + Fixed point versions are using the standard textbook algorithm since the fixed point + numerical behavior is different from the float one. + + Algorithm for fixed point versions is summarized below: + + + 
+      Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+
+      sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+      sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t var; + arm_var_f32(pSrc,blockSize,&var); + arm_sqrt_f32(var, pResult); +} + +/** + @} end of STD group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c new file mode 100644 index 0000000..a193f57 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c @@ -0,0 +1,63 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f64.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t var; + arm_var_f64(pSrc,blockSize,&var); + *pResult = sqrt(var); +} + +/** + @} end of STD group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c new file mode 100644 index 0000000..4e15a85 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c @@ -0,0 +1,177 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q15.c + * Description: Standard deviation of an array of Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t var=0; + + arm_var_q15(pSrc, blockSize, &var); + arm_sqrt_q15(var,pResult); +} +#else +void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += (in * in); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + /* Compute standard deviation and store result in destination */ + arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of STD group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c new file mode 100644 index 0000000..3036a2b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c @@ -0,0 +1,163 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q31.c + * Description: Standard deviation of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult standard deviation value returned here. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t var=0; + + arm_var_q31(pSrc, blockSize, &var); + arm_sqrt_q31(var, pResult); +} +#else +void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Accumulator */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute standard deviation and store result in destination */ + arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of STD group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c new file mode 100644 index 0000000..8700428 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c @@ -0,0 +1,213 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f16.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + + +void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f16); + float16_t fMean; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + arm_mean_f16(pSrc, blockSize, &fMean); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + /* + * sum lanes + */ + vecSrc = vsubq_m(vuninitializedq_f16(), vecSrc, fMean, p); + sumVec = vfmaq_m(sumVec, vecSrc, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + /* Variance */ + *pResult = (_Float16)vecAddAcrossF16Mve(sumVec) / (_Float16) (blockSize - 1.0f16); +} +#else + +void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary result storage */ + _Float16 fSum = 0.0f; + _Float16 fMean, fValue; + const float16_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += (_Float16)*pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = (_Float16)sum / (_Float16) blockSize; + + pInput = pSrc; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = (_Float16)fSum / ((_Float16)blockSize - 1.0f16); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of variance group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c new file mode 100644 index 0000000..69ab060 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c @@ -0,0 +1,297 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f32.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup variance Variance + + Calculates the variance of the elements in the input vector. + The underlying algorithm used is the direct method sometimes referred to as the two-pass method: + + 
+      Result = sum(element - meanOfElements)^2) / numElement - 1
+
+      meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t fMean; + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + arm_mean_f32(pSrc, blockSize, &fMean); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * sum lanes + */ + vecSrc = vsubq(vecSrc, fMean); + sumVec = vfmaq(sumVec, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + + sum = vecAddAcrossF32Mve(sumVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + in = *pSrc++ - fMean; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = sum / (float32_t) (blockSize - 1); +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t mean; + + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + float32x4_t avg; + + arm_mean_f32(pSrc,blockSize,&mean); + avg = vdupq_n_f32(mean); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + inV = vsubq_f32(inV, avg); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = sum / (float32_t)(blockSize - 1.0f); + +} + +#else +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t fSum = 0.0f; + float32_t fMean, fValue; + const float32_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float32_t) blockSize; + + pInput = pSrc; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float32_t)(blockSize - 1.0f); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of variance group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c new file mode 100644 index 0000000..229db63 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c @@ -0,0 +1,104 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f64.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +void arm_var_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + float64_t fSum = 0.; + float64_t fMean, fValue; + const float64_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float64_t) blockSize; + + pInput = pSrc; + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float64_t)(blockSize - 1.); +} + +/** + @} end of variance group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c new file mode 100644 index 0000000..9c78d34 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c @@ -0,0 +1,234 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q15.c + * Description: Variance of an array of Q15 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q63_t sumOfSquares = 0LL; + q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */ + q63_t sum = 0LL; + q15_t in; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */ + /* Compute Sum of squares of the input samples + * and then store the result in a temporary variable, sumOfSquares. */ + + sumOfSquares = vmlaldavaq_s16(sumOfSquares, vecSrc, vecSrc); + sum = vaddvaq_s16(sum, vecSrc); + + blkCnt --; + pSrc += 8; + } + + /* Tail */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (ARM_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares of the input samples + * and then store the result in a temporary variable, meanOfSquares. */ + meanOfSquares = arm_div_int64_to_int32(sumOfSquares, (blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = arm_div_int64_to_int32((q63_t)sum * sum, (q31_t)(blockSize * (blockSize - 1U))); + + /* mean of the squares minus the square of the mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15; +} +#else +void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (ARM_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of variance group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c new file mode 100644 index 0000000..025cc56 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c @@ -0,0 +1,218 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q31.c + * Description: Variance of an array of Q31 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + and as a consequence has only 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sumOfSquares = 0LL; + q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */ + q63_t sum = 0LL; + q31_t in; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrc); + /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */ + /* Compute Sum of squares of the input samples + * and then store the result in a temporary variable, sumOfSquares. */ + + /* downscale */ + vecSrc = vshrq(vecSrc, 8); + sumOfSquares = vmlaldavaq(sumOfSquares, vecSrc, vecSrc); + sum = vaddlvaq(sum, vecSrc); + + blkCnt --; + pSrc += 4; + } + + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares of the input samples + * and then store the result in a temporary variable, meanOfSquares. */ + meanOfSquares = sumOfSquares / (q63_t) (blockSize - 1U); + + /* Compute square of mean */ + squareOfMean = sum * sum / (q63_t) (blockSize * (blockSize - 1U)); + + /* Compute standard deviation and then store the result to the destination */ + *pResult = asrl(meanOfSquares - squareOfMean, 15U); +} +#else +void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute variance and store result in destination */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} +#endif +/** + @} end of variance group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c new file mode 100644 index 0000000..9a1aa6a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c @@ -0,0 +1,278 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_barycenter_f16.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSupport + */ + +/** + @defgroup barycenter Barycenter + + Barycenter of weighted vectors + */ + +/** + @addtogroup barycenter + @{ + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_barycenter_f16(const float16_t *in, + const float16_t *weights, + float16_t *out, + uint32_t nbVectors, + uint32_t vecDim) +{ + const float16_t *pIn, *pW; + const float16_t *pIn1, *pIn2, *pIn3, *pIn4; + float16_t *pOut; + uint32_t blkCntVector, blkCntSample; + float16_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + + arm_fill_f16(0.0f, out, vecDim); + + + /* Sum */ + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while (blkCntVector > 0) + { + f16x8_t outV, inV1, inV2, inV3, inV4; + float16_t w1, w2, w3, w4; + + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += (_Float16)w1 + (_Float16)w2 + (_Float16)w3 + (_Float16)w4; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) { + outV = vld1q((const float16_t *) pOut); + inV1 = vld1q(pIn1); + inV2 = vld1q(pIn2); + inV3 = vld1q(pIn3); + inV4 = vld1q(pIn4); + outV = vfmaq(outV, inV1, w1); + outV = vfmaq(outV, inV2, w2); + outV = vfmaq(outV, inV3, w3); + outV = vfmaq(outV, inV4, w4); + vst1q(pOut, outV); + + pOut += 8; + pIn1 += 8; + pIn2 += 8; + pIn3 += 8; + pIn4 += 8; + + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) { + *pOut = (_Float16)*pOut + (_Float16)*pIn1++ * (_Float16)w1; + *pOut = (_Float16)*pOut + (_Float16)*pIn2++ * (_Float16)w2; + *pOut = (_Float16)*pOut + (_Float16)*pIn3++ * (_Float16)w3; + *pOut = (_Float16)*pOut + (_Float16)*pIn4++ * (_Float16)w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3 * vecDim; + pIn2 += 3 * vecDim; + pIn3 += 3 * vecDim; + pIn4 += 3 * vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while (blkCntVector > 0) + { + f16x8_t inV, outV; + + pOut = out; + w = *pW++; + accum += (_Float16)w; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) + { + outV = vld1q_f16(pOut); + inV = vld1q_f16(pIn); + outV = vfmaq(outV, inV, w); + vst1q_f16(pOut, outV); + pOut += 8; + pIn += 8; + + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) + { + *pOut = (_Float16)*pOut + (_Float16)*pIn++ * (_Float16)w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f16 / (_Float16)accum; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) + { + f16x8_t tmp; + + tmp = vld1q((const float16_t *) pOut); + tmp = vmulq(tmp, accum); + vst1q(pOut, tmp); + pOut += 8; + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) + { + *pOut = (_Float16)*pOut * (_Float16)accum; + pOut++; + blkCntSample--; + } +} +#else +void arm_barycenter_f16(const float16_t *in, const float16_t *weights, float16_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float16_t *pIn,*pW; + float16_t *pOut; + uint32_t blkCntVector,blkCntSample; + float16_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f16; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f16; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += (_Float16)w; + + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = (_Float16)*pOut + (_Float16)*pIn++ * (_Float16)w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = (_Float16)*pOut / (_Float16)accum; + pOut++; + blkCntSample--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of barycenter group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c new file mode 100644 index 0000000..e941cbd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c @@ -0,0 +1,419 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_barycenter_f32.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" +#include +#include + + +/** + @ingroup barycenter + @{ + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_barycenter_f32(const float32_t *in, + const float32_t *weights, + float32_t *out, + uint32_t nbVectors, + uint32_t vecDim) +{ + const float32_t *pIn, *pW; + const float32_t *pIn1, *pIn2, *pIn3, *pIn4; + float32_t *pOut; + uint32_t blkCntVector, blkCntSample; + float32_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + + arm_fill_f32(0.0f, out, vecDim); + + + /* Sum */ + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while (blkCntVector > 0) + { + f32x4_t outV, inV1, inV2, inV3, inV4; + float32_t w1, w2, w3, w4; + + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += w1 + w2 + w3 + w4; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) { + outV = vld1q((const float32_t *) pOut); + inV1 = vld1q(pIn1); + inV2 = vld1q(pIn2); + inV3 = vld1q(pIn3); + inV4 = vld1q(pIn4); + outV = vfmaq(outV, inV1, w1); + outV = vfmaq(outV, inV2, w2); + outV = vfmaq(outV, inV3, w3); + outV = vfmaq(outV, inV4, w4); + vst1q(pOut, outV); + + pOut += 4; + pIn1 += 4; + pIn2 += 4; + pIn3 += 4; + pIn4 += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) { + *pOut = *pOut + *pIn1++ * w1; + *pOut = *pOut + *pIn2++ * w2; + *pOut = *pOut + *pIn3++ * w3; + *pOut = *pOut + *pIn4++ * w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3 * vecDim; + pIn2 += 3 * vecDim; + pIn3 += 3 * vecDim; + pIn4 += 3 * vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while (blkCntVector > 0) + { + f32x4_t inV, outV; + + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV = vld1q_f32(pIn); + outV = vfmaq(outV, inV, w); + vst1q_f32(pOut, outV); + pOut += 4; + pIn += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f / accum; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) + { + f32x4_t tmp; + + tmp = vld1q((const float32_t *) pOut); + tmp = vmulq(tmp, accum); + vst1q(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) + { + *pOut = *pOut * accum; + pOut++; + blkCntSample--; + } +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" +void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float32_t *pIn,*pW, *pIn1, *pIn2, *pIn3, *pIn4; + float32_t *pOut; + uint32_t blkCntVector,blkCntSample; + float32_t accum, w,w1,w2,w3,w4; + + float32x4_t tmp, inV,outV, inV1, inV2, inV3, inV4; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + tmp = vdupq_n_f32(0.0f); + pOut = out; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + vst1q_f32(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while(blkCntVector > 0) + { + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += w1 + w2 + w3 + w4; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV1 = vld1q_f32(pIn1); + inV2 = vld1q_f32(pIn2); + inV3 = vld1q_f32(pIn3); + inV4 = vld1q_f32(pIn4); + outV = vmlaq_n_f32(outV,inV1,w1); + outV = vmlaq_n_f32(outV,inV2,w2); + outV = vmlaq_n_f32(outV,inV3,w3); + outV = vmlaq_n_f32(outV,inV4,w4); + vst1q_f32(pOut, outV); + pOut += 4; + pIn1 += 4; + pIn2 += 4; + pIn3 += 4; + pIn4 += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn1++ * w1; + *pOut = *pOut + *pIn2++ * w2; + *pOut = *pOut + *pIn3++ * w3; + *pOut = *pOut + *pIn4++ * w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3*vecDim; + pIn2 += 3*vecDim; + pIn3 += 3*vecDim; + pIn4 += 3*vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV = vld1q_f32(pIn); + outV = vmlaq_n_f32(outV,inV,w); + vst1q_f32(pOut, outV); + pOut += 4; + pIn += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f / accum; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + tmp = vld1q_f32(pOut); + tmp = vmulq_n_f32(tmp,accum); + vst1q_f32(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut * accum; + pOut++; + blkCntSample--; + } + +} +#else +void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float32_t *pIn,*pW; + float32_t *pOut; + uint32_t blkCntVector,blkCntSample; + float32_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = *pOut / accum; + pOut++; + blkCntSample--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of barycenter group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c new file mode 100644 index 0000000..05edb29 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c @@ -0,0 +1,1043 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitonic_sort_f32.c + * Description: Floating point bitonic sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h" + + +#if !defined(ARM_MATH_NEON) + +static void arm_bitonic_sort_core_f32(float32_t *pSrc, uint32_t n, uint8_t dir) +{ + uint32_t step; + uint32_t k, j; + float32_t *leftPtr, *rightPtr; + float32_t temp; + + step = n>>1; + leftPtr = pSrc; + rightPtr = pSrc+n-1; + + for(k=0; k *rightPtr)) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; // Move right + rightPtr--; // Move left + } + + // Merge + for(step=(n>>2); step>0; step/=2) + { + for(j=0; j *rightPtr) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; + rightPtr++; + } + } + } +} +#endif + +#if defined(ARM_MATH_NEON) + + +static float32x4x2_t arm_bitonic_resort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + /* Start with two vectors: + * +---+---+---+---+ + * | a | b | c | d | + * +---+---+---+---+ + * +---+---+---+---+ + * | e | f | g | h | + * +---+---+---+---+ + * All the elements of the first are guaranteed to be less than or equal to + * all of the elements in the second, and both vectors are bitonic. + * We need to perform these operations to completely sort both lists: + * vminmax([abcd],[efgh]) + * vminmax([acbd],[egfh]) + */ + vtrn128_64q(a, b); + /* +---+---+---+---+ + * | a | b | e | f | + * +---+---+---+---+ + * +---+---+---+---+ + * | c | d | g | h | + * +---+---+---+---+ + */ + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + vtrn128_32q(a, b); + /* +---+---+---+---+ + * | a | c | e | g | + * +---+---+---+---+ + * +---+---+---+---+ + * | b | d | f | h | + * +---+---+---+---+ + */ + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + return vzipq_f32(a, b); +} + + +static float32x4x2_t arm_bitonic_merge_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + /* a and b are guaranteed to be bitonic */ + // Reverse the element of the second vector + b = vrev128q_f32(b); + + // Compare the two vectors + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + // Merge the two vectors + float32x4x2_t ab = arm_bitonic_resort_8_f32(a, b, dir); + + return ab; +} + +static void arm_bitonic_resort_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir) +{ + /* Start with two vectors: + * +---+---+---+---+---+---+---+---+ + * | a | b | c | d | e | f | g | h | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | i | j | k | l | m | n | o | p | + * +---+---+---+---+---+---+---+---+ + * All the elements of the first are guaranteed to be less than or equal to + * all of the elements in the second, and both vectors are bitonic. + * We need to perform these operations to completely sort both lists: + * vminmax([abcd],[efgh]) vminmax([ijkl],[mnop]) + * vminmax([abef],[cdgh]) vminmax([ijmn],[klop]) + * vminmax([acef],[bdfh]) vminmax([ikmo],[jlmp]) + */ + + vtrn256_128q(a, b); + /* +---+---+---+---+---+---+---+---+ + * | a | b | c | d | i | j | k | l | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | e | f | g | h | m | n | o | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + vtrn256_64q(a, b); + + /* +---+---+---+---+---+---+---+---+ + * | a | b | e | f | i | j | m | n | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | c | d | g | h | k | l | o | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + vtrn256_32q(a, b); + /* We now have: + * +---+---+---+---+---+---+---+---+ + * | a | c | e | g | i | k | m | o | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | b | d | f | h | j | l | n | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + float32x4x2_t out1 = vzipq_f32(a.val[0], b.val[0]); + float32x4x2_t out2 = vzipq_f32(a.val[1], b.val[1]); + + vst1q_f32(pOut, out1.val[0]); + vst1q_f32(pOut+4, out1.val[1]); + vst1q_f32(pOut+8, out2.val[0]); + vst1q_f32(pOut+12, out2.val[1]); +} + +static void arm_bitonic_merge_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir) +{ + // Merge two preordered float32x4x2_t + vrev256q_f32(b); + + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + arm_bitonic_resort_16_f32(pOut, a, b, dir); +} + +static void arm_bitonic_sort_16_f32(float32_t *pSrc, float32_t *pDst, uint8_t dir) +{ + float32x4_t a; + float32x4_t b; + float32x4_t c; + float32x4_t d; + + // Load 16 samples + a = vld1q_f32(pSrc); + b = vld1q_f32(pSrc+4); + c = vld1q_f32(pSrc+8); + d = vld1q_f32(pSrc+12); + + // Bitonic sorting network for 4 samples x 4 times + if(dir) + { + vminmaxq(a, b); + vminmaxq(c, d); + + vminmaxq(a, d); + vminmaxq(b, c); + + vminmaxq(a, b); + vminmaxq(c, d); + } + else + { + vminmaxq(b, a); + vminmaxq(d, c); + + vminmaxq(d, a); + vminmaxq(c, b); + + vminmaxq(b, a); + vminmaxq(d, c); + } + + float32x4x2_t ab = vtrnq_f32 (a, b); + float32x4x2_t cd = vtrnq_f32 (c, d); + + // Transpose 4 ordered arrays of 4 samples + a = vcombine_f32(vget_low_f32(ab.val[0]), vget_low_f32(cd.val[0])); + b = vcombine_f32(vget_low_f32(ab.val[1]), vget_low_f32(cd.val[1])); + c = vcombine_f32(vget_high_f32(ab.val[0]), vget_high_f32(cd.val[0])); + d = vcombine_f32(vget_high_f32(ab.val[1]), vget_high_f32(cd.val[1])); + + // Merge pairs of arrays of 4 samples + ab = arm_bitonic_merge_8_f32(a, b, dir); + cd = arm_bitonic_merge_8_f32(c, d, dir); + + // Merge arrays of 8 samples + arm_bitonic_merge_16_f32(pDst, ab, cd, dir); +} + + + + + +static void arm_bitonic_merge_32_f32(float32_t * pSrc, float32x4x2_t ab1, float32x4x2_t ab2, float32x4x2_t cd1, float32x4x2_t cd2, uint8_t dir) +{ + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + } + //Transpose 256 + float32x4_t temp; + + temp = ab2.val[0]; + ab2.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab2.val[1]; + ab2.val[1] = cd1.val[1]; + cd1.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + } + + //Transpose 128 + arm_bitonic_merge_16_f32(pSrc+0, ab1, cd1, dir); + arm_bitonic_merge_16_f32(pSrc+16, ab2, cd2, dir); +} + +static void arm_bitonic_merge_64_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4; + float32x4x2_t cd1, cd2, cd3, cd4; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12); + ab3.val[0] = vld1q_f32(pSrc+16); + ab3.val[1] = vld1q_f32(pSrc+20); + ab4.val[0] = vld1q_f32(pSrc+24); + ab4.val[1] = vld1q_f32(pSrc+28); + + vldrev128q_f32(cd4.val[1], pSrc+32); + vldrev128q_f32(cd4.val[0], pSrc+36); + vldrev128q_f32(cd3.val[1], pSrc+40); + vldrev128q_f32(cd3.val[0], pSrc+44); + vldrev128q_f32(cd2.val[1], pSrc+48); + vldrev128q_f32(cd2.val[0], pSrc+52); + vldrev128q_f32(cd1.val[1], pSrc+56); + vldrev128q_f32(cd1.val[0], pSrc+60); + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + } + + //Transpose 512 + float32x4_t temp; + + temp = ab3.val[0]; + ab3.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab3.val[1]; + ab3.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab4.val[0]; + ab4.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab4.val[1]; + ab4.val[1] = cd2.val[1]; + cd2.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + } + + //Transpose 256 + arm_bitonic_merge_32_f32(pSrc+0, ab1, ab2, cd1, cd2, dir); + arm_bitonic_merge_32_f32(pSrc+32, ab3, ab4, cd3, cd4, dir); +} + +static void arm_bitonic_merge_128_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8; + float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12); + ab3.val[0] = vld1q_f32(pSrc+16); + ab3.val[1] = vld1q_f32(pSrc+20); + ab4.val[0] = vld1q_f32(pSrc+24); + ab4.val[1] = vld1q_f32(pSrc+28); + ab5.val[0] = vld1q_f32(pSrc+32); + ab5.val[1] = vld1q_f32(pSrc+36); + ab6.val[0] = vld1q_f32(pSrc+40); + ab6.val[1] = vld1q_f32(pSrc+44); + ab7.val[0] = vld1q_f32(pSrc+48); + ab7.val[1] = vld1q_f32(pSrc+52); + ab8.val[0] = vld1q_f32(pSrc+56); + ab8.val[1] = vld1q_f32(pSrc+60); + + vldrev128q_f32(cd8.val[1], pSrc+64); + vldrev128q_f32(cd8.val[0], pSrc+68); + vldrev128q_f32(cd7.val[1], pSrc+72); + vldrev128q_f32(cd7.val[0], pSrc+76); + vldrev128q_f32(cd6.val[1], pSrc+80); + vldrev128q_f32(cd6.val[0], pSrc+84); + vldrev128q_f32(cd5.val[1], pSrc+88); + vldrev128q_f32(cd5.val[0], pSrc+92); + vldrev128q_f32(cd4.val[1], pSrc+96); + vldrev128q_f32(cd4.val[0], pSrc+100); + vldrev128q_f32(cd3.val[1], pSrc+104); + vldrev128q_f32(cd3.val[0], pSrc+108); + vldrev128q_f32(cd2.val[1], pSrc+112); + vldrev128q_f32(cd2.val[0], pSrc+116); + vldrev128q_f32(cd1.val[1], pSrc+120); + vldrev128q_f32(cd1.val[0], pSrc+124); + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + vminmax256q(ab5, cd5); + vminmax256q(ab6, cd6); + vminmax256q(ab7, cd7); + vminmax256q(ab8, cd8); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + vminmax256q(cd5, ab5); + vminmax256q(cd6, ab6); + vminmax256q(cd7, ab7); + vminmax256q(cd8, ab8); + } + + //Transpose + float32x4_t temp; + + temp = ab5.val[0]; + ab5.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab5.val[1]; + ab5.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab6.val[0]; + ab6.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab6.val[1]; + ab6.val[1] = cd2.val[1]; + cd2.val[1] = temp; + temp = ab7.val[0]; + ab7.val[0] = cd3.val[0]; + cd3.val[0] = temp; + temp = ab7.val[1]; + ab7.val[1] = cd3.val[1]; + cd3.val[1] = temp; + temp = ab8.val[0]; + ab8.val[0] = cd4.val[0]; + cd4.val[0] = temp; + temp = ab8.val[1]; + ab8.val[1] = cd4.val[1]; + cd4.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + vminmax256q(ab5, cd5); + vminmax256q(ab6, cd6); + vminmax256q(ab7, cd7); + vminmax256q(ab8, cd8); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + vminmax256q(cd5, ab5); + vminmax256q(cd6, ab6); + vminmax256q(cd7, ab7); + vminmax256q(cd8, ab8); + } + + vst1q_f32(pSrc, ab1.val[0]); + vst1q_f32(pSrc+4, ab1.val[1]); + vst1q_f32(pSrc+8, ab2.val[0]); + vst1q_f32(pSrc+12, ab2.val[1]); + vst1q_f32(pSrc+16, ab3.val[0]); + vst1q_f32(pSrc+20, ab3.val[1]); + vst1q_f32(pSrc+24, ab4.val[0]); + vst1q_f32(pSrc+28, ab4.val[1]); + vst1q_f32(pSrc+32, cd1.val[0]); + vst1q_f32(pSrc+36, cd1.val[1]); + vst1q_f32(pSrc+40, cd2.val[0]); + vst1q_f32(pSrc+44, cd2.val[1]); + vst1q_f32(pSrc+48, cd3.val[0]); + vst1q_f32(pSrc+52, cd3.val[1]); + vst1q_f32(pSrc+56, cd4.val[0]); + vst1q_f32(pSrc+60, cd4.val[1]); + vst1q_f32(pSrc+64, ab5.val[0]); + vst1q_f32(pSrc+68, ab5.val[1]); + vst1q_f32(pSrc+72, ab6.val[0]); + vst1q_f32(pSrc+76, ab6.val[1]); + vst1q_f32(pSrc+80, ab7.val[0]); + vst1q_f32(pSrc+84, ab7.val[1]); + vst1q_f32(pSrc+88, ab8.val[0]); + vst1q_f32(pSrc+92, ab8.val[1]); + vst1q_f32(pSrc+96, cd5.val[0]); + vst1q_f32(pSrc+100, cd5.val[1]); + vst1q_f32(pSrc+104, cd6.val[0]); + vst1q_f32(pSrc+108, cd6.val[1]); + vst1q_f32(pSrc+112, cd7.val[0]); + vst1q_f32(pSrc+116, cd7.val[1]); + vst1q_f32(pSrc+120, cd8.val[0]); + vst1q_f32(pSrc+124, cd8.val[1]); + + //Transpose + arm_bitonic_merge_64_f32(pSrc+0 , dir); + arm_bitonic_merge_64_f32(pSrc+64, dir); +} + +static void arm_bitonic_merge_256_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8; + float32x4x2_t ab9, ab10, ab11, ab12, ab13, ab14, ab15, ab16; + float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8; + float32x4x2_t cd9, cd10, cd11, cd12, cd13, cd14, cd15, cd16; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12 ); + ab3.val[0] = vld1q_f32(pSrc+16 ); + ab3.val[1] = vld1q_f32(pSrc+20 ); + ab4.val[0] = vld1q_f32(pSrc+24 ); + ab4.val[1] = vld1q_f32(pSrc+28 ); + ab5.val[0] = vld1q_f32(pSrc+32 ); + ab5.val[1] = vld1q_f32(pSrc+36 ); + ab6.val[0] = vld1q_f32(pSrc+40 ); + ab6.val[1] = vld1q_f32(pSrc+44 ); + ab7.val[0] = vld1q_f32(pSrc+48 ); + ab7.val[1] = vld1q_f32(pSrc+52 ); + ab8.val[0] = vld1q_f32(pSrc+56 ); + ab8.val[1] = vld1q_f32(pSrc+60 ); + ab9.val[0] = vld1q_f32(pSrc+64 ); + ab9.val[1] = vld1q_f32(pSrc+68 ); + ab10.val[0] = vld1q_f32(pSrc+72 ); + ab10.val[1] = vld1q_f32(pSrc+76 ); + ab11.val[0] = vld1q_f32(pSrc+80 ); + ab11.val[1] = vld1q_f32(pSrc+84 ); + ab12.val[0] = vld1q_f32(pSrc+88 ); + ab12.val[1] = vld1q_f32(pSrc+92 ); + ab13.val[0] = vld1q_f32(pSrc+96 ); + ab13.val[1] = vld1q_f32(pSrc+100); + ab14.val[0] = vld1q_f32(pSrc+104); + ab14.val[1] = vld1q_f32(pSrc+108); + ab15.val[0] = vld1q_f32(pSrc+112); + ab15.val[1] = vld1q_f32(pSrc+116); + ab16.val[0] = vld1q_f32(pSrc+120); + ab16.val[1] = vld1q_f32(pSrc+124); + + vldrev128q_f32(cd16.val[1], pSrc+128); + vldrev128q_f32(cd16.val[0], pSrc+132); + vldrev128q_f32(cd15.val[1], pSrc+136); + vldrev128q_f32(cd15.val[0], pSrc+140); + vldrev128q_f32(cd14.val[1], pSrc+144); + vldrev128q_f32(cd14.val[0], pSrc+148); + vldrev128q_f32(cd13.val[1], pSrc+152); + vldrev128q_f32(cd13.val[0], pSrc+156); + vldrev128q_f32(cd12.val[1], pSrc+160); + vldrev128q_f32(cd12.val[0], pSrc+164); + vldrev128q_f32(cd11.val[1], pSrc+168); + vldrev128q_f32(cd11.val[0], pSrc+172); + vldrev128q_f32(cd10.val[1], pSrc+176); + vldrev128q_f32(cd10.val[0], pSrc+180); + vldrev128q_f32(cd9.val[1] , pSrc+184); + vldrev128q_f32(cd9.val[0] , pSrc+188); + vldrev128q_f32(cd8.val[1] , pSrc+192); + vldrev128q_f32(cd8.val[0] , pSrc+196); + vldrev128q_f32(cd7.val[1] , pSrc+200); + vldrev128q_f32(cd7.val[0] , pSrc+204); + vldrev128q_f32(cd6.val[1] , pSrc+208); + vldrev128q_f32(cd6.val[0] , pSrc+212); + vldrev128q_f32(cd5.val[1] , pSrc+216); + vldrev128q_f32(cd5.val[0] , pSrc+220); + vldrev128q_f32(cd4.val[1] , pSrc+224); + vldrev128q_f32(cd4.val[0] , pSrc+228); + vldrev128q_f32(cd3.val[1] , pSrc+232); + vldrev128q_f32(cd3.val[0] , pSrc+236); + vldrev128q_f32(cd2.val[1] , pSrc+240); + vldrev128q_f32(cd2.val[0] , pSrc+244); + vldrev128q_f32(cd1.val[1] , pSrc+248); + vldrev128q_f32(cd1.val[0] , pSrc+252); + + //Compare + if(dir) + { + vminmax256q(ab1 , cd1 ); + vminmax256q(ab2 , cd2 ); + vminmax256q(ab3 , cd3 ); + vminmax256q(ab4 , cd4 ); + vminmax256q(ab5 , cd5 ); + vminmax256q(ab6 , cd6 ); + vminmax256q(ab7 , cd7 ); + vminmax256q(ab8 , cd8 ); + vminmax256q(ab9 , cd9 ); + vminmax256q(ab10, cd10); + vminmax256q(ab11, cd11); + vminmax256q(ab12, cd12); + vminmax256q(ab13, cd13); + vminmax256q(ab14, cd14); + vminmax256q(ab15, cd15); + vminmax256q(ab16, cd16); + } + else + { + vminmax256q(cd1 , ab1 ); + vminmax256q(cd2 , ab2 ); + vminmax256q(cd3 , ab3 ); + vminmax256q(cd4 , ab4 ); + vminmax256q(cd5 , ab5 ); + vminmax256q(cd6 , ab6 ); + vminmax256q(cd7 , ab7 ); + vminmax256q(cd8 , ab8 ); + vminmax256q(cd9 , ab9 ); + vminmax256q(cd10, ab10); + vminmax256q(cd11, ab11); + vminmax256q(cd12, ab12); + vminmax256q(cd13, ab13); + vminmax256q(cd14, ab14); + vminmax256q(cd15, ab15); + vminmax256q(cd16, ab16); + } + + //Transpose + float32x4_t temp; + + temp = ab9.val[0]; + ab9.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab9.val[1]; + ab9.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab10.val[0]; + ab10.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab10.val[1]; + ab10.val[1] = cd2.val[1]; + cd2.val[1] = temp; + temp = ab11.val[0]; + ab11.val[0] = cd3.val[0]; + cd3.val[0] = temp; + temp = ab11.val[1]; + ab11.val[1] = cd3.val[1]; + cd3.val[1] = temp; + temp = ab12.val[0]; + ab12.val[0] = cd4.val[0]; + cd4.val[0] = temp; + temp = ab12.val[1]; + ab12.val[1] = cd4.val[1]; + cd4.val[1] = temp; + temp = ab13.val[0]; + ab13.val[0] = cd5.val[0]; + cd5.val[0] = temp; + temp = ab13.val[1]; + ab13.val[1] = cd5.val[1]; + cd5.val[1] = temp; + temp = ab14.val[0]; + ab14.val[0] = cd6.val[0]; + cd6.val[0] = temp; + temp = ab14.val[1]; + ab14.val[1] = cd6.val[1]; + cd6.val[1] = temp; + temp = ab15.val[0]; + ab15.val[0] = cd7.val[0]; + cd7.val[0] = temp; + temp = ab15.val[1]; + ab15.val[1] = cd7.val[1]; + cd7.val[1] = temp; + temp = ab16.val[0]; + ab16.val[0] = cd8.val[0]; + cd8.val[0] = temp; + temp = ab16.val[1]; + ab16.val[1] = cd8.val[1]; + cd8.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1 , cd1 ); + vminmax256q(ab2 , cd2 ); + vminmax256q(ab3 , cd3 ); + vminmax256q(ab4 , cd4 ); + vminmax256q(ab5 , cd5 ); + vminmax256q(ab6 , cd6 ); + vminmax256q(ab7 , cd7 ); + vminmax256q(ab8 , cd8 ); + vminmax256q(ab9 , cd9 ); + vminmax256q(ab10, cd10); + vminmax256q(ab11, cd11); + vminmax256q(ab12, cd12); + vminmax256q(ab13, cd13); + vminmax256q(ab14, cd14); + vminmax256q(ab15, cd15); + vminmax256q(ab16, cd16); + } + else + { + vminmax256q(cd1 , ab1 ); + vminmax256q(cd2 , ab2 ); + vminmax256q(cd3 , ab3 ); + vminmax256q(cd4 , ab4 ); + vminmax256q(cd5 , ab5 ); + vminmax256q(cd6 , ab6 ); + vminmax256q(cd7 , ab7 ); + vminmax256q(cd8 , ab8 ); + vminmax256q(cd9 , ab9 ); + vminmax256q(cd10, ab10); + vminmax256q(cd11, ab11); + vminmax256q(cd12, ab12); + vminmax256q(cd13, ab13); + vminmax256q(cd14, ab14); + vminmax256q(cd15, ab15); + vminmax256q(cd16, ab16); + } + + vst1q_f32(pSrc, ab1.val[0] ); + vst1q_f32(pSrc+4, ab1.val[1] ); + vst1q_f32(pSrc+8, ab2.val[0] ); + vst1q_f32(pSrc+12, ab2.val[1] ); + vst1q_f32(pSrc+16, ab3.val[0] ); + vst1q_f32(pSrc+20, ab3.val[1] ); + vst1q_f32(pSrc+24, ab4.val[0] ); + vst1q_f32(pSrc+28, ab4.val[1] ); + vst1q_f32(pSrc+32, ab5.val[0] ); + vst1q_f32(pSrc+36, ab5.val[1] ); + vst1q_f32(pSrc+40, ab6.val[0] ); + vst1q_f32(pSrc+44, ab6.val[1] ); + vst1q_f32(pSrc+48, ab7.val[0] ); + vst1q_f32(pSrc+52, ab7.val[1] ); + vst1q_f32(pSrc+56, ab8.val[0] ); + vst1q_f32(pSrc+60, ab8.val[1] ); + vst1q_f32(pSrc+64, cd1.val[0] ); + vst1q_f32(pSrc+68, cd1.val[1] ); + vst1q_f32(pSrc+72, cd2.val[0] ); + vst1q_f32(pSrc+76, cd2.val[1] ); + vst1q_f32(pSrc+80, cd3.val[0] ); + vst1q_f32(pSrc+84, cd3.val[1] ); + vst1q_f32(pSrc+88, cd4.val[0] ); + vst1q_f32(pSrc+92, cd4.val[1] ); + vst1q_f32(pSrc+96, cd5.val[0] ); + vst1q_f32(pSrc+100, cd5.val[1] ); + vst1q_f32(pSrc+104, cd6.val[0] ); + vst1q_f32(pSrc+108, cd6.val[1] ); + vst1q_f32(pSrc+112, cd7.val[0] ); + vst1q_f32(pSrc+116, cd7.val[1] ); + vst1q_f32(pSrc+120, cd8.val[0] ); + vst1q_f32(pSrc+124, cd8.val[1] ); + vst1q_f32(pSrc+128, ab9.val[0] ); + vst1q_f32(pSrc+132, ab9.val[1] ); + vst1q_f32(pSrc+136, ab10.val[0]); + vst1q_f32(pSrc+140, ab10.val[1]); + vst1q_f32(pSrc+144, ab11.val[0]); + vst1q_f32(pSrc+148, ab11.val[1]); + vst1q_f32(pSrc+152, ab12.val[0]); + vst1q_f32(pSrc+156, ab12.val[1]); + vst1q_f32(pSrc+160, ab13.val[0]); + vst1q_f32(pSrc+164, ab13.val[1]); + vst1q_f32(pSrc+168, ab14.val[0]); + vst1q_f32(pSrc+172, ab14.val[1]); + vst1q_f32(pSrc+176, ab15.val[0]); + vst1q_f32(pSrc+180, ab15.val[1]); + vst1q_f32(pSrc+184, ab16.val[0]); + vst1q_f32(pSrc+188, ab16.val[1]); + vst1q_f32(pSrc+192, cd9.val[0] ); + vst1q_f32(pSrc+196, cd9.val[1] ); + vst1q_f32(pSrc+200, cd10.val[0]); + vst1q_f32(pSrc+204, cd10.val[1]); + vst1q_f32(pSrc+208, cd11.val[0]); + vst1q_f32(pSrc+212, cd11.val[1]); + vst1q_f32(pSrc+216, cd12.val[0]); + vst1q_f32(pSrc+220, cd12.val[1]); + vst1q_f32(pSrc+224, cd13.val[0]); + vst1q_f32(pSrc+228, cd13.val[1]); + vst1q_f32(pSrc+232, cd14.val[0]); + vst1q_f32(pSrc+236, cd14.val[1]); + vst1q_f32(pSrc+240, cd15.val[0]); + vst1q_f32(pSrc+244, cd15.val[1]); + vst1q_f32(pSrc+248, cd16.val[0]); + vst1q_f32(pSrc+252, cd16.val[1]); + + //Transpose + arm_bitonic_merge_128_f32(pSrc+0 , dir); + arm_bitonic_merge_128_f32(pSrc+128, dir); +} + +#define SWAP(a,i,j) \ + temp = vgetq_lane_f32(a, j); \ + a = vsetq_lane_f32(vgetq_lane_f32(a, i), a, j);\ + a = vsetq_lane_f32(temp, a, i); + +static float32x4_t arm_bitonic_sort_4_f32(float32x4_t a, uint8_t dir) +{ + float32_t temp; + + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) ) + { + SWAP(a,0,1); + } + if( dir==(vgetq_lane_f32(a, 2) > vgetq_lane_f32(a, 3)) ) + { + SWAP(a,2,3); + } + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 3)) ) + { + SWAP(a,0,3); + } + if( dir==(vgetq_lane_f32(a, 1) > vgetq_lane_f32(a, 2)) ) + { + SWAP(a,1,2); + } + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) ) + { + SWAP(a,0,1); + } + if( dir==(vgetq_lane_f32(a, 2)>vgetq_lane_f32(a, 3)) ) + { + SWAP(a,2,3); + } + + return a; +} + +static float32x4x2_t arm_bitonic_sort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + a = arm_bitonic_sort_4_f32(a, dir); + b = arm_bitonic_sort_4_f32(b, dir); + return arm_bitonic_merge_8_f32(a, b, dir); +} + + + +#endif + +/** + @ingroup groupSupport + */ + +/** + @defgroup Sorting Vector sorting algorithms + + Sort the elements of a vector + + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_bitonic_sort_f32( +const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint16_t s, i; + uint8_t dir = S->dir; + +#ifdef ARM_MATH_NEON + (void)s; + + float32_t * pOut; + uint16_t counter = blockSize>>5; + + if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only + { + if(pSrc == pDst) // in-place + pOut = pSrc; + else + pOut = pDst; + + float32x4x2_t ab1, ab2; + float32x4x2_t cd1, cd2; + + if(blockSize == 1) + pOut = pSrc; + else if(blockSize == 2) + { + float32_t temp; + + if( dir==(pSrc[0]>pSrc[1]) ) + { + temp = pSrc[1]; + pOut[1] = pSrc[0]; + pOut[0] = temp; + } + else + pOut = pSrc; + } + else if(blockSize == 4) + { + float32x4_t a = vld1q_f32(pSrc); + + a = arm_bitonic_sort_4_f32(a, dir); + + vst1q_f32(pOut, a); + } + else if(blockSize == 8) + { + float32x4_t a; + float32x4_t b; + float32x4x2_t ab; + + a = vld1q_f32(pSrc); + b = vld1q_f32(pSrc+4); + + ab = arm_bitonic_sort_8_f32(a, b, dir); + + vst1q_f32(pOut, ab.val[0]); + vst1q_f32(pOut+4, ab.val[1]); + } + else if(blockSize >=16) + { + // Order 16 bits long vectors + for(i=0; i>1; + for(i=0; i>1; + for(i=0; i>1; + for(i=0; idir; + uint32_t i; + uint8_t swapped =1; + float32_t * pA; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + while(swapped==1) // If nothing has been swapped after one loop stop + { + swapped=0; + + for(i=0; ipA[i+1])) + { + // Swap + temp = pA[i]; + pA[i] = pA[i+1]; + pA[i+1] = temp; + + // Update flag + swapped = 1; + } + } + + blockSize--; + } +} + +/** + @} end of Sorting group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c new file mode 100644 index 0000000..6d0003b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c @@ -0,0 +1,134 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f16.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a f16 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_copy_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + do { + mve_pred16_t p = vctp16q(blockSize); + + vstrhq_p_f16(pDst, + vldrhq_z_f16((float16_t const *) pSrc, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} + +#else + +void arm_copy_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicCopy group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c new file mode 100644 index 0000000..f6f2a33 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c @@ -0,0 +1,196 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f32.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup copy Vector Copy + + Copies sample by sample from source vector to destination vector. + + 
+      pDst[n] = pSrc[n];   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + vstrwq_f32(pDst, vldrwq_f32(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + inV = vld1q_f32(pSrc); + vst1q_f32(pDst, inV); + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicCopy group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c new file mode 100644 index 0000000..05c21e1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c @@ -0,0 +1,75 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f64.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_copy_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of BasicCopy group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c new file mode 100644 index 0000000..fcb7d22 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c @@ -0,0 +1,134 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q15.c + * Description: Copies the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q15 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pDst,vldrhq_s16(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt --; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, read_q15x2_ia (&pSrc)); + write_q15x2_ia (&pDst, read_q15x2_ia (&pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c new file mode 100644 index 0000000..1249380 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c @@ -0,0 +1,139 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q31.c + * Description: Copies the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q31 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + vstrwq_s32(pDst,vldrwq_s32(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c new file mode 100644 index 0000000..70f7b7f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c @@ -0,0 +1,136 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q7.c + * Description: Copies the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q7 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + + vstrbq_s8(pDst,vldrbq_s8(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + blkCnt --; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 4 samples at a time */ + write_q7x4_ia (&pDst, read_q7x4_ia (&pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c new file mode 100644 index 0000000..cf4451f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c @@ -0,0 +1,138 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup f16_to_x Convert 16-bit floating point value + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to f32 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the f32 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_f16_to_float built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +void arm_f16_to_float( + const float16_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + float16x8_t vecDst; + float32x4x2_t tmp; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecDst = vldrhq_f16(pSrc); + pSrc += 8; + + tmp.val[0] = vcvtbq_f32_f16(vecDst); + tmp.val[1] = vcvttq_f32_f16(vecDst); + vst2q(pDst,tmp); + + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + while (blkCnt > 0) + { + + *pDst++ = (float32_t) *pSrc++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} + +#else +void arm_f16_to_float( + const float16_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float32_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c new file mode 100644 index 0000000..cdd714e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c @@ -0,0 +1,161 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to Q15 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding in scalar version, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_f16_to_q15( + const float16_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + float16_t maxQ = (float16_t) Q15_MAX; + float16x8_t vecDst; + + + do { + mve_pred16_t p = vctp16q(blockSize); + + vecDst = vldrhq_z_f16((float16_t const *) pSrc, p); + /* C = A * 32767 */ + /* convert from float to Q15 and then store the results in the destination buffer */ + vecDst = vmulq_m(vuninitializedq_f16(), vecDst, maxQ, p); + + vstrhq_p_s16(pDst, + vcvtaq_m(vuninitializedq_s16(), vecDst, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} + +#else + +void arm_f16_to_q15( + const float16_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ +#ifdef ARM_MATH_ROUNDING + float16_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* + * C = A * 65536 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + in = *pIn++; + in = (in * 32768.0); + in += in > 0.0 ? 0.5 : -0.5; + *pDst++ = clip_q31_to_q15((q31_t) (in)); + +#else + + /* + * C = A * 32768 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + *pDst++ = clip_q31_to_q15((q31_t) ((_Float16)*pIn++ * 32768.0f16)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* + * Decrement the loop counter + */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c new file mode 100644 index 0000000..f52f505 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c @@ -0,0 +1,131 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f16.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a f16 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_fill_f16( + float16_t value, + float16_t * pDst, + uint32_t blockSize) +{ + do { + mve_pred16_t p = vctp16q(blockSize); + + vstrhq_p_f16(pDst, + vdupq_m_n_f16(vuninitializedq_f16(), value, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} +#else +void arm_fill_f16( + float16_t value, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Fill group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c new file mode 100644 index 0000000..b06ceb3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c @@ -0,0 +1,193 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f32.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup Fill Vector Fill + + Fills the destination vector with a constant value. + + 
+      pDst[n] = value;   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + + vstrwq_f32(pDst,vdupq_n_f32(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + + float32x4_t inV = vdupq_n_f32(value); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + vst1q_f32(pDst, inV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + *pDst++ = value; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Fill group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c new file mode 100644 index 0000000..152cb4c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c @@ -0,0 +1,75 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f64.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_fill_f64( + float64_t value, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of Fill group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c new file mode 100644 index 0000000..a45aae4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c @@ -0,0 +1,138 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q15.c + * Description: Fills a constant value into a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q15 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + + vstrhq_s16(pDst,vdupq_n_s16(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 8; + blkCnt --; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing two 16 bit values to 32 bit value in order to use SIMD */ + packedValue = __PKHBT(value, value, 16U); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, packedValue); + write_q15x2_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c new file mode 100644 index 0000000..9a8b129 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c @@ -0,0 +1,139 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q31.c + * Description: Fills a constant value into a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q31 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + + vstrwq_s32(pDst,vdupq_n_s32(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c new file mode 100644 index 0000000..1211436 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c @@ -0,0 +1,137 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q7.c + * Description: Fills a constant value into a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q7 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + + vstrbq_s8(pDst,vdupq_n_s8(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 16; + blkCnt --; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing four 8 bit values to 32 bit value in order to use SIMD */ + packedValue = __PACKq7(value, value, value, value); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 4 samples at a time */ + write_q7x4_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c new file mode 100644 index 0000000..c726153 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c @@ -0,0 +1,135 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to f16 vector. + @param[in] pSrc points to the f32 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_float_to_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +void arm_float_to_f16( + const float32_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + float32x4x2_t tmp; + float16x8_t vecDst; + float32_t const *pSrcVec; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + /* convert from float32 to float16 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); pSrcVec += 8; + /* narrow / merge */ + vecDst = vcvtbq_f16_f32(vecDst, tmp.val[0]); + vecDst = vcvttq_f16_f32(vecDst, tmp.val[1]); + vst1q(pDst, vecDst); pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt); + tmp = vld2q(pSrcVec); + vecDst = vcvtbq_f16_f32(vecDst, tmp.val[0]); + vecDst = vcvttq_f16_f32(vecDst, tmp.val[1]); + vstrhq_p(pDst, vecDst, p0); + } +} + +#else + +void arm_float_to_f16( + const float32_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float16_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c new file mode 100644 index 0000000..dd5bab1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c @@ -0,0 +1,312 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q15 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t maxQ = (float32_t) Q15_MAX; + f32x4x2_t tmp; + q15x8_t vecDst = { 0 }; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = A * 32768 */ + /* convert from float to q15 and then store the results in the destination buffer */ + tmp = vld2q(pSrc); + + tmp.val[0] = vmulq(tmp.val[0], maxQ); + tmp.val[1] = vmulq(tmp.val[1], maxQ); + + vecDst = vqmovnbq(vecDst, vcvtaq_s32_f32(tmp.val[0])); + vecDst = vqmovntq(vecDst, vcvtaq_s32_f32(tmp.val[1])); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + pDst += 8; + pSrc += 8; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrc++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pSrc++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 32768.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 32768.0f); + float32x4_t r; + uint32x4_t cmp; + float32_t in; + #endif + + int32x4_t cvt; + int16x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c new file mode 100644 index 0000000..76cd238 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c @@ -0,0 +1,318 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q31.c + * Description: Converts the elements of the floating-point vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup float_to_x Convert 32-bit floating point value + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q31 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t maxQ = (float32_t) Q31_MAX; + f32x4_t vecDst; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. */ + while (blkCnt > 0U) + { + + vecDst = vldrwq_f32(pSrc); + /* C = A * 2147483648 */ + /* convert from float to Q31 and then store the results in the destination buffer */ + vecDst = vmulq(vecDst, maxQ); + + vstrwq_s32(pDst, vcvtaq_s32_f32(vecDst)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrc++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pSrc++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32_t in; + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 2147483648.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 2147483648.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 32768 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + +} +#else +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c new file mode 100644 index 0000000..f64e6d2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c @@ -0,0 +1,334 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q7.c + * Description: Converts the elements of the floating-point vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + *\par Description: + * \par + * The equation used for the conversion process is: + * 
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.
+ *
+ * \par Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + * \note + * In order to apply rounding, the library should be rebuilt with the ROUNDING macro + * defined in the preprocessor section of project options. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + float32_t maxQ = powf(2.0, 7); + f32x4x4_t tmp; + q15x8_t evVec = { 0 }, oddVec = { 0 }; + q7x16_t vecDst = { 0 }; + float32_t const *pSrcVec; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) { + tmp = vld4q(pSrcVec); + pSrcVec += 16; + /* + * C = A * 128.0 + * convert from float to q7 and then store the results in the destination buffer + */ + tmp.val[0] = vmulq(tmp.val[0], maxQ); + tmp.val[1] = vmulq(tmp.val[1], maxQ); + tmp.val[2] = vmulq(tmp.val[2], maxQ); + tmp.val[3] = vmulq(tmp.val[3], maxQ); + + /* + * convert and pack evens + */ + evVec = vqmovnbq(evVec, vcvtaq_s32_f32(tmp.val[0])); + evVec = vqmovntq(evVec, vcvtaq_s32_f32(tmp.val[2])); + /* + * convert and pack odds + */ + oddVec = vqmovnbq(oddVec, vcvtaq_s32_f32(tmp.val[1])); + oddVec = vqmovntq(oddVec, vcvtaq_s32_f32(tmp.val[3])); + /* + * merge + */ + vecDst = vqmovnbq(vecDst, evVec); + vecDst = vqmovntq(vecDst, oddVec); + + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrcVec++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pSrcVec++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +#if defined(ARM_MATH_NEON) +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32_t in; + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 128.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 128.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int16x4_t cvt1,cvt2; + int8x8_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + vst1_s8(pDst, outV); + pDst += 8; + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + + vst1_s8(pDst, outV); + pDst += 8; +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + +} +#else +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c new file mode 100644 index 0000000..aa52173 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c @@ -0,0 +1,123 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_heap_sort_f32.c + * Description: Floating point heap sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h" + + + +static void arm_heapify(float32_t * pSrc, uint32_t n, uint32_t i, uint8_t dir) +{ + /* Put all the elements of pSrc in heap order */ + uint32_t k = i; // Initialize largest/smallest as root + uint32_t l = 2*i + 1; // left = 2*i + 1 + uint32_t r = 2*i + 2; // right = 2*i + 2 + float32_t temp; + + if (l < n && dir==(pSrc[l] > pSrc[k]) ) + k = l; + + if (r < n && dir==(pSrc[r] > pSrc[k]) ) + k = r; + + if (k != i) + { + temp = pSrc[i]; + pSrc[i]=pSrc[k]; + pSrc[k]=temp; + + arm_heapify(pSrc, n, k, dir); + } +} + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The heap sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted region, + * and shrinks the unsorted region by extracting the largest + * element and moving it to the sorted region. A heap data + * structure is used to find the maximum. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ +void arm_heap_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t * pA; + int32_t i; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Build the heap array so that the largest value is the root + for (i = blockSize/2 - 1; i >= 0; i--) + arm_heapify(pA, blockSize, i, S->dir); + + for (i = blockSize - 1; i >= 0; i--) + { + // Swap + temp = pA[i]; + pA[i] = pA[0]; + pA[0] = temp; + + // Restore heap order + arm_heapify(pA, i, 0, S->dir); + } +} +/** + @} end of Sorting group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c new file mode 100644 index 0000000..386c5ce --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c @@ -0,0 +1,97 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_insertion_sort_f32.c + * Description: Floating point insertion sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The insertion sort is a simple sorting algorithm that + * reads all the element of the input array and removes one element + * at a time, finds the location it belongs in the final sorted list, + * and inserts it there. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void arm_insertion_sort_f32( + const arm_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize) +{ + float32_t * pA; + uint8_t dir = S->dir; + uint32_t i, j; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Real all the element of the input array + for(i=0; i0 && dir==(pA[j]= end || dir==(pA[i] <= pA[j])) ) + { + pB[k] = pA[i]; + i++; + } + else + { + pB[k] = pA[j]; + j++; + } + } +} + +static void arm_merge_sort_core_f32(float32_t * pB, uint32_t begin, uint32_t end, float32_t * pA, uint8_t dir) +{ + if((int32_t)end - (int32_t)begin >= 2 ) // If run size != 1 divide + { + int32_t middle = (end + begin) / 2; // Take the middle point + + arm_merge_sort_core_f32(pA, begin, middle, pB, dir); // Sort the left part + arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part + + topDownMerge(pB, begin, middle, end, pA, dir); + } +} + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The merge sort algorithm is a comparison algorithm that + * divide the input array in sublists and merge them to produce + * longer sorted sublists until there is only one list remaining. + * + * @par A work array is always needed. It must be allocated by the user + * linked to the instance at initialization time. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed + */ + + +void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize) +{ + float32_t * pA; + + /* Out-of-place */ + if(pSrc != pDst) + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t)); + pA = pDst; + } + else + pA = pSrc; + + /* A working buffer is needed */ + memcpy(S->buffer, pSrc, blockSize*sizeof(float32_t)); + + arm_merge_sort_core_f32(S->buffer, 0, blockSize, pA, S->dir); +} +/** + @} end of Sorting group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c new file mode 100644 index 0000000..73f916a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c @@ -0,0 +1,57 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_merge_sort_init_f32.c + * Description: Floating point merge sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ +void arm_merge_sort_init_f32(arm_merge_sort_instance_f32 * S, arm_sort_dir dir, float32_t * buffer) +{ + S->dir = dir; + S->buffer = buffer; +} +/** + @} end of Sorting group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c new file mode 100644 index 0000000..a250b0b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c @@ -0,0 +1,159 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit fixed point value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to f16 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float16_t) pSrc[n] / 32768;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_q15_to_f16( + const q15_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecDst; + q15_t const *pSrcVec; + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + /* C = (float16_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + vecDst = vld1q(pSrcVec); pSrcVec += 8; + vstrhq(pDst, vcvtq_n_f16_s16(vecDst, 15)); pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecDst = vld1q(pSrcVec); pSrcVec += 8; + vstrhq_p(pDst, vcvtq_n_f16_s16(vecDst, 15), p0); + } +} +#else + +void arm_q15_to_f16( + const q15_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((_Float16) *pIn++ / 32768.0f16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q15_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c new file mode 100644 index 0000000..1bc9729 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c @@ -0,0 +1,211 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit fixed point value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to floating-point vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + q15x8_t vecDst; + q15_t const *pSrcVec; + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + vecDst = vldrhq_s32(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32((int32x4_t)vecDst, 15)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pSrcVec++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int16x8_t inV; + int32x4_t inV0, inV1; + float32x4_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + inV = vld1q_s16(pIn); + pIn += 8; + + inV0 = vmovl_s16(vget_low_s16(inV)); + inV1 = vmovl_s16(vget_high_s16(inV)); + + outV = vcvtq_n_f32_s32(inV0,15); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inV1,15); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 8, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q15_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c new file mode 100644 index 0000000..2a56392 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c @@ -0,0 +1,186 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q31.c + * Description: Converts the elements of the Q15 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q31 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; + + q31x4_t vecDst; + + blkCnt = blockSize>> 2; + while (blkCnt > 0U) + { + + /* C = (q31_t)A << 16 */ + /* convert from q15 to q31 and then store the results in the destination buffer */ + /* load q15 + 32-bit widening */ + vecDst = vldrhq_s32((q15_t const *) pSrc); + vecDst = vshlq_n(vecDst, 16); + vstrwq_s32(pDst, vecDst); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + pSrc += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pSrc++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; + q31_t out1, out2, out3, out4; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t)A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + in1 = read_q15x2_ia (&pIn); + in2 = read_q15x2_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + /* extract lower 16 bits to 32 bit result */ + out1 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out2 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out3 = in2 << 16U; + /* extract upper 16 bits to 32 bit result */ + out4 = in2 & 0xFFFF0000; + +#else + + /* extract upper 16 bits to 32 bit result */ + out1 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out2 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out3 = in2 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out4 = in2 << 16U; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + *pDst++ = out1; + *pDst++ = out2; + *pDst++ = out3; + *pDst++ = out4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pIn++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q15_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c new file mode 100644 index 0000000..8a33729 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c @@ -0,0 +1,194 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q7.c + * Description: Converts the elements of the Q15 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q7 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; /* loop counters */ + q15x8x2_t tmp; + q15_t const *pSrcVec; + q7x16_t vecDst = { 0 }; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + /* convert from q15 to q7 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); + pSrcVec += 16; + vecDst = vqshrnbq_n_s16(vecDst, tmp.val[0], 8); + vecDst = vqshrntq_n_s16(vecDst, tmp.val[1], 8); + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pSrcVec++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = read_q15x2_ia (&pIn); + in2 = read_q15x2_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHBT(in2, in1, 16); + +#else + + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in1, in2, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* rotate packed value by 24 */ + out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24); + + /* anding with 0xff00ff00 to get two 8 bit values */ + out1 = out1 & 0xFF00FF00; + /* anding with 0x00ff00ff to get two 8 bit values */ + out2 = out2 & 0x00FF00FF; + + /* oring two values(contains two 8 bit values) to get four packed 8 bit values */ + out1 = out1 | out2; + + /* store 4 samples at a time to destiantion buffer */ + write_q7x4_ia (&pDst, out1); + +#else + + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q15_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c new file mode 100644 index 0000000..a478044 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c @@ -0,0 +1,206 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_float.c + * Description: Converts the elements of the Q31 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q31_to_x Convert 32-bit fixed point value + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to floating-point vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecDst; + q31_t const *pSrcVec; + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* convert from q31 to float and then store the results in the destination buffer */ + vecDst = vld1q(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32(vecDst, 31)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pSrcVec++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int32x4_t inV; + float32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + inV = vld1q_s32(pIn); + pIn += 4; + + outV = vcvtq_n_f32_s32(inV,31); + + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 2147483648.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q31_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c new file mode 100644 index 0000000..2d0c58a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c @@ -0,0 +1,185 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q15.c + * Description: Converts the elements of the Q31 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q15 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4x2_t tmp; + q15x8_t vecDst = { 0 }; + q31_t const *pSrcVec; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = (q15_t) A >> 16 */ + /* convert from q31 to q15 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); + pSrcVec += 8; + vecDst = vshrnbq_n_s32(vecDst, tmp.val[0], 16); + vecDst = vshrntq_n_s32(vecDst, tmp.val[1], 16); + vst1q(pDst, vecDst); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pSrcVec++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2, in3, in4; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = *pIn++; + in2 = *pIn++; + in3 = *pIn++; + in4 = *pIn++; + + /* pack two higher 16-bit values from two 32-bit values */ +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHTB(in4, in3, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHTB(in3, in4, 16); +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pIn++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q31_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c new file mode 100644 index 0000000..27d1423 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c @@ -0,0 +1,173 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q7.c + * Description: Converts the elements of the Q31 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q7 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4x4_t tmp; + q15x8_t evVec = { 0 }, oddVec = { 0 }; + q7x16_t vecDst = { 0 }; + q31_t const *pSrcVec; + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + tmp = vld4q(pSrcVec); + pSrcVec += 16; + /* C = (q7_t) A >> 24 */ + /* convert from q31 to q7 and then store the results in the destination buffer */ + /* + * narrow and pack evens + */ + evVec = vshrnbq_n_s32(evVec, tmp.val[0], 16); + evVec = vshrntq_n_s32(evVec, tmp.val[2], 16); + /* + * narrow and pack odds + */ + oddVec = vshrnbq_n_s32(oddVec, tmp.val[1], 16); + oddVec = vshrntq_n_s32(oddVec, tmp.val[3], 16); + /* + * narrow & merge + */ + vecDst = vshrnbq_n_s16(vecDst, evVec, 8); + vecDst = vshrntq_n_s16(vecDst, oddVec, 8); + + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pSrcVec++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q7_t out1, out2, out3, out4; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + + out1 = (q7_t) (*pIn++ >> 24); + out2 = (q7_t) (*pIn++ >> 24); + out3 = (q7_t) (*pIn++ >> 24); + out4 = (q7_t) (*pIn++ >> 24); + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q31_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c new file mode 100644 index 0000000..f70206d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c @@ -0,0 +1,222 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_float.c + * Description: Converts the elements of the Q7 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q7_to_x Convert 8-bit fixed point value + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to floating-point vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecDst; + q7_t const *pSrcVec; + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q7 to float and then store the results in the destination buffer */ + vecDst = vldrbq_s32(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32((int32x4_t)vecDst, 7)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pSrcVec++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int8x16_t inV; + int16x8_t inVLO, inVHI; + int32x4_t inVLL, inVLH, inVHL, inVHH; + float32x4_t outV; + + blkCnt = blockSize >> 4U; + + /* Compute 16 outputs at a time. + ** a second loop below computes the remaining 1 to 15 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + inV = vld1q_s8(pIn); + pIn += 16; + + inVLO = vmovl_s8(vget_low_s8(inV)); + inVHI = vmovl_s8(vget_high_s8(inV)); + + inVLL = vmovl_s16(vget_low_s16(inVLO)); + inVLH = vmovl_s16(vget_high_s16(inVLO)); + inVHL = vmovl_s16(vget_low_s16(inVHI)); + inVHH = vmovl_s16(vget_high_s16(inVHI)); + + outV = vcvtq_n_f32_s32(inVLL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVLH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 16, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 0xF; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q7_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c new file mode 100644 index 0000000..b169fba --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c @@ -0,0 +1,192 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q15.c + * Description: Converts the elements of the Q7 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q15 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; /* loop counters */ + q15x8_t vecDst; + q7_t const *pSrcVec; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + /* load q7 + 32-bit widening */ + vecDst = vldrbq_s16(pSrcVec); + pSrcVec += 8; + vecDst = vecDst << 8; + vstrhq(pDst, vecDst); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pSrcVec++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in = read_q7x4_ia (&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + in1 = in1 << 8U; + in2 = in2 << 8U; + + in1 = in1 & 0xFF00FF00; + in2 = in2 & 0xFF00FF00; + +#ifndef ARM_MATH_BIG_ENDIAN + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in2, in1, 16); +#endif + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pIn++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q7_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c new file mode 100644 index 0000000..7867a08 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c @@ -0,0 +1,168 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q31.c + * Description: Converts the elements of the Q7 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q31 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecDst; + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + + /* C = (q31_t)A << 16 */ + /* convert from q15 to q31 and then store the results in the destination buffer */ + /* load q15 + 32-bit widening */ + vecDst = vldrbq_s32((q7_t const *) pSrc); + vecDst = vshlq_n(vecDst, 24); + vstrwq_s32(pDst, vecDst); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + pSrc += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pSrc++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + in = read_q7x4_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (in & 0xFF000000); + +#else + + *pDst++ = (in & 0xFF000000); + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) * pIn++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q7_to_x group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c new file mode 100644 index 0000000..6c0e638 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c @@ -0,0 +1,185 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quick_sort_f32.c + * Description: Floating point quick sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h" + +static uint32_t arm_quick_sort_partition_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* This function will be called */ + int32_t i, j, pivot_index; + float32_t pivot; + float32_t temp; + + /* The first element is the pivot */ + pivot_index = first; + pivot = pSrc[pivot_index]; + + /* Initialize indices for do-while loops */ + i = first - 1; + j = last + 1; + + while(i < j) + { + /* The loop will stop as soon as the indices i and j cross each other. + * + * This event will happen surely since the values of the indices are incremented and + * decrement in the do-while loops that are executed at least once. + * It is impossible to loop forever inside the do-while loops since the pivot is + * always an element of the array and the conditions cannot be always true (at least + * the i-th or the j-th element will be equal to the pivot-th element). + * For example, in the extreme case of an ordered array the do-while loop related to i will stop + * at the first iteration (because pSrc[i]=pSrc[pivot] already), and the loop related to j + * will stop after (last-first) iterations (when j=pivot=i=first). j is returned and + * j+1 is going to be used as pivot by other calls of the function, until j=pivot=last. */ + + /* Move indices to the right and to the left */ + if(dir) + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] < pivot && i pivot); + } + else + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] > pivot && i Swap */ + temp=pSrc[i]; + pSrc[i]=pSrc[j]; + pSrc[j]=temp; + } + } + + return j; +} + +static void arm_quick_sort_core_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* If the array [first ... last] has more than one element */ + if(firstdir); + /* The previous function could be called recursively a maximum + * of (blockSize-1) times, generating a stack consumption of 4*(blockSize-1) bytes. */ +} + +/** + @} end of Sorting group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c new file mode 100644 index 0000000..7fa49ae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c @@ -0,0 +1,111 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_selection_sort_f32.c + * Description: Floating point selection sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The Selection sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted sublist + * (initially the sorted sublist is empty and the unsorted sublist + * is the input array), looks for the smallest (or biggest) + * element in the unsorted sublist, swapping it with the leftmost + * one, and moving the sublists boundary one element to the right. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void arm_selection_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i, j, k; + uint8_t dir = S->dir; + float32_t temp; + + float32_t * pA; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + /* Move the boundary one element to the right */ + for (i=0; ialg) + { + case ARM_SORT_BITONIC: + arm_bitonic_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_BUBBLE: + arm_bubble_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_HEAP: + arm_heap_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_INSERTION: + arm_insertion_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_QUICK: + arm_quick_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_SELECTION: + arm_selection_sort_f32(S, pSrc, pDst, blockSize); + break; + } +} + +/** + @} end of Sorting group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c new file mode 100644 index 0000000..7220b4c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c @@ -0,0 +1,58 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sort_init_f32.c + * Description: Floating point sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ +void arm_sort_init_f32(arm_sort_instance_f32 * S, arm_sort_alg alg, arm_sort_dir dir) +{ + S->alg = alg; + S->dir = dir; +} + +/** + @} end of Sorting group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c new file mode 100644 index 0000000..2c80545 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c @@ -0,0 +1,150 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_weighted_sum_f16.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupSupport + */ + +/** + @defgroup weightedsum Weighted Sum + + Weighted sum of values + */ + + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +float16_t arm_weighted_sum_f16(const float16_t *in,const float16_t *weigths, uint32_t blockSize) +{ + _Float16 accum1, accum2; + float16x8_t accum1V, accum2V; + float16x8_t inV, wV; + const float16_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + + accum1V = vdupq_n_f16(0.0f16); + accum2V = vdupq_n_f16(0.0f16); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + inV = vld1q(pIn); + wV = vld1q(pW); + + pIn += 4; + pW += 4; + + accum1V = vfmaq(accum1V, inV, wV); + accum2V = vaddq(accum2V, wV); + blkCnt--; + } + + accum1 = vecAddAcrossF16Mve(accum1V); + accum2 = vecAddAcrossF16Mve(accum2V); + + blkCnt = blockSize & 7; + while(blkCnt > 0) + { + accum1 += (_Float16)*pIn++ * (_Float16)*pW; + accum2 += (_Float16)*pW++; + blkCnt--; + } + + + return (accum1 / accum2); +} + +#else + +float16_t arm_weighted_sum_f16(const float16_t *in, const float16_t *weigths, uint32_t blockSize) +{ + + _Float16 accum1, accum2; + const float16_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f16; + accum2=0.0f16; + + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += (_Float16)*pIn++ * (_Float16)*pW; + accum2 += (_Float16)*pW++; + blkCnt--; + } + + return(accum1 / accum2); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of weightedsum group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c new file mode 100644 index 0000000..243378d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c @@ -0,0 +1,191 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_weighted_sum_f32.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/support_functions.h" + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" + +float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize) +{ + float32_t accum1, accum2; + f32x4_t accum1V, accum2V; + f32x4_t inV, wV; + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + + accum1V = vdupq_n_f32(0.0); + accum2V = vdupq_n_f32(0.0); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + inV = vld1q(pIn); + wV = vld1q(pW); + + pIn += 4; + pW += 4; + + accum1V = vfmaq(accum1V, inV, wV); + accum2V = vaddq(accum2V, wV); + blkCnt--; + } + + accum1 = vecAddAcrossF32Mve(accum1V); + accum2 = vecAddAcrossF32Mve(accum2V); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + + return (accum1 / accum2); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" +float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize) +{ + + float32_t accum1, accum2; + float32x4_t accum1V, accum2V; + float32x2_t tempV; + + float32x4_t inV,wV; + + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f; + accum2=0.0f; + + accum1V = vdupq_n_f32(0.0f); + accum2V = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + inV = vld1q_f32(pIn); + wV = vld1q_f32(pW); + + pIn += 4; + pW += 4; + + accum1V = vmlaq_f32(accum1V,inV,wV); + accum2V = vaddq_f32(accum2V,wV); + blkCnt--; + } + + tempV = vpadd_f32(vget_low_f32(accum1V),vget_high_f32(accum1V)); + accum1 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + tempV = vpadd_f32(vget_low_f32(accum2V),vget_high_f32(accum2V)); + accum2 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + + return(accum1 / accum2); +} +#else +float32_t arm_weighted_sum_f32(const float32_t *in, const float32_t *weigths, uint32_t blockSize) +{ + + float32_t accum1, accum2; + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f; + accum2=0.0f; + + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + return(accum1 / accum2); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of weightedsum group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c new file mode 100644 index 0000000..cc8e8b0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c @@ -0,0 +1,234 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + + +/** + @brief In-place floating-point bit reversal function. + @param[in,out] pSrc points to in-place floating-point data buffer + @param[in] fftSize length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none + */ + +void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float32_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + +/** + @brief In-place Q31 bit reversal function. + @param[in,out] pSrc points to in-place Q31 data buffer. + @param[in] fftLen length of FFT. + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint32_t fftLenBy2, fftLenBy2p1, i, j; + q31_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + + +/** + @brief In-place Q15 bit reversal function. + @param[in,out] pSrc16 points to in-place Q15 data buffer + @param[in] fftLen length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q15( + q15_t * pSrc16, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + q31_t *pSrc = (q31_t *) pSrc16; + q31_t in; + uint32_t fftLenBy2, fftLenBy2p1; + uint32_t i, j; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[i]; + pSrc[i] = pSrc[j]; + pSrc[j] = in; + + /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */ + /* pSrc[i + fftLenBy2p1+1U] <-> pSrc[j + fftLenBy2p1+1U] */ + in = pSrc[i + fftLenBy2p1]; + pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1]; + pSrc[j + fftLenBy2p1] = in; + } + + /* pSrc[i+1U] <-> pSrc[j+fftLenBy2]; */ + /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1U] */ + in = pSrc[i + 1U]; + pSrc[i + 1U] = pSrc[j + fftLenBy2]; + pSrc[j + fftLenBy2] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c new file mode 100644 index 0000000..e093aec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c @@ -0,0 +1,138 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal2.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + + +/** + @brief In-place 64 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 64-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_64( + uint64_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint64_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + +/** + @brief In-place 32 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_32( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint32_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + + +/** + @brief In-place 16 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_16( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint16_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c new file mode 100644 index 0000000..bd13013 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c @@ -0,0 +1,106 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal_f16.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" + +/* +* @brief In-place bit reversal function. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftSize length of the FFT. +* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. +* @param[in] *pBitRevTab points to the bit reversal table. +* @return none. +*/ + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_bitreversal_f16( +float16_t * pSrc, +uint16_t fftSize, +uint16_t bitRevFactor, +const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float16_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c new file mode 100644 index 0000000..ee4f926 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c @@ -0,0 +1,690 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_f32.c + * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h" + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h" + + +static float16_t arm_inverse_fft_length_f16(uint16_t fftLen) +{ + float16_t retValue=1.0; + + switch (fftLen) + { + + case 4096U: + retValue = (float16_t)0.000244140625f; + break; + + case 2048U: + retValue = (float16_t)0.00048828125f; + break; + + case 1024U: + retValue = (float16_t)0.0009765625f; + break; + + case 512U: + retValue = (float16_t)0.001953125f; + break; + + case 256U: + retValue = (float16_t)0.00390625f; + break; + + case 128U: + retValue = (float16_t)0.0078125f; + break; + + case 64U: + retValue = (float16_t)0.015625f; + break; + + case 32U: + retValue = (float16_t)0.03125f; + break; + + case 16U: + retValue = (float16_t)0.0625f; + break; + + + default: + break; + } + return(retValue); +} + + +static void _arm_radix4_butterfly_f16_mve(const arm_cfft_instance_f16 * S,float16_t * pSrc, uint32_t fftLen) +{ + f16x8_t vecTmp0, vecTmp1; + f16x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f16x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = + { ( 0 - 16) * (int32_t)sizeof(float16_t *) + , ( 4 - 16) * (int32_t)sizeof(float16_t *) + , ( 8 - 16) * (int32_t)sizeof(float16_t *) + , (12 - 16) * (int32_t)sizeof(float16_t *)}; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4u; k > 1; k >>= 2) + { + float16_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + float16_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float16_t *inA = pBase; + float16_t *inB = inA + n2 * CMPLX_DIM; + float16_t *inC = inB + n2 * CMPLX_DIM; + float16_t *inD = inC + n2 * CMPLX_DIM; + float16_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float16_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float16_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f16x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 2 f16 complex pair + */ + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_f16(inB); + vecD = vldrhq_f16(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 8; + + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 8; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 +=8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* load scheduling */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 4); + vecD = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 12); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + /* pre-load for next iteration */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + vecTmp0 = vecSum0 + vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64, (f32x4_t)vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 4, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 12, (f32x4_t)vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_f16_mve(const arm_cfft_instance_f16 * S, float16_t *pSrc, uint32_t fftLen) +{ + float16_t const *pCoefVec; + float16_t const *pCoef = S->pTwiddle; + float16_t *pIn0, *pIn1; + uint32_t n2; + uint32_t blkCnt; + f16x8_t vecIn0, vecIn1, vecSum, vecDiff; + f16x8_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + while (blkCnt > 0U) + { + vecIn0 = *(f16x8_t *) pIn0; + vecIn1 = *(f16x8_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecSum = vaddq(vecIn0, vecIn1); + vecDiff = vsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_Conj_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 8; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_f16_mve(S, pSrc, n2); + + _arm_radix4_butterfly_f16_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; +} + +static void _arm_radix4_butterfly_inverse_f16_mve(const arm_cfft_instance_f16 * S,float16_t * pSrc, uint32_t fftLen, float16_t onebyfftLen) +{ + f16x8_t vecTmp0, vecTmp1; + f16x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f16x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + ( 0 - 16) * (int32_t)sizeof(q31_t *), + ( 4 - 16) * (int32_t)sizeof(q31_t *), + ( 8 - 16) * (int32_t)sizeof(q31_t *), + (12 - 16) * (int32_t)sizeof(q31_t *) + }; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4; k > 1; k >>= 2) + { + float16_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float16_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float16_t *inA = pBase; + float16_t *inB = inA + n2 * CMPLX_DIM; + float16_t *inC = inB + n2 * CMPLX_DIM; + float16_t *inD = inC + n2 * CMPLX_DIM; + float16_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float16_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float16_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f16x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 2 f32 complex pair + */ + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_f16(inB); + vecD = vldrhq_f16(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 8; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 4); + vecD = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 12); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + vecTmp0 = vecSum0 + vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64, (f32x4_t)vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 4, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 12, (f32x4_t)vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_inverse_f16_mve(const arm_cfft_instance_f16 * S,float16_t *pSrc, uint32_t fftLen) +{ + float16_t const *pCoefVec; + float16_t const *pCoef = S->pTwiddle; + float16_t *pIn0, *pIn1; + uint32_t n2; + float16_t onebyfftLen = arm_inverse_fft_length_f16(fftLen); + uint32_t blkCnt; + f16x8_t vecIn0, vecIn1, vecSum, vecDiff; + f16x8_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + while (blkCnt > 0U) + { + vecIn0 = *(f16x8_t *) pIn0; + vecIn1 = *(f16x8_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecSum = vaddq(vecIn0, vecIn1); + vecDiff = vsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 8; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc, n2, onebyfftLen); + + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc + fftLen, n2, onebyfftLen); +} + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + + +void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc, fftLen, arm_inverse_fft_length_f16(S->fftLen)); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_f16_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_f16_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f16_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_16_inpl_mve((uint16_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +extern void arm_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + + +extern void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + +extern void arm_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float16_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f16 ( p1, L, (float16_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + arm_bitreversal_16((uint16_t*)p1, S->bitRevLength,(uint16_t*)S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f16/(_Float16)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; l>= 2u; + for (int k = fftLen / 4u; k > 1; k >>= 2) + { + float32_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float32_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float32_t *inA = pBase; + float32_t *inB = inA + n2 * CMPLX_DIM; + float32_t *inC = inB + n2 * CMPLX_DIM; + float32_t *inD = inC + n2 * CMPLX_DIM; + float32_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float32_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float32_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f32x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 f32 complex pair + */ + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_f32(inB); + vecD = vldrwq_f32(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 4; + + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 4; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 +=4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 4; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* load scheduling */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = vldrwq_gather_base_f32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_f32(vecScGathAddr, 24); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + /* pre-load for next iteration */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + vecTmp0 = vecSum0 + vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_f32_mve(const arm_cfft_instance_f32 * S, float32_t *pSrc, uint32_t fftLen) +{ + float32_t const *pCoefVec; + float32_t const *pCoef = S->pTwiddle; + float32_t *pIn0, *pIn1; + uint32_t n2; + uint32_t blkCnt; + f32x4_t vecIn0, vecIn1, vecSum, vecDiff; + f32x4_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 2; + while (blkCnt > 0U) + { + vecIn0 = *(f32x4_t *) pIn0; + vecIn1 = *(f32x4_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 4; + + vecSum = vecIn0 + vecIn1; + vecDiff = vecIn0 - vecIn1; + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_Conj_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 4; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_f32_mve(S, pSrc, n2); + + _arm_radix4_butterfly_f32_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; +} + +static void _arm_radix4_butterfly_inverse_f32_mve(const arm_cfft_instance_f32 * S,float32_t * pSrc, uint32_t fftLen, float32_t onebyfftLen) +{ + f32x4_t vecTmp0, vecTmp1; + f32x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f32x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), + (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), + (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4; k > 1; k >>= 2) + { + float32_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float32_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float32_t *inA = pBase; + float32_t *inB = inA + n2 * CMPLX_DIM; + float32_t *inC = inB + n2 * CMPLX_DIM; + float32_t *inD = inC + n2 * CMPLX_DIM; + float32_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float32_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float32_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f32x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 f32 complex pair + */ + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_f32(inB); + vecD = vldrwq_f32(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 4; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 4; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32 ((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = vldrwq_gather_base_f32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_f32(vecScGathAddr, 24); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + vecTmp0 = vecSum0 + vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_inverse_f32_mve(const arm_cfft_instance_f32 * S,float32_t *pSrc, uint32_t fftLen) +{ + float32_t const *pCoefVec; + float32_t const *pCoef = S->pTwiddle; + float32_t *pIn0, *pIn1; + uint32_t n2; + float32_t onebyfftLen = arm_inverse_fft_length_f32(fftLen); + uint32_t blkCnt; + f32x4_t vecIn0, vecIn1, vecSum, vecDiff; + f32x4_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 2; + while (blkCnt > 0U) + { + vecIn0 = *(f32x4_t *) pIn0; + vecIn1 = *(f32x4_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 4; + + vecSum = vecIn0 + vecIn1; + vecDiff = vecIn0 - vecIn1; + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 4; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc, n2, onebyfftLen); + + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc + fftLen, n2, onebyfftLen); +} + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + + +void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc, fftLen, arm_inverse_fft_length_f32(S->fftLen)); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_f32_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_f32_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f32_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_32_inpl_mve((uint32_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + + +#else +extern void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/** + @ingroup groupTransforms + */ + +/** + @defgroup ComplexFFT Complex FFT Functions + + @par + The Fast Fourier Transform (FFT) is an efficient algorithm for computing the + Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster + than the DFT, especially for long lengths. + The algorithms described in this section + operate on complex data. A separate set of functions is devoted to handling + of real sequences. + @par + There are separate algorithms for handling floating-point, Q15, and Q31 data + types. The algorithms available for each data type are described next. + @par + The FFT functions operate in-place. That is, the array holding the input data + will also be used to hold the corresponding result. The input data is complex + and contains 2*fftLen interleaved values as shown below. + 
{real[0], imag[0], real[1], imag[1], ...}
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + For the MVE version, the new arm_cfft_init_f32 initialization function is + mandatory. Compilation flags are available to include only the required tables for the + needed FFTs. Other FFT versions can continue to be initialized as + explained below. + @par + For not MVE versions, pre-initialized data structures containing twiddle factors + and bit reversal tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_f32. For example: + @par + arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_f32 function follows: + @code + const static arm_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_f32_len16; + break; + case 32: + S = &arm_cfft_sR_f32_len32; + break; + case 64: + S = &arm_cfft_sR_f32_len64; + break; + case 128: + S = &arm_cfft_sR_f32_len128; + break; + case 256: + S = &arm_cfft_sR_f32_len256; + break; + case 512: + S = &arm_cfft_sR_f32_len512; + break; + case 1024: + S = &arm_cfft_sR_f32_len1024; + break; + case 2048: + S = &arm_cfft_sR_f32_len2048; + break; + case 4096: + S = &arm_cfft_sR_f32_len4096; + break; + } + @endcode + + @par + The new arm_cfft_init_f32 can also be used. + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_q31. For example: + @par + arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_q31 function follows: + @code + const static arm_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_q31_len16; + break; + case 32: + S = &arm_cfft_sR_q31_len32; + break; + case 64: + S = &arm_cfft_sR_q31_len64; + break; + case 128: + S = &arm_cfft_sR_q31_len128; + break; + case 256: + S = &arm_cfft_sR_q31_len256; + break; + case 512: + S = &arm_cfft_sR_q31_len512; + break; + case 1024: + S = &arm_cfft_sR_q31_len1024; + break; + case 2048: + S = &arm_cfft_sR_q31_len2048; + break; + case 4096: + S = &arm_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + +void arm_cfft_radix8by2_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen; + float32_t * pCol1, * pCol2, * pMid1, * pMid2; + float32_t * p2 = p1 + L; + const float32_t * tw = (float32_t *) S->pTwiddle; + float32_t t1[4], t2[4], t3[4], t4[4], twR, twI; + float32_t m0, m1, m2, m3; + uint32_t l; + + pCol1 = p1; + pCol2 = p2; + + /* Define new length */ + L >>= 1; + + /* Initialize mid pointers */ + pMid1 = p1 + L; + pMid2 = p2 + L; + + /* do two dot Fourier transform */ + for (l = L >> 2; l > 0; l-- ) + { + t1[0] = p1[0]; + t1[1] = p1[1]; + t1[2] = p1[2]; + t1[3] = p1[3]; + + t2[0] = p2[0]; + t2[1] = p2[1]; + t2[2] = p2[2]; + t2[3] = p2[3]; + + t3[0] = pMid1[0]; + t3[1] = pMid1[1]; + t3[2] = pMid1[2]; + t3[3] = pMid1[3]; + + t4[0] = pMid2[0]; + t4[1] = pMid2[1]; + t4[2] = pMid2[2]; + t4[3] = pMid2[3]; + + *p1++ = t1[0] + t2[0]; + *p1++ = t1[1] + t2[1]; + *p1++ = t1[2] + t2[2]; + *p1++ = t1[3] + t2[3]; /* col 1 */ + + t2[0] = t1[0] - t2[0]; + t2[1] = t1[1] - t2[1]; + t2[2] = t1[2] - t2[2]; + t2[3] = t1[3] - t2[3]; /* for col 2 */ + + *pMid1++ = t3[0] + t4[0]; + *pMid1++ = t3[1] + t4[1]; + *pMid1++ = t3[2] + t4[2]; + *pMid1++ = t3[3] + t4[3]; /* col 1 */ + + t4[0] = t4[0] - t3[0]; + t4[1] = t4[1] - t3[1]; + t4[2] = t4[2] - t3[2]; + t4[3] = t4[3] - t3[3]; /* for col 2 */ + + twR = *tw++; + twI = *tw++; + + /* multiply by twiddle factors */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + /* R = R * Tr - I * Ti */ + *p2++ = m0 + m1; + /* I = I * Tr + R * Ti */ + *p2++ = m2 - m3; + + /* use vertical symmetry */ + /* 0.9988 - 0.0491i <==> -0.0491 - 0.9988i */ + m0 = t4[0] * twI; + m1 = t4[1] * twR; + m2 = t4[1] * twI; + m3 = t4[0] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + + twR = *tw++; + twI = *tw++; + + m0 = t2[2] * twR; + m1 = t2[3] * twI; + m2 = t2[3] * twR; + m3 = t2[2] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + + m0 = t4[2] * twI; + m1 = t4[3] * twR; + m2 = t4[3] * twI; + m3 = t4[2] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + } + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 2U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 2U); +} + +void arm_cfft_radix8by4_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen >> 1; + float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4; + const float32_t *tw2, *tw3, *tw4; + float32_t * p2 = p1 + L; + float32_t * p3 = p2 + L; + float32_t * p4 = p3 + L; + float32_t t2[4], t3[4], t4[4], twR, twI; + float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1; + float32_t m0, m1, m2, m3; + uint32_t l, twMod2, twMod3, twMod4; + + pCol1 = p1; /* points to real values by default */ + pCol2 = p2; + pCol3 = p3; + pCol4 = p4; + pEnd1 = p2 - 1; /* points to imaginary values by default */ + pEnd2 = p3 - 1; + pEnd3 = p4 - 1; + pEnd4 = pEnd3 + L; + + tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle; + + L >>= 1; + + /* do four dot Fourier transform */ + + twMod2 = 2; + twMod3 = 4; + twMod4 = 6; + + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* Twiddle factors are ones */ + *p2++ = t2[0]; + *p2++ = t2[1]; + *p3++ = t3[0]; + *p3++ = t3[1]; + *p4++ = t4[0]; + *p4++ = t4[1]; + + tw2 += twMod2; + tw3 += twMod3; + tw4 += twMod4; + + for (l = (L - 2) >> 1; l > 0; l-- ) + { + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* BOTTOM */ + p1ap3_1 = pEnd1[-1] + pEnd3[-1]; + p1sp3_1 = pEnd1[-1] - pEnd3[-1]; + p1ap3_0 = pEnd1[ 0] + pEnd3[0]; + p1sp3_0 = pEnd1[ 0] - pEnd3[0]; + /* col 2 */ + t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1; + t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1]; + /* col 3 */ + t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1]; + t3[3] = p1ap3_0 - pEnd2[ 0] - pEnd4[ 0]; + /* col 4 */ + t4[2] = pEnd2[ 0] - pEnd4[ 0] - p1sp3_1; + t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0; + /* col 1 - Bottom */ + *pEnd1-- = p1ap3_0 + pEnd2[ 0] + pEnd4[ 0]; + *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1]; + + /* COL 2 */ + /* read twiddle factors */ + twR = *tw2++; + twI = *tw2++; + /* multiply by twiddle factors */ + /* let Z1 = a + i(b), Z2 = c + i(d) */ + /* => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d) */ + + /* Top */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* use vertical symmetry col 2 */ + /* 0.9997 - 0.0245i <==> 0.0245 - 0.9997i */ + /* Bottom */ + m0 = t2[3] * twI; + m1 = t2[2] * twR; + m2 = t2[2] * twI; + m3 = t2[3] * twR; + + *pEnd2-- = m0 - m1; + *pEnd2-- = m2 + m3; + + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + tw3 += twMod3; + /* Top */ + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* use vertical symmetry col 3 */ + /* 0.9988 - 0.0491i <==> -0.9988 - 0.0491i */ + /* Bottom */ + m0 = -t3[3] * twR; + m1 = t3[2] * twI; + m2 = t3[2] * twR; + m3 = t3[3] * twI; + + *pEnd3-- = m0 - m1; + *pEnd3-- = m3 - m2; + + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + tw4 += twMod4; + /* Top */ + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + /* use vertical symmetry col 4 */ + /* 0.9973 - 0.0736i <==> -0.0736 + 0.9973i */ + /* Bottom */ + m0 = t4[3] * twI; + m1 = t4[2] * twR; + m2 = t4[2] * twI; + m3 = t4[3] * twR; + + *pEnd4-- = m0 - m1; + *pEnd4-- = m2 + m3; + } + + /* MIDDLE */ + /* Twiddle factors are */ + /* 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - Top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* COL 2 */ + twR = tw2[0]; + twI = tw2[1]; + + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 4U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 4U); + + /* third col */ + arm_radix8_butterfly_f32 (pCol3, L, (float32_t *) S->pTwiddle, 4U); + + /* fourth col */ + arm_radix8_butterfly_f32 (pCol4, L, (float32_t *) S->pTwiddle, 4U); +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float32_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for (l = 0; l < L; l++) + { + *pSrc = -*pSrc; + pSrc += 2; + } + } + + switch (L) + { + case 16: + case 128: + case 1024: + arm_cfft_radix8by2_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 32: + case 256: + case 2048: + arm_cfft_radix8by4_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 64: + case 512: + case 4096: + arm_radix8_butterfly_f32 ( p1, L, (float32_t *) S->pTwiddle, 1); + break; + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f / (float32_t)L; + + /* Conjugate and scale output data */ + pSrc = p1; + for (l= 0; l < L; l++) + { + *pSrc++ *= invL ; + *pSrc = -(*pSrc) * invL; + pSrc++; + } + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c new file mode 100644 index 0000000..83b2cd3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c @@ -0,0 +1,318 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_f64.c + * Description: Combined Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + + +extern void arm_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_bitreversal_64( + uint64_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier) +{ + + float64_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + + float64_t t1, t2, r1, r2, s1, s2; + + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } +} + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_cfft_radix4by2_f64( + float64_t * pSrc, + uint32_t fftLen, + const float64_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float64_t xt, yt, cosVal, sinVal; + float64_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + } + + // first col + arm_radix4_butterfly_f64( pSrc, n2, (float64_t*)pCoef, 2U); + // second col + arm_radix4_butterfly_f64( pSrc + fftLen, n2, (float64_t*)pCoef, 2U); + +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Double Precision floating-point complex FFT. + @param[in] S points to an instance of the Double Precision floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float64_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f64 ( p1, L, (float64_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + arm_bitreversal_64((uint64_t*)p1, S->bitRevLength,S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0 / (float64_t)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; lbitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f16 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h" + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables_f16.h" + +arm_status arm_cfft_radix4by2_rearrange_twiddles_f16(arm_cfft_instance_f16 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_f16; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_f16; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_f16; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_f16; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_f16; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + +arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_F16_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (float16_t *)twiddleCoefF16_4096; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F16_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (float16_t *)twiddleCoefF16_2048; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F16_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (float16_t *)twiddleCoefF16_1024; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_F16_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (float16_t *)twiddleCoefF16_512; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_F16_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (float16_t *)twiddleCoefF16_256; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_F16_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (float16_t *)twiddleCoefF16_128; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_F16_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (float16_t *)twiddleCoefF16_64; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_F16_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (float16_t *)twiddleCoefF16_32; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_F16_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (float16_t *)twiddleCoefF16_16; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f16,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f16,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f16,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f16,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f16,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c new file mode 100644 index 0000000..b82f5ce --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c @@ -0,0 +1,362 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_f32.c + * Description: Initialization function for cfft f32 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f32 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h" + +arm_status arm_cfft_radix4by2_rearrange_twiddles_f32(arm_cfft_instance_f32 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_f32; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_f32; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_f32; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_f32; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_f32; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + +arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_F32_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (float32_t *)twiddleCoef_4096; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F32_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (float32_t *)twiddleCoef_2048; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F32_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (float32_t *)twiddleCoef_1024; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_F32_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (float32_t *)twiddleCoef_512; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_F32_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (float32_t *)twiddleCoef_256; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_F32_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (float32_t *)twiddleCoef_128; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_F32_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (float32_t *)twiddleCoef_64; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_F32_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (float32_t *)twiddleCoef_32; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_F32_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (float32_t *)twiddleCoef_16; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f32,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f32,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f32,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f32,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f32,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c new file mode 100644 index 0000000..cb2dae8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c @@ -0,0 +1,154 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_f64.c + * Description: Initialization function for cfft f64 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f64 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" + + +arm_status arm_cfft_init_f64( + arm_cfft_instance_f64 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f64,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f64,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f64,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f64,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f64,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c new file mode 100644 index 0000000..a0f6356 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c @@ -0,0 +1,360 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_q15.c + * Description: Initialization function for cfft q15 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q15 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h" + + +arm_status arm_cfft_radix4by2_rearrange_twiddles_q15(arm_cfft_instance_q15 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_q15; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_q15; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256)) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512)) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_q15; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64)) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128)) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_q15; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16)) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32)) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_q15; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + + + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (q15_t *)twiddleCoef_4096_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (q15_t *)twiddleCoef_2048_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (q15_t *)twiddleCoef_1024_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (q15_t *)twiddleCoef_512_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (q15_t *)twiddleCoef_256_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (q15_t *)twiddleCoef_128_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (q15_t *)twiddleCoef_64_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (q15_t *)twiddleCoef_32_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (q15_t *)twiddleCoef_16_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q15,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q15,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q15,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q15,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q15,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c new file mode 100644 index 0000000..0877d2c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c @@ -0,0 +1,360 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_q31.c + * Description: Initialization function for cfft q31 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q31 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_mve_tables.h" + + +arm_status arm_cfft_radix4by2_rearrange_twiddles_q31(arm_cfft_instance_q31 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_q31; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_q31; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256)) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512)) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_q31; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64)) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128)) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_q31; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16)) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32)) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_q31; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + + + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (q31_t *)twiddleCoef_4096_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (q31_t *)twiddleCoef_2048_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (q31_t *)twiddleCoef_1024_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (q31_t *)twiddleCoef_512_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (q31_t *)twiddleCoef_256_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (q31_t *)twiddleCoef_128_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (q31_t *)twiddleCoef_64_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (q31_t *)twiddleCoef_32_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (q31_t *)twiddleCoef_16_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q31,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q31,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q31,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q31,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q31,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c new file mode 100644 index 0000000..83ca024 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c @@ -0,0 +1,897 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q15.c + * Description: Combined Radix Decimation in Q15 Frequency CFFT processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" + + +static void _arm_radix4_butterfly_q15_mve( + const arm_cfft_instance_q15 * S, + q15_t *pSrc, + uint32_t fftLen) +{ + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q15x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q15_t *), (4 - 16) * (int32_t)sizeof(q15_t *), + (8 - 16) * (int32_t)sizeof(q15_t *), (12 - 16) * (int32_t)sizeof(q15_t *) + }; + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q15_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q15_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q15_t *inA = pBase; + q15_t *inB = inA + n2 * CMPLX_DIM; + q15_t *inC = inB + n2 * CMPLX_DIM; + q15_t *inD = inC + n2 * CMPLX_DIM; + q15_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q15_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q15_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q15x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 4 x q15 complex pair + */ + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_s16(inB); + vecD = vldrhq_s16(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + + vst1q(inB, vecTmp1); + inB += 8; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32 ((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 4); + vecD = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 12); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, (int32x4_t) vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 4, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 12, (int32x4_t) vecTmp0); + + blkCnt--; + } + +} + +static void arm_cfft_radix4by2_q15_mve(const arm_cfft_instance_q15 *S, q15_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q15_t *pIn0; + q15_t *pIn1; + const q15_t *pCoef = S->pTwiddle; + uint32_t blkCnt; + q15x8_t vecIn0, vecIn1, vecSum, vecDiff; + q15x8_t vecCmplxTmp, vecTw; + q15_t const *pCoefVec; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn1 = *(q15x8_t *) pIn1; + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 8; + + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecDiff = vhsubq(vecIn0, vecIn1); + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxConjB(vecDiff, vecTw, q15x8_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_q15_mve(S, pSrc, n2); + + _arm_radix4_butterfly_q15_mve(S, pSrc + fftLen, n2); + + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 3; + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 8; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vstrhq_p(pIn0, vecIn0, p0); + } +} + +static void _arm_radix4_butterfly_inverse_q15_mve(const arm_cfft_instance_q15 *S,q15_t *pSrc, uint32_t fftLen) +{ + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q15x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q15_t *), (4 - 16) * (int32_t)sizeof(q15_t *), + (8 - 16) * (int32_t)sizeof(q15_t *), (12 - 16) * (int32_t)sizeof(q15_t *) + }; + + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q15_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q15_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q15_t *inA = pBase; + q15_t *inB = inA + n2 * CMPLX_DIM; + q15_t *inC = inB + n2 * CMPLX_DIM; + q15_t *inD = inC + n2 * CMPLX_DIM; + q15_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q15_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q15_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q15x8_t vecW; + + + blkCnt = n2 / 4; + /* + * load 4 x q15 complex pair + */ + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_s16(inB); + vecD = vldrhq_s16(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + + vst1q(inB, vecTmp1); + inB += 8; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + vst1q(inC, vecTmp1); + inC += 8; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 4); + vecD = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 12); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, (int32x4_t) vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 4, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 12, (int32x4_t) vecTmp0); + + blkCnt--; + } +} + +static void arm_cfft_radix4by2_inverse_q15_mve(const arm_cfft_instance_q15 *S, q15_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q15_t *pIn0; + q15_t *pIn1; + const q15_t *pCoef = S->pTwiddle; + + uint32_t blkCnt; + q15x8_t vecIn0, vecIn1, vecSum, vecDiff; + q15x8_t vecCmplxTmp, vecTw; + q15_t const *pCoefVec; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn1 = *(q15x8_t *) pIn1; + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 8; + + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecDiff = vhsubq(vecIn0, vecIn1); + vecCmplxTmp = vqrdmlsdhq(vuninitializedq_s16() , vecDiff, vecTw); + vecCmplxTmp = vqrdmladhxq(vecCmplxTmp, vecDiff, vecTw); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc, n2); + + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 3; + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 8; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 7; + while (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vstrhq_p(pIn0, vecIn0, p0); + } +} + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q15_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_q15_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q15_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_16_inpl_mve((uint16_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + +#else + +extern void arm_radix4_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q15 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_16 ((uint16_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia (&pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16U; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 ) ); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } + +} + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia (&pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16U; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 )); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } +} + +#endif /* defined(ARM_MATH_MVEI) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c new file mode 100644 index 0000000..373e8a7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c @@ -0,0 +1,851 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q31.c + * Description: Combined Radix Decimation in Frequency CFFT fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" + + +static void _arm_radix4_butterfly_q31_mve( + const arm_cfft_instance_q31 * S, + q31_t *pSrc, + uint32_t fftLen) +{ + q31x4_t vecTmp0, vecTmp1; + q31x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q31x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q31_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q31_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q31_t *inA = pBase; + q31_t *inB = inA + n2 * CMPLX_DIM; + q31_t *inC = inB + n2 * CMPLX_DIM; + q31_t *inD = inC + n2 * CMPLX_DIM; + q31_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q31_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q31_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q31x4_t vecW; + + + blkCnt = n2 / 2; + /* + * load 2 x q31 complex pair + */ + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_s32(inB); + vecD = vldrwq_s32(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + + vst1q(inB, vecTmp1); + inB += 4; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + vst1q(inC, vecTmp1); + inC += 4; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * End of 1st stages process + * data is in 11.21(q21) format for the 1024 point as there are 3 middle stages + * data is in 9.23(q23) format for the 256 point as there are 2 middle stages + * data is in 7.25(q25) format for the 64 point as there are 1 middle stage + * data is in 5.27(q27) format for the 16 point as there are no middle stages + */ + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = vldrwq_gather_base_s32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_s32(vecScGathAddr, 24); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * output is in 11.21(q21) format for the 1024 point + * output is in 9.23(q23) format for the 256 point + * output is in 7.25(q25) format for the 64 point + * output is in 5.27(q27) format for the 16 point + */ +} + + +static void arm_cfft_radix4by2_q31_mve(const arm_cfft_instance_q31 *S, q31_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q31_t *pIn0; + q31_t *pIn1; + const q31_t *pCoef = S->pTwiddle; + uint32_t blkCnt; + q31x4_t vecIn0, vecIn1, vecSum, vecDiff; + q31x4_t vecCmplxTmp, vecTw; + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + + blkCnt = n2 / 2; + + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn1 = vld1q_s32(pIn1); + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 4; + + vecTw = vld1q_s32(pCoef); + pCoef += 4; + vecDiff = vhsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxConjB(vecDiff, vecTw, q31x4_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_q31_mve(S, pSrc, n2); + + _arm_radix4_butterfly_q31_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 2; + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 4; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vstrwq_p(pIn0, vecIn0, p0); + } + +} + +static void _arm_radix4_butterfly_inverse_q31_mve( + const arm_cfft_instance_q31 *S, + q31_t *pSrc, + uint32_t fftLen) +{ + q31x4_t vecTmp0, vecTmp1; + q31x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q31x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q31_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q31_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q31_t *inA = pBase; + q31_t *inB = inA + n2 * CMPLX_DIM; + q31_t *inC = inB + n2 * CMPLX_DIM; + q31_t *inD = inC + n2 * CMPLX_DIM; + q31_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q31_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q31_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q31x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 x q31 complex pair + */ + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_s32(inB); + vecD = vldrwq_s32(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + + vst1q(inB, vecTmp1); + inB += 4; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + vst1q(inC, vecTmp1); + inC += 4; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * End of 1st stages process + * data is in 11.21(q21) format for the 1024 point as there are 3 middle stages + * data is in 9.23(q23) format for the 256 point as there are 2 middle stages + * data is in 7.25(q25) format for the 64 point as there are 1 middle stage + * data is in 5.27(q27) format for the 16 point as there are no middle stages + */ + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = vldrwq_gather_base_s32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_s32(vecScGathAddr, 24); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + /* + * output is in 11.21(q21) format for the 1024 point + * output is in 9.23(q23) format for the 256 point + * output is in 7.25(q25) format for the 64 point + * output is in 5.27(q27) format for the 16 point + */ +} + +static void arm_cfft_radix4by2_inverse_q31_mve(const arm_cfft_instance_q31 *S, q31_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q31_t *pIn0; + q31_t *pIn1; + const q31_t *pCoef = S->pTwiddle; + + //uint16_t twidCoefModifier = arm_cfft_radix2_twiddle_factor(S->fftLen); + //q31_t twidIncr = (2 * twidCoefModifier * sizeof(q31_t)); + uint32_t blkCnt; + //uint64x2_t vecOffs; + q31x4_t vecIn0, vecIn1, vecSum, vecDiff; + q31x4_t vecCmplxTmp, vecTw; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + //vecOffs[0] = 0; + //vecOffs[1] = (uint64_t) twidIncr; + blkCnt = n2 / 2; + + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn1 = vld1q_s32(pIn1); + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 4; + + //vecTw = (q31x4_t) vldrdq_gather_offset_s64(pCoef, vecOffs); + vecTw = vld1q_s32(pCoef); + pCoef += 4; + vecDiff = vhsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxB(vecDiff, vecTw, q31x4_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + //vecOffs = vaddq((q31x4_t) vecOffs, 2 * twidIncr); + blkCnt--; + } + + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc, n2); + + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 2; + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 4; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vstrwq_p(pIn0, vecIn0, p0); + } + +} + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q31_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_q31_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q31_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_32_inpl_mve((uint32_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} +#else + +extern void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q31 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q31 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1; + pSrc[2 * l + 1] = p1 << 1; + } + + + /* first col */ + arm_radix4_butterfly_q31 (pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q31 (pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } + +} + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1U; + pSrc[2 * l + 1] = p1 << 1U; + } + + /* first col */ + arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c new file mode 100644 index 0000000..c95a01f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c @@ -0,0 +1,479 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_f16.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_radix2_butterfly_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + +extern void arm_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_f16( +const arm_cfft_radix2_instance_f16 * S, + float16_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + arm_radix2_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + arm_radix2_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- +** Internal helper function used by the FFTs +** ------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix2_butterfly_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (ARM_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * i + 2]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * i + 2]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * i + 3]; + a1 = (_Float16)pSrc[2 * i + 3] + (_Float16)pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif // #if defined (ARM_MATH_DSP) + +} + + +void arm_radix2_butterfly_inverse_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (ARM_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * i + 2]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * i + 2]; + + a1 = (_Float16)pSrc[2 * i + 3] + (_Float16)pSrc[2 * i + 1]; + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * i + 3]; + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p2 = (_Float16)xt * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p3 = (_Float16)yt * (_Float16)onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p2 = (_Float16)xt * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p3 = (_Float16)yt * (_Float16)onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2U * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2U * l + 1U] = p3; + } // butterfly loop end + +#endif // #if defined (ARM_MATH_DSP) + +} + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c new file mode 100644 index 0000000..dba45f4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c @@ -0,0 +1,474 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_f32.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_f32( +const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- + ** Internal helper function used by the FFTs + ** ------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2 * l + 1] = p3; + } // butterfly loop end + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c new file mode 100644 index 0000000..17e7c80 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c @@ -0,0 +1,218 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_f16.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_radix2_init_f16( + arm_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16_4096; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c new file mode 100644 index 0000000..71fba78 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c @@ -0,0 +1,213 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_f32.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c new file mode 100644 index 0000000..f07cad4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c @@ -0,0 +1,198 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q15.c + * Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + S->twidCoefModifier = 8U; + S->bitRevFactor = 8U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c new file mode 100644 index 0000000..5823559 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c @@ -0,0 +1,195 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q31.c + * Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c new file mode 100644 index 0000000..49f6d9d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c @@ -0,0 +1,693 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q15.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + i += n1; + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* groups loop end */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16)) ); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* groups loop end */ + + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c new file mode 100644 index 0000000..6f36181 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c @@ -0,0 +1,341 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q31.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l, m; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + m = fftLen / n1; + do + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + i += n1; + m--; + } while ( m > 0); // butterfly loop end + + } // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} + + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // butterfly loop end + + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c new file mode 100644 index 0000000..4c46bc1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c @@ -0,0 +1,1276 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_f16.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +extern void arm_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + + +void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + } + + // first col + arm_radix4_butterfly_f16( pSrc, n2, (float16_t*)pCoef, 2U); + // second col + arm_radix4_butterfly_f16( pSrc + fftLen, n2, (float16_t*)pCoef, 2U); + +} + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix4_f16( + const arm_cfft_radix4_instance_f16 * S, + float16_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix4_butterfly_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_DSP) + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* xb - xd */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* yb - yd */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out += (_Float16)p0; + Yb12_out -= (_Float16)p1; + Xc12_out += (_Float16)p2; + Yc12_out -= (_Float16)p3; + Xd12_out += (_Float16)p4; + Yd12_out -= (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* (xb - xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* (yb - yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out += (_Float16)p0; + Yb12_out -= (_Float16)p1; + Xc12_out += (_Float16)p2; + Yc12_out -= (_Float16)p3; + Xd12_out += (_Float16)p4; + Yd12_out -= (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xb-xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + + /* (yb-yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = ((_Float16)Xaplusc + (_Float16)Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = ((_Float16)Yaplusc + (_Float16)Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for Cortex-M0 */ + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = (_Float16)pSrc[(2U * i0)] + (_Float16)pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = (_Float16)pSrc[(2U * i0)] - (_Float16)pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (_Float16)r1 + (_Float16)t1; + + /* xa + xc -(xb + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)s1 + (_Float16)t2; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb - yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = ((_Float16)r1 * (_Float16)co2) + ((_Float16)s1 * (_Float16)si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = ((_Float16)s1 * (_Float16)co2) - ((_Float16)r1 * (_Float16)si2); + + /* (xa - xc) + (yb - yd) */ + r1 = (_Float16)r2 + (_Float16)t1; + + /* (xa - xc) - (yb - yd) */ + r2 = (_Float16)r2 - (_Float16)t1; + + /* (ya - yc) - (xb - xd) */ + s1 = (_Float16)s2 - (_Float16)t2; + + /* (ya - yc) + (xb - xd) */ + s2 = (_Float16)s2 + (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = ((_Float16)r1 * (_Float16)co1) + ((_Float16)s1 * (_Float16)si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = ((_Float16)s1 * (_Float16)co1) - ((_Float16)r1 * (_Float16)si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = ((_Float16)r2 * (_Float16)co3) + ((_Float16)s2 * (_Float16)si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = ((_Float16)s2 * (_Float16)co3) - ((_Float16)r2 * (_Float16)si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/* +* @brief Core function for the floating-point CIFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @param[in] onebyfftLen value of 1/fftLen. +* @return none. +*/ + +void arm_radix4_butterfly_inverse_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_DSP) + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5,p6,p7; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* xb - xd */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* yb - yd */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 =(_Float16) Xd12C_out * (_Float16)si3; + + Xb12_out -= (_Float16)p0; + Yb12_out += (_Float16)p1; + Xc12_out -= (_Float16)p2; + Yc12_out += (_Float16)p3; + Xd12_out -= (_Float16)p4; + Yd12_out += (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* (xb - xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* (yb - yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out -= (_Float16)p0; + Yb12_out += (_Float16)p1; + Xc12_out -= (_Float16)p2; + Yc12_out += (_Float16)p3; + Xd12_out -= (_Float16)p4; + Yd12_out += (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xb-xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + + /* (yb-yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = ((_Float16)Xaplusc + (_Float16)Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = ((_Float16)Yaplusc + (_Float16)Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p2 = (_Float16)a2 * (_Float16)onebyfftLen; + p3 = (_Float16)a3 * (_Float16)onebyfftLen; + p4 = (_Float16)a4 * (_Float16)onebyfftLen; + p5 = (_Float16)a5 * (_Float16)onebyfftLen; + p6 = (_Float16)a6 * (_Float16)onebyfftLen; + p7 = (_Float16)a7 * (_Float16)onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for Cortex-M0 */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = (_Float16)pSrc[(2U * i0)] + (_Float16)pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = (_Float16)pSrc[(2U * i0)] - (_Float16)pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (_Float16)r1 + (_Float16)t1; + + /* xa + xc -(xb + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)s1 + (_Float16)t2; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb - yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = ((_Float16)r1 * (_Float16)co2) - ((_Float16)s1 * (_Float16)si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = ((_Float16)s1 * (_Float16)co2) + ((_Float16)r1 * (_Float16)si2); + + /* (xa - xc) - (yb - yd) */ + r1 = (_Float16)r2 - (_Float16)t1; + + /* (xa - xc) + (yb - yd) */ + r2 = (_Float16)r2 + (_Float16)t1; + + /* (ya - yc) + (xb - xd) */ + s1 = (_Float16)s2 + (_Float16)t2; + + /* (ya - yc) - (xb - xd) */ + s2 = (_Float16)s2 - (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = ((_Float16)r1 * (_Float16)co1) - ((_Float16)s1 * (_Float16)si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = ((_Float16)s1 * (_Float16)co1) + ((_Float16)r1 * (_Float16)si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = ((_Float16)r2 * (_Float16)co3) - ((_Float16)s2 * (_Float16)si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = ((_Float16)s2 * (_Float16)co3) + ((_Float16)r2 * (_Float16)si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (_Float16)pSrc[2U * i0] + (_Float16)pSrc[2U * i2]; + + /* xa - xc */ + r2 = (_Float16)pSrc[2U * i0] - (_Float16)pSrc[2U * i2]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = ((_Float16)r1 + (_Float16)t1) * (_Float16)onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = ((_Float16)s1 + (_Float16)t2) * (_Float16)onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb-yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (_Float16)r1 * (_Float16)onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (_Float16)s1 * (_Float16)onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = (_Float16)r2 - (_Float16)t1; + + /* (xa - xc) + (yb-yd) */ + r2 = (_Float16)r2 + (_Float16)t1; + + /* (ya - yc) + (xb-xd) */ + s1 = (_Float16)s2 + (_Float16)t2; + + /* (ya - yc) - (xb-xd) */ + s2 = (_Float16)s2 - (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (_Float16)r1 * (_Float16)onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (_Float16)s1 * (_Float16)onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (_Float16)r2 * (_Float16)onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (_Float16)s2 * (_Float16)onebyfftLen; + } + +#endif /* #if defined (ARM_MATH_DSP) */ +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c new file mode 100644 index 0000000..4c7020a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c @@ -0,0 +1,1207 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_f32.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to the twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = (Xaplusc + Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = (Xaminusc + Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = (Yaminusc - Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = (Xaminusc - Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = (Xbminusd + Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + brief Core function for the floating-point CIFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + param[in] onebyfftLen value of 1/fftLen + return none + */ + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5,p6,p7; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = (Xaplusc + Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = (Xaminusc - Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = (Yaminusc + Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = (Xaminusc + Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = (Yaminusc - Xbminusd); + + p0 = a0 * onebyfftLen; + p1 = a1 * onebyfftLen; + p2 = a2 * onebyfftLen; + p3 = a3 * onebyfftLen; + p4 = a4 * onebyfftLen; + p5 = a5 * onebyfftLen; + p6 = a6 * onebyfftLen; + p7 = a7 * onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) - (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2); + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) - (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) - (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) * onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb-yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = r1 * onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = s1 * onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb-yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb-xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb-xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = r1 * onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = s1 * onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = r2 * onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = s2 * onebyfftLen; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +} + + + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c new file mode 100644 index 0000000..152542d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c @@ -0,0 +1,175 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_f16.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_radix4_init_f16( + arm_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c new file mode 100644 index 0000000..3d1a5ef --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c @@ -0,0 +1,172 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_f32.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } +#endif +#endif +#endif + + return (status); +} + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c new file mode 100644 index 0000000..c4a024e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c @@ -0,0 +1,161 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q15.c + * Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c new file mode 100644 index 0000000..9b6273f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c @@ -0,0 +1,158 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q31.c + * Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c new file mode 100644 index 0000000..33b5029 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c @@ -0,0 +1,1826 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q15.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in,out] pSrc points to the complex data buffer. Processing occurs in-place. + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + +| CFFT Size | Input format | Output format | Number of bits to upscale | +| --------: | ------------: | ------------: | ------------------------: | +| 16 | 1.15 | 5.11 | 4 | +| 64 | 1.15 | 7.9 | 6 | +| 256 | 1.15 | 9.7 | 8 | +| 1024 | 1.15 | 11.5 | 10 | + +| CIFFT Size | Input format | Output format | Number of bits to upscale | +| ---------: | ------------: | ------------: | ------------------------: | +| 16 | 1.15 | 5.11 | 0 | +| 64 | 1.15 | 7.9 | 0 | +| 256 | 1.15 | 9.7 | 0 | +| 1024 | 1.15 | 11.5 | 0 | + + */ + +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q15 CFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + T = __SHADD16(T, 0); /* it turns out doing this twice is 2 cycles, the alternative takes 3 cycles */ +/* + in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles + T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF); +*/ + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUAD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QASX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUAD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUSDX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUSDX(S, C1) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUAD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUSDX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUSDX(R, C3) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUAD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUAD(C1, S) >> 16U; + out2 = __SMUSDX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSDX(S, C1) >> 16U; + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(C3, R) >> 16U; + out2 = __SMUSDX(C3, R); +#else + out1 = __SMUSDX(R, C3) >> 16U; + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia (&ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia (&ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia (&ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia (&ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + j = n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc) */ + R0 = __SSAT(T0 + S0, 16U); + /* R1 = (xa + xc) */ + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc) */ + S0 = __SSAT(T0 - S0, 16); + /* S1 = (xa - xc) */ + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1] >> 2U; + + /* T0 = (yb + yd) */ + T0 = __SSAT(T0 + U0, 16U); + /* T1 = (xb + xd) */ + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* ya' = ya + yb + yc + yd */ + /* xa' = xa + xb + xc + xd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd) */ + /* R1 = (xa + xc) - (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1]; + + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2; + T1 = pSrc16[(i1 * 2U) + 1] >> 2; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd */ + U0 = pSrc16[i3 * 2U] >> 2; + U1 = pSrc16[(i3 * 2U) + 1] >> 2; + /* T0 = yb-yd */ + T0 = __SSAT(T0 - U0, 16); + /* T1 = xb-xd */ + T1 = __SSAT(T1 - U1, 16); + + /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */ + R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */ + S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16U); + S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16U); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16); + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16); + + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * (ic * 2U)]; + Si2 = pCoef16[(2U * (ic * 2U)) + 1U]; + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16); + R1 = __SSAT(T1 + S1, 16); + + /* S0 = (ya - yc), S1 =(xa - xc) */ + S0 = __SSAT(T0 - S0, 16); + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16); + T1 = __SSAT(T1 + U1, 16); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + out2 = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + pSrc16[i0 * 2U] = out1; + pSrc16[(2U * i0) + 1U] = out2; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd */ + T0 = __SSAT(T0 - U0, 16); + T1 = __SSAT(T1 - U1, 16); + + /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */ + R0 = (S0 >> 1U) - (T1 >> 1U); + R1 = (S1 >> 1U) + (T0 >> 1U); + + /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */ + S0 = (S0 >> 1U) + (T1 >> 1U); + S1 = (S1 >> 1U) - (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16U); + + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16U); + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* start of last stage process */ + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd)) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + } + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +/** + @brief Core function for the Q15 CIFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUSD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(C2, R) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */ + S = __QASX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUSD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUADX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUADX(C1, S) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUSD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUADX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUADX(C3, R) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUSD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSD(C1, S) >> 16U; + out2 = __SMUADX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUADX(S, C1) >> 16U; + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(C3, R) >> 16U; + out2 = __SMUADX(C3, R); +#else + out1 = __SMUADX(C3, R) >> 16U; + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia (&ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia (&ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia (&ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia (&ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* arm_radix4_butterfly_inverse_q15 */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + + j = n2; + + /* Input is in 1.15(q15) format */ + + /* Start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + /* Read yd (real), xd(imag) input */ + /* input is down scale by 4 to avoid overflow */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1U]; + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd) */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16); + /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* End of first stage process */ + + /* data is in 4.11(q11) format */ + + + /* Start of Middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[2U * ic * 2U + 1U]; + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + pSrc16[(i0 * 2U) + 1U] = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16); + /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (S0 >> 1U) + (T1 >> 1U); + R1 = (S1 >> 1U) - (T0 >> 1U); + + /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (S0 >> 1U) - (T1 >> 1U); + S1 = (S1 >> 1U) + (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* End of Middle stages process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* start of last stage process */ + + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd) */ + /* yb' = (ya+xb-yc-xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd) */ + /* yd' = (ya-xb-yc+xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + } + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c new file mode 100644 index 0000000..bad1640 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c @@ -0,0 +1,844 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q31.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + +| CFFT Size | Input format | Output format | Number of bits to upscale | +| --------: | ------------: | ------------: | ------------------------: | +| 16 | 1.31 | 5.27 | 4 | +| 64 | 1.31 | 7.25 | 6 | +| 256 | 1.31 | 9.23 | 8 | +| 1024 | 1.31 | 11.21 | 10 | + +| CIFFT Size | Input format | Output format | Number of bits to upscale | +| ---------: | ------------: | ------------: | ------------------------: | +| 16 | 1.31 | 5.27 | 0 | +| 64 | 1.31 | 7.25 | 0 | +| 256 | 1.31 | 9.23 | 0 | +| 1024 | 1.31 | 11.21 | 0 | + + */ + +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + * + * Butterfly implementation: + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q31 CFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + + /* start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[(2U * i0)] >> 4U) + (pSrc[(2U * i2)] >> 4U); + /* xa - xc */ + r2 = (pSrc[(2U * i0)] >> 4U) - (pSrc[(2U * i2)] >> 4U); + + /* xb + xd */ + t1 = (pSrc[(2U * i1)] >> 4U) + (pSrc[(2U * i3)] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[(2U * i1)] >> 4U) - (pSrc[(2U * i3)] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* end of first stage process */ + + /* data is in 5.27(q27) format */ + + + /* start of Middle stages process */ + + + /* each stage in middle stages provides two down scaling of the input */ + + twidCoefModifier <<= 2U; + + + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* start of Last stage process */ + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa + yb - xc - yd); + yb_out = (ya - xb - yc + xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa - yb - xc + yd); + yd_out = (ya + xb - yc - xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ + +} + + +/** + @brief Core function for the Q31 CIFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT Function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* input is be 1.31(q31) format for all FFT sizes */ + /* Total process is divided into three stages */ + /* process first stage, middle stages, & last stage */ + + /* Start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + do + { + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[2U * i0] >> 4U) + (pSrc[2U * i2] >> 4U); + /* xa - xc */ + r2 = (pSrc[2U * i0] >> 4U) - (pSrc[2U * i2] >> 4U); + + /* xb + xd */ + t1 = (pSrc[2U * i1] >> 4U) + (pSrc[2U * i3] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[2U * i1] >> 4U) - (pSrc[2U * i3] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) - + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[2U * i1 + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) + + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* data is in 5.27(q27) format */ + /* each stage provides two down scaling of the input */ + + + /* Start of Middle stages process */ + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + for (j = 0; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32U)) - + ((int32_t) (((q63_t) s1 * si2) >> 32U))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32U)) + + ((int32_t) (((q63_t) r1 * si2) >> 32U))) >> 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[(2U * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* Start of last stage process */ + + + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa - yb - xc + yd); + yb_out = (ya + xb - yc - xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa + yb - xc - yd); + yd_out = (ya - xb - yc + xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c new file mode 100644 index 0000000..77dfc5b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c @@ -0,0 +1,293 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix8_f16.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void arm_radix8_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float16_t r1, r2, r3, r4, r5, r6, r7, r8; + float16_t t1, t2; + float16_t s1, s2, s3, s4, s5, s6, s7, s8; + float16_t p1, p2, p3, p4; + float16_t co2, co3, co4, co5, co6, co7, co8; + float16_t si2, si3, si4, si5, si6, si7, si8; + const float16_t C81 = 0.70710678118f16; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = (_Float16)pSrc[2 * i1] + (_Float16)pSrc[2 * i5]; + r5 = (_Float16)pSrc[2 * i1] - (_Float16)pSrc[2 * i5]; + r2 = (_Float16)pSrc[2 * i2] + (_Float16)pSrc[2 * i6]; + r6 = (_Float16)pSrc[2 * i2] - (_Float16)pSrc[2 * i6]; + r3 = (_Float16)pSrc[2 * i3] + (_Float16)pSrc[2 * i7]; + r7 = (_Float16)pSrc[2 * i3] - (_Float16)pSrc[2 * i7]; + r4 = (_Float16)pSrc[2 * i4] + (_Float16)pSrc[2 * i8]; + r8 = (_Float16)pSrc[2 * i4] - (_Float16)pSrc[2 * i8]; + t1 = (_Float16)r1 - (_Float16)r3; + r1 = (_Float16)r1 + (_Float16)r3; + r3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1] = (_Float16)r1 + (_Float16)r2; + pSrc[2 * i5] = (_Float16)r1 - (_Float16)r2; + r1 = (_Float16)pSrc[2 * i1 + 1] + (_Float16)pSrc[2 * i5 + 1]; + s5 = (_Float16)pSrc[2 * i1 + 1] - (_Float16)pSrc[2 * i5 + 1]; + r2 = (_Float16)pSrc[2 * i2 + 1] + (_Float16)pSrc[2 * i6 + 1]; + s6 = (_Float16)pSrc[2 * i2 + 1] - (_Float16)pSrc[2 * i6 + 1]; + s3 = (_Float16)pSrc[2 * i3 + 1] + (_Float16)pSrc[2 * i7 + 1]; + s7 = (_Float16)pSrc[2 * i3 + 1] - (_Float16)pSrc[2 * i7 + 1]; + r4 = (_Float16)pSrc[2 * i4 + 1] + (_Float16)pSrc[2 * i8 + 1]; + s8 = (_Float16)pSrc[2 * i4 + 1] - (_Float16)pSrc[2 * i8 + 1]; + t2 = (_Float16)r1 - (_Float16)s3; + r1 = (_Float16)r1 + (_Float16)s3; + s3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1 + 1] = (_Float16)r1 + (_Float16)r2; + pSrc[2 * i5 + 1] = (_Float16)r1 - (_Float16)r2; + pSrc[2 * i3] = (_Float16)t1 + (_Float16)s3; + pSrc[2 * i7] = (_Float16)t1 - (_Float16)s3; + pSrc[2 * i3 + 1] = (_Float16)t2 - (_Float16)r3; + pSrc[2 * i7 + 1] = (_Float16)t2 + (_Float16)r3; + r1 = ((_Float16)r6 - (_Float16)r8) * (_Float16)C81; + r6 = ((_Float16)r6 + (_Float16)r8) * (_Float16)C81; + r2 = ((_Float16)s6 - (_Float16)s8) * (_Float16)C81; + s6 = ((_Float16)s6 + (_Float16)s8) * (_Float16)C81; + t1 = (_Float16)r5 - (_Float16)r1; + r5 = (_Float16)r5 + (_Float16)r1; + r8 = (_Float16)r7 - (_Float16)r6; + r7 = (_Float16)r7 + (_Float16)r6; + t2 = (_Float16)s5 - (_Float16)r2; + s5 = (_Float16)s5 + (_Float16)r2; + s8 = (_Float16)s7 - (_Float16)s6; + s7 = (_Float16)s7 + (_Float16)s6; + pSrc[2 * i2] = (_Float16)r5 + (_Float16)s7; + pSrc[2 * i8] = (_Float16)r5 - (_Float16)s7; + pSrc[2 * i6] = (_Float16)t1 + (_Float16)s8; + pSrc[2 * i4] = (_Float16)t1 - (_Float16)s8; + pSrc[2 * i2 + 1] = (_Float16)s5 - (_Float16)r7; + pSrc[2 * i8 + 1] = (_Float16)s5 + (_Float16)r7; + pSrc[2 * i6 + 1] = (_Float16)t2 - (_Float16)r8; + pSrc[2 * i4 + 1] = (_Float16)t2 + (_Float16)r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = (_Float16)pSrc[2 * i1] + (_Float16)pSrc[2 * i5]; + r5 = (_Float16)pSrc[2 * i1] - (_Float16)pSrc[2 * i5]; + r2 = (_Float16)pSrc[2 * i2] + (_Float16)pSrc[2 * i6]; + r6 = (_Float16)pSrc[2 * i2] - (_Float16)pSrc[2 * i6]; + r3 = (_Float16)pSrc[2 * i3] + (_Float16)pSrc[2 * i7]; + r7 = (_Float16)pSrc[2 * i3] - (_Float16)pSrc[2 * i7]; + r4 = (_Float16)pSrc[2 * i4] + (_Float16)pSrc[2 * i8]; + r8 = (_Float16)pSrc[2 * i4] - (_Float16)pSrc[2 * i8]; + t1 = (_Float16)r1 - (_Float16)r3; + r1 = (_Float16)r1 + (_Float16)r3; + r3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1] = (_Float16)r1 + (_Float16)r2; + r2 = (_Float16)r1 - (_Float16)r2; + s1 = (_Float16)pSrc[2 * i1 + 1] + (_Float16)pSrc[2 * i5 + 1]; + s5 = (_Float16)pSrc[2 * i1 + 1] - (_Float16)pSrc[2 * i5 + 1]; + s2 = (_Float16)pSrc[2 * i2 + 1] + (_Float16)pSrc[2 * i6 + 1]; + s6 = (_Float16)pSrc[2 * i2 + 1] - (_Float16)pSrc[2 * i6 + 1]; + s3 = (_Float16)pSrc[2 * i3 + 1] + (_Float16)pSrc[2 * i7 + 1]; + s7 = (_Float16)pSrc[2 * i3 + 1] - (_Float16)pSrc[2 * i7 + 1]; + s4 = (_Float16)pSrc[2 * i4 + 1] + (_Float16)pSrc[2 * i8 + 1]; + s8 = (_Float16)pSrc[2 * i4 + 1] - (_Float16)pSrc[2 * i8 + 1]; + t2 = (_Float16)s1 - (_Float16)s3; + s1 = (_Float16)s1 + (_Float16)s3; + s3 = (_Float16)s2 - (_Float16)s4; + s2 = (_Float16)s2 + (_Float16)s4; + r1 = (_Float16)t1 + (_Float16)s3; + t1 = (_Float16)t1 - (_Float16)s3; + pSrc[2 * i1 + 1] = (_Float16)s1 + (_Float16)s2; + s2 = (_Float16)s1 - (_Float16)s2; + s1 = (_Float16)t2 - (_Float16)r3; + t2 = (_Float16)t2 + (_Float16)r3; + p1 = (_Float16)co5 * (_Float16)r2; + p2 = (_Float16)si5 * (_Float16)s2; + p3 = (_Float16)co5 * (_Float16)s2; + p4 = (_Float16)si5 * (_Float16)r2; + pSrc[2 * i5] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i5 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co3 * (_Float16)r1; + p2 = (_Float16)si3 * (_Float16)s1; + p3 = (_Float16)co3 * (_Float16)s1; + p4 = (_Float16)si3 * (_Float16)r1; + pSrc[2 * i3] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i3 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co7 * (_Float16)t1; + p2 = (_Float16)si7 * (_Float16)t2; + p3 = (_Float16)co7 * (_Float16)t2; + p4 = (_Float16)si7 * (_Float16)t1; + pSrc[2 * i7] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i7 + 1] = (_Float16)p3 - (_Float16)p4; + r1 = ((_Float16)r6 - (_Float16)r8) * (_Float16)C81; + r6 = ((_Float16)r6 + (_Float16)r8) * (_Float16)C81; + s1 = ((_Float16)s6 - (_Float16)s8) * (_Float16)C81; + s6 = ((_Float16)s6 + (_Float16)s8) * (_Float16)C81; + t1 = (_Float16)r5 - (_Float16)r1; + r5 = (_Float16)r5 + (_Float16)r1; + r8 = (_Float16)r7 - (_Float16)r6; + r7 = (_Float16)r7 + (_Float16)r6; + t2 = (_Float16)s5 - (_Float16)s1; + s5 = (_Float16)s5 + (_Float16)s1; + s8 = (_Float16)s7 - (_Float16)s6; + s7 = (_Float16)s7 + (_Float16)s6; + r1 = (_Float16)r5 + (_Float16)s7; + r5 = (_Float16)r5 - (_Float16)s7; + r6 = (_Float16)t1 + (_Float16)s8; + t1 = (_Float16)t1 - (_Float16)s8; + s1 = (_Float16)s5 - (_Float16)r7; + s5 = (_Float16)s5 + (_Float16)r7; + s6 = (_Float16)t2 - (_Float16)r8; + t2 = (_Float16)t2 + (_Float16)r8; + p1 = (_Float16)co2 * (_Float16)r1; + p2 = (_Float16)si2 * (_Float16)s1; + p3 = (_Float16)co2 * (_Float16)s1; + p4 = (_Float16)si2 * (_Float16)r1; + pSrc[2 * i2] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i2 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co8 * (_Float16)r5; + p2 = (_Float16)si8 * (_Float16)s5; + p3 = (_Float16)co8 * (_Float16)s5; + p4 = (_Float16)si8 * (_Float16)r5; + pSrc[2 * i8] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i8 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co6 * (_Float16)r6; + p2 = (_Float16)si6 * (_Float16)s6; + p3 = (_Float16)co6 * (_Float16)s6; + p4 = (_Float16)si6 * (_Float16)r6; + pSrc[2 * i6] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i6 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co4 * (_Float16)t1; + p2 = (_Float16)si4 * (_Float16)t2; + p3 = (_Float16)co4 * (_Float16)t2; + p4 = (_Float16)si4 * (_Float16)t1; + pSrc[2 * i4] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i4 + 1] = (_Float16)p3 - (_Float16)p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c new file mode 100644 index 0000000..328a725 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c @@ -0,0 +1,289 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix8_f32.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float32_t r1, r2, r3, r4, r5, r6, r7, r8; + float32_t t1, t2; + float32_t s1, s2, s3, s4, s5, s6, s7, s8; + float32_t p1, p2, p3, p4; + float32_t co2, co3, co4, co5, co6, co7, co8; + float32_t si2, si3, si4, si5, si6, si7, si8; + const float32_t C81 = 0.70710678118f; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + pSrc[2 * i5] = r1 - r2; + r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = r1 - s3; + r1 = r1 + s3; + s3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1 + 1] = r1 + r2; + pSrc[2 * i5 + 1] = r1 - r2; + pSrc[2 * i3] = t1 + s3; + pSrc[2 * i7] = t1 - s3; + pSrc[2 * i3 + 1] = t2 - r3; + pSrc[2 * i7 + 1] = t2 + r3; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + r2 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - r2; + s5 = s5 + r2; + s8 = s7 - s6; + s7 = s7 + s6; + pSrc[2 * i2] = r5 + s7; + pSrc[2 * i8] = r5 - s7; + pSrc[2 * i6] = t1 + s8; + pSrc[2 * i4] = t1 - s8; + pSrc[2 * i2 + 1] = s5 - r7; + pSrc[2 * i8 + 1] = s5 + r7; + pSrc[2 * i6 + 1] = t2 - r8; + pSrc[2 * i4 + 1] = t2 + r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + r2 = r1 - r2; + s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = s1 - s3; + s1 = s1 + s3; + s3 = s2 - s4; + s2 = s2 + s4; + r1 = t1 + s3; + t1 = t1 - s3; + pSrc[2 * i1 + 1] = s1 + s2; + s2 = s1 - s2; + s1 = t2 - r3; + t2 = t2 + r3; + p1 = co5 * r2; + p2 = si5 * s2; + p3 = co5 * s2; + p4 = si5 * r2; + pSrc[2 * i5] = p1 + p2; + pSrc[2 * i5 + 1] = p3 - p4; + p1 = co3 * r1; + p2 = si3 * s1; + p3 = co3 * s1; + p4 = si3 * r1; + pSrc[2 * i3] = p1 + p2; + pSrc[2 * i3 + 1] = p3 - p4; + p1 = co7 * t1; + p2 = si7 * t2; + p3 = co7 * t2; + p4 = si7 * t1; + pSrc[2 * i7] = p1 + p2; + pSrc[2 * i7 + 1] = p3 - p4; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + s1 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - s1; + s5 = s5 + s1; + s8 = s7 - s6; + s7 = s7 + s6; + r1 = r5 + s7; + r5 = r5 - s7; + r6 = t1 + s8; + t1 = t1 - s8; + s1 = s5 - r7; + s5 = s5 + r7; + s6 = t2 - r8; + t2 = t2 + r8; + p1 = co2 * r1; + p2 = si2 * s1; + p3 = co2 * s1; + p4 = si2 * r1; + pSrc[2 * i2] = p1 + p2; + pSrc[2 * i2 + 1] = p3 - p4; + p1 = co8 * r5; + p2 = si8 * s5; + p3 = co8 * s5; + p4 = si8 * r5; + pSrc[2 * i8] = p1 + p2; + pSrc[2 * i8 + 1] = p3 - p4; + p1 = co6 * r6; + p2 = si6 * s6; + p3 = co6 * s6; + p4 = si6 * r6; + pSrc[2 * i6] = p1 + p2; + pSrc[2 * i6 + 1] = p3 - p4; + p1 = co4 * t1; + p2 = si4 * t2; + p3 = co4 * t2; + p4 = si4 * t1; + pSrc[2 * i4] = p1 + p2; + pSrc[2 * i4 + 1] = p3 - p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c new file mode 100644 index 0000000..7367b11 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c @@ -0,0 +1,456 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_f32.c + * Description: Processing function of DCT4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +/** + @ingroup groupTransforms + */ + +/** + @defgroup DCT4_IDCT4 DCT Type IV Functions + + Representation of signals by minimum number of values is important for storage and transmission. + The possibility of large discontinuity between the beginning and end of a period of a signal + in DFT can be avoided by extending the signal so that it is even-symmetric. + Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the + spectrum and is very widely used in signal and image coding applications. + The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. + DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular. + + DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. + Reordering of the input data makes the computation of DCT just a problem of + computing the DFT of a real signal with a few additional operations. + This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations. + + DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. + DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. + DCT2 implementation can be described in the following steps: + - Re-ordering input + - Calculating Real FFT + - Multiplication of weights and Real FFT output and getting real part from the product. + + This process is explained by the block diagram below: + \image html DCT4.gif "Discrete Cosine Transform - type-IV" + + @par Algorithm + The N-point type-IV DCT is defined as a real, linear transformation by the formula: + \f[ + X_c(k) = \sqrt{\frac{2}{N}}\sum_{n=0}^{N-1} x(n)cos\Big[\Big(n+\frac{1}{2}\Big)\Big(k+\frac{1}{2}\Big)\frac{\pi}{N}\Big] + \f] + where k = 0, 1, 2, ..., N-1 + @par + Its inverse is defined as follows: + \f[ + x(n) = \sqrt{\frac{2}{N}}\sum_{k=0}^{N-1} X_c(k)cos\Big[\Big(n+\frac{1}{2}\Big)\Big(k+\frac{1}{2}\Big)\frac{\pi}{N}\Big] + \f] + where n = 0, 1, 2, ..., N-1 + @par + The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). + The symmetry of the transform matrix indicates that the fast algorithms for the forward + and inverse transform computation are identical. + Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both. + + @par Lengths supported by the transform: + As DCT4 internally uses Real FFT, it supports all the lengths 128, 512, 2048 and 8192. + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Instance Structure + The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. + A separate instance structure must be defined for each transform. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes Real FFT as its process function is used internally in DCT4, by calling \ref arm_rfft_init_f32(). + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Manually initialize the instance structure as follows: + 
+      arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+
+ where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4; + \c normalize is normalizing factor used and is equal to sqrt(2/N); + \c pTwiddle points to the twiddle factor table; + \c pCosFactor points to the cosFactor table; + \c pRfft points to the real FFT instance; + \c pCfft points to the complex FFT instance; + The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() + and arm_rfft_f32() respectively for details regarding static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the DCT4 transform functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the floating-point DCT4/IDCT4. + @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure + @param[in] pState points to state buffer + @param[in,out] pInlineBuffer points to the in-place input and output buffer + @return none + */ + +void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer) +{ + const float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + float32_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N); + arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement the loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c new file mode 100644 index 0000000..957e01e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c @@ -0,0 +1,140 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_f32.c + * Description: Initialization function of DCT-4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the floating-point DCT4/IDCT4. + @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Floating-point normalizing factors are mentioned in the table below for different DCT sizes: + + +| DCT Size | Normalizing factor value | +| --------: | ------------------------: | +| 2048 | 0.03125 | +| 512 | 0.0625 | +| 128 | 0.125 | + + */ + +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = Weights_8192; + S->pCosFactor = cos_factors_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + case 2048U: + S->pTwiddle = Weights_2048; + S->pCosFactor = cos_factors_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + case 512U: + S->pTwiddle = Weights_512; + S->pCosFactor = cos_factors_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + case 128U: + S->pTwiddle = Weights_128; + S->pCosFactor = cos_factors_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c new file mode 100644 index 0000000..0cd18fb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c @@ -0,0 +1,139 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q15.c + * Description: Initialization function of DCT-4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q15 DCT4/IDCT4. + @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: + +| DCT Size | Normalizing factor value (hexadecimal) | +| --------: | ---------------------------------------:| +| 2048 | 0x400 | +| 512 | 0x800 | +| 128 | 0x1000 | + + */ + +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ15_8192; + S->pCosFactor = cos_factorsQ15_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + case 2048U: + S->pTwiddle = WeightsQ15_2048; + S->pCosFactor = cos_factorsQ15_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + case 512U: + S->pTwiddle = WeightsQ15_512; + S->pCosFactor = cos_factorsQ15_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + case 128U: + S->pTwiddle = WeightsQ15_128; + S->pCosFactor = cos_factorsQ15_128; + break; + #endif + + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT */ + arm_rfft_init_q15(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c new file mode 100644 index 0000000..1d7d2f1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c @@ -0,0 +1,138 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q31.c + * Description: Initialization function of DCT-4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q31 DCT4/IDCT4. + @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor: + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: + +| DCT Size | Normalizing factor value (hexadecimal) | +| --------: | ---------------------------------------:| +| 2048 | 0x4000000 | +| 512 | 0x8000000 | +| 128 | 0x10000000 | + + */ + +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ31_8192; + S->pCosFactor = cos_factorsQ31_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + case 2048U: + S->pTwiddle = WeightsQ31_2048; + S->pCosFactor = cos_factorsQ31_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + case 512U: + S->pTwiddle = WeightsQ31_512; + S->pCosFactor = cos_factorsQ31_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + case 128U: + S->pTwiddle = WeightsQ31_128; + S->pCosFactor = cos_factorsQ31_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_q31(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c new file mode 100644 index 0000000..a9d4e78 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c @@ -0,0 +1,391 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q15.c + * Description: Processing function of DCT4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q15 DCT4/IDCT4. + @param[in] S points to an instance of the Q15 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. The input and output + formats for different DCT sizes and number of bits to upscale are mentioned in the table below: + +| DCT Size | Input format | Output format | Number of bits to upscale | +| --------: | ------------: | ------------: | ------------------------: | +| 2048 | 1.15 | 11.5 | 10 | +| 512 | 1.15 | 9.7 | 8 | +| 128 | 1.15 | 7.9 | 6 | + + + */ + +void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer) +{ + const q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q15_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q15 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q15 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c new file mode 100644 index 0000000..5976bd0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c @@ -0,0 +1,392 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q31.c + * Description: Processing function of DCT4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q31 DCT4/IDCT4. + @param[in] S points to an instance of the Q31 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, + as the conversion from DCT2 to DCT4 involves one subtraction. + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. + The input and output formats for different DCT sizes and number of bits to upscale are + mentioned in the table below: + +| DCT Size | Input format | Output format | Number of bits to upscale | +| --------: | ------------: | ------------: | ------------------------: | +| 2048 | 2.30 | 12.20 | 11 | +| 512 | 2.30 | 10.22 | 9 | +| 128 | 2.30 | 8.24 | 7 | + + */ + +void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer) +{ + const q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q31_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q31 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q31 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31(pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c new file mode 100644 index 0000000..f9cf6fd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c @@ -0,0 +1,165 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_f16.c + * Description: MFCC function for the f16 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q15, and Q31 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC F16 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples if the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length size when MFCC + is implemented with CFFT. + It has length FFT Length + 2 when implemented with RFFT + (default implementation). + + The source buffer is modified by this function. + + */ +void arm_mfcc_f16( + const arm_mfcc_instance_f16 * S, + float16_t *pSrc, + float16_t *pDst, + float16_t *pTmp + ) +{ + float16_t maxValue; + uint32_t index; + uint32_t i; + float16_t result; + const float16_t *coefs=S->filterCoefs; + arm_matrix_instance_f16 pDctMat; + + /* Normalize */ + arm_absmax_f16(pSrc,S->fftLen,&maxValue,&index); + + arm_scale_f16(pSrc,1.0f16/(_Float16)maxValue,pSrc,S->fftLen); + + /* Multiply by window */ + arm_mult_f16(pSrc,S->windowCoefs,pSrc,S->fftLen); + + /* Compute spectrum magnitude + */ +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp[2*i] = pSrc[i]; + pTmp[2*i+1] = 0.0f16; + } + arm_cfft_f16(&(S->cfft),pTmp,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_fast_f16(&(S->rfft),pSrc,pTmp,0); + /* Unpack real values */ + pTmp[S->fftLen]=pTmp[1]; + pTmp[S->fftLen+1]=0.0f16; + pTmp[1]=0.0f; +#endif + arm_cmplx_mag_f16(pTmp,pSrc,S->fftLen); + + /* Apply MEL filters */ + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_f16(pSrc+S->filterPos[i], + coefs, + S->filterLengths[i], + &result); + + coefs += S->filterLengths[i]; + + pTmp[i] = result; + + } + + /* Compute the log */ + arm_offset_f16(pTmp,1.0e-4f16,pTmp,S->nbMelFilters); + arm_vlog_f16(pTmp,pTmp,S->nbMelFilters); + + /* Multiply with the DCT matrix */ + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(float16_t*)S->dctCoefs; + + arm_mat_vec_mult_f16(&pDctMat, pTmp, pDst); + + +} + +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c new file mode 100644 index 0000000..544f717 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c @@ -0,0 +1,154 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_f32.c + * Description: MFCC function for the f32 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/** + @ingroup groupTransforms + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC F32 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples if the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length size when MFCC + is implemented with CFFT. + It has length FFT Length + 2 when implemented with RFFT + (default implementation). + + The source buffer is modified by this function. + + */ +void arm_mfcc_f32( + const arm_mfcc_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pTmp + ) +{ + float32_t maxValue; + uint32_t index; + uint32_t i; + float32_t result; + const float32_t *coefs=S->filterCoefs; + arm_matrix_instance_f32 pDctMat; + + /* Normalize */ + arm_absmax_f32(pSrc,S->fftLen,&maxValue,&index); + + arm_scale_f32(pSrc,1.0f/maxValue,pSrc,S->fftLen); + + /* Multiply by window */ + arm_mult_f32(pSrc,S->windowCoefs,pSrc,S->fftLen); + + /* Compute spectrum magnitude + */ +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp[2*i] = pSrc[i]; + pTmp[2*i+1] = 0.0f; + } + arm_cfft_f32(&(S->cfft),pTmp,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_fast_f32(&(S->rfft),pSrc,pTmp,0); + /* Unpack real values */ + pTmp[S->fftLen]=pTmp[1]; + pTmp[S->fftLen+1]=0.0f; + pTmp[1]=0.0f; +#endif + arm_cmplx_mag_f32(pTmp,pSrc,S->fftLen); + + /* Apply MEL filters */ + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_f32(pSrc+S->filterPos[i], + coefs, + S->filterLengths[i], + &result); + + coefs += S->filterLengths[i]; + + pTmp[i] = result; + + } + + /* Compute the log */ + arm_offset_f32(pTmp,1.0e-6f,pTmp,S->nbMelFilters); + arm_vlog_f32(pTmp,pTmp,S->nbMelFilters); + + /* Multiply with the DCT matrix */ + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(float32_t*)S->dctCoefs; + + arm_mat_vec_mult_f32(&pDctMat, pTmp, pDst); + + +} + +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c new file mode 100644 index 0000000..74b6c3d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c @@ -0,0 +1,114 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_f16.c + * Description: MFCC initialization function for the f16 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + + +/** + @brief Initialization of the MFCC F16 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_f16( + arm_mfcc_instance_f16 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float16_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float16_t *filterCoefs, + const float16_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_f16(&(S->cfft),fftLen); + #else + status=arm_rfft_fast_init_f16(&(S->rfft),fftLen); + #endif + + return(status); +} + +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c new file mode 100644 index 0000000..9e0bf0c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c @@ -0,0 +1,111 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_f32.c + * Description: MFCC initialization function for the f32 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_f32( + arm_mfcc_instance_f32 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float32_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float32_t *filterCoefs, + const float32_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_f32(&(S->cfft),fftLen); + #else + status=arm_rfft_fast_init_f32(&(S->rfft),fftLen); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c new file mode 100644 index 0000000..ccd6da9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c @@ -0,0 +1,111 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_q15.c + * Description: MFCC initialization function for the q15 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_q15( + arm_mfcc_instance_q15 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q15_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q15_t *filterCoefs, + const q15_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_q15(&(S->cfft),fftLen); + #else + status=arm_rfft_init_q15(&(S->rfft),fftLen,0,1); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c new file mode 100644 index 0000000..5573b33 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c @@ -0,0 +1,111 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_q31.c + * Description: MFCC initialization function for the q31 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_q31( + arm_mfcc_instance_q31 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q31_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q31_t *filterCoefs, + const q31_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_q31(&(S->cfft),fftLen); + #else + status=arm_rfft_init_q31(&(S->rfft),fftLen,0,1); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c new file mode 100644 index 0000000..9cbd447 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c @@ -0,0 +1,203 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_q15.c + * Description: MFCC function for the q15 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/* Constants for Q15 implementation */ +#define LOG2TOLOG_Q15 0x02C5C860 +#define MICRO_Q15 0x00000219 +#define SHIFT_MELFILTER_SATURATION_Q15 10 +/** + @ingroup groupTransforms + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC Q15 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples in Q15 + @param[out] pDst points to the output MFCC values in q8.7 format + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples is the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length. + + The source buffer is modified by this function. + + The function may saturate. If the FFT length is too + big and the number of MEL filters too small then the fixed + point computations may saturate. + + */ + +arm_status arm_mfcc_q15( + const arm_mfcc_instance_q15 * S, + q15_t *pSrc, + q15_t *pDst, + q31_t *pTmp + ) +{ + q15_t m; + uint32_t index; + uint32_t fftShift=0; + q31_t logExponent; + q63_t result; + arm_matrix_instance_q15 pDctMat; + uint32_t i; + uint32_t coefsPos; + uint32_t filterLimit; + q15_t *pTmp2=(q15_t*)pTmp; + + arm_status status = ARM_MATH_SUCCESS; + + // q15 + arm_absmax_q15(pSrc,S->fftLen,&m,&index); + + if (m !=0) + { + q15_t quotient; + int16_t shift; + + status = arm_divide_q15(0x7FFF,m,"ient,&shift); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + arm_scale_q15(pSrc,quotient,shift,pSrc,S->fftLen); + } + + + // q15 + arm_mult_q15(pSrc,S->windowCoefs, pSrc, S->fftLen); + + + /* Compute spectrum magnitude + */ + fftShift = 31 - __CLZ(S->fftLen); +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp2[2*i] = pSrc[i]; + pTmp2[2*i+1] = 0; + } + arm_cfft_q15(&(S->cfft),pTmp2,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_q15(&(S->rfft),pSrc,pTmp2); +#endif + filterLimit = 1 + (S->fftLen >> 1); + + + // q15 - fftShift + arm_cmplx_mag_q15(pTmp2,pSrc,filterLimit); + // q14 - fftShift + + /* Apply MEL filters */ + coefsPos = 0; + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_q15(pSrc+S->filterPos[i], + &(S->filterCoefs[coefsPos]), + S->filterLengths[i], + &result); + + coefsPos += S->filterLengths[i]; + + // q34.29 - fftShift + result += MICRO_Q15; + result >>= SHIFT_MELFILTER_SATURATION_Q15; + // q34.29 - fftShift - satShift + pTmp[i] = __SSAT(result,31) ; + + } + + + // q34.29 - fftShift - satShift + /* Compute the log */ + arm_vlog_q31(pTmp,pTmp,S->nbMelFilters); + + + // q5.26 + + logExponent = fftShift + 2 + SHIFT_MELFILTER_SATURATION_Q15; + logExponent = logExponent * LOG2TOLOG_Q15; + + + // q8.26 + arm_offset_q31(pTmp,logExponent,pTmp,S->nbMelFilters); + arm_shift_q31(pTmp,-19,pTmp,S->nbMelFilters); + for(i=0; inbMelFilters; i++) + { + pSrc[i] = __SSAT((q15_t)pTmp[i],16); + } + + // q8.7 + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(q15_t*)S->dctCoefs; + + arm_mat_vec_mult_q15(&pDctMat, pSrc, pDst); + + return(status); +} + +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c new file mode 100644 index 0000000..6993c55 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c @@ -0,0 +1,202 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_q31.c + * Description: MFCC function for the q31 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/basic_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/complex_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/fast_math_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/matrix_functions.h" + +/* Constants for Q31 implementation */ +#define LOG2TOLOG_Q31 0x02C5C860 +#define MICRO_Q31 0x08637BD0 +#define SHIFT_MELFILTER_SATURATION_Q31 10 +/** + @ingroup groupTransforms + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC Q31 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples in Q31 + @param[out] pDst points to the output MFCC values in q8.23 format + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples is the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length. + + The source buffer is modified by this function. + + The function may saturate. If the FFT length is too + big and the number of MEL filters too small then the fixed + point computations may saturate. + + */ + + +arm_status arm_mfcc_q31( + const arm_mfcc_instance_q31 * S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pTmp + ) +{ + q31_t m; + uint32_t index; + uint32_t fftShift=0; + q31_t logExponent; + q63_t result; + arm_matrix_instance_q31 pDctMat; + uint32_t i; + uint32_t coefsPos; + uint32_t filterLimit; + q31_t *pTmp2=(q31_t*)pTmp; + + arm_status status = ARM_MATH_SUCCESS; + + // q31 + arm_absmax_q31(pSrc,S->fftLen,&m,&index); + + if (m !=0) + { + q31_t quotient; + int16_t shift; + + status = arm_divide_q31(0x7FFFFFFF,m,"ient,&shift); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + arm_scale_q31(pSrc,quotient,shift,pSrc,S->fftLen); + } + + + // q31 + arm_mult_q31(pSrc,S->windowCoefs, pSrc, S->fftLen); + + + /* Compute spectrum magnitude + */ + fftShift = 31 - __CLZ(S->fftLen); +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp2[2*i] = pSrc[i]; + pTmp2[2*i+1] = 0; + } + arm_cfft_q31(&(S->cfft),pTmp2,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_q31(&(S->rfft),pSrc,pTmp2); +#endif + filterLimit = 1 + (S->fftLen >> 1); + + + // q31 - fftShift + arm_cmplx_mag_q31(pTmp2,pSrc,filterLimit); + // q30 - fftShift + + + /* Apply MEL filters */ + coefsPos = 0; + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_q31(pSrc+S->filterPos[i], + &(S->filterCoefs[coefsPos]), + S->filterLengths[i], + &result); + + coefsPos += S->filterLengths[i]; + + // q16.48 - fftShift + result += MICRO_Q31; + result >>= (SHIFT_MELFILTER_SATURATION_Q31 + 18); + // q16.29 - fftShift - satShift + pTmp[i] = __SSAT(result,31) ; + + } + + + // q16.29 - fftShift - satShift + /* Compute the log */ + arm_vlog_q31(pTmp,pTmp,S->nbMelFilters); + + + // q5.26 + + logExponent = fftShift + 2 + SHIFT_MELFILTER_SATURATION_Q31; + logExponent = logExponent * LOG2TOLOG_Q31; + + + // q5.26 + arm_offset_q31(pTmp,logExponent,pTmp,S->nbMelFilters); + arm_shift_q31(pTmp,-3,pTmp,S->nbMelFilters); + + + // q8.23 + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(q31_t*)S->dctCoefs; + + arm_mat_vec_mult_q31(&pDctMat, pTmp, pDst); + + return(status); +} + +/** + @} end of MFCC group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c new file mode 100644 index 0000000..ea6d9df --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c @@ -0,0 +1,322 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +extern void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the floating-point RFFT/RIFFT. + Source buffer is modified by this function. + + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in] pSrc points to the input buffer + @param[out] pDst points to the output buffer + @return none + + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) and 0.0f + */ + +void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst) +{ + const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft; + + /* Calculation of Real IFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + + /* Complex radix-4 IFFT process */ + arm_radix4_butterfly_inverse_f32 (pDst, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier, S_CFFT->onebyfftLen); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pDst, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + } + else + { + /* Calculation of RFFT of input */ + + /* Complex radix-4 FFT process */ + arm_radix4_butterfly_f32 (pSrc, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pSrc, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + + /* Real FFT core process */ + arm_split_rfft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4U * fftLen) - 1U]; /* temp pointers for output buffer */ + float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2U * fftLen) - 1U]; /* temp pointers for input buffer */ + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + /* read pATable[2 * i] */ + CoefA1 = *pCoefA++; + /* pATable[2 * i + 1] */ + CoefA2 = *pCoefA; + + /* pSrc[2 * i] * pATable[2 * i] */ + outR = *pSrc1 * CoefA1; + /* pSrc[2 * i] * CoefA2 */ + outI = *pSrc1++ * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR -= (*pSrc1 + *pSrc2) * CoefA2; + /* pSrc[2 * i + 1] * CoefA1 */ + outI += *pSrc1++ * CoefA1; + + CoefB1 = *pCoefB; + + /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI -= *pSrc2 * CoefA2; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2-- * CoefB1; + + /* write output */ + *pDst1++ = outR; + *pDst1++ = outI; + + /* write complex conjugate output */ + *pDst2-- = -outI; + *pDst2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2U); + pCoefA = pCoefA + ((modifier * 2U) - 1U); + + i--; + + } + + pDst[2U * fftLen] = pSrc[0] - pSrc[1]; + pDst[(2U * fftLen) + 1U] = 0.0f; + + pDst[0] = pSrc[0] + pSrc[1]; + pDst[1] = 0.0f; + +} + + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2U * fftLen) + 1U]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * CoefA1 */ + outR = *pSrc1 * CoefA1; + + /* - pSrc[2 * i] * CoefA2 */ + outI = -(*pSrc1++) * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR += (*pSrc1 + *pSrc2) * CoefA2; + + /* pSrc[2 * i + 1] * CoefA1 */ + outI += (*pSrc1++) * CoefA1; + + CoefB1 = *pCoefB; + + /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2 * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI += *pSrc2-- * CoefA2; + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c new file mode 100644 index 0000000..367b2ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c @@ -0,0 +1,523 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f16.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void stage_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b; /* temporary variables */ + float16_t p0, p1, p2, p3; /* temporary variables */ + + float16x8x2_t tw,xA,xB; + float16x8x2_t tmp1, tmp2, res; + + uint16x8_t vecStridesBkwd; + + vecStridesBkwd = vddupq_u16((uint16_t)14, 2); + + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = (_Float16)xBR + (_Float16)xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f16 * ( (_Float16)t1a + (_Float16)t1b ); + *pOut++ = 0.5f16 * ( (_Float16)t1a - (_Float16)t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k - 14; + pA += 2; + + blockCnt = k >> 3; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + + xA = vld2q_f16(pA); + pA += 16; + + xB = vld2q_f16(pB); + + xB.val[0] = vldrhq_gather_shifted_offset_f16(pB, vecStridesBkwd); + xB.val[1] = vldrhq_gather_shifted_offset_f16(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f16(xB.val[1]); + pB -= 16; + + + tw = vld2q_f16(pCoeff); + pCoeff += 16; + + + tmp1.val[0] = vaddq_f16(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f16(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f16(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f16(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f16(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f16(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f16(res.val[0], 0.5f); + res.val[1] = vmulq_n_f16(res.val[1], 0.5f); + + + vst2q_f16(pOut, res); + pOut += 16; + + + blockCnt--; + } + + pB += 14; + blockCnt = k & 7; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xBR - (_Float16)xAR ; + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = (_Float16)twR * (_Float16)t1a; + p1 = (_Float16)twI * (_Float16)t1a; + p2 = (_Float16)twR * (_Float16)t1b; + p3 = (_Float16)twI * (_Float16)t1b; + + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR + (_Float16)p0 + (_Float16)p3 ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)p1 - (_Float16)p2 ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b, r, s, t, u; /* temporary variables */ + + float16x8x2_t tw,xA,xB; + float16x8x2_t tmp1, tmp2, res; + uint16x8_t vecStridesBkwd; + + vecStridesBkwd = vddupq_u16((uint16_t)14, 2); + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f16 * ( (_Float16)xAR + (_Float16)xAI ); + *pOut++ = 0.5f16 * ( (_Float16)xAR - (_Float16)xAI ); + + pB = p + 2*k - 14; + pA += 2 ; + + blockCnt = k >> 3; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xA = vld2q_f16(pA); + pA += 16; + + xB = vld2q_f16(pB); + + xB.val[0] = vldrhq_gather_shifted_offset_f16(pB, vecStridesBkwd); + xB.val[1] = vldrhq_gather_shifted_offset_f16(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f16(xB.val[1]); + pB -= 16; + + + tw = vld2q_f16(pCoeff); + tw.val[1] = vnegq_f16(tw.val[1]); + pCoeff += 16; + + + tmp1.val[0] = vaddq_f16(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f16(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f16(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f16(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f16(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f16(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f16(res.val[0], 0.5f); + res.val[1] = vmulq_n_f16(res.val[1], 0.5f); + + + vst2q_f16(pOut, res); + pOut += 16; + + + blockCnt--; + } + + pB += 14; + blockCnt = k & 7; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xAR - (_Float16)xBR ; + t1b = (_Float16)xAI + (_Float16)xBI ; + + r = (_Float16)twR * (_Float16)t1a; + s = (_Float16)twI * (_Float16)t1b; + t = (_Float16)twI * (_Float16)t1a; + u = (_Float16)twR * (_Float16)t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR - (_Float16)r - (_Float16)s ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)t - (_Float16)u ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } + +} +#else +void stage_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b; /* temporary variables */ + float16_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = (_Float16)xBR + (_Float16)xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f16 * ( (_Float16)t1a + (_Float16)t1b ); + *pOut++ = 0.5f16 * ( (_Float16)t1a - (_Float16)t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xBR - (_Float16)xAR ; + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = (_Float16)twR * (_Float16)t1a; + p1 = (_Float16)twI * (_Float16)t1a; + p2 = (_Float16)twR * (_Float16)t1b; + p3 = (_Float16)twI * (_Float16)t1b; + + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR + (_Float16)p0 + (_Float16)p3 ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)p1 - (_Float16)p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f16 * ( (_Float16)xAR + (_Float16)xAI ); + *pOut++ = 0.5f16 * ( (_Float16)xAR - (_Float16)xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xAR - (_Float16)xBR ; + t1b = (_Float16)xAI + (_Float16)xBI ; + + r = (_Float16)twR * (_Float16)t1a; + s = (_Float16)twI * (_Float16)t1b; + t = (_Float16)twI * (_Float16)t1a; + u = (_Float16)twR * (_Float16)t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR - (_Float16)r - (_Float16)s ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)t - (_Float16)u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @ingroup groupTransforms +*/ + + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f16 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut, + uint8_t ifftFlag) +{ + const arm_cfft_instance_f16 * Sint = &(S->Sint); + + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f16(S, p, pOut); + /* Complex radix-4 IFFT process */ + arm_cfft_f16( Sint, pOut, ifftFlag, 1); + } + else + { + + /* Calculation of RFFT of input */ + arm_cfft_f16( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f16(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c new file mode 100644 index 0000000..c93f6a0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c @@ -0,0 +1,609 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void stage_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + float32x4x2_t tw,xA,xB; + float32x4x2_t tmp1, tmp2, res; + + uint32x4_t vecStridesFwd, vecStridesBkwd; + + vecStridesFwd = vidupq_u32((uint32_t)0, 2); + vecStridesBkwd = -vecStridesFwd; + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + blockCnt = k >> 2; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + + xA = vld2q_f32(pA); + pA += 8; + + xB = vld2q_f32(pB); + + xB.val[0] = vldrwq_gather_shifted_offset_f32(pB, vecStridesBkwd); + xB.val[1] = vldrwq_gather_shifted_offset_f32(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f32(xB.val[1]); + pB -= 8; + + + tw = vld2q_f32(pCoeff); + pCoeff += 8; + + + tmp1.val[0] = vaddq_f32(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f32(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f32(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f32(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f32(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f32(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f32(res.val[0], 0.5f); + res.val[1] = vmulq_n_f32(res.val[1], 0.5f); + + + vst2q_f32(pOut, res); + pOut += 8; + + + blockCnt--; + } + + blockCnt = k & 3; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + float32x4x2_t tw,xA,xB; + float32x4x2_t tmp1, tmp2, res; + uint32x4_t vecStridesFwd, vecStridesBkwd; + + vecStridesFwd = vidupq_u32((uint32_t)0, 2); + vecStridesBkwd = -vecStridesFwd; + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + blockCnt = k >> 2; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xA = vld2q_f32(pA); + pA += 8; + + xB = vld2q_f32(pB); + + xB.val[0] = vldrwq_gather_shifted_offset_f32(pB, vecStridesBkwd); + xB.val[1] = vldrwq_gather_shifted_offset_f32(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f32(xB.val[1]); + pB -= 8; + + + tw = vld2q_f32(pCoeff); + tw.val[1] = vnegq_f32(tw.val[1]); + pCoeff += 8; + + + tmp1.val[0] = vaddq_f32(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f32(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f32(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f32(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f32(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f32(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f32(res.val[0], 0.5f); + res.val[1] = vmulq_n_f32(res.val[1], 0.5f); + + + vst2q_f32(pOut, res); + pOut += 8; + + + blockCnt--; + } + + blockCnt = k & 3; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } + +} +#else +void stage_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The CMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorithm relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.gif "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.gif "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref arm_rfft_fast_f32() and \ref arm_rfft_fast_init_f32(). + The older functions \ref arm_rfft_f32() and \ref arm_rfft_init_f32() have been deprecated + but are still documented. + For f16, the functions are \ref arm_rfft_fast_f16() and \ref arm_rfft_fast_init_f16(). + For f64, the functions are \ref arm_rfft_fast_f64() and \ref arm_rfft_fast_init_f64(). + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + Due to the use of complex transform internally, the source buffer is + modified by the rfft. + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional **except for MVE versions where it is mandatory**. + If you don't use the initialization functions, then the structures should be initialized with code + similar to the one below: + 
+      arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform (fftLenReal/2). + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. +@par + Note that with MVE versions you can't initialize instance structures directly and **must + use the initialization function**. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f32 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut, + uint8_t ifftFlag) +{ + const arm_cfft_instance_f32 * Sint = &(S->Sint); + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f32(S, p, pOut); + /* Complex radix-4 IFFT process */ + arm_cfft_f32( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + arm_cfft_f32( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f32(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c new file mode 100644 index 0000000..2b0ba10 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c @@ -0,0 +1,232 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f64.c + * Description: RFFT & RIFFT Double precision Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +void stage_rfft_f64( + const arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b; /* temporary variables */ + float64_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5 * ( t1a + t1b ); + *pOut++ = 0.5 * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5 * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5 * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + k--; + } while (k > 0U); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f64( + const arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5 * ( xAR + xAI ); + *pOut++ = 0.5 * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0U) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5 * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5 * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +/** + @ingroup groupTransforms +*/ + + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the Double Precision floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f64 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut, + uint8_t ifftFlag) +{ + arm_cfft_instance_f64 * Sint = &(S->Sint); + Sint->fftLen = S->fftLenRFFT / 2; + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f64(S, p, pOut); + + /* Complex radix-4 IFFT process */ + arm_cfft_f64( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + arm_cfft_f64( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f64(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c new file mode 100644 index 0000000..1496b74 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c @@ -0,0 +1,361 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f16.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables_f16.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f16( + arm_rfft_fast_instance_f16 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f16 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f16; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c new file mode 100644 index 0000000..f469ac4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c @@ -0,0 +1,356 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f32.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_32_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_64_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_128_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +arm_status arm_rfft_256_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_512_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_1024_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +arm_status arm_rfft_2048_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +arm_status arm_rfft_4096_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f32( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f32 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f32; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c new file mode 100644 index 0000000..e653f86 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c @@ -0,0 +1,348 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f64.c + * Description: Split Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16) && defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) + +/** + @brief Initialization function for the 32pt double precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 16U; + S->fftLenRFFT = 32U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_16; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_16; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) + +/** + @brief Initialization function for the 64pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 32U; + S->fftLenRFFT = 64U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_32; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_32; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) + +/** + @brief Initialization function for the 128pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 64U; + S->fftLenRFFT = 128U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_64; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_64; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) + +/** + @brief Initialization function for the 256pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 128U; + S->fftLenRFFT = 256U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_128; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_128; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) + +/** + @brief Initialization function for the 512pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 256U; + S->fftLenRFFT = 512U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_256; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_256; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +/** + @brief Initialization function for the 1024pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 512U; + S->fftLenRFFT = 1024U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_512; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_512; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +/** + @brief Initialization function for the 2048pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 1024U; + S->fftLenRFFT = 2048U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_1024; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_1024; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +/** +* @brief Initialization function for the 4096pt Double Precision floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 2048U; + S->fftLenRFFT = 4096U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_2048; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_2048; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f64( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f64 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16) && defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f64; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c new file mode 100644 index 0000000..e1b088d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c @@ -0,0 +1,151 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_f32.c + * Description: RFFT & RIFFT Floating point initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the floating-point RFFT/RIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in,out] S_CFFT points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLenReal length of the FFT. + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Description + The parameter fftLenRealspecifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 128, 512, 2048. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Complex FFT length */ + S->fftLenBy2 = (uint16_t) fftLenReal / 2U; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (float32_t *) realCoefA; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (float32_t *) realCoefB; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLenReal) + { + /* Init table modifier value */ + case 8192U: + S->twidCoefRModifier = 1U; + break; + case 2048U: + S->twidCoefRModifier = 4U; + break; + case 512U: + S->twidCoefRModifier = 16U; + break; + case 128U: + S->twidCoefRModifier = 64U; + break; + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + /* Init Complex FFT Instance */ + S->pCfft = S_CFFT; + + if (S->ifftFlagR) + { + /* Initializes the CIFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1U, 0U); + } + else + { + /* Initializes the CFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0U, 0U); + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); + +} + +/** + @} end of RealFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c new file mode 100644 index 0000000..79b0f4c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c @@ -0,0 +1,252 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q15.c + * Description: RFFT & RIFFT Q15 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q15 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q15_t *) realCoefAQ15; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q15_t *) realCoefBQ15; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + S->twidCoefRModifier = 1U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),4096); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len4096; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len2048; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len1024; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len512; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len256; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len128; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len64; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len32; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len16; + #endif + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c new file mode 100644 index 0000000..fa81090 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c @@ -0,0 +1,250 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q31.c + * Description: RFFT & RIFFT Q31 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_common_tables.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" + + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q31 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. +*/ + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q31_t *) realCoefAQ31; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q31_t *) realCoefBQ31; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + + + S->twidCoefRModifier = 1U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),4096); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len4096; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len2048; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len1024; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len512; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len256; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len128; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len64; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len32; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len16; + #endif + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c new file mode 100644 index 0000000..ee8b613 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c @@ -0,0 +1,554 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q15.c + * Description: RFFT & RIFFT Q15 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q15 RFFT/RIFFT. + @param[in] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function.) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par Input and Output formats for RFFT Q15 + +| RFFT Size | Input Format | Output Format | Number of bits to upscale | +| ---------: | ------------: | -------------: | ------------------------: | +| 32 | 1.15 | 5.11 | 5 | +| 64 | 1.15 | 6.10 | 6 | +| 128 | 1.15 | 7.9 | 7 | +| 256 | 1.15 | 8.8 | 8 | +| 512 | 1.15 | 9.7 | 9 | +| 1024 | 1.15 | 10.6 | 10 | +| 2048 | 1.15 | 11.5 | 11 | +| 4096 | 1.15 | 12.4 | 12 | +| 8192 | 1.15 | 13.3 | 13 | + + @par Input and Output formats for RIFFT Q15 + +| RIFFT Size | Input Format | Output Format | Number of bits to upscale | +| ----------: | ------------: | -------------: | ------------------------: | +| 32 | 1.15 | 5.11 | 0 | +| 64 | 1.15 | 6.10 | 0 | +| 128 | 1.15 | 7.9 | 0 | +| 256 | 1.15 | 8.8 | 0 | +| 512 | 1.15 | 9.7 | 0 | +| 1024 | 1.15 | 10.6 | 0 | +| 2048 | 1.15 | 11.5 | 0 | +| 4096 | 1.15 | 12.4 | 0 | +| 8192 | 1.15 | 13.3 | 0 | + + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + */ + +void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst) +{ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const arm_cfft_instance_q15 *S_CFFT = &(S->cfftInst); +#else + const arm_cfft_instance_q15 *S_CFFT = S->pCfft; +#endif + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q15 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + arm_shift_q15(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q15 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real FFT + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" + +#if defined(__CMSIS_GCC_H) +#define MVE_CMPLX_MULT_FX_AxB_S16(A,B) vqdmladhxq_s16(vqdmlsdhq_s16((__typeof(A))vuninitializedq_s16(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB_S16(A,B) vqdmladhq_s16(vqdmlsdhxq_s16((__typeof(A))vuninitializedq_s16(), A, B), A, B) + +#endif + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pOut1 = &pDst[2]; + q15_t *pIn1 = &pSrc[2]; + uint16x8_t offsetIn = { 6, 7, 4, 5, 2, 3, 0, 1 }; + uint16x8_t offsetCoef; + const uint16_t offsetCoefArr[16] = { + 0, 0, 2, 2, 4, 4, 6, 6, + 0, 1, 0, 1, 0, 1, 0, 1 + }; + + offsetCoef = vmulq_n_u16(vld1q_u16(offsetCoefArr), modifier) + vld1q_u16(offsetCoefArr + 8); + offsetIn = vaddq_n_u16(offsetIn, (2 * fftLen - 8)); + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + const q15_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[2]; + + i = fftLen - 1U; + i = i / 4 + 1; + while (i > 0U) { + q15x8_t in1 = vld1q_s16(pIn1); + q15x8_t in2 = vldrhq_gather_shifted_offset_s16(pSrc, offsetIn); + q15x8_t coefA = vldrhq_gather_shifted_offset_s16(pCoefAb, offsetCoef); + q15x8_t coefB = vldrhq_gather_shifted_offset_s16(pCoefBb, offsetCoef); + +#if defined(__CMSIS_GCC_H) + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxB_S16(in1, coefA), + MVE_CMPLX_MULT_FX_AxConjB_S16(coefB, in2)); +#else + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxB(in1, coefA, q15x8_t), + MVE_CMPLX_MULT_FX_AxConjB(coefB, in2, q15x8_t)); +#endif + vst1q_s16(pOut1, out); + pOut1 += 8; + + offsetCoef = vaddq_n_u16(offsetCoef, modifier * 8); + offsetIn -= 8; + pIn1 += 8; + i -= 1; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#else +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; +#if defined (ARM_MATH_DSP) + q15_t *pD1, *pD2; +#endif + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + pSrc1 = &pSrc[2]; + pSrc2 = &pSrc[(2U * fftLen) - 2U]; + +#if defined (ARM_MATH_DSP) + + i = 1U; + pD1 = pDst + 2; + pD2 = pDst + (4U * fftLen) - 2; + + for (i = fftLen - 1; i > 0; i--) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]) + */ + + +#ifndef ARM_MATH_BIG_ENDIAN + /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + outR = __SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA)); +#else + /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */ + outR = -(__SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMLAD(read_q15x2 (pSrc2), read_q15x2((q15_t *) pCoefB), outR) >> 16U; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMUSDX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + outI = __SMUSDX(read_q15x2 ((q15_t *) pCoefB), read_q15x2_da (&pSrc2)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */ + outI = __SMLADX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), outI); + + /* write output */ + *pD1++ = (q15_t) outR; + *pD1++ = outI >> 16U; + + /* write complex conjugate output */ + pD2[0] = (q15_t) outR; + pD2[1] = -(outI >> 16U); + pD2 -= 2; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; + +#else + + i = 1U; + + while (i < fftLen) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + */ + + outR = *pSrc1 * *pCoefA; + outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1)); + outR = outR + (*pSrc2 * *pCoefB); + outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16; + + /* + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + outI = *pSrc2 * *(pCoefB + 1); + outI = outI - (*(pSrc2 + 1) * *pCoefB); + outI = outI + (*(pSrc1 + 1) * *pCoefA); + outI = outI + (*pSrc1 * *(pCoefA + 1)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + pDst[2U * i] = (q15_t) outR; + pDst[2U * i + 1U] = outI >> 16U; + + /* write complex conjugate output */ + pDst[(4U * fftLen) - (2U * i)] = (q15_t) outR; + pDst[((4U * fftLen) - (2U * i)) + 1U] = -(outI >> 16U); + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + + i++; + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1; + pDst[1] = 0; + +#endif /* #if defined (ARM_MATH_DSP) */ +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real IFFT + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pIn1; + uint16x8_t offset = { 6, 7, 4, 5, 2, 3, 0, 1 }; + uint16x8_t offsetCoef; + int16x8_t conj = { 1, -1, 1, -1, 1, -1, 1, -1 }; /* conjugate */ + const uint16_t offsetCoefArr[16] = { + 0, 0, 2, 2, 4, 4, 6, 6, + 0, 1, 0, 1, 0, 1, 0, 1 + }; + + offsetCoef = vmulq_n_u16(vld1q_u16(offsetCoefArr), modifier) + vld1q_u16(offsetCoefArr + 8); + + offset = vaddq_n_u16(offset, (2 * fftLen - 6)); + + /* Init coefficient pointers */ + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + const q15_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[0]; + + i = fftLen; + i = i / 4; + + while (i > 0U) { + q15x8_t in1 = vld1q_s16(pIn1); + q15x8_t in2 = vldrhq_gather_shifted_offset_s16(pSrc, offset); + q15x8_t coefA = vldrhq_gather_shifted_offset_s16(pCoefAb, offsetCoef); + q15x8_t coefB = vldrhq_gather_shifted_offset_s16(pCoefBb, offsetCoef); + + /* can we avoid the conjugate here ? */ + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxConjB(in1, coefA, q15x8_t), + vmulq(conj, MVE_CMPLX_MULT_FX_AxB(in2, coefB, q15x8_t))); + + vst1q_s16(pDst, out); + pDst += 8; + + offsetCoef = vaddq_n_u16(offsetCoef, modifier * 8); + offset -= 8; + + pIn1 += 8; + i -= 1; + } +} +#else +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; + q15_t *pDst1 = &pDst[0]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + pSrc1 = &pSrc[0]; + pSrc2 = &pSrc[2 * fftLen]; + + i = fftLen; + while (i > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + +#if defined (ARM_MATH_DSP) + +#ifndef ARM_MATH_BIG_ENDIAN + /* pIn[2 * n - 2 * i] * pBTable[2 * i] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */ + outR = -(__SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] + pIn[2 * n - 2 * i] * pBTable[2 * i] */ + outR = __SMLAD(read_q15x2(pSrc1), read_q15x2 ((q15_t *) pCoefA), outR) >> 16U; + + /* -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + outI = __SMUADX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); + + /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMLSDX(read_q15x2 ((q15_t *) pCoefA), read_q15x2_ia (&pSrc1), -outI); +#else + outI = __SMLSDX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), -outI); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* write output */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst1, __PKHBT(outR, (outI >> 16U), 16)); +#else + write_q15x2_ia (&pDst1, __PKHBT((outI >> 16U), outR, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + outR = *pSrc2 * *pCoefB; + outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1)); + outR = outR + (*pSrc1 * *pCoefA); + outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16; + + outI = *(pSrc1 + 1) * *pCoefA; + outI = outI - (*pSrc1 * *(pCoefA + 1)); + outI = outI - (*pSrc2 * *(pCoefB + 1)); + outI = outI - (*(pSrc2 + 1) * *(pCoefB)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + *pDst1++ = (q15_t) outR; + *pDst1++ = (q15_t) (outI >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier); + + i--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c new file mode 100644 index 0000000..20d93cf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c @@ -0,0 +1,458 @@ +#include "edge-impulse-sdk/dsp/config.hpp" +#if EIDSP_LOAD_CMSIS_DSP_SOURCES +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q31.c + * Description: FFT & RIFFT Q31 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q31 RFFT/RIFFT. + @param[in] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par Input and Output formats for RFFT Q31 + +| RFFT Size | Input Format | Output Format | Number of bits to upscale | +| ---------: | ------------: | -------------: | ------------------------: | +| 32 | 1.31 | 5.27 | 5 | +| 64 | 1.31 | 6.26 | 6 | +| 128 | 1.31 | 7.25 | 7 | +| 256 | 1.31 | 8.24 | 8 | +| 512 | 1.31 | 9.23 | 9 | +| 1024 | 1.31 | 10.22 | 10 | +| 2048 | 1.31 | 11.21 | 11 | +| 4096 | 1.31 | 12.20 | 12 | +| 8192 | 1.31 | 13.19 | 13 | + + @par Input and Output formats for RIFFT Q31 + +| RIFFT Size | Input Format | Output Format | Number of bits to upscale | +| ----------: | ------------: | -------------: | ------------------------: | +| 32 | 1.31 | 5.27 | 0 | +| 64 | 1.31 | 6.26 | 0 | +| 128 | 1.31 | 7.25 | 0 | +| 256 | 1.31 | 8.24 | 0 | +| 512 | 1.31 | 9.23 | 0 | +| 1024 | 1.31 | 10.22 | 0 | +| 2048 | 1.31 | 11.21 | 0 | +| 4096 | 1.31 | 12.20 | 0 | +| 8192 | 1.31 | 13.19 | 0 | + + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + + */ + +void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst) +{ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const arm_cfft_instance_q31 *S_CFFT = &(S->cfftInst); +#else + const arm_cfft_instance_q31 *S_CFFT = S->pCfft; +#endif + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q31 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + arm_shift_q31(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q31 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_helium_utils.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_vec_fft.h" + +#if defined(__CMSIS_GCC_H) + +#define MVE_CMPLX_MULT_FX_AxB_S32(A,B) vqdmladhxq_s32(vqdmlsdhq_s32((__typeof(A))vuninitializedq_s32(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB_S32(A,B) vqdmladhq_s32(vqdmlsdhxq_s32((__typeof(A))vuninitializedq_s32(), A, B), A, B) + +#endif + +void arm_split_rfft_q31( + q31_t *pSrc, + uint32_t fftLen, + const q31_t *pATable, + const q31_t *pBTable, + q31_t *pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t *pOut1 = &pDst[2]; + q31_t *pIn1 = &pSrc[2]; + uint32x4_t offset = { 2, 3, 0, 1 }; + uint32x4_t offsetCoef = { 0, 1, modifier * 2, modifier * 2 + 1 }; + + offset = offset + (2 * fftLen - 4); + + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + const q31_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[2]; + + i = fftLen - 1U; + i = i / 2 + 1; + while (i > 0U) { + q31x4_t in1 = vld1q_s32(pIn1); + q31x4_t in2 = vldrwq_gather_shifted_offset_s32(pSrc, offset); + q31x4_t coefA = vldrwq_gather_shifted_offset_s32(pCoefAb, offsetCoef); + q31x4_t coefB = vldrwq_gather_shifted_offset_s32(pCoefBb, offsetCoef); +#if defined(__CMSIS_GCC_H) + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxB_S32(in1, coefA),MVE_CMPLX_MULT_FX_AxConjB_S32(coefB, in2)); +#else + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxB(in1, coefA, q31x4_t), + MVE_CMPLX_MULT_FX_AxConjB(coefB, in2, q31x4_t)); +#endif + vst1q(pOut1, out); + pOut1 += 4; + + offsetCoef += modifier * 4; + offset -= 4; + + pIn1 += 4; + i -= 1; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#else +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[4 * fftLen - 1]; + q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[2 * fftLen - 1]; + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* outI = pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, CoefA2); + + /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + multSub_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* (pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pOut1++ = outR; + *pOut1++ = outI; + + /* write complex conjugate output */ + *pOut2-- = -outI; + *pOut2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier - 1); + + /* Decrement loop count */ + i--; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t *pIn1; + uint32x4_t offset = { 2, 3, 0, 1 }; + uint32x4_t offsetCoef = { 0, 1, modifier * 2, modifier * 2 + 1 }; + int32x4_t conj = { 1, -1, 1, -1 }; + + offset = offset + (2 * fftLen - 2); + + /* Init coefficient pointers */ + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + const q31_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[0]; + + i = fftLen; + i = i >> 1; + while (i > 0U) { + q31x4_t in1 = vld1q_s32(pIn1); + q31x4_t in2 = vldrwq_gather_shifted_offset_s32(pSrc, offset); + q31x4_t coefA = vldrwq_gather_shifted_offset_s32(pCoefAb, offsetCoef); + q31x4_t coefB = vldrwq_gather_shifted_offset_s32(pCoefBb, offsetCoef); + + /* can we avoid the conjugate here ? */ +#if defined(__CMSIS_GCC_H) + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxConjB_S32(in1, coefA), + vmulq_s32(conj, MVE_CMPLX_MULT_FX_AxB_S32(in2, coefB))); +#else + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxConjB(in1, coefA, q31x4_t), + vmulq_s32(conj, MVE_CMPLX_MULT_FX_AxB(in2, coefB, q31x4_t))); +#endif + vst1q_s32(pDst, out); + pDst += 4; + + offsetCoef += modifier * 4; + offset -= 4; + + pIn1 += 4; + i -= 1; + } +} +#else +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[2 * fftLen + 1]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pIn[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* - pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, -CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pIn[2 * n - 2 * i] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ + +#endif // EIDSP_LOAD_CMSIS_DSP_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_math_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_math_types.h new file mode 100644 index 0000000..d650980 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_math_types.h @@ -0,0 +1,172 @@ +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * @file arm_nn_math_types.h + * @brief Compiler include and basic types + * @version V1.2.0 + * @date 20 June 2022 + * Target Processor: Cortex-M + ******************************************************************************/ + +/** + Copied from CMSIS/DSP/arm_math_types.h and modified +*/ + +#ifndef _ARM_NN_MATH_TYPES_H_ + +#define _ARM_NN_MATH_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +/* Integer aliases */ +typedef int8_t q7_t; +typedef int16_t q15_t; +typedef int32_t q31_t; +typedef int64_t q63_t; + +/* Compiler specific diagnostic adjustment */ +#if defined(__CC_ARM) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#elif defined(__GNUC__) + +#elif defined(__ICCARM__) + +#elif defined(__TI_ARM__) + +#elif defined(__CSMC__) + +#elif defined(__TASKING__) + +#elif defined(_MSC_VER) + +#else +#error Unknown compiler +#endif + +/* Included for instrinsics definitions */ +#if defined(_MSC_VER) +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static __inline +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __declspec(align(x)) +#endif + +#elif defined(__GNUC_PYTHON__) +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +#else +#include "edge-impulse-sdk/CMSIS/Core/Include/cmsis_compiler.h" +#endif + +/* evaluate ARM DSP feature */ +#if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#ifndef ARM_MATH_DSP +#define ARM_MATH_DSP 1 +#endif +#endif + +#if __ARM_FEATURE_MVE +#ifndef ARM_MATH_MVEI +#define ARM_MATH_MVEI +#endif +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined(__CC_ARM) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#elif defined(__GNUC__) +// #pragma GCC diagnostic pop + +#elif defined(__ICCARM__) + +#elif defined(__TI_ARM__) + +#elif defined(__CSMC__) + +#elif defined(__TASKING__) + +#elif defined(_MSC_VER) + +#else +#error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + +#if __ARM_FEATURE_MVE +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Add necessary typedefs + */ + +#define NN_Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define NN_Q15_MAX ((q15_t)(0x7FFF)) +#define NN_Q7_MAX ((q7_t)(0x7F)) +#define NN_Q31_MIN ((q31_t)(0x80000000L)) +#define NN_Q15_MIN ((q15_t)(0x8000)) +#define NN_Q7_MIN ((q7_t)(0x80)) + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum +{ + ARM_CMSIS_NN_SUCCESS = 0, /**< No error */ + ARM_CMSIS_NN_ARG_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_CMSIS_NN_NO_IMPL_ERROR = -2, /**< No implementation available */ +} arm_cmsis_nn_status; + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_NN_MATH_TYPES_H_ */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_tables.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_tables.h new file mode 100644 index 0000000..85a7537 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_tables.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_tables.h + * Description: Extern declaration for NN tables + * + * $Date: 17. August 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_NN_TABLES_H +#define _ARM_NN_TABLES_H + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_math_types.h" + +/** + * @brief tables for various activation functions + * + */ + +extern const q15_t sigmoidTable_q15[256]; +extern const q7_t sigmoidTable_q7[256]; + +extern const q7_t tanhTable_q7[256]; +extern const q15_t tanhTable_q15[256]; + +/** + * @brief 2-way tables for various activation functions + * + * 2-way table, H table for value larger than 1/4 + * L table for value smaller than 1/4, H table for remaining + * We have this only for the q15_t version. It does not make + * sense to have it for q7_t type + */ +extern const q15_t sigmoidHTable_q15[192]; +extern const q15_t sigmoidLTable_q15[128]; + +#endif /* ARM_NN_TABLES_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h new file mode 100644 index 0000000..6040d72 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_types.h + * Description: Public header file to contain the CMSIS-NN structs for the + * TensorFlowLite micro compliant functions + * + * $Date: 22. Februari 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NN_TYPES_H +#define _ARM_NN_TYPES_H + +#include + +/** CMSIS-NN object to contain the width and height of a tile */ +typedef struct +{ + int32_t w; /**< Width */ + int32_t h; /**< Height */ +} cmsis_nn_tile; + +/** CMSIS-NN object used for the function context. */ +typedef struct +{ + void *buf; /**< Pointer to a buffer needed for the optimization */ + int32_t size; /**< Buffer size */ +} cmsis_nn_context; + +/** CMSIS-NN object to contain the dimensions of the tensors */ +typedef struct +{ + int32_t n; /**< Generic dimension to contain either the batch size or output channels. + Please refer to the function documentation for more information */ + int32_t h; /**< Height */ + int32_t w; /**< Width */ + int32_t c; /**< Input channels */ +} cmsis_nn_dims; + +/** CMSIS-NN object for the per-channel quantization parameters */ +typedef struct +{ + int32_t *multiplier; /**< Multiplier values */ + int32_t *shift; /**< Shift values */ +} cmsis_nn_per_channel_quant_params; + +/** CMSIS-NN object for the per-tensor quantization parameters */ +typedef struct +{ + int32_t multiplier; /**< Multiplier value */ + int32_t shift; /**< Shift value */ +} cmsis_nn_per_tensor_quant_params; + +/** CMSIS-NN object for the quantized Relu activation */ +typedef struct +{ + int32_t min; /**< Min value used to clamp the result */ + int32_t max; /**< Max value used to clamp the result */ +} cmsis_nn_activation; + +/** CMSIS-NN object for the convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_tile dilation; + cmsis_nn_activation activation; +} cmsis_nn_conv_params; + +/** CMSIS-NN object for Depthwise convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + int32_t ch_mult; /**< Channel Multiplier. ch_mult * in_ch = out_ch */ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_tile dilation; + cmsis_nn_activation activation; +} cmsis_nn_dw_conv_params; +/** CMSIS-NN object for pooling layer parameters */ +typedef struct +{ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_activation activation; +} cmsis_nn_pool_params; + +/** CMSIS-NN object for Fully Connected layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t filter_offset; /**< Zero value for the filter tensor. Not used */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_activation activation; +} cmsis_nn_fc_params; + +/** CMSIS-NN object for SVDF layer parameters */ +typedef struct +{ + int32_t rank; + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_activation input_activation; + cmsis_nn_activation output_activation; +} cmsis_nn_svdf_params; + +/** CMSIS-NN object for Softmax s16 layer parameters */ +typedef struct +{ + const int16_t *exp_lut; + const int16_t *one_by_one_lut; +} cmsis_nn_softmax_lut_s16; + +#endif // _ARM_NN_TYPES_H diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h new file mode 100644 index 0000000..1548a20 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h @@ -0,0 +1,2656 @@ +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnfunctions.h + * Description: Public header file for CMSIS NN Library + * + * $Date: 7 Aug 2022 + * $Revision: V.10.1.2 + * + * Target Processor: Cortex-M CPUs + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS NN Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS NN software library, + * a collection of efficient neural network kernels developed to maximize the + * performance and minimize the memory footprint of neural networks on Cortex-M processor cores. + * + * The library is divided into a number of functions each covering a specific category: + * - Convolution Functions + * - Activation Functions + * - Fully-connected Layer Functions + * - SVDF Layer Functions + * - Pooling Functions + * - Softmax Functions + * - Basic math Functions + * + * The library has separate functions for operating on different weight and activation data + * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the + * kernels are included in the function description. The implementation details are also + * described in this paper [1]. + * + * Supported Processors + * ------- + * CMSIS-NN targets Cortex-M processors with typically three different implementations for each function. Each + * targets a different group of processors. + * - Processors without SIMD capability (e.g, Cortex-M0) + * - Processors with DSP extention (e.g Cortex-M4) + * - Processors with MVE extension (e.g Cortex-M55) + * The right implementation is picked through feature flags and the user usually does not have to explicit set it. + * + * Function Classification + * -------- + * The functions can be classified into two segments + * - Legacy functions supporting ARM's internal symmetric quantization(8 bits). + * - Functions that support TensorFlow Lite framework with symmetric quantization(8 bits). + * + * The legacy functions can be identified with their suffix of _q7 or _q15 and are no new development is done there. + * The article in [2] describes in detail how to run a network using the legacy functions. + * + * The functions supporting TensorFlow Lite framework is identified by the _s8 suffix and can be invoked from TFL + * micro. The functions are bit exact to TensorFlow Lite. Refer to the TensorFlow's documentation in [3] on how to run + * a TensorFlow Lite model using optimized CMSIS-NN kernels. + * + * Block Diagram + * -------- + * \image html CMSIS-NN-OVERVIEW.PNG + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Pre-processor Macros + * ------------ + * + * Each library project have different pre-processor macros. + * + * - ARM_MATH_DSP: + * + * Define macro ARM_MATH_DSP, If the silicon supports DSP instructions(DSP extension). + * + * - ARM_MATH_MVEI: + * + * Define macro ARM_MATH_MVEI, If the silicon supports M-Profile Vector Extension. + + * - ARM_MATH_AUTOVECTORIZE + * Used in conjucture with ARM_MATH_MVEI to let the compiler auto vectorize for the functions that uses inline + * assembly. It does not affect functions that use C or intrinsics. + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. This is supported only for the legacy + * functions i.e, functions targetted at TensorFlow Lite do not support big endianness. By default library builds for + * little endian targets. + * + * - ARM_NN_TRUNCATE: + * + * Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation. + * + * + * Copyright Notice + * ------------ + * + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601 + * + * [2] Converting a Neural Network for Arm Cortex-M with CMSIS-NN + * + https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/converting-a-neural-network-for-arm-cortex-m-with-cmsis-nn/single-page + * [3] https://www.tensorflow.org/lite/microcontrollers/library + * + * [4] https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN#legacy-vs-tfl-micro-compliant-apis + */ + +/** + * @defgroup groupNN Neural Network Functions + * A collection of functions to perform basic operations for neural network layers. Functions with a _s8 suffix support + * TensorFlow Lite framework. + */ + +#ifndef _ARM_NNFUNCTIONS_H +#define _ARM_NNFUNCTIONS_H + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h" + +#define USE_INTRINSIC + +//#define ARM_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Struct for specifying activation function types + * + */ +typedef enum +{ + ARM_SIGMOID = 0, + /**< Sigmoid activation function */ + ARM_TANH = 1, + /**< Tanh activation function */ +} arm_nn_activation_type; + +/** + * @defgroup NNConv Convolution Functions + * + * Collection of convolution, depthwise convolution functions and their variants. + * + * The convolution is implemented in 2 steps: im2col and GEMM + * + * im2col is a process of converting each patch of image data into + * a column. After im2col, the convolution is computed as matrix-matrix + * multiplication. + * + * To reduce the memory footprint, the im2col is performed partially. + * Each iteration, only a few column (i.e., patches) are generated and + * computed with GEMM kernels similar to CMSIS-DSP arm_mat_mult functions. + * + */ + +/** + * @brief s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + * arm_convolve_wrapper_s8_get_buffer_size will return the buffer_size if required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR if argument constraints fail. or, + * ARM_CMSIS_NN_SUCCESS on successful completion. + * + */ +arm_cmsis_nn_status arm_convolve_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_wrapper_s8 + * + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] input_dims Input (activation) dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the spatial + * filter dimensions + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_wrapper_s8_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief s16 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + * arm_convolve_wrapper_s8_get_buffer_size will return the buffer_size if required + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + * + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR if argument constraints fail. or, + * ARM_CMSIS_NN_SUCCESS on successful completion. + * + */ +arm_cmsis_nn_status arm_convolve_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_wrapper_s16 + * + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] input_dims Input (activation) dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the spatial + * filter dimensions + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_wrapper_s16_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + * arm_convolve_s8_get_buffer_size will return the buffer_size if required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * + */ +arm_cmsis_nn_status arm_convolve_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for s8 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic s16 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + * arm_convolve_s16_get_buffer_size will return the buffer_size if required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7/q15 is used as data type eventhough it is s8/s16 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * + */ +arm_cmsis_nn_status arm_convolve_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); +/** + * @brief Optimized s16 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + * arm_convolve_fast_s16_get_buffer_size will return the buffer_size if required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions. (filter_dims->w * filter_dims->h * input_dims->c) must not + exceed 512 + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7/q15 is used as data type eventhough it is s8/s16 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * 4. Implementation supports kernel volumes (filter width * filter height * input channels) < 512. + * + */ + +arm_cmsis_nn_status arm_convolve_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for s16 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Get the required buffer size for fast s16 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ +arm_cmsis_nn_status arm_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q7 convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_CMSIS_NN_SUCCESS + */ +arm_cmsis_nn_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ +arm_cmsis_nn_status arm_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR or ARM_CMSIS_NN_SUCCESS based on the outcome of input arguments + * constraints checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +arm_cmsis_nn_status arm_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR or ARM_CMSIS_NN_SUCCESS based on the outcome of input arguments + * constraints checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_cmsis_nn_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR if argument constraints fail. or, + * ARM_CMSIS_NN_SUCCESS on successful completion. + * + * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for + * second half of MobileNets after depthwise separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +arm_cmsis_nn_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast s8 version for 1x1 convolution (non-square shape) + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + * arm_convolve_1x1_s8_fast_get_buffer_size will return the buffer_size if required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, 1, C_IN] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR if argument constraints fail. or, + * ARM_CMSIS_NN_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->c is a multiple of 4 + * -# conv_params->padding.w = conv_params->padding.h = 0 + * -# conv_params->stride.w = conv_params->stride.h = 1 + * + */ +arm_cmsis_nn_status arm_convolve_1x1_s8_fast(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_1x1_s8_fast + * + * @param[in] input_dims Input (activation) dimensions + * @return The function returns the required buffer size in bytes + * + */ +int32_t arm_convolve_1x1_s8_fast_get_buffer_size(const cmsis_nn_dims *input_dims); + +/** + * @brief 1xn convolution + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + * arm_convolve_1_x_n_s8_get_buffer_size will return the buffer_size if required + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the horizontal + * spatial filter dimension + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR if argument constraints fail. or, + * ARM_CMSIS_NN_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->n equals 1 + * -# ouput_dims->w is a multiple of 4 + * -# Explicit constraints(since it is for 1xN convolution) + * -## input_dims->h equals 1 + * -## output_dims->h equals 1 + * -## filter_dims->h equals 1 + *@todo Remove constraint on output_dims->w to make the function generic. + * + */ +arm_cmsis_nn_status arm_convolve_1_x_n_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required additional buffer size for 1xn convolution + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the + * horizontal spatial filter dimension + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_1_x_n_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Q7 version of convolution for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR or ARM_CMSIS_NN_SUCCESS based on the outcome of input arguments + * constraints checking. + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_cmsis_nn_status arm_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR or ARM_CMSIS_NN_SUCCESS based on the outcome of input arguments + * constraints checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + * dim_im_out is a multiple of 2 + */ + +arm_cmsis_nn_status arm_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR or ARM_CMSIS_NN_SUCCESS based on the outcome of input arguments + * constraints checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_cmsis_nn_status arm_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR or ARM_CMSIS_NN_SUCCESS based on the outcome of input arguments + * constraints checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +arm_cmsis_nn_status arm_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_CMSIS_NN_ARG_ERROR or ARM_CMSIS_NN_SUCCESS based on the outcome of input arguments + * constraints checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ +arm_cmsis_nn_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Wrapper function to pick the right optimized s8 depthwise convolution function + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_CMSIS_NN_SUCCESS - Successful completion. + * + * @details + * - Supported framework: TensorFlow Lite + * - Picks one of the the following functions + * -# arm_depthwise_conv_s8() + * -# arm_depthwise_conv_3x3_s8() - Cortex-M CPUs with DSP extension only + * -# arm_depthwise_conv_s8_opt() + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Check details of arm_depthwise_conv_s8_opt() for potential data that can be accessed outside of the + * boundary. + */ +arm_cmsis_nn_status arm_depthwise_conv_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get size of additional buffer required by arm_depthwise_conv_wrapper_s8() + * + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @return Size of additional memory required for optimizations in bytes. + * + */ +int32_t arm_depthwise_conv_wrapper_s8_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 depthwise convolution function that doesn't have any constraints on the input dimensions. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required exists if additional memory is. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Batch argument N is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +arm_cmsis_nn_status arm_depthwise_conv_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Basic s16 depthwise convolution function that doesn't have any constraints on the input dimensions. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * exists if additional memory is. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Batch argument N is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q15 is used as data type eventhough it is s16 data. It is done so to be consistent with existing APIs. + */ +arm_cmsis_nn_status arm_depthwise_conv_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Wrapper function to pick the right optimized s16 depthwise convolution function + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : Not used + * Range of dw_conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns + * ARM_CMSIS_NN_SUCCESS - Successful completion. + * + * @details + * - Supported framework: TensorFlow Lite + * - Picks one of the the following functions + * -# arm_depthwise_conv_s16() + * -# arm_depthwise_conv_fast_s16() - Cortex-M CPUs with DSP extension only + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +arm_cmsis_nn_status arm_depthwise_conv_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get size of additional buffer required by arm_depthwise_conv_wrapper_s16() + * + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * Range of dw_conv_params->input_offset : Not used + * Range of dw_conv_params->input_offset : Not used + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @return Size of additional memory required for optimizations in bytes. + * + */ +int32_t arm_depthwise_conv_wrapper_s16_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief Optimized s16 depthwise convolution function with constraint that in_channel equals out_channel. + * Refer arm_depthwise_conv_s16() for function argument details. + * + * @return The function returns one of the following + * ARM_CMSIS_NN_ARG_ERROR - ctx-buff == NULL and + * arm_depthwise_conv_fast_s16_get_buffer_size() > 0 or + * input channel != output channel or + * ch_mult != 1 + * + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + * @details + * - Supported framework: TensorFlow Lite + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels or ch_mult equals 1 + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Reccomended when number of channels is 4 or greater. + * + */ +arm_cmsis_nn_status arm_depthwise_conv_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for optimized s16 depthwise convolution + * function with constraint that in_channel equals out_channel. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [1, H, W, C_IN] + * Batch argument N is not used. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_depthwise_conv_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Optimized s8 depthwise convolution function for 3x3 kernel size with some constraints on + * the input arguments(documented below). Refer arm_depthwise_conv_s8() for function + * argument details. + * + * @return The function returns one of the following + * ARM_CMSIS_NN_ARG_ERROR - Unsupported dimension of tensors + * - Unsupported pad size along the x axis + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels + * -# Filter height and width equals 3 + * -# Padding along x is either 0 or 1. + * + */ +arm_cmsis_nn_status arm_depthwise_conv_3x3_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel. + * Refer arm_depthwise_conv_s8() for function argument details. + * + * @return The function returns one of the following + * ARM_CMSIS_NN_ARG_ERROR - input channel != output channel or + * ch_mult != 1 + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read out + * for the following if MVE optimizations(Arm Helium Technology) are used. + * - Output shift + * - Output multiplier + * - Output bias + * - kernel + * @details + * - Supported framework: TensorFlow Lite + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels or ch_mult equals 1 + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Reccomended when number of channels is 4 or greater. + * + */ +arm_cmsis_nn_status arm_depthwise_conv_s8_opt(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for optimized s8 depthwise convolution + * function with constraint that in_channel equals out_channel. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [1, H, W, C_IN] + * Batch argument N is not used. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_depthwise_conv_s8_opt_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @defgroup FC Fully-connected Layer Functions + * + * Collection of fully-connected and matrix multiplication functions. + * + * Fully-connected layer is basically a matrix-vector multiplication + * with bias. The matrix is the weights and the input/output vectors + * are the activation values. Supported {weight, activation} precisions + * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}. + * + * Here we have two types of kernel functions. The basic function + * implements the function using regular GEMV approach. The opt functions + * operates with weights in interleaved formats. + * + */ + +/** + *@brief Q7 basic fully-connected layer function + *@param[in] pV pointer to input vector + *@param[in] pM pointer to matrix weights + *@param[in] dim_vec length of the vector + *@param[in] num_of_rows number of rows in weight matrix + *@param[in] bias_shift amount of left-shift for bias + *@param[in] out_shift amount of right-shift for output + *@param[in] bias pointer to bias + *@param[in,out] pOut pointer to output vector + *@param[in,out] vec_buffer pointer to buffer space for input + *@return The function returns ARM_CMSIS_NN_SUCCESS + * + */ + +arm_cmsis_nn_status arm_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Basic s8 Fully Connected function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] fc_params Fully Connected layer parameters. + * Range of fc_params->input_offset : [-127, 128] + * fc_params->filter_offset : 0 + * Range of fc_params->output_offset : [-128, 127] + * @param[in] quant_params Per-tensor quantization info. + * It contains the multiplier and shift values to be applied to the output tensor. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Input dimension is taken as Nx(H * W * C_IN) + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Two dimensional filter dimensions. Format: [N, C] + * N : accumulation depth and equals (H * W * C_IN) from input_dims + * C : output depth and equals C_OUT in output_dims + * H & W : Not used + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * N, H, W : Not used + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, C_OUT] + * N : Batches + * C_OUT : Output depth + * H & W : Not used. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +arm_cmsis_nn_status arm_fully_connected_s8(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 basic fully-connected and + * matrix multiplication layer function for TF Lite + * @param[in] filter_dims dimension of filter + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_fully_connected_s8_get_buffer_size(const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic s16 Fully Connected function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] fc_params Fully Connected layer parameters. + * fc_params->input_offset : 0 + * fc_params->filter_offset : 0 + * fc_params->output_offset : 0 + * @param[in] quant_params Per-tensor quantization info. + * It contains the multiplier and shift values to be applied to the output tensor. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Input dimension is taken as Nx(H * W * C_IN) + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Two dimensional filter dimensions. Format: [N, C] + * N : accumulation depth and equals (H * W * C_IN) from input_dims + * C : output depth and equals C_OUT in output_dims + * H & W : Not used + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * N, H, W : Not used + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, C_OUT] + * N : Batches + * C_OUT : Output depth + * H & W : Not used. + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q15 is used as data type eventhough it is s16 data. It is done so to be consistent with existing APIs. + */ +arm_cmsis_nn_status arm_fully_connected_s16(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for S16 basic fully-connected and + * matrix multiplication layer function for TF Lite + * @param[in] filter_dims dimension of filter + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_fully_connected_s16_get_buffer_size(const cmsis_nn_dims *filter_dims); + +/** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ + +arm_cmsis_nn_status arm_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ + +arm_cmsis_nn_status arm_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ + +arm_cmsis_nn_status arm_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ + +arm_cmsis_nn_status arm_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ + +arm_cmsis_nn_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Matrix-Multiplication Kernels for Convolution + * + * These functions are used within convolution layer functions for + * matrix multiplication. + * + * The implementation is similar to CMSIS-DSP arm_mat_mult functions + * with one Q7 and one Q15 operands. The Q15 operand is the im2col + * output which is always with 2 columns. + * + */ + +/** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut); + +#ifdef __cplusplus +} +#endif + +/* + * Other functions + * These layers are typically not timing critical + * Basic implementation is supported here + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup BasicMath Basic math functions + * + * Elementwise add and multiplication functions. + * + */ + +/** + * @brief s8 elementwise add of two vectors + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: -127 to 128 + * @param[in] input_1_mult multiplier for input 1 + * @param[in] input_1_shift shift for input 1 + * @param[in] input_2_offset offset for input 2. Range: -127 to 128 + * @param[in] input_2_mult multiplier for input 2 + * @param[in] input_2_shift shift for input 2 + * @param[in] left_shift input left shift + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Range: -128 to 127 + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -128 + * @param[in] out_activation_max maximum value to clamp output to. Max: 127 + * @param[in] block_size number of samples + * @return The function returns ARM_CMSIS_NN_SUCCESS + */ +arm_cmsis_nn_status arm_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s16 elementwise add of two vectors + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Not used. + * @param[in] input_1_mult multiplier for input 1 + * @param[in] input_1_shift shift for input 1 + * @param[in] input_2_offset offset for input 2. Not used. + * @param[in] input_2_mult multiplier for input 2 + * @param[in] input_2_shift shift for input 2 + * @param[in] left_shift input left shift + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Not used. + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -32768 + * @param[in] out_activation_max maximum value to clamp output to. Max: 32767 + * @param[in] block_size number of samples + * @return The function returns ARM_CMSIS_NN_SUCCESS + */ +arm_cmsis_nn_status arm_elementwise_add_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s8 elementwise multiplication + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: -127 to 128 + * @param[in] input_2_offset offset for input 2. Range: -127 to 128 + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Range: -128 to 127 + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -128 + * @param[in] out_activation_max maximum value to clamp output to. Max: 127 + * @param[in] block_size number of samples + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details Supported framework: TensorFlow Lite micro + */ +arm_cmsis_nn_status arm_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s16 elementwise multiplication + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Not used. + * @param[in] input_2_offset offset for input 2. Not used. + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Not used. + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -32768 + * @param[in] out_activation_max maximum value to clamp output to. Max: 32767 + * @param[in] block_size number of samples + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details Supported framework: TensorFlow Lite micro + */ +arm_cmsis_nn_status arm_elementwise_mul_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @defgroup Acti Activation Functions + * + * Perform activation layers, including ReLU (Rectified Linear Unit), + * sigmoid and tanh + * + */ + +/** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + */ + +void arm_relu_q7(q7_t *data, uint16_t size); + +/** + * @brief s8 ReLU6 function + * @param[in,out] data pointer to input + * @param[in] size number of elements + */ + +void arm_relu6_s8(q7_t *data, uint16_t size); + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + */ + +void arm_relu_q15(q15_t *data, uint16_t size); + +/** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + */ + +void arm_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type); + +/** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type); + +/** + * @defgroup Pooling Pooling Functions + * + * Perform pooling functions, including max pooling and average pooling + * + */ + +/** + * @brief Q7 max pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * + */ + +void arm_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief Q7 average pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * + */ + +void arm_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief s8 average pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_cmsis_nn_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 average pooling function + * @param[in] dim_dst_width output tensor dimension + * @param[in] ch_src number of input tensor channels + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_avgpool_s8_get_buffer_size(const int dim_dst_width, const int ch_src); + +/** + * @brief s16 average pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns + * ARM_CMSIS_NN_SUCCESS - Successful operation + * ARM_CMSIS_NN_ARG_ERROR - In case of invalid arguments + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_cmsis_nn_status arm_avgpool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *output_data); + +/** + * @brief Get the required buffer size for S16 average pooling function + * @param[in] dim_dst_width output tensor dimension + * @param[in] ch_src number of input tensor channels + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_avgpool_s16_get_buffer_size(const int dim_dst_width, const int ch_src); + +/** + * @brief s8 max pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. The input tensor must not + * overlap with the output tensor. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_cmsis_nn_status arm_max_pool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief s16 max pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] src Input (activation) data pointer. The input tensor must not + * overlap with the output tensor. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] dst Output data pointer. Data type: int16 + * @return The function returns + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_cmsis_nn_status arm_max_pool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *dst); + +/** + * @defgroup Softmax Softmax Functions + * + * EXP(2) based softmax functions. + * + */ + +/** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out); + +/** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out); +/** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out); + +/** + * @brief S8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output); + +/** + * @brief S8 to s16 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_softmax_s8_s16(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int16_t *output); + +/** + * @brief S16 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] softmax_params Softmax s16 layer parameters with two pointers to LUTs speficied below. + * For indexing the high 9 bits are used and 7 remaining for interpolation. + * That means 512 entries for the 9-bit indexing and 1 extra for interpolation, i.e. 513 + * values for each LUT. + * - Lookup table for exp(x), where x uniform distributed between [-10.0 , 0.0] + * - Lookup table for 1 / (1 + x), where x uniform distributed between [0.0 , 1.0] + * @param[out] output Pointer to the output tensor + * @return The function returns + * ARM_CMSIS_NN_ARG_ERROR Argument error check failed + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +arm_cmsis_nn_status arm_softmax_s16(const int16_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const cmsis_nn_softmax_lut_s16 *softmax_params, + int16_t *output); + +/** + * @brief U8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ + +void arm_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output); + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * Unless specified otherwise, arguments are mandatory. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x stride along the width + * @param[in] stride_y stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns the following + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + */ +arm_cmsis_nn_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult); + +/** + * @defgroup Reshape Reshape Functions + * + */ + +/** + * @brief Reshape a s8 vector into another with different shape + * @param[in] input points to the s8 input vector + * @param[out] output points to the s8 output vector + * @param[in] total_size total size of the input and output vectors in bytes + * + * @note The output is expected to be in a memory area that does not overlap with the input's + * + */ +void arm_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size); + +/** + * @defgroup Concatenation Concatenation Functions + * + */ + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the X axis + * This function should be called for each input tensor to concatenate. The argument offset_x + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_x = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_x(&input[i], ..., &output, ..., ..., offset_x) + * offset_x += input_x[i] + * } + * + * This function assumes that the output tensor has: + * -# The same height of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with the output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_x * input_y * input_z * input_w) + offset_x + * bytes. + * @param[in] output_x Width of output tensor + * @param[in] offset_x The offset (in number of elements) on the X axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_x is less than output_x + * + */ +void arm_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Y axis + * This function should be called for each input tensor to concatenate. The argument offset_y + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_y = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_y(&input[i], ..., &output, ..., ..., offset_y) + * offset_y += input_y[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with the output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_z * input_w * input_x * input_y) + offset_y + * bytes. + * @param[in] output_y Height of output tensor + * @param[in] offset_y The offset on the Y axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_y is less than output_y + * + */ +void arm_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Z axis + * This function should be called for each input tensor to concatenate. The argument offset_z + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_z = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_z(&input[i], ..., &output, ..., ..., offset_z) + * offset_z += input_z[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_x * input_y * input_z * input_w) + offset_z + * bytes. + * @param[in] output_z Channels in output tensor + * @param[in] offset_z The offset on the Z axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_z is less than output_z + * + */ +void arm_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the W axis (Batch size) + * This function should be called for each input tensor to concatenate. The argument offset_w + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_w = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_w(&input[i], ..., &output, ..., ..., offset_w) + * offset_w += input_w[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same number o channels of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * input_x * input_y * input_z * input_w + * bytes. + * @param[in] offset_w The offset on the W axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + */ +void arm_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w); +/** + * @defgroup SVDF SVDF Layer Functions + * + */ + +/** + * @brief s8 SVDF function with 8 bit state tensor and 8 bit time weights + * + * @param[in] input_ctx Temporary scratch buffer + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] output_ctx Temporary output scratch buffer + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] svdf_params SVDF Parameters + * Range of svdf_params->input_offset : [-128, 127] + * Range of svdf_params->output_offset : [-128, 127] + * @param[in] input_quant_params Input quantization parameters + * @param[in] output_quant_params Output quantization parameters + * @param[in] input_dims Input tensor dimensions + * @param[in] input_data Pointer to input tensor + * @param[in] state_dims State tensor dimensions + * @param[in] state_data Pointer to state tensor + * @param[in] weights_feature_dims Weights (feature) tensor dimensions + * @param[in] weights_feature_data Pointer to the weights (feature) tensor + * @param[in] weights_time_dims Weights (time) tensor dimensions + * @param[in] weights_time_data Pointer to the weights (time) tensor + * @param[in] bias_dims Bias tensor dimensions + * @param[in] bias_data Pointer to bias tensor + * @param[in] output_dims Output tensor dimensions + * @param[out] output_data Pointer to the output tensor + * + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * + */ +arm_cmsis_nn_status arm_svdf_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q7_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q7_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief s8 SVDF function with 16 bit state tensor and 16 bit time weights + * + * @param[in] input_ctx Temporary scratch buffer + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] output_ctx Temporary output scratch buffer + * The caller is expected to clear the buffer ,if applicable, for security reasons. + * @param[in] svdf_params SVDF Parameters + * Range of svdf_params->input_offset : [-128, 127] + * Range of svdf_params->output_offset : [-128, 127] + * @param[in] input_quant_params Input quantization parameters + * @param[in] output_quant_params Output quantization parameters + * @param[in] input_dims Input tensor dimensions + * @param[in] input_data Pointer to input tensor + * @param[in] state_dims State tensor dimensions + * @param[in] state_data Pointer to state tensor + * @param[in] weights_feature_dims Weights (feature) tensor dimensions + * @param[in] weights_feature_data Pointer to the weights (feature) tensor + * @param[in] weights_time_dims Weights (time) tensor dimensions + * @param[in] weights_time_data Pointer to the weights (time) tensor + * @param[in] bias_dims Bias tensor dimensions + * @param[in] bias_data Pointer to bias tensor + * @param[in] output_dims Output tensor dimensions + * @param[out] output_data Pointer to the output tensor + * + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * + */ +arm_cmsis_nn_status arm_svdf_state_s16_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q15_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h new file mode 100644 index 0000000..232aa61 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h @@ -0,0 +1,1270 @@ +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnsupportfunctions.h + * Description: Public header file of support functions for CMSIS NN Library + * + * $Date: 8 August 2022 + * $Revision: V.10.0.0 + * + * Target Processor: Cortex-M CPUs + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NNSUPPORTFUNCTIONS_H_ +#define _ARM_NNSUPPORTFUNCTIONS_H_ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_math_types.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/none.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEFT_SHIFT(_shift) (_shift > 0 ? _shift : 0) +#define RIGHT_SHIFT(_shift) (_shift > 0 ? 0 : -_shift) +#define MASK_IF_ZERO(x) (x) == 0 ? ~0 : 0 +#define MASK_IF_NON_ZERO(x) (x) != 0 ? ~0 : 0 +#define SELECT_USING_MASK(mask, a, b) ((mask) & (a)) ^ (~(mask) & (b)) + +#define MAX(A, B) ((A) > (B) ? (A) : (B)) +#define MIN(A, B) ((A) < (B) ? (A) : (B)) +#define CLAMP(x, h, l) MAX(MIN((x), (h)), (l)) +#define REDUCE_MULTIPLIER(_mult) ((_mult < 0x7FFF0000) ? ((_mult + (1 << 15)) >> 16) : 0x7FFF) + +// Number of channels processed in a block for DW Conv(MVE) +// Requirement: Greater than 0 & less than 128 +// This can be fine tuned to match number of input channels for best performance. +// A layer with lower number of channels than CH_IN_BLOCK_MVE will result in higher +// scratch buffer usage and a layer with higher number of channels than CH_IN_BLOCK_MVE +// will result in lower scratch buffer usage. +#define CH_IN_BLOCK_MVE (124) + +/** + * @brief definition to pack four 8 bit values. + */ +#define PACK_Q7x4_32x1(v0, v1, v2, v3) \ + ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) + +/** + * @brief definition to pack two 16 bit values. + */ +#define PACK_Q15x2_32x1(v0, v1) (((int32_t)v0 & (int32_t)0xFFFF) | ((int32_t)v1 << 16)) + +/** + * @brief Union for SIMD access of q31/q15/q7 types + */ +union arm_nnword +{ + q31_t word; + /**< q31 type */ + q15_t half_words[2]; + /**< q15 type */ + q7_t bytes[4]; + /**< q7 type */ +}; + +/** + * @brief Union for data type long long + */ +struct arm_nn_double +{ + uint32_t low; + int32_t high; +}; + +union arm_nn_long_long +{ + int64_t long_long; + struct arm_nn_double word; +}; + +/** + * @defgroup nndata_convert Neural Network Data Conversion Functions + * + * Perform data type conversion in-between neural network operations + * + */ + +/** + * @brief Converts the elements of the q7 vector to q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * + */ +void arm_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Non-saturating addition of elements of a q7 vector + * @param[in] *input Pointer to the q7 input vector + * @param[out] *output Pointer to the q31 output variable. + * @param[in] block_size length of the input vector + * \par Description: + * + * 2^24 samples can be added without saturating the result. + * + * The equation used for the conversion process is: + * + * 
+ *  sum = input[0] + input[1] + .. + input[block_size -1]
+ *
+ * + * */ +void arm_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * + */ +void arm_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements from a q7 vector to a q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset q7 offset to be added to each input vector element. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ *  dst[n] = (q15_t) src[n] + offset;   0 <= n < block_size.
+ *
+ * + */ +void arm_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset offset to be added to each input vector element. + * + * @details This function does the q7 to q15 expansion with re-ordering of bytes. Re-ordering is a consequence of + * the sign extension intrinsic(DSP extension). The tail (i.e., last (N % 4) elements) retains its + * original order. + * + */ +void arm_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements from a q7 vector and accumulate to a q15 vector + * @param[in] *src points to the q7 input vector + * @param[out] *dst points to the q15 output vector + * @param[in] block_size length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ *  dst[n] += (q15_t) src[n] ;   0 <= n < block_size.
+ *
+ * + */ +void arm_nn_accumulate_q7_to_q15(q15_t *dst, const q7_t *src, uint32_t block_size); + +/** + * @brief Depthwise conv on an im2col buffer where the input channel equals output channel. + * @param[in] row pointer to row + * @param[in] col pointer to im2col buffer, always consists of 2 columns. + * @param[in] num_ch number of channels + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] kernel_size number of elements in one column. + * @param[in] output_bias per output channel bias. Range : int32 + * @param[out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite micro. + */ +q7_t *arm_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * @param[in] input_row pointer to row operand + * @param[in] input_col pointer to col operand + * @param[in] output_ch number of rows of input_row + * @param[in] col_batches number of column batches. Range: 1 to 4 + * @param[in] output_shift pointer to per output channel requantization shift parameter. + * @param[in] output_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] col_offset input tensor(col) offset. + * @param[in] row_offset kernel offset(row). Not used. + * @param[in] out_activation_min minimum value to clamp the output to. Range : int8 + * @param[in] out_activation_max maximum value to clamp the output to. Range : int8 + * @param[in] row_len number of elements in each row + * @param[in] bias per output channel bias. Range : int32 + * @param[in,out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite + */ +q7_t *arm_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t out_activation_min, + const int16_t out_activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out); +/** + * @brief Matrix-multiplication function for convolution with per-channel requantization for 16 bits convolution. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] activation_min minimum value to clamp the output to. Range : int16 + * @param[in] activation_max maximum value to clamp the output to. Range : int16 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int64 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ +q15_t *arm_nn_mat_mult_kernel_s16(const q7_t *input_a, + const q15_t *input_b, + const int32_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int16_t activation_min, + const int16_t activation_max, + const int32_t num_col_a, + const int64_t *const output_bias, + q15_t *out_0); + +/** + * @brief General Vector by Matrix multiplication with requantization and storage of result. + * @param[in] row_elements number of row elements + * @param[in] skipped_row_elements number of row elements skipped due to padding. + * row_elements + skipped_row_elements = (kernel_x * kernel_y) * input_ch + * @param[in] row_base_ref pointer to row operand + * @param[in] col_base_ref pointer to col operand + * @param[out] out_ch Number of output channels + * @param[in] conv_params Pointer to convolution parameters like offsets and activation values + * @param[in] quant_params Pointer to per-channel quantization parameters + * @param[in] bias Pointer to optional per-channel bias + * @param[out] output Pointer to output where int8 results are stored. + * @return The function performs matrix(row_base_ref) multiplication with vector(col_base_ref) and + * scaled result is stored in memory. + * + * @details Pseudo-code + * *output = 0 + * sum_col = 0 + * for (j = 0; j < out_ch; j++) + * for (i = 0; i < row_elements; i++) + * *output += row_base_ref[i] * col_base_ref[i] + * sum_col += col_base_ref[i] + * scale sum_col using quant_params and bias + * store result in 'output' + * + * + */ +arm_cmsis_nn_status arm_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int32_t skipped_row_elements, + const int8_t *row_base_ref, + const int8_t *col_base_ref, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output); + +/** + * @brief Matrix-multiplication with requantization & activation function for four rows and one column + * @param[in] row_elements number of row elements + * @param[in] offset offset between rows. Can be the same as row_elements. + * For e.g, in a 1x1 conv scenario with stride as 1. + * @param[in] row_base pointer to row operand + * @param[in] col_base pointer to col operand + * @param[in] out_ch Number of output channels + * @param[in] conv_params Pointer to convolution parameters like offsets and activation values + * @param[in] quant_params Pointer to per-channel quantization parameters + * @param[in] bias Pointer to per-channel bias + * @param[out] output Pointer to output where int8 results are stored. + * + * @return The function returns the updated output pointer or NULL if implementation is not available. + * + * @details Compliant to TFLM int8 specification. MVE implementation only + */ +int8_t *arm_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * This function assumes: + * - LHS input matrix NOT transposed (nt) + * - RHS input matrix transposed (t) + * + * @note This operation also performs the broadcast bias addition before the requantization + * + * @param[in] lhs Pointer to the LHS input matrix + * @param[in] rhs Pointer to the RHS input matrix + * @param[in] bias Pointer to the bias vector. The length of this vector is equal to the number of + * output columns (or RHS input rows) + * @param[out] dst Pointer to the output matrix with "m" rows and "n" columns + * @param[in] dst_multipliers Pointer to the multipliers vector needed for the per-channel requantization. + * The length of this vector is equal to the number of output columns (or RHS input + * rows) + * @param[in] dst_shifts Pointer to the shifts vector needed for the per-channel requantization. The length + * of this vector is equal to the number of output columns (or RHS input rows) + * @param[in] lhs_rows Number of LHS input rows + * @param[in] rhs_rows Number of RHS input rows + * @param[in] rhs_cols Number of LHS/RHS input columns + * @param[in] lhs_offset Offset to be applied to the LHS input value + * @param[in] dst_offset Offset to be applied the output result + * @param[in] activation_min Minimum value to clamp down the output. Range : int8 + * @param[in] activation_max Maximum value to clamp up the output. Range : int8 + * + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ +arm_cmsis_nn_status arm_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] bias Input bias + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side vector. + * Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] dst_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] address_offset Memory position offset for dst. First output is stored at 'dst', the + * second at 'dst + address_offset' and so on. Default value is typically 1. + * + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ +arm_cmsis_nn_status arm_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max, + const int32_t address_offset); + +/** + * @brief s16 Vector by Matrix (transposed) multiplication + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] bias Input bias + * @param[out] dst Output vector + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int16 + * @param[in] activation_max Maximum value to clamp the output to. Range: int16 + * + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ +arm_cmsis_nn_status arm_nn_vec_mat_mult_t_s16(const q15_t *lhs, + const q7_t *rhs, + const q63_t *bias, + q15_t *dst, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication with s16 output + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side + * vector. Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] scatter_offset Address offset for dst. First output is stored at 'dst', the + * second at 'dst + scatter_offset' and so on. + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int16 + * @param[in] activation_max Maximum value to clamp the output to. Range: int16 + * + * @return The function returns ARM_CMSIS_NN_SUCCESS + * + */ +arm_cmsis_nn_status arm_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t scatter_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in padded cases where + * the padding is -lhs_offset(Range: int8). Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] active_ch Subset of total_ch processed + * @param[in] total_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +arm_cmsis_nn_status arm_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const int32_t active_ch, + const int32_t total_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in non-padded cases. + * Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] active_ch Subset of total_ch processed + * @param[in] total_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels. + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels. + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels. + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +arm_cmsis_nn_status arm_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const int32_t active_ch, + const int32_t total_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in non-padded cases. + * Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] num_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels. + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels. + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels. + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +int16_t *arm_nn_depthwise_conv_nt_t_s16(const int16_t *lhs, + const q7_t *rhs, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int64_t *const output_bias, + int16_t *out); + +/** + *@brief Matrix-multiplication function for convolution with reordered columns + *@param[in] pA pointer to operand A + *@param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + *@param[in] ch_im_out numRow of A + *@param[in] numCol_A numCol of A + *@param[in] bias_shift amount of left-shift for bias + *@param[in] out_shift amount of right-shift for output + *@param[in] bias the bias + *@param[in,out] pOut pointer to output + *@return The function returns the incremented output pointer + * + *@details This function assumes that data in pInBuffer are reordered + */ +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut); + +/** + @brief Read 2 q15 elements and post increment pointer. + @param[in] in_q15 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q15x2_ia(const q15_t **in_q15) +{ + q31_t val; + + memcpy(&val, *in_q15, 4); + *in_q15 += 2; + + return (val); +} + +/** + @brief Read 4 q7 from q7 pointer and post increment pointer. + @param[in] in_q7 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q7x4_ia(const q7_t **in_q7) +{ + q31_t val; + memcpy(&val, *in_q7, 4); + *in_q7 += 4; + + return (val); +} + +/** + @brief Read 2 q15 from q15 pointer. + @param[in] in_q15 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q15x2(const q15_t *in_q15) +{ + q31_t val; + memcpy(&val, in_q15, 4); + + return (val); +} + +/** + @brief Read 4 q7 values. + @param[in] in_q7 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q7x4(const q7_t *in_q7) +{ + q31_t val; + memcpy(&val, in_q7, 4); + + return (val); +} + +/** + @brief Write four q7 to q7 pointer and increment pointer afterwards. + @param[in] in Double pointer to input value + @param[in] value Four bytes to copy + */ +__STATIC_FORCEINLINE void arm_nn_write_q7x4_ia(q7_t **in, q31_t value) +{ + memcpy(*in, &value, 4); + *in += 4; +} + +/** + * @brief memset optimized for MVE + * @param[in, out] dst Destination pointer + * @param[in] val Value to set + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void arm_memset_q7(q7_t *dst, const q7_t val, uint32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + __asm volatile(" vdup.8 q0, %[set_val] \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vstrb.8 q0, [%[in]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [in] "+r"(dst) + : [cnt] "r"(block_size), [set_val] "r"(val) + : "q0", "memory", "r14"); +#else + memset(dst, val, block_size); +#endif +} + +#if defined(ARM_MATH_DSP) + +/** + * @brief read and expand one q7 word into two q15 words + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); + q31_t inAbuf1 = __SXTB16_RORn((uint32_t)inA, 8); + q31_t inAbuf2 = __SXTB16(inA); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = (int32_t)(__PKHTB(inAbuf1, inAbuf2, 16)); + *out1 = (int32_t)(__PKHBT(inAbuf2, inAbuf1, 16)); +#else + *out1 = (int32_t)(__PKHTB(inAbuf1, inAbuf2, 16)); + *out2 = (int32_t)(__PKHBT(inAbuf2, inAbuf1, 16)); +#endif + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad_reordered(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out2 = __SXTB16(inA); +#endif + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering and add an offset + */ +__STATIC_FORCEINLINE const q7_t * +read_and_pad_reordered_with_offset(const q7_t *source, q31_t *out1, q31_t *out2, q31_t offset) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out2 = __SXTB16(inA); +#endif + *out1 = __QADD16(*out1, offset); + *out2 = __QADD16(*out2, offset); + + return source; +} + +#endif + +/** + * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation + * + * Basic Math Functions for Neural Network Computation + * + */ + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief Matrix-multiplication function for convolution with per-channel requantization. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int32 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ +q7_t *arm_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0); + +/** + * @brief Common softmax function for s8 input and s8 or s16 output + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[in] int16_output Indicating s8 output if 0 else s16 output + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_nn_softmax_common_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + const bool int16_output, + void *output); + +/** + * @brief macro for adding rounding offset + */ +#ifndef ARM_NN_TRUNCATE +#define NN_ROUND(out_shift) ((0x1 << out_shift) >> 1) +#else +#define NN_ROUND(out_shift) 0 +#endif + +// Macros for shortening quantization functions' names and avoid long lines +#define MUL_SAT(a, b) arm_nn_doubling_high_mult((a), (b)) +#define MUL_SAT_MVE(a, b) arm_doubling_high_mult_mve_32x4((a), (b)) +#define MUL_POW2(a, b) arm_nn_mult_by_power_of_two((a), (b)) + +#define DIV_POW2(a, b) arm_nn_divide_by_power_of_two((a), (b)) +#define DIV_POW2_MVE(a, b) arm_divide_by_power_of_two_mve((a), (b)) + +#define EXP_ON_NEG(x) arm_nn_exp_on_negative_values((x)) +#define ONE_OVER1(x) arm_nn_one_over_one_plus_x_for_x_in_0_1((x)) + +// Patched by Edge Impulse, make CMSIS-NN models compile under x86 +#if __GNUC_PYTHON__ == 1 +#undef __RESTRICT +#define __RESTRICT +#endif // __GNUC_PYTHON__ == 1 + +/** + * @brief Saturating doubling high multiply. Result matches + * NEON instruction VQRDMULH. + * @param[in] m1 Multiplicand. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @param[in] m2 Multiplier. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_doubling_high_mult(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + // Rounding offset to add for a right shift of 31 + q63_t mult = 1 << 30; + + if ((m1 < 0) ^ (m2 < 0)) + { + mult = 1 - mult; + } + // Gets resolved as a SMLAL instruction + mult = mult + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult / (1ll << 31)); + + if ((m1 == m2) && (m1 == (int32_t)NN_Q31_MIN)) + { + result = NN_Q31_MAX; + } + return result; +} + +/** + * @brief Doubling high multiply without saturation. This is intended + * for requantization where the scale is a positive integer + * + * @param[in] m1 Multiplicand. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @param[in] m2 Multiplier Range: {NN_Q31_MIN, NN_Q31_MAX} + * @return Result of multiplication. + * @note The result of this matches that of neon instruction + * VQRDMULH for m1 in range {NN_Q31_MIN, NN_Q31_MAX} and m2 in + * range {NN_Q31_MIN + 1, NN_Q31_MAX}. Saturation occurs when + * m1 equals m2 equals NN_Q31_MIN and that is not handled by + * this function. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_doubling_high_mult_no_sat(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + union arm_nn_long_long mult; + + // Rounding offset to add for a right shift of 31 + mult.word.low = 1 << 30; + mult.word.high = 0; + + // Gets resolved as a SMLAL instruction + mult.long_long = mult.long_long + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult.long_long >> 31); + + return result; +} + +/** + * @brief Rounding divide by power of two. + * @param[in] dividend - Dividend + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_divide_by_power_of_two(const q31_t dividend, const q31_t exponent) +{ + q31_t result = 0; + const q31_t remainder_mask = (1 << exponent) - 1; + int32_t remainder = remainder_mask & dividend; + + // Basic division + result = dividend >> exponent; + + // Adjust 'result' for rounding (mid point away from zero) + q31_t threshold = remainder_mask >> 1; + if (result < 0) + { + threshold++; + } + if (remainder > threshold) + { + result++; + } + + return result; +} + +/** + * @brief Requantize a given value. + * @param[in] val Value to be requantized + * @param[in] multiplier multiplier. Range {NN_Q31_MIN + 1, Q32_MAX} + * @param[in] shift left or right shift for 'val * multiplier' + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_requantize(const q31_t val, const q31_t multiplier, const q31_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int64_t total_shift = 31 - shift; + const int64_t new_val = val * (int64_t)multiplier; + + int32_t result = new_val >> (total_shift - 1); + result = (result + 1) >> 1; + + return result; +#else + return arm_nn_divide_by_power_of_two(arm_nn_doubling_high_mult_no_sat(val * (1 << LEFT_SHIFT(shift)), multiplier), + RIGHT_SHIFT(shift)); +#endif +} + +/** + * @brief Requantize a given 64 bit value. + * @param[in] val Value to be requantized in the range {-(1<<47)} to {(1<<47) - 1} + * @param[in] reduced_multiplier Reduced multiplier in the range {NN_Q31_MIN + 1, Q32_MAX} to {Q16_MIN + 1, + * Q16_MAX} + * @param[in] shift Left or right shift for 'val * multiplier' in the range {-31} to {7} + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_requantize_s64(const q63_t val, const q31_t reduced_multiplier, const q31_t shift) +{ + const q63_t new_val = val * reduced_multiplier; + + q31_t result = new_val >> (14 - shift); // 64->32 bit reduction + result = (result + 1) >> 1; // Last shift position and insert round + + return result; +} + +/** + * @brief memcpy optimized for MVE + * @param[in, out] dst Destination pointer + * @param[in] src Source pointer. + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void arm_memcpy_q7(q7_t *__RESTRICT dst, const q7_t *__RESTRICT src, uint32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + __asm volatile(" wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vldrb.8 q0, [%[in]], #16 \n" + " vstrb.8 q0, [%[out]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [in] "+r"(src), [out] "+r"(dst) + : [cnt] "r"(block_size) + : "q0", "memory", "r14"); +#else + memcpy(dst, src, block_size); +#endif +} + +/** + * @brief memcpy wrapper for int16 + * @param[in, out] dst Destination pointer + * @param[in] src Source pointer. + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void arm_memcpy_q15(q15_t *__RESTRICT dst, const q15_t *__RESTRICT src, uint32_t block_size) +{ + memcpy(dst, src, block_size); +} + +#if defined(ARM_MATH_MVEI) +/** + * @brief Vector saturating doubling high multiply returning high half. + * @param[in] m1 Multiplicand + * @param[in] m2 Multiplier + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE int32x4_t arm_doubling_high_mult_mve(const int32x4_t m1, const q31_t m2) +{ + return vqrdmulhq_n_s32(m1, m2); +} + +/** + * @brief Vector rounding divide by power of two. + * @param[in] dividend - Dividend vector + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE int32x4_t arm_divide_by_power_of_two_mve(const int32x4_t dividend, const q31_t exponent) +{ + const int32x4_t shift = vdupq_n_s32(-exponent); + const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); + const int32x4_t fixed_up_dividend = vqaddq_s32(dividend, fixup); + return vrshlq_s32(fixed_up_dividend, shift); +} + +/** + * @brief Requantize a given vector. + * @param[in] val Vector to be requantized + * @param[in] multiplier multiplier + * @param[in] shift shift + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE int32x4_t arm_requantize_mve(const int32x4_t val, const q31_t multiplier, const q31_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int right_shift = MIN(-1, shift); + const int left_shift = shift - right_shift; + + const int32x4_t left_shift_dup = vdupq_n_s32(left_shift); + const int32x4_t right_shift_dup = vdupq_n_s32(right_shift); + + int32x4_t result = vqdmulhq_n_s32(vshlq_s32(val, left_shift_dup), multiplier); + result = vrshlq_s32(result, right_shift_dup); + + return result; +#else + return arm_divide_by_power_of_two_mve( + arm_doubling_high_mult_mve(vshlq_s32(val, vdupq_n_s32(LEFT_SHIFT(shift))), multiplier), RIGHT_SHIFT(shift)); +#endif +} + +__STATIC_FORCEINLINE int32x4_t arm_doubling_high_mult_mve_32x4(const int32x4_t m1, const int32x4_t m2) +{ + return vqrdmulhq_s32(m1, m2); +} + +__STATIC_FORCEINLINE int32x4_t arm_divide_by_power_of_two_mve_32x4(const int32x4_t dividend, const int32x4_t exponent) +{ + const int32x4_t shift = -exponent; + const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); + const int32x4_t fixed_up_dividend = vqaddq_s32(dividend, fixup); + return vrshlq_s32(fixed_up_dividend, shift); +} + +__STATIC_FORCEINLINE int32x4_t arm_requantize_mve_32x4(const int32x4_t val, + const int32x4_t multiplier, + const int32x4_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int32x4_t right_shift = vminq_s32(vdupq_n_s32(-1), shift); + const int32x4_t left_shift = vqsubq_s32(shift, right_shift); + + int32x4_t result = vqdmulhq_s32(vshlq_s32(val, left_shift), multiplier); + result = vrshlq_s32(result, right_shift); + + return result; +#else + const int32x4_t zz = vdupq_n_s32(0); + const mve_pred16_t p = vcmpgtq_n_s32(shift, 0); + + const int32x4_t left_shift = vpselq_s32(shift, zz, p); + const int32x4_t right_shift = -vpselq_s32(zz, shift, p); + + return arm_divide_by_power_of_two_mve_32x4(arm_doubling_high_mult_mve_32x4(vshlq_s32(val, left_shift), multiplier), + right_shift); +#endif +} +#endif + +// @note The following functions are used only for softmax layer, scaled bits = 5 assumed + +__STATIC_FORCEINLINE int32_t arm_nn_exp_on_negative_values(int32_t val) +{ + int32_t mask = 0; + int32_t shift = 24; + + const int32_t val_mod_minus_quarter = (val & ((1 << shift) - 1)) - (1 << shift); + const int32_t remainder = val_mod_minus_quarter - val; + const int32_t x = (val_mod_minus_quarter << 5) + (1 << 28); + const int32_t x2 = MUL_SAT(x, x); + + int32_t result = 1895147668 + + MUL_SAT(1895147668, x + DIV_POW2(MUL_SAT(DIV_POW2(MUL_SAT(x2, x2), 2) + MUL_SAT(x2, x), 715827883) + x2, 1)); + +#define SELECT_IF_NON_ZERO(x) \ + { \ + mask = MASK_IF_NON_ZERO(remainder & (1 << shift++)); \ + result = SELECT_USING_MASK(mask, MUL_SAT(result, x), result); \ + } + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mask = MASK_IF_ZERO(val); + return SELECT_USING_MASK(mask, NN_Q31_MAX, result); +} + +__STATIC_FORCEINLINE q31_t arm_nn_mult_by_power_of_two(const int32_t val, const int32_t exp) +{ + const int32_t thresh = ((1 << (31 - exp)) - 1); + int32_t result = val << exp; + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val > thresh), NN_Q31_MAX, result); + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val < -thresh), NN_Q31_MIN, result); + return result; +} + +__STATIC_FORCEINLINE int32_t arm_nn_one_over_one_plus_x_for_x_in_0_1(int32_t val) +{ + const int64_t sum = (int64_t)val + (int64_t)NN_Q31_MAX; + const int32_t half_denominator = (int32_t)((sum + (sum >= 0 ? 1 : -1)) / 2L); + int32_t x = 1515870810 + MUL_SAT(half_denominator, -1010580540); + + const int32_t shift = (1 << 29); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + + return MUL_POW2(x, 1); +} + +/** + @brief Write 2 q15 elements and post increment pointer. + @param[in] dest_q15 Pointer to pointer that holds address of destination. + @param[in] src_q31 Input value to be written. + */ +__STATIC_FORCEINLINE void arm_nn_write_q15x2_ia(q15_t **dest_q15, q31_t src_q31) +{ + q31_t val = src_q31; + + memcpy(*dest_q15, &val, 4); + *dest_q15 += 2; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c new file mode 100644 index 0000000..5872806 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c @@ -0,0 +1,100 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_tables.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief neural network activation function using direct table look-up + * + * @note Refer header file for details. + * + */ + +void arm_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t)in & bit_mask; + q15_t value = lookup_table[(uint8_t)(in >> shift_size)]; + if ((in >> shift_size) != 0x7f) + { + q15_t value2 = lookup_table[(uint8_t)(1 + ((uint8_t)(in >> shift_size)))]; + /* doing the interpolation here for better accuracy */ + out = ((q31_t)(full_frac - frac) * value + (q31_t)value2 * frac) >> shift_size; + } + else + { + /* the largest positive value does not have a right side for linear interpolation */ + out = value; + } + + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c new file mode 100644 index 0000000..874f766 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c @@ -0,0 +1,84 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2020, 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_tables.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/* + * Q7 neural network activation function using direct table look-up + * + * Refer header file for details. + * + */ + +void arm_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t)(in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c new file mode 100644 index 0000000..e9ee83a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c @@ -0,0 +1,69 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu6_s8.c + * Description: Basic s8 version of ReLU6 + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/* + * Basic ReLU6 function + * + * Refer to header file for details. + * + */ + +void arm_relu6_s8(q7_t *data, uint16_t size) +{ + int32_t i; + + for (i = 0; i < size; i++) + { + int32_t ip = data[i]; + + ip = MAX(ip, 0); + data[i] = MIN(ip, 6); + } +} + +/** + * @} end of Acti group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c new file mode 100644 index 0000000..93ff722 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c @@ -0,0 +1,104 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/* + * Q15 ReLu function + * + * Refer header file for details. + * + */ + +void arm_relu_q15(q15_t *data, uint16_t size) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for M cores with DSP extension */ + + uint16_t i = size >> 1; + q15_t *input = data; + q15_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = arm_nn_read_q15x2_ia((const q15_t **)&input); + + /* extract the first bit */ + buf = __ROR(in & 0x80008000, 15); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB16(0x00000000, buf); + + arm_nn_write_q15x2_ia(&output, in & (~mask)); + i--; + } + + if (size & 0x1) + { + if (*input < 0) + { + *input = 0; + } + input++; + } +#else + /* Run the following code as reference implementation for M cores without DSP extension */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @} end of Acti group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c new file mode 100644 index 0000000..029b39a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c @@ -0,0 +1,109 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: 4 Aug 2022 + * $Revision: V.1.1.4 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/* + * Q7 ReLu function + * + * Refer header file for details. + * + */ + +void arm_relu_q7(q7_t *data, uint16_t size) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for M cores with DSP extension */ + + uint16_t i = size >> 2; + q7_t *input = data; + q7_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = arm_nn_read_q7x4_ia((const q7_t **)&input); + + /* extract the first bit */ + buf = (int32_t)__ROR((uint32_t)in & 0x80808080, 7); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB8(0x00000000, buf); + + arm_nn_write_q7x4_ia(&output, in & (~mask)); + + i--; + } + + i = size & 0x3; + while (i) + { + if (*input < 0) + { + *input = 0; + } + input++; + i--; + } + +#else + /* Run the following code as reference implementation for cores without DSP extension */ + + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif +} + +/** + * @} end of Acti group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c new file mode 100644 index 0000000..7fbb104 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c @@ -0,0 +1,140 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_add_s16 + * Description: Elementwise add + * + * $Date: 10 May 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s16 elementwise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + +arm_cmsis_nn_status arm_elementwise_add_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + (void)input_1_offset; + (void)input_2_offset; + (void)out_offset; + int32_t input_1; + int32_t input_2; + int32_t sum; + int32_t two_halfword_1, two_halfword_2; + int16_t sum_1, sum_2; + int32_t loop_count = block_size / 2; + + while (loop_count > 0) + { + two_halfword_1 = arm_nn_read_q15x2_ia(&input_1_vect); + two_halfword_2 = arm_nn_read_q15x2_ia(&input_2_vect); + + input_1 = (int16_t)(two_halfword_1 & 0xFFFF) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + input_2 = (int16_t)(two_halfword_2 & 0xFFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + sum_1 = (int16_t)sum; + + input_1 = (int16_t)(two_halfword_1 >> 16) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + input_2 = (int16_t)(two_halfword_2 >> 16) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + sum_2 = (int16_t)sum; + + arm_nn_write_q15x2_ia(&output, PACK_Q15x2_32x1(sum_1, sum_2)); + + loop_count--; + } + loop_count = block_size & 0x1; + + while (loop_count > 0) + { + /* C = A + B */ + input_1 = *input_1_vect++ << left_shift; + input_2 = *input_2_vect++ << left_shift; + + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (int16_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of BasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c new file mode 100644 index 0000000..9ff0311 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c @@ -0,0 +1,238 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_add_s8 + * Description: Elementwise add + * + * $Date: 19 April 2022 + * $Revision: V.3.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s8 elementwise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + +arm_cmsis_nn_status arm_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + int32_t count = block_size; + + while (count > 0) + { + int32x4_t vect_1; + int32x4_t vect_2; + + mve_pred16_t p = vctp32q((uint32_t)count); + + vect_1 = vldrbq_z_s32(input_1_vect, p); + vect_2 = vldrbq_z_s32(input_2_vect, p); + + vect_1 = vaddq_s32(vect_1, vdupq_n_s32(input_1_offset)); + vect_2 = vaddq_s32(vect_2, vdupq_n_s32(input_2_offset)); + + vect_1 = vshlq_r_s32(vect_1, left_shift); + vect_2 = vshlq_r_s32(vect_2, left_shift); + + vect_1 = arm_requantize_mve(vect_1, input_1_mult, input_1_shift); + vect_2 = arm_requantize_mve(vect_2, input_2_mult, input_2_shift); + + vect_1 = vaddq_s32(vect_1, vect_2); + vect_1 = arm_requantize_mve(vect_1, out_mult, out_shift); + + vect_1 = vaddq_n_s32(vect_1, out_offset); + + vect_1 = vmaxq_s32(vect_1, vdupq_n_s32(out_activation_min)); + vect_1 = vminq_s32(vect_1, vdupq_n_s32(out_activation_max)); + + input_1_vect += 4; + input_2_vect += 4; + vstrbq_p_s32(output, vect_1, p); + + output += 4; + count -= 4; + } +#else + int32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t sum; + +#if defined(ARM_MATH_DSP) + int32_t a_1, b_1, a_2, b_2; + + int32_t offset_1_packed, offset_2_packed; + + int8_t r1, r2, r3, r4; + + offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL); + offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL); + + loop_count = block_size >> 2; + + while (loop_count > 0) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Sum 1 */ + input_1 = (b_1 & 0x0FFFF) << left_shift; + + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = (b_2 & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r1 = (q7_t)sum; + + /* Sum 3 */ + input_1 = ((b_1 >> 16) & 0x0FFFF) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = ((b_2 >> 16) & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r3 = (q7_t)sum; + + /* Sum 2 */ + input_1 = (a_1 & 0x0FFFF) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = (a_2 & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r2 = (q7_t)sum; + + /* Sum 4 */ + input_1 = ((a_1 >> 16) & 0x0FFFF) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = ((a_2 >> 16) & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r4 = (q7_t)sum; + + arm_nn_write_q7x4_ia(&output, PACK_Q7x4_32x1(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0) + { + /* C = A + B */ + + input_1 = (*input_1_vect++ + input_1_offset) << left_shift; + input_2 = (*input_2_vect++ + input_2_offset) << left_shift; + + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (q7_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + +#endif /* ARM_MATH_MVEI */ + + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of BasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c new file mode 100644 index 0000000..5d53550 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c @@ -0,0 +1,126 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_mul_s16 + * Description: Element wise multiplication + * + * $Date: 10 May 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/** + * @brief s16 element wise multiplication of two vectors + * + * @note Refer header file for details. + * + */ +arm_cmsis_nn_status arm_elementwise_mul_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + (void)input_1_offset; + (void)input_2_offset; + (void)out_offset; + int32_t input_1; + int32_t input_2; + int32_t mul_res; + int32_t two_halfword_1, two_halfword_2; + int16_t mul_1, mul_2; + int32_t loop_count = block_size / 2; + + while (loop_count > 0) + { + two_halfword_1 = arm_nn_read_q15x2_ia(&input_1_vect); + two_halfword_2 = arm_nn_read_q15x2_ia(&input_2_vect); + + input_1 = (int16_t)(two_halfword_1 & 0xFFFF); + input_2 = (int16_t)(two_halfword_2 & 0xFFFF); + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift); + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + mul_1 = (int16_t)mul_res; + + input_1 = (int16_t)(two_halfword_1 >> 16); + input_2 = (int16_t)(two_halfword_2 >> 16); + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift); + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + mul_2 = (int16_t)mul_res; + + arm_nn_write_q15x2_ia(&output, PACK_Q15x2_32x1(mul_1, mul_2)); + + loop_count--; + } + loop_count = block_size & 0x1; + + while (loop_count > 0) + { + /* C = A * B */ + + input_1 = *input_1_vect++; + input_2 = *input_2_vect++; + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift); + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (int16_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } + + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of BasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c new file mode 100644 index 0000000..663112a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c @@ -0,0 +1,204 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_mul_s8 + * Description: Element wise multiplication + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s8 element wise multiplication of two vectors + * + * Refer header file for details. + * + */ + +arm_cmsis_nn_status arm_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + + int32_t loop_count; +#if defined(ARM_MATH_MVEI) + + loop_count = (block_size + 3) / 4; + uint32_t num_elements = block_size; + + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp32q(num_elements); + + int32x4_t input_1 = vldrbq_z_s32(input_1_vect, p); + input_1 = vaddq_n_s32(input_1, input_1_offset); + + int32x4_t input_2 = vldrbq_z_s32(input_2_vect, p); + input_2 = vaddq_n_s32(input_2, input_2_offset); + + int32x4_t res_0 = vmulq_s32(input_1, input_2); + + res_0 = arm_requantize_mve_32x4(res_0, vdupq_n_s32(out_mult), vdupq_n_s32(out_shift)); + + res_0 += vdupq_n_s32(out_offset); + + res_0 = vmaxq_s32(res_0, vdupq_n_s32(out_activation_min)); + res_0 = vminq_s32(res_0, vdupq_n_s32(out_activation_max)); + + vstrbq_p_s32(output, res_0, p); + input_1_vect += 4; + input_2_vect += 4; + output += 4; + num_elements -= 4; + } + +#else + int32_t input_1; + int32_t input_2; + int32_t mul_res; + +#if defined(ARM_MATH_DSP) + int32_t a_1, b_1, a_2, b_2; + + int32_t offset_1_packed, offset_2_packed; + + int8_t r1, r2, r3, r4; + + offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL); + offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL); + + loop_count = block_size >> 2; + + while (loop_count > 0) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Mul 1 */ + input_1 = (int16_t)(b_1 & 0x0FFFFL); + input_2 = (int16_t)(b_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r1 = (q7_t)mul_res; + + /* Mul 3 */ + input_1 = (int16_t)((b_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((b_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r3 = (q7_t)mul_res; + + /* Mul 2 */ + input_1 = (int16_t)(a_1 & 0x0FFFFL); + input_2 = (int16_t)(a_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r2 = (q7_t)mul_res; + + /* Mul 4 */ + input_1 = (int16_t)((a_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((a_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r4 = (q7_t)mul_res; + + arm_nn_write_q7x4_ia(&output, PACK_Q7x4_32x1(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0) + { + /* C = A * B */ + + input_1 = *input_1_vect++ + input_1_offset; + input_2 = *input_2_vect++ + input_2_offset; + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (q7_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } +#endif + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of BasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c new file mode 100644 index 0000000..442a497 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c @@ -0,0 +1,70 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_w.c + * Description: s8 version of concatenation along the W axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the W axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w) +{ + const uint32_t input_copy_size = input_x * input_y * input_z * input_w; + + output += offset_w * (input_x * input_y * input_z); + + arm_memcpy_q7(output, input, input_copy_size); +} + +/** + * @} end of Concatenation group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c new file mode 100644 index 0000000..bcc0d38 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_x.c + * Description: s8 version of concatenation along the X axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the X axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x) +{ + const uint32_t num_iterations = input_y * input_z * input_w; + + output += offset_x; + + uint32_t i; + + // Copy per row + for (i = 0; i < num_iterations; ++i) + { + arm_memcpy_q7(output, input, input_x); + input += input_x; + output += output_x; + } +} + +/** + * @} end of Concatenation group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c new file mode 100644 index 0000000..b0f7f43 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c @@ -0,0 +1,80 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_y.c + * Description: s8 version of concatenation along the Y axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Y axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y) +{ + const uint32_t num_iterations = input_z * input_w; + const uint32_t input_copy_size = input_x * input_y; + const uint32_t output_stride = input_x * output_y; + + output += offset_y * input_x; + uint32_t i; + + // Copy per tile + for (i = 0; i < num_iterations; ++i) + { + arm_memcpy_q7(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c new file mode 100644 index 0000000..4ba99f5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c @@ -0,0 +1,79 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_z.c + * Description: s8 version of concatenation along the Z axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Z axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z) +{ + const uint32_t input_copy_size = input_x * input_y * input_z; + const uint32_t output_stride = input_x * input_y * output_z; + + output += offset_z * (input_x * input_y); + + uint32_t i; + + for (i = 0; i < input_w; ++i) + { + arm_memcpy_q7(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c new file mode 100644 index 0000000..64a24d6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c @@ -0,0 +1,169 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1_x_n_s8.c + * Description: s8 version of 1xN convolution using symmetric quantization. + * + * $Date: 20 June 2022 + * $Revision: V.3.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * 1xN s8 convolution function. + * + * Refer header file for details. + * + */ + +arm_cmsis_nn_status arm_convolve_1_x_n_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + arm_cmsis_nn_status status = ARM_CMSIS_NN_SUCCESS; + /* The wrapper API is the ultimate reference for argument check */ + if ((input_dims->h != 1) || (output_dims->w % 4 != 0) || conv_params->dilation.w != 1) + { + status = ARM_CMSIS_NN_ARG_ERROR; + goto out; + } + +#if defined(ARM_MATH_MVEI) + (void)ctx; + + const uint16_t input_x = input_dims->w; + const uint16_t kernel_x = filter_dims->w; + const uint16_t output_x = output_dims->w; + const uint16_t output_ch = output_dims->c; + const uint16_t input_ch = input_dims->c; + const uint16_t pad_x = conv_params->padding.w; + const uint16_t stride_x = conv_params->stride.w; + + int i_batch; + for (i_batch = 0; i_batch < input_dims->n; i_batch++) + { + for (int i_out_x = 0; i_out_x <= (output_x - 4); i_out_x += 4) + { + int32_t input_begin_idx[4]; + int32_t ker_begin_idx[4]; + int32_t ker_end_idx[4]; + + for (int i = 0; i < 4; i++) + { + const int32_t est_input_x_idx = stride_x * (i_out_x + i) - pad_x; + input_begin_idx[i] = MAX(0, est_input_x_idx); + ker_begin_idx[i] = MAX(0, -est_input_x_idx); + ker_end_idx[i] = MIN(kernel_x, input_x - est_input_x_idx); + } + + if ((ker_begin_idx[0] != 0) || (ker_end_idx[3] != kernel_x)) + { + for (int i = 0; i < 4; i++) + { + const int32_t actual_kernel_len = ker_end_idx[i] - ker_begin_idx[i]; + arm_nn_mat_mul_core_1x_s8(actual_kernel_len * input_ch, + (kernel_x - actual_kernel_len) * input_ch, + input_data + input_begin_idx[i] * input_ch, + filter_data + (ker_begin_idx[i] * input_ch), + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + output_data += output_ch; + } + } + else + { + output_data = arm_nn_mat_mul_core_4x_s8(kernel_x * input_ch, + stride_x * input_ch, + input_data + input_begin_idx[0] * input_ch, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + } + } + /* Advance to the next batch */ + input_data += (input_x * input_ch); + } + +#else + status = arm_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); +#endif + +out: + /* Return to application */ + return status; +} + +int32_t arm_convolve_1_x_n_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if !defined(ARM_MATH_MVEI) + return arm_convolve_s8_get_buffer_size(input_dims, filter_dims); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..d0abf21 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c @@ -0,0 +1,207 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast Q7 version of 1x1 convolution (non-sqaure shape) + * Refer function header for details + * + */ + +arm_cmsis_nn_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + (void)dim_im_in_y; + int16_t i_out_y, i_out_x; + int16_t i_ch_out; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer, ch_im_in); + pBuffer += ch_im_in; + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + q31_t sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c new file mode 100644 index 0000000..98eb524 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c @@ -0,0 +1,146 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_s8_fast.c + * Description: Fast q7 version of 1x1 convolution (non-square shape) + * + * $Date: 20 june 2022 + * $Revision: V.3.0.1 + * + * Target Processor: Cortex-M Processors + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" +#include + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast s8 version for 1x1 convolution (non-square shape) + * + * Refer header file for details. + * + */ + +arm_cmsis_nn_status arm_convolve_1x1_s8_fast(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if (conv_params->padding.w != 0 || conv_params->padding.h != 0 || conv_params->stride.w != 1 || + conv_params->stride.h != 1) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + (void)ctx; + (void)filter_dims; + (void)bias_dims; + +#if defined(ARM_MATH_MVEI) + + const int32_t col_len = input_dims->w * input_dims->h * input_dims->n; + const int32_t output_ch = output_dims->c; + const int32_t input_ch = input_dims->c; + + for (int i_items = 0; i_items <= (col_len - 4); i_items += 4) + { + output_data = arm_nn_mat_mul_core_4x_s8(input_ch, + input_ch, + input_data + i_items * input_ch, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + } + + /* Handle left over elements */ + for (int i_items = (col_len & ~0x3); i_items < col_len; i_items++) + { + arm_nn_mat_mul_core_1x_s8(input_ch, + 0, + input_data + i_items * input_ch, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + output_data += output_ch; + } + +#else + /* Run the following code as reference implementation for Cortex-M processors with or without DSP extension */ + + const int32_t lhs_rows = input_dims->w * input_dims->h * input_dims->n; + const int32_t rhs_rows = output_dims->c; + const int32_t rhs_cols = input_dims->c; + + arm_nn_mat_mult_nt_t_s8(input_data, + filter_data, + bias_data, + output_data, + quant_params->multiplier, + quant_params->shift, + lhs_rows, + rhs_rows, + rhs_cols, + conv_params->input_offset, + conv_params->output_offset, + conv_params->activation.min, + conv_params->activation.max); + +#endif + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +int32_t arm_convolve_1x1_s8_fast_get_buffer_size(const cmsis_nn_dims *input_dims) +{ + (void)input_dims; + return 0; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c new file mode 100644 index 0000000..fe642d8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c @@ -0,0 +1,187 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic Q15 convolution function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + uint16_t im2col_out_pixel_index = 0; + q15_t *pBuffer = bufferA; + q15_t *pOut = Im_out; + q15_t *im_buffer = bufferA; + const q15_t *pA; + int i; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + pA = wt; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = im_buffer; + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q15_t)__SSAT((sum >> out_shift), 16); + pOut++; + } + + /* counter reset */ + pBuffer = im_buffer; + im2col_out_pixel_index++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c new file mode 100644 index 0000000..a0bbd22 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c @@ -0,0 +1,230 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast Q15 convolution function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0 || dim_im_out & 0x1) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA2); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel * dim_kernel; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c new file mode 100644 index 0000000..7d62293 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c @@ -0,0 +1,238 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast Q15 convolution function (non-sqaure shape) + * Refer function header for details + */ + +arm_cmsis_nn_status arm_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA2); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c new file mode 100644 index 0000000..ed388a5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c @@ -0,0 +1,252 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Q7 convolution function for RGB image + * Refer function header for details + */ + +arm_cmsis_nn_status arm_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + // This part implements the im2col function + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */ + arm_memset_q7((q7_t *)pBuffer, (q7_t)0, 3 * sizeof(q15_t)); + pBuffer += 3; + } + else + { + /* + * Equivalent to: + * arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3); + */ + + const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3; + q31_t buf = arm_nn_read_q7x4(pPixel); + + union arm_nnword top; + union arm_nnword bottom; + + top.word = __SXTB16(buf); + bottom.word = __SXTB16(__ROR(buf, 8)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * little-endian, | omit | 3rd | 2nd | 1st | + * MSB LSB + * top | 3rd | 1st |; bottom | omit | 2nd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = top.word; + * *(pBuffer+2) = bottom.half_words[0]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = top.half_words[0]; + int32_t packed_word = __PKHBT(bottom.word, top.word, 0); + arm_memcpy_q7((q7_t *)pBuffer, (q7_t *)&packed_word, 4); +#else + /* + * big-endian, | 1st | 2nd | 3rd | omit | + * MSB LSB + * top | 2nd | omit |; bottom | 1st | 3rd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = bottom.word; + * *(pBuffer+2) = top.half_words[1]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = bottom.half_words[0]; + int32_t packed_word = __PKHTB(top.word, bottom.word, 0); + arm_memcpy_q7((q7_t *)pBuffer, (q7_t *)&packed_word, 4); +#endif + pBuffer += 2; + } + } + } + + if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, 3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = 3 * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia((const q15_t **)&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia((const q15_t **)&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = 3 * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c new file mode 100644 index 0000000..a74a1a7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c @@ -0,0 +1,205 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic Q7 convolution function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + const q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)bufferA; + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c new file mode 100644 index 0000000..9079695 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c @@ -0,0 +1,214 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic Q7 convolution function (non-sqaure shape) + * Refer function header for details + * + */ + +arm_cmsis_nn_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + const q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)bufferA; + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c new file mode 100644 index 0000000..8f28bd6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c @@ -0,0 +1,341 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast Q7 convolution function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out - padding; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out - padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *)Im_in + + (i_ker_y * dim_im_in + i_out_x * stride - padding) * ch_im_in, + pBuffer, + ch_im_in * dim_kernel); + pBuffer += ch_im_in * dim_kernel; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..a091be3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c @@ -0,0 +1,356 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast Q7 convolution function (non-sqaure shape) + * Refer function header for details + */ + +arm_cmsis_nn_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out_y - padding_y; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out_x - padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in, + pBuffer, + ch_im_in * dim_kernel_x); + pBuffer += ch_im_in * dim_kernel_x; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c new file mode 100644 index 0000000..26c64fa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c @@ -0,0 +1,245 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_fast_s16.c + * Description: Optimized s16 version of convolution. + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s16 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_cmsis_nn_status arm_convolve_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ + (void)bias_dims; + if (filter_dims->w * filter_dims->h * input_dims->c >= 512) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + if (ctx->buf == NULL && arm_convolve_s8_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + q15_t *buffer_a = (q15_t *)ctx->buf; + + const int32_t input_batches = input_dims->n; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_ch = output_dims->c; + + const int32_t pad_x = conv_params->padding.w; + const int32_t pad_y = conv_params->padding.h; + const int32_t stride_x = conv_params->stride.w; + const int32_t stride_y = conv_params->stride.h; + + const int16_t out_activation_min = conv_params->activation.min; + const int16_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Generate two columns from the input tensor a GEMM computation */ + q15_t *two_column_buf = buffer_a; + q15_t *out = output_data; + /* This part implements the im2col function */ + for (int32_t i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (int32_t i_out_x = 0; i_out_x < output_x; i_out_x++) + { + for (int32_t i_ker_y = i_out_y * stride_y - pad_y; i_ker_y < i_out_y * stride_y - pad_y + kernel_y; + i_ker_y++) + { + for (int32_t i_ker_x = i_out_x * stride_x - pad_x; i_ker_x < i_out_x * stride_x - pad_x + kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + /* Filling 0 for out-of-bound paddings */ + arm_memset_q7((q7_t *)two_column_buf, 0, sizeof(q15_t) * input_ch); + } + else + { + arm_memcpy_q7((q7_t *)two_column_buf, + (const q7_t *)(input_data + (i_ker_y * input_x + i_ker_x) * input_ch), + input_ch * sizeof(q15_t)); + } + two_column_buf += input_ch; + } + } + /* Computation is filed for every 2 columns */ + if (two_column_buf == buffer_a + 2 * input_ch * kernel_y * kernel_x) + { + out = arm_nn_mat_mult_kernel_s16(filter_data, + buffer_a, + output_ch, + output_shift, + output_mult, + out_activation_min, + out_activation_max, + (input_ch * kernel_y * kernel_x), + bias_data, + out); + + /* Counter reset */ + two_column_buf = buffer_a; + } + } + } + + /* Left-over because odd number of output pixels */ + if (two_column_buf != buffer_a) + { + const q7_t *ker_a = filter_data; + int i; + + for (i = 0; i < output_ch; i++) + { + /* Init the accumulator*/ + q31_t sum = 0; + + /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ + const q15_t *ip_as_col = buffer_a; + + /* 4 multiply and accumulates are done in one loop. */ + uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + + while (col_count) + { + q31_t ker_a1, ker_a2; + q31_t ip_b1, ip_b2; + + ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2); + + ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a1, ip_b1, sum); + ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a2, ip_b2, sum); + + col_count--; + } + /* Handle left over mac */ + col_count = input_ch * kernel_y * kernel_x & 0x3; + while (col_count) + { + q7_t ker_a1 = *ker_a++; + q15_t ip_b1 = *ip_as_col++; + sum += ker_a1 * ip_b1; + col_count--; + } + if (bias_data) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i]); + q63_t acc_64 = sum + bias_data[i]; + sum = arm_nn_requantize_s64(acc_64, reduced_multiplier, output_shift[i]); + } + else + { + sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]); + } + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + *out++ = (q15_t)sum; + } + } +#else + (void)input_data; + (void)output_data; + (void)bias_data; + (void)filter_data; + (void)buffer_a; + (void)kernel_x; + (void)kernel_y; + (void)pad_x; + (void)pad_y; + (void)stride_x; + (void)stride_y; + (void)out_activation_min; + (void)out_activation_max; + (void)output_mult; + (void)output_shift; + return ARM_CMSIS_NN_ARG_ERROR; +#endif + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +int32_t arm_convolve_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c new file mode 100644 index 0000000..7d8d14f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c @@ -0,0 +1,160 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_s16.c + * Description: s16 version of convolution using symmetric quantization. + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s16 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_cmsis_nn_status arm_convolve_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ + (void)bias_dims; + (void)ctx; + + const int32_t input_batches = input_dims->n; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_ch = output_dims->c; + + const int32_t pad_x = conv_params->padding.w; + const int32_t pad_y = conv_params->padding.h; + const int32_t stride_x = conv_params->stride.w; + const int32_t stride_y = conv_params->stride.h; + const int32_t dilation_x = conv_params->dilation.w; + const int32_t dilation_y = conv_params->dilation.h; + + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (int32_t i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i_out_ch]); + + for (int32_t base_idx_y = -pad_y, i_out_y = 0; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) + { + for (int32_t base_idx_x = -pad_x, i_out_x = 0; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) + { + int64_t conv_out_acc = 0; + + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + const int32_t ker_y_start = MAX(0, start_y_max); + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + const int32_t ker_x_start = MAX(0, start_x_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + const int32_t ker_y_end = MIN(kernel_y, end_min_y); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + const int32_t ker_x_end = MIN(kernel_x, end_min_x); + + for (int32_t i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + for (int32_t i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t in_row = base_idx_y + dilation_y * i_ker_y; + const int32_t in_col = base_idx_x + dilation_x * i_ker_x; + + for (int32_t i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + conv_out_acc += input_data[(in_row * input_x + in_col) * input_ch + i_input_ch] * + filter_data[i_out_ch * input_ch * kernel_y * kernel_x + + (i_ker_y * kernel_x + i_ker_x) * input_ch + i_input_ch]; + } + } + } + + if (bias_data) + { + conv_out_acc += bias_data[i_out_ch]; + } + + int32_t conv_out = arm_nn_requantize_s64(conv_out_acc, reduced_multiplier, output_shift[i_out_ch]); + conv_out = MAX(conv_out, out_activation_min); + conv_out = MIN(conv_out, out_activation_max); + output_data[i_out_ch + (i_out_y * output_x + i_out_x) * output_ch] = (int16_t)conv_out; + } + } + } + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +int32_t arm_convolve_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ + (void)input_dims; + (void)filter_dims; + return 0; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c new file mode 100644 index 0000000..2782521 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c @@ -0,0 +1,339 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_s8.c + * Description: s8 version of convolution using symmetric quantization. + * + * $Date: 19 April 2022 + * $Revision: V.3.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s8 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_cmsis_nn_status arm_convolve_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + + if (ctx->buf == NULL && arm_convolve_s8_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + q15_t *buffer_a = (q15_t *)ctx->buf; + + const int32_t input_batches = input_dims->n; + const uint16_t input_x = input_dims->w; + const uint16_t input_y = input_dims->h; + const uint16_t input_ch = input_dims->c; + const uint16_t kernel_x = filter_dims->w; + const uint16_t kernel_y = filter_dims->h; + const uint16_t output_x = output_dims->w; + const uint16_t output_y = output_dims->h; + const uint16_t output_ch = output_dims->c; + + const uint16_t pad_x = conv_params->padding.w; + const uint16_t pad_y = conv_params->padding.h; + const uint16_t stride_x = conv_params->stride.w; + const uint16_t stride_y = conv_params->stride.h; + + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + int i_batch; + for (i_batch = 0; i_batch < input_batches; i_batch++) + { +#if defined(ARM_MATH_MVEI) + /* Generate upto four columns from the input tensor a GEMM computation */ + q7_t *im2col_buf = (q7_t *)buffer_a; + q7_t *out = output_data; + int32_t buffer_fill_cnt = 0; + int32_t padded = 0; + const int32_t num_elem = kernel_x * kernel_y * input_ch; + const int32_t dilation_x = conv_params->dilation.w; + const int32_t dilation_y = conv_params->dilation.h; + + /* This part implements the im2col function */ + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + + for (int32_t i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + for (int32_t i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t k_y = base_idx_y + dilation_y * i_ker_y; + const int32_t k_x = base_idx_x + dilation_x * i_ker_x; + + if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x) + { + memset(im2col_buf, (int8_t)-input_offset, sizeof(q7_t) * input_ch); + padded = 1; + } + else + { + arm_memcpy_q7(im2col_buf, input_data + (k_y * input_x + k_x) * input_ch, input_ch); + } + im2col_buf += input_ch; + } + } + + buffer_fill_cnt++; + + /* Computation is filed for every 4 columns */ + if (buffer_fill_cnt == 4 && (padded == 0)) + { + buffer_fill_cnt = 0; + out = arm_nn_mat_mul_core_4x_s8(num_elem, + num_elem, + (q7_t *)buffer_a, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + out); + im2col_buf = (q7_t *)buffer_a; + } + else if (buffer_fill_cnt == 4 && (padded != 0)) + { + buffer_fill_cnt = 0; + out = arm_nn_mat_mult_s8(filter_data, + (q7_t *)buffer_a, + output_ch, + 4, + output_shift, + output_mult, + out_offset, + input_offset, + 0, + out_activation_min, + out_activation_max, + num_elem, + bias_data, + out); + + im2col_buf = (q7_t *)buffer_a; + padded = 0; + } + } + } + /* Handle left over columns */ + if (buffer_fill_cnt != 0) + { + out = arm_nn_mat_mult_s8(filter_data, + (q7_t *)buffer_a, + output_ch, + buffer_fill_cnt, + output_shift, + output_mult, + out_offset, + input_offset, + 0, + out_activation_min, + out_activation_max, + num_elem, + bias_data, + out); + } +#else // #if defined(ARM_MATH_MVEI) + const uint16_t dilation_x = conv_params->dilation.w; + const uint16_t dilation_y = conv_params->dilation.h; + + int32_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* Generate two columns from the input tensor a GEMM computation */ + q15_t *two_column_buf = buffer_a; + q7_t *out = output_data; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + + for (i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t k_y = base_idx_y + dilation_y * i_ker_y; + const int32_t k_x = base_idx_x + dilation_x * i_ker_x; + + if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x) + { + /* Filling 0 for out-of-bound paddings */ + memset(two_column_buf, 0, sizeof(q15_t) * input_ch); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_with_offset( + input_data + (k_y * input_x + k_x) * input_ch, two_column_buf, input_ch, input_offset); + } + two_column_buf += input_ch; + } + } + + /* Computation is filed for every 2 columns */ + if (two_column_buf == buffer_a + 2 * input_ch * kernel_y * kernel_x) + { + out = arm_nn_mat_mult_kernel_s8_s16(filter_data, + buffer_a, + output_ch, + output_shift, + output_mult, + out_offset, + out_activation_min, + out_activation_max, + input_ch * kernel_y * kernel_x, + bias_data, + out); + + /* counter reset */ + two_column_buf = buffer_a; + } + } + } + + /* left-over because odd number of output pixels */ + if (two_column_buf != buffer_a) + { + const q7_t *ker_a = filter_data; + int i; + + for (i = 0; i < output_ch; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = 0; + if (bias_data) + { + sum = bias_data[i]; + } + + /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ + const q15_t *ip_as_col = buffer_a; + + /* 4 multiply and accumulates are done in one loop. */ +#if defined(ARM_MATH_DSP) + uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + + while (col_count) + { + q31_t ker_a1, ker_a2; + q31_t ip_b1, ip_b2; + + ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2); + + ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a1, ip_b1, sum); + ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a2, ip_b2, sum); + + col_count--; + } + /* Handle left over mac */ + col_count = input_ch * kernel_y * kernel_x & 0x3; +#else + uint16_t col_count = input_ch * kernel_y * kernel_x; +#endif + while (col_count) + { + q7_t ker_a1 = *ker_a++; + q15_t ip_b1 = *ip_as_col++; + sum += ker_a1 * ip_b1; + col_count--; + } + + sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + *out++ = (q7_t)sum; + } + } +#endif // #if defined(ARM_MATH_MVEI) + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +int32_t arm_convolve_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_MVEI) + int32_t col_length = input_dims->c * filter_dims->w * filter_dims->h; + // Get number of complete int16 lanes(multiple of 8) for given col_length. This is dependent on + // implementation of arm_nn_mat_mult_s8 + col_length = (col_length + 7) / 8; + // 4 -> number of im2col buffers, 8 -> 8 elements per Q register + return 4 * col_length * 8 * (int32_t)sizeof(int8_t); +#else + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +#endif +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c new file mode 100644 index 0000000..efdbc41 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c @@ -0,0 +1,134 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2021-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_wrapper_s16.c + * Description: s16 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +arm_cmsis_nn_status arm_convolve_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + if (filter_dims->w * filter_dims->h * input_dims->c < 512 && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_fast_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return arm_convolve_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +#else + return arm_convolve_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); +#endif +} + +int32_t arm_convolve_wrapper_s16_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + (void)conv_params; + (void)output_dims; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + if (filter_dims->w * filter_dims->h * input_dims->c < 512 && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_fast_s16_get_buffer_size(input_dims, filter_dims); + } + + return arm_convolve_s16_get_buffer_size(input_dims, filter_dims); +#else + return arm_convolve_s16_get_buffer_size(input_dims, filter_dims); +#endif +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c new file mode 100644 index 0000000..9cd898e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c @@ -0,0 +1,136 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_wrapper_s8.c + * Description: s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * $Date: 4 August 2022 + * $Revision: V.2.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +arm_cmsis_nn_status arm_convolve_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (conv_params->stride.w == 1) && + (conv_params->stride.h == 1) && (filter_dims->w == 1) && (filter_dims->h == 1) && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1x1_s8_fast(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else if ((input_dims->h == 1) && (output_dims->w % 4 == 0) && conv_params->dilation.w == 1 && (filter_dims->h == 1)) + { + return arm_convolve_1_x_n_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return arm_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +} + +int32_t arm_convolve_wrapper_s8_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (conv_params->stride.w == 1) && + (conv_params->stride.h == 1) && (filter_dims->w == 1) && (filter_dims->h == 1) && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1x1_s8_fast_get_buffer_size(input_dims); + } + else if ((input_dims->h == 1) && (output_dims->w % 4 == 0) && (conv_params->dilation.w == 1) && + (filter_dims->h == 1)) + { + return arm_convolve_1_x_n_s8_get_buffer_size(input_dims, filter_dims); + } + else + { + return arm_convolve_s8_get_buffer_size(input_dims, filter_dims); + } +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c new file mode 100644 index 0000000..def3b47 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c @@ -0,0 +1,228 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_3x3_s8.c + * Description: Optimized s8 depthwise convolution function for channel + * multiplier of 1 and 3x3 kernel size. + * + * $Date: 19 July 2022 + * $Revision: V.3.1.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that + * in_channel == out_channel and kernel_x == kernel_y == 3 with pads at most 1 + * + * Refer prototype header file for details. + * + */ + +arm_cmsis_nn_status arm_depthwise_conv_3x3_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)ctx; + (void)bias_dims; + + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + /* Check input constraints pad_x <= 1 */ + if (pad_x > 1 || filter_dims->w != 3 || filter_dims->h != 3) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + const int32_t *bias_base = bias; + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + int32_t in_ch = 0; + int32_t ker_w_start = MAX(0, -in_w); + + bias = bias_base; + for (; in_ch <= (input_ch - 4); in_ch += 4) + { + int32_t out_buff0 = 0; + int32_t out_buff1 = 0; + int32_t out_buff2 = 0; + int32_t out_buff3 = 0; + if (bias) + { + out_buff0 = *bias++; + out_buff1 = *bias++; + out_buff2 = *bias++; + out_buff3 = *bias++; + } + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + int32_t in_val = 0; + int32_t ker_val = 0; + + if (ker_w_start == 0) + { + in_val = arm_nn_read_q7x4(input_ptr); + ker_val = arm_nn_read_q7x4(kernel_ptr); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + in_val = arm_nn_read_q7x4(input_ptr + input_ch); + ker_val = arm_nn_read_q7x4(kernel_ptr + input_ch); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + + if ((input_x - in_w) >= 3) + { + in_val = arm_nn_read_q7x4(input_ptr + (input_ch << 1)); + ker_val = arm_nn_read_q7x4(kernel_ptr + (input_ch << 1)); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff0 = arm_nn_requantize(out_buff0, output_mult[in_ch + 0], output_shift[in_ch + 0]); + out_buff1 = arm_nn_requantize(out_buff1, output_mult[in_ch + 1], output_shift[in_ch + 1]); + out_buff2 = arm_nn_requantize(out_buff2, output_mult[in_ch + 2], output_shift[in_ch + 2]); + out_buff3 = arm_nn_requantize(out_buff3, output_mult[in_ch + 3], output_shift[in_ch + 3]); + + out_buff0 += output_offset; + out_buff1 += output_offset; + out_buff2 += output_offset; + out_buff3 += output_offset; + + out_buff0 = MIN(MAX(out_buff0, output_activation_min), output_activation_max); + out_buff1 = MIN(MAX(out_buff1, output_activation_min), output_activation_max); + out_buff2 = MIN(MAX(out_buff2, output_activation_min), output_activation_max); + out_buff3 = MIN(MAX(out_buff3, output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff0; + output[out_idx++] = (int8_t)out_buff1; + output[out_idx++] = (int8_t)out_buff2; + output[out_idx++] = (int8_t)out_buff3; + } + + // Leftover + for (; in_ch < input_ch; ++in_ch) + { + int32_t out_buff = 0; + if (bias) + { + out_buff = *bias++; + } + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + if (ker_w_start == 0) + { + out_buff += (*(input_ptr) + input_offset) * *(kernel_ptr); + } + + out_buff += (*(input_ptr + input_ch) + input_offset) * *(kernel_ptr + input_ch); + + if ((input_x - in_w) >= 3) + { + out_buff += (*(input_ptr + (input_ch << 1)) + input_offset) * *(kernel_ptr + (input_ch << 1)); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff = arm_nn_requantize(out_buff, output_mult[in_ch], output_shift[in_ch]); + out_buff += output_offset; + out_buff = MIN(MAX(out_buff, output_activation_min), output_activation_max); + output[out_idx++] = (int8_t)out_buff; + } + } + } + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c new file mode 100644 index 0000000..20201b9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_fast_s16.c @@ -0,0 +1,471 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_fast_s16.c + * Description: Optimized s16 depthwise separable convolution function for + * channel multiplier of 1. + * + * $Date: 6 July 2022 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s16 depthwise convolution function with constraint that in_channel equals out_channel + * + * Refer prototype header file for details. + * + */ + +arm_cmsis_nn_status arm_depthwise_conv_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + if (filter_dims->w * filter_dims->h >= 512) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + if (ctx->buf == NULL && arm_depthwise_conv_fast_s16_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + +#if defined(ARM_MATH_DSP) + (void)bias_dims; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_batches = input_dims->n; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + q15_t *buffer_a = (q15_t *)ctx->buf; + +#if defined(ARM_MATH_MVEI) + int16_t *lhs_buffer = buffer_a; + int16_t *out = output; + int buffer_count = 0; + const int32_t kernel_size = kernel_x * kernel_y; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + /* This part implements the im2col function */ + for (int i_out_y = 0, base_idx_y = -pad_y; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) + { + for (int i_out_x = 0, base_idx_x = -pad_x; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) + { + for (int i_ker_y = base_idx_y; i_ker_y < base_idx_y + kernel_y; i_ker_y++) + { + for (int i_ker_x = base_idx_x; i_ker_x < base_idx_x + kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + memset(lhs_buffer, (int16_t)0, (uint32_t)(input_ch * sizeof(int16_t))); + } + else + { + arm_memcpy_q15(lhs_buffer, + (int16_t *)(input + (i_ker_y * input_x + i_ker_x) * input_ch), + (uint32_t)(input_ch * sizeof(int16_t))); + } + lhs_buffer += input_ch; + } + } + buffer_count++; + if (buffer_count == 4) + { + lhs_buffer = buffer_a; + + out = arm_nn_depthwise_conv_nt_t_s16(lhs_buffer, + kernel, + input_ch, + output_shift, + output_mult, + output_activation_min, + output_activation_max, + kernel_size, + bias, + out); + buffer_count = 0; + } + } + } + input += input_x * input_y * input_ch; + } + + /* Handle left over buffers */ + lhs_buffer = buffer_a; + for (int i_buf = 0; i_buf < buffer_count; i_buf++) + { + int32_t loop_count = (input_ch + 3) / 4; + int32_t num_ch_to_process = input_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; num_ch_to_process -= 4, offset += 4, i_loop_cnt++) + { + const int8_t *row_0 = kernel + offset; + const int16_t *col_0 = lhs_buffer + (kernel_size * input_ch * i_buf) + offset; + + int32x4_t out_0 = vdupq_n_s32(0); + + for (int i_ker = 0; i_ker < kernel_size; i_ker++) + { + const int32x4_t ker_0 = vldrbq_s32(row_0); + + int32x4_t ip_0 = vldrhq_s32(col_0); + out_0 += vmulq_s32(ip_0, ker_0); + + col_0 += input_ch; + row_0 += input_ch; + } + + int64_t in_requantize_0 = (int64_t)out_0[0]; + int64_t in_requantize_1 = (int64_t)out_0[1]; + int64_t in_requantize_2 = (int64_t)out_0[2]; + int64_t in_requantize_3 = (int64_t)out_0[3]; + + if (bias) + { + in_requantize_0 += bias[offset]; + in_requantize_1 += bias[offset + 1]; + in_requantize_2 += bias[offset + 2]; + in_requantize_3 += bias[offset + 3]; + } + + int32_t reduced_multiplier_0 = REDUCE_MULTIPLIER(output_mult[offset]); + int32_t reduced_multiplier_1 = REDUCE_MULTIPLIER(output_mult[offset + 1]); + int32_t reduced_multiplier_2 = REDUCE_MULTIPLIER(output_mult[offset + 2]); + int32_t reduced_multiplier_3 = REDUCE_MULTIPLIER(output_mult[offset + 3]); + + out_0[0] = arm_nn_requantize_s64(in_requantize_0, reduced_multiplier_0, output_shift[offset]); + out_0[1] = arm_nn_requantize_s64(in_requantize_1, reduced_multiplier_1, output_shift[offset + 1]); + out_0[2] = arm_nn_requantize_s64(in_requantize_2, reduced_multiplier_2, output_shift[offset + 2]); + out_0[3] = arm_nn_requantize_s64(in_requantize_3, reduced_multiplier_3, output_shift[offset + 3]); + + out_0 = vmaxq_s32(out_0, vdupq_n_s32(output_activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(output_activation_max)); + + mve_pred16_t p = vctp32q((uint32_t)num_ch_to_process); + vstrhq_p_s32(out, out_0, p); + + out += 4; + } + + const int tail_ch = input_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + } + +#else // ARM_MATH_DSP + + /* Run the following code in cores using DSP extension */ + q15_t *const col_buffer_start = buffer_a; + q15_t *col_buffer = col_buffer_start; + const int64_t *const bias_start_pos = bias; + const int32_t *const out_mult_start_pos = output_mult; + const int32_t *const out_shift_start_pos = output_shift; + uint16_t row_count; + uint16_t row_shift; + int32_t result; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + + /* Out of bounds is only considered for the y axis as it provides a contiguous zero'ing opportunity than + along the x axis */ + const int ker_y_start = MAX(0, -base_idx_y); + /* Condition for kernel end dimension: (base_idx_y + ker_y_end) < input_y */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + + int32_t index = 0; + if (ker_y_start != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * ker_y_start * sizeof(q15_t)); + index += (kernel_x * input_ch) * ker_y_start; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + + for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + + if (idx_x < 0 || idx_x >= input_x) + { + memset(&col_buffer[index], 0, input_ch * sizeof(q15_t)); + } + else + { + arm_memcpy_q15(&col_buffer[index], + input + (idx_y * input_x + idx_x) * input_ch, + input_ch * sizeof(q15_t)); + } + index += input_ch; + } + } + + const int diff = kernel_y - ker_y_end; + if (diff != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * diff * sizeof(q15_t)); + } + + row_count = output_ch / 4; + row_shift = 0; + bias = bias_start_pos; + output_mult = out_mult_start_pos; + output_shift = out_shift_start_pos; + + while (row_count) + { + q31_t sum_1 = 0; + q31_t sum_2 = 0; + q31_t sum_3 = 0; + q31_t sum_4 = 0; + + int32_t output_mult_1 = REDUCE_MULTIPLIER(output_mult[0]); + int32_t output_mult_2 = REDUCE_MULTIPLIER(output_mult[1]); + int32_t output_mult_3 = REDUCE_MULTIPLIER(output_mult[2]); + int32_t output_mult_4 = REDUCE_MULTIPLIER(output_mult[3]); + output_mult += 4; + + uint16_t col_count = (kernel_x * kernel_y) / 2; + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + row_shift += 4; + + while (col_count) + { + /* General idea is to read 4 + 4 (input, kernel) pair and re-arrange them in the right order to + use in a SMLAD instruction . One run of this loop produces 4 partial outputs with 8 MACs. */ + q31_t row_a1, row_a2, row_b1, row_b2, col_a, row_c, col_b, col_c; + + /* Read 4 weights */ + row_b1 = arm_nn_read_q7x4(row_pos); + row_a1 = arm_nn_read_q7x4(row_pos + input_ch); + col_a = arm_nn_read_q15x2(col_pos); + col_b = arm_nn_read_q15x2(col_pos + input_ch); + + row_a2 = __SXTB16(row_b1); + row_b1 = __SXTB16(__ROR(row_b1, 8)); + + row_b2 = __SXTB16(row_a1); + row_a1 = __SXTB16(__ROR(row_a1, 8)); + + col_c = __PKHBT(col_b, col_a, 16); + col_a = __PKHTB(col_b, col_a, 16); + row_c = __PKHBT(row_b2, row_a2, 16); + sum_1 = __SMLAD(col_c, row_c, sum_1); + + row_c = __PKHBT(row_b1, row_a1, 16); + sum_2 = __SMLAD(col_a, row_c, sum_2); + + col_a = arm_nn_read_q15x2(col_pos + 2); + col_b = arm_nn_read_q15x2(col_pos + input_ch + 2); + + col_c = __PKHBT(col_b, col_a, 16); + col_a = __PKHTB(col_b, col_a, 16); + row_c = __PKHTB(row_a2, row_b2, 16); + sum_3 = __SMLAD(col_c, row_c, sum_3); + + row_c = __PKHTB(row_a1, row_b1, 16); + sum_4 = __SMLAD(col_a, row_c, sum_4); + + row_pos += input_ch << 1; + col_pos += input_ch << 1; + col_count--; + } + + col_count = (kernel_x * kernel_y) & 0x1; + while (col_count) + { + sum_1 += row_pos[0] * col_pos[0]; + sum_2 += row_pos[1] * col_pos[1]; + sum_3 += row_pos[2] * col_pos[2]; + sum_4 += row_pos[3] * col_pos[3]; + + row_pos += input_ch; + col_pos += input_ch; + + col_count--; + } + + int64_t acc_1 = sum_1; + int64_t acc_2 = sum_2; + int64_t acc_3 = sum_3; + int64_t acc_4 = sum_4; + + if (bias) + { + acc_1 += *bias++; + acc_2 += *bias++; + acc_3 += *bias++; + acc_4 += *bias++; + } + + result = arm_nn_requantize_s64(acc_1, output_mult_1, *output_shift++); + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (q15_t)result; + + result = arm_nn_requantize_s64(acc_2, output_mult_2, *output_shift++); + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (q15_t)result; + + result = arm_nn_requantize_s64(acc_3, output_mult_3, *output_shift++); + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (q15_t)result; + + result = arm_nn_requantize_s64(acc_4, output_mult_4, *output_shift++); + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (q15_t)result; + + row_count--; + } + + row_count = output_ch & 0x3; + while (row_count) + { + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + q31_t sum = 0; + const uint16_t col_count = (kernel_x * kernel_y); + row_shift += 1; + + for (int i = 0; i < col_count; i++) + { + sum += row_pos[i * input_ch] * col_pos[i * input_ch]; + } + int64_t acc = sum; + if (bias) + { + acc += *bias++; + } + result = arm_nn_requantize_s64(acc, REDUCE_MULTIPLIER(*output_mult), *output_shift++); + output_mult++; + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (q15_t)result; + + row_count--; + } + // clear counter and pointers + col_buffer = col_buffer_start; + } + } + + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +#endif +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + return arm_depthwise_conv_s16(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + kernel, + bias_dims, + bias, + output_dims, + output); +#endif /* ARM_MATH_MVEI | ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +int32_t arm_depthwise_conv_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_DSP) +#if defined(ARM_MATH_MVEI) + /* The + 8 accounts for a worst case out of bounds read of the lhs buffers in the *_nt_t_* function. */ + return 4 * input_dims->c * filter_dims->w * filter_dims->h * sizeof(int16_t) + 8; +#else // ARM_MATH_DSP + return input_dims->c * filter_dims->w * filter_dims->h * sizeof(int16_t); +#endif +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c new file mode 100644 index 0000000..e0e39ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c @@ -0,0 +1,296 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s16.c + * Description: s16 version of depthwise convolution. + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void __attribute__((unused)) depthwise_conv_s16_mult_4_s16(const int16_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int64_t *bias, + int16_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff32[4] = {REDUCE_MULTIPLIER(output_mult[out_ch + 0 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 1 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 2 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 3 + mult_tile])}; + + int64_t out_buff[4] = {0, 0, 0, 0}; + + if (bias) + { + out_buff[0] = bias[out_ch + 0 + mult_tile]; + out_buff[1] = bias[out_ch + 1 + mult_tile]; + out_buff[2] = bias[out_ch + 2 + mult_tile]; + out_buff[3] = bias[out_ch + 3 + mult_tile]; + } + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang loop unroll(disable) +#endif + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + // TODO: Unroll of 4 with 64 bit accumulator will probably result in too much register + // spills. Try with unroll of 2 when enabling this. + int32_t in_val = input[in_idx + ker_w * input_ch]; + out_buff[0] += in_val * kernel[ker_idx + 0 + mult_tile]; + out_buff[1] += in_val * kernel[ker_idx + 1 + mult_tile]; + out_buff[2] += in_val * kernel[ker_idx + 2 + mult_tile]; + out_buff[3] += in_val * kernel[ker_idx + 3 + mult_tile]; + } + } + + out_buff32[0] = + arm_nn_requantize_s64(out_buff[0], out_buff32[0], output_shift[out_ch + 0 + mult_tile]); + out_buff32[1] = + arm_nn_requantize_s64(out_buff[1], out_buff32[1], output_shift[out_ch + 1 + mult_tile]); + out_buff32[2] = + arm_nn_requantize_s64(out_buff[2], out_buff32[2], output_shift[out_ch + 2 + mult_tile]); + out_buff32[3] = + arm_nn_requantize_s64(out_buff[3], out_buff32[3], output_shift[out_ch + 3 + mult_tile]); + + out_buff32[0] = MIN(MAX(out_buff32[0], output_activation_min), output_activation_max); + out_buff32[1] = MIN(MAX(out_buff32[1], output_activation_min), output_activation_max); + out_buff32[2] = MIN(MAX(out_buff32[2], output_activation_min), output_activation_max); + out_buff32[3] = MIN(MAX(out_buff32[3], output_activation_min), output_activation_max); + + output[out_idx++] = (int16_t)out_buff32[0]; + output[out_idx++] = (int16_t)out_buff32[1]; + output[out_idx++] = (int16_t)out_buff32[2]; + output[out_idx++] = (int16_t)out_buff32[3]; + } + } + } + } +} + +static void depthwise_conv_s16_generic_s16(const int16_t *input, + const uint16_t input_batches, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const int8_t *kernel, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int64_t *bias, + int16_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const uint16_t dilation_x, + const uint16_t dilation_y) + +{ + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[idx_out_ch]); + int64_t acc_0 = 0; + + int ker_y_start; + int ker_x_start; + int ker_y_end; + int ker_x_end; + + if (dilation_x > 1) + { + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + ker_x_start = MAX(0, start_x_max); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + ker_x_end = MIN(kernel_x, end_min_x); + } + else + { + ker_x_start = MAX(0, -base_idx_x); + ker_x_end = MIN(kernel_x, input_x - base_idx_x); + } + + if (dilation_y > 1) + { + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + ker_y_start = MAX(0, start_y_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + ker_y_end = MIN(kernel_y, end_min_y); + } + else + { + ker_y_start = MAX(0, -base_idx_y); + ker_y_end = MIN(kernel_y, input_y - base_idx_y); + } + + if (bias) + { + acc_0 = bias[idx_out_ch]; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + dilation_y * i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + dilation_x * i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += input[idx_0] * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + int32_t result = arm_nn_requantize_s64(acc_0, reduced_multiplier, output_shift[idx_out_ch]); + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (int16_t)result; + } + } + } + } + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +} + +/* + * Basic s16 depthwise convolution function. + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_depthwise_conv_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + const uint16_t dilation_x = dw_conv_params->dilation.w; + const uint16_t dilation_y = dw_conv_params->dilation.h; + + (void)bias_dims; + (void)ctx; + + depthwise_conv_s16_generic_s16(input, + input_dims->n, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->activation.min, + dw_conv_params->activation.max, + dilation_x, + dilation_y); + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c new file mode 100644 index 0000000..862e87f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c @@ -0,0 +1,358 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s8.c + * Description: s8 version of depthwise convolution. + * + * $Date: 29 July 2022 + * $Revision: V.3.0.3 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +#if !defined(__ARMCC_VERSION) +__attribute__((optimize("no-unroll-loops"))) +#endif +static void +depthwise_conv_s8_mult_4(const int8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + int8_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + const int32_t *bias_base = bias; + const int32_t *mult_base = output_mult; + const int32_t *shift_base = output_shift; + const int8_t *kernel_base = kernel; + + for (int32_t in_h = -pad_y, out_h = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + bias = bias_base; + output_mult = mult_base; + output_shift = shift_base; + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4] = {0, 0, 0, 0}; + if (bias) + { + out_buff[0] = *bias++; + out_buff[1] = *bias++; + out_buff[2] = *bias++; + out_buff[3] = *bias++; + } + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + kernel = kernel_base + mult_tile + ker_idx; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang loop unroll(disable) +#endif + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, kernel += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * kernel[0]; + out_buff[1] += in_val * kernel[1]; + out_buff[2] += in_val * kernel[2]; + out_buff[3] += in_val * kernel[3]; + } + } +#if defined(ARM_MATH_MVEI) + int32x4_t res = vldrwq_s32(out_buff); + res = arm_requantize_mve_32x4(res, vldrwq_s32(output_mult), vldrwq_s32(output_shift)); + output_mult += 4; + output_shift += 4; + res = vaddq_n_s32(res, output_offset); + + res = vmaxq_s32(res, vdupq_n_s32(output_activation_min)); + res = vminq_s32(res, vdupq_n_s32(output_activation_max)); + vstrbq_s32(output, res); + output += 4; +#else + out_buff[0] = arm_nn_requantize(out_buff[0], *output_mult++, *output_shift++); + out_buff[1] = arm_nn_requantize(out_buff[1], *output_mult++, *output_shift++); + out_buff[2] = arm_nn_requantize(out_buff[2], *output_mult++, *output_shift++); + out_buff[3] = arm_nn_requantize(out_buff[3], *output_mult++, *output_shift++); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + *output++ = (int8_t)out_buff[0]; + *output++ = (int8_t)out_buff[1]; + *output++ = (int8_t)out_buff[2]; + *output++ = (int8_t)out_buff[3]; + +#endif + } + } + } + } +} + +static void depthwise_conv_s8_generic(const q7_t *input, + const uint16_t input_batches, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const q7_t *kernel, + const uint16_t output_ch, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int32_t *bias, + q7_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max, + const uint16_t dilation_x, + const uint16_t dilation_y) + +{ + (void)output_ch; + int i_out = 0; + int i_batch; + + for (i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0 = 0; + + int ker_y_start; + int ker_x_start; + int ker_y_end; + int ker_x_end; + + if (dilation_x > 1) + { + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + ker_x_start = MAX(0, start_x_max); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + ker_x_end = MIN(kernel_x, end_min_x); + } + else + { + ker_x_start = MAX(0, -base_idx_x); + ker_x_end = MIN(kernel_x, input_x - base_idx_x); + } + + if (dilation_y > 1) + { + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + ker_y_start = MAX(0, start_y_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + ker_y_end = MIN(kernel_y, end_min_y); + } + else + { + ker_y_start = MAX(0, -base_idx_y); + ker_y_end = MIN(kernel_y, input_y - base_idx_y); + } + + if (bias) + { + acc_0 = bias[idx_out_ch]; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + dilation_y * i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + dilation_x * i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_requantize(acc_0, output_mult[idx_out_ch], output_shift[idx_out_ch]); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +} + +/* + * Basic s8 depthwise convolution function. + * + * Refer header file for details. + * Optimization using DSP extension is not available for the generic case where channel multiplier is > 1. + * + */ +arm_cmsis_nn_status arm_depthwise_conv_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + const uint16_t dilation_x = dw_conv_params->dilation.w; + const uint16_t dilation_y = dw_conv_params->dilation.h; + + (void)bias_dims; + (void)ctx; + + if (dw_conv_params->ch_mult % 4 == 0 && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { + depthwise_conv_s8_mult_4(input, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max); + } + else + { + depthwise_conv_s8_generic(input, + input_dims->n, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max, + dilation_x, + dilation_y); + } + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c new file mode 100644 index 0000000..fc12e72 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c @@ -0,0 +1,465 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s8_opt.c + * Description: Optimized s8 depthwise separable convolution function for + * channel multiplier of 1. + * + * $Date: 27 July 2022 + * $Revision: V.3.1.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel + * + * Refer prototype header file for details. + * + */ + +arm_cmsis_nn_status arm_depthwise_conv_s8_opt(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + + /* Check depth multiplier is 1 */ + if (input_ch != output_ch) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + if (ctx->buf == NULL && arm_depthwise_conv_s8_opt_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } +#ifdef ARM_MATH_DSP + (void)bias_dims; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + q15_t *buffer_a = (q15_t *)ctx->buf; + +#ifdef ARM_MATH_MVEI + /* Generate two columns from the input tensor */ + q7_t *lhs_buffer = (q7_t *)buffer_a; + q7_t *out = output; + int padded = 0; + int buffer_count = 0; + const int32_t kernel_size = kernel_x * kernel_y; + + const int32_t ch_loop = (input_ch + (CH_IN_BLOCK_MVE - 1)) / CH_IN_BLOCK_MVE; + int32_t remaining_ch = output_ch; + int32_t active_ch = MIN(CH_IN_BLOCK_MVE, remaining_ch); + remaining_ch -= CH_IN_BLOCK_MVE; + + for (int i_ch = 0; i_ch < ch_loop; i_ch++) + { + out = output + i_ch * CH_IN_BLOCK_MVE; + const int8_t *input_slice = input + (i_ch * CH_IN_BLOCK_MVE); + + for (int i_out_y = 0, base_idx_y = -pad_y; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) + { + for (int i_out_x = 0, base_idx_x = -pad_x; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) + { + for (int i_ker_y = base_idx_y; i_ker_y < base_idx_y + kernel_y; i_ker_y++) + { + for (int i_ker_x = base_idx_x; i_ker_x < base_idx_x + kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + arm_memset_q7(lhs_buffer, (int8_t)-input_offset, (uint32_t)active_ch); + padded = 1; + } + else + { + arm_memcpy_q7(lhs_buffer, + input_slice + (i_ker_y * input_x + i_ker_x) * input_ch, + (uint32_t)active_ch); + } + lhs_buffer += CH_IN_BLOCK_MVE; + } + } + buffer_count++; + + if (buffer_count == 4) + { + const int32_t block_offset = i_ch * CH_IN_BLOCK_MVE; + lhs_buffer = (q7_t *)buffer_a; + if (padded == 0) + { + arm_nn_depthwise_conv_nt_t_s8(lhs_buffer, + kernel + block_offset, + input_offset, + active_ch, + input_ch, + output_shift + block_offset, + output_mult + block_offset, + output_offset, + output_activation_min, + output_activation_max, + kernel_size, + bias + block_offset, + out); + } + else + { + arm_nn_depthwise_conv_nt_t_padded_s8(lhs_buffer, + kernel + block_offset, + input_offset, + active_ch, + input_ch, + output_shift + block_offset, + output_mult + block_offset, + output_offset, + output_activation_min, + output_activation_max, + kernel_size, + bias + block_offset, + out); + padded = 0; + } + out += (4 * input_ch); + buffer_count = 0; + } + } + } + /* Handle left over buffers */ + lhs_buffer = (q7_t *)buffer_a; + + int8_t *out_base = out; + for (int i_buf = 0; i_buf < buffer_count; i_buf++) + { + int32_t loop_count = (active_ch + 3) / 4; + int32_t num_ch_to_process = active_ch; + out = out_base + (i_buf * input_ch); + for (int i_loop_cnt = 0, offset = i_ch * CH_IN_BLOCK_MVE; i_loop_cnt < loop_count; + num_ch_to_process -= 4, offset += 4, i_loop_cnt++) + { + const int8_t *col_0 = lhs_buffer + (kernel_size * CH_IN_BLOCK_MVE * i_buf) + (i_loop_cnt * 4); + const int8_t *row_0 = kernel + offset; + int32x4_t out_0 = vdupq_n_s32(0); + if (bias) + { + out_0 = vldrwq_s32(&bias[offset]); + } + + for (int i_ker = 0; i_ker < kernel_size; i_ker++) + { + const int32x4_t ker_0 = vldrbq_s32(row_0); + int32x4_t ip_0 = vldrbq_s32(col_0); + ip_0 = vaddq_n_s32(ip_0, input_offset); + out_0 += vmulq_s32(ip_0, ker_0); + + col_0 += CH_IN_BLOCK_MVE; + row_0 += input_ch; + } + + const int32x4_t mult = vldrwq_s32(&output_mult[offset]); + const int32x4_t shift = vldrwq_s32(&output_shift[offset]); + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, output_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(output_activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(output_activation_max)); + mve_pred16_t p = vctp32q((uint32_t)num_ch_to_process); + vstrbq_p_s32(out, out_0, p); + + out += 4; + } + } + buffer_count = 0; + + active_ch = MIN(CH_IN_BLOCK_MVE, remaining_ch); + remaining_ch -= CH_IN_BLOCK_MVE; + } + +#else // ARM_MATH_DSP + /* Run the following code in cores using DSP extension */ + q15_t *const col_buffer_start = buffer_a; + q15_t *col_buffer = col_buffer_start; + const int32_t *const bias_start_pos = bias; + const q31_t *const out_mult_start_pos = output_mult; + const q31_t *const out_shift_start_pos = output_shift; + uint16_t row_count; + uint16_t row_shift; + + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + + /* Out of bounds is only considered for the y axis as it provides a contiguous zero'ing opportunity than + along the x axis */ + const int ker_y_start = MAX(0, -base_idx_y); + /* Condition for kernel end dimension: (base_idx_y + ker_y_end) < input_y */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + + int32_t index = 0; + if (ker_y_start != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * ker_y_start * sizeof(q15_t)); + index += (kernel_x * input_ch) * ker_y_start; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + + for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + if (idx_x < 0 || idx_x >= input_x) + { + memset(&col_buffer[index], 0, input_ch * sizeof(q15_t)); + } + else + { + arm_q7_to_q15_with_offset((q7_t *)input + (idx_y * input_x + idx_x) * input_ch, + &col_buffer[index], + input_ch, + input_offset); + } + index += input_ch; + } + } + + const int diff = kernel_y - ker_y_end; + if (diff != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * diff * sizeof(q15_t)); + } + + row_count = output_ch / 4; + row_shift = 0; + bias = bias_start_pos; + output_mult = out_mult_start_pos; + output_shift = out_shift_start_pos; + + while (row_count) + { + q31_t sum = 0; + q31_t sum_2 = 0; + q31_t sum_3 = 0; + q31_t sum_4 = 0; + if (bias) + { + sum = *bias++; + sum_2 = *bias++; + sum_3 = *bias++; + sum_4 = *bias++; + } + + uint16_t col_count = (kernel_x * kernel_y) / 2; + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + row_shift += 4; + + while (col_count) + { + /* General idea is to read 4 + 4 (input, kernel) pair and re-arrange them in the right order to + use in a SMLAD instruction . One run of this loop produces 4 partial outputs with 8 MACs. */ + /* Note: variable names can be improved here to align with rows and columns. */ + q31_t ip_a1, ip_a2, ip_b1, ip_b2, op_a, op_b, op_c; + /* Read 4 weights */ + ip_b1 = arm_nn_read_q7x4(row_pos); + ip_a1 = arm_nn_read_q7x4(row_pos + input_ch); + op_a = arm_nn_read_q15x2(col_pos); + op_b = arm_nn_read_q15x2(col_pos + input_ch); + + ip_a2 = __SXTB16(ip_b1); + ip_b1 = __SXTB16(__ROR(ip_b1, 8)); + + ip_b2 = __SXTB16(ip_a1); + ip_a1 = __SXTB16(__ROR(ip_a1, 8)); + + op_c = __PKHBT(op_b, op_a, 16); + op_a = __PKHTB(op_b, op_a, 16); + op_b = __PKHBT(ip_b2, ip_a2, 16); + sum = __SMLAD(op_c, op_b, sum); + + op_b = __PKHBT(ip_b1, ip_a1, 16); + sum_2 = __SMLAD(op_a, op_b, sum_2); + + op_a = arm_nn_read_q15x2(col_pos + 2); + op_b = arm_nn_read_q15x2(col_pos + input_ch + 2); + + op_c = __PKHBT(op_b, op_a, 16); + op_a = __PKHTB(op_b, op_a, 16); + op_b = __PKHTB(ip_a2, ip_b2, 16); + sum_3 = __SMLAD(op_c, op_b, sum_3); + + op_b = __PKHTB(ip_a1, ip_b1, 16); + sum_4 = __SMLAD(op_a, op_b, sum_4); + + row_pos += input_ch << 1; + col_pos += input_ch << 1; + col_count--; + } + + col_count = (kernel_x * kernel_y) & 0x1; + while (col_count) + { + sum += row_pos[0] * col_pos[0]; + sum_2 += row_pos[1] * col_pos[1]; + sum_3 += row_pos[2] * col_pos[2]; + sum_4 += row_pos[3] * col_pos[3]; + + row_pos += input_ch; + col_pos += input_ch; + + col_count--; + } + sum = arm_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + sum_2 = arm_nn_requantize(sum_2, *output_mult++, *output_shift++); + sum_2 += output_offset; + sum_2 = MAX(sum_2, output_activation_min); + sum_2 = MIN(sum_2, output_activation_max); + *output++ = (q7_t)sum_2; + sum_3 = arm_nn_requantize(sum_3, *output_mult++, *output_shift++); + sum_3 += output_offset; + sum_3 = MAX(sum_3, output_activation_min); + sum_3 = MIN(sum_3, output_activation_max); + *output++ = (q7_t)sum_3; + + sum_4 = arm_nn_requantize(sum_4, *output_mult++, *output_shift++); + sum_4 += output_offset; + sum_4 = MAX(sum_4, output_activation_min); + sum_4 = MIN(sum_4, output_activation_max); + *output++ = (q7_t)sum_4; + + row_count--; + } + + row_count = output_ch & 0x3; + while (row_count) + { + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + q31_t sum = 0; + if (bias) + { + sum = *bias++; + } + const uint16_t col_count = (kernel_x * kernel_y); + row_shift += 1; + + for (int i = 0; i < col_count; i++) + { + sum += row_pos[i * input_ch] * col_pos[i * input_ch]; + } + sum = arm_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + row_count--; + } + + // clear counter and pointers + col_buffer = col_buffer_start; + } + } +#endif +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + return arm_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + kernel, + bias_dims, + bias, + output_dims, + output); +#endif /* ARM_MATH_MVEI | ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +int32_t arm_depthwise_conv_s8_opt_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_MVEI) + (void)input_dims; + return (4 * CH_IN_BLOCK_MVE * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int8_t); +#elif defined(ARM_MATH_DSP) + return (input_dims->c * filter_dims->w * filter_dims->h) * sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c new file mode 100644 index 0000000..0404276 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c @@ -0,0 +1,337 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_u8_basic_ver1.c + * Description: u8 depthwise convolution function + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target : Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_u8_mult_4(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4]; + + out_buff[0] = 0; + out_buff[1] = 0; + out_buff[2] = 0; + out_buff[3] = 0; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; + + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * (kernel[ker_idx + 0 + mult_tile] + filter_offset); + out_buff[1] += in_val * (kernel[ker_idx + 1 + mult_tile] + filter_offset); + out_buff[2] += in_val * (kernel[ker_idx + 2 + mult_tile] + filter_offset); + out_buff[3] += in_val * (kernel[ker_idx + 3 + mult_tile] + filter_offset); + } + } + + if (bias != NULL) + { + out_buff[0] += bias[out_ch + 0 + mult_tile]; + out_buff[1] += bias[out_ch + 1 + mult_tile]; + out_buff[2] += bias[out_ch + 2 + mult_tile]; + out_buff[3] += bias[out_ch + 3 + mult_tile]; + } + out_buff[0] = arm_nn_requantize(out_buff[0], output_mult, output_shift); + out_buff[1] = arm_nn_requantize(out_buff[1], output_mult, output_shift); + out_buff[2] = arm_nn_requantize(out_buff[2], output_mult, output_shift); + out_buff[3] = arm_nn_requantize(out_buff[3], output_mult, output_shift); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (uint8_t)out_buff[0]; + output[out_idx++] = (uint8_t)out_buff[1]; + output[out_idx++] = (uint8_t)out_buff[2]; + output[out_idx++] = (uint8_t)out_buff[3]; + } + } + } + } +} + +static void depthwise_conv_u8_generic(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + (void)output_ch; + int i_out = 0; + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + acc_0 = 0; + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * (kernel[ker_idx_0] + filter_offset); + } + } + if (bias != NULL) + { + acc_0 += bias[idx_out_ch]; + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_requantize(acc_0, output_mult, output_shift); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } +} + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * available, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_shift Amount of right-shift for output + * @param[in] output_mult Output multiplier for requantization + * @return The function returns one of the following + * ARM_CMSIS_NN_SUCCESS - Successful operation + * + */ + +arm_cmsis_nn_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t output_shift, + const int32_t output_mult) +{ + (void)dilation_x; + (void)dilation_y; + + if (ch_mult % 4 == 0) + { + depthwise_conv_u8_mult_4(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + else + { + depthwise_conv_u8_generic(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c new file mode 100644 index 0000000..072e7ea --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s16.c @@ -0,0 +1,125 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_wrapper_s16.c + * Description: Wrapper API to select appropriate depthwise conv API based + * on dimensions. + * + * $Date: 6 July 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +#define USE_FAST_DW_CONV_FUNCTION(dw_conv_params, filter_dims, input_dims) \ + (dw_conv_params->ch_mult == 1 && dw_conv_params->dilation.w == 1 && dw_conv_params->dilation.h == 1 && \ + filter_dims->w * filter_dims->h * input_dims->c < 512) + +/* + * s16 Depthwise conv wrapper function + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_depthwise_conv_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *filter, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + arm_cmsis_nn_status status = ARM_CMSIS_NN_SUCCESS; + + if (USE_FAST_DW_CONV_FUNCTION(dw_conv_params, filter_dims, input_dims)) + { + status = arm_depthwise_conv_fast_s16(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + else + { + status = arm_depthwise_conv_s16(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + + /* Return to application */ + return status; +} + +int32_t arm_depthwise_conv_wrapper_s16_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + (void)dw_conv_params; + (void)input_dims; + (void)filter_dims; + (void)output_dims; + int32_t size = 0; + + if (USE_FAST_DW_CONV_FUNCTION(dw_conv_params, filter_dims, input_dims)) + { + size = arm_depthwise_conv_fast_s16_get_buffer_size(input_dims, filter_dims); + } + + return size; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c new file mode 100644 index 0000000..df2bb64 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c @@ -0,0 +1,139 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_wrapper_s8.c + * Description: Wrapper API to select appropriate depthwise conv API based + * on dimensions. + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * s8 Depthwise conv wrapper function + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_depthwise_conv_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *filter, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + arm_cmsis_nn_status status = ARM_CMSIS_NN_SUCCESS; + if (1 == dw_conv_params->ch_mult && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { +#if !defined(ARM_MATH_MVEI) + if ((filter_dims->w == 3) && (filter_dims->h == 3) && (dw_conv_params->padding.h <= 1) && + (dw_conv_params->padding.w <= 1)) + { + status = arm_depthwise_conv_3x3_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + else +#endif + { + status = arm_depthwise_conv_s8_opt(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + } + else + { + status = arm_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + + /* Return to application */ + return status; +} + +int32_t arm_depthwise_conv_wrapper_s8_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + (void)dw_conv_params; + int32_t size = 0; + + if (input_dims->c == output_dims->c && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { + size = arm_depthwise_conv_s8_opt_get_buffer_size(input_dims, filter_dims); + } + + return size; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c new file mode 100644 index 0000000..0a91889 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c @@ -0,0 +1,392 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Q7 depthwise separable convolution function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } + else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + */ + memcpy(pBuffer, (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel * dim_kernel) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + + asm volatile("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [sum] "+r"(sum), + [sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4), + [pB] "+r"(pB), + [pA] "+r"(pA) + : [colCnt] "r"(colCnt), [ch_im_in] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#else + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + asm volatile("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [sum] "+r"(sum), + [sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4), + [pB] "+r"(pB), + [pA] "+r"(pA) + : [colCnt] "r"(colCnt), [ch_im_in] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel * dim_kernel) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = arm_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel * dim_kernel); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } + + /* clear counter and pointers */ + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; + int conv_out; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c new file mode 100644 index 0000000..e85b01b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c @@ -0,0 +1,405 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Q7 depthwise separable convolution function (non-square shape) + * Refer function header for details + */ + +arm_cmsis_nn_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + + (void)bufferB; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + * + */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } + else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n" + : [sum] "+r"(sum), + [sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4), + [pB] "+r"(pB), + [pA] "+r"(pA) + : [colCnt] "r"(colCnt), [ch_im_in] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#else + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n" + : [sum] "+r"(sum), + [sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4), + [pB] "+r"(pB), + [pA] "+r"(pA) + : [colCnt] "r"(colCnt), [ch_im_in] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#endif /*ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel_x * dim_kernel_y) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = arm_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } + + // clear counter and pointers + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNConv group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c new file mode 100644 index 0000000..4804ba9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c @@ -0,0 +1,222 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_s8_core.c + * Description: Depthwise convolution on im2col buffers. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.4 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/* + * Depthwise conv on an im2col buffer where the input channel equals + * output channel. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + int32_t ch_per_loop = num_ch / 4; + + const int32_t *bias = output_bias; + int8_t *out_tmp = out; + + int32_t idx = 0; + + while (ch_per_loop > 0) + { + int32x4_t ip_0; + int32x4_t ip_1; + int32_t ker_loop = kernel_size / 3; + int32x4_t out_0 = vldrwq_s32(bias); + int32x4_t out_1 = out_0; + bias += 4; + + const int32_t offset = idx * 4; + const int8_t *row_0 = row + offset; + const int16_t *col_0 = col + offset; + const int16_t *col_1 = col + kernel_size * num_ch + offset; + + int32x4_t ker_0 = vldrbq_s32(row_0); + + while (ker_loop > 0) + { + const int8_t *row_1 = row_0 + num_ch; + const int8_t *row_2 = row_0 + 2 * num_ch; + const int32x4_t ker_1 = vldrbq_s32(row_1); + const int32x4_t ker_2 = vldrbq_s32(row_2); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_0); + out_1 += vmulq_s32(ip_1, ker_0); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_1); + out_1 += vmulq_s32(ip_1, ker_1); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_2); + out_1 += vmulq_s32(ip_1, ker_2); + row_0 += 3 * num_ch; + + ker_0 = vldrbq_s32(row_0); + ker_loop--; + } + + idx++; + /* Handle tail kernel elements */ + ker_loop = kernel_size - ((kernel_size / 3) * 3); + while (ker_loop > 0) + { + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + + out_0 += vmulq_s32(ip_0, ker_0); + out_1 += vmulq_s32(ip_1, ker_0); + + col_0 += num_ch; + col_1 += num_ch; + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + + row_0 += num_ch; + ker_0 = vldrbq_s32(row_0); + ker_loop--; + } + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + vstrbq_s32(out_tmp, out_0); + + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_s32(out_tmp + num_ch, out_1); + + out_tmp += 4; + ch_per_loop--; + } + + int32_t tail_ch = num_ch & 3; + if (tail_ch != 0) + { + int32_t ch_idx = (num_ch & ~3); + int32x4_t col_0_sum; + int32x4_t col_1_sum; + + const int32_t single_buffer_size = kernel_size * num_ch; + for (int i = 0; i < tail_ch; i++) + { + const int16_t *col_pos_0 = col + ch_idx; + const int16_t *col_pos_1 = col_pos_0 + single_buffer_size; + + const int8_t *row_pos = row + ch_idx; + int32_t sum_0 = bias[i]; + int32_t sum_1 = bias[i]; + + for (int j = 0; j < kernel_size; j++) + { + const int8_t row_val = row_pos[j * num_ch]; + sum_0 += row_val * col_pos_0[j * num_ch]; + sum_1 += row_val * col_pos_1[j * num_ch]; + } + col_0_sum[i] = sum_0; + col_1_sum[i] = sum_1; + + ch_idx++; + } + const mve_pred16_t p = vctp32q((uint32_t)tail_ch); + const int32x4_t mult = vldrwq_z_s32(out_mult, p); + const int32x4_t shift = vldrwq_z_s32(out_shift, p); + + col_0_sum = arm_requantize_mve_32x4(col_0_sum, mult, shift); + col_1_sum = arm_requantize_mve_32x4(col_1_sum, mult, shift); + + col_0_sum = vaddq_n_s32(col_0_sum, out_offset); + col_0_sum = vmaxq_s32(col_0_sum, vdupq_n_s32(activation_min)); + col_0_sum = vminq_s32(col_0_sum, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out_tmp, col_0_sum, p); + + col_1_sum = vaddq_n_s32(col_1_sum, out_offset); + col_1_sum = vmaxq_s32(col_1_sum, vdupq_n_s32(activation_min)); + col_1_sum = vminq_s32(col_1_sum, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out_tmp + num_ch, col_1_sum, p); + + out_tmp += tail_ch; + } + + return out_tmp + num_ch; +#else + (void)row; + (void)col; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)kernel_size; + (void)output_bias; + (void)out; + return NULL; +#endif +} + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c new file mode 100644 index 0000000..5c95485 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c @@ -0,0 +1,190 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution. + * + * Refer to header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; + + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + pA2 = read_and_pad(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inA11, inA12; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + } + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c new file mode 100644 index 0000000..29043c8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c @@ -0,0 +1,141 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with re-ordered input. + * + * Refer to header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ + +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad_reordered(pA, &inA11, &inA12); + pA2 = read_and_pad_reordered(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c new file mode 100644 index 0000000..62ee822 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c @@ -0,0 +1,249 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s8_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 14. December 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if !defined(ARM_MATH_MVEI) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + q31_t ch_1_out_0 = 0; + q31_t ch_1_out_1 = 0; + /* Init accumulator with bias for channel N and N + 1 */ + if (bias) + { + ch_0_out_0 = *bias; + ch_0_out_1 = *bias++; + ch_1_out_0 = *bias; + ch_1_out_1 = *bias++; + } + +#if defined(ARM_MATH_DSP) + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + ip_a1 = read_and_pad(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; +#else + uint16_t col_count = num_col_a; +#endif + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + + /* load the bias */ + if (bias) + { + ch_0_out_0 = *bias; + ch_0_out_1 = *bias++; + } + +#if defined(ARM_MATH_DSP) + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; +#else + uint16_t col_count = num_col_a; +#endif + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c new file mode 100644 index 0000000..9eed28f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c @@ -0,0 +1,184 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 16 August 2022 + * $Revision: V.2.0.7 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/* + * s8 General matrix multiplication function with per-channel requantization for upto 4 column batches. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + (void)row_offset; + if (col_batches == 4) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t row_len_tmp = row_len; + const int8_t *ip_r0 = input_row + (i_out_ch * row_len); + const int8_t *ip_c0 = input_col; + const int8_t *ip_c1 = input_col + row_len; + const int8_t *ip_c2 = input_col + (2 * row_len); + const int8_t *ip_c3 = input_col + (3 * row_len); + + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + int32_t acc_3 = 0; + const int32_t row_loop_cnt = (row_len + 7) / 8; + + for (int i_row_loop = 0; i_row_loop < row_loop_cnt; i_row_loop++) + { + mve_pred16_t p = vctp16q((uint32_t)row_len_tmp); + const int16x8_t offset = vdupq_x_n_s16(col_offset, p); + row_len_tmp -= 8; + + int16x8_t c0 = vldrbq_s16(ip_c0); + ip_c0 += 8; + c0 = vaddq_s16(c0, offset); + + int16x8_t c1 = vldrbq_s16(ip_c1); + ip_c1 += 8; + c1 = vaddq_s16(c1, offset); + + int16x8_t c2 = vldrbq_s16(ip_c2); + ip_c2 += 8; + c2 = vaddq_s16(c2, offset); + + int16x8_t c3 = vldrbq_s16(ip_c3); + ip_c3 += 8; + c3 = vaddq_s16(c3, offset); + + int16x8_t r0 = vldrbq_z_s16(ip_r0, p); + ip_r0 += 8; + + acc_0 = vmladavaq_p_s16(acc_0, r0, c0, p); + acc_1 = vmladavaq_p_s16(acc_1, r0, c1, p); + acc_2 = vmladavaq_p_s16(acc_2, r0, c2, p); + acc_3 = vmladavaq_p_s16(acc_3, r0, c3, p); + } + + int32x4_t res = {acc_0, acc_1, acc_2, acc_3}; + if (bias) + { + res = vaddq_n_s32(res, bias[i_out_ch]); + } + res = arm_requantize_mve(res, output_mult[i_out_ch], output_shift[i_out_ch]); + res = vaddq_n_s32(res, out_offset); + + res = vmaxq_s32(res, vdupq_n_s32(activation_min)); + res = vminq_s32(res, vdupq_n_s32(activation_max)); + + const uint32x4_t scatter_offset = {0, output_ch, output_ch * 2, output_ch * 3}; + vstrbq_scatter_offset_s32(&out[i_out_ch], scatter_offset, res); + } + out += 4 * output_ch; + } + else + { + for (int i_col_batch = (col_batches & ~0x3); i_col_batch < (col_batches & 0x3); i_col_batch++) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t row_len_tmp = row_len; + + const int8_t *ip_r0 = input_row + (i_out_ch * row_len); + const int8_t *ip_c0 = input_col + (i_col_batch * row_len); + int32_t acc_0 = 0; + const int32_t row_loop_cnt = (row_len + 7) / 8; + + for (int i_row_loop = 0; i_row_loop < row_loop_cnt; i_row_loop++) + { + const mve_pred16_t p = vctp16q((uint32_t)row_len_tmp); + const int16x8_t offset = vdupq_x_n_s16(col_offset, p); + row_len_tmp -= 8; + + int16x8_t c0 = vldrbq_s16(ip_c0); + ip_c0 += 8; + c0 = vaddq_s16(c0, offset); + + int16x8_t r0 = vldrbq_z_s16(ip_r0, p); + ip_r0 += 8; + acc_0 = vmladavaq_p_s16(acc_0, r0, c0, p); + } + + if (bias) + { + acc_0 += bias[i_out_ch]; + } + acc_0 = arm_nn_requantize(acc_0, output_mult[i_out_ch], output_shift[i_out_ch]); + acc_0 += out_offset; + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + out[i_out_ch] = (q7_t)acc_0; + } + out += output_ch; + } + } + return out; + +#else + (void)input_row; + (void)input_col; + (void)output_ch; + (void)col_batches; + (void)output_shift; + (void)output_mult; + (void)out_offset; + (void)col_offset; + (void)row_offset; + (void)activation_min; + (void)activation_max; + (void)row_len; + (void)bias; + (void)out; + return NULL; +#endif +} + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c new file mode 100644 index 0000000..0987a31 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c @@ -0,0 +1,181 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * @brief Mixed Q15-Q7 fully-connected layer function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad(pB, &inM11, &inM12); + pB2 = read_and_pad(pB2, &inM21, &inM22); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /*adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_CMSIS_NN_SUCCESS */ + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c new file mode 100644 index 0000000..f4872c1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c @@ -0,0 +1,345 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * Mixed Q15-Q7 opt fully-connected layer function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } + +#else + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile( + "COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [sum] "+r"(sum), [sum2] "+r"(sum2), [sum3] "+r"(sum3), [sum4] "+r"(sum4), [pB] "+r"(pB), [pA] "+r"(pA) + : [colCnt] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#else + asm volatile( + "COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [sum] "+r"(sum), [sum2] "+r"(sum2), [sum3] "+r"(sum3), [sum4] "+r"(sum4), [pB] "+r"(pB), [pA] "+r"(pA) + : [colCnt] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_CMSIS_NN_SUCCESS */ + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c new file mode 100644 index 0000000..6ea0b27 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c @@ -0,0 +1,182 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * Q15 opt fully-connected layer function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + const q15_t *pB2 = pB + dim_vec; + q15_t *pO = pOut; + const q15_t *pA; + const q15_t *pBias = bias; + uint16_t rowCnt = num_of_rows >> 1; + + /* this loop loops over different output */ + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV1, inM1, inM2; + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = arm_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = arm_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /* adjust the pointers and counters */ + pB = pB + dim_vec; + rowCnt--; + } + + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inM1; + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + + sum += inV * inM; + + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c new file mode 100644 index 0000000..82887fa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c @@ -0,0 +1,288 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * @brief Q15 opt fully-connected layer function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + q15_t *pO = pOut; + const q15_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV, inM11, sum); + inM12 = arm_nn_read_q15x2_ia(&pB); + sum2 = __SMLAD(inV, inM12, sum2); + inM13 = arm_nn_read_q15x2_ia(&pB); + sum3 = __SMLAD(inV, inM13, sum3); + inM14 = arm_nn_read_q15x2_ia(&pB); + sum4 = __SMLAD(inV, inM14, sum4); + colCnt--; + } + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + + asm volatile( + "COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r0, [%[pB]], #16\n" + "smlad %[sum], r4, r0, %[sum]\n" + "ldr.w r1, [%[pB] , #-12]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r2, [%[pB] , #-8]\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "ldr.w r3, [%[pB] , #-4]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [sum] "+r"(sum), [sum2] "+r"(sum2), [sum3] "+r"(sum3), [sum4] "+r"(sum4), [pB] "+r"(pB), [pA] "+r"(pA) + : [colCnt] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB++; + q15_t inM3 = *pB++; + q15_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM1, inM2; + + inM1 = arm_nn_read_q15x2_ia(&pB); + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM1, sum); + + inM2 = arm_nn_read_q15x2_ia(&pB); + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM2, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_CMSIS_NN_SUCCESS */ + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c new file mode 100644 index 0000000..de67bb2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c @@ -0,0 +1,185 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * Q7 basic fully-connected layer function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q7_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA; + uint16_t rowCnt = num_of_rows >> 1; + + /* expand the vector into the buffer */ + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad_reordered(pB, &inM11, &inM12); + pB2 = read_and_pad_reordered(pB2, &inM21, &inM22); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum2 >> out_shift), 8)); + + /* adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + uint16_t colCnt = dim_vec >> 2; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad_reordered(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + (void)vec_buffer; + int i, j; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t)__SSAT((ip_out >> out_shift), 8); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_CMSIS_NN_SUCCESS */ + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c new file mode 100644 index 0000000..0c8eae6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c @@ -0,0 +1,411 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * Q7 opt fully-connected layer function + * Refer function header for details + */ + +arm_cmsis_nn_status arm_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q7_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA; + uint16_t rowCnt = num_of_rows >> 2; + + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } +#else + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile( + "COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [sum] "+r"(sum), [sum2] "+r"(sum2), [sum3] "+r"(sum3), [sum4] "+r"(sum4), [pB] "+r"(pB), [pA] "+r"(pA) + : [colCnt] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#else + asm volatile( + "COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [sum] "+r"(sum), [sum2] "+r"(sum2), [sum3] "+r"(sum3), [sum4] "+r"(sum4), [pB] "+r"(pB), [pA] "+r"(pA) + : [colCnt] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum2 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum3 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum4 >> out_shift), 8)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad_reordered(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)vec_buffer; + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t)__SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_CMSIS_NN_SUCCESS */ + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c new file mode 100644 index 0000000..8e43b71 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c @@ -0,0 +1,101 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_s16 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S16 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_fully_connected_s16(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + (void)bias_dims; + (void)ctx; + (void)fc_params->filter_offset; + + int32_t batch_cnt = input_dims->n; + + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(quant_params->multiplier); + + while (batch_cnt) + { + arm_nn_vec_mat_mult_t_s16(input, + kernel, + bias, + output, + reduced_multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + + return (ARM_CMSIS_NN_SUCCESS); +} + +int32_t arm_fully_connected_s16_get_buffer_size(const cmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c new file mode 100644 index 0000000..08f100a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c @@ -0,0 +1,103 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_s8 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: 19 April 2022 + * $Revision: V.4.0.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S8 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ + +arm_cmsis_nn_status arm_fully_connected_s8(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)bias_dims; + (void)ctx; + (void)fc_params->filter_offset; + + int32_t batch_cnt = input_dims->n; + + while (batch_cnt) + { + arm_nn_vec_mat_mult_t_s8(input, + kernel, + bias, + output, + fc_params->input_offset, + 0, + fc_params->output_offset, + quant_params->multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max, + 1L); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + return (ARM_CMSIS_NN_SUCCESS); +} + +int32_t arm_fully_connected_s8_get_buffer_size(const cmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c new file mode 100644 index 0000000..7875682 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c @@ -0,0 +1,89 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_accumulate_q7_to_q15.c + * Description: Accumulate q7 vector into q15 one. + * + * $Date: 20 July 2021 + * $Revision: V.1.1.2 + * + * pSrc Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void arm_nn_accumulate_q7_to_q15(q15_t *pDst, const q7_t *pSrc, uint32_t length) +{ + q15_t *pCnt = pDst; + const q7_t *pV = pSrc; + int32_t count = length; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + q31_t v1, v2, vo1, vo2; + count = length >> 2; + q31_t in; + + while (count > 0l) + { + q31_t value = arm_nn_read_q7x4_ia(&pV); + v1 = __SXTB16(__ROR((uint32_t)value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + vo2 = (q31_t)__PKHTB(v1, v2, 16); + vo1 = (q31_t)__PKHBT(v2, v1, 16); +#else + vo1 = (q31_t)__PKHTB(v1, v2, 16); + vo2 = (q31_t)__PKHBT(v2, v1, 16); +#endif + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + count--; + } + count = length & 0x3; +#endif + while (count > 0l) + { + *pCnt++ += *pV++; + count--; + } +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c new file mode 100644 index 0000000..7ff743d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c @@ -0,0 +1,85 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_add_q7.c + * Description: Non saturating addition of elements of a q7 vector. + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_tables.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void arm_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size) +{ + uint32_t block_count; + q31_t result = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Loop unrolling: Compute 4 outputs at a time */ + block_count = block_size >> 2U; + + while (block_count > 0U) + { + const int32_t mult_q15x2 = (1UL << 16) | 1UL; + q31_t in_q7x4 = arm_nn_read_q7x4_ia(&input); + q31_t temp_q15x2 = __SXTAB16(__SXTB16(in_q7x4), __ROR((uint32_t)in_q7x4, 8)); + + result = __SMLAD(temp_q15x2, mult_q15x2, result); + + /* Decrement loop counter */ + block_count--; + } + + /* Loop unrolling: Compute remaining outputs */ + block_count = block_size & 0x3; +#else + block_count = block_size; +#endif + while (block_count > 0U) + { + /* Add and store result in destination buffer. */ + result += *input++; + + /* Decrement loop counter */ + block_count--; + } + + *output = result; +} + +/** + * @} end of NNBasicMath group + */ +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c new file mode 100644 index 0000000..7d12144 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c @@ -0,0 +1,173 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2020, 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_nt_t_padded_s8.c + * Description: Depthwise convolution with padded matrices. + * + * $Date: 27. July 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M processors with MVE extension + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of transposed rhs matrix with 4 lhs matrices. One or more of the rhs matrices are padded. + * Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +arm_cmsis_nn_status arm_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const int32_t active_ch, + const int32_t total_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (active_ch + 3) / 4; + const int32_t *bias = output_bias; + uint32_t num_ch_to_process = active_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; + num_ch_to_process -= 4, out += 4, offset += 4, i_loop_cnt++) + { + int32x4_t out_0 = vdupq_n_s32(0); + if (bias) + { + out_0 = vldrwq_s32(bias); + bias += 4; + } + int32x4_t out_1 = out_0; + int32x4_t out_2 = out_0; + int32x4_t out_3 = out_0; + + const int8_t *rhs_0 = rhs + offset; + const int8_t *lhs_0 = lhs + offset; + const int8_t *lhs_1 = lhs + row_x_col * CH_IN_BLOCK_MVE + offset; + const int8_t *lhs_2 = lhs + (row_x_col * CH_IN_BLOCK_MVE * 2) + offset; + const int8_t *lhs_3 = lhs + (row_x_col * CH_IN_BLOCK_MVE * 3) + offset; + + for (int i_row_x_col = 0; i_row_x_col < row_x_col; i_row_x_col++) + { + const int32x4_t ker_0 = vldrbq_s32(rhs_0); + + int32x4_t ip_0 = vldrbq_s32(lhs_0); + ip_0 = vaddq_n_s32(ip_0, input_offset); + out_0 += vmulq_s32(ip_0, ker_0); + + int32x4_t ip_1 = vldrbq_s32(lhs_1); + ip_1 = vaddq_n_s32(ip_1, input_offset); + out_1 += vmulq_s32(ip_1, ker_0); + + int32x4_t ip_2 = vldrbq_s32(lhs_2); + ip_2 = vaddq_n_s32(ip_2, input_offset); + out_2 += vmulq_s32(ip_2, ker_0); + + int32x4_t ip_3 = vldrbq_s32(lhs_3); + ip_3 = vaddq_n_s32(ip_3, input_offset); + + out_3 += vmulq_s32(ip_3, ker_0); + + lhs_0 += CH_IN_BLOCK_MVE; + lhs_1 += CH_IN_BLOCK_MVE; + lhs_2 += CH_IN_BLOCK_MVE; + lhs_3 += CH_IN_BLOCK_MVE; + + rhs_0 += total_ch; + } + + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + mve_pred16_t p = vctp32q(num_ch_to_process); + vstrbq_p_s32(out, out_0, p); + + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + total_ch, out_1, p); + + out_2 = arm_requantize_mve_32x4(out_2, mult, shift); + out_2 = vaddq_n_s32(out_2, out_offset); + out_2 = vmaxq_s32(out_2, vdupq_n_s32(activation_min)); + out_2 = vminq_s32(out_2, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 2 * total_ch, out_2, p); + + out_3 = arm_requantize_mve_32x4(out_3, mult, shift); + out_3 = vaddq_n_s32(out_3, out_offset); + out_3 = vmaxq_s32(out_3, vdupq_n_s32(activation_min)); + out_3 = vminq_s32(out_3, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 3 * total_ch, out_3, p); + } + + return ARM_CMSIS_NN_SUCCESS; + +#else + (void)lhs; + (void)rhs; + (void)input_offset; + (void)active_ch; + (void)total_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return ARM_CMSIS_NN_NO_IMPL_ERROR; +#endif +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c new file mode 100644 index 0000000..503aa64 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s16.c @@ -0,0 +1,175 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_nt_t_s16.c + * Description: Depthwise convolution on matrices with no padding. + * + * $Date: 6 July 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M processors with MVE extension + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of rhs matrix with 4 lhs matrices with no padding. Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ +int16_t *arm_nn_depthwise_conv_nt_t_s16(const int16_t *lhs, + const q7_t *rhs, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int64_t *const output_bias, + int16_t *out) +{ +#if defined(ARM_MATH_MVEI) + + const int64_t *bias = output_bias; + int32_t loop_count = (num_ch + 3) / 4; + uint32_t num_ch_to_process = num_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; + num_ch_to_process -= 4, offset += 4, out += 4, i_loop_cnt++) + { + const int8_t *rhs_0 = rhs + offset; + const int16_t *lhs_0 = lhs + offset; + const int16_t *lhs_1 = lhs + row_x_col * num_ch + offset; + const int16_t *lhs_2 = lhs + (row_x_col * num_ch * 2) + offset; + const int16_t *lhs_3 = lhs + (row_x_col * num_ch * 3) + offset; + + int32x4_t out_0 = vdupq_n_s32(0); + int32x4_t out_1 = vdupq_n_s32(0); + int32x4_t out_2 = vdupq_n_s32(0); + int32x4_t out_3 = vdupq_n_s32(0); + + for (int i_row_x_col = 0; i_row_x_col < row_x_col; i_row_x_col++) + { + const int32x4_t ker_0 = vldrbq_s32(rhs_0); + + int32x4_t ip_0 = vldrhq_s32(lhs_0); + out_0 += vmulq_s32(ip_0, ker_0); + + int32x4_t ip_1 = vldrhq_s32(lhs_1); + out_1 += vmulq_s32(ip_1, ker_0); + + int32x4_t ip_2 = vldrhq_s32(lhs_2); + out_2 += vmulq_s32(ip_2, ker_0); + + int32x4_t ip_3 = vldrhq_s32(lhs_3); + out_3 += vmulq_s32(ip_3, ker_0); + + lhs_0 += num_ch; + lhs_1 += num_ch; + lhs_2 += num_ch; + lhs_3 += num_ch; + + rhs_0 += num_ch; + } + + for (int i_requantize = 0; i_requantize < 4; i_requantize++) + { + int32_t reduced_multiplier = REDUCE_MULTIPLIER(out_mult[i_requantize]); + int32_t shift = out_shift[i_requantize]; + int64_t in_requantize_0 = (int64_t)out_0[i_requantize]; + int64_t in_requantize_1 = (int64_t)out_1[i_requantize]; + int64_t in_requantize_2 = (int64_t)out_2[i_requantize]; + int64_t in_requantize_3 = (int64_t)out_3[i_requantize]; + + if (bias) + { + in_requantize_0 += *bias; + in_requantize_1 += *bias; + in_requantize_2 += *bias; + in_requantize_3 += *bias; + bias++; + } + + out_0[i_requantize] = arm_nn_requantize_s64(in_requantize_0, reduced_multiplier, shift); + out_1[i_requantize] = arm_nn_requantize_s64(in_requantize_1, reduced_multiplier, shift); + out_2[i_requantize] = arm_nn_requantize_s64(in_requantize_2, reduced_multiplier, shift); + out_3[i_requantize] = arm_nn_requantize_s64(in_requantize_3, reduced_multiplier, shift); + } + + mve_pred16_t p = vctp32q(num_ch_to_process); + + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + vstrhq_p_s32(out, out_0, p); + + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrhq_p_s32(out + num_ch, out_1, p); + + out_2 = vmaxq_s32(out_2, vdupq_n_s32(activation_min)); + out_2 = vminq_s32(out_2, vdupq_n_s32(activation_max)); + vstrhq_p_s32(out + 2 * num_ch, out_2, p); + + out_3 = vmaxq_s32(out_3, vdupq_n_s32(activation_min)); + out_3 = vminq_s32(out_3, vdupq_n_s32(activation_max)); + vstrhq_p_s32(out + 3 * num_ch, out_3, p); + + out_mult += 4; + out_shift += 4; + } + const int tail_ch = num_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + + return out + (3 * num_ch); +#else + (void)lhs; + (void)rhs; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c new file mode 100644 index 0000000..b8d0871 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c @@ -0,0 +1,173 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2020, 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_nt_t_s8.c + * Description: Depthwise convolution on matrices with no padding. + * + * $Date: 27. July 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M processors with MVE extension. + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of rhs matrix with 4 lhs matrices with no padding. Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const int32_t active_ch, + const int32_t total_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + const int32_t *bias = output_bias; + int32_t loop_count = (active_ch + 3) / 4; + uint32_t num_ch_to_process = active_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; + num_ch_to_process -= 4, offset += 4, out += 4, i_loop_cnt++) + { + int32x4_t out_0 = vdupq_n_s32(0); + if (bias) + { + out_0 = vldrwq_s32(bias); + bias += 4; + } + int32x4_t out_1 = out_0; + int32x4_t out_2 = out_0; + int32x4_t out_3 = out_0; + + const int8_t *rhs_0 = rhs + offset; + const int8_t *lhs_0 = lhs + offset; + const int8_t *lhs_1 = lhs + row_x_col * CH_IN_BLOCK_MVE + offset; + const int8_t *lhs_2 = lhs + (row_x_col * CH_IN_BLOCK_MVE * 2) + offset; + const int8_t *lhs_3 = lhs + (row_x_col * CH_IN_BLOCK_MVE * 3) + offset; + int32x4_t ker_sum = vdupq_n_s32(0); + + for (int i_row_x_col = 0; i_row_x_col < row_x_col; i_row_x_col++) + { + const int32x4_t ker_0 = vldrbq_s32(rhs_0); + ker_sum = vaddq_s32(ker_sum, ker_0); + + int32x4_t ip_0 = vldrbq_s32(lhs_0); + out_0 += vmulq_s32(ip_0, ker_0); + + int32x4_t ip_1 = vldrbq_s32(lhs_1); + out_1 += vmulq_s32(ip_1, ker_0); + + int32x4_t ip_2 = vldrbq_s32(lhs_2); + out_2 += vmulq_s32(ip_2, ker_0); + + int32x4_t ip_3 = vldrbq_s32(lhs_3); + out_3 += vmulq_s32(ip_3, ker_0); + + lhs_0 += CH_IN_BLOCK_MVE; + lhs_1 += CH_IN_BLOCK_MVE; + lhs_2 += CH_IN_BLOCK_MVE; + lhs_3 += CH_IN_BLOCK_MVE; + + rhs_0 += total_ch; + } + + ker_sum = vmulq_n_s32(ker_sum, input_offset); + out_0 = ker_sum + out_0; + out_1 = ker_sum + out_1; + out_2 = ker_sum + out_2; + out_3 = ker_sum + out_3; + + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + mve_pred16_t p = vctp32q(num_ch_to_process); + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out, out_0, p); + + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + total_ch, out_1, p); + + out_2 = arm_requantize_mve_32x4(out_2, mult, shift); + out_2 = vaddq_n_s32(out_2, out_offset); + out_2 = vmaxq_s32(out_2, vdupq_n_s32(activation_min)); + out_2 = vminq_s32(out_2, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 2 * total_ch, out_2, p); + + out_3 = arm_requantize_mve_32x4(out_3, mult, shift); + out_3 = vaddq_n_s32(out_3, out_offset); + out_3 = vmaxq_s32(out_3, vdupq_n_s32(activation_min)); + out_3 = vminq_s32(out_3, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 3 * total_ch, out_3, p); + } + + return ARM_CMSIS_NN_SUCCESS; +#else + (void)lhs; + (void)rhs; + (void)input_offset; + (void)active_ch; + (void)total_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return ARM_CMSIS_NN_NO_IMPL_ERROR; +#endif +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c new file mode 100644 index 0000000..67685df --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c @@ -0,0 +1,155 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mul_core_1x_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 22 Aug 2022 + * $Revision: V.3.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 1 row + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int32_t skipped_row_elements, + const int8_t *row_base_ref, + const int8_t *col_base_ref, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output) +{ +#if defined(ARM_MATH_MVEI) + const int8_t *col_base = col_base_ref; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + + int32_t acc[4]; + for (int i = 0; i < out_ch; i++) + { + int32_t acc_n0 = 0; + const int8_t *row_base = row_base_ref; + + int32_t sum_tmp = 0; + +#if defined(ARM_MATH_AUTOVECTORIZE) + for (int j = 0; j < row_elements; j++) + { + int32_t col = col_base[j]; + sum_tmp += col; + acc_n0 += row_base[j] * col; + } +#else + __ASM volatile(" vldrb.8 q0, [%[col]], #16 \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vaddva.s8 %[sum], q0 \n" + " vldrb.8 q1, [%[row0]], #16 \n" + " vmladava.s8 %[out0], q0, q1 \n" + " vldrb.8 q0, [%[col]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [col] "+r"(col_base), [sum] "+Te"(sum_tmp), [row0] "+r"(row_base), [out0] "+Te"(acc_n0) + : [cnt] "r"(row_elements) + : "q0", "q1", "memory", "r14"); +#endif + + sum_tmp *= conv_params->input_offset; + acc_n0 += sum_tmp; + + const int32_t index = i & 0x3; + acc[index] = acc_n0; + + if (index == 3) + { + int32x4_t res = vldrwq_s32(acc); + if (bias) + { + res = vaddq_s32(res, vldrwq_s32(bias)); + bias += 4; + } + res = arm_requantize_mve_32x4(res, vldrwq_s32(output_mult), vldrwq_s32(output_shift)); + output_mult += 4; + output_shift += 4; + res = vaddq_n_s32(res, out_offset); + res = vmaxq_s32(res, vdupq_n_s32(out_activation_min)); + res = vminq_s32(res, vdupq_n_s32(out_activation_max)); + vstrbq_s32(output, res); + output += 4; + } + col_base = col_base_ref + (i + 1) * (row_elements + skipped_row_elements); + } + // Handle left over elements + for (int i = 0; i < (out_ch & 0x3); i++) + { + int32_t acc_n0 = acc[i]; + if (bias) + { + acc_n0 += bias[i]; + } + acc_n0 = arm_nn_requantize(acc_n0, output_mult[i], output_shift[i]); + acc_n0 += conv_params->output_offset; + acc_n0 = MAX(acc_n0, conv_params->activation.min); + acc_n0 = MIN(acc_n0, conv_params->activation.max); + *output++ = (q7_t)acc_n0; + } + +#else + (void)row_elements; + (void)skipped_row_elements; + (void)row_base_ref; + (void)col_base_ref; + (void)out_ch; + (void)conv_params; + (void)quant_params; + (void)bias; + (void)output; +#endif + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c new file mode 100644 index 0000000..b0ea228 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c @@ -0,0 +1,153 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mul_core_4x_s8.c + * Description: General matrix multiplication function for MVE extension + * + * $Date: 22. Aug 2022 + * $Revision: V.3.1.0 + * + * Target Processor: Cortex-M processors + * -------------------------------------------------------------------- */ +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 4 rows and one column + * + * Refer header file for details. + * + */ + +int8_t *arm_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base_ref, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output) +{ + +#if defined(ARM_MATH_MVEI) + for (int i = 0; i < out_ch; i++) + { + int32_t acc_n0 = 0; + int32_t acc_n1 = 0; + int32_t acc_n2 = 0; + int32_t acc_n3 = 0; + + const int8_t *ip_row_0 = row_base; + const int8_t *ip_row_1 = row_base + offset; + const int8_t *ip_row_2 = row_base + (2 * offset); + const int8_t *ip_row_3 = row_base + (3 * offset); + const int8_t *col_base = col_base_ref + i * row_elements; + int32_t sum_tmp = 0; + +#if defined(ARM_MATH_AUTOVECTORIZE) + for (int j = 0; j < row_elements; j++) + { + int32_t col = col_base[j]; + sum_tmp += col; + acc_n0 += ip_row_0[j] * col; + acc_n1 += ip_row_1[j] * col; + acc_n2 += ip_row_2[j] * col; + acc_n3 += ip_row_3[j] * col; + } +#else + __ASM volatile(" vldrb.8 q0, [%[col]], #16 \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vaddva.s8 %[sum], q0 \n" + " vldrb.8 q1, [%[row0]], #16 \n" + " vmladava.s8 %[out0], q0, q1 \n" + " vldrb.8 q2, [%[row1]], #16 \n" + " vmladava.s8 %[out1], q0, q2 \n" + " vldrb.8 q3, [%[row2]], #16 \n" + " vmladava.s8 %[out2], q0, q3 \n" + " vldrb.8 q4, [%[row3]], #16 \n" + " vmladava.s8 %[out3], q0, q4 \n" + " vldrb.8 q0, [%[col]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [col] "+r"(col_base), + [sum] "+Te"(sum_tmp), + [row0] "+r"(ip_row_0), + [row1] "+r"(ip_row_1), + [row2] "+r"(ip_row_2), + [row3] "+r"(ip_row_3), + [out0] "+Te"(acc_n0), + [out1] "+Te"(acc_n1), + [out2] "+Te"(acc_n2), + [out3] "+Te"(acc_n3) + : [cnt] "r"(row_elements) + : "q0", "q1", "q2", "q3", "q4", "memory", "r14"); +#endif + + int32x4_t res = {acc_n0, acc_n1, acc_n2, acc_n3}; + sum_tmp *= conv_params->input_offset; + if (bias) + { + sum_tmp += bias[i]; + } + res = vaddq_n_s32(res, sum_tmp); + + res = arm_requantize_mve(res, quant_params->multiplier[i], quant_params->shift[i]); + res = vaddq_n_s32(res, conv_params->output_offset); + + res = vmaxq_s32(res, vdupq_n_s32(conv_params->activation.min)); + res = vminq_s32(res, vdupq_n_s32(conv_params->activation.max)); + + const uint32x4_t scatter_offset = {0, (uint32_t)out_ch, (uint32_t)out_ch * 2, (uint32_t)out_ch * 3}; + vstrbq_scatter_offset_s32(output, scatter_offset, res); + output++; + } + + return output + (3 * out_ch); +#else + (void)row_elements; + (void)offset; + (void)row_base; + (void)col_base_ref; + (void)out_ch; + (void)conv_params; + (void)quant_params; + (void)bias; + (void)output; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c new file mode 100644 index 0000000..b93e078 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c @@ -0,0 +1,254 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 12 August 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q15_t *arm_nn_mat_mult_kernel_s16(const q7_t *input_a, + const q15_t *input_b, + const int32_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int16_t activation_min, + const int16_t activation_max, + const int32_t num_col_a, + const int64_t *const output_bias, + q15_t *out_0) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* set up the second output pointers */ + q15_t *out_1 = out_0 + output_ch; + const int64_t *bias = output_bias; + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator for channel N and N + 1 */ + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + q31_t ch_1_out_0 = 0; + q31_t ch_1_out_1 = 0; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + ip_a1 = read_and_pad(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_0_out_0 + *bias; + ch_0_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_0_out_1 + *bias++; + ch_0_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + out_mult++; + } + else + { + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + out_mult++; + } + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q15_t)ch_0_out_0; + + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q15_t)ch_0_out_1; + out_shift++; + + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_1_out_0 + *bias; + ch_1_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_1_out_1 + *bias++; + ch_1_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + out_mult++; + } + else + { + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + out_mult++; + } + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q15_t)ch_1_out_0; + + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q15_t)ch_1_out_1; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_0_out_0 + *bias; + ch_0_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_0_out_1 + *bias++; + ch_0_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + } + else + { + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + } + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q15_t)ch_0_out_0; + + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q15_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c new file mode 100644 index 0000000..552a4e1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c @@ -0,0 +1,586 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_s8_nt_t_s8 + * Description: Matrix multiplication support function with the right-hand-side (rhs) matrix transposed + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication with the right-hand-side matrix transposed + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max) +{ +#if defined(ARM_MATH_DSP) + const int32_t off0 = rhs_cols - 4; + + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + res11 = __SMLAD(val0, val4, res11); + } + + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = arm_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = arm_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + } + + // Left-over accumulations + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#else + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = arm_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = arm_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#endif + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c new file mode 100644 index 0000000..ec58c86 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c @@ -0,0 +1,69 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 4 Aug 2022 + * $Revision: V.1.1.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Q7 vector multiplication with variable output shifts + * Refer function header for details + * + */ + +void arm_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; /* loop counters */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t)__SSAT(((q31_t)((q31_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c new file mode 100644 index 0000000..0d02f9a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c @@ -0,0 +1,68 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 4 Aug 2022 + * $Revision: V.1.1.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Q7 vector multiplication with variable output shifts + * Refer function header for details + */ + +void arm_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; /* loop counters */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t)__SSAT(((q15_t)((q15_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c new file mode 100644 index 0000000..54f5403 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c @@ -0,0 +1,372 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2020-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_s16 + * Description: s16 vector by matrix (transposed) multiplication + * + * $Date: 11 August 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" +#define MAX_COL_COUNT (512) + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s16 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_nn_vec_mat_mult_t_s16(const q15_t *lhs, + const q7_t *rhs, + const q63_t *bias, + q15_t *dst, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ +#if defined(ARM_MATH_DSP) + + int32_t rhs_cols_fast = rhs_cols; + + if (rhs_cols > MAX_COL_COUNT) + { + rhs_cols_fast = MAX_COL_COUNT; + } + +#if defined(ARM_MATH_MVEI) + int32_t row_loop_cnt = rhs_rows / 4; + int32_t col_loop_cnt = (rhs_cols_fast + 7) / 8; + + for (int32_t i_row_loop_count = 0; i_row_loop_count < row_loop_cnt; i_row_loop_count++) + { + int32_t col_cnt = rhs_cols_fast; + + const int16_t *lhs_ptr = lhs; + const int8_t *rhs_ptr_0 = rhs; + const int8_t *rhs_ptr_1 = rhs + rhs_cols; + const int8_t *rhs_ptr_2 = rhs + rhs_cols * 2; + const int8_t *rhs_ptr_3 = rhs + rhs_cols * 3; + + int32_t result_0 = 0; + int32_t result_1 = 0; + int32_t result_2 = 0; + int32_t result_3 = 0; + + for (int i_col_loop_cnt = 0; i_col_loop_cnt < col_loop_cnt; i_col_loop_cnt++) + { + mve_pred16_t pred = vctp16q(col_cnt); + col_cnt -= 8; + + int16x8_t lhs_input = vldrhq_z_s16(lhs_ptr, pred); + + int16x8_t rhs_input_0 = vldrbq_z_s16(rhs_ptr_0, pred); + int16x8_t rhs_input_1 = vldrbq_z_s16(rhs_ptr_1, pred); + int16x8_t rhs_input_2 = vldrbq_z_s16(rhs_ptr_2, pred); + int16x8_t rhs_input_3 = vldrbq_z_s16(rhs_ptr_3, pred); + + result_0 = vmladavaq_s16(result_0, lhs_input, rhs_input_0); + result_1 = vmladavaq_s16(result_1, lhs_input, rhs_input_1); + result_2 = vmladavaq_s16(result_2, lhs_input, rhs_input_2); + result_3 = vmladavaq_s16(result_3, lhs_input, rhs_input_3); + + lhs_ptr += 8; + + rhs_ptr_0 += 8; + rhs_ptr_1 += 8; + rhs_ptr_2 += 8; + rhs_ptr_3 += 8; + } + + int64_t result_64_0 = result_0; + int64_t result_64_1 = result_1; + int64_t result_64_2 = result_2; + int64_t result_64_3 = result_3; + + if (rhs_cols > MAX_COL_COUNT) + { + for (int i_rhs_cols = MAX_COL_COUNT; i_rhs_cols < rhs_cols; i_rhs_cols++) + { + const int16_t lhs_temp = *lhs_ptr++; + + result_64_0 += *rhs_ptr_0++ * lhs_temp; + result_64_1 += *rhs_ptr_1++ * lhs_temp; + result_64_2 += *rhs_ptr_2++ * lhs_temp; + result_64_3 += *rhs_ptr_3++ * lhs_temp; + } + } + + if (bias) + { + result_64_0 += *bias++; + result_64_1 += *bias++; + result_64_2 += *bias++; + result_64_3 += *bias++; + } + + int32_t tmp; + tmp = arm_nn_requantize_s64(result_64_0, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + tmp = 0; + tmp = arm_nn_requantize_s64(result_64_1, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + tmp = 0; + tmp = arm_nn_requantize_s64(result_64_2, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + tmp = 0; + tmp = arm_nn_requantize_s64(result_64_3, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + rhs += 4 * rhs_cols; + } + + for (int8_t rows_left = rhs_rows & 0x3; rows_left > 0; rows_left--) + { + int32_t result = 0; + + col_loop_cnt = (rhs_cols_fast + 7) / 8; + + const int16_t *lhs_ptr = lhs; + const int8_t *rhs_ptr = rhs; + + int32_t col_cnt = (int32_t)rhs_cols_fast; + + for (int i_col_loop_cnt = 0; i_col_loop_cnt < col_loop_cnt; i_col_loop_cnt++) + { + mve_pred16_t pred = vctp16q(col_cnt); + col_cnt -= 8; + + int16x8_t lhs_input = vldrhq_z_s16(lhs_ptr, pred); + int16x8_t rhs_input = vldrbq_z_s16(rhs_ptr, pred); + + result = vmladavaq_p_s16(result, lhs_input, rhs_input, pred); + + lhs_ptr += 8; + rhs_ptr += 8; + } + + int64_t result_64 = result; + + if (bias) + { + result_64 += *bias++; + } + + if (rhs_cols > MAX_COL_COUNT) + { + for (int i_rhs_cols = MAX_COL_COUNT; i_rhs_cols < rhs_cols; i_rhs_cols++) + { + const int16_t lhs_temp = *lhs_ptr++; + + result_64 += *rhs_ptr++ * lhs_temp; + } + } + + int32_t tmp = 0; + tmp = arm_nn_requantize_s64(result_64, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + rhs += rhs_cols; + } + +#else // ARM_MATH_MVEI + + const int32_t row_loop_cnt = rhs_rows / 2; + + for (int32_t i = 0; i < row_loop_cnt; i++) + { + + q63_t acc_64_0 = 0; + q63_t acc_64_1 = 0; + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols_fast / 4; + + const int16_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t ker_0, ker_1, vec_part_0, vec_part_1; + + vec_part_0 = arm_nn_read_q15x2_ia(&lhs_vec); + vec_part_1 = arm_nn_read_q15x2_ia(&lhs_vec); + + rhs_0 = read_and_pad(rhs_0, &ker_0, &ker_1); + + acc_0 = __SMLAD(ker_0, vec_part_0, acc_0); + acc_0 = __SMLAD(ker_1, vec_part_1, acc_0); + + rhs_1 = read_and_pad(rhs_1, &ker_0, &ker_1); + + acc_1 = __SMLAD(ker_0, vec_part_0, acc_1); + acc_1 = __SMLAD(ker_1, vec_part_1, acc_1); + } + + acc_64_0 += acc_0; + acc_64_1 += acc_1; + + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec); + lhs_vec++; + acc_64_0 += lhs_temp * (*rhs_0); + rhs_0++; + acc_64_1 += lhs_temp * (*rhs_1); + rhs_1++; + } + + if (bias) + { + acc_64_0 += *bias++; + acc_64_1 += *bias++; + } + q31_t tmp; + + tmp = arm_nn_requantize_s64(acc_64_0, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + tmp = arm_nn_requantize_s64(acc_64_1, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + } + + if (rhs_rows & 0x1) + { + q63_t acc_64_0 = 0; + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols_fast / 4; + + const int16_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t ker_0, ker_1, vec; + rhs_0 = read_and_pad(rhs_0, &ker_0, &ker_1); + + vec = arm_nn_read_q15x2_ia(&lhs_vec); + acc_0 = __SMLAD(ker_0, vec, acc_0); + + vec = arm_nn_read_q15x2_ia(&lhs_vec); + acc_0 = __SMLAD(ker_1, vec, acc_0); + } + + acc_64_0 += acc_0; + + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec); + lhs_vec++; + acc_64_0 += lhs_temp * (*rhs_0); + rhs_0++; + } + + if (bias) + { + acc_64_0 += *bias++; + } + q31_t tmp; + tmp = arm_nn_requantize_s64(acc_64_0, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + } + +#endif // ARM_MATH_MVEI +#else // ARM_MATH_DSP + for (int i_row_loop_cnt = 0; i_row_loop_cnt < rhs_rows; i_row_loop_cnt++) + { + const q15_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + + q63_t result = 0; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q63_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q63_t lhs_value = *lhs_ptr; + + result += lhs_value * rhs_value0; + + ++rhs_ptr_0; + ++lhs_ptr; + } + + if (bias) + { + result += *bias++; + } + // Quantize down + result = arm_nn_requantize_s64(result, dst_multiplier, dst_shift); + + // Clamp the result + result = ((result) > (activation_min) ? (result) : (activation_min)); + result = ((result) < (activation_max) ? (result) : (activation_max)); + + *dst++ = (q15_t)result; + rhs += rhs_cols; + } +#endif // ARM_MATH_DSP + + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c new file mode 100644 index 0000000..7663bb6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c @@ -0,0 +1,406 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2020-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_s8 + * Description: s8 vector by matrix (transposed) multiplication + * + * $Date: 16 Aug 2022 + * $Revision: V.4.0.2 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max, + const int32_t address_offset) +{ + (void)rhs_offset; +#if defined(ARM_MATH_MVEI) + const int32_t row_loop_cnt = rhs_rows / 3; + const uint32x4_t address_offset_array = {0, address_offset, address_offset * 2, address_offset * 3}; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + const int8_t *rhs_2 = rhs + 2 * rhs_cols; + + int32_t rhs_sum_0 = 0; + int32_t rhs_sum_1 = 0; + int32_t rhs_sum_2 = 0; + + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + const int8x16_t ker_1 = vldrbq_z_s8(rhs_1, p); + rhs_sum_1 = vaddvaq_p_s8(rhs_sum_1, ker_1, p); + acc_1 = vmladavaq_p_s8(acc_1, ker_1, input, p); + + const int8x16_t ker_2 = vldrbq_z_s8(rhs_2, p); + rhs_sum_2 = vaddvaq_p_s8(rhs_sum_2, ker_2, p); + acc_2 = vmladavaq_p_s8(acc_2, ker_2, input, p); + + lhs_vec += 16; + rhs_0 += 16; + rhs_1 += 16; + rhs_2 += 16; + } + rhs += 3 * rhs_cols; + + int32x4_t acc = {acc_0, acc_1, acc_2, 0}; + mve_pred16_t p = vctp32q(3); + if (bias) + { + int32x4_t b = vldrwq_z_s32(bias, p); + acc = vaddq_x_s32(acc, b, p); + bias += 3; + } + const int32x4_t rhs_sum = {rhs_sum_0, rhs_sum_1, rhs_sum_2, 0}; + acc += vdupq_n_s32(lhs_offset) * rhs_sum; + + acc = arm_requantize_mve(acc, dst_multiplier, dst_shift); + acc = vaddq_s32(acc, vdupq_n_s32(dst_offset)); + acc = vmaxq_s32(acc, vdupq_n_s32(activation_min)); + acc = vminq_s32(acc, vdupq_n_s32(activation_max)); + + if (address_offset > 1L) + { + vstrbq_scatter_offset_s32(dst, address_offset_array, acc); + } + else + { + vstrbq_p_s32(dst, acc, p); + } + dst += 3 * address_offset; + } + + const int loop_cnt = rhs_rows % 3; + for (int i_row_loop_cnt = 0; i_row_loop_cnt < loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + int32_t rhs_sum_0 = 0; + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + lhs_vec += 16; + rhs_0 += 16; + } + rhs += rhs_cols; + + if (bias) + { + acc_0 += *bias; + bias++; + } + const int32_t offsets = rhs_sum_0 * lhs_offset; + acc_0 += offsets; + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_0 += dst_offset; + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + *dst = MIN(acc_0, activation_max); + dst += address_offset; + } + +#elif defined(ARM_MATH_DSP) + const int32_t row_loop_cnt = rhs_rows / 2; + const int16_t lhs_offset_s16 = (int16_t)lhs_offset; + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + if (bias) + { + acc_0 = *bias++; + acc_1 = *bias++; + } + + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + + ker_0 = arm_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1); + rhs_1++; + } + + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = arm_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + acc_1 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (int8_t)acc_0; + *(dst + address_offset) = (int8_t)acc_1; + dst += 2 * address_offset; + } + + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + if (bias) + { + acc_0 = *bias++; + } + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + } + + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (int8_t)acc_0; + dst += address_offset; + } + +#else + + const int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + if (bias) + { + res00 = *bias++; + res01 = *bias++; + res02 = *bias++; + } + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = arm_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = arm_nn_requantize(res02, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res02 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q7_t)res00; + *(dst + address_offset) = (q7_t)res01; + *(dst + 2 * address_offset) = (q7_t)res02; + dst += 3 * address_offset; + + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + if (bias) + { + res00 = *bias++; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0]; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (int8_t)res00; + dst += address_offset; + rhs += rhs_cols; + } +#endif + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c new file mode 100644 index 0000000..293edb2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c @@ -0,0 +1,345 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2021-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_svdf_s8 + * Description: s8 vector by matrix (transposed) multiplication with + * s16 output. Targetted at SVDF operator. + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_cmsis_nn_status arm_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ + (void)rhs_offset; + if (rhs_cols < 0 || (NN_Q31_MAX - rhs_cols) < 16 || dst_offset < 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + (void)rhs_offset; +#if defined(ARM_MATH_MVEI) + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + const int8_t *rhs_2 = rhs + 2 * rhs_cols; + + int32_t rhs_sum_0 = 0; + int32_t rhs_sum_1 = 0; + int32_t rhs_sum_2 = 0; + + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + const int8x16_t ker_1 = vldrbq_z_s8(rhs_1, p); + rhs_sum_1 = vaddvaq_p_s8(rhs_sum_1, ker_1, p); + acc_1 = vmladavaq_p_s8(acc_1, ker_1, input, p); + + const int8x16_t ker_2 = vldrbq_z_s8(rhs_2, p); + rhs_sum_2 = vaddvaq_p_s8(rhs_sum_2, ker_2, p); + acc_2 = vmladavaq_p_s8(acc_2, ker_2, input, p); + + lhs_vec += 16; + rhs_0 += 16; + rhs_1 += 16; + rhs_2 += 16; + } + rhs += 3 * rhs_cols; + + int32x4_t acc = {acc_0, acc_1, acc_2, 0}; + const int32x4_t rhs_sum = {rhs_sum_0, rhs_sum_1, rhs_sum_2, 0}; + acc += vdupq_n_s32(lhs_offset) * rhs_sum; + + acc = arm_requantize_mve(acc, dst_multiplier, dst_shift); + acc = vmaxq_s32(acc, vdupq_n_s32(activation_min)); + acc = vminq_s32(acc, vdupq_n_s32(activation_max)); + *(dst) = (int16_t)acc[0]; + *(dst + dst_offset) = (int16_t)acc[1]; + *(dst + 2 * dst_offset) = (int16_t)acc[2]; + dst += 3 * dst_offset; + } + + const int loop_cnt = rhs_rows % 3; + for (int i_row_loop_cnt = 0; i_row_loop_cnt < loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + int32_t rhs_sum_0 = 0; + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + lhs_vec += 16; + rhs_0 += 16; + } + rhs += rhs_cols; + + const int32_t offsets = rhs_sum_0 * lhs_offset; + acc_0 = __QADD(acc_0, offsets); + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + *dst = (q15_t)MIN(acc_0, activation_max); + dst += dst_offset; + } + +#elif defined(ARM_MATH_DSP) + int32_t row_loop_cnt = rhs_rows / 2; + + const int16_t lhs_offset_s16 = lhs_offset; + const int16_t rhs_offset_s16 = rhs_offset; + + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + const uint32_t rhs_offset_s16x2 = __PKHBT(rhs_offset_s16, rhs_offset_s16, 16); + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + ker_0 = arm_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1 + rhs_offset); + rhs_1++; + } + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = arm_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (q15_t)acc_0; + *(dst + dst_offset) = (q15_t)acc_1; + dst += 2 * dst_offset; + } + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16(lhs_offset_s16x2, __ROR((uint32_t)vec_0, 8)); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16(rhs_offset_s16x2, __ROR((uint32_t)ker_0, 8)); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + } + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (q15_t)acc_0; + dst += dst_offset; + } + +#else + + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = arm_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = arm_nn_requantize(res02, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q15_t)res00; + *(dst + dst_offset) = (q15_t)res01; + *(dst + 2 * dst_offset) = (q15_t)res02; + dst += 3 * dst_offset; + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0] + rhs_offset; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (q15_t)res00; + dst += dst_offset; + rhs += rhs_cols; + } +#endif + + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c new file mode 100644 index 0000000..ef8093e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c @@ -0,0 +1,207 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, 0x5e, 0x5f, 0x61, + 0x62, 0x63, 0x65, 0x66, 0x67, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, + 0x75, 0x76, 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, 0x06, + 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, 0x0f, 0x10, 0x11, 0x12, + 0x13, 0x14, 0x15, 0x16, 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, + 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, + 0x5a57, 0x5bfb, 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, 0x68a6, 0x69d2, 0x6af1, 0x6c05, + 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, + 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, + 0x7e69, 0x7e81, 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, + 0x7f55, 0x7f5f, 0x7f69, 0x7f72, 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, + 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, + 0x7ff4, 0x7ff4, 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, + 0x0017, 0x0019, 0x001a, 0x001c, 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, + 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, + 0x013e, 0x0152, 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, + 0x02f1, 0x0320, 0x0353, 0x0388, 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, + 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, + 0x1f5f, 0x20e0, 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, 0x3053, 0x3238, 0x3424, 0x3615, + 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, + 0x4cd3, 0x4dc8, 0x4ebb, 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, 0x56ef, 0x57cd, + 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, + 0x62cc, 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, 0x68a6, 0x693d, 0x69d2, 0x6a63, + 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, 0x0f42, + 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, + 0x162e, 0x16c3, 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, 0x1c81, 0x1d34, 0x1dea, + 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, + 0x351b, 0x3615, 0x370f, 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, + 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, + 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, 0x7e98, 0x7eae, + 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, + 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, + 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, 0x000b, 0x000c, + 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, + 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, 0x0085, 0x008e, 0x0097, 0x00a1, + 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, 0x0168, 0x017f, + 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, + 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, 0x61, 0x65, 0x68, + 0x6a, 0x6d, 0x6f, 0x71, 0x72, 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, 0x85, 0x85, 0x86, 0x87, + 0x88, 0x88, 0x8a, 0x8b, 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, + 0xbf, 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, + 0x5a1a, 0x5df6, 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, 0x73dc, 0x753a, 0x7672, 0x7788, + 0x787f, 0x795b, 0x7a1e, 0x7acb, 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, + 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, + 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, + 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, + 0x8006, 0x8007, 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, + 0x8024, 0x8029, 0x802f, 0x8035, 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, + 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, + 0x9869, 0x9b50, 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, 0xc4d9, 0xcb52, 0xd221, 0xd941, + 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, + 0x3151, 0x34ae, 0x37f6, 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, 0x514d, 0x53a3, + 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, + 0x6b6e, 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, 0x73dc, 0x7490, 0x753a, 0x75da, + 0x7672, 0x7701, 0x7788, 0x7807, 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, 0x849b, + 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, + 0x8ac6, 0x8b70, 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, 0x936b, 0x9492, 0x95c9, + 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, + 0xd5a8, 0xd941, 0xdcec, 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, + 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, + 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, + 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8002, + 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, 0x8008, 0x8009, + 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, + 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c new file mode 100644 index 0000000..110a93b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c @@ -0,0 +1,114 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/* + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * Refer function header for details + */ + +void arm_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; + uint32_t blkCnt; + +#if defined(ARM_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + while (blkCnt > 0u) + { + in = arm_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remaining two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + out2 = (int32_t)__PKHTB(in1, in2, 16); + out1 = (int32_t)__PKHBT(in2, in1, 16); +#else + out1 = (int32_t)__PKHTB(in1, in2, 16); + out2 = (int32_t)__PKHBT(in2, in1, 16); +#endif + arm_nn_write_q15x2_ia(&pDst, out1); + arm_nn_write_q15x2_ia(&pDst, out2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of nndata_convert group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c new file mode 100644 index 0000000..c7ee063 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c @@ -0,0 +1,144 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: 4 Aug 2022 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/* + * Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * Refer to header for details + * + * This function does the q7 to q15 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + q31_t in; + q31_t in1, in2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = arm_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + arm_nn_write_q7x4_ia((q7_t **)&pDst, in2); + arm_nn_write_q7x4_ia((q7_t **)&pDst, in1); +#else + arm_nn_write_q7x4_ia((q7_t **)&pDst, in1); + arm_nn_write_q7x4_ia((q7_t **)&pDst, in2); +#endif + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of q7_to_x group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c new file mode 100644 index 0000000..572c7bc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c @@ -0,0 +1,104 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_with_offset.c + * Description: Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. The re-ordering + * is a signature of sign extension intrinsic(DSP extension). + * + * $Date: 4 Aug 2022 + * $Revision: V.2.0.4 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/* + * Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. + * + * Refer header file for details. + * + */ + +void arm_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + +#if defined(ARM_MATH_DSP) + uint32_t block_cnt; + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t out_q15x2_1; + q31_t out_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = (q31_t)__PKHBT(offset, offset, 16); + while (block_cnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + in_q7x4 = arm_nn_read_q7x4_ia(&src); + + /* Extract and sign extend each of the four q7 values to q15 */ + out_q15x2_1 = __SXTAB16(offset_q15x2, __ROR((uint32_t)in_q7x4, 8)); + out_q15x2_2 = __SXTAB16(offset_q15x2, in_q7x4); + + arm_nn_write_q15x2_ia(&dst, out_q15x2_2); + arm_nn_write_q15x2_ia(&dst, out_q15x2_1); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4u; + + while (block_cnt > 0u) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +#else + (void)src; + (void)dst; + (void)block_size; + (void)offset; + /* Not available */ +#endif +} + +/** + * @} end of nndata_convert group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c new file mode 100644 index 0000000..fd88488 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c @@ -0,0 +1,118 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in_q7x4 compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in_q7x4 writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_with_offset.c + * Description: Converts the elements of the Q7 vector to Q15 vector with an added offset + * + * $Date: March 3, 2020 + * $Revision: V.2.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +void arm_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + int block_cnt; + +#if defined(ARM_MATH_MVEI) + + int16x8_t source; + const int16x8_t source_offset = vdupq_n_s16(offset); + block_cnt = block_size / 8; + + while (block_cnt > 0) + { + source = vldrbq_s16(src); + source = vaddq_s16(source, source_offset); + vstrhq_s16(dst, source); + dst += 8; + src += 8; + block_cnt--; + } + + block_cnt = block_size & 0x7; + +#elif defined(ARM_MATH_DSP) + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t in_q15x2_1; + q31_t in_q15x2_2; + q31_t out_q15x2_1; + q31_t out_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = __PKHBT(offset, offset, 16); + while (block_cnt > 0) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + in_q7x4 = arm_nn_read_q7x4_ia(&src); + + /* Extract and sign extend each of the four q7 values to q15 */ + in_q15x2_1 = __SXTAB16(offset_q15x2, __ROR(in_q7x4, 8)); + in_q15x2_2 = __SXTAB16(offset_q15x2, in_q7x4); + + out_q15x2_2 = __PKHTB(in_q15x2_1, in_q15x2_2, 16); + out_q15x2_1 = __PKHBT(in_q15x2_2, in_q15x2_1, 16); + + arm_nn_write_q15x2_ia(&dst, out_q15x2_1); + arm_nn_write_q15x2_ia(&dst, out_q15x2_2); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4; + +#else + /* Run the below code for Cortex-M0 */ + /* Loop over block_size number of values */ + block_cnt = block_size; +#endif + + while (block_cnt > 0) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +} + +/** + * @} end of nndata_convert group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c new file mode 100644 index 0000000..be5b7f0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c @@ -0,0 +1,311 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_avgpool_s16.c + * Description: Pooling function implementations + * + * $Date: 27 July 2022 + * $Revision: V.2.2.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + +static void scale_q31_to_q15_and_clamp(const q31_t *buffer, + q15_t *target, + int32_t length, + const int32_t count, + const int act_min, + const int act_max) +{ + const int half_count = count / 2; + + for (int i = 0; i < length; i++) + { + int32_t sum = buffer[i] > 0 ? (buffer[i] + half_count) : (buffer[i] - half_count); + sum = sum / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + target[i] = (q15_t)sum; + } +} +#endif + +/** + * @ingroup groupNN + + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s16 average pooling function + * + * Refer to header file for details. + * + */ +arm_cmsis_nn_status arm_avgpool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q15_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q15_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; +#if defined(ARM_MATH_MVEI) + (void)ctx; + for (int i_y = 0; i_y < output_y; i_y++) + { + for (int i_x = 0; i_x < output_x; i_x++) + { + const int32_t k_y_start = MAX(0, i_y * stride_y - pad_y); + const int32_t k_y_end = MIN(i_y * stride_y - pad_y + kernel_y, input_y); + + const int32_t k_x_start = MAX(0, i_x * stride_x - pad_x); + const int32_t k_x_end = MIN(i_x * stride_x - pad_x + kernel_x, input_x); + + const int16_t *src_base = src; + int16_t *out = &dst[ch_src * (i_x + i_y * output_x)]; + + int32_t ch_count = (ch_src + 7) / 8; + int32_t channels = ch_src; + + while (ch_count > 0) + { + int32_t count = 0; + + int32x4_t sum_1 = vdupq_n_s32(0); + int32x4_t sum_2 = vdupq_n_s32(0); + // Load store tail predicate + const mve_pred16_t ld_st_p = vctp16q(channels); + channels -= 8; + + for (int k_y = k_y_start; k_y < k_y_end; k_y++) + { + for (int k_x = k_x_start; k_x < k_x_end; k_x++) + { + const int16_t *src_inner = src_base + (ch_src * (k_x + k_y * input_x)); + const int16x8_t temp = vldrhq_z_s16(src_inner, ld_st_p); + + const int32x4_t temp_lo = vmovlbq_s16(temp); + const int32x4_t temp_hi = vmovltq_s16(temp); + + sum_1 = vaddq_s32(sum_1, temp_lo); + sum_2 = vaddq_s32(sum_2, temp_hi); + + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + // Perform the following operation + // sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + const int32_t half_count = count / 2; + // Predicate for 'sum > 0' operation + mve_pred16_t p = vcmpgtq_n_s32(sum_1, 0); + sum_1 = vaddq_m_n_s32(sum_1, sum_1, half_count, p); + sum_1 = vsubq_m_n_s32(sum_1, sum_1, half_count, ~p); + + p = vcmpgtq_n_s32(sum_2, 0); + sum_2 = vaddq_m_n_s32(sum_2, sum_2, half_count, p); + sum_2 = vsubq_m_n_s32(sum_2, sum_2, half_count, ~p); + + for (int i = 0; i < 4; i++) + { + sum_1[i] = sum_1[i] / count; + sum_2[i] = sum_2[i] / count; + } + + sum_1 = vmaxq_s32(sum_1, vdupq_n_s32(act_min)); + sum_1 = vminq_s32(sum_1, vdupq_n_s32(act_max)); + + sum_2 = vmaxq_s32(sum_2, vdupq_n_s32(act_min)); + sum_2 = vminq_s32(sum_2, vdupq_n_s32(act_max)); + + int16x8_t temp = vdupq_n_s16(0); + temp = vmovnbq_s32(temp, sum_1); + temp = vmovntq_s32(temp, sum_2); + + vstrhq_p_s16(out, temp, ld_st_p); + + out += 8; + ch_count--; + src_base += 8; + } + } + } +#elif defined(ARM_MATH_DSP) + + q31_t *buffer = (q31_t *)ctx->buf; + + if (buffer == NULL) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + /* Run the following code for CPU's with DSP extension + */ + for (int i_y = 0, idx_y = -pad_y; i_y < output_y; idx_y += stride_y, i_y++) + { + for (int i_x = 0, idx_x = -pad_x; i_x < output_x; idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: + (base_idx_ + kernel__start) >= 0 */ + const int32_t kernel_y_start = MAX(0, -idx_y); + const int32_t kernel_x_start = MAX(0, -idx_x); + + /* Condition for kernel end dimension: + (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - idx_x); + + int count = 0; + + for (int k_y = kernel_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = kernel_x_start; k_x < kernel_x_end; k_x++) + { + const q15_t *start = src + ch_src * (k_x + idx_x + (k_y + idx_y) * input_x); + + if (count == 0) + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = start[i]; + } + } + else + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = __QADD(start[i], buffer[i]); + } + } + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + scale_q31_to_q15_and_clamp(buffer, dst, ch_src, count, act_min, act_max); + dst += ch_src; + } + } + +#else + /* Reference C code adapted from CMSIS-NN arm_avgpool_s8.c. + */ + + (void)ctx; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + for (int i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + sum += src[i_ch_in + ch_src * (k_x + base_idx_x + (k_y + base_idx_y) * input_x)]; + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum; + } + } + } +#endif + + return ARM_CMSIS_NN_SUCCESS; +} + +int32_t arm_avgpool_s16_get_buffer_size(const int output_x, const int ch_src) +{ + (void)output_x; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + return (ch_src * (int32_t)sizeof(int32_t)); +#else + (void)ch_src; +#endif + return 0; +} + +/** + * @} end of Pooling group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c new file mode 100644 index 0000000..05c284f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c @@ -0,0 +1,366 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_avgpool_s8.c + * Description: Pooling function implementations + * + * $Date: 7 July 2022 + * $Revision: V.3.0.2 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) +static void scale_q31_to_q7_and_clamp(const q31_t *buffer, + q7_t *target, + int32_t length, + const int32_t count, + const int act_min, + const int act_max) +{ + const int half_count = count / 2; + + for (int i = 0; i < length; i++) + { + int32_t sum = buffer[i] > 0 ? (buffer[i] + half_count) : (buffer[i] - half_count); + sum = sum / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + target[i] = (q7_t)sum; + } +} +#endif + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s8 average pooling function + * + * Refer to header file for details. + * + */ + +#if defined(ARM_MATH_MVEI) + +arm_cmsis_nn_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + (void)ctx; + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + for (int i_y = 0; i_y < output_y; i_y++) + { + for (int i_x = 0; i_x < output_x; i_x++) + { + const int32_t k_y_start = MAX(0, i_y * stride_y - pad_y); + const int32_t k_y_end = MIN(i_y * stride_y - pad_y + kernel_y, input_y); + + const int32_t k_x_start = MAX(0, i_x * stride_x - pad_x); + const int32_t k_x_end = MIN(i_x * stride_x - pad_x + kernel_x, input_x); + + const int8_t *src_base = src; + int8_t *out = &dst[ch_src * (i_x + i_y * output_x)]; + + int32_t ch_count = (ch_src + 15) / 16; + int32_t channels = ch_src; + + while (ch_count > 0) + { + int8x16_t temp; + int16x8_t temp_lo, temp_hi; + int32x4_t temp_lo_lo, temp_lo_hi, temp_hi_lo, temp_hi_hi; + int32_t count = 0; + + int32x4_t sum_1 = vdupq_n_s32(0); + int32x4_t sum_2 = vdupq_n_s32(0); + int32x4_t sum_3 = vdupq_n_s32(0); + int32x4_t sum_4 = vdupq_n_s32(0); + // Load store tail predicate + const mve_pred16_t ld_st_p = vctp8q(channels); + channels -= 16; + + for (int k_y = k_y_start; k_y < k_y_end; k_y++) + { + for (int k_x = k_x_start; k_x < k_x_end; k_x++) + { + const int8_t *src_inner = src_base + (ch_src * (k_x + k_y * input_x)); + temp = vldrbq_z_s8(src_inner, ld_st_p); + + temp_lo = vmovlbq_s8(temp); + temp_hi = vmovltq_s8(temp); + + temp_lo_lo = vmovlbq_s16(temp_lo); + temp_lo_hi = vmovltq_s16(temp_lo); + + temp_hi_lo = vmovlbq_s16(temp_hi); + temp_hi_hi = vmovltq_s16(temp_hi); + + sum_1 = vaddq_s32(sum_1, temp_lo_lo); + sum_2 = vaddq_s32(sum_2, temp_lo_hi); + sum_3 = vaddq_s32(sum_3, temp_hi_lo); + sum_4 = vaddq_s32(sum_4, temp_hi_hi); + + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + // Perform the following operation + // sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + const int32_t half_count = count / 2; + // Predicate for 'sum > 0' operation + mve_pred16_t p = vcmpgtq_n_s32(sum_1, 0); + sum_1 = vaddq_m_n_s32(sum_1, sum_1, half_count, p); + sum_1 = vsubq_m_n_s32(sum_1, sum_1, half_count, ~p); + + p = vcmpgtq_n_s32(sum_2, 0); + sum_2 = vaddq_m_n_s32(sum_2, sum_2, half_count, p); + sum_2 = vsubq_m_n_s32(sum_2, sum_2, half_count, ~p); + + p = vcmpgtq_n_s32(sum_3, 0); + sum_3 = vaddq_m_n_s32(sum_3, sum_3, half_count, p); + sum_3 = vsubq_m_n_s32(sum_3, sum_3, half_count, ~p); + + p = vcmpgtq_n_s32(sum_4, 0); + sum_4 = vaddq_m_n_s32(sum_4, sum_4, half_count, p); + sum_4 = vsubq_m_n_s32(sum_4, sum_4, half_count, ~p); + + for (int i = 0; i < 4; i++) + { + sum_1[i] = sum_1[i] / count; + sum_2[i] = sum_2[i] / count; + sum_3[i] = sum_3[i] / count; + sum_4[i] = sum_4[i] / count; + } + + sum_1 = vmaxq_s32(sum_1, vdupq_n_s32(act_min)); + sum_1 = vminq_s32(sum_1, vdupq_n_s32(act_max)); + + sum_2 = vmaxq_s32(sum_2, vdupq_n_s32(act_min)); + sum_2 = vminq_s32(sum_2, vdupq_n_s32(act_max)); + + sum_3 = vmaxq_s32(sum_3, vdupq_n_s32(act_min)); + sum_3 = vminq_s32(sum_3, vdupq_n_s32(act_max)); + + sum_4 = vmaxq_s32(sum_4, vdupq_n_s32(act_min)); + sum_4 = vminq_s32(sum_4, vdupq_n_s32(act_max)); + + temp_lo = vmovnbq_s32(temp_lo, sum_1); + temp_lo = vmovntq_s32(temp_lo, sum_2); + + temp_hi = vmovnbq_s32(temp_hi, sum_3); + temp_hi = vmovntq_s32(temp_hi, sum_4); + + temp = vmovnbq_s16(temp, temp_lo); + temp = vmovntq_s16(temp, temp_hi); + + vstrbq_p_s8(out, temp, ld_st_p); + out += 16; + + ch_count--; + src_base += 16; + } + } + } + return ARM_CMSIS_NN_SUCCESS; +} + +#else +arm_cmsis_nn_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + if (ctx->buf == NULL && arm_avgpool_s8_get_buffer_size(output_dims->w, input_dims->c)) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + q31_t *buffer = (q31_t *)ctx->buf; + +#if defined(ARM_MATH_DSP) + + /* Run the following code for CPU's with DSP extension + */ + for (int i_y = 0, idx_y = -pad_y; i_y < output_y; idx_y += stride_y, i_y++) + { + for (int i_x = 0, idx_x = -pad_x; i_x < output_x; idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: + (base_idx_ + kernel__start) >= 0 */ + const int32_t kernel_y_start = MAX(0, -idx_y); + const int32_t kernel_x_start = MAX(0, -idx_x); + + /* Condition for kernel end dimension: + (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - idx_x); + + int count = 0; + + for (int k_y = kernel_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = kernel_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + ch_src * (k_x + idx_x + (k_y + idx_y) * input_x); + + if (count == 0) + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = start[i]; + } + } + else + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = __QADD(start[i], buffer[i]); + } + } + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + scale_q31_to_q7_and_clamp(buffer, dst, ch_src, count, act_min, act_max); + dst += ch_src; + } + } +#else + + /* Reference C code adapted from CMSIS-NN arm_avepool_q7_HWC. + */ + (void)buffer; + + for (int i_y = 0; i_y < output_y; i_y++) + { + for (int i_x = 0; i_x < output_x; i_x++) + { + for (int i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + for (int k_y = i_y * stride_y - pad_y; k_y < i_y * stride_y - pad_y + kernel_y; k_y++) + { + for (int k_x = i_x * stride_x - pad_x; k_x < i_x * stride_x - pad_x + kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < input_y && k_x < input_x) + { + sum += src[i_ch_in + ch_src * (k_x + k_y * input_x)]; + count++; + } + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum; + } + } + } + +#endif + return ARM_CMSIS_NN_SUCCESS; +} + +#endif /* ARM_MATH_MVEI */ + +int32_t arm_avgpool_s8_get_buffer_size(const int output_x, const int ch_src) +{ + (void)output_x; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + return (ch_src * sizeof(int32_t)); +#else + (void)ch_src; + return 0; +#endif +} +/** + * @} end of Pooling group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c new file mode 100644 index 0000000..0b39d5e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c @@ -0,0 +1,216 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_max_pool_s16.c + * Description: Pooling function implementations + * + * $Date: 16 August 2022 + * $Revision: V.2.1.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +static void compare_and_replace_if_larger(int16_t *base, const int16_t *target, int32_t length) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (length + 7) / 8; + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp16q((uint32_t)length); + const int16x8_t op_1 = vldrhq_z_s16(base, p); + const int16x8_t op_2 = vldrhq_z_s16(target, p); + const int16x8_t max = vmaxq_s16(op_1, op_2); + vstrhq_p_s16(base, max, p); + base += 8; + target += 8; + length -= 8; + } +#else + q15_t *dst = base; + const q15_t *src = target; + union arm_nnword ref_max; + union arm_nnword comp_max; + int32_t cnt = length >> 1; + + while (cnt > 0l) + { + ref_max.word = arm_nn_read_q15x2(dst); + comp_max.word = arm_nn_read_q15x2_ia(&src); + + if (comp_max.half_words[0] > ref_max.half_words[0]) + { + ref_max.half_words[0] = comp_max.half_words[0]; + } + if (comp_max.half_words[1] > ref_max.half_words[1]) + { + ref_max.half_words[1] = comp_max.half_words[1]; + } + + arm_nn_write_q15x2_ia(&dst, ref_max.word); + + cnt--; + } + + if (length & 0x1) + { + if (*src > *dst) + { + *dst = *src; + } + } +#endif +} + +static void clamp_output(int16_t *source, int32_t length, const int16_t act_min, const int16_t act_max) +{ +#if defined(ARM_MATH_MVEI) + const int16x8_t min = vdupq_n_s16((int16_t)act_min); + const int16x8_t max = vdupq_n_s16((int16_t)act_max); + + int32_t loop_count = (length + 7) / 8; + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp16q((uint32_t)length); + length -= 8; + const int16x8_t src = vldrhq_z_s16(source, p); + int16x8_t res = vmaxq_x_s16(src, min, p); + res = vminq_x_s16(res, max, p); + vstrhq_p_s16(source, res, p); + source += 8; + } +#else + union arm_nnword in; + int32_t cnt = length >> 1; + + while (cnt > 0l) + { + in.word = arm_nn_read_q15x2(source); + + in.half_words[0] = MAX(in.half_words[0], act_min); + in.half_words[0] = MIN(in.half_words[0], act_max); + in.half_words[1] = MAX(in.half_words[1], act_min); + in.half_words[1] = MIN(in.half_words[1], act_max); + + arm_nn_write_q15x2_ia(&source, in.word); + cnt--; + } + + if (length & 0x1) + { + int16_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source = comp; + } +#endif +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s16 max pooling function + * + * Refer to header file for details. + * + */ + +arm_cmsis_nn_status arm_max_pool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int16_t act_min = pool_params->activation.min; + const int16_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + int16_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const int16_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + memcpy(dst, start, channel_in * sizeof(int16_t)); + count++; + } + else + { + compare_and_replace_if_larger(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of Pooling group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c new file mode 100644 index 0000000..581a8c6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c @@ -0,0 +1,234 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_max_pool_s8.c + * Description: Pooling function implementations + * + * $Date: 16 August 2022 + * $Revision: V.3.0.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +static void compare_and_replace_if_larger_q7(q7_t *base, const q7_t *target, int32_t length) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (length + 15) / 16; + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp8q((uint32_t)length); + const int8x16_t op_1 = vldrbq_z_s8(base, p); + const int8x16_t op_2 = vldrbq_z_s8(target, p); + const int8x16_t max = vmaxq_x_s8(op_1, op_2, p); + vstrbq_p_s8(base, max, p); + base += 16; + target += 16; + length -= 16; + } +#else + q7_t *dst = base; + const q7_t *src = target; + union arm_nnword ref_max; + union arm_nnword comp_max; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + ref_max.word = arm_nn_read_q7x4(dst); + comp_max.word = arm_nn_read_q7x4_ia(&src); + + if (comp_max.bytes[0] > ref_max.bytes[0]) + { + ref_max.bytes[0] = comp_max.bytes[0]; + } + if (comp_max.bytes[1] > ref_max.bytes[1]) + { + ref_max.bytes[1] = comp_max.bytes[1]; + } + if (comp_max.bytes[2] > ref_max.bytes[2]) + { + ref_max.bytes[2] = comp_max.bytes[2]; + } + if (comp_max.bytes[3] > ref_max.bytes[3]) + { + ref_max.bytes[3] = comp_max.bytes[3]; + } + + arm_nn_write_q7x4_ia(&dst, ref_max.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + if (*src > *dst) + { + *dst = *src; + } + dst++; + src++; + cnt--; + } +#endif +} + +static void clamp_output(q7_t *source, int32_t length, const int32_t act_min, const int32_t act_max) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (length + 15) / 16; + const int8x16_t vmin = vdupq_n_s8((int8_t)act_min); + const int8x16_t vmax = vdupq_n_s8((int8_t)act_max); + + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp8q((uint32_t)length); + length -= 16; + const int8x16_t src = vldrbq_z_s8(source, p); + int8x16_t res = vmaxq_x_s8(src, vmin, p); + res = vminq_x_s8(res, vmax, p); + vstrbq_p_s8(source, res, p); + source += 16; + } +#else + union arm_nnword in; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + in.word = arm_nn_read_q7x4(source); + + in.bytes[0] = MAX(in.bytes[0], act_min); + in.bytes[0] = MIN(in.bytes[0], act_max); + in.bytes[1] = MAX(in.bytes[1], act_min); + in.bytes[1] = MIN(in.bytes[1], act_max); + in.bytes[2] = MAX(in.bytes[2], act_min); + in.bytes[2] = MIN(in.bytes[2], act_max); + in.bytes[3] = MAX(in.bytes[3], act_min); + in.bytes[3] = MIN(in.bytes[3], act_max); + + arm_nn_write_q7x4_ia(&source, in.word); + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + int32_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source++ = (int8_t)comp; + cnt--; + } +#endif +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s8 max pooling function + * + * Refer to header file for details. + * + */ + +arm_cmsis_nn_status arm_max_pool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + q7_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + arm_memcpy_q7(dst, start, channel_in); + count++; + } + else + { + compare_and_replace_if_larger_q7(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of Pooling group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c new file mode 100644 index 0000000..c88fc24 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c @@ -0,0 +1,468 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 4 Aug 2022 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + +/* + * A few utility functions used by pooling functions + * + * + */ + +static void buffer_scale_back_q15_to_q7(q15_t *buffer, q7_t *target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t)(buffer[i] / scale); + } +} + +static void compare_and_replace_if_larger_q7(q7_t *base, // base data + const q7_t *target, // compare target + const uint16_t length // data length +) +{ + q7_t *pIn = base; + const q7_t *pCom = target; + union arm_nnword in; + union arm_nnword com; + uint16_t cnt = length >> 2; + + while (cnt > 0u) + { + in.word = arm_nn_read_q7x4((const q7_t *)pIn); + com.word = arm_nn_read_q7x4_ia((const q7_t **)&pCom); + + // if version + if (com.bytes[0] > in.bytes[0]) + in.bytes[0] = com.bytes[0]; + if (com.bytes[1] > in.bytes[1]) + in.bytes[1] = com.bytes[1]; + if (com.bytes[2] > in.bytes[2]) + in.bytes[2] = com.bytes[2]; + if (com.bytes[3] > in.bytes[3]) + in.bytes[3] = com.bytes[3]; + + arm_nn_write_q7x4_ia(&pIn, in.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0u) + { + if (*pCom > *pIn) + { + *pIn = *pCom; + } + pIn++; + pCom++; + cnt--; + } +} + +static void accumulate_q7_to_q15(q15_t *base, q7_t *target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; + uint16_t cnt = length >> 2; + q31_t in; + + while (cnt > 0u) + { + q31_t value = arm_nn_read_q7x4_ia((const q7_t **)&pV); + v1 = __SXTB16(__ROR(value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + + vo2 = __PKHTB(v1, v2, 16); + vo1 = __PKHBT(v2, v1, 16); + +#else + + vo1 = __PKHTB(v1, v2, 16); + vo2 = __PKHBT(v2, v1, 16); + +#endif + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + +#endif // ARM_MATH_DSP + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA Not used + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void arm_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + (void)bufferA; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_x, i_y; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + /* arm_copy_q7(win_start, target, ch_im_in); */ + memmove(target, win_start, ch_im_in); + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + compare_and_replace_if_larger_q7(target, win_start, ch_im_in); + } + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + /* arm_copy_q7(row_start, target, dim_im_out * ch_im_in); */ + memmove(target, row_start, dim_im_out * ch_im_in); + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in); + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * Buffer size: + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void arm_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + q15_t *buffer = (q15_t *)bufferA; + int16_t i_x, i_y; + int16_t count = 0; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + arm_q7_to_q15_no_shift(win_start, buffer, ch_im_in); + count = 1; + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + accumulate_q7_to_q15(buffer, win_start, ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + arm_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + count = 1; + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + (void)bufferA; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @} end of Pooling group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c new file mode 100644 index 0000000..0b1892b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c @@ -0,0 +1,61 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_reshape_s8.c + * Description: Reshape a s8 vector + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Reshape + * @{ + */ + +/* + * Basic s8 reshape function. + * + * Refer header file for details. + * + */ + +void arm_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size) +{ + arm_memcpy_q7(output, input, total_size); +} + +/** + * @} end of Reshape group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c new file mode 100644 index 0000000..3d386e8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c @@ -0,0 +1,275 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_svdf_s8.c + * Description: S8 basic SVDF layer function + * + * $Date: 4 May 2022 + * $Revision: V.4.0.1 + * + * Target Processor: Cortex-M processors + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite with 8 bit state tensor + * + * Refer to header file for details. + * + */ + +arm_cmsis_nn_status arm_svdf_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q7_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q7_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + if (input_ctx->buf == NULL) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + q31_t *buffer_a = (q31_t *)input_ctx->buf; + + if (output_ctx->buf == NULL) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + q31_t *buffer_b = (q31_t *)output_ctx->buf; + + // Left shift state + memmove((int8_t *)state_data, + (int8_t *)state_data + 1, + (size_t)((input_batches * feature_batches * time_batches - 1) * (int32_t)sizeof(int8_t))); + + // Matrix multiplication input * feature weight + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q7_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + arm_cmsis_nn_status res = arm_nn_vec_mat_mult_t_s8(input, + weight, + NULL, + res_ptr, + -zp_in, + 0, + 0, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max, + time_batches); + + if (res != ARM_CMSIS_NN_SUCCESS) + { + return res; + } + } + + // Matrix multiplicate time weight * state tensors + { + q31_t *ptr_a = buffer_a; + const int8_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const int8_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + // Perform matrix multiplication in blocks of four + int j = 0; + int32_t block_count = time_batches >> 2; + for (int i = 0; i < block_count; i++) + { + j += 4; + + q31_t r1_1, r1_2, r2_1, r2_2; + v1 = read_and_pad_reordered(v1, &r1_1, &r1_2); + v2 = read_and_pad_reordered(v2, &r2_1, &r2_2); + sum = __SMLAD(r1_1, r2_1, sum); + sum = __SMLAD(r1_2, r2_2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + +#if defined(ARM_MATH_MVEI) + int32_t num_elements = input_batches * unit_count; + const int32_t loop_count = (num_elements + 3) / 4; + for (int i_op = 0; i_op < loop_count; i_op++) + { + mve_pred16_t p = vctp32q((uint32_t)num_elements); + int32x4_t op = vldrwq_z_s32(buffer_b, p); + op = arm_requantize_mve(op, multiplier_out, shift_2); + op = vaddq_n_s32(op, zp_out); + const int32x4_t min_vec = vdupq_n_s32((int8_t)out_activation_min); + const int32x4_t max_vec = vdupq_n_s32((int8_t)out_activation_max); + op = vmaxq_s32(op, min_vec); + op = vminq_s32(op, max_vec); + vstrbq_p_s32(output_data, op, p); + output_data += 4; + buffer_b += 4; + num_elements -= 4; + } +#else + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + arm_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } +#endif + + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of SVDF group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c new file mode 100644 index 0000000..d804121 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c @@ -0,0 +1,271 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_svdf_s8.c + * Description: S8 basic SVDF layer function with s16 state tensor + * + * $Date: 4 May 2022 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M processors + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite with 16 bit state tensor + * + * Refer to header file for details. + * + */ + +arm_cmsis_nn_status arm_svdf_state_s16_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q15_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + if (input_ctx->buf == NULL) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + q31_t *buffer_a = (q31_t *)input_ctx->buf; + + if (output_ctx->buf == NULL) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + q31_t *buffer_b = (q31_t *)output_ctx->buf; + + // Left shift state + memmove((q15_t *)state_data, + (q15_t *)state_data + 1, + (size_t)((input_batches * feature_batches * time_batches - 1) * (int32_t)sizeof(int16_t))); + + // Matrix multiplication input * feature weight + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q15_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + arm_cmsis_nn_status res = arm_nn_vec_mat_mult_t_svdf_s8(input, + weight, + res_ptr, + -zp_in, + 0, + time_batches, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max); + + if (res != ARM_CMSIS_NN_SUCCESS) + { + return res; + } + } + + { + // Matrix multiplication time weight * state tensors + q31_t *ptr_a = buffer_a; + const q15_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const q15_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + // Perform matrix multiplication in blocks of two + int j = 0; + int32_t block_count = time_batches >> 1; + for (int i = 0; i < block_count; i++) + { + j += 2; + q31_t r1 = arm_nn_read_q15x2_ia(&v1); + q31_t r2 = arm_nn_read_q15x2_ia(&v2); + + sum = __SMLAD(r1, r2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + +#if defined(ARM_MATH_MVEI) + int32_t num_elements = input_batches * unit_count; + const int32_t loop_count = (num_elements + 3) / 4; + for (int i_op = 0; i_op < loop_count; i_op++) + { + mve_pred16_t p = vctp32q((uint32_t)num_elements); + int32x4_t op = vldrwq_z_s32(buffer_b, p); + op = arm_requantize_mve(op, multiplier_out, shift_2); + op = vaddq_n_s32(op, zp_out); + const int32x4_t min_vec = vdupq_n_s32((int8_t)out_activation_min); + const int32x4_t max_vec = vdupq_n_s32((int8_t)out_activation_max); + op = vmaxq_s32(op, min_vec); + op = vminq_s32(op, max_vec); + vstrbq_p_s32(output_data, op, p); + output_data += 4; + buffer_b += 4; + num_elements -= 4; + } +#else + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + arm_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } +#endif + + return (ARM_CMSIS_NN_SUCCESS); +} + +/** + * @} end of SVDF group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c new file mode 100644 index 0000000..5328340 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c @@ -0,0 +1,151 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_softmax_common_s8.c + * Description: Softmax with s8 input and output of s8 or s16. + * + * $Date: 17 March 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M processors + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/* + * Softmax function with s8 input and output of s8 or s16. + * + * Refer header file for details. + * + */ +void arm_nn_softmax_common_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + const bool int16_output, + void *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ(sum); + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + int32_t bits_over_unit; + + if (int16_output) + { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + return; +#endif + int16_t *output_s16 = (int16_t *)output + row_idx * row_size; + + bits_over_unit = ACCUM_BITS - headroom + 15; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q15_MIN; + output_s16[col] = (int16_t)CLAMP(res, (int32_t)NN_Q15_MAX, (int32_t)NN_Q15_MIN); + } + else + { + output_s16[col] = NN_Q15_MIN; + } + } + } + else + { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I8 + return; +#endif + int8_t *output_s8 = (int8_t *)output + row_idx * row_size; + + bits_over_unit = ACCUM_BITS - headroom + 23; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q7_MIN; + output_s8[col] = (int8_t)CLAMP(res, (int32_t)NN_Q7_MAX, (int32_t)NN_Q7_MIN); + } + else + { + output_s8[col] = NN_Q7_MIN; + } + } + } + + input += row_size; + } +} + +/** + * @} end of NNBasicMath group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c new file mode 100644 index 0000000..550c111 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c @@ -0,0 +1,118 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2018, 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/* + * Q15 softmax function + * + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17 + base - vec_in[i], 5); + p_out[i] = (q15_t)__SSAT((output_base >> shift), 16); + } + else + { + p_out[i] = 0; + } + } +} + +/** + * @} end of Softmax group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c new file mode 100644 index 0000000..bb37660 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c @@ -0,0 +1,106 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2020, 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/* + * Q7 softmax function + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -128; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - (1 << 3); + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 3); + sum += 0x1 << shift; + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = (1 << 20) / sum; + + for (i = 0; i < dim_vec; i++) + { + + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13 + base - vec_in[i], 5); + p_out[i] = (q7_t)__SSAT((output_base >> shift), 8); + } +} + +/** + * @} end of Softmax group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c new file mode 100644 index 0000000..be45eae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c @@ -0,0 +1,126 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s16.c + * Description: S16 softmax function + * + * $Date: 19 April 2022 + * $Revision: V.2.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @addtogroup Softmax + * @{ + */ + +arm_cmsis_nn_status arm_softmax_s16(const int16_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const cmsis_nn_softmax_lut_s16 *softmax_params, + int16_t *output) +{ + int32_t col = 0; + int32_t row_idx; + + if (softmax_params->exp_lut == NULL || softmax_params->one_by_one_lut == NULL) + { + return ARM_CMSIS_NN_ARG_ERROR; + } + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int16_t max = *input; + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + int16_t *cached_exp_results = output; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + const int32_t scaled_diff = arm_nn_requantize(diff, mult, shift); + const int32_t symmetric_scaled_diff = scaled_diff + NN_Q15_MAX; + const int16_t saturated_symmetric_scaled_diff = MIN(MAX(symmetric_scaled_diff, NN_Q15_MIN), NN_Q15_MAX); + + // Lookup from exp table and cache result for next step + const int16_t index = (256 + (saturated_symmetric_scaled_diff >> 7)); + const int16_t offset = saturated_symmetric_scaled_diff & 0x7f; + const int16_t base = softmax_params->exp_lut[index]; + const int16_t slope = softmax_params->exp_lut[index + 1] - softmax_params->exp_lut[index]; + const int16_t delta = (slope * offset + 64) >> 7; + const int16_t result = (base + delta); + cached_exp_results[col] = result; + + sum += cached_exp_results[col]; + } + + const int32_t headroom = __CLZ(sum); + + // Compute the reciprocal 1/sum + const int32_t shifted_sum = (((sum) << (headroom - 1)) + (1 << 13)) >> 14; + + // Since LUT computes 1/(1 + x), compute x = (sum - 1) => -65536 + // Since LUT expects a symmetrical input, recenter from [UINT16_MIN, UINT16_MAX] to [INT16_MIN, INT16_MAX] => + // -32768 ==> So in total -65536 -32768 => -98304 + const int16_t symmetric_shifted_sum = shifted_sum - 98304; + + // Lookup from one by one table + const int16_t index = (256 + (symmetric_shifted_sum >> 7)); + const int16_t offset = symmetric_shifted_sum & 0x7f; + const int16_t base = softmax_params->one_by_one_lut[index]; + const int16_t slope = softmax_params->one_by_one_lut[index + 1] - softmax_params->one_by_one_lut[index]; + const int16_t delta = (slope * offset + 64) >> 7; + const int16_t one_by_one_result = (base + delta); + + for (col = 0; col < row_size; ++col) + { + const int16_t right_shift = 30 - headroom; + int32_t result = (cached_exp_results[col] * one_by_one_result) >> right_shift; + result = (result + 1) >> 1; // Last shift position and insert round + output[col] = (int16_t)result; + } + + output += row_size; + input += row_size; + } + + return ARM_CMSIS_NN_SUCCESS; +} + +/** + * @} end of Softmax group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c new file mode 100644 index 0000000..2de8707 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c @@ -0,0 +1,219 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s8.c + * Description: S8 softmax function + * + * $Date: 9 March 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +#ifdef ARM_MATH_MVEI +static int32x4_t arm_exp_on_negative_values_mve_32x4(int32x4_t val) +{ +#define SHIFT_START (24) + int32_t shift = SHIFT_START; + int32x4_t mask; + + const int32x4_t val_mod_minus_quarter = + vandq_s32(val, vdupq_n_s32((1 << SHIFT_START) - 1)) - vdupq_n_s32(1 << SHIFT_START); + const int32x4_t remainder = vsubq_s32(val_mod_minus_quarter, val); + const int32x4_t x = vaddq_n_s32(val_mod_minus_quarter << 5, 1 << 28); + const int32x4_t x2 = MUL_SAT_MVE(x, x); + const int32x4_t op_1 = DIV_POW2_MVE(MUL_SAT_MVE(x2, x2), 2) + MUL_SAT_MVE(x2, x); + const int32x4_t op_2 = x + DIV_POW2_MVE(MUL_SAT_MVE(op_1, vdupq_n_s32(715827883)) + x2, 1); + int32x4_t result = vdupq_n_s32(1895147668) + MUL_SAT_MVE(vdupq_n_s32(1895147668), op_2); + +#define SELECT_IF_NON_ZERO(x) \ + { \ + mve_pred16_t p = vcmpneq_n_s32(remainder & vdupq_n_s32(1 << shift++), 0); \ + mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p); \ + result = SELECT_USING_MASK(mask, MUL_SAT_MVE(result, vdupq_n_s32(x)), result); \ + } + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mve_pred16_t p = vcmpeqq_n_s32(val, 0); + mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p); + + result = SELECT_USING_MASK(mask, vdupq_n_s32(NN_Q31_MAX), result); + return result; +} +#endif + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void arm_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output) +{ +#ifdef ARM_MATH_MVEI + +#define ACT_MIN ((int8_t)NN_Q7_MIN) +#define ACT_MAX ((int8_t)NN_Q7_MAX) + + const int32_t mask = (1 << shift); + + for (int i_num_rows = 0; i_num_rows < num_rows; ++i_num_rows) + { + int8_t max = ACT_MIN; + + int32_t vec_count = (row_size + 15) / 16; + uint32_t r_count = (uint32_t)row_size; + for (int i = 0; i < vec_count; i++) + { + mve_pred16_t p = vctp8q(r_count); + const int8x16_t ip = vldrbq_z_s8(&input[i * 16], p); + max = vmaxvq_p_s8(max, ip, p); + r_count -= 16; + } + + vec_count = row_size / 4; + int32_t idx = 0; + int32_t sum = 0; + + while (vec_count) + { + int32x4_t ip = vldrbq_s32(&input[idx * 4]); + ip = vsubq_n_s32(ip, max); + mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min); + if (p != 0) + { + ip = vmulq_n_s32(ip, mask); + + int32x4_t res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); + + res = arm_exp_on_negative_values_mve_32x4(res); + res = DIV_POW2_MVE(res, ACCUM_BITS); + res = vpselq_s32(res, vdupq_n_s32(0), p); + sum += vaddvq_s32(res); + } + + vec_count--; + idx++; + } + + const int32_t tail_idx = row_size & ~3; + for (int i = 0; i < (row_size & 3); i++) + { + const int32_t diff = input[tail_idx + i] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + + vec_count = row_size / 4; + idx = 0; + + while (vec_count) + { + int32x4_t ip = vldrbq_s32(&input[idx]); + ip = vsubq_n_s32(ip, max); + + mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min); + + int32x4_t tmp_res; + + if (p != 0) + { + ip = vmulq_n_s32(ip, mask); + + tmp_res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); + tmp_res = arm_exp_on_negative_values_mve_32x4(tmp_res); + tmp_res = MUL_SAT_MVE(vdupq_n_s32(shifted_scale), tmp_res); + tmp_res = DIV_POW2_MVE(tmp_res, bits_over_unit); + tmp_res += vdupq_n_s32(ACT_MIN); + + tmp_res = vmaxq_s32(tmp_res, vdupq_n_s32(ACT_MIN)); + tmp_res = vminq_s32(tmp_res, vdupq_n_s32(ACT_MAX)); + tmp_res = vpselq_s32(tmp_res, vdupq_n_s32(ACT_MIN), p); + } + else + { + tmp_res = vdupq_n_s32(ACT_MIN); + } + vstrbq_s32(&output[idx], tmp_res); + vec_count--; + idx += 4; + } + + for (int i = 0; i < (row_size & 3); i++) + { + int32_t diff = input[tail_idx + i] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q7_MIN; + output[tail_idx + i] = (int8_t)CLAMP(res, (int32_t)ACT_MAX, (int32_t)ACT_MIN); + } + else + { + output[tail_idx + i] = ACT_MIN; + } + } + + input += row_size; + output += row_size; + } +#else + arm_nn_softmax_common_s8(input, num_rows, row_size, mult, shift, diff_min, false, (void *)output); +#endif +} + +/** + * @} end of Softmax group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c new file mode 100644 index 0000000..a6eb67a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c @@ -0,0 +1,59 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s8_s16.c + * Description: S8 to s16 softmax function + * + * $Date: 7 January 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void arm_softmax_s8_s16(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int16_t *output) +{ + arm_nn_softmax_common_s8(input, num_rows, row_size, mult, shift, diff_min, true, (void *)output); +} +/** + * @} end of Softmax group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c new file mode 100644 index 0000000..a9b27fb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c @@ -0,0 +1,106 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_u8.c + * Description: U8 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ +void arm_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + uint8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum << headroom) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit); + output[col] = (uint8_t)CLAMP(res, (int32_t)255, (int32_t)0); + } + else + { + output[col] = 0; + } + } + input += row_size; + output += row_size; + } +} +/** + * @} end of Softmax group + */ +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c new file mode 100644 index 0000000..25220fe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c @@ -0,0 +1,74 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES +/* + * SPDX-FileCopyrightText: Copyright 2010-2019, 2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_with_batch_q7.c + * Description: Q7 softmax function + * + * $Date: 4 Aug 2022 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/* + * Q7 softmax function with batch parameter + * + * details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out) +{ + for (int i = 0; i < nb_batches; i++) + { + arm_softmax_q7(vec_in, dim_vec, p_out); + vec_in += dim_vec; + p_out += dim_vec; + } +} + +/** + * @} end of Softmax group + */ + +#endif // EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/sources.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/sources.txt new file mode 100644 index 0000000..a8db8ad --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/CMSIS/sources.txt @@ -0,0 +1 @@ +Created by update_tflite.sh diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/LICENSE b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/LICENSE new file mode 100644 index 0000000..7c3542e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/LICENSE @@ -0,0 +1,10 @@ +Unless specifically indicated otherwise in a file, files are licensed under the Apache 2.0 license, as can be found in: LICENSE-apache-2.0.txt + +Folders containing files under different permissive license than Apache 2.0 are listed below. Each folder contains its own license specified for its files. + +* CMSIS - Apache 2.0 +* dsp/kissfft - BSD-3-Clause +* dsp/dct - MIT +* tensorflow - Apache 2.0 +* third_party/flatbuffers - Apache 2.0 +* third_party/gemmlowp - Apache 2.0 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/LICENSE-apache-2.0.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/LICENSE-apache-2.0.txt new file mode 100644 index 0000000..0cdd12c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/LICENSE-apache-2.0.txt @@ -0,0 +1,165 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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However, +in accepting such obligations, You may act only on Your own behalf and on Your +sole responsibility, not on behalf of any other Contributor, and only if You +agree to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/README.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/README.md new file mode 100644 index 0000000..d635729 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/README.md @@ -0,0 +1,9 @@ +# Edge Impulse DSP and Inferencing SDK + +Portable library for digital signal processing and machine learning inferencing. This repository contains the device implementation in C++ for both processing and learning blocks in [Edge Impulse](https://www.edgeimpulse.com). + +[Documentation](https://docs.edgeimpulse.com/reference#inferencing-sdk) + +## Develop locally + +If you want to develop locally the easiest is to grab the [example-standalone-inferencing](https://github.com/edgeimpulse/example-standalone-inferencing) (Desktop) or [example-standalone-inferencing-mbed](https://github.com/edgeimpulse/example-standalone-inferencing-mbed) (ST IoT Discovery Kit, f.e. to test CMSIS-DSP / CMSIS-NN integration) example applications, add your Edge Impulse project (use the C++ Library export option), then symlink this repository in. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_aligned_malloc.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_aligned_malloc.h new file mode 100644 index 0000000..7ef1a26 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_aligned_malloc.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_ALIGNED_MALLOC_H_ +#define _EDGE_IMPULSE_ALIGNED_MALLOC_H_ + +#include +#include "../porting/ei_classifier_porting.h" + +#ifdef __cplusplus +namespace { +#endif // __cplusplus + +/** +* Based on https://github.com/embeddedartistry/embedded-resources/blob/master/examples/c/malloc_aligned.c +*/ + +/** +* Simple macro for making sure memory addresses are aligned +* to the nearest power of two +*/ +#ifndef align_up +#define align_up(num, align) \ + (((num) + ((align) - 1)) & ~((align) - 1)) +#endif + +//Number of bytes we're using for storing the aligned pointer offset +typedef uint16_t offset_t; +#define PTR_OFFSET_SZ sizeof(offset_t) + +/** +* aligned_malloc takes in the requested alignment and size +* We will call malloc with extra bytes for our header and the offset +* required to guarantee the desired alignment. +*/ +__attribute__((unused)) void * ei_aligned_calloc(size_t align, size_t size) +{ + void * ptr = NULL; + + //We want it to be a power of two since align_up operates on powers of two + assert((align & (align - 1)) == 0); + + if(align && size) + { + /* + * We know we have to fit an offset value + * We also allocate extra bytes to ensure we can meet the alignment + */ + uint32_t hdr_size = PTR_OFFSET_SZ + (align - 1); + void * p = ei_calloc(size + hdr_size, 1); + + if(p) + { + /* + * Add the offset size to malloc's pointer (we will always store that) + * Then align the resulting value to the arget alignment + */ + ptr = (void *) align_up(((uintptr_t)p + PTR_OFFSET_SZ), align); + + //Calculate the offset and store it behind our aligned pointer + *((offset_t *)ptr - 1) = (offset_t)((uintptr_t)ptr - (uintptr_t)p); + + } // else NULL, could not malloc + } //else NULL, invalid arguments + + return ptr; +} + +/** +* aligned_free works like free(), but we work backwards from the returned +* pointer to find the correct offset and pointer location to return to free() +* Note that it is VERY BAD to call free() on an aligned_malloc() pointer. +*/ +__attribute__((unused)) void ei_aligned_free(void * ptr) +{ + assert(ptr); + + /* + * Walk backwards from the passed-in pointer to get the pointer offset + * We convert to an offset_t pointer and rely on pointer math to get the data + */ + offset_t offset = *((offset_t *)ptr - 1); + + /* + * Once we have the offset, we can get our original pointer and call free + */ + void * p = (void *)((uint8_t *)ptr - offset); + ei_free(p); +} + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // _EDGE_IMPULSE_ALIGNED_MALLOC_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_config.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_config.h new file mode 100644 index 0000000..8865a85 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_config.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_CONFIG_H_ +#define _EI_CLASSIFIER_CONFIG_H_ + +// clang-format off + +// This is a file that's only used in benchmarking to override HW optimized kernels +#ifdef __has_include + #if __has_include("source/benchmark.h") + #include "source/benchmark.h" + #endif +#endif + +#if EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP == 1 + #define EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN 0 + #define EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES 1 +#endif + +#ifndef EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN +#if defined(__MBED__) + #include "mbed_version.h" + #if (MBED_VERSION < MBED_ENCODE_VERSION((5), (7), (0))) + #define EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN 0 + #else + #define EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN 1 + #endif // Mbed OS 5.7 version check + +// __ARM_ARCH_PROFILE is a predefine of arm-gcc. __TARGET_* is armcc +#elif __ARM_ARCH_PROFILE == 'M' || defined(__TARGET_CPU_CORTEX_M0) || defined(__TARGET_CPU_CORTEX_M0PLUS) || defined(__TARGET_CPU_CORTEX_M3) || defined(__TARGET_CPU_CORTEX_M4) || defined(__TARGET_CPU_CORTEX_M7) || defined(ARDUINO_NRF52_ADAFRUIT) + #define EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN 1 +#else + #define EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN 0 +#endif +#endif // EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN + +// CMSIS-NN falls back to reference kernels when __ARM_FEATURE_DSP and __ARM_FEATURE_MVE are not defined +// we should never use those... So disable CMSIS-NN in that case and throw a warning +#if EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 + #if !defined(__ARM_FEATURE_DSP) && !defined(__ARM_FEATURE_MVE) + #pragma message( \ + "CMSIS-NN enabled, but neither __ARM_FEATURE_DSP nor __ARM_FEATURE_MVE defined. Falling back.") + #undef EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN + #define EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN 0 + #endif +#endif // EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 + +#if EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +#define CMSIS_NN 1 +#define EI_CLASSIFIER_TFLITE_LOAD_CMSIS_NN_SOURCES 1 +#endif + +#ifndef EI_CLASSIFIER_TFLITE_ENABLE_ARC +#ifdef CPU_ARC +#define EI_CLASSIFIER_TFLITE_ENABLE_ARC 1 +#else +#define EI_CLASSIFIER_TFLITE_ENABLE_ARC 0 +#endif // CPU_ARC +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC + +#ifndef EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN + #if defined(ESP32) + #include "sdkconfig.h" + #define EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN 1 + #define ESP_NN 1 + #endif // ESP32 check + #if defined(CONFIG_IDF_TARGET_ESP32S3) + #define EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 1 + #endif // ESP32S3 check +#else + #define ESP_NN 1 +#endif + +// no include checks in the compiler? then just include metadata and then ops_define (optional if on EON model) +#ifndef __has_include + #include "model-parameters/model_metadata.h" + #if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) && (EI_CLASSIFIER_COMPILED == 1) + #include "tflite-model/trained_model_ops_define.h" + #endif +#else + #if __has_include("tflite-model/trained_model_ops_define.h") + #include "tflite-model/trained_model_ops_define.h" + #endif +#endif // __has_include + +// clang-format on +#endif // _EI_CLASSIFIER_CONFIG_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_smooth.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_smooth.h new file mode 100644 index 0000000..4f7e039 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_smooth.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_SMOOTH_H_ +#define _EI_CLASSIFIER_SMOOTH_H_ + +#if EI_CLASSIFIER_OBJECT_DETECTION != 1 + +#include + +typedef struct ei_classifier_smooth { + int *last_readings; + size_t last_readings_size; + uint8_t min_readings_same; + float classifier_confidence; + float anomaly_confidence; + uint8_t count[EI_CLASSIFIER_LABEL_COUNT + 2] = { 0 }; + size_t count_size = EI_CLASSIFIER_LABEL_COUNT + 2; +} ei_classifier_smooth_t; + +/** + * Initialize a smooth structure. This is useful if you don't want to trust + * single readings, but rather want consensus + * (e.g. 7 / 10 readings should be the same before I draw any ML conclusions). + * This allocates memory on the heap! + * @param smooth Pointer to an uninitialized ei_classifier_smooth_t struct + * @param n_readings Number of readings you want to store + * @param min_readings_same Minimum readings that need to be the same before concluding (needs to be lower than n_readings) + * @param classifier_confidence Minimum confidence in a class (default 0.8) + * @param anomaly_confidence Maximum error for anomalies (default 0.3) + */ +void ei_classifier_smooth_init(ei_classifier_smooth_t *smooth, size_t n_readings, + uint8_t min_readings_same, float classifier_confidence = 0.8, + float anomaly_confidence = 0.3) { + smooth->last_readings = (int*)ei_malloc(n_readings * sizeof(int)); + for (size_t ix = 0; ix < n_readings; ix++) { + smooth->last_readings[ix] = -1; // -1 == uncertain + } + smooth->last_readings_size = n_readings; + smooth->min_readings_same = min_readings_same; + smooth->classifier_confidence = classifier_confidence; + smooth->anomaly_confidence = anomaly_confidence; + smooth->count_size = EI_CLASSIFIER_LABEL_COUNT + 2; +} + +/** + * Call when a new reading comes in. + * @param smooth Pointer to an initialized ei_classifier_smooth_t struct + * @param result Pointer to a result structure (after calling ei_run_classifier) + * @returns Label, either 'uncertain', 'anomaly', or a label from the result struct + */ +const char* ei_classifier_smooth_update(ei_classifier_smooth_t *smooth, ei_impulse_result_t *result) { + // clear out the count array + memset(smooth->count, 0, EI_CLASSIFIER_LABEL_COUNT + 2); + + // roll through the last_readings buffer + numpy::roll(smooth->last_readings, smooth->last_readings_size, -1); + + int reading = -1; // uncertain + + // print the predictions + // printf("["); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + if (result->classification[ix].value >= smooth->classifier_confidence) { + reading = (int)ix; + } + } +#if EI_CLASSIFIER_HAS_ANOMALY + if (result->anomaly >= smooth->anomaly_confidence) { + reading = -2; // anomaly + } +#endif + + smooth->last_readings[smooth->last_readings_size - 1] = reading; + + // now count last 10 readings and see what we actually see... + for (size_t ix = 0; ix < smooth->last_readings_size; ix++) { + if (smooth->last_readings[ix] >= 0) { + smooth->count[smooth->last_readings[ix]]++; + } + else if (smooth->last_readings[ix] == -1) { // uncertain + smooth->count[EI_CLASSIFIER_LABEL_COUNT]++; + } + else if (smooth->last_readings[ix] == -2) { // anomaly + smooth->count[EI_CLASSIFIER_LABEL_COUNT + 1]++; + } + } + + // then loop over the count and see which is highest + uint8_t top_result = 0; + uint8_t top_count = 0; + bool met_confidence_threshold = false; + uint8_t confidence_threshold = smooth->min_readings_same; // XX% of windows should be the same + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT + 2; ix++) { + if (smooth->count[ix] > top_count) { + top_result = ix; + top_count = smooth->count[ix]; + } + if (smooth->count[ix] >= confidence_threshold) { + met_confidence_threshold = true; + } + } + + if (met_confidence_threshold) { + if (top_result == EI_CLASSIFIER_LABEL_COUNT) { + return "uncertain"; + } + else if (top_result == EI_CLASSIFIER_LABEL_COUNT + 1) { + return "anomaly"; + } + else { + return result->classification[top_result].label; + } + } + return "uncertain"; +} + +/** + * Clear up a smooth structure + */ +void ei_classifier_smooth_free(ei_classifier_smooth_t *smooth) { + ei_free(smooth->last_readings); +} + +#endif // #if EI_CLASSIFIER_OBJECT_DETECTION != 1 + +#endif // _EI_CLASSIFIER_SMOOTH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_types.h new file mode 100644 index 0000000..1ea8732 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_classifier_types.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_RUN_CLASSIFIER_TYPES_H_ +#define _EDGE_IMPULSE_RUN_CLASSIFIER_TYPES_H_ + +#include +// needed for standalone C example +#include "model-parameters/model_metadata.h" + +#ifndef EI_CLASSIFIER_MAX_OBJECT_DETECTION_COUNT +#define EI_CLASSIFIER_MAX_OBJECT_DETECTION_COUNT 10 +#endif + +/** + * @defgroup ei_structs Structs + * + * Public-facing structs for Edge Impulse C++ SDK. + * + * @addtogroup ei_structs + * @{ + */ + +/** + * @brief Holds the output of inference, anomaly results, and timing information. + * + * `ei_impulse_result_t` holds the output of `run_classifier()`. If object detection is + * enabled, then the output results is a + * pointer to an array of bounding boxes of size `bounding_boxes_count`, as given by + * [ei_impulse_result_bounding_box_t](https://docs.edgeimpulse.com/reference/ei_impulse_result_bounding_box_t). + * Otherwise, results are stored as an array of classification scores, as given by + * [ei_impulse_result_classification_t](https://docs.edgeimpulse.com/reference/ei_impulse_result_classification_t). + * + * If anomaly detection is enabled (e.g. `EI_CLASSIFIER_HAS_ANOMALY == 1`), then the + * anomaly score will be stored as a floating point value in `anomaly`. + * + * Timing information is stored in an + * [ei_impulse_result_timing_t](https://docs.edgeimpulse.com/reference/ei_impulse_result_timing_t) + * struct. + * + * **Source**: [classifier/ei_classifier_types.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/classifier/ei_classifier_types.h) + * + * **Example**: [standalone inferencing main.cpp](https://github.com/edgeimpulse/example-standalone-inferencing/blob/master/source/main.cpp) + */ +typedef struct { + /** + * Label of the detected object + */ + const char *label; + + /** + * Value of the detected object + */ + float value; +} ei_impulse_result_classification_t; + +/** + * @brief Holds the output of visual anomaly detection (FOMO-AD) + * + * If visual anomaly detection is enabled (e.g. `EI_CLASSIFIER_HAS_VISUAL_ANOMALY == + * 1`), then the output results will be a pointer to an array of grid cells of size + * `visual_ad_count`, as given by + * [ei_impulse_result_bounding_box_t](https://docs.edgeimpulse.com/reference/ei_impulse_result_bounding_box_t). + * + * The visual anomaly detection result is stored in `visual_ad_result`, which contains the mean and max values of the grid cells. + * + * **Source**: [classifier/ei_classifier_types.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/classifier/ei_classifier_types.h) + * + * **Example**: [standalone inferencing main.cpp](https://github.com/edgeimpulse/example-standalone-inferencing/blob/master/source/main.cpp) +*/ +typedef struct { + /** + * Mean value of the grid cells + */ + float mean_value; + + /** + * Max value of the grid cells + */ + float max_value; +} ei_impulse_visual_ad_result_t; + +/** + * @brief Holds information for a single bounding box. + * + * If object detection is enabled (i.e. `EI_CLASSIFIER_OBJECT_DETECTION == 1`), then + * inference results will be one or more bounding boxes. The bounding boxes with the + * highest confidence scores (assuming those scores are equal to or greater than + * `EI_CLASSIFIER_OBJECT_DETECTION_THRESHOLD`), given by the `value` member, are + * returned from inference. The total number of bounding boxes returned will be at + * least `EI_CLASSIFIER_OBJECT_DETECTION_COUNT`. The exact number of bounding boxes + * is stored in `bounding_boxes_count` field of [ei_impulse_result_t]/C++ Inference + * SDK Library/structs/ei_impulse_result_t.md). + * + * A bounding box is a rectangle that ideally surrounds the identified object. The + * (`x`, `y`) coordinates in the struct identify the top-left corner of the box. + * `label` is the predicted class with the highest confidence score. `value` is the + * confidence score between [0.0..1.0] of the given `label`. + * + * **Source**: [classifier/ei_classifier_types.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/classifier/ei_classifier_types.h) + * + * **Example**: [standalone inferencing main.cpp](https://github.com/edgeimpulse/example-standalone-inferencing/blob/master/source/main.cpp) +*/ +typedef struct { + /** + * Pointer to a character array describing the associated class of the given + * bounding box. Taken from one of the elements of + * `ei_classifier_inferencing_categories[]`. + */ + const char *label; + + /** + * x coordinate of the top-left corner of the bounding box + */ + uint32_t x; + + /** + * y coordinate of the top-left corner of the bounding box + */ + uint32_t y; + + /** + * Width of the bounding box + */ + uint32_t width; + + /** + * Height of the bounding box + */ + uint32_t height; + + /** + * Confidence score of the label describing the bounding box + */ + float value; +} ei_impulse_result_bounding_box_t; + +/** + * @brief Holds timing information about the processing (DSP) and inference blocks. + * + * Records timing information during the execution of the preprocessing (DSP) and + * inference blocks. Can be used to determine if inference will meet timing requirements + * on your particular platform. + * + * **Source**: [classifier/ei_classifier_types.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/classifier/ei_classifier_types.h) + * + * **Example**: [standalone inferencing main.cpp](https://github.com/edgeimpulse/example-standalone-inferencing/blob/master/source/main.cpp) + */ +typedef struct { + /** + * If using `run_impulse()` to perform sampling and inference, it is the amount of + * time (in milliseconds) it took to fetch raw samples. Not used for + * `run_classifier()`. + */ + int sampling; + + /** + * Amount of time (in milliseconds) it took to run the preprocessing (DSP) block + */ + int dsp; + + /** + * Amount of time (in milliseconds) it took to run the inference block + */ + int classification; + + /** + * Amount of time (in milliseconds) it took to run anomaly detection. Valid only if + * `EI_CLASSIFIER_HAS_ANOMALY == 1`. + */ + int anomaly; + + /** + * Amount of time (in microseconds) it took to run the post-processing block + */ + int64_t dsp_us; + + /** + * Amount of time (in microseconds) it took to run the inference block + */ + int64_t classification_us; + + /** + * Amount of time (in microseconds) it took to run anomaly detection. Valid only if + * `EI_CLASSIFIER_HAS_ANOMALY == 1`. + */ + int64_t anomaly_us; +} ei_impulse_result_timing_t; + +/** + * @brief Holds the output of inference, anomaly results, and timing information. + * + * `ei_impulse_result_t` holds the output of `run_classifier()`. If object detection is + * enabled (e.g. `EI_CLASSIFIER_OBJECT_DETECTION == 1`), then the output results is a + * pointer to an array of bounding boxes of size `bounding_boxes_count`, as given by + * [ei_impulse_result_bounding_box_t](https://docs.edgeimpulse.com/reference/ei_impulse_result_bounding_box_t). + * Otherwise, results are stored as an array of classification scores, as given by + * [ei_impulse_result_classification_t](https://docs.edgeimpulse.com/reference/ei_impulse_result_classification_t). + * + * If anomaly detection is enabled (e.g. `EI_CLASSIFIER_HAS_ANOMALY == 1`), then the + * anomaly score will be stored as a floating point value in `anomaly`. + * + * Timing information is stored in an + * [ei_impulse_result_timing_t](https://docs.edgeimpulse.com/reference/ei_impulse_result_timing_t) + * struct. + * + * **Source**: [classifier/ei_classifier_types.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/classifier/ei_classifier_types.h) + * + * **Example**: [standalone inferencing main.cpp](https://github.com/edgeimpulse/example-standalone-inferencing/blob/master/source/main.cpp) + */ +typedef struct { + /** + * Array of bounding boxes of the detected objects, if object detection is enabled. + */ + ei_impulse_result_bounding_box_t *bounding_boxes; + + /** + * Number of bounding boxes detected. If object detection is not enabled, this will + * be 0. + */ + uint32_t bounding_boxes_count; + + /** + * Array of classification results. If object detection is enabled, this will be + * empty. + */ +#ifdef EI_DSP_RESULT_OVERRIDE + // For CI only. We will create the array to hold results + ei_impulse_result_classification_t* classification; +#else +#if EI_CLASSIFIER_LABEL_COUNT == 0 + // EI_CLASSIFIER_LABEL_COUNT can be 0 for anomaly only models + // to prevent compiler warnings/errors, we need to have at least one element + ei_impulse_result_classification_t classification[1]; +#else + ei_impulse_result_classification_t classification[EI_CLASSIFIER_LABEL_COUNT]; +#endif // EI_CLASSIFIER_LABEL_COUNT == 0 +#endif // EI_DSP_RESULT_OVERRIDE else + + /** + * Anomaly score. If anomaly detection is not enabled, this will be 0. A higher + * anomaly score indicates greater likelihood of an anomalous sample (e.g. it is + * farther away from its cluster). + */ + float anomaly; + + /** + * Timing information for the processing (DSP) and inference blocks. + */ + ei_impulse_result_timing_t timing; + + /** + * Copy the output data to a buffer. If set to false, the output data will be + * returned as a pointer to the internal buffer. If set to true, the output data + * will be copied to the buffer provided in `ei_impulse_output_t`. + */ + bool copy_output; +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY || __DOXYGEN__ + /** + * Array of grid cells of the detected visual anomalies, if visual anomaly detection + * is enabled. + */ + ei_impulse_result_bounding_box_t *visual_ad_grid_cells; + + /** + * Number of grid cells detected as visual anomalies, if visual anomaly detection is + * enabled. + */ + uint32_t visual_ad_count; + + /** + * Visual anomaly detection result, if visual anomaly detection is enabled. + */ + ei_impulse_visual_ad_result_t visual_ad_result; +#endif // EI_CLASSIFIER_HAS_VISUAL_ANOMALY +} ei_impulse_result_t; + +/** @} */ + +#endif // _EDGE_IMPULSE_RUN_CLASSIFIER_TYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_fill_result_struct.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_fill_result_struct.h new file mode 100644 index 0000000..e3bfd04 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_fill_result_struct.h @@ -0,0 +1,1741 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_FILL_RESULT_STRUCT_H_ +#define _EI_CLASSIFIER_FILL_RESULT_STRUCT_H_ + +using namespace ei; + +#include "model-parameters/model_metadata.h" +#if EI_CLASSIFIER_HAS_MODEL_VARIABLES == 1 +#include "model-parameters/model_variables.h" +#endif +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/classifier/ei_classifier_types.h" +#include "edge-impulse-sdk/classifier/ei_nms.h" +#include "edge-impulse-sdk/dsp/ei_vector.h" + +#ifndef EI_HAS_OBJECT_DETECTION + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_SSD) + #define EI_HAS_SSD 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_FOMO) + #define EI_HAS_FOMO 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI) + #define EI_HAS_YOLOV5 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOX) + #define EI_HAS_YOLOX 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV7) + #define EI_HAS_YOLOV7 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_RETINANET) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_SSD) + #define EI_HAS_TAO_DECODE_DETECTIONS 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4) + #define EI_HAS_TAO_YOLO 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3) + #define EI_HAS_TAO_YOLOV3 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4) + #define EI_HAS_TAO_YOLOV4 1 + #endif + #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV2) + #define EI_HAS_YOLOV2 1 + #endif +#endif + +__attribute__((unused)) inline float sigmoid(float a) { + return 1.0f / (1.0f + exp(-a)); +} + +#ifdef EI_HAS_FOMO +typedef struct cube { + size_t x; + size_t y; + size_t width; + size_t height; + float confidence; + const char *label; +} ei_classifier_cube_t; + +/** + * Checks whether a new section overlaps with a cube, + * and if so, will **update the cube** + */ +__attribute__((unused)) static bool ei_cube_check_overlap(ei_classifier_cube_t *c, int x, int y, int width, int height, float confidence) { + bool is_overlapping = !(c->x + c->width < x || c->y + c->height < y || c->x > x + width || c->y > y + height); + if (!is_overlapping) return false; + + // if we overlap, but the x of the new box is lower than the x of the current box + if (x < c->x) { + // update x to match new box and make width larger (by the diff between the boxes) + c->x = x; + c->width += c->x - x; + } + // if we overlap, but the y of the new box is lower than the y of the current box + if (y < c->y) { + // update y to match new box and make height larger (by the diff between the boxes) + c->y = y; + c->height += c->y - y; + } + // if we overlap, and x+width of the new box is higher than the x+width of the current box + if (x + width > c->x + c->width) { + // just make the box wider + c->width += (x + width) - (c->x + c->width); + } + // if we overlap, and y+height of the new box is higher than the y+height of the current box + if (y + height > c->y + c->height) { + // just make the box higher + c->height += (y + height) - (c->y + c->height); + } + // if the new box has higher confidence, then override confidence of the whole box + if (confidence > c->confidence) { + c->confidence = confidence; + } + return true; +} + +__attribute__((unused)) static void ei_handle_cube(std::vector *cubes, int x, int y, float vf, const char *label, float detection_threshold) { + if (vf < detection_threshold) return; + + bool has_overlapping = false; + int width = 1; + int height = 1; + + for (auto c : *cubes) { + // not cube for same class? continue + if (strcmp(c->label, label) != 0) continue; + + if (ei_cube_check_overlap(c, x, y, width, height, vf)) { + has_overlapping = true; + break; + } + } + + if (!has_overlapping) { + ei_classifier_cube_t *cube = new ei_classifier_cube_t(); + cube->x = x; + cube->y = y; + cube->width = 1; + cube->height = 1; + cube->confidence = vf; + cube->label = label; + cubes->push_back(cube); + } +} + +__attribute__((unused)) static void fill_result_struct_from_cubes(ei_impulse_result_t *result, std::vector *cubes, int out_width_factor, uint32_t object_detection_count) { + std::vector bbs; + static std::vector results; + int added_boxes_count = 0; + results.clear(); + for (auto sc : *cubes) { + bool has_overlapping = false; + + int x = sc->x; + int y = sc->y; + int width = sc->width; + int height = sc->height; + const char *label = sc->label; + float vf = sc->confidence; + + for (auto c : bbs) { + // not cube for same class? continue + if (strcmp(c->label, label) != 0) continue; + + if (ei_cube_check_overlap(c, x, y, width, height, vf)) { + has_overlapping = true; + break; + } + } + + if (has_overlapping) { + continue; + } + + bbs.push_back(sc); + + ei_impulse_result_bounding_box_t tmp = { + .label = sc->label, + .x = (uint32_t)(sc->x * out_width_factor), + .y = (uint32_t)(sc->y * out_width_factor), + .width = (uint32_t)(sc->width * out_width_factor), + .height = (uint32_t)(sc->height * out_width_factor), + .value = sc->confidence + }; + + results.push_back(tmp); + added_boxes_count++; + } + + // if we didn't detect min required objects, fill the rest with fixed value + if (added_boxes_count < object_detection_count) { + results.resize(object_detection_count); + for (size_t ix = added_boxes_count; ix < object_detection_count; ix++) { + results[ix].value = 0.0f; + } + } + + for (auto c : *cubes) { + delete c; + } + + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); +} +#endif + +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_fomo(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + int out_width, + int out_height) { +#ifdef EI_HAS_FOMO + std::vector cubes; + + int out_width_factor = impulse->input_width / out_width; + + for (size_t y = 0; y < out_width; y++) { + // ei_printf(" [ "); + for (size_t x = 0; x < out_height; x++) { + size_t loc = ((y * out_height) + x) * (impulse->label_count + 1); + + for (size_t ix = 1; ix < impulse->label_count + 1; ix++) { + float vf = data[loc+ix]; + + ei_handle_cube(&cubes, x, y, vf, impulse->categories[ix - 1], block_config->threshold); + } + } + } + + fill_result_struct_from_cubes(result, &cubes, out_width_factor, impulse->object_detection_count); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif +} + +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_i8_fomo(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + int8_t *data, + float zero_point, + float scale, + int out_width, + int out_height) { +#ifdef EI_HAS_FOMO + std::vector cubes; + + int out_width_factor = impulse->input_width / out_width; + + for (size_t y = 0; y < out_width; y++) { + // ei_printf(" [ "); + for (size_t x = 0; x < out_height; x++) { + size_t loc = ((y * out_height) + x) * (impulse->label_count + 1); + + for (size_t ix = 1; ix < impulse->label_count + 1; ix++) { + int8_t v = data[loc+ix]; + float vf = static_cast(v - zero_point) * scale; + + ei_handle_cube(&cubes, x, y, vf, impulse->categories[ix - 1], block_config->threshold); + } + } + } + + fill_result_struct_from_cubes(result, &cubes, out_width_factor, impulse->object_detection_count); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif +} + +/** + * Fill the result structure from an unquantized output tensor + * (we don't support quantized here a.t.m.) + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_object_detection(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + float *scores, + float *labels, + bool debug) { +#ifdef EI_HAS_SSD + static std::vector results; + results.clear(); + results.resize(impulse->object_detection_count); + for (size_t ix = 0; ix < impulse->object_detection_count; ix++) { + + float score = scores[ix]; + float label = labels[ix]; + + if (score >= block_config->threshold) { + float ystart = data[(ix * 4) + 0]; + float xstart = data[(ix * 4) + 1]; + float yend = data[(ix * 4) + 2]; + float xend = data[(ix * 4) + 3]; + + if (xstart < 0) xstart = 0; + if (xstart > 1) xstart = 1; + if (ystart < 0) ystart = 0; + if (ystart > 1) ystart = 1; + if (yend < 0) yend = 0; + if (yend > 1) yend = 1; + if (xend < 0) xend = 0; + if (xend > 1) xend = 1; + if (xend < xstart) xend = xstart; + if (yend < ystart) yend = ystart; + + if (debug) { + ei_printf("%s (", impulse->categories[(uint32_t)label]); + ei_printf_float(label); + ei_printf("): "); + ei_printf_float(score); + ei_printf(" [ "); + ei_printf_float(xstart); + ei_printf(", "); + ei_printf_float(ystart); + ei_printf(", "); + ei_printf_float(xend); + ei_printf(", "); + ei_printf_float(yend); + ei_printf(" ]\n"); + } + + results[ix].label = impulse->categories[(uint32_t)label]; + results[ix].x = static_cast(xstart * static_cast(impulse->input_width)); + results[ix].y = static_cast(ystart * static_cast(impulse->input_height)); + results[ix].width = static_cast((xend - xstart) * static_cast(impulse->input_width)); + results[ix].height = static_cast((yend - ystart) * static_cast(impulse->input_height)); + results[ix].value = score; + } + else { + results[ix].value = 0.0f; + } + } + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif +} + +/** + * Fill the result structure from a quantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_i8(const ei_impulse_t *impulse, + ei_impulse_result_t *result, + int8_t *data, + float zero_point, + float scale, + bool debug) { + for (uint32_t ix = 0; ix < impulse->label_count; ix++) { + float value = static_cast(data[ix] - zero_point) * scale; + + if (debug) { + ei_printf("%s:\t", impulse->categories[ix]); + ei_printf_float(value); + ei_printf("\n"); + } + result->classification[ix].label = impulse->categories[ix]; + result->classification[ix].value = value; + } + + return EI_IMPULSE_OK; +} + +/** + * Fill the result structure from an unquantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32(const ei_impulse_t *impulse, + ei_impulse_result_t *result, + float *data, + bool debug) { +#ifdef EI_DSP_RESULT_OVERRIDE + uint32_t stop_count = EI_DSP_RESULT_OVERRIDE; +#else + uint32_t stop_count = impulse->label_count; +#endif + for (uint32_t ix = 0; ix < stop_count; ix++) { + + float value = data[ix]; + + if (debug) { + ei_printf("%s:\t", impulse->categories[ix]); + ei_printf_float(value); + ei_printf("\n"); + } +// For testing purposes, we will have more values than labels +#ifndef EI_DSP_RESULT_OVERRIDE + result->classification[ix].label = impulse->categories[ix]; +#endif + result->classification[ix].value = value; + } + + return EI_IMPULSE_OK; +} + +/** + * Fill the visual anomaly result structures from an unquantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_visual_ad_struct_f32(const ei_impulse_t *impulse, + ei_impulse_result_t *result, + float *data, + float threshold, + bool debug) { +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + float max_val = 0; + float sum_val = 0; + // the feature extractor output will be 1/8 of input + // due to the cut-off layer chosen in MobileNetV2 + uint32_t grid_size_x = (impulse->input_width / 8) / 2 - 1; + uint32_t grid_size_y = (impulse->input_height / 8) / 2 - 1; + + for (uint32_t ix = 0; ix < grid_size_x * grid_size_y; ix++) { + float value = data[ix]; + sum_val += value; + if (value > max_val) { + max_val = value; + } + } + + result->visual_ad_result.mean_value = sum_val / (grid_size_x * grid_size_y); + result->visual_ad_result.max_value = max_val; + + static ei_vector results; + + int added_boxes_count = 0; + results.clear(); + + for (uint32_t x = 0; x <= grid_size_x - 1; x++) { + for (uint32_t y = 0; y <= grid_size_y - 1; y++) { + if (data[x * grid_size_x + y] >= threshold) { + ei_impulse_result_bounding_box_t tmp = { + .label = "anomaly", + .x = static_cast(y * (static_cast(impulse->input_height) / grid_size_y)), + .y = static_cast(x * (static_cast(impulse->input_width) / grid_size_x)), + .width = (impulse->input_width / grid_size_x), + .height = (impulse->input_height / grid_size_y), + .value = data[x * grid_size_x + y] + }; + + results.push_back(tmp); + added_boxes_count++; + } + } + } + + // if we didn't detect min required objects, fill the rest with fixed value + if (added_boxes_count < impulse->object_detection_count) { + results.resize(impulse->object_detection_count); + for (size_t ix = added_boxes_count; ix < impulse->object_detection_count; ix++) { + results[ix].value = 0.0f; + } + } + + result->visual_ad_grid_cells = results.data(); + result->visual_ad_count = results.size(); +#endif // EI_CLASSIFIER_HAS_VISUAL_ANOMALY + return EI_IMPULSE_OK; +} + +/** + * Fill the result structure from an unquantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_yolov5(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + int version, + float *data, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_YOLOV5 + static std::vector results; + results.clear(); + + size_t col_size = 5 + impulse->label_count; + size_t row_count = output_features_count / col_size; + + for (size_t ix = 0; ix < row_count; ix++) { + size_t base_ix = ix * col_size; + float xc = data[base_ix + 0]; + float yc = data[base_ix + 1]; + float w = data[base_ix + 2]; + float h = data[base_ix + 3]; + float x = xc - (w / 2.0f); + float y = yc - (h / 2.0f); + if (x < 0) { + x = 0; + } + if (y < 0) { + y = 0; + } + if (x + w > impulse->input_width) { + w = impulse->input_width - x; + } + if (y + h > impulse->input_height) { + h = impulse->input_height - y; + } + + if (w < 0 || h < 0) { + continue; + } + + float score = data[base_ix + 4]; + + uint32_t label = 0; + for (size_t lx = 0; lx < impulse->label_count; lx++) { + float l = data[base_ix + 5 + lx]; + if (l > 0.5f) { + label = lx; + break; + } + } + + if (score >= block_config->threshold && score <= 1.0f) { + ei_impulse_result_bounding_box_t r; + r.label = impulse->categories[label]; + + if (version != 5) { + x *= static_cast(impulse->input_width); + y *= static_cast(impulse->input_height); + w *= static_cast(impulse->input_width); + h *= static_cast(impulse->input_height); + } + + r.x = static_cast(x); + r.y = static_cast(y); + r.width = static_cast(w); + r.height = static_cast(h); + r.value = score; + results.push_back(r); + } + } + + EI_IMPULSE_ERROR nms_res = ei_run_nms(impulse, &results, debug); + if (nms_res != EI_IMPULSE_OK) { + return nms_res; + } + + // if we didn't detect min required objects, fill the rest with fixed value + size_t added_boxes_count = results.size(); + size_t min_object_detection_count = impulse->object_detection_count; + if (added_boxes_count < min_object_detection_count) { + results.resize(min_object_detection_count); + for (size_t ix = added_boxes_count; ix < min_object_detection_count; ix++) { + results[ix].value = 0.0f; + } + } + + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif +} + +/** + * Fill the result structure from a quantized output tensor +*/ +template +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_quantized_yolov5(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + int version, + T *data, + float zero_point, + float scale, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_YOLOV5 + static std::vector results; + results.clear(); + + size_t col_size = 5 + impulse->label_count; + size_t row_count = output_features_count / col_size; + + for (size_t ix = 0; ix < row_count; ix++) { + size_t base_ix = ix * col_size; + float xc = (data[base_ix + 0] - zero_point) * scale; + float yc = (data[base_ix + 1] - zero_point) * scale; + float w = (data[base_ix + 2] - zero_point) * scale; + float h = (data[base_ix + 3] - zero_point) * scale; + float x = xc - (w / 2.0f); + float y = yc - (h / 2.0f); + if (x < 0) { + x = 0; + } + if (y < 0) { + y = 0; + } + if (x + w > impulse->input_width) { + w = impulse->input_width - x; + } + if (y + h > impulse->input_height) { + h = impulse->input_height - y; + } + + if (w < 0 || h < 0) { + continue; + } + + float score = (data[base_ix + 4] - zero_point) * scale; + + uint32_t label = 0; + for (size_t lx = 0; lx < impulse->label_count; lx++) { + float l = (data[base_ix + 5 + lx] - zero_point) * scale; + if (l > 0.5f) { + label = lx; + break; + } + } + + if (score >= block_config->threshold && score <= 1.0f) { + ei_impulse_result_bounding_box_t r; + r.label = ei_classifier_inferencing_categories[label]; + + if (version != 5) { + x *= static_cast(impulse->input_width); + y *= static_cast(impulse->input_height); + w *= static_cast(impulse->input_width); + h *= static_cast(impulse->input_height); + } + + r.x = static_cast(x); + r.y = static_cast(y); + r.width = static_cast(w); + r.height = static_cast(h); + r.value = score; + results.push_back(r); + } + } + + EI_IMPULSE_ERROR nms_res = ei_run_nms(impulse, &results, debug); + if (nms_res != EI_IMPULSE_OK) { + return nms_res; + } + + // if we didn't detect min required objects, fill the rest with fixed value + size_t added_boxes_count = results.size(); + size_t min_object_detection_count = impulse->object_detection_count; + if (added_boxes_count < min_object_detection_count) { + results.resize(min_object_detection_count); + for (size_t ix = added_boxes_count; ix < min_object_detection_count; ix++) { + results[ix].value = 0.0f; + } + } + + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif +} + +/** + * Fill the result structure from an unquantized output tensor + * (we don't support quantized here a.t.m.) + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_yolox(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_YOLOX + static std::vector results; + results.clear(); + + // START: def yolox_postprocess() + + // if not p6: + // strides = [8, 16, 32] + // else: + // strides = [8, 16, 32, 64] + const std::vector strides { 8, 16, 32 }; + + // hsizes = [img_size[0] // stride for stride in strides] + // wsizes = [img_size[1] // stride for stride in strides] + std::vector hsizes(strides.size()); + std::vector wsizes(strides.size()); + for (int ix = 0; ix < (int)strides.size(); ix++) { + hsizes[ix] = (int)floor((float)impulse->input_width / (float)strides[ix]); + wsizes[ix] = (int)floor((float)impulse->input_height / (float)strides[ix]); + } + + // for hsize, wsize, stride in zip(hsizes, wsizes, strides): + // grid = np.stack((xv, yv), 2).reshape(1, -1, 2) + // grids.append(grid) + // shape = grid.shape[:2] + // expanded_strides.append(np.full((*shape, 1), stride)) + std::vector grids; + std::vector expanded_strides; + + for (int ix = 0; ix < (int)strides.size(); ix++) { + int hsize = hsizes.at(ix); + int wsize = wsizes.at(ix); + int stride = strides.at(ix); + + // xv, yv = np.meshgrid(np.arange(wsize), np.arange(hsize)) + // grid = np.stack((xv, yv), 2).reshape(1, -1, 2) + matrix_i32_t *grid = new matrix_i32_t(hsize * wsize, 2); + int grid_ix = 0; + for (int h = 0; h < hsize; h++) { + for (int w = 0; w < wsize; w++) { + grid->buffer[grid_ix + 0] = w; + grid->buffer[grid_ix + 1] = h; + grid_ix += 2; + } + } + grids.push_back(grid); + + // shape = grid.shape[:2] + // expanded_strides.append(np.full((*shape, 1), stride)) + matrix_i32_t *expanded_stride = new matrix_i32_t(hsize * wsize, 1); + for (int ix = 0; ix < hsize * wsize; ix++) { + expanded_stride->buffer[ix] = stride; + } + expanded_strides.push_back(expanded_stride); + } + + // grids = np.concatenate(grids, 1) + int total_grid_rows = 0; + for (auto g : grids) { + total_grid_rows += g->rows; + } + matrix_i32_t c_grid(total_grid_rows, 2); + int c_grid_ix = 0; + for (auto g : grids) { + for (int row = 0; row < (int)g->rows; row++) { + c_grid.buffer[c_grid_ix + 0] = g->buffer[(row * 2) + 0]; + c_grid.buffer[c_grid_ix + 1] = g->buffer[(row * 2) + 1]; + c_grid_ix += 2; + } + delete g; + } + + // expanded_strides = np.concatenate(expanded_strides, 1) + int total_stride_rows = 0; + for (auto g : expanded_strides) { + total_stride_rows += g->rows; + } + matrix_i32_t c_expanded_strides(total_stride_rows, 1); + int c_expanded_strides_ix = 0; + for (auto g : expanded_strides) { + for (int row = 0; row < (int)g->rows; row++) { + c_expanded_strides.buffer[c_expanded_strides_ix + 0] = g->buffer[(row * 1) + 0]; + c_expanded_strides_ix += 1; + } + delete g; + } + + const int output_rows = output_features_count / (5 + impulse->label_count); + matrix_t outputs(output_rows, 5 + impulse->label_count, data); + for (int row = 0; row < (int)outputs.rows; row++) { + float v0 = outputs.buffer[(row * outputs.cols) + 0]; + float v1 = outputs.buffer[(row * outputs.cols) + 1]; + float v2 = outputs.buffer[(row * outputs.cols) + 2]; + float v3 = outputs.buffer[(row * outputs.cols) + 3]; + + float cgrid0 = (float)c_grid.buffer[(row * c_grid.cols) + 0]; + float cgrid1 = (float)c_grid.buffer[(row * c_grid.cols) + 1]; + + float stride = (float)c_expanded_strides.buffer[row]; + + // outputs[..., :2] = (outputs[..., :2] + grids) * expanded_strides + outputs.buffer[(row * outputs.cols) + 0] = (v0 + cgrid0) * stride; + outputs.buffer[(row * outputs.cols) + 1] = (v1 + cgrid1) * stride; + + // outputs[..., 2:4] = np.exp(outputs[..., 2:4]) * expanded_strides + outputs.buffer[(row * outputs.cols) + 2] = exp(v2) * stride; + outputs.buffer[(row * outputs.cols) + 3] = exp(v3) * stride; + } + + // END: def yolox_postprocess() + + // boxes = predictions[:, :4] + matrix_t boxes(outputs.rows, 4); + for (int row = 0; row < (int)outputs.rows; row++) { + boxes.buffer[(row * boxes.cols) + 0] = outputs.buffer[(row * outputs.cols) + 0]; + boxes.buffer[(row * boxes.cols) + 1] = outputs.buffer[(row * outputs.cols) + 1]; + boxes.buffer[(row * boxes.cols) + 2] = outputs.buffer[(row * outputs.cols) + 2]; + boxes.buffer[(row * boxes.cols) + 3] = outputs.buffer[(row * outputs.cols) + 3]; + } + + // scores = predictions[:, 4:5] * predictions[:, 5:] + matrix_t scores(outputs.rows, impulse->label_count); + for (int row = 0; row < (int)outputs.rows; row++) { + float confidence = outputs.buffer[(row * outputs.cols) + 4]; + for (int cc = 0; cc < impulse->label_count; cc++) { + scores.buffer[(row * scores.cols) + cc] = confidence * outputs.buffer[(row * outputs.cols) + (5 + cc)]; + } + } + + // iterate through scores to see if we have anything with confidence + for (int row = 0; row < (int)scores.rows; row++) { + for (int col = 0; col < (int)scores.cols; col++) { + float confidence = scores.buffer[(row * scores.cols) + col]; + + if (confidence >= block_config->threshold && confidence <= 1.0f) { + ei_impulse_result_bounding_box_t r; + r.label = impulse->categories[col]; + r.value = confidence; + + // now find the box... + float xcenter = boxes.buffer[(row * boxes.cols) + 0]; + float ycenter = boxes.buffer[(row * boxes.cols) + 1]; + float width = boxes.buffer[(row * boxes.cols) + 2]; + float height = boxes.buffer[(row * boxes.cols) + 3]; + + int x = (int)(xcenter - (width / 2.0f)); + int y = (int)(ycenter - (height / 2.0f)); + + if (x < 0) { + x = 0; + } + if (x > (int)impulse->input_width) { + x = impulse->input_width; + } + if (y < 0) { + y = 0; + } + if (y > (int)impulse->input_height) { + y = impulse->input_height; + } + + r.x = x; + r.y = y; + r.width = (int)round(width); + r.height = (int)round(height); + + results.push_back(r); + } + } + } + + EI_IMPULSE_ERROR nms_res = ei_run_nms(impulse, &results, debug); + if (nms_res != EI_IMPULSE_OK) { + return nms_res; + } + + // if we didn't detect min required objects, fill the rest with fixed value + size_t added_boxes_count = results.size(); + size_t min_object_detection_count = impulse->object_detection_count; + if (added_boxes_count < min_object_detection_count) { + results.resize(min_object_detection_count); + for (size_t ix = added_boxes_count; ix < min_object_detection_count; ix++) { + results[ix].value = 0.0f; + } + } + + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // EI_HAS_YOLOX +} + +/** + * Fill the result structure from an unquantized output tensor + * (we don't support quantized here a.t.m.) + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_yolox_detect(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + size_t output_features_count) { +#ifdef EI_HAS_YOLOX + static std::vector results; + results.clear(); + + // expected format [xmin ymin xmax ymax score label] + const int output_rows = output_features_count / 6; + matrix_t outputs(output_rows, 6, data); + + // iterate through scores to see if we have anything with confidence + for (int row = 0; row < (int)outputs.rows; row++) { + float confidence = outputs.buffer[(row * outputs.cols) + 4]; + int class_idx = (int)outputs.buffer[(row * outputs.cols) + 5]; + + if (confidence >= block_config->threshold && confidence <= 1.0f) { + ei_impulse_result_bounding_box_t r; + r.label = ei_classifier_inferencing_categories[class_idx]; + r.value = confidence; + + // now find the box... + float xmin = outputs.buffer[(row * outputs.cols) + 0]; + float ymin = outputs.buffer[(row * outputs.cols) + 1]; + float xmax = outputs.buffer[(row * outputs.cols) + 2]; + float ymax = outputs.buffer[(row * outputs.cols) + 3]; + + float width = xmax - xmin; + float height = ymax - ymin; + + int x = (int)xmin; + int y = (int)ymin; + + if (x < 0) { + x = 0; + } + if (x > (int)impulse->input_width) { + x = impulse->input_width; + } + if (y < 0) { + y = 0; + } + if (y > (int)impulse->input_height) { + y = impulse->input_height; + } + + r.x = x; + r.y = y; + r.width = (int)round(width); + r.height = (int)round(height); + + results.push_back(r); + } + } + + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // EI_HAS_YOLOX +} + +/** + * Fill the result structure from an unquantized output tensor + * (we don't support quantized here a.t.m.) + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_yolov7(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + size_t output_features_count) { +#ifdef EI_HAS_YOLOV7 + static std::vector results; + results.clear(); + + size_t col_size = 7; + size_t row_count = output_features_count / col_size; + + // output is: + // batch_id, xmin, ymin, xmax, ymax, cls_id, score + for (size_t ix = 0; ix < row_count; ix++) { + size_t base_ix = ix * col_size; + float xmin = data[base_ix + 1]; + float ymin = data[base_ix + 2]; + float xmax = data[base_ix + 3]; + float ymax = data[base_ix + 4]; + uint32_t label = (uint32_t)data[base_ix + 5]; + float score = data[base_ix + 6]; + + if (score >= block_config->threshold && score <= 1.0f) { + ei_impulse_result_bounding_box_t r; + r.label = ei_classifier_inferencing_categories[label]; + + r.x = static_cast(xmin); + r.y = static_cast(ymin); + r.width = static_cast(xmax - xmin); + r.height = static_cast(ymax - ymin); + r.value = score; + results.push_back(r); + } + } + + // if we didn't detect min required objects, fill the rest with fixed value + size_t added_boxes_count = results.size(); + size_t min_object_detection_count = impulse->object_detection_count; + if (added_boxes_count < min_object_detection_count) { + results.resize(min_object_detection_count); + for (size_t ix = added_boxes_count; ix < min_object_detection_count; ix++) { + results[ix].value = 0.0f; + } + } + + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_YOLOV7 +} + +#if (EI_HAS_TAO_DECODE_DETECTIONS == 1) || (EI_HAS_TAO_YOLO == 1) + +__attribute__((unused)) static void prepare_tao_results_common(const ei_impulse_t *impulse, + ei_impulse_result_t *result, + std::vector *results) { + #define EI_CLASSIFIER_OBJECT_DETECTION_KEEP_TOPK 200 + + // if we didn't detect min required objects, fill the rest with fixed value + size_t added_boxes_count = results->size(); + size_t object_detection_count = impulse->object_detection_count; + if (added_boxes_count < object_detection_count) { + results->resize(object_detection_count); + for (size_t ix = added_boxes_count; ix < object_detection_count; ix++) { + (*results)[ix].value = 0.0f; + } + } + + // we sort in reverse order accross all classes, + // since results for each class are pushed to the end. + std::sort(results->begin(), results->end(), [ ]( const ei_impulse_result_bounding_box_t& lhs, const ei_impulse_result_bounding_box_t& rhs ) + { + return lhs.value > rhs.value; + }); + + // keep topK + if (results->size() > EI_CLASSIFIER_OBJECT_DETECTION_KEEP_TOPK) { + results->erase(results->begin() + EI_CLASSIFIER_OBJECT_DETECTION_KEEP_TOPK, results->end()); + } + + result->bounding_boxes = results->data(); + result->bounding_boxes_count = results->size(); +} + + +#endif + +#ifdef EI_HAS_TAO_DECODE_DETECTIONS +/** + * Fill the result structure from an output tensor +*/ +template +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_tao_decode_detections_common(const ei_impulse_t *impulse, + ei_impulse_result_t *result, + T *data, + float zero_point, + float scale, + size_t output_features_count, + float threshold, + bool debug = false) { + + size_t col_size = 12 + impulse->label_count + 1; + size_t row_count = output_features_count / col_size; + + static std::vector results; + static std::vector class_results; + results.clear(); + + for (size_t cls_idx = 1; cls_idx < (size_t)(impulse->label_count + 1); cls_idx++) { + + std::vector boxes; + std::vector scores; + std::vector classes; + class_results.clear(); + + for (size_t ix = 0; ix < row_count; ix++) { + + float score = (static_cast(data[ix * col_size + cls_idx]) - zero_point) * scale; + + if ((score < threshold) || (score > 1.0f)) { + continue; + } + + // # 1. calculate boxes location + size_t base_ix = ix * col_size + col_size; // references the end of the row + + float r_12 = (static_cast(data[base_ix - 12]) - zero_point) * scale; + float r_11 = (static_cast(data[base_ix - 11]) - zero_point) * scale; + float r_10 = (static_cast(data[base_ix - 10]) - zero_point) * scale; + float r_9 = (static_cast(data[base_ix - 9]) - zero_point) * scale; + float r_8 = (static_cast(data[base_ix - 8]) - zero_point) * scale; + float r_7 = (static_cast(data[base_ix - 7]) - zero_point) * scale; + float r_6 = (static_cast(data[base_ix - 6]) - zero_point) * scale; + float r_5 = (static_cast(data[base_ix - 5]) - zero_point) * scale; + float r_4 = (static_cast(data[base_ix - 4]) - zero_point) * scale; + float r_3 = (static_cast(data[base_ix - 3]) - zero_point) * scale; + float r_2 = (static_cast(data[base_ix - 2]) - zero_point) * scale; + float r_1 = (static_cast(data[base_ix - 1]) - zero_point) * scale; + + // cx_pred = y_pred[..., -12] + // cy_pred = y_pred[..., -11] + // w_pred = y_pred[..., -10] + // h_pred = y_pred[..., -9] + float cx_pred = r_12; + float cy_pred = r_11; + float w_pred = r_10; + float h_pred = r_9; + + // w_anchor = y_pred[..., -6] - y_pred[..., -8] + // h_anchor = y_pred[..., -5] - y_pred[..., -7] + float w_anchor = r_6 - r_8; + float h_anchor = r_5 - r_7; + + // cx_anchor = tf.truediv(y_pred[..., -6] + y_pred[..., -8], 2.0) + // cy_anchor = tf.truediv(y_pred[..., -5] + y_pred[..., -7], 2.0) + float cx_anchor = (r_6 + r_8) / 2.0f; + float cy_anchor = (r_5 + r_7) / 2.0f; + + // cx_variance = y_pred[..., -4] + // cy_variance = y_pred[..., -3] + float cx_variance = r_4; + float cy_variance = r_3; + + // variance_w = y_pred[..., -2] + // variance_h = y_pred[..., -1] + float variance_w = r_2; + float variance_h = r_1; + + // # Convert anchor box offsets to image offsets. + // cx = cx_pred * cx_variance * w_anchor + cx_anchor + // cy = cy_pred * cy_variance * h_anchor + cy_anchor + // w = tf.exp(w_pred * variance_w) * w_anchor + // h = tf.exp(h_pred * variance_h) * h_anchor + float cx = cx_pred * cx_variance * w_anchor + cx_anchor; + float cy = cy_pred * cy_variance * h_anchor + cy_anchor; + float w = exp(w_pred * variance_w) * w_anchor; + float h = exp(h_pred * variance_h) * h_anchor; + + // # Convert 'centroids' to 'corners'. + float xmin = cx - (w / 2.0f); + float ymin = cy - (h / 2.0f); + float xmax = cx + (w / 2.0f); + float ymax = cy + (h / 2.0f); + + xmin *= impulse->input_width; + ymin *= impulse->input_height; + xmax *= impulse->input_width; + ymax *= impulse->input_height; + + boxes.push_back(ymin); + boxes.push_back(xmin); + boxes.push_back(ymax); + boxes.push_back(xmax); + scores.push_back(score); + classes.push_back((int)(cls_idx-1)); + } + + size_t nr_boxes = scores.size(); + EI_IMPULSE_ERROR nms_res = ei_run_nms(impulse, &class_results, + boxes.data(), scores.data(), classes.data(), + nr_boxes, + true /*clip_boxes*/, + debug); + + if (nms_res != EI_IMPULSE_OK) { + return nms_res; + } + + for (auto bb: class_results) { + results.push_back(bb); + } + } + + prepare_tao_results_common(impulse, result, &results); + + return EI_IMPULSE_OK; +} +#endif // #ifdef EI_HAS_TAO_DETECT_DETECTIONS + +/** + * Fill the result structure from a quantized output tensor +*/ +template +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_quantized_tao_decode_detections(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + T *data, + float zero_point, + float scale, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_TAO_DECODE_DETECTIONS + return fill_result_struct_tao_decode_detections_common(impulse, result, data, zero_point, scale, output_features_count, block_config->threshold, debug); +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_TAO_DETECT_DETECTIONS +} + + +/** + * Fill the result structure from an unquantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_tao_decode_detections(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_TAO_DECODE_DETECTIONS + return fill_result_struct_tao_decode_detections_common(impulse, result, data, 0.0f, 1.0f, output_features_count, block_config->threshold, debug); +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_TAO_DETECT_DETECTIONS +} + +#ifdef EI_HAS_TAO_YOLOV3 +/** + * Fill the result structure from an output tensor +*/ +template +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_tao_yolov3_common(const ei_impulse_t *impulse, + ei_impulse_result_t *result, + T *data, + float zero_point, + float scale, + size_t output_features_count, + float threshold, + bool debug) { + // # x: 3-D tensor. Last dimension is + // (cy, cx, ph, pw, step_y, step_x, pred_y, pred_x, pred_h, pred_w, object, cls...) + size_t col_size = 11 + impulse->label_count; + size_t row_count = output_features_count / col_size; + + static std::vector results; + static std::vector class_results; + + results.clear(); + for (size_t cls_idx = 0; cls_idx < (size_t)impulse->label_count; cls_idx++) { + + std::vector boxes; + std::vector scores; + std::vector classes; + class_results.clear(); + + for (size_t ix = 0; ix < row_count; ix++) { + size_t data_ix = ix * col_size; + float r_0 = (static_cast(data[data_ix + 0]) - zero_point) * scale; + float r_1 = (static_cast(data[data_ix + 1]) - zero_point) * scale; + float r_2 = (static_cast(data[data_ix + 2]) - zero_point) * scale; + float r_3 = (static_cast(data[data_ix + 3]) - zero_point) * scale; + float r_4 = (static_cast(data[data_ix + 4]) - zero_point) * scale; + float r_5 = (static_cast(data[data_ix + 5]) - zero_point) * scale; + float r_6 = (static_cast(data[data_ix + 6]) - zero_point) * scale; + float r_7 = (static_cast(data[data_ix + 7]) - zero_point) * scale; + float r_8 = (static_cast(data[data_ix + 8]) - zero_point) * scale; + float r_9 = (static_cast(data[data_ix + 9]) - zero_point) * scale; + float r_10 = (static_cast(data[data_ix + 10]) - zero_point) * scale; + + float cls = (static_cast(data[data_ix + 11 + cls_idx]) - zero_point) * scale; + float score = sigmoid(cls) * sigmoid(r_10); + + if ((score < threshold) || (score > 1.0f)) { + continue; + } + + float by = r_0 + sigmoid(r_6) * r_4; + float bx = r_1 + sigmoid(r_7) * r_5; + float bh = r_2 * exp(r_8); + float bw = r_3 * exp(r_9); + + float ymin = by - 0.5 * bh; + float xmin = bx - 0.5 * bw; + float ymax = by + 0.5 * bh; + float xmax = bx + 0.5 * bw; + + // from relative to absolute + ymin *= impulse->input_height; + xmin *= impulse->input_width; + ymax *= impulse->input_height; + xmax *= impulse->input_width; + + boxes.push_back(ymin); + boxes.push_back(xmin); + boxes.push_back(ymax); + boxes.push_back(xmax); + scores.push_back(score); + classes.push_back((int)cls_idx); + } + + size_t nr_boxes = scores.size(); + EI_IMPULSE_ERROR nms_res = ei_run_nms(impulse, &class_results, + boxes.data(), scores.data(), classes.data(), + nr_boxes, + true /*clip_boxes*/, + debug); + if (nms_res != EI_IMPULSE_OK) { + return nms_res; + } + + for (auto bb: class_results) { + results.push_back(bb); + } + } + + prepare_tao_results_common(impulse, result, &results); + return EI_IMPULSE_OK; +} +#endif // #ifdef EI_HAS_TAO_YOLOV3 + +#ifdef EI_HAS_TAO_YOLOV4 +/** + * Fill the result structure from an output tensor +*/ +template +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_tao_yolov4_common(const ei_impulse_t *impulse, + ei_impulse_result_t *result, + T *data, + float zero_point, + float scale, + size_t output_features_count, + float threshold, + bool debug) { + // # x: 3-D tensor. Last dimension is + // (cy, cx, ph, pw, step_y, step_x, pred_y, pred_x, pred_h, pred_w, object, cls...) + size_t col_size = 11 + impulse->label_count; + size_t row_count = output_features_count / col_size; + + static std::vector results; + static std::vector class_results; + results.clear(); + + const float grid_scale_xy = 1.0f; + + for (size_t cls_idx = 0; cls_idx < (size_t)impulse->label_count; cls_idx++) { + + std::vector boxes; + std::vector scores; + std::vector classes; + class_results.clear(); + + for (size_t ix = 0; ix < row_count; ix++) { + + float r_0 = (static_cast(data[ix * col_size + 0]) - zero_point) * scale; + float r_1 = (static_cast(data[ix * col_size + 1]) - zero_point) * scale; + float r_2 = (static_cast(data[ix * col_size + 2]) - zero_point) * scale; + float r_3 = (static_cast(data[ix * col_size + 3]) - zero_point) * scale; + float r_4 = (static_cast(data[ix * col_size + 4]) - zero_point) * scale; + float r_5 = (static_cast(data[ix * col_size + 5]) - zero_point) * scale; + float r_6 = (static_cast(data[ix * col_size + 6]) - zero_point) * scale; + float r_7 = (static_cast(data[ix * col_size + 7]) - zero_point) * scale; + float r_8 = (static_cast(data[ix * col_size + 8]) - zero_point) * scale; + float r_9 = (static_cast(data[ix * col_size + 9]) - zero_point) * scale; + float r_10 = (static_cast(data[ix * col_size + 10]) - zero_point) * scale; + + float cls = (static_cast(data[ix * col_size + 11 + cls_idx]) - zero_point) * scale; + float score = sigmoid(cls) * sigmoid(r_10); + + if ((score < threshold) || (score > 1.0f)) { + continue; + } + + float pred_y = sigmoid(r_6) * grid_scale_xy - (grid_scale_xy - 1.0f) / 2.0f; + float pred_x = sigmoid(r_7) * grid_scale_xy - (grid_scale_xy - 1.0f) / 2.0f; + float pred_h = exp(std::min(r_8, 8.0f)); + float pred_w = exp(std::min(r_9, 8.0f)); + + r_6 = pred_y; + r_7 = pred_x; + r_8 = pred_h; + r_9 = pred_w; + + float by = r_0 + r_6 * r_4; + float bx = r_1 + r_7 * r_5; + float bh = r_2 * r_8; + float bw = r_3 * r_9; + + float ymin = by - 0.5 * bh; + float xmin = bx - 0.5 * bw; + float ymax = by + 0.5 * bh; + float xmax = bx + 0.5 * bw; + + // from relative to absolute + ymin *= impulse->input_height; + xmin *= impulse->input_width; + ymax *= impulse->input_height; + xmax *= impulse->input_width; + + boxes.push_back(ymin); + boxes.push_back(xmin); + boxes.push_back(ymax); + boxes.push_back(xmax); + scores.push_back(score); + classes.push_back((int)cls_idx); + } + + size_t nr_boxes = scores.size(); + EI_IMPULSE_ERROR nms_res = ei_run_nms(impulse, &class_results, + boxes.data(), scores.data(), classes.data(), + nr_boxes, + true /*clip_boxes*/, + debug); + if (nms_res != EI_IMPULSE_OK) { + return nms_res; + } + + for (auto bb: class_results) { + results.push_back(bb); + } + } + + prepare_tao_results_common(impulse, result, &results); + return EI_IMPULSE_OK; +} +#endif // #ifdef EI_HAS_TAO_YOLOV4 + +/** + * Fill the result structure from an unquantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_tao_yolov3(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_TAO_YOLOV3 + return fill_result_struct_tao_yolov3_common(impulse, result, data, 0.0f, 1.0f, output_features_count, block_config->threshold, debug); +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_TAO_YOLOV3 +} + +/** + * Fill the result structure from a quantized output tensor +*/ +template +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_quantized_tao_yolov3(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + T *data, + float zero_point, + float scale, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_TAO_YOLOV3 + return fill_result_struct_tao_yolov3_common(impulse, result, data, zero_point, scale, output_features_count, block_config->threshold, debug); +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_TAO_YOLOV3 +} + +/** + * Fill the result structure from an unquantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_tao_yolov4(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_TAO_YOLOV4 + return fill_result_struct_tao_yolov4_common(impulse, result, data, 0.0f, 1.0f, output_features_count, block_config->threshold, debug); +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_TAO_YOLOV4 +} + +/** + * Fill the result structure from a quantized output tensor +*/ +template +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_quantized_tao_yolov4(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + T *data, + float zero_point, + float scale, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_TAO_YOLOV4 + return fill_result_struct_tao_yolov4_common(impulse, result, data, zero_point, scale, output_features_count, block_config->threshold, debug); +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_TAO_YOLOV4 +} + +#ifdef EI_HAS_YOLOV2 +// based on akida_models-1.2.0/detection/processing.py +// input is "2D" array with shape [grid_h * grid_w * nb_box, nb_classes] +__attribute__((unused)) static void softmax(std::vector& input, const size_t nb_classes) +{ + const float max = *std::max_element(input.begin(), input.end()); + const float min = *std::min_element(input.begin(), input.end()); + const float t = -100.0f; + + // x = x - np.max(x) + std::transform(input.begin(), input.end(), input.begin(), + [max](float x) { return x - max; }); + + // if np.min(x) < t: x = x / np.min(x) * t + std::transform(input.begin(), input.end(), input.begin(), + [min, t](float x) { return x < t ? (x / min * t): x; }); + + // e_x = np.exp(x) + // do it in place as we don't need raw the input anymore + std::transform(input.begin(), input.end(), input.begin(), + [](float x) { return std::exp(x); }); + + // e_x / e_x.sum(axis, keepdims=True) + // calculated for each 'row', across nb_classes + for(auto it = input.begin(); it != input.end(); it += nb_classes) { + float sum = 0.0f; + // e_x.sum(axis, keepdims=True) + for(auto it2 = it; it2 != it + nb_classes; it2++) { + sum += *it2; + } + // e_x / e_x.sum(axis, keepdims=True) + std::transform(it, it + nb_classes, it, + [sum](float ex) { return ex / sum; }); + } +} + +class BoundingBox { +public: + float x1, y1, x2, y2, confidence; + std::vector classes; + + BoundingBox(float x1, float y1, float x2, float y2, float confidence, const std::vector& classes) + : x1(x1), y1(y1), x2(x2), y2(y2), confidence(confidence), classes(classes) {} + + float get_score() const { + return confidence; + } + + int get_label() const { + auto maxElementIndex = std::max_element(classes.begin(), classes.end()) - classes.begin(); + return maxElementIndex; + } + + float _interval_overlap(float x1, float x2, float x3, float x4) const { + if(x3 < x1) { + if(x4 < x1) { + return 0; + } + return std::min(x2, x4) - x1; + } + if(x2 < x3) { + return 0; + } + return std::min(x2, x4) - x3; + } + + + float iou(const BoundingBox& other) const { + // Implementation of the Intersection over Union calculation + float intersect_w = this->_interval_overlap(this->x1, this->x2, other.x1, other.x2); + float intersect_h = this->_interval_overlap(this->y1, this->y2, other.y1, other.y2); + + float intersect = intersect_w * intersect_h; + + float w1 = this->x2 - this->x1; + float h1 = this->y2 - this->y1; + float w2 = other.x2 - other.x1; + float h2 = other.y2 - other.y1; + + float un = w1 * h1 + w2 * h2 - intersect; + + return float(intersect) / un; + } +}; +#endif // EI_HAS_YOLOV2 +/** + * Fill the result structure from an unquantized output tensor + */ +__attribute__((unused)) static EI_IMPULSE_ERROR fill_result_struct_f32_yolov2(const ei_impulse_t *impulse, + const ei_learning_block_config_tflite_graph_t *block_config, + ei_impulse_result_t *result, + float *data, + size_t output_features_count, + bool debug = false) { +#ifdef EI_HAS_YOLOV2 + static std::vector results; + results.clear(); + + // Example output shape: (7, 7, 5, 7) + // TODO: calculate grid_h, grid_w, nb_box from output_features_count or get as a param + // grid_h, grid_w, nb_box = output.shape[:3] + const size_t grid_h = 7; + const size_t grid_w = 7; + const size_t nb_box = 5; + const std::vector> anchors = {{0.56594, 1.05012}, {1.0897, 2.03908}, {2.37823, 3.00376}, {2.4593, 4.913}, {5.15981, 5.56699}}; + + const size_t nb_classes = impulse->label_count; + const float obj_threshold = 0.5; + const float nms_threshold = 0.5; + std::vector output; + const int stride = 4 + 1 + nb_classes; + + output.assign(data, data + output_features_count); + + // boxes = [] + std::vector boxes; + + // equivalent to: classes_confidences = output[..., 5:] + std::vector classes_confidences; + const size_t dim = 5; + for(auto it = output.begin() + dim; it <= output.end(); it += (dim + nb_classes)) { + classes_confidences.insert(classes_confidences.end(), it, it + nb_classes); + } + // calculate softmax for later use, we need to calculate it across the whole input data so operate on a sliced output + softmax(classes_confidences, nb_classes); + + for (size_t row = 0; row < grid_h; ++row) { + for (size_t col = 0; col < grid_w; ++col) { + for (size_t b = 0; b < nb_box; ++b) { + size_t idx = row * grid_w * nb_box * stride + col * nb_box * stride + b * stride; + size_t classes_idx = row * grid_w * nb_box * nb_classes + col * nb_box * nb_classes + b * nb_classes; + + // Apply sigmoid to the 4th element + // output[..., 4] = _sigmoid(output[..., 4]) + float sigmoid_val = sigmoid(output[idx + 4]); + output[idx + 4] = sigmoid_val; + + // classes = output[row, col, b, 5:] + std::vector classes(classes_confidences.begin() + classes_idx, classes_confidences.begin() + classes_idx + nb_classes); + + // output[..., 5:] = output[..., 4][..., np.newaxis] * _softmax(output[..., 5:]) + // output[..., 5:] *= output[..., 5:] > obj_threshold + std::transform(classes.begin(), classes.end(), classes.begin(), + [sigmoid_val, obj_threshold](float c) { c *= sigmoid_val; return c > obj_threshold ? c : 0.0f; }); + + // if np.sum(classes) > 0: + float sum = 0.0f; + for(auto it = classes.begin(); it != classes.end(); it++) { + sum += *it; + } + if(sum > 0.0f) { + // x, y, w, h = output[row, col, b, :4] + float x = output[idx + 0]; + float y = output[idx + 1]; + float w = output[idx + 2]; + float h = output[idx + 3]; + + // x = (col + _sigmoid(x)) / grid_w # center position, unit: image width + x = (col + sigmoid(x)) / grid_w; + // y = (row + _sigmoid(y)) / grid_h # center position, unit: image height + y = (row + sigmoid(y)) / grid_h; + // w = anchors[b][0] * np.exp(w) / grid_w # unit: image width + w = anchors[b].first * std::exp(w) / grid_w; + // h = anchors[b][1] * np.exp(h) / grid_h # unit: image height + h = anchors[b].second * std::exp(h) / grid_h; + + // confidence = output[row, col, b, 4] + float confidence = output[idx + 4]; + + // x1 = max(x - w / 2, 0) + float x1 = std::max(x - w / 2, 0.0f); + // y1 = max(y - h / 2, 0) + float y1 = std::max(y - h / 2, 0.0f); + // x2 = min(x + w / 2, grid_w) + float x2 = std::min(x + w / 2, static_cast(grid_w)); + // y2 = min(y + h / 2, grid_h) + float y2 = std::min(y + h / 2, static_cast(grid_h)); + + boxes.emplace_back(x1, y1, x2, y2, confidence, classes); + } + } + } + } + + // Non-maximal suppression (on boxes) + for (size_t c = 0; c < nb_classes; ++c) { + std::vector> sorted_indices; + for (size_t i = 0; i < boxes.size(); ++i) { + sorted_indices.emplace_back(boxes[i].classes[c], i); + } + + std::sort(sorted_indices.begin(), sorted_indices.end(), + [](const std::pair& a, const std::pair& b) { + return a.first > b.first; + }); + + for (size_t i = 0; i < sorted_indices.size(); ++i) { + int index_i = sorted_indices[i].second; + if (boxes[index_i].classes[c] == 0) + continue; + + for (size_t j = i + 1; j < sorted_indices.size(); ++j) { + int index_j = sorted_indices[j].second; + + if ((boxes[index_i].iou(boxes[index_j]) >= nms_threshold) && + (boxes[index_i].get_label() == (int)c) && + (boxes[index_j].get_label() == (int)c)) { + boxes[index_j].confidence = 0; + } + } + } + } + + // remove the boxes which are less likely than a obj_threshold + boxes.erase(std::remove_if(boxes.begin(), boxes.end(), + [obj_threshold](const BoundingBox& box) { + return box.get_score() <= obj_threshold; + }), boxes.end()); + + // sort boxes by box.get_score() + std::sort(boxes.begin(), boxes.end(), + [](const BoundingBox& a, const BoundingBox& b) { + return a.get_score() > b.get_score(); + }); + + // convert relative coordinates to absolute coordinates + for(auto & box: boxes) { + ei_impulse_result_bounding_box_t res; + res.label = ei_classifier_inferencing_categories[box.get_label()]; + res.x = ceil(box.x1 * impulse->input_width); + res.y = ceil(box.y1 * impulse->input_height); + res.width = ceil((box.x2 - box.x1) * impulse->input_width); + res.height = ceil((box.y2 - box.y1) * impulse->input_height); + res.value = box.get_score(); + results.push_back(res); + } + + // if we didn't detect min required objects, fill the rest with fixed value + size_t added_boxes_count = results.size(); + size_t min_object_detection_count = impulse->object_detection_count; + if (added_boxes_count < min_object_detection_count) { + results.resize(min_object_detection_count); + for (size_t ix = added_boxes_count; ix < min_object_detection_count; ix++) { + results[ix].value = 0.0f; + } + } + + result->bounding_boxes = results.data(); + result->bounding_boxes_count = results.size(); + + return EI_IMPULSE_OK; +#else + return EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE; +#endif // #ifdef EI_HAS_YOLOV7 +} + +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 +bool find_mtx_by_idx(ei_feature_t* mtx, ei::matrix_t** matrix, uint32_t mtx_id, size_t mtx_size) { + for (size_t i = 0; i < mtx_size; i++) { + if (mtx[i].matrix == NULL) { + continue; + } + if (mtx[i].blockId == mtx_id || mtx[i].blockId == 0) { + *matrix = mtx[i].matrix; + return true; + } + } + return false; +} +#endif + +#endif // _EI_CLASSIFIER_FILL_RESULT_STRUCT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_model_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_model_types.h new file mode 100644 index 0000000..4c36205 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_model_types.h @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_MODEL_TYPES_H_ +#define _EDGE_IMPULSE_MODEL_TYPES_H_ + +#include + +#include "edge-impulse-sdk/classifier/ei_classifier_types.h" +#include "edge-impulse-sdk/dsp/ei_dsp_handle.h" +#include "edge-impulse-sdk/dsp/numpy.hpp" +#if EI_CLASSIFIER_USE_FULL_TFLITE || (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_AKIDA) || (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_MEMRYX) +#include "tensorflow-lite/tensorflow/lite/c/common.h" +#else +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#endif // EI_CLASSIFIER_USE_FULL_TFLITE + +#define EI_CLASSIFIER_NONE 255 +#define EI_CLASSIFIER_UTENSOR 1 +#define EI_CLASSIFIER_TFLITE 2 +#define EI_CLASSIFIER_CUBEAI 3 +#define EI_CLASSIFIER_TFLITE_FULL 4 +#define EI_CLASSIFIER_TENSAIFLOW 5 +#define EI_CLASSIFIER_TENSORRT 6 +#define EI_CLASSIFIER_DRPAI 7 +#define EI_CLASSIFIER_TFLITE_TIDL 8 +#define EI_CLASSIFIER_AKIDA 9 +#define EI_CLASSIFIER_SYNTIANT 10 +#define EI_CLASSIFIER_ONNX_TIDL 11 +#define EI_CLASSIFIER_MEMRYX 12 + +#define EI_CLASSIFIER_SENSOR_UNKNOWN -1 +#define EI_CLASSIFIER_SENSOR_MICROPHONE 1 +#define EI_CLASSIFIER_SENSOR_ACCELEROMETER 2 +#define EI_CLASSIFIER_SENSOR_CAMERA 3 +#define EI_CLASSIFIER_SENSOR_9DOF 4 +#define EI_CLASSIFIER_SENSOR_ENVIRONMENTAL 5 +#define EI_CLASSIFIER_SENSOR_FUSION 6 + +// These must match the enum values in TensorFlow Lite's "TfLiteType" +#define EI_CLASSIFIER_DATATYPE_FLOAT32 1 +#define EI_CLASSIFIER_DATATYPE_INT8 9 + +#define EI_CLASSIFIER_LAST_LAYER_UNKNOWN -1 +#define EI_CLASSIFIER_LAST_LAYER_SSD 1 +#define EI_CLASSIFIER_LAST_LAYER_FOMO 2 +#define EI_CLASSIFIER_LAST_LAYER_YOLOV5 3 +#define EI_CLASSIFIER_LAST_LAYER_YOLOX 4 +#define EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI 5 +#define EI_CLASSIFIER_LAST_LAYER_YOLOV7 6 +#define EI_CLASSIFIER_LAST_LAYER_TAO_RETINANET 7 +#define EI_CLASSIFIER_LAST_LAYER_TAO_SSD 8 +#define EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3 9 +#define EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4 10 +#define EI_CLASSIFIER_LAST_LAYER_YOLOV2 11 + +#define EI_CLASSIFIER_IMAGE_SCALING_NONE 0 +#define EI_CLASSIFIER_IMAGE_SCALING_0_255 1 +#define EI_CLASSIFIER_IMAGE_SCALING_TORCH 2 +#define EI_CLASSIFIER_IMAGE_SCALING_MIN1_1 3 +#define EI_CLASSIFIER_IMAGE_SCALING_MIN128_127 4 +#define EI_CLASSIFIER_IMAGE_SCALING_BGR_SUBTRACT_IMAGENET_MEAN 5 + +// maps back to ClassificationMode in keras-types.ts +#define EI_CLASSIFIER_CLASSIFICATION_MODE_CLASSIFICATION 1 +#define EI_CLASSIFIER_CLASSIFICATION_MODE_REGRESSION 2 +#define EI_CLASSIFIER_CLASSIFICATION_MODE_OBJECT_DETECTION 3 +#define EI_CLASSIFIER_CLASSIFICATION_MODE_ANOMALY_GMM 4 +#define EI_CLASSIFIER_CLASSIFICATION_MODE_VISUAL_ANOMALY 5 +#define EI_CLASSIFIER_CLASSIFICATION_MODE_ANOMALY_KMEANS 6 +#define EI_CLASSIFIER_CLASSIFICATION_MODE_DSP 7 + +struct ei_impulse; + +typedef struct { + ei::matrix_t* matrix; + uint32_t blockId; +} ei_feature_t; + +typedef struct { + uint16_t implementation_version; + bool is_configured; + uint32_t average_window_duration_ms; + float detection_threshold; + uint32_t suppression_ms; + uint32_t suppression_flags; +} ei_model_performance_calibration_t; + +typedef int (*extract_fn_t)(ei::signal_t *signal, ei::matrix_t *output_matrix, void *config, float frequency); + +typedef struct { + uint32_t blockId; + size_t n_output_features; + extract_fn_t extract_fn; + void *config; + uint8_t *axes; + size_t axes_size; + int version; // future proof, can easily add to this struct now + DspHandle* (*factory)(void* config, float sampling_freq); // nullptr means no state + // v1 ends here +} ei_model_dsp_t; + +typedef struct { + float *centroid; + float max_error; +} ei_classifier_anom_cluster_t; + +typedef struct { + uint32_t blockId; + bool keep_output; + EI_IMPULSE_ERROR (*infer_fn)(const ei_impulse *impulse, ei_feature_t *fmatrix, uint32_t learn_block_index, uint32_t* input_block_ids, uint32_t input_block_ids_size, ei_impulse_result_t *result, void *config, bool debug); + void *config; + int image_scaling; + const uint32_t* input_block_ids; + const uint32_t input_block_ids_size; + uint32_t output_features_count; +} ei_learning_block_t; + +typedef struct { + uint16_t implementation_version; + uint8_t input_datatype; + bool input_quantized; + float input_scale; + float input_zeropoint; + uint8_t output_datatype; + bool output_quantized; + float output_scale; + float output_zeropoint; +} ei_config_tensaiflow_graph_t; + +typedef struct { + uint16_t implementation_version; + const unsigned char *model; + size_t model_size; + size_t arena_size; +} ei_config_tflite_graph_t; + +typedef struct { + uint16_t implementation_version; + TfLiteStatus (*model_init)(void*(*alloc_fnc)(size_t, size_t)); + TfLiteStatus (*model_invoke)(); + TfLiteStatus (*model_reset)(void (*free)(void* ptr)); + TfLiteStatus (*model_input)(int, TfLiteTensor*); + TfLiteStatus (*model_output)(int, TfLiteTensor*); +} ei_config_tflite_eon_graph_t; + +typedef struct { + uint16_t implementation_version; + uint8_t classification_mode; + uint32_t block_id; + /* object detection */ + bool object_detection; + int8_t object_detection_last_layer; + uint8_t output_data_tensor; + uint8_t output_labels_tensor; + uint8_t output_score_tensor; + /* object detection and visual AD */ + float threshold; + /* tflite graph params */ + bool quantized; + bool compiled; + /* tflite graph config pointer */ + void *graph_config; +} ei_learning_block_config_tflite_graph_t; + +typedef struct { + uint16_t implementation_version; + uint8_t classification_mode; + const uint16_t *anom_axis; + uint16_t anom_axes_size; + const ei_classifier_anom_cluster_t *anom_clusters; + uint16_t anom_cluster_count; + const float *anom_scale; + const float *anom_mean; +} ei_learning_block_config_anomaly_kmeans_t; + +typedef struct { + uint16_t implementation_version; + uint8_t classification_mode; + const uint16_t *anom_axis; + uint16_t anom_axes_size; + float anomaly_threshold; + bool visual; + void* graph_config; +} ei_learning_block_config_anomaly_gmm_t; + +typedef struct { + float confidence_threshold; + float iou_threshold; +} ei_object_detection_nms_config_t; + +typedef struct ei_impulse { + /* project details */ + uint32_t project_id; + const char *project_owner; + const char *project_name; + uint32_t deploy_version; + + /* DSP details */ + uint32_t nn_input_frame_size; + uint32_t raw_sample_count; + uint32_t raw_samples_per_frame; + uint32_t dsp_input_frame_size; + uint32_t input_width; + uint32_t input_height; + uint32_t input_frames; + float interval_ms; + float frequency; + size_t dsp_blocks_size; + ei_model_dsp_t *dsp_blocks; + + /* object detection */ + uint16_t object_detection_count; + uint32_t fomo_output_size; + uint32_t tflite_output_features_count; + + /* learning blocks */ + const size_t learning_blocks_size; + const ei_learning_block_t *learning_blocks; + + /* inference parameters */ + uint32_t inferencing_engine; + + /* sensors and on-device inference */ + uint32_t sensor; + const char *fusion_string; + uint32_t slice_size; + uint32_t slices_per_model_window; + + /* output details */ + uint16_t has_anomaly; + uint16_t label_count; + const ei_model_performance_calibration_t calibration; + const char **categories; + ei_object_detection_nms_config_t object_detection_nms; +} ei_impulse_t; + +class ei_impulse_state_t { +typedef DspHandle* _dsp_handle_ptr_t; +public: + const ei_impulse_t *impulse; // keep a pointer to the impulse + _dsp_handle_ptr_t *dsp_handles; + bool is_temp_handle = false; // to know if we're using the old (stateless) API + ei_impulse_state_t(const ei_impulse_t *impulse) + : impulse(impulse) + { + const auto num_dsp_blocks = impulse->dsp_blocks_size; + dsp_handles = (_dsp_handle_ptr_t*)ei_malloc(sizeof(_dsp_handle_ptr_t)*num_dsp_blocks); + for(size_t ix = 0; ix < num_dsp_blocks; ix++) { + dsp_handles[ix] = nullptr; + } + } + + DspHandle* get_dsp_handle(size_t ix) { + if (dsp_handles[ix] == nullptr) { + dsp_handles[ix] = impulse->dsp_blocks[ix].factory(impulse->dsp_blocks[ix].config, impulse->frequency); + } + return dsp_handles[ix]; + } + + void reset() + { + for (size_t ix = 0; ix < impulse->dsp_blocks_size; ix++) { + if (dsp_handles[ix] != nullptr) { + delete dsp_handles[ix]; + dsp_handles[ix] = nullptr; + } + } + } + + void* operator new(size_t size) { + return ei_malloc(size); + } + + void operator delete(void* ptr) { + ei_free(ptr); + } + + void* operator new[](size_t size) { + return ei_malloc(size); + } + + void operator delete[](void* ptr) { + ei_free(ptr); + } + + ~ei_impulse_state_t() + { + reset(); + ei_free(dsp_handles); + } +}; + +class ei_impulse_handle_t { +public: + ei_impulse_handle_t(const ei_impulse_t *impulse) + : state(impulse), impulse(impulse) {}; + ei_impulse_state_t state; + const ei_impulse_t *impulse; +}; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + const unsigned char *model; + size_t model_size; + size_t arena_size; +} ei_dsp_config_tflite_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + TfLiteStatus (*init_fn)(void*(*alloc_fnc)(size_t, size_t)); + TfLiteStatus (*invoke_fn)(); + TfLiteStatus (*reset_fn)(void (*free)(void* ptr)); + TfLiteStatus (*input_fn)(int, TfLiteTensor*); + TfLiteStatus (*output_fn)(int, TfLiteTensor*); +} ei_dsp_config_tflite_eon_t; + +#endif // _EDGE_IMPULSE_MODEL_TYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_nms.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_nms.h new file mode 100644 index 0000000..5bfcdf8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_nms.h @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_NMS_H_ +#define _EDGE_IMPULSE_NMS_H_ + +#include "model-parameters/model_metadata.h" +#if EI_CLASSIFIER_HAS_MODEL_VARIABLES == 1 +#include "model-parameters/model_variables.h" +#endif +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/classifier/ei_classifier_types.h" +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" + +#if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOX) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_RETINANET) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_SSD) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV2) + +// The code below comes from tensorflow/lite/kernels/internal/reference/non_max_suppression.h +// Copyright 2019 The TensorFlow Authors. All rights reserved. +// Licensed under the Apache License, Version 2.0 +#include +#include +#include +#include + +// A pair of diagonal corners of the box. +struct BoxCornerEncoding { + float y1; + float x1; + float y2; + float x2; +}; + +static inline float ComputeIntersectionOverUnion(const float* boxes, const int i, + const int j) { + auto& box_i = reinterpret_cast(boxes)[i]; + auto& box_j = reinterpret_cast(boxes)[j]; + const float box_i_y_min = std::min(box_i.y1, box_i.y2); + const float box_i_y_max = std::max(box_i.y1, box_i.y2); + const float box_i_x_min = std::min(box_i.x1, box_i.x2); + const float box_i_x_max = std::max(box_i.x1, box_i.x2); + const float box_j_y_min = std::min(box_j.y1, box_j.y2); + const float box_j_y_max = std::max(box_j.y1, box_j.y2); + const float box_j_x_min = std::min(box_j.x1, box_j.x2); + const float box_j_x_max = std::max(box_j.x1, box_j.x2); + + const float area_i = + (box_i_y_max - box_i_y_min) * (box_i_x_max - box_i_x_min); + const float area_j = + (box_j_y_max - box_j_y_min) * (box_j_x_max - box_j_x_min); + if (area_i <= 0 || area_j <= 0) return 0.0; + const float intersection_ymax = std::min(box_i_y_max, box_j_y_max); + const float intersection_xmax = std::min(box_i_x_max, box_j_x_max); + const float intersection_ymin = std::max(box_i_y_min, box_j_y_min); + const float intersection_xmin = std::max(box_i_x_min, box_j_x_min); + const float intersection_area = + std::max(intersection_ymax - intersection_ymin, 0.0) * + std::max(intersection_xmax - intersection_xmin, 0.0); + return intersection_area / (area_i + area_j - intersection_area); +} + +// Implements (Single-Class) Soft NMS (with Gaussian weighting). +// Supports functionality of TensorFlow ops NonMaxSuppressionV4 & V5. +// Reference: "Soft-NMS - Improving Object Detection With One Line of Code" +// [Bodla et al, https://arxiv.org/abs/1704.04503] +// Implementation adapted from the TensorFlow NMS code at +// tensorflow/core/kernels/non_max_suppression_op.cc. +// +// Arguments: +// boxes: box encodings in format [y1, x1, y2, x2], shape: [num_boxes, 4] +// num_boxes: number of candidates +// scores: scores for candidate boxes, in the same order. shape: [num_boxes] +// max_output_size: the maximum number of selections. +// iou_threshold: Intersection-over-Union (IoU) threshold for NMS +// score_threshold: All candidate scores below this value are rejected +// soft_nms_sigma: Soft NMS parameter, used for decaying scores +// +// Outputs: +// selected_indices: all the selected indices. Underlying array must have +// length >= max_output_size. Cannot be null. +// selected_scores: scores of selected indices. Defer from original value for +// Soft NMS. If not null, array must have length >= max_output_size. +// num_selected_indices: Number of selections. Only these many elements are +// set in selected_indices, selected_scores. Cannot be null. +// +// Assumes inputs are valid (for eg, iou_threshold must be >= 0). +static inline void NonMaxSuppression(const float* boxes, const int num_boxes, + const float* scores, const int max_output_size, + const float iou_threshold, + const float score_threshold, + const float soft_nms_sigma, int* selected_indices, + float* selected_scores, + int* num_selected_indices) { + struct Candidate { + int index; + float score; + int suppress_begin_index; + }; + + // Priority queue to hold candidates. + auto cmp = [](const Candidate bs_i, const Candidate bs_j) { + return bs_i.score < bs_j.score; + }; + std::priority_queue, decltype(cmp)> + candidate_priority_queue(cmp); + // Populate queue with candidates above the score threshold. + for (int i = 0; i < num_boxes; ++i) { + if (scores[i] > score_threshold) { + candidate_priority_queue.emplace(Candidate({i, scores[i], 0})); + } + } + + *num_selected_indices = 0; + int num_outputs = std::min(static_cast(candidate_priority_queue.size()), + max_output_size); + if (num_outputs == 0) return; + + // NMS loop. + float scale = 0; + if (soft_nms_sigma > 0.0) { + scale = -0.5 / soft_nms_sigma; + } + while (*num_selected_indices < num_outputs && + !candidate_priority_queue.empty()) { + Candidate next_candidate = candidate_priority_queue.top(); + const float original_score = next_candidate.score; + candidate_priority_queue.pop(); + + // Overlapping boxes are likely to have similar scores, therefore we + // iterate through the previously selected boxes backwards in order to + // see if `next_candidate` should be suppressed. We also enforce a property + // that a candidate can be suppressed by another candidate no more than + // once via `suppress_begin_index` which tracks which previously selected + // boxes have already been compared against next_candidate prior to a given + // iteration. These previous selected boxes are then skipped over in the + // following loop. + bool should_hard_suppress = false; + for (int j = *num_selected_indices - 1; + j >= next_candidate.suppress_begin_index; --j) { + const float iou = ComputeIntersectionOverUnion( + boxes, next_candidate.index, selected_indices[j]); + + // First decide whether to perform hard suppression. + if (iou >= iou_threshold) { + should_hard_suppress = true; + break; + } + + // Suppress score if NMS sigma > 0. + if (soft_nms_sigma > 0.0) { + next_candidate.score = + next_candidate.score * std::exp(scale * iou * iou); + } + + // If score has fallen below score_threshold, it won't be pushed back into + // the queue. + if (next_candidate.score <= score_threshold) break; + } + // If `next_candidate.score` has not dropped below `score_threshold` + // by this point, then we know that we went through all of the previous + // selections and can safely update `suppress_begin_index` to + // `selected.size()`. If on the other hand `next_candidate.score` + // *has* dropped below the score threshold, then since `suppress_weight` + // always returns values in [0, 1], further suppression by items that were + // not covered in the above for loop would not have caused the algorithm + // to select this item. We thus do the same update to + // `suppress_begin_index`, but really, this element will not be added back + // into the priority queue. + next_candidate.suppress_begin_index = *num_selected_indices; + + if (!should_hard_suppress) { + if (next_candidate.score == original_score) { + // Suppression has not occurred, so select next_candidate. + selected_indices[*num_selected_indices] = next_candidate.index; + if (selected_scores) { + selected_scores[*num_selected_indices] = next_candidate.score; + } + ++*num_selected_indices; + } + if ((soft_nms_sigma > 0.0) && (next_candidate.score > score_threshold)) { + // Soft suppression might have occurred and current score is still + // greater than score_threshold; add next_candidate back onto priority + // queue. + candidate_priority_queue.push(next_candidate); + } + } + } +} + +/** + * Run non-max suppression over the results array (for bounding boxes) + */ +EI_IMPULSE_ERROR ei_run_nms( + const ei_impulse_t *impulse, + std::vector *results, + float *boxes, + float *scores, + int *classes, + size_t bb_count, + bool clip_boxes, + bool debug) { + + if (bb_count < 1) { + return EI_IMPULSE_OK; + } + + int *selected_indices = (int*)ei_malloc(1 * bb_count * sizeof(int)); + float *selected_scores = (float*)ei_malloc(1 * bb_count * sizeof(float)); + + if (!scores || !boxes || !selected_indices || !selected_scores || !classes) { + ei_free(selected_indices); + ei_free(selected_scores); + return EI_IMPULSE_OUT_OF_MEMORY; + } + + // boxes: box encodings in format [y1, x1, y2, x2], shape: [num_boxes, 4] + // num_boxes: number of candidates + // scores: scores for candidate boxes, in the same order. shape: [num_boxes] + // max_output_size: the maximum number of selections. + // iou_threshold: Intersection-over-Union (IoU) threshold for NMS + // score_threshold: All candidate scores below this value are rejected + // soft_nms_sigma: Soft NMS parameter, used for decaying scores + + int num_selected_indices; + + NonMaxSuppression( + (const float*)boxes, // boxes + bb_count, // num_boxes + (const float*)scores, // scores + bb_count, // max_output_size + impulse->object_detection_nms.iou_threshold, // iou_threshold + impulse->object_detection_nms.confidence_threshold, // score_threshold + 0.0f, // soft_nms_sigma + selected_indices, + selected_scores, + &num_selected_indices); + + std::vector new_results; + + for (size_t ix = 0; ix < (size_t)num_selected_indices; ix++) { + + int out_ix = selected_indices[ix]; + ei_impulse_result_bounding_box_t bb; + bb.label = impulse->categories[classes[out_ix]]; + bb.value = selected_scores[ix]; + + float ymin = boxes[(out_ix * 4) + 0]; + float xmin = boxes[(out_ix * 4) + 1]; + float ymax = boxes[(out_ix * 4) + 2]; + float xmax = boxes[(out_ix * 4) + 3]; + + if (clip_boxes) { + ymin = std::min(std::max(ymin, 0.0f), (float)impulse->input_height); + xmin = std::min(std::max(xmin, 0.0f), (float)impulse->input_width); + ymax = std::min(std::max(ymax, 0.0f), (float)impulse->input_height); + xmax = std::min(std::max(xmax, 0.0f), (float)impulse->input_width); + } + + bb.y = static_cast(ymin); + bb.x = static_cast(xmin); + bb.height = static_cast(ymax) - bb.y; + bb.width = static_cast(xmax) - bb.x; + new_results.push_back(bb); + + if (debug) { + ei_printf("Found bb with label %s\n", bb.label); + } + + } + + results->clear(); + + for (size_t ix = 0; ix < new_results.size(); ix++) { + results->push_back(new_results[ix]); + } + + ei_free(selected_indices); + ei_free(selected_scores); + + return EI_IMPULSE_OK; + +} + +/** + * Run non-max suppression over the results array (for bounding boxes) + */ +EI_IMPULSE_ERROR ei_run_nms( + const ei_impulse_t *impulse, + std::vector *results, + bool clip_boxes, + bool debug) { + + size_t bb_count = 0; + for (size_t ix = 0; ix < results->size(); ix++) { + auto bb = results->at(ix); + if (bb.value == 0) { + continue; + } + bb_count++; + } + + if (bb_count < 1) { + return EI_IMPULSE_OK; + } + + float *boxes = (float*)ei_malloc(4 * bb_count * sizeof(float)); + float *scores = (float*)ei_malloc(1 * bb_count * sizeof(float)); + int *classes = (int*) ei_malloc(bb_count * sizeof(int)); + + if (!scores || !boxes || !classes) { + ei_free(boxes); + ei_free(scores); + ei_free(classes); + return EI_IMPULSE_OUT_OF_MEMORY; + } + + size_t box_ix = 0; + for (size_t ix = 0; ix < results->size(); ix++) { + auto bb = results->at(ix); + if (bb.value == 0) { + continue; + } + boxes[(box_ix * 4) + 0] = bb.y; + boxes[(box_ix * 4) + 1] = bb.x; + boxes[(box_ix * 4) + 2] = bb.y + bb.height; + boxes[(box_ix * 4) + 3] = bb.x + bb.width; + scores[box_ix] = bb.value; + + for (size_t j = 0; j < impulse->label_count; j++) { + if (strcmp(impulse->categories[j], bb.label) == 0) + classes[box_ix] = j; + } + + box_ix++; + } + + EI_IMPULSE_ERROR nms_res = ei_run_nms(impulse, results, + boxes, scores, + classes, bb_count, + clip_boxes, + debug); + + + ei_free(boxes); + ei_free(scores); + ei_free(classes); + + return nms_res; + +} + +/** + * Run non-max suppression over the results array (for bounding boxes) + */ +EI_IMPULSE_ERROR ei_run_nms( + const ei_impulse_t *impulse, + std::vector *results, + bool debug = false) { + return ei_run_nms(impulse, results, true, debug); +} + +/** + * Run non-max suppression over the results array (for bounding boxes) + */ +EI_IMPULSE_ERROR ei_run_nms(std::vector *results, bool debug = false) { +#if EI_CLASSIFIER_HAS_MODEL_VARIABLES == 1 + auto& impulse = *ei_default_impulse.impulse; +#else + const ei_impulse_t impulse = { + .object_detection_nms.confidence_threshold = 0.0f, + .object_detection_nms.iou_threshold = 0.2f + }; +#endif + return ei_run_nms(&impulse, results, debug); +} + +#endif // #if (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOX) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_RETINANET) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_SSD) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3) || (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4) + +#endif // _EDGE_IMPULSE_NMS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_performance_calibration.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_performance_calibration.h new file mode 100644 index 0000000..a14c1e5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_performance_calibration.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef EI_PERFORMANCE_CALIBRATION_H +#define EI_PERFORMANCE_CALIBRATION_H + +/* Includes ---------------------------------------------------------------- */ +#include "edge-impulse-sdk/dsp/numpy_types.h" +#include "edge-impulse-sdk/dsp/returntypes.hpp" +#include "ei_model_types.h" + +/* Private const types ----------------------------------------------------- */ +#define MEM_ERROR "ERR: Failed to allocate memory for performance calibration\r\n" + +#define EI_PC_RET_NO_EVENT_DETECTED -1 +#define EI_PC_RET_MEMORY_ERROR -2 + +class RecognizeEvents { + +public: + RecognizeEvents( + const ei_model_performance_calibration_t *config, + uint32_t n_labels, + uint32_t sample_length, + float sample_interval_ms) + { + this->_score_array = nullptr; + this->_running_sum = nullptr; + this->_detection_threshold = config->detection_threshold; + this->_suppression_flags = config->suppression_flags; + this->_should_boost = config->is_configured; + this->_n_labels = n_labels; + + /* Determine sample length in ms */ + float sample_length_ms = (static_cast(sample_length) * sample_interval_ms); + + /* Calculate number of inference runs needed for the duration window */ + this->_average_window_duration_samples = + (config->average_window_duration_ms < static_cast(sample_length_ms)) + ? 1 + : static_cast(static_cast(config->average_window_duration_ms) / sample_length_ms); + + /* Calculate number of inference runs for suppression */ + this->_suppression_samples = (config->suppression_ms < static_cast(sample_length_ms)) + ? 0 + : static_cast(static_cast(config->suppression_ms) / sample_length_ms); + + /* Detection threshold should be high enough to only classifiy 1 possibly output */ + if (this->_detection_threshold <= (1.f / this->_n_labels)) { + ei_printf("ERR: Classifier detection threshold too low\r\n"); + return; + } + + /* Array to store scores for all labels */ + this->_score_array = (float *)ei_malloc( + this->_average_window_duration_samples * this->_n_labels * sizeof(float)); + + if (this->_score_array == NULL) { + ei_printf(MEM_ERROR); + return; + } + + for (uint32_t i = 0; i < this->_average_window_duration_samples * this->_n_labels; i++) { + this->_score_array[i] = 0.f; + } + this->_score_idx = 0; + + /* Running sum for all labels */ + this->_running_sum = (float *)ei_malloc(this->_n_labels * sizeof(float)); + + if (this->_running_sum != NULL) { + for (uint32_t i = 0; i < this->_n_labels; i++) { + this->_running_sum[i] = 0.f; + } + } + else { + ei_printf(MEM_ERROR); + return; + } + + this->_suppression_count = this->_suppression_samples; + this->_n_scores_in_array = 0; + } + + ~RecognizeEvents() + { + if (this->_score_array) { + ei_free((void *)this->_score_array); + } + if (this->_running_sum) { + ei_free((void *)this->_running_sum); + } + } + + bool should_boost() + { + return this->_should_boost; + } + + int32_t trigger(ei_impulse_result_classification_t *scores) + { + int32_t recognized_event = EI_PC_RET_NO_EVENT_DETECTED; + float current_top_score = 0.f; + uint32_t current_top_index = 0; + + /* Check pointers */ + if (this->_score_array == NULL || this->_running_sum == NULL) { + return EI_PC_RET_MEMORY_ERROR; + } + + /* Update the score array and running sum */ + for (uint32_t i = 0; i < this->_n_labels; i++) { + this->_running_sum[i] -= this->_score_array[(this->_score_idx * this->_n_labels) + i]; + this->_running_sum[i] += scores[i].value; + this->_score_array[(this->_score_idx * this->_n_labels) + i] = scores[i].value; + } + + if (++this->_score_idx >= this->_average_window_duration_samples) { + this->_score_idx = 0; + } + + /* Number of samples to average, increases until the buffer is full */ + if (this->_n_scores_in_array < this->_average_window_duration_samples) { + this->_n_scores_in_array++; + } + + /* Average data and place in scores & determine top score */ + for (uint32_t i = 0; i < this->_n_labels; i++) { + scores[i].value = this->_running_sum[i] / this->_n_scores_in_array; + + if (scores[i].value > current_top_score) { + if(this->_suppression_flags == 0) { + current_top_score = scores[i].value; + current_top_index = i; + } + else if(this->_suppression_flags & (1 << i)) { + current_top_score = scores[i].value; + current_top_index = i; + } + } + } + + /* Check threshold, suppression */ + if (this->_suppression_samples && this->_suppression_count < this->_suppression_samples) { + this->_suppression_count++; + } + else { + if (current_top_score >= this->_detection_threshold) { + recognized_event = current_top_index; + + if (this->_suppression_flags & (1 << current_top_index)) { + this->_suppression_count = 0; + } + } + } + + return recognized_event; + }; + + void *operator new(size_t size) + { + void *p = ei_malloc(size); + return p; + } + + void operator delete(void *p) + { + ei_free(p); + } + +private: + uint32_t _average_window_duration_samples; + float _detection_threshold; + bool _should_boost; + uint32_t _suppression_samples; + uint32_t _suppression_count; + uint32_t _suppression_flags; + uint32_t _n_labels; + float *_score_array; + uint32_t _score_idx; + float *_running_sum; + uint32_t _n_scores_in_array; +}; + +#endif //EI_PERFORMANCE_CALIBRATION diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_quantize.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_quantize.h new file mode 100644 index 0000000..727d920 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_quantize.h @@ -0,0 +1,37 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef __EI_QUANTIZE__H__ +#define __EI_QUANTIZE__H__ + +#include +#include + +static int32_t pre_cast_quantize(float value, float scale, int32_t zero_point, bool is_signed) { + + int32_t max_value = is_signed ? 127 : 255; + int32_t min_value = is_signed ? -128 : 0; + // Saturate/clip any overflows post scaling + return std::min( std::max( static_cast(round(value / scale)) + zero_point, min_value), max_value); +} + +#endif //!__EI_QUANTIZE__H__ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_classifier.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_classifier.h new file mode 100644 index 0000000..d9b0e6f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_classifier.h @@ -0,0 +1,1134 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_RUN_CLASSIFIER_H_ +#define _EDGE_IMPULSE_RUN_CLASSIFIER_H_ + +#include "ei_model_types.h" +#include "model-parameters/model_metadata.h" + +#include "ei_run_dsp.h" +#include "ei_classifier_types.h" +#include "ei_signal_with_axes.h" +#include "ei_performance_calibration.h" + +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/porting/ei_logging.h" +#include + +#if EI_CLASSIFIER_HAS_ANOMALY +#include "inferencing_engines/anomaly.h" +#endif + +#if defined(EI_CLASSIFIER_HAS_SAMPLER) && EI_CLASSIFIER_HAS_SAMPLER == 1 +#include "ei_sampler.h" +#endif + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) && (EI_CLASSIFIER_COMPILED != 1) +#include "edge-impulse-sdk/classifier/inferencing_engines/tflite_micro.h" +#elif EI_CLASSIFIER_COMPILED == 1 +#include "edge-impulse-sdk/classifier/inferencing_engines/tflite_eon.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL +#include "edge-impulse-sdk/classifier/inferencing_engines/tflite_full.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_TIDL +#include "edge-impulse-sdk/classifier/inferencing_engines/tflite_tidl.h" +#elif (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSORRT) +#include "edge-impulse-sdk/classifier/inferencing_engines/tensorrt.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSAIFLOW +#include "edge-impulse-sdk/classifier/inferencing_engines/tensaiflow.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI +#include "edge-impulse-sdk/classifier/inferencing_engines/drpai.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_AKIDA +#include "edge-impulse-sdk/classifier/inferencing_engines/akida.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_ONNX_TIDL +#include "edge-impulse-sdk/classifier/inferencing_engines/onnx_tidl.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_MEMRYX +#include "edge-impulse-sdk/classifier/inferencing_engines/memryx.h" +#elif EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_NONE +// noop +#else +#error "Unknown inferencing engine" +#endif + +// This file has an implicit dependency on ei_run_dsp.h, so must come after that include! +#include "model-parameters/model_variables.h" + +#ifdef __cplusplus +namespace { +#endif // __cplusplus + +/* Function prototypes ----------------------------------------------------- */ +extern "C" EI_IMPULSE_ERROR run_inference(ei_impulse_handle_t *handle, ei_feature_t *fmatrix, ei_impulse_result_t *result, bool debug); +extern "C" EI_IMPULSE_ERROR run_classifier_image_quantized(const ei_impulse_t *impulse, signal_t *signal, ei_impulse_result_t *result, bool debug); +static EI_IMPULSE_ERROR can_run_classifier_image_quantized(const ei_impulse_t *impulse, ei_learning_block_t block_ptr); + +#if EI_CLASSIFIER_LOAD_IMAGE_SCALING +EI_IMPULSE_ERROR ei_scale_fmatrix(ei_learning_block_t *block, ei::matrix_t *fmatrix); +EI_IMPULSE_ERROR ei_unscale_fmatrix(ei_learning_block_t *block, ei::matrix_t *fmatrix); +#endif // EI_CLASSIFIER_LOAD_IMAGE_SCALING + +/* Private variables ------------------------------------------------------- */ + +static uint64_t classifier_continuous_features_written = 0; +static RecognizeEvents *avg_scores = NULL; + +/* Private functions ------------------------------------------------------- */ + +/* These functions (up to Public functions section) are not exposed to end-user, +therefore changes are allowed. */ + + +/** + * @brief Display the results of the inference + * + * @param result The result + */ +__attribute__((unused)) void display_results(ei_impulse_result_t* result) +{ + // print the predictions + ei_printf("Predictions (DSP: %d ms., Classification: %d ms., Anomaly: %d ms.): \n", + result->timing.dsp, result->timing.classification, result->timing.anomaly); +#if EI_CLASSIFIER_OBJECT_DETECTION == 1 + ei_printf("#Object detection results:\r\n"); + bool bb_found = result->bounding_boxes[0].value > 0; + for (size_t ix = 0; ix < result->bounding_boxes_count; ix++) { + auto bb = result->bounding_boxes[ix]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (", bb.label); + ei_printf_float(bb.value); + ei_printf(") [ x: %u, y: %u, width: %u, height: %u ]\n", bb.x, bb.y, bb.width, bb.height); + } + + if (!bb_found) { + ei_printf(" No objects found\n"); + } + +#elif (EI_CLASSIFIER_LABEL_COUNT == 1) && (!EI_CLASSIFIER_HAS_ANOMALY)// regression + ei_printf("#Regression results:\r\n"); + ei_printf(" %s: ", result->classification[0].label); + ei_printf_float(result->classification[0].value); + ei_printf("\n"); + +#elif EI_CLASSIFIER_LABEL_COUNT > 1 // if there is only one label, this is an anomaly only + ei_printf("#Classification results:\r\n"); + for (size_t ix = 0; ix < EI_CLASSIFIER_LABEL_COUNT; ix++) { + ei_printf(" %s: ", result->classification[ix].label); + ei_printf_float(result->classification[ix].value); + ei_printf("\n"); + } +#endif +#if EI_CLASSIFIER_HAS_ANOMALY == 3 // visual AD + ei_printf("#Visual anomaly grid results:\r\n"); + for (uint32_t i = 0; i < result->visual_ad_count; i++) { + ei_impulse_result_bounding_box_t bb = result->visual_ad_grid_cells[i]; + if (bb.value == 0) { + continue; + } + ei_printf(" %s (", bb.label); + ei_printf_float(bb.value); + ei_printf(") [ x: %u, y: %u, width: %u, height: %u ]\n", bb.x, bb.y, bb.width, bb.height); + } + ei_printf("Visual anomaly values: Mean "); + ei_printf_float(result->visual_ad_result.mean_value); + ei_printf(" Max "); + ei_printf_float(result->visual_ad_result.max_value); + ei_printf("\r\n"); +#elif (EI_CLASSIFIER_HAS_ANOMALY > 0) // except for visual AD + ei_printf("Anomaly prediction: "); + ei_printf_float(result->anomaly); + ei_printf("\r\n"); +#endif +} + +/** + * @brief Do inferencing over the processed feature matrix + * + * @param impulse struct with information about model and DSP + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +extern "C" EI_IMPULSE_ERROR run_inference( + ei_impulse_handle_t *handle, + ei_feature_t *fmatrix, + ei_impulse_result_t *result, + bool debug = false) +{ + auto& impulse = handle->impulse; + for (size_t ix = 0; ix < impulse->learning_blocks_size; ix++) { + + ei_learning_block_t block = impulse->learning_blocks[ix]; + +#if EI_CLASSIFIER_LOAD_IMAGE_SCALING + // we do not plan to have multiple dsp blocks with image + // so just apply scaling to the first one + EI_IMPULSE_ERROR scale_res = ei_scale_fmatrix(&block, fmatrix[0].matrix); + if (scale_res != EI_IMPULSE_OK) { + return scale_res; + } +#endif + + result->copy_output = block.keep_output; + + EI_IMPULSE_ERROR res = block.infer_fn(impulse, fmatrix, ix, (uint32_t*)block.input_block_ids, block.input_block_ids_size, result, block.config, debug); + if (res != EI_IMPULSE_OK) { + return res; + } + +#if EI_CLASSIFIER_LOAD_IMAGE_SCALING + // undo scaling + scale_res = ei_unscale_fmatrix(&block, fmatrix[0].matrix); + if (scale_res != EI_IMPULSE_OK) { + return scale_res; + } +#endif + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + return EI_IMPULSE_OK; +} + +/** + * @brief Process a complete impulse + * + * @param impulse struct with information about model and DSP + * @param signal Sample data + * @param result Output classifier results + * @param handle Handle from open_impulse. nullptr for backward compatibility + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +extern "C" EI_IMPULSE_ERROR process_impulse(ei_impulse_handle_t *handle, + signal_t *signal, + ei_impulse_result_t *result, + bool debug = false) +{ + if(!handle) { + return EI_IMPULSE_INFERENCE_ERROR; + } + +#if (EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 && (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSAIFLOW || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_ONNX_TIDL)) || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI + // Shortcut for quantized image models + ei_learning_block_t block = handle->impulse->learning_blocks[0]; + if (can_run_classifier_image_quantized(handle->impulse, block) == EI_IMPULSE_OK) { + return run_classifier_image_quantized(handle->impulse, signal, result, debug); + } +#endif + +#ifndef EI_DSP_RESULT_OVERRIDE + // Don't wipe in CI, as we store a pointer + memset(result, 0, sizeof(ei_impulse_result_t)); +#endif + uint32_t block_num = handle->impulse->dsp_blocks_size + handle->impulse->learning_blocks_size; + + // smart pointer to features array + std::unique_ptr features_ptr(new ei_feature_t[block_num]); + ei_feature_t* features = features_ptr.get(); + memset(features, 0, sizeof(ei_feature_t) * block_num); + + // have it outside of the loop to avoid going out of scope + std::unique_ptr *matrix_ptrs = new std::unique_ptr[block_num]; + + uint64_t dsp_start_us = ei_read_timer_us(); + + size_t out_features_index = 0; + + for (size_t ix = 0; ix < handle->impulse->dsp_blocks_size; ix++) { + ei_model_dsp_t block = handle->impulse->dsp_blocks[ix]; + matrix_ptrs[ix] = std::unique_ptr(new ei::matrix_t(1, block.n_output_features)); + features[ix].matrix = matrix_ptrs[ix].get(); + features[ix].blockId = block.blockId; + + if (out_features_index + block.n_output_features > handle->impulse->nn_input_frame_size) { + ei_printf("ERR: Would write outside feature buffer\n"); + delete[] matrix_ptrs; + return EI_IMPULSE_DSP_ERROR; + } + +#if EIDSP_SIGNAL_C_FN_POINTER + if (block.axes_size != handle->impulse->raw_samples_per_frame) { + ei_printf("ERR: EIDSP_SIGNAL_C_FN_POINTER can only be used when all axes are selected for DSP blocks\n"); + delete[] matrix_ptrs; + return EI_IMPULSE_DSP_ERROR; + } + auto internal_signal = signal; +#else + SignalWithAxes swa(signal, block.axes, block.axes_size, handle->impulse); + auto internal_signal = swa.get_signal(); +#endif + + int ret; + if (block.factory) { // ie, if we're using state + // Msg user + static bool has_printed = false; + if (!has_printed) { + EI_LOGI("Impulse maintains state. Call run_classifier_init() to reset state (e.g. if data stream is interrupted.)\n"); + has_printed = true; + } + + // getter has a lazy init, so we can just call it + auto dsp_handle = handle->state.get_dsp_handle(ix); + if(dsp_handle) { + ret = dsp_handle->extract(internal_signal, features[ix].matrix, block.config, handle->impulse->frequency); + } else { + return EI_IMPULSE_OUT_OF_MEMORY; + } + } else { + ret = block.extract_fn(internal_signal, features[ix].matrix, block.config, handle->impulse->frequency); + } + + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to run DSP process (%d)\n", ret); + delete[] matrix_ptrs; + return EI_IMPULSE_DSP_ERROR; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + delete[] matrix_ptrs; + return EI_IMPULSE_CANCELED; + } + + out_features_index += block.n_output_features; + } + +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + for (size_t ix = 0; ix < handle->impulse->learning_blocks_size; ix++) { + ei_learning_block_t block = handle->impulse->learning_blocks[ix]; + + if (block.keep_output) { + matrix_ptrs[handle->impulse->dsp_blocks_size + ix] = std::unique_ptr(new ei::matrix_t(1, block.output_features_count)); + features[handle->impulse->dsp_blocks_size + ix].matrix = matrix_ptrs[handle->impulse->dsp_blocks_size + ix].get(); + features[handle->impulse->dsp_blocks_size + ix].blockId = block.blockId; + } + } +#endif // EI_CLASSIFIER_SINGLE_FEATURE_INPUT + + result->timing.dsp_us = ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (debug) { + ei_printf("Features (%d ms.): ", result->timing.dsp); + for (size_t ix = 0; ix < block_num; ix++) { + if (features[ix].matrix == nullptr) { + continue; + } + for (size_t jx = 0; jx < features[ix].matrix->cols; jx++) { + ei_printf_float(features[ix].matrix->buffer[jx]); + ei_printf(" "); + } + ei_printf("\n"); + } + } + + if (debug) { + ei_printf("Running impulse...\n"); + } + + EI_IMPULSE_ERROR res = run_inference(handle, features, result, debug); + delete[] matrix_ptrs; + return res; +} + +/** + * @brief Opens an impulse + * + * @param impulse struct with information about model and DSP + * + * @return A pointer to the impulse handle, or nullptr if memory allocation failed. + */ +extern "C" EI_IMPULSE_ERROR init_impulse(ei_impulse_handle_t *handle) { + if (!handle) { + return EI_IMPULSE_OUT_OF_MEMORY; + } + handle->state.reset(); + return EI_IMPULSE_OK; +} + +/** + * @brief Process a complete impulse for continuous inference + * + * @param impulse struct with information about model and DSP + * @param signal Sample data + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +extern "C" EI_IMPULSE_ERROR process_impulse_continuous(ei_impulse_handle_t *handle, + signal_t *signal, + ei_impulse_result_t *result, + bool debug, + bool enable_maf) +{ + auto impulse = handle->impulse; + static ei::matrix_t static_features_matrix(1, impulse->nn_input_frame_size); + if (!static_features_matrix.buffer) { + return EI_IMPULSE_ALLOC_FAILED; + } + + memset(result, 0, sizeof(ei_impulse_result_t)); + + EI_IMPULSE_ERROR ei_impulse_error = EI_IMPULSE_OK; + + uint64_t dsp_start_us = ei_read_timer_us(); + + size_t out_features_index = 0; + + for (size_t ix = 0; ix < impulse->dsp_blocks_size; ix++) { + ei_model_dsp_t block = impulse->dsp_blocks[ix]; + + if (out_features_index + block.n_output_features > impulse->nn_input_frame_size) { + ei_printf("ERR: Would write outside feature buffer\n"); + return EI_IMPULSE_DSP_ERROR; + } + + ei::matrix_t fm(1, block.n_output_features, + static_features_matrix.buffer + out_features_index); + + int (*extract_fn_slice)(ei::signal_t *signal, ei::matrix_t *output_matrix, void *config, const float frequency, matrix_size_t *out_matrix_size); + + /* Switch to the slice version of the mfcc feature extract function */ + if (block.extract_fn == extract_mfcc_features) { + extract_fn_slice = &extract_mfcc_per_slice_features; + } + else if (block.extract_fn == extract_spectrogram_features) { + extract_fn_slice = &extract_spectrogram_per_slice_features; + } + else if (block.extract_fn == extract_mfe_features) { + extract_fn_slice = &extract_mfe_per_slice_features; + } + else { + ei_printf("ERR: Unknown extract function, only MFCC, MFE and spectrogram supported\n"); + return EI_IMPULSE_DSP_ERROR; + } + + matrix_size_t features_written; + +#if EIDSP_SIGNAL_C_FN_POINTER + if (block.axes_size != impulse->raw_samples_per_frame) { + ei_printf("ERR: EIDSP_SIGNAL_C_FN_POINTER can only be used when all axes are selected for DSP blocks\n"); + return EI_IMPULSE_DSP_ERROR; + } + int ret = extract_fn_slice(signal, &fm, block.config, impulse->frequency, &features_written); +#else + SignalWithAxes swa(signal, block.axes, block.axes_size, impulse); + int ret = extract_fn_slice(swa.get_signal(), &fm, block.config, impulse->frequency, &features_written); +#endif + + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to run DSP process (%d)\n", ret); + return EI_IMPULSE_DSP_ERROR; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + classifier_continuous_features_written += (features_written.rows * features_written.cols); + + out_features_index += block.n_output_features; + } + + result->timing.dsp_us = ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (classifier_continuous_features_written >= impulse->nn_input_frame_size) { + dsp_start_us = ei_read_timer_us(); + + uint32_t block_num = impulse->dsp_blocks_size + impulse->learning_blocks_size; + + // smart pointer to features array + std::unique_ptr features_ptr(new ei_feature_t[block_num]); + ei_feature_t* features = features_ptr.get(); + memset(features, 0, sizeof(ei_feature_t) * block_num); + + // have it outside of the loop to avoid going out of scope + std::unique_ptr *matrix_ptrs = new std::unique_ptr[block_num]; + + out_features_index = 0; + // iterate over every dsp block and run normalization + for (size_t ix = 0; ix < impulse->dsp_blocks_size; ix++) { + ei_model_dsp_t block = impulse->dsp_blocks[ix]; + matrix_ptrs[ix] = std::unique_ptr(new ei::matrix_t(1, block.n_output_features)); + features[ix].matrix = matrix_ptrs[ix].get(); + features[ix].blockId = block.blockId; + + /* Create a copy of the matrix for normalization */ + for (size_t m_ix = 0; m_ix < block.n_output_features; m_ix++) { + features[ix].matrix->buffer[m_ix] = static_features_matrix.buffer[out_features_index + m_ix]; + } + + if (block.extract_fn == extract_mfcc_features) { + calc_cepstral_mean_and_var_normalization_mfcc(features[ix].matrix, block.config); + } + else if (block.extract_fn == extract_spectrogram_features) { + calc_cepstral_mean_and_var_normalization_spectrogram(features[ix].matrix, block.config); + } + else if (block.extract_fn == extract_mfe_features) { + calc_cepstral_mean_and_var_normalization_mfe(features[ix].matrix, block.config); + } + out_features_index += block.n_output_features; + } + + result->timing.dsp_us += ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (debug) { + ei_printf("Feature Matrix: \n"); + for (size_t ix = 0; ix < features->matrix->cols; ix++) { + ei_printf_float(features->matrix->buffer[ix]); + ei_printf(" "); + } + ei_printf("\n"); + ei_printf("Running impulse...\n"); + } + + ei_impulse_error = run_inference(handle, features, result, debug); + +#if EI_CLASSIFIER_CALIBRATION_ENABLED + if (impulse->sensor == EI_CLASSIFIER_SENSOR_MICROPHONE) { + if((void *)avg_scores != NULL && enable_maf == true) { + if (enable_maf && !impulse->calibration.is_configured) { + // perfcal is not configured, print msg first time + static bool has_printed_msg = false; + + if (!has_printed_msg) { + ei_printf("WARN: run_classifier_continuous, enable_maf is true, but performance calibration is not configured.\n"); + ei_printf(" Previously we'd run a moving-average filter over your outputs in this case, but this is now disabled.\n"); + ei_printf(" Go to 'Performance calibration' in your Edge Impulse project to configure post-processing parameters.\n"); + ei_printf(" (You can enable this from 'Dashboard' if it's not visible in your project)\n"); + ei_printf("\n"); + + has_printed_msg = true; + } + } + else { + // perfcal is configured + static bool has_printed_msg = false; + + if (!has_printed_msg) { + ei_printf("\nPerformance calibration is configured for your project. If no event is detected, all values are 0.\r\n\n"); + has_printed_msg = true; + } + + int label_detected = avg_scores->trigger(result->classification); + + if (avg_scores->should_boost()) { + for (int i = 0; i < impulse->label_count; i++) { + if (i == label_detected) { + result->classification[i].value = 1.0f; + } + else { + result->classification[i].value = 0.0f; + } + } + } + } + } + } +#endif + delete[] matrix_ptrs; + } + else { + for (int i = 0; i < impulse->label_count; i++) { + // set label correctly in the result struct if we have no results (otherwise is nullptr) + result->classification[i].label = impulse->categories[(uint32_t)i]; + } + } + + return ei_impulse_error; +} + +/** + * Check if the current impulse could be used by 'run_classifier_image_quantized' + */ +__attribute__((unused)) static EI_IMPULSE_ERROR can_run_classifier_image_quantized(const ei_impulse_t *impulse, ei_learning_block_t block_ptr) { + + if (impulse->inferencing_engine != EI_CLASSIFIER_TFLITE + && impulse->inferencing_engine != EI_CLASSIFIER_TENSAIFLOW + && impulse->inferencing_engine != EI_CLASSIFIER_DRPAI + && impulse->inferencing_engine != EI_CLASSIFIER_ONNX_TIDL) // check later + { + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + + // visual anomaly also needs to go through the normal path + if (impulse->has_anomaly){ + return EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES; + } + + // Check if we have tflite graph + if (block_ptr.infer_fn != run_nn_inference) { + return EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES; + } + + // Check if we have a quantized NN Input layer (input is always quantized for DRP-AI) + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)block_ptr.config; + if (block_config->quantized != 1) { + return EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES; + } + + // And if we have one DSP block which operates on images... + if (impulse->dsp_blocks_size != 1 || impulse->dsp_blocks[0].extract_fn != extract_image_features) { + return EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES; + } + + return EI_IMPULSE_OK; +} + +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 && (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSAIFLOW || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_ONNX_TIDL) + +/** + * Special function to run the classifier on images, only works on TFLite models (either interpreter, EON, tensaiflow, drpai, tidl, memryx) + * that allocates a lot less memory by quantizing in place. This only works if 'can_run_classifier_image_quantized' + * returns EI_IMPULSE_OK. + */ +extern "C" EI_IMPULSE_ERROR run_classifier_image_quantized( + const ei_impulse_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + bool debug = false) +{ + memset(result, 0, sizeof(ei_impulse_result_t)); + + return run_nn_inference_image_quantized(impulse, signal, result, impulse->learning_blocks[0].config, debug); +} + +#endif // #if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 && (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSAIFLOW || EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI) + +#if EI_CLASSIFIER_LOAD_IMAGE_SCALING +static const float torch_mean[] = { 0.485, 0.456, 0.406 }; +static const float torch_std[] = { 0.229, 0.224, 0.225 }; +// This is ordered BGR +static const float tao_mean[] = { 103.939, 116.779, 123.68 }; + +EI_IMPULSE_ERROR ei_scale_fmatrix(ei_learning_block_t *block, ei::matrix_t *fmatrix) { + if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_TORCH) { + // @todo; could we write some faster vector math here? + for (size_t ix = 0; ix < fmatrix->rows * fmatrix->cols; ix += 3) { + fmatrix->buffer[ix + 0] = (fmatrix->buffer[ix + 0] - torch_mean[0]) / torch_std[0]; + fmatrix->buffer[ix + 1] = (fmatrix->buffer[ix + 1] - torch_mean[1]) / torch_std[1]; + fmatrix->buffer[ix + 2] = (fmatrix->buffer[ix + 2] - torch_mean[2]) / torch_std[2]; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_0_255) { + int scale_res = numpy::scale(fmatrix, 255.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_MIN128_127) { + int scale_res = numpy::scale(fmatrix, 255.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + scale_res = numpy::subtract(fmatrix, 128.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_MIN1_1) { + int scale_res = numpy::scale(fmatrix, 2.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + scale_res = numpy::subtract(fmatrix, 1.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_BGR_SUBTRACT_IMAGENET_MEAN) { + int scale_res = numpy::scale(fmatrix, 255.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + // Transpose RGB to BGR and subtract mean + for (size_t ix = 0; ix < fmatrix->rows * fmatrix->cols; ix += 3) { + float r = fmatrix->buffer[ix + 0]; + fmatrix->buffer[ix + 0] = fmatrix->buffer[ix + 2] - tao_mean[0]; + fmatrix->buffer[ix + 1] -= tao_mean[1]; + fmatrix->buffer[ix + 2] = r - tao_mean[2]; + } + } + + return EI_IMPULSE_OK; +} + +EI_IMPULSE_ERROR ei_unscale_fmatrix(ei_learning_block_t *block, ei::matrix_t *fmatrix) { + if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_TORCH) { + // @todo; could we write some faster vector math here? + for (size_t ix = 0; ix < fmatrix->rows * fmatrix->cols; ix += 3) { + fmatrix->buffer[ix + 0] = (fmatrix->buffer[ix + 0] * torch_std[0]) + torch_mean[0]; + fmatrix->buffer[ix + 1] = (fmatrix->buffer[ix + 1] * torch_std[1]) + torch_mean[1]; + fmatrix->buffer[ix + 2] = (fmatrix->buffer[ix + 2] * torch_std[2]) + torch_mean[2]; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_MIN128_127) { + int scale_res = numpy::add(fmatrix, 128.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + scale_res = numpy::scale(fmatrix, 1 / 255.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_MIN1_1) { + int scale_res = numpy::add(fmatrix, 1.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + scale_res = numpy::scale(fmatrix, 1 / 2.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_0_255) { + int scale_res = numpy::scale(fmatrix, 1 / 255.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + } + else if (block->image_scaling == EI_CLASSIFIER_IMAGE_SCALING_BGR_SUBTRACT_IMAGENET_MEAN) { + // Transpose BGR to RGB and add mean + for (size_t ix = 0; ix < fmatrix->rows * fmatrix->cols; ix += 3) { + float b = fmatrix->buffer[ix + 0]; + fmatrix->buffer[ix + 0] = fmatrix->buffer[ix + 2] + tao_mean[2]; + fmatrix->buffer[ix + 1] += tao_mean[1]; + fmatrix->buffer[ix + 2] = b + tao_mean[0]; + } + int scale_res = numpy::scale(fmatrix, 1 / 255.0f); + if (scale_res != EIDSP_OK) { + ei_printf("ERR: Failed to scale matrix (%d)\n", scale_res); + return EI_IMPULSE_DSP_ERROR; + } + } + return EI_IMPULSE_OK; +} +#endif + +/* Public functions ------------------------------------------------------- */ + +/* Tread carefully: public functions are not to be changed +to preserve backwards compatibility. Anything in this public section +will be documented by Doxygen. */ + +/** + * @defgroup ei_functions Functions + * + * Public-facing functions for running inference using the Edge Impulse C++ library. + * + * **Source**: [classifier/ei_run_classifier.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/classifier/ei_run_classifier.h) + * + * @addtogroup ei_functions + * @{ + */ + +/** + * @brief Initialize static variables for running preprocessing and inference + * continuously. + * + * Initializes and clears any internal static variables needed by `run_classifier_continuous()`. + * This includes the moving average filter (MAF). This function should be called prior to + * calling `run_classifier_continuous()`. + * + * **Blocking**: yes + * + * **Example**: [nano_ble33_sense_microphone_continuous.ino](https://github.com/edgeimpulse/example-lacuna-ls200/blob/main/nano_ble33_sense_microphone_continous/nano_ble33_sense_microphone_continuous.ino) + */ +extern "C" void run_classifier_init(void) +{ + + classifier_continuous_features_written = 0; + ei_dsp_clear_continuous_audio_state(); + init_impulse(&ei_default_impulse); + +#if EI_CLASSIFIER_CALIBRATION_ENABLED + + const auto impulse = ei_default_impulse.impulse; + const ei_model_performance_calibration_t *calibration = &impulse->calibration; + + if(calibration != NULL) { + avg_scores = new RecognizeEvents(calibration, + impulse->label_count, impulse->slice_size, impulse->interval_ms); + } +#endif +} + +/** + * @brief Initialize static variables for running preprocessing and inference + * continuously. + * + * Initializes and clears any internal static variables needed by `run_classifier_continuous()`. + * This includes the moving average filter (MAF). This function should be called prior to + * calling `run_classifier_continuous()`. + * + * **Blocking**: yes + * + * **Example**: [nano_ble33_sense_microphone_continuous.ino](https://github.com/edgeimpulse/example-lacuna-ls200/blob/main/nano_ble33_sense_microphone_continous/nano_ble33_sense_microphone_continuous.ino) + * + * @param[in] handle struct with information about model and DSP + */ +__attribute__((unused)) void run_classifier_init(ei_impulse_handle_t *handle) +{ + classifier_continuous_features_written = 0; + ei_dsp_clear_continuous_audio_state(); + init_impulse(handle); + +#if EI_CLASSIFIER_CALIBRATION_ENABLED + auto impulse = handle->impulse; + const ei_model_performance_calibration_t *calibration = &impulse->calibration; + + if(calibration != NULL) { + avg_scores = new RecognizeEvents(calibration, + impulse->label_count, impulse->slice_size, impulse->interval_ms); + } +#endif +} + +/** + * @brief Deletes static variables when running preprocessing and inference continuously. + * + * Deletes internal static variables used by `run_classifier_continuous()`, which + * includes the moving average filter (MAF). This function should be called when you + * are done running continuous classification. + * + * **Blocking**: yes + * + * **Example**: [ei_run_audio_impulse.cpp](https://github.com/edgeimpulse/firmware-nordic-thingy53/blob/main/src/inference/ei_run_audio_impulse.cpp) + */ +extern "C" void run_classifier_deinit(void) +{ + if((void *)avg_scores != NULL) { + delete avg_scores; + } +} + +/** + * @brief Run preprocessing (DSP) on new slice of raw features. Add output features + * to rolling matrix and run inference on full sample. + * + * Accepts a new slice of features give by the callback defined in the `signal` parameter. + * It performs preprocessing (DSP) on this new slice of features and appends the output to + * a sliding window of pre-processed features (stored in a static features matrix). The matrix + * stores the new slice and as many old slices as necessary to make up one full sample for + * performing inference. + * + * `run_classifier_init()` must be called before making any calls to + * `run_classifier_continuous().` + * + * For example, if you are doing keyword spotting on 1-second slices of audio and you want to + * perform inference 4 times per second (given by `EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW`), you + * would collect 0.25 seconds of audio and call run_classifier_continuous(). The function would + * compute the Mel-Frequency Cepstral Coefficients (MFCCs) for that 0.25 second slice of audio, + * drop the oldest 0.25 seconds' worth of MFCCs from its internal matrix, and append the newest + * slice of MFCCs. This process allows the library to keep track of the pre-processed features + * (e.g. MFCCs) in the window instead of the entire set of raw features (e.g. raw audio data), + * which can potentially save a lot of space in RAM. After updating the static matrix, + * inference is performed using the whole matrix, which acts as a sliding window of + * pre-processed features. + * + * Additionally, a moving average filter (MAF) can be enabled for `run_classifier_continuous()`, + * which averages (arithmetic mean) the last *n* inference results for each class. *n* is + * `EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW / 2`. In our example above, if we enabled the MAF, the + * values in `result` would contain predictions averaged from the previous 2 inferences. + * + * To learn more about `run_classifier_continuous()`, see + * [this guide](https://docs.edgeimpulse.com/docs/tutorials/advanced-inferencing/continuous-audio-sampling) + * on continuous audio sampling. While the guide is written for audio signals, the concepts of continuous sampling and inference can be extrapolated to any time-series data. + * + * **Blocking**: yes + * + * **Example**: [nano_ble33_sense_microphone_continuous.ino](https://github.com/edgeimpulse/example-lacuna-ls200/blob/main/nano_ble33_sense_microphone_continous/nano_ble33_sense_microphone_continuous.ino) + * + * @param[in] signal Pointer to a signal_t struct that contains the number of elements in the + * slice of raw features (e.g. `EI_CLASSIFIER_SLICE_SIZE`) and a pointer to a callback that reads + * in the slice of raw features. + * @param[out] result Pointer to an `ei_impulse_result_t` struct that contains the various output + * results from inference after run_classifier() returns. + * @param[in] debug Print internal preprocessing and inference debugging information via + * `ei_printf()`. + * @param[in] enable_maf Enable the moving average filter (MAF) for the classifier. + * + * @return Error code as defined by `EI_IMPULSE_ERROR` enum. Will be `EI_IMPULSE_OK` if inference + * completed successfully. + */ +extern "C" EI_IMPULSE_ERROR run_classifier_continuous( + signal_t *signal, + ei_impulse_result_t *result, + bool debug = false, + bool enable_maf = true) +{ + auto& impulse = ei_default_impulse; + return process_impulse_continuous(&impulse, signal, result, debug, enable_maf); +} + +/** + * @brief Run preprocessing (DSP) on new slice of raw features. Add output features + * to rolling matrix and run inference on full sample. + * + * Accepts a new slice of features give by the callback defined in the `signal` parameter. + * It performs preprocessing (DSP) on this new slice of features and appends the output to + * a sliding window of pre-processed features (stored in a static features matrix). The matrix + * stores the new slice and as many old slices as necessary to make up one full sample for + * performing inference. + * + * `run_classifier_init()` must be called before making any calls to + * `run_classifier_continuous().` + * + * For example, if you are doing keyword spotting on 1-second slices of audio and you want to + * perform inference 4 times per second (given by `EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW`), you + * would collect 0.25 seconds of audio and call run_classifier_continuous(). The function would + * compute the Mel-Frequency Cepstral Coefficients (MFCCs) for that 0.25 second slice of audio, + * drop the oldest 0.25 seconds' worth of MFCCs from its internal matrix, and append the newest + * slice of MFCCs. This process allows the library to keep track of the pre-processed features + * (e.g. MFCCs) in the window instead of the entire set of raw features (e.g. raw audio data), + * which can potentially save a lot of space in RAM. After updating the static matrix, + * inference is performed using the whole matrix, which acts as a sliding window of + * pre-processed features. + * + * Additionally, a moving average filter (MAF) can be enabled for `run_classifier_continuous()`, + * which averages (arithmetic mean) the last *n* inference results for each class. *n* is + * `EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW / 2`. In our example above, if we enabled the MAF, the + * values in `result` would contain predictions averaged from the previous 2 inferences. + * + * To learn more about `run_classifier_continuous()`, see + * [this guide](https://docs.edgeimpulse.com/docs/tutorials/advanced-inferencing/continuous-audio-sampling) + * on continuous audio sampling. While the guide is written for audio signals, the concepts of continuous sampling and inference can be extrapolated to any time-series data. + * + * **Blocking**: yes + * + * **Example**: [nano_ble33_sense_microphone_continuous.ino](https://github.com/edgeimpulse/example-lacuna-ls200/blob/main/nano_ble33_sense_microphone_continous/nano_ble33_sense_microphone_continuous.ino) + * + * @param[in] impulse `ei_impulse_handle_t` struct with information about preprocessing and model. + * @param[in] signal Pointer to a signal_t struct that contains the number of elements in the + * slice of raw features (e.g. `EI_CLASSIFIER_SLICE_SIZE`) and a pointer to a callback that reads + * in the slice of raw features. + * @param[out] result Pointer to an `ei_impulse_result_t` struct that contains the various output + * results from inference after run_classifier() returns. + * @param[in] debug Print internal preprocessing and inference debugging information via + * `ei_printf()`. + * @param[in] enable_maf Enable the moving average filter (MAF) for the classifier. + * + * @return Error code as defined by `EI_IMPULSE_ERROR` enum. Will be `EI_IMPULSE_OK` if inference + * completed successfully. + */ +__attribute__((unused)) EI_IMPULSE_ERROR run_classifier_continuous( + ei_impulse_handle_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + bool debug = false, + bool enable_maf = true) +{ + return process_impulse_continuous(impulse, signal, result, debug, enable_maf); +} + +/** + * @brief Run the classifier over a raw features array. + * + * + * Overloaded function [run_classifier()](#run_classifier-1) that defaults to the single impulse. + * + * **Blocking**: yes + * + * @param[in] signal Pointer to a `signal_t` struct that contains the total length of the raw + * feature array, which must match EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, and a pointer to a callback + * that reads in the raw features. + * @param[out] result Pointer to an ei_impulse_result_t struct that will contain the various output + * results from inference after `run_classifier()` returns. + * @param[in] debug Print internal preprocessing and inference debugging information via `ei_printf()`. + * + * @return Error code as defined by `EI_IMPULSE_ERROR` enum. Will be `EI_IMPULSE_OK` if inference + * completed successfully. + */ +extern "C" EI_IMPULSE_ERROR run_classifier( + signal_t *signal, + ei_impulse_result_t *result, + bool debug = false) +{ + return process_impulse(&ei_default_impulse, signal, result, debug); +} + +/** + * @brief Run the classifier over a raw features array. + * + * + * Accepts a `signal_t` input struct pointing to a callback that reads in pages of raw features. + * `run_classifier()` performs any necessary preprocessing on the raw features (e.g. DSP, cropping + * of images, etc.) before performing inference. Results from inference are stored in an + * `ei_impulse_result_t` struct. + * + * **Blocking**: yes + * + * **Example**: [standalone inferencing main.cpp](https://github.com/edgeimpulse/example-standalone-inferencing/blob/master/source/main.cpp) + * + * @param[in] impulse Pointer to an `ei_impulse_handle_t` struct that contains the model and + * preprocessing information. + * @param[in] signal Pointer to a `signal_t` struct that contains the total length of the raw + * feature array, which must match EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, and a pointer to a callback + * that reads in the raw features. + * @param[out] result Pointer to an ei_impulse_result_t struct that will contain the various output + * results from inference after `run_classifier()` returns. + * @param[in] debug Print internal preprocessing and inference debugging information via `ei_printf()`. + * + * @return Error code as defined by `EI_IMPULSE_ERROR` enum. Will be `EI_IMPULSE_OK` if inference + * completed successfully. + */ +__attribute__((unused)) EI_IMPULSE_ERROR run_classifier( + ei_impulse_handle_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + bool debug = false) +{ + return process_impulse(impulse, signal, result, debug); +} + +/** @} */ // end of ei_functions Doxygen group + +/* Deprecated functions ------------------------------------------------------- */ + +/* These functions are being deprecated and possibly will be removed or moved in future. +Do not use these - if possible, change your code to reflect the upcoming changes. */ + +#if EIDSP_SIGNAL_C_FN_POINTER == 0 + +/** + * @brief Run the impulse, if you provide an instance of sampler it will also persist + * the data for you. + * + * @deprecated This function is deprecated and will be removed in future versions. Use + * `run_classifier()` instead. + * + * @param[in] sampler Instance to an **initialized** sampler + * @param[out] result Object to store the results in + * @param[in] data_fn Callback function to retrieve data from sensors + * @param[in] debug Whether to log debug messages (default false) + * + * @return Error code as defined by `EI_IMPULSE_ERROR` enum. Will be `EI_IMPULSE_OK` if inference + * completed successfully. + */ +__attribute__((unused)) EI_IMPULSE_ERROR run_impulse( +#if (defined(EI_CLASSIFIER_HAS_SAMPLER) && EI_CLASSIFIER_HAS_SAMPLER == 1) || defined(__DOXYGEN__) + EdgeSampler *sampler, +#endif + ei_impulse_result_t *result, +#ifdef __MBED__ + mbed::Callback data_fn, +#else + std::function data_fn, +#endif + bool debug = false) { + + auto& impulse = *(ei_default_impulse.impulse); + + float *x = (float*)calloc(impulse.dsp_input_frame_size, sizeof(float)); + if (!x) { + return EI_IMPULSE_OUT_OF_MEMORY; + } + + uint64_t next_tick = 0; + + uint64_t sampling_us_start = ei_read_timer_us(); + + // grab some data + for (int i = 0; i < (int)impulse.dsp_input_frame_size; i += impulse.raw_samples_per_frame) { + uint64_t curr_us = ei_read_timer_us() - sampling_us_start; + + next_tick = curr_us + (impulse.interval_ms * 1000); + + data_fn(x + i, impulse.raw_samples_per_frame); +#if defined(EI_CLASSIFIER_HAS_SAMPLER) && EI_CLASSIFIER_HAS_SAMPLER == 1 + if (sampler != NULL) { + sampler->write_sensor_data(x + i, impulse.raw_samples_per_frame); + } +#endif + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + free(x); + return EI_IMPULSE_CANCELED; + } + + while (next_tick > ei_read_timer_us() - sampling_us_start); + } + + result->timing.sampling = (ei_read_timer_us() - sampling_us_start) / 1000; + + signal_t signal; + int err = numpy::signal_from_buffer(x, impulse.dsp_input_frame_size, &signal); + if (err != 0) { + free(x); + ei_printf("ERR: signal_from_buffer failed (%d)\n", err); + return EI_IMPULSE_DSP_ERROR; + } + + EI_IMPULSE_ERROR r = run_classifier(&signal, result, debug); + free(x); + return r; +} + +#if (defined(EI_CLASSIFIER_HAS_SAMPLER) && EI_CLASSIFIER_HAS_SAMPLER == 1) || defined(__DOXYGEN__) +/** + * @brief Run the impulse, does not persist data. + * + * @deprecated This function is deprecated and will be removed in future versions. Use + * `run_classifier()` instead. + * + * @param[out] result Object to store the results in + * @param[in] data_fn Callback function to retrieve data from sensors + * @param[out] debug Whether to log debug messages (default false) + * + * @return Error code as defined by `EI_IMPULSE_ERROR` enum. Will be `EI_IMPULSE_OK` if inference + * completed successfully. + */ +__attribute__((unused)) EI_IMPULSE_ERROR run_impulse( + ei_impulse_result_t *result, +#ifdef __MBED__ + mbed::Callback data_fn, +#else + std::function data_fn, +#endif + bool debug = false) { + return run_impulse(NULL, result, data_fn, debug); +} +#endif + +#endif // #if EIDSP_SIGNAL_C_FN_POINTER == 0 + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // _EDGE_IMPULSE_RUN_CLASSIFIER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_classifier_image.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_classifier_image.h new file mode 100644 index 0000000..37ff775 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_classifier_image.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2022 Edge Impulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_RUN_CLASSIFIER_IMAGE_H_ +#define _EDGE_IMPULSE_RUN_CLASSIFIER_IMAGE_H_ + +#include "ei_run_classifier.h" + + + +#endif // _EDGE_IMPULSE_RUN_CLASSIFIER_IMAGE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_dsp.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_dsp.h new file mode 100644 index 0000000..e46612c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_run_dsp.h @@ -0,0 +1,1461 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_RUN_DSP_H_ +#define _EDGE_IMPULSE_RUN_DSP_H_ + +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/dsp/spectral/spectral.hpp" +#include "edge-impulse-sdk/dsp/speechpy/speechpy.hpp" +#include "edge-impulse-sdk/classifier/ei_signal_with_range.h" +#include "edge-impulse-sdk/dsp/ei_flatten.h" +#include "model-parameters/model_metadata.h" + +#if EI_CLASSIFIER_HR_ENABLED +#include "edge-impulse-sdk/dsp/ei_hr.hpp" +#endif + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" { + extern void ei_printf(const char *format, ...); +} +#else +extern void ei_printf(const char *format, ...); +#endif + +#ifdef __cplusplus +namespace { +#endif // __cplusplus + +using namespace ei; + +#if defined(EI_DSP_IMAGE_BUFFER_STATIC_SIZE) +float ei_dsp_image_buffer[EI_DSP_IMAGE_BUFFER_STATIC_SIZE]; +#endif + +// this is the frame we work on... allocate it statically so we share between invocations +static float *ei_dsp_cont_current_frame = nullptr; +static size_t ei_dsp_cont_current_frame_size = 0; +static int ei_dsp_cont_current_frame_ix = 0; + +__attribute__((unused)) int extract_hr_features( + signal_t *signal, + matrix_t *output_matrix, + void *config_ptr, + const float frequency) +{ +#if EI_CLASSIFIER_HR_ENABLED + auto handle = hr_class::create(config_ptr, frequency); + auto ret = handle->extract(signal, output_matrix, config_ptr, frequency); + delete handle; + return ret; +#else + ei_printf("ERR: Please contact EI sales to enable heart rate processing in deployment"); + return EIDSP_NOT_SUPPORTED; +#endif +} + +__attribute__((unused)) int extract_spectral_analysis_features( + signal_t *signal, + matrix_t *output_matrix, + void *config_ptr, + const float frequency) +{ + ei_dsp_config_spectral_analysis_t *config = (ei_dsp_config_spectral_analysis_t *)config_ptr; + + // input matrix from the raw signal + matrix_t input_matrix(signal->total_length / config->axes, config->axes); + if (!input_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + signal->get_data(0, signal->total_length, input_matrix.buffer); + +#if EI_DSP_PARAMS_SPECTRAL_ANALYSIS_ANALYSIS_TYPE_WAVELET || EI_DSP_PARAMS_ALL + if (strcmp(config->analysis_type, "Wavelet") == 0) { + return spectral::wavelet::extract_wavelet_features(&input_matrix, output_matrix, config, frequency); + } +#endif + +#if EI_DSP_PARAMS_SPECTRAL_ANALYSIS_ANALYSIS_TYPE_FFT || EI_DSP_PARAMS_ALL + if (strcmp(config->analysis_type, "FFT") == 0) { + if (config->implementation_version == 1) { + return spectral::feature::extract_spectral_analysis_features_v1( + &input_matrix, + output_matrix, + config, + frequency); + } else if (config->implementation_version == 4) { + return spectral::feature::extract_spectral_analysis_features_v4( + &input_matrix, + output_matrix, + config, + frequency); + } else { + return spectral::feature::extract_spectral_analysis_features_v2( + &input_matrix, + output_matrix, + config, + frequency); + } + } +#endif + +#if !EI_DSP_PARAMS_GENERATED || EI_DSP_PARAMS_ALL || !(EI_DSP_PARAMS_SPECTRAL_ANALYSIS_ANALYSIS_TYPE_FFT || EI_DSP_PARAMS_SPECTRAL_ANALYSIS_ANALYSIS_TYPE_WAVELET) + if (config->implementation_version == 1) { + return spectral::feature::extract_spectral_analysis_features_v1( + &input_matrix, + output_matrix, + config, + frequency); + } + if (config->implementation_version == 2) { + return spectral::feature::extract_spectral_analysis_features_v2( + &input_matrix, + output_matrix, + config, + frequency); + } +#endif + return EIDSP_NOT_SUPPORTED; +} + +__attribute__((unused)) int extract_raw_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float frequency) { + ei_dsp_config_raw_t config = *((ei_dsp_config_raw_t*)config_ptr); + + // Because of rounding errors during re-sampling the output size of the block might be + // smaller than the input of the block. Make sure we don't write outside of the bounds + // of the array: + // https://forum.edgeimpulse.com/t/using-custom-sensors-on-raspberry-pi-4/3506/7 + size_t els_to_copy = signal->total_length; + if (els_to_copy > output_matrix->rows * output_matrix->cols) { + els_to_copy = output_matrix->rows * output_matrix->cols; + } + + signal->get_data(0, els_to_copy, output_matrix->buffer); + + // scale the signal + int ret = numpy::scale(output_matrix, config.scale_axes); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + return EIDSP_OK; +} + +__attribute__((unused)) int extract_flatten_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float frequency) { + auto handle = flatten_class::create(config_ptr, frequency); + auto ret = handle->extract(signal, output_matrix, config_ptr, frequency); + delete handle; + return ret; +} + +static class speechpy::processing::preemphasis *preemphasis; +static int preemphasized_audio_signal_get_data(size_t offset, size_t length, float *out_ptr) { + return preemphasis->get_data(offset, length, out_ptr); +} + +__attribute__((unused)) int extract_mfcc_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float sampling_frequency) { + ei_dsp_config_mfcc_t config = *((ei_dsp_config_mfcc_t*)config_ptr); + + if (config.axes != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if((config.implementation_version == 0) || (config.implementation_version > 4)) { + EIDSP_ERR(EIDSP_BLOCK_VERSION_INCORRECT); + } + + if (signal->total_length == 0) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + const uint32_t frequency = static_cast(sampling_frequency); + + // preemphasis class to preprocess the audio... + class speechpy::processing::preemphasis pre(signal, config.pre_shift, config.pre_cof, false); + preemphasis = ⪯ + + signal_t preemphasized_audio_signal; + preemphasized_audio_signal.total_length = signal->total_length; + preemphasized_audio_signal.get_data = &preemphasized_audio_signal_get_data; + + // calculate the size of the MFCC matrix + matrix_size_t out_matrix_size = + speechpy::feature::calculate_mfcc_buffer_size( + signal->total_length, frequency, config.frame_length, config.frame_stride, config.num_cepstral, config.implementation_version); + /* Only throw size mismatch error calculated buffer doesn't fit for continuous inferencing */ + if (out_matrix_size.rows * out_matrix_size.cols > output_matrix->rows * output_matrix->cols) { + ei_printf("out_matrix = %dx%d\n", (int)output_matrix->rows, (int)output_matrix->cols); + ei_printf("calculated size = %dx%d\n", (int)out_matrix_size.rows, (int)out_matrix_size.cols); + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + output_matrix->rows = out_matrix_size.rows; + output_matrix->cols = out_matrix_size.cols; + + // and run the MFCC extraction + int ret = speechpy::feature::mfcc(output_matrix, &preemphasized_audio_signal, + frequency, config.frame_length, config.frame_stride, config.num_cepstral, config.num_filters, config.fft_length, + config.low_frequency, config.high_frequency, true, config.implementation_version); + if (ret != EIDSP_OK) { + ei_printf("ERR: MFCC failed (%d)\n", ret); + EIDSP_ERR(ret); + } + + // cepstral mean and variance normalization + ret = speechpy::processing::cmvnw(output_matrix, config.win_size, true, false); + if (ret != EIDSP_OK) { + ei_printf("ERR: cmvnw failed (%d)\n", ret); + EIDSP_ERR(ret); + } + + output_matrix->cols = out_matrix_size.rows * out_matrix_size.cols; + output_matrix->rows = 1; + + return EIDSP_OK; +} + + +__attribute__((unused)) static int extract_mfcc_run_slice(signal_t *signal, matrix_t *output_matrix, ei_dsp_config_mfcc_t *config, const float sampling_frequency, matrix_size_t *matrix_size_out, int implementation_version) { + uint32_t frequency = (uint32_t)sampling_frequency; + + int x; + + // calculate the size of the spectrogram matrix + matrix_size_t out_matrix_size = + speechpy::feature::calculate_mfcc_buffer_size( + signal->total_length, frequency, config->frame_length, config->frame_stride, config->num_cepstral, + implementation_version); + + // we roll the output matrix back so we have room at the end... + x = numpy::roll(output_matrix->buffer, output_matrix->rows * output_matrix->cols, + -(out_matrix_size.rows * out_matrix_size.cols)); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // slice in the output matrix to write to + // the offset in the classification matrix here is always at the end + size_t output_matrix_offset = (output_matrix->rows * output_matrix->cols) - + (out_matrix_size.rows * out_matrix_size.cols); + + matrix_t output_matrix_slice(out_matrix_size.rows, out_matrix_size.cols, output_matrix->buffer + output_matrix_offset); + + // and run the MFCC extraction + x = speechpy::feature::mfcc(&output_matrix_slice, signal, + frequency, config->frame_length, config->frame_stride, config->num_cepstral, config->num_filters, config->fft_length, + config->low_frequency, config->high_frequency, true, implementation_version); + if (x != EIDSP_OK) { + ei_printf("ERR: MFCC failed (%d)\n", x); + EIDSP_ERR(x); + } + + matrix_size_out->rows += out_matrix_size.rows; + if (out_matrix_size.cols > 0) { + matrix_size_out->cols = out_matrix_size.cols; + } + + return EIDSP_OK; +} + +__attribute__((unused)) int extract_mfcc_per_slice_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float sampling_frequency, matrix_size_t *matrix_size_out) { +#if defined(__cplusplus) && EI_C_LINKAGE == 1 + ei_printf("ERR: Continuous audio is not supported when EI_C_LINKAGE is defined\n"); + EIDSP_ERR(EIDSP_NOT_SUPPORTED); +#else + + ei_dsp_config_mfcc_t config = *((ei_dsp_config_mfcc_t*)config_ptr); + + if (config.axes != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if((config.implementation_version == 0) || (config.implementation_version > 4)) { + EIDSP_ERR(EIDSP_BLOCK_VERSION_INCORRECT); + } + + if (signal->total_length == 0) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + const uint32_t frequency = static_cast(sampling_frequency); + + // preemphasis class to preprocess the audio... + class speechpy::processing::preemphasis pre(signal, config.pre_shift, config.pre_cof, false); + preemphasis = ⪯ + + signal_t preemphasized_audio_signal; + preemphasized_audio_signal.total_length = signal->total_length; + preemphasized_audio_signal.get_data = &preemphasized_audio_signal_get_data; + + // Go from the time (e.g. 0.25 seconds to number of frames based on freq) + const size_t frame_length_values = frequency * config.frame_length; + const size_t frame_stride_values = frequency * config.frame_stride; + const int frame_overlap_values = static_cast(frame_length_values) - static_cast(frame_stride_values); + + if (frame_overlap_values < 0) { + ei_printf("ERR: frame_length ("); + ei_printf_float(config.frame_length); + ei_printf(") cannot be lower than frame_stride ("); + ei_printf_float(config.frame_stride); + ei_printf(") for continuous classification\n"); + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + int x; + + // have current frame, but wrong size? then free + if (ei_dsp_cont_current_frame && ei_dsp_cont_current_frame_size != frame_length_values) { + ei_free(ei_dsp_cont_current_frame); + ei_dsp_cont_current_frame = nullptr; + } + + int implementation_version = config.implementation_version; + + // this is the offset in the signal from which we'll work + size_t offset_in_signal = 0; + + if (!ei_dsp_cont_current_frame) { + ei_dsp_cont_current_frame = (float*)ei_calloc(frame_length_values * sizeof(float), 1); + if (!ei_dsp_cont_current_frame) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + ei_dsp_cont_current_frame_size = frame_length_values; + ei_dsp_cont_current_frame_ix = 0; + } + + + if ((frame_length_values) > preemphasized_audio_signal.total_length + ei_dsp_cont_current_frame_ix) { + ei_printf("ERR: frame_length (%d) cannot be larger than signal's total length (%d) for continuous classification\n", + (int)frame_length_values, (int)preemphasized_audio_signal.total_length + ei_dsp_cont_current_frame_ix); + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + matrix_size_out->rows = 0; + matrix_size_out->cols = 0; + + // for continuous use v2 stack frame calculations + if (implementation_version == 1) { + implementation_version = 2; + } + + if (ei_dsp_cont_current_frame_ix > (int)ei_dsp_cont_current_frame_size) { + ei_printf("ERR: ei_dsp_cont_current_frame_ix is larger than frame size (ix=%d size=%d)\n", + ei_dsp_cont_current_frame_ix, (int)ei_dsp_cont_current_frame_size); + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + // if we still have some code from previous run + while (ei_dsp_cont_current_frame_ix > 0) { + // then from the current frame we need to read `frame_length_values - ei_dsp_cont_current_frame_ix` + // starting at offset 0 + x = preemphasized_audio_signal.get_data(0, frame_length_values - ei_dsp_cont_current_frame_ix, ei_dsp_cont_current_frame + ei_dsp_cont_current_frame_ix); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // now ei_dsp_cont_current_frame is complete + signal_t frame_signal; + x = numpy::signal_from_buffer(ei_dsp_cont_current_frame, frame_length_values, &frame_signal); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + x = extract_mfcc_run_slice(&frame_signal, output_matrix, &config, sampling_frequency, matrix_size_out, implementation_version); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // if there's overlap between frames we roll through + if (frame_stride_values > 0) { + numpy::roll(ei_dsp_cont_current_frame, frame_length_values, -frame_stride_values); + } + + ei_dsp_cont_current_frame_ix -= frame_stride_values; + } + + if (ei_dsp_cont_current_frame_ix < 0) { + offset_in_signal = -ei_dsp_cont_current_frame_ix; + ei_dsp_cont_current_frame_ix = 0; + } + + if (offset_in_signal >= signal->total_length) { + offset_in_signal -= signal->total_length; + return EIDSP_OK; + } + + // now... we need to discard part of the signal... + SignalWithRange signal_with_range(&preemphasized_audio_signal, offset_in_signal, signal->total_length); + + signal_t *range_signal = signal_with_range.get_signal(); + size_t range_signal_orig_length = range_signal->total_length; + + // then we'll just go through normal processing of the signal: + x = extract_mfcc_run_slice(range_signal, output_matrix, &config, sampling_frequency, matrix_size_out, implementation_version); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // Make sure v1 model are reset to the original length; + range_signal->total_length = range_signal_orig_length; + + // update offset + int length_of_signal_used = speechpy::processing::calculate_signal_used(range_signal->total_length, sampling_frequency, + config.frame_length, config.frame_stride, false, implementation_version); + offset_in_signal += length_of_signal_used; + + // see what's left? + int bytes_left_end_of_frame = signal->total_length - offset_in_signal; + bytes_left_end_of_frame += frame_overlap_values; + + if (bytes_left_end_of_frame > 0) { + // then read that into the ei_dsp_cont_current_frame buffer + x = preemphasized_audio_signal.get_data( + (preemphasized_audio_signal.total_length - bytes_left_end_of_frame), + bytes_left_end_of_frame, + ei_dsp_cont_current_frame); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + } + + ei_dsp_cont_current_frame_ix = bytes_left_end_of_frame; + + preemphasis = nullptr; + + return EIDSP_OK; +#endif +} + +__attribute__((unused)) int extract_spectrogram_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float sampling_frequency) { + ei_dsp_config_spectrogram_t config = *((ei_dsp_config_spectrogram_t*)config_ptr); + + if (config.axes != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (signal->total_length == 0) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + const uint32_t frequency = static_cast(sampling_frequency); + + // calculate the size of the MFE matrix + matrix_size_t out_matrix_size = + speechpy::feature::calculate_mfe_buffer_size( + signal->total_length, frequency, config.frame_length, config.frame_stride, config.fft_length / 2 + 1, + config.implementation_version); + /* Only throw size mismatch error calculated buffer doesn't fit for continuous inferencing */ + if (out_matrix_size.rows * out_matrix_size.cols > output_matrix->rows * output_matrix->cols) { + ei_printf("out_matrix = %dx%d\n", (int)output_matrix->rows, (int)output_matrix->cols); + ei_printf("calculated size = %dx%d\n", (int)out_matrix_size.rows, (int)out_matrix_size.cols); + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + output_matrix->rows = out_matrix_size.rows; + output_matrix->cols = out_matrix_size.cols; + + int ret = speechpy::feature::spectrogram(output_matrix, signal, + sampling_frequency, config.frame_length, config.frame_stride, config.fft_length, config.implementation_version); + if (ret != EIDSP_OK) { + ei_printf("ERR: Spectrogram failed (%d)\n", ret); + EIDSP_ERR(ret); + } + + if (config.implementation_version < 3) { + ret = numpy::normalize(output_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + } + else { + // normalization + ret = speechpy::processing::spectrogram_normalization(output_matrix, config.noise_floor_db, config.implementation_version == 3); + if (ret != EIDSP_OK) { + ei_printf("ERR: normalization failed (%d)\n", ret); + EIDSP_ERR(ret); + } + } + + output_matrix->cols = out_matrix_size.rows * out_matrix_size.cols; + output_matrix->rows = 1; + + return EIDSP_OK; +} + + +__attribute__((unused)) static int extract_spectrogram_run_slice(signal_t *signal, matrix_t *output_matrix, ei_dsp_config_spectrogram_t *config, const float sampling_frequency, matrix_size_t *matrix_size_out) { + uint32_t frequency = (uint32_t)sampling_frequency; + + int x; + + // calculate the size of the spectrogram matrix + matrix_size_t out_matrix_size = + speechpy::feature::calculate_mfe_buffer_size( + signal->total_length, frequency, config->frame_length, config->frame_stride, config->fft_length / 2 + 1, + config->implementation_version); + + // we roll the output matrix back so we have room at the end... + x = numpy::roll(output_matrix->buffer, output_matrix->rows * output_matrix->cols, + -(out_matrix_size.rows * out_matrix_size.cols)); + if (x != EIDSP_OK) { + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(x); + } + + // slice in the output matrix to write to + // the offset in the classification matrix here is always at the end + size_t output_matrix_offset = (output_matrix->rows * output_matrix->cols) - + (out_matrix_size.rows * out_matrix_size.cols); + + matrix_t output_matrix_slice(out_matrix_size.rows, out_matrix_size.cols, output_matrix->buffer + output_matrix_offset); + + // and run the spectrogram extraction + int ret = speechpy::feature::spectrogram(&output_matrix_slice, signal, + frequency, config->frame_length, config->frame_stride, config->fft_length, config->implementation_version); + + if (ret != EIDSP_OK) { + ei_printf("ERR: Spectrogram failed (%d)\n", ret); + EIDSP_ERR(ret); + } + + matrix_size_out->rows += out_matrix_size.rows; + if (out_matrix_size.cols > 0) { + matrix_size_out->cols = out_matrix_size.cols; + } + + return EIDSP_OK; +} + +__attribute__((unused)) int extract_spectrogram_per_slice_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float sampling_frequency, matrix_size_t *matrix_size_out) { +#if defined(__cplusplus) && EI_C_LINKAGE == 1 + ei_printf("ERR: Continuous audio is not supported when EI_C_LINKAGE is defined\n"); + EIDSP_ERR(EIDSP_NOT_SUPPORTED); +#else + + ei_dsp_config_spectrogram_t config = *((ei_dsp_config_spectrogram_t*)config_ptr); + + static bool first_run = false; + + if (config.axes != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (signal->total_length == 0) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + const uint32_t frequency = static_cast(sampling_frequency); + + /* Fake an extra frame_length for stack frames calculations. There, 1 frame_length is always + subtracted and there for never used. But skip the first slice to fit the feature_matrix + buffer */ + if(config.implementation_version < 2) { + + if (first_run == true) { + signal->total_length += (size_t)(config.frame_length * (float)frequency); + } + + first_run = true; + } + + // Go from the time (e.g. 0.25 seconds to number of frames based on freq) + const size_t frame_length_values = frequency * config.frame_length; + const size_t frame_stride_values = frequency * config.frame_stride; + const int frame_overlap_values = static_cast(frame_length_values) - static_cast(frame_stride_values); + + if (frame_overlap_values < 0) { + ei_printf("ERR: frame_length ("); + ei_printf_float(config.frame_length); + ei_printf(") cannot be lower than frame_stride ("); + ei_printf_float(config.frame_stride); + ei_printf(") for continuous classification\n"); + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + if (frame_length_values > signal->total_length) { + ei_printf("ERR: frame_length (%d) cannot be larger than signal's total length (%d) for continuous classification\n", + (int)frame_length_values, (int)signal->total_length); + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + int x; + + // have current frame, but wrong size? then free + if (ei_dsp_cont_current_frame && ei_dsp_cont_current_frame_size != frame_length_values) { + ei_free(ei_dsp_cont_current_frame); + ei_dsp_cont_current_frame = nullptr; + } + + if (!ei_dsp_cont_current_frame) { + ei_dsp_cont_current_frame = (float*)ei_calloc(frame_length_values * sizeof(float), 1); + if (!ei_dsp_cont_current_frame) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + ei_dsp_cont_current_frame_size = frame_length_values; + ei_dsp_cont_current_frame_ix = 0; + } + + matrix_size_out->rows = 0; + matrix_size_out->cols = 0; + + // this is the offset in the signal from which we'll work + size_t offset_in_signal = 0; + + if (ei_dsp_cont_current_frame_ix > (int)ei_dsp_cont_current_frame_size) { + ei_printf("ERR: ei_dsp_cont_current_frame_ix is larger than frame size\n"); + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + // if we still have some code from previous run + while (ei_dsp_cont_current_frame_ix > 0) { + // then from the current frame we need to read `frame_length_values - ei_dsp_cont_current_frame_ix` + // starting at offset 0 + x = signal->get_data(0, frame_length_values - ei_dsp_cont_current_frame_ix, ei_dsp_cont_current_frame + ei_dsp_cont_current_frame_ix); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // now ei_dsp_cont_current_frame is complete + signal_t frame_signal; + x = numpy::signal_from_buffer(ei_dsp_cont_current_frame, frame_length_values, &frame_signal); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + x = extract_spectrogram_run_slice(&frame_signal, output_matrix, &config, sampling_frequency, matrix_size_out); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // if there's overlap between frames we roll through + if (frame_stride_values > 0) { + numpy::roll(ei_dsp_cont_current_frame, frame_length_values, -frame_stride_values); + } + + ei_dsp_cont_current_frame_ix -= frame_stride_values; + } + + if (ei_dsp_cont_current_frame_ix < 0) { + offset_in_signal = -ei_dsp_cont_current_frame_ix; + ei_dsp_cont_current_frame_ix = 0; + } + + if (offset_in_signal >= signal->total_length) { + offset_in_signal -= signal->total_length; + return EIDSP_OK; + } + + // now... we need to discard part of the signal... + SignalWithRange signal_with_range(signal, offset_in_signal, signal->total_length); + + signal_t *range_signal = signal_with_range.get_signal(); + size_t range_signal_orig_length = range_signal->total_length; + + // then we'll just go through normal processing of the signal: + x = extract_spectrogram_run_slice(range_signal, output_matrix, &config, sampling_frequency, matrix_size_out); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // update offset + int length_of_signal_used = speechpy::processing::calculate_signal_used(range_signal->total_length, sampling_frequency, + config.frame_length, config.frame_stride, false, config.implementation_version); + offset_in_signal += length_of_signal_used; + + // not sure why this is being manipulated... + range_signal->total_length = range_signal_orig_length; + + // see what's left? + int bytes_left_end_of_frame = signal->total_length - offset_in_signal; + bytes_left_end_of_frame += frame_overlap_values; + + if (bytes_left_end_of_frame > 0) { + // then read that into the ei_dsp_cont_current_frame buffer + x = signal->get_data( + (signal->total_length - bytes_left_end_of_frame), + bytes_left_end_of_frame, + ei_dsp_cont_current_frame); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + } + + ei_dsp_cont_current_frame_ix = bytes_left_end_of_frame; + + if (config.implementation_version < 2) { + if (first_run == true) { + signal->total_length -= (size_t)(config.frame_length * (float)frequency); + } + } + + return EIDSP_OK; +#endif +} + + +__attribute__((unused)) int extract_mfe_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float sampling_frequency) { + ei_dsp_config_mfe_t config = *((ei_dsp_config_mfe_t*)config_ptr); + + if (config.axes != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (signal->total_length == 0) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + if ((config.implementation_version == 0) || (config.implementation_version > 4)) { + EIDSP_ERR(EIDSP_BLOCK_VERSION_INCORRECT); + } + + const uint32_t frequency = static_cast(sampling_frequency); + + signal_t preemphasized_audio_signal; + + // before version 3 we did not have preemphasis + if (config.implementation_version < 3) { + preemphasis = nullptr; + + preemphasized_audio_signal.total_length = signal->total_length; + preemphasized_audio_signal.get_data = signal->get_data; + } + else { + // preemphasis class to preprocess the audio... + class speechpy::processing::preemphasis *pre = new class speechpy::processing::preemphasis(signal, 1, 0.98f, true); + preemphasis = pre; + + preemphasized_audio_signal.total_length = signal->total_length; + preemphasized_audio_signal.get_data = &preemphasized_audio_signal_get_data; + } + + // calculate the size of the MFE matrix + matrix_size_t out_matrix_size = + speechpy::feature::calculate_mfe_buffer_size( + preemphasized_audio_signal.total_length, frequency, config.frame_length, config.frame_stride, config.num_filters, + config.implementation_version); + /* Only throw size mismatch error calculated buffer doesn't fit for continuous inferencing */ + if (out_matrix_size.rows * out_matrix_size.cols > output_matrix->rows * output_matrix->cols) { + ei_printf("out_matrix = %dx%d\n", (int)output_matrix->rows, (int)output_matrix->cols); + ei_printf("calculated size = %dx%d\n", (int)out_matrix_size.rows, (int)out_matrix_size.cols); + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + output_matrix->rows = out_matrix_size.rows; + output_matrix->cols = out_matrix_size.cols; + + int ret; + // This probably seems incorrect, but the mfe func can actually handle all versions + // There's a subtle issue with cmvn and v2, not worth tracking down + // So for v2 and v1, we'll just use the old code + // (the new mfe does away with the intermediate filterbank matrix) + if (config.implementation_version > 2) { + ret = speechpy::feature::mfe(output_matrix, nullptr, &preemphasized_audio_signal, + frequency, config.frame_length, config.frame_stride, config.num_filters, config.fft_length, + config.low_frequency, config.high_frequency, config.implementation_version); + } else { + ret = speechpy::feature::mfe_v3(output_matrix, nullptr, &preemphasized_audio_signal, + frequency, config.frame_length, config.frame_stride, config.num_filters, config.fft_length, + config.low_frequency, config.high_frequency, config.implementation_version); + } + + if (preemphasis) { + delete preemphasis; + } + if (ret != EIDSP_OK) { + ei_printf("ERR: MFE failed (%d)\n", ret); + EIDSP_ERR(ret); + } + + if (config.implementation_version < 3) { + // cepstral mean and variance normalization + ret = speechpy::processing::cmvnw(output_matrix, config.win_size, false, true); + if (ret != EIDSP_OK) { + ei_printf("ERR: cmvnw failed (%d)\n", ret); + EIDSP_ERR(ret); + } + } + else { + // normalization + ret = speechpy::processing::mfe_normalization(output_matrix, config.noise_floor_db); + if (ret != EIDSP_OK) { + ei_printf("ERR: normalization failed (%d)\n", ret); + EIDSP_ERR(ret); + } + } + + output_matrix->cols = out_matrix_size.rows * out_matrix_size.cols; + output_matrix->rows = 1; + + return EIDSP_OK; +} + +__attribute__((unused)) static int extract_mfe_run_slice(signal_t *signal, matrix_t *output_matrix, ei_dsp_config_mfe_t *config, const float sampling_frequency, matrix_size_t *matrix_size_out) { + uint32_t frequency = (uint32_t)sampling_frequency; + + int x; + + // calculate the size of the spectrogram matrix + matrix_size_t out_matrix_size = + speechpy::feature::calculate_mfe_buffer_size( + signal->total_length, frequency, config->frame_length, config->frame_stride, config->num_filters, + config->implementation_version); + + // we roll the output matrix back so we have room at the end... + x = numpy::roll(output_matrix->buffer, output_matrix->rows * output_matrix->cols, + -(out_matrix_size.rows * out_matrix_size.cols)); + if (x != EIDSP_OK) { + EIDSP_ERR(x); + } + + // slice in the output matrix to write to + // the offset in the classification matrix here is always at the end + size_t output_matrix_offset = (output_matrix->rows * output_matrix->cols) - + (out_matrix_size.rows * out_matrix_size.cols); + + matrix_t output_matrix_slice(out_matrix_size.rows, out_matrix_size.cols, output_matrix->buffer + output_matrix_offset); + + // and run the MFE extraction + // This probably seems incorrect, but the mfe func can actually handle all versions + // There's a subtle issue with cmvn and v2, not worth tracking down + // So for v2 and v1, we'll just use the old code + // (the new mfe does away with the intermediate filterbank matrix) + if (config->implementation_version > 2) { + x = speechpy::feature::mfe(&output_matrix_slice, nullptr, signal, + frequency, config->frame_length, config->frame_stride, config->num_filters, config->fft_length, + config->low_frequency, config->high_frequency, config->implementation_version); + } else { + x = speechpy::feature::mfe_v3(&output_matrix_slice, nullptr, signal, + frequency, config->frame_length, config->frame_stride, config->num_filters, config->fft_length, + config->low_frequency, config->high_frequency, config->implementation_version); + } + if (x != EIDSP_OK) { + ei_printf("ERR: MFE failed (%d)\n", x); + EIDSP_ERR(x); + } + + matrix_size_out->rows += out_matrix_size.rows; + if (out_matrix_size.cols > 0) { + matrix_size_out->cols = out_matrix_size.cols; + } + + return EIDSP_OK; +} + +__attribute__((unused)) int extract_mfe_per_slice_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float sampling_frequency, matrix_size_t *matrix_size_out) { +#if defined(__cplusplus) && EI_C_LINKAGE == 1 + ei_printf("ERR: Continuous audio is not supported when EI_C_LINKAGE is defined\n"); + EIDSP_ERR(EIDSP_NOT_SUPPORTED); +#else + + ei_dsp_config_mfe_t config = *((ei_dsp_config_mfe_t*)config_ptr); + + // signal is already the right size, + // output matrix is not the right size, but we can start writing at offset 0 and then it's OK too + + static bool first_run = false; + + if (config.axes != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if ((config.implementation_version == 0) || (config.implementation_version > 4)) { + EIDSP_ERR(EIDSP_BLOCK_VERSION_INCORRECT); + } + + if (signal->total_length == 0) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + const uint32_t frequency = static_cast(sampling_frequency); + + // Fake an extra frame_length for stack frames calculations. There, 1 frame_length is always + // subtracted and there for never used. But skip the first slice to fit the feature_matrix + // buffer + if (config.implementation_version == 1) { + if (first_run == true) { + signal->total_length += (size_t)(config.frame_length * (float)frequency); + } + + first_run = true; + } + + // ok all setup, let's construct the signal (with preemphasis for impl version >3) + signal_t preemphasized_audio_signal; + + // before version 3 we did not have preemphasis + if (config.implementation_version < 3) { + preemphasis = nullptr; + preemphasized_audio_signal.total_length = signal->total_length; + preemphasized_audio_signal.get_data = signal->get_data; + } + else { + // preemphasis class to preprocess the audio... + class speechpy::processing::preemphasis *pre = new class speechpy::processing::preemphasis(signal, 1, 0.98f, true); + preemphasis = pre; + preemphasized_audio_signal.total_length = signal->total_length; + preemphasized_audio_signal.get_data = &preemphasized_audio_signal_get_data; + } + + // Go from the time (e.g. 0.25 seconds to number of frames based on freq) + const size_t frame_length_values = frequency * config.frame_length; + const size_t frame_stride_values = frequency * config.frame_stride; + const int frame_overlap_values = static_cast(frame_length_values) - static_cast(frame_stride_values); + + if (frame_overlap_values < 0) { + ei_printf("ERR: frame_length ("); + ei_printf_float(config.frame_length); + ei_printf(") cannot be lower than frame_stride ("); + ei_printf_float(config.frame_stride); + ei_printf(") for continuous classification\n"); + + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + if (frame_length_values > preemphasized_audio_signal.total_length) { + ei_printf("ERR: frame_length (%d) cannot be larger than signal's total length (%d) for continuous classification\n", + (int)frame_length_values, (int)preemphasized_audio_signal.total_length); + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + int x; + + // have current frame, but wrong size? then free + if (ei_dsp_cont_current_frame && ei_dsp_cont_current_frame_size != frame_length_values) { + ei_free(ei_dsp_cont_current_frame); + ei_dsp_cont_current_frame = nullptr; + } + + if (!ei_dsp_cont_current_frame) { + ei_dsp_cont_current_frame = (float*)ei_calloc(frame_length_values * sizeof(float), 1); + if (!ei_dsp_cont_current_frame) { + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + ei_dsp_cont_current_frame_size = frame_length_values; + ei_dsp_cont_current_frame_ix = 0; + } + + matrix_size_out->rows = 0; + matrix_size_out->cols = 0; + + // this is the offset in the signal from which we'll work + size_t offset_in_signal = 0; + + if (ei_dsp_cont_current_frame_ix > (int)ei_dsp_cont_current_frame_size) { + ei_printf("ERR: ei_dsp_cont_current_frame_ix is larger than frame size\n"); + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + // if we still have some code from previous run + while (ei_dsp_cont_current_frame_ix > 0) { + // then from the current frame we need to read `frame_length_values - ei_dsp_cont_current_frame_ix` + // starting at offset 0 + x = preemphasized_audio_signal.get_data(0, frame_length_values - ei_dsp_cont_current_frame_ix, ei_dsp_cont_current_frame + ei_dsp_cont_current_frame_ix); + if (x != EIDSP_OK) { + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(x); + } + + // now ei_dsp_cont_current_frame is complete + signal_t frame_signal; + x = numpy::signal_from_buffer(ei_dsp_cont_current_frame, frame_length_values, &frame_signal); + if (x != EIDSP_OK) { + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(x); + } + + x = extract_mfe_run_slice(&frame_signal, output_matrix, &config, sampling_frequency, matrix_size_out); + if (x != EIDSP_OK) { + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(x); + } + + // if there's overlap between frames we roll through + if (frame_stride_values > 0) { + numpy::roll(ei_dsp_cont_current_frame, frame_length_values, -frame_stride_values); + } + + ei_dsp_cont_current_frame_ix -= frame_stride_values; + } + + if (ei_dsp_cont_current_frame_ix < 0) { + offset_in_signal = -ei_dsp_cont_current_frame_ix; + ei_dsp_cont_current_frame_ix = 0; + } + + if (offset_in_signal >= signal->total_length) { + if (preemphasis) { + delete preemphasis; + } + offset_in_signal -= signal->total_length; + return EIDSP_OK; + } + + // now... we need to discard part of the signal... + SignalWithRange signal_with_range(&preemphasized_audio_signal, offset_in_signal, signal->total_length); + + signal_t *range_signal = signal_with_range.get_signal(); + size_t range_signal_orig_length = range_signal->total_length; + + // then we'll just go through normal processing of the signal: + x = extract_mfe_run_slice(range_signal, output_matrix, &config, sampling_frequency, matrix_size_out); + if (x != EIDSP_OK) { + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(x); + } + + // update offset + int length_of_signal_used = speechpy::processing::calculate_signal_used(range_signal->total_length, sampling_frequency, + config.frame_length, config.frame_stride, false, config.implementation_version); + offset_in_signal += length_of_signal_used; + + // not sure why this is being manipulated... + range_signal->total_length = range_signal_orig_length; + + // see what's left? + int bytes_left_end_of_frame = signal->total_length - offset_in_signal; + bytes_left_end_of_frame += frame_overlap_values; + + if (bytes_left_end_of_frame > 0) { + // then read that into the ei_dsp_cont_current_frame buffer + x = preemphasized_audio_signal.get_data( + (preemphasized_audio_signal.total_length - bytes_left_end_of_frame), + bytes_left_end_of_frame, + ei_dsp_cont_current_frame); + if (x != EIDSP_OK) { + if (preemphasis) { + delete preemphasis; + } + EIDSP_ERR(x); + } + } + + ei_dsp_cont_current_frame_ix = bytes_left_end_of_frame; + + + if (config.implementation_version == 1) { + if (first_run == true) { + signal->total_length -= (size_t)(config.frame_length * (float)frequency); + } + } + + if (preemphasis) { + delete preemphasis; + } + + return EIDSP_OK; +#endif +} + +__attribute__((unused)) int extract_image_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float frequency) { + ei_dsp_config_image_t config = *((ei_dsp_config_image_t*)config_ptr); + + int16_t channel_count = strcmp(config.channels, "Grayscale") == 0 ? 1 : 3; + + size_t output_ix = 0; + +#if defined(EI_DSP_IMAGE_BUFFER_STATIC_SIZE) + const size_t page_size = EI_DSP_IMAGE_BUFFER_STATIC_SIZE; +#else + const size_t page_size = 1024; +#endif + + // buffered read from the signal + size_t bytes_left = signal->total_length; + for (size_t ix = 0; ix < signal->total_length; ix += page_size) { + size_t elements_to_read = bytes_left > page_size ? page_size : bytes_left; + +#if defined(EI_DSP_IMAGE_BUFFER_STATIC_SIZE) + matrix_t input_matrix(elements_to_read, config.axes, ei_dsp_image_buffer); +#else + matrix_t input_matrix(elements_to_read, config.axes); +#endif + if (!input_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + signal->get_data(ix, elements_to_read, input_matrix.buffer); + + for (size_t jx = 0; jx < elements_to_read; jx++) { + uint32_t pixel = static_cast(input_matrix.buffer[jx]); + + // rgb to 0..1 + float r = static_cast(pixel >> 16 & 0xff) / 255.0f; + float g = static_cast(pixel >> 8 & 0xff) / 255.0f; + float b = static_cast(pixel & 0xff) / 255.0f; + + if (channel_count == 3) { + output_matrix->buffer[output_ix++] = r; + output_matrix->buffer[output_ix++] = g; + output_matrix->buffer[output_ix++] = b; + } + else { + // ITU-R 601-2 luma transform + // see: https://pillow.readthedocs.io/en/stable/reference/Image.html#PIL.Image.Image.convert + float v = (0.299f * r) + (0.587f * g) + (0.114f * b); + output_matrix->buffer[output_ix++] = v; + } + } + + bytes_left -= elements_to_read; + } + + return EIDSP_OK; +} + +#if (EI_CLASSIFIER_QUANTIZATION_ENABLED == 1) && (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI) + +__attribute__((unused)) int extract_drpai_features_quantized(signal_t *signal, matrix_u8_t *output_matrix, void *config_ptr, const float frequency) { + ei_dsp_config_image_t config = *((ei_dsp_config_image_t*)config_ptr); + + int16_t channel_count = strcmp(config.channels, "Grayscale") == 0 ? 1 : 3; + + size_t output_ix = 0; + +#if defined(EI_DSP_IMAGE_BUFFER_STATIC_SIZE) + const size_t page_size = EI_DSP_IMAGE_BUFFER_STATIC_SIZE; +#else + const size_t page_size = 1024; +#endif + + // buffered read from the signal + size_t bytes_left = signal->total_length; + for (size_t ix = 0; ix < signal->total_length; ix += page_size) { + size_t elements_to_read = bytes_left > page_size ? page_size : bytes_left; + +#if defined(EI_DSP_IMAGE_BUFFER_STATIC_SIZE) + matrix_t input_matrix(elements_to_read, config.axes, ei_dsp_image_buffer); +#else + matrix_t input_matrix(elements_to_read, config.axes); +#endif + if (!input_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + signal->get_data(ix, elements_to_read, input_matrix.buffer); + + for (size_t jx = 0; jx < elements_to_read; jx++) { + uint32_t pixel = static_cast(input_matrix.buffer[jx]); + + if (channel_count == 3) { + uint8_t r = static_cast(pixel >> 16 & 0xff); + uint8_t g = static_cast(pixel >> 8 & 0xff); + uint8_t b = static_cast(pixel & 0xff); + + output_matrix->buffer[output_ix++] = r; + output_matrix->buffer[output_ix++] = g; + output_matrix->buffer[output_ix++] = b; + } + else { + //NOTE: not implementing greyscale yet + } + } + bytes_left -= elements_to_read; + } + + return EIDSP_OK; +} + +#endif //(EI_CLASSIFIER_QUANTIZATION_ENABLED == 1) && (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI) + +#if (EI_CLASSIFIER_QUANTIZATION_ENABLED == 1) && (EI_CLASSIFIER_INFERENCING_ENGINE != EI_CLASSIFIER_DRPAI) + +__attribute__((unused)) int extract_image_features_quantized(signal_t *signal, matrix_i8_t *output_matrix, void *config_ptr, float scale, float zero_point, const float frequency, + int image_scaling) { + ei_dsp_config_image_t config = *((ei_dsp_config_image_t*)config_ptr); + + int16_t channel_count = strcmp(config.channels, "Grayscale") == 0 ? 1 : 3; + + size_t output_ix = 0; + + const int32_t iRedToGray = (int32_t)(0.299f * 65536.0f); + const int32_t iGreenToGray = (int32_t)(0.587f * 65536.0f); + const int32_t iBlueToGray = (int32_t)(0.114f * 65536.0f); + + static const float torch_mean[] = { 0.485, 0.456, 0.406 }; + static const float torch_std[] = { 0.229, 0.224, 0.225 }; + +#if defined(EI_DSP_IMAGE_BUFFER_STATIC_SIZE) + const size_t page_size = EI_DSP_IMAGE_BUFFER_STATIC_SIZE; +#else + const size_t page_size = 1024; +#endif + + // buffered read from the signal + size_t bytes_left = signal->total_length; + for (size_t ix = 0; ix < signal->total_length; ix += page_size) { + size_t elements_to_read = bytes_left > page_size ? page_size : bytes_left; + +#if defined(EI_DSP_IMAGE_BUFFER_STATIC_SIZE) + matrix_t input_matrix(elements_to_read, config.axes, ei_dsp_image_buffer); +#else + matrix_t input_matrix(elements_to_read, config.axes); +#endif + if (!input_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + signal->get_data(ix, elements_to_read, input_matrix.buffer); + + for (size_t jx = 0; jx < elements_to_read; jx++) { + uint32_t pixel = static_cast(input_matrix.buffer[jx]); + + if (channel_count == 3) { + // fast code path + if (scale == 0.003921568859368563f && zero_point == -128 && image_scaling == EI_CLASSIFIER_IMAGE_SCALING_NONE) { + int32_t r = static_cast(pixel >> 16 & 0xff); + int32_t g = static_cast(pixel >> 8 & 0xff); + int32_t b = static_cast(pixel & 0xff); + + output_matrix->buffer[output_ix++] = static_cast(r + zero_point); + output_matrix->buffer[output_ix++] = static_cast(g + zero_point); + output_matrix->buffer[output_ix++] = static_cast(b + zero_point); + } + // slow code path + else { + float r = static_cast(pixel >> 16 & 0xff); + float g = static_cast(pixel >> 8 & 0xff); + float b = static_cast(pixel & 0xff); + + if (image_scaling == EI_CLASSIFIER_IMAGE_SCALING_NONE) { + r /= 255.0f; + g /= 255.0f; + b /= 255.0f; + } + else if (image_scaling == EI_CLASSIFIER_IMAGE_SCALING_TORCH) { + r /= 255.0f; + g /= 255.0f; + b /= 255.0f; + + r = (r - torch_mean[0]) / torch_std[0]; + g = (g - torch_mean[1]) / torch_std[1]; + b = (b - torch_mean[2]) / torch_std[2]; + } + else if (image_scaling == EI_CLASSIFIER_IMAGE_SCALING_MIN128_127) { + r -= 128.0f; + g -= 128.0f; + b -= 128.0f; + } + + output_matrix->buffer[output_ix++] = static_cast(round(r / scale) + zero_point); + output_matrix->buffer[output_ix++] = static_cast(round(g / scale) + zero_point); + output_matrix->buffer[output_ix++] = static_cast(round(b / scale) + zero_point); + } + } + else { + // fast code path + if (scale == 0.003921568859368563f && zero_point == -128 && image_scaling == EI_CLASSIFIER_IMAGE_SCALING_NONE) { + int32_t r = static_cast(pixel >> 16 & 0xff); + int32_t g = static_cast(pixel >> 8 & 0xff); + int32_t b = static_cast(pixel & 0xff); + + // ITU-R 601-2 luma transform + // see: https://pillow.readthedocs.io/en/stable/reference/Image.html#PIL.Image.Image.convert + int32_t gray = (iRedToGray * r) + (iGreenToGray * g) + (iBlueToGray * b); + gray >>= 16; // scale down to int8_t + gray += zero_point; + if (gray < - 128) gray = -128; + else if (gray > 127) gray = 127; + output_matrix->buffer[output_ix++] = static_cast(gray); + } + // slow code path + else { + float r = static_cast(pixel >> 16 & 0xff); + float g = static_cast(pixel >> 8 & 0xff); + float b = static_cast(pixel & 0xff); + + if (image_scaling == EI_CLASSIFIER_IMAGE_SCALING_NONE) { + r /= 255.0f; + g /= 255.0f; + b /= 255.0f; + } + else if (image_scaling == EI_CLASSIFIER_IMAGE_SCALING_TORCH) { + r /= 255.0f; + g /= 255.0f; + b /= 255.0f; + + r = (r - torch_mean[0]) / torch_std[0]; + g = (g - torch_mean[1]) / torch_std[1]; + b = (b - torch_mean[2]) / torch_std[2]; + } + else if (image_scaling == EI_CLASSIFIER_IMAGE_SCALING_MIN128_127) { + r -= 128.0f; + g -= 128.0f; + b -= 128.0f; + } + + // ITU-R 601-2 luma transform + // see: https://pillow.readthedocs.io/en/stable/reference/Image.html#PIL.Image.Image.convert + float v = (0.299f * r) + (0.587f * g) + (0.114f * b); + output_matrix->buffer[output_ix++] = static_cast(round(v / scale) + zero_point); + } + } + } + + bytes_left -= elements_to_read; + + } + return EIDSP_OK; +} +#endif // (EI_CLASSIFIER_QUANTIZATION_ENABLED == 1) && (EI_CLASSIFIER_INFERENCING_ENGINE != EI_CLASSIFIER_DRPAI) + +/** + * Clear all state regarding continuous audio. Invoke this function after continuous audio loop ends. + */ +__attribute__((unused)) int ei_dsp_clear_continuous_audio_state() { + if (ei_dsp_cont_current_frame) { + ei_free(ei_dsp_cont_current_frame); + } + + ei_dsp_cont_current_frame = nullptr; + ei_dsp_cont_current_frame_size = 0; + ei_dsp_cont_current_frame_ix = 0; + + return EIDSP_OK; +} + +/** + * @brief Calculates the cepstral mean and variable normalization. + * + * @param matrix Source and destination matrix + * @param config_ptr ei_dsp_config_mfcc_t struct pointer + */ +__attribute__((unused)) void calc_cepstral_mean_and_var_normalization_mfcc(ei_matrix *matrix, void *config_ptr) +{ + ei_dsp_config_mfcc_t *config = (ei_dsp_config_mfcc_t *)config_ptr; + + uint32_t original_matrix_size = matrix->rows * matrix->cols; + + /* Modify rows and colums ration for matrix normalization */ + matrix->rows = original_matrix_size / config->num_cepstral; + matrix->cols = config->num_cepstral; + + // cepstral mean and variance normalization + int ret = speechpy::processing::cmvnw(matrix, config->win_size, true, false); + if (ret != EIDSP_OK) { + ei_printf("ERR: cmvnw failed (%d)\n", ret); + return; + } + + /* Reset rows and columns ratio */ + matrix->rows = 1; + matrix->cols = original_matrix_size; +} + +/** + * @brief Calculates the cepstral mean and variable normalization. + * + * @param matrix Source and destination matrix + * @param config_ptr ei_dsp_config_mfe_t struct pointer + */ +__attribute__((unused)) void calc_cepstral_mean_and_var_normalization_mfe(ei_matrix *matrix, void *config_ptr) +{ + ei_dsp_config_mfe_t *config = (ei_dsp_config_mfe_t *)config_ptr; + + uint32_t original_matrix_size = matrix->rows * matrix->cols; + + /* Modify rows and colums ration for matrix normalization */ + matrix->rows = (original_matrix_size) / config->num_filters; + matrix->cols = config->num_filters; + + if (config->implementation_version < 3) { + // cepstral mean and variance normalization + int ret = speechpy::processing::cmvnw(matrix, config->win_size, false, true); + if (ret != EIDSP_OK) { + ei_printf("ERR: cmvnw failed (%d)\n", ret); + return; + } + } + else { + // normalization + int ret = speechpy::processing::mfe_normalization(matrix, config->noise_floor_db); + if (ret != EIDSP_OK) { + ei_printf("ERR: normalization failed (%d)\n", ret); + return; + } + } + + /* Reset rows and columns ratio */ + matrix->rows = 1; + matrix->cols = (original_matrix_size); +} + +/** + * @brief Calculates the cepstral mean and variable normalization. + * + * @param matrix Source and destination matrix + * @param config_ptr ei_dsp_config_spectrogram_t struct pointer + */ +__attribute__((unused)) void calc_cepstral_mean_and_var_normalization_spectrogram(ei_matrix *matrix, void *config_ptr) +{ + ei_dsp_config_spectrogram_t *config = (ei_dsp_config_spectrogram_t *)config_ptr; + + uint32_t original_matrix_size = matrix->rows * matrix->cols; + + /* Modify rows and colums ration for matrix normalization */ + matrix->cols = config->fft_length / 2 + 1; + matrix->rows = (original_matrix_size) / matrix->cols; + + if (config->implementation_version < 3) { + int ret = numpy::normalize(matrix); + if (ret != EIDSP_OK) { + ei_printf("ERR: normalization failed (%d)\n", ret); + return; + } + } + else { + // normalization + int ret = speechpy::processing::spectrogram_normalization(matrix, config->noise_floor_db, config->implementation_version == 3); + if (ret != EIDSP_OK) { + ei_printf("ERR: normalization failed (%d)\n", ret); + return; + } + } + + /* Reset rows and columns ratio */ + matrix->rows = 1; + matrix->cols = (original_matrix_size); +} + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // _EDGE_IMPULSE_RUN_DSP_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_signal_with_axes.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_signal_with_axes.h new file mode 100644 index 0000000..ccf4291 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_signal_with_axes.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_SIGNAL_WITH_AXES_H_ +#define _EI_CLASSIFIER_SIGNAL_WITH_AXES_H_ + +#include "edge-impulse-sdk/dsp/numpy_types.h" +#include "edge-impulse-sdk/dsp/returntypes.hpp" +#include "edge-impulse-sdk/classifier/ei_model_types.h" + +#if !EIDSP_SIGNAL_C_FN_POINTER + +using namespace ei; + +class SignalWithAxes { +public: + SignalWithAxes(signal_t *original_signal, uint8_t *axes, size_t axes_count, const ei_impulse_t *impulse): + _original_signal(original_signal), _axes(axes), _axes_count(axes_count), _impulse(impulse) + { + + } + + signal_t * get_signal() { + if (this->_axes_count == _impulse->raw_samples_per_frame) { + return this->_original_signal; + } + + wrapped_signal.total_length = _original_signal->total_length / _impulse->raw_samples_per_frame * _axes_count; +#ifdef __MBED__ + wrapped_signal.get_data = mbed::callback(this, &SignalWithAxes::get_data); +#else + wrapped_signal.get_data = [this](size_t offset, size_t length, float *out_ptr) { + return this->get_data(offset, length, out_ptr); + }; +#endif + return &wrapped_signal; + } + + int get_data(size_t offset, size_t length, float *out_ptr) { + size_t offset_on_original_signal = offset / _axes_count * _impulse->raw_samples_per_frame; + size_t length_on_original_signal = length / _axes_count * _impulse->raw_samples_per_frame; + + size_t out_ptr_ix = 0; + + for (size_t ix = offset_on_original_signal; ix < offset_on_original_signal + length_on_original_signal; ix += _impulse->raw_samples_per_frame) { + for (size_t axis_ix = 0; axis_ix < this->_axes_count; axis_ix++) { + int r = _original_signal->get_data(ix + _axes[axis_ix], 1, &out_ptr[out_ptr_ix++]); + if (r != 0) { + return r; + } + } + } + + return 0; + } + +private: + signal_t *_original_signal; + uint8_t *_axes; + size_t _axes_count; + const ei_impulse_t *_impulse; + signal_t wrapped_signal; +}; + +#endif // #if !EIDSP_SIGNAL_C_FN_POINTER + +#endif // _EI_CLASSIFIER_SIGNAL_WITH_AXES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_signal_with_range.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_signal_with_range.h new file mode 100644 index 0000000..7571c7e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/ei_signal_with_range.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_SIGNAL_WITH_RANGE_H_ +#define _EI_CLASSIFIER_SIGNAL_WITH_RANGE_H_ + +#include "edge-impulse-sdk/dsp/numpy_types.h" +#include "edge-impulse-sdk/dsp/returntypes.hpp" + +#if !EIDSP_SIGNAL_C_FN_POINTER + +using namespace ei; + +class SignalWithRange { +public: + SignalWithRange(signal_t *original_signal, uint32_t range_start, uint32_t range_end): + _original_signal(original_signal), _range_start(range_start), _range_end(range_end) + { + + } + + signal_t * get_signal() { + if (this->_range_start == 0 && this->_range_end == this->_original_signal->total_length) { + return this->_original_signal; + } + + wrapped_signal.total_length = _range_end - _range_start; +#ifdef __MBED__ + wrapped_signal.get_data = mbed::callback(this, &SignalWithRange::get_data); +#else + wrapped_signal.get_data = [this](size_t offset, size_t length, float *out_ptr) { + return this->get_data(offset, length, out_ptr); + }; +#endif + return &wrapped_signal; + } + + int get_data(size_t offset, size_t length, float *out_ptr) { + return _original_signal->get_data(offset + _range_start, length, out_ptr); + } + +private: + signal_t *_original_signal; + uint32_t _range_start; + uint32_t _range_end; + signal_t wrapped_signal; +}; + +#endif // #if !EIDSP_SIGNAL_C_FN_POINTER + +#endif // _EI_CLASSIFIER_SIGNAL_WITH_RANGE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/akida.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/akida.h new file mode 100644 index 0000000..08f4fc8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/akida.h @@ -0,0 +1,578 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef EI_CLASSIFIER_INFERENCING_ENGINE_AKIDA_H +#define EI_CLASSIFIER_INFERENCING_ENGINE_AKIDA_H + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_AKIDA) + +/** + * @brief if we are not forcing SOFTWARE inference (simulation) + * then make sure we will try to use hardware + * + */ +#ifndef EI_CLASSIFIER_USE_AKIDA_SOFTWARE +#define EI_CLASSIFIER_USE_AKIDA_HARDWARE 1 +#endif + +/** + * @brief If more than one device is present in system + * setting this to device index can select a proper device. + * e.g.: set to 1 to selct /dev/akida1 + * + */ +#ifndef EI_CLASSIFIER_USE_AKIDA_HARDWARE_NO +#define EI_CLASSIFIER_USE_AKIDA_HARDWARE_NO 0 +#endif + +#include "model-parameters/model_metadata.h" +#include +#include "tensorflow-lite/tensorflow/lite/c/common.h" +#include "tensorflow-lite/tensorflow/lite/interpreter.h" +#include "tensorflow-lite/tensorflow/lite/kernels/register.h" +#include "tensorflow-lite/tensorflow/lite/model.h" +#include "tensorflow-lite/tensorflow/lite/optional_debug_tools.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.h" +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "tensorflow-lite/tensorflow/lite/kernels/internal/reference/softmax.h" +#undef EI_CLASSIFIER_INFERENCING_ENGINE +#define EI_CLASSIFIER_INFERENCING_ENGINE EI_CLASSIFIER_TFLITE_FULL +#include "tflite_helper.h" +#undef EI_CLASSIFIER_INFERENCING_ENGINE +#define EI_CLASSIFIER_INFERENCING_ENGINE EI_CLASSIFIER_AKIDA +#include +#include +#include +#include +#include +#include +#include +#include "pybind11/embed.h" +#include "pybind11/numpy.h" +#include "pybind11/stl.h" + +namespace py = pybind11; + +std::stringstream engine_info; + +static py::module_ akida; +static py::object model; +static py::object model_predict; +static py::object model_forward; +static py::object device; +static bool akida_initialized = false; +static std::vector input_shape; +static tflite::RuntimeShape softmax_shape; +static tflite::SoftmaxParams dummy_params; +static int model_input_bits = 0; +static float scale; +static int down_scale; +typedef struct { + std::unique_ptr model; + std::unique_ptr interpreter; +} ei_tflite_state_t; + +std::map ei_tflite_instances; + +bool init_akida(const uint8_t *model_arr, size_t model_arr_size, bool debug) +{ + py::module_ sys; + py::list path; + constexpr char model_file_path[] = "/tmp/akida_model.fbz"; + + if(debug) { + try { + sys = py::module_::import("sys"); + path = sys.attr("path"); + ei_printf("DEBUG: sys.path:"); + for (py::handle p: path) { + ei_printf("\t%s\n", p.cast().c_str()); + } + } + catch (py::error_already_set &e) { + ei_printf("ERR: Importing 'sys' library failed:\n%s\n", e.what()); + // as it is only for debug purposes, continue + } + } + + try { + // import Python's akida module + akida = py::module_::import("akida"); + } + catch (py::error_already_set &e) { + ei_printf("ERR: Importing 'akida' library failed:\n%s\n", e.what()); + return false; + } + + if(debug) { + std::string ver = akida.attr("__version__").cast(); + ei_printf("DEBUG: Akida version: %s\n", ver.c_str()); + } + + py::object Model = akida.attr("Model"); + + // deploy akida model file into temporary file + std::ofstream model_file(model_file_path, std::ios::out | std::ios::binary); + model_file.write(reinterpret_cast(model_arr), model_arr_size); + if(model_file.bad()) { + ei_printf("ERR: failed to unpack model ile into %s\n", model_file_path); + model_file.close(); + return false; + } + model_file.close(); + + // load model + try { + model = Model(model_file_path); + } + catch (py::error_already_set &e) { + ei_printf("ERR: Can't load model file from %s\n", model_file_path); + ei_printf("ERR: %s\n", e.what()); + return false; + } + + // get input shape from model + input_shape = model.attr("input_shape").cast>(); + //TODO: temporarily only 3D input data is supported (see note in run_nn_inference) + if(input_shape.size() != 3) { + ei_printf("ERR: Unsupported input data shape. Expected 3 dimensions got %d\n", (int)input_shape.size()); + return false; + } + // extend input by (N, ...) - hardcoded to (1, ...) + input_shape.insert(input_shape.begin(), (size_t)1); + + // get model input_bits + std::vector layers = model.attr("layers").cast>(); + auto input_layer = layers[0]; + model_input_bits = input_layer.attr("input_bits").cast(); + if((model_input_bits != 8) && (model_input_bits != 4)) { + ei_printf("ERR: Unsupported input_bits. Expected 4 or 8 got %d\n", model_input_bits); + return false; + } + + // initialize scale coefficients + if(model_input_bits == 8) { + scale = 255; + down_scale = 1; + } + else if(model_input_bits == 4) { + // these values are recommended by BrainChip + scale = 15; + down_scale = 16; + } + + if(debug) { + ei_printf("INFO: Model input_bits: %d\n", model_input_bits); + ei_printf("INFO: Scale: %f\n", scale); + ei_printf("INFO: Down scale: %d\n", down_scale); + } + +#if (defined(EI_CLASSIFIER_USE_AKIDA_HARDWARE) && (EI_CLASSIFIER_USE_AKIDA_HARDWARE == 1)) + // get list of available devices + py::list devices = akida.attr("devices")(); + if(devices.empty() == true) { + ei_printf("ERR: AKD1000 device not found!\n"); + return false; + } + + if(devices.size() > 1) { + ei_printf("More than one device found! Using /dev/akida%d\n", EI_CLASSIFIER_USE_AKIDA_HARDWARE_NO); + device = devices[EI_CLASSIFIER_USE_AKIDA_HARDWARE_NO]; + } + else { + device = devices[0]; + } + //TODO: check if selected device is correct (compare versions) + // enable power measurement + device.attr("soc").attr("power_measurement_enabled") = true; + + // map model to the device + try { + model.attr("map")(device); + } + catch (py::error_already_set &e) { + ei_printf("ERR: Can't load the ML model onto the AKD1000 SoC\n"); + ei_printf("ERR: %s\n", e.what()); + return false; + } +#elif (defined(EI_CLASSIFIER_USE_AKIDA_SOFTWARE) && (EI_CLASSIFIER_USE_AKIDA_SOFTWARE == 1)) +#warning "Akida model will be run in SIMULATION mode (not on real hardware)!" +#else +#error "Neither EI_CLASSIFIER_USE_AKIDA_HARDWARE or EI_CLASSIFIER_USE_AKIDA_SOFTWARE are defined or set to 1" +#endif + + // init softmax shape + std::vector tmp = model.attr("output_shape").cast>(); + softmax_shape.BuildFrom(tmp); + // dumy beta parameter for softmax purposes + dummy_params.beta = 1; + + // get reference to predict function + model_predict = model.attr("predict"); + model_forward = model.attr("forward"); + + // clear info stream + engine_info.str(""); + + return true; +} + +template +void debug_print(const std::vector vec, const int val_per_row = 3) +{ + int n = 0; + for(auto it = vec.begin(); it != vec.end(); it++) { + ei_printf("%f ", *it); + if(++n > val_per_row - 1) { + ei_printf("\n"); + n = 0; + } + } +} + +/** + * @brief Do neural network inferencing over the processed feature matrix + * + * @param impulse Struct describing impulse architecture + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug) +{ + ei_learning_block_config_tflite_graph_t *block_config = ((ei_learning_block_config_tflite_graph_t*)config_ptr); + ei_config_tflite_graph_t *graph_config = ((ei_config_tflite_graph_t*)block_config->graph_config); + + EI_IMPULSE_ERROR fill_res = EI_IMPULSE_OK; + + // init Python embedded interpreter (should be called once!) + static py::scoped_interpreter guard{}; + + // check if we've initialized the interpreter and device? + if (akida_initialized == false) { + if(init_akida(graph_config->model, graph_config->model_size, debug) == false) { + return EI_IMPULSE_AKIDA_ERROR; + } + akida_initialized = true; + } + + // according to: + // https://doc.brainchipinc.com/api_reference/akida_apis.html#akida.Model.predict + // input type is always uint8 + py::array_t input_data(input_shape); + + /* + * convert data to uint8 and copy features into input tensor + * For images RGB shape is (width, height, colors) + * For images BW shape is (width, height, 1) + * For Audio shape is (width, height, 1) - spectrogram + * TODO: test with other ML models/data types + * For details see: + * https://pybind11.readthedocs.io/en/stable/advanced/pycpp/numpy.html#direct-access + */ + auto r = input_data.mutable_unchecked<4>(); + float temp; + + size_t mtx_size = impulse->dsp_blocks_size + impulse->learning_blocks_size; + for (size_t i = 0; i < input_block_ids_size; i++) { + uint16_t cur_mtx = input_block_ids[i]; +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + ei::matrix_t* matrix = NULL; + + if (!find_mtx_by_idx(fmatrix, &matrix, cur_mtx, mtx_size)) { + ei_printf("ERR: Cannot find matrix with id %zu\n", cur_mtx); + return EI_IMPULSE_INVALID_SIZE; + } +#else + ei::matrix_t* matrix = fmatrix[0].matrix; +#endif + for (py::ssize_t x = 0; x < r.shape(1); x++) { + for (py::ssize_t y = 0; y < r.shape(2); y++) { + for(py::ssize_t z = 0; z < r.shape(3); z++) { + temp = (matrix->buffer[x * r.shape(2) * r.shape(3) + y * r.shape(3) + z] * scale); + temp = std::max(0.0f, std::min(temp, 255.0f)); + r(0, x, y, z) = (uint8_t)(temp / down_scale); + } + } + } + } + + // Run inference on AKD1000 + uint64_t ctx_start_us = ei_read_timer_us(); + py::array_t potentials; + try { + potentials = model_predict(input_data); + } + catch (py::error_already_set &e) { + ei_printf("ERR: Inference error:\n%s\n", e.what()); + return EI_IMPULSE_AKIDA_ERROR; + } + // TODO: 'forward' is returning int8 or int32, but EI SDK supports int8 or float32 only + // py::array_t potentials = model_forward(input_data); + uint64_t ctx_end_us = ei_read_timer_us(); + + potentials = potentials.squeeze(); + + if(debug) { + std::string ret_str = py::str(potentials).cast(); + ei_printf("AKD1000 raw output:\n%s\n", ret_str.c_str()); + } + + // convert to vector of floats to make further processing much easier + std::vector potentials_v;// = potentials.cast>(); + + // TODO: output conversion depending on output shape? + if (block_config->object_detection == false) { + potentials_v = potentials.squeeze().cast>(); + } + else { + // TODO: output from AkidaNet/MobileNet is always N x M x P (3 dimensions)? + auto q = potentials.unchecked<>(); + for (py::ssize_t x = 0; x < q.shape(0); x++) { + for (py::ssize_t y = 0; y < q.shape(1); y++) { + for(py::ssize_t z = 0; z < q.shape(2); z++) { + potentials_v.push_back(q(x, y, z)); + } + } + } + } + + if(block_config->object_detection_last_layer != EI_CLASSIFIER_LAST_LAYER_YOLOV2) { + // apply softmax, becuase Akida is not supporting this operation + tflite::reference_ops::Softmax(dummy_params, softmax_shape, potentials_v.data(), softmax_shape, potentials_v.data()); + } + + if(debug == true) { + ei_printf("After softmax:\n"); + debug_print(potentials_v); + } + + float active_power = 0; +#if (defined(EI_CLASSIFIER_USE_AKIDA_HARDWARE)) + // power measurement post-processing + float floor_power = device.attr("soc").attr("power_meter").attr("floor").cast(); + py::array pwr_events = device.attr("soc").attr("power_meter").attr("events")(); + auto events = pwr_events.mutable_unchecked(); + for (py::ssize_t i = 0; i < events.shape(0); i++) { + active_power += events(i).attr("power").cast(); + } + active_power = (active_power/pwr_events.size()) - floor_power; +#endif + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + // clear info + engine_info.str(""); + engine_info << "Power consumption: " << std::fixed << std::setprecision(2) << active_power << " mW\n"; + engine_info << "Inferences per second: " << (1000000 / result->timing.classification_us); + + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + fill_res = fill_result_struct_f32_fomo( + impulse, + block_config, + result, + potentials_v.data(), + impulse->fomo_output_size, + impulse->fomo_output_size); + break; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOV2: { + fill_res = fill_result_struct_f32_yolov2( + impulse, + block_config, + result, + potentials_v.data(), + impulse->tflite_output_features_count); + break; + } + case EI_CLASSIFIER_LAST_LAYER_SSD: { + ei_printf("ERR: MobileNet SSD models are not implemented for Akida (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOV5: { + ei_printf("ERR: YOLO v5 models are not implemented for Akida (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else { + fill_res = fill_result_struct_f32(impulse, result, potentials_v.data(), debug); + } + + return fill_res; +} + +/** + * Construct a tflite interpreter (creates it if needed) + */ +static EI_IMPULSE_ERROR get_interpreter(ei_learning_block_config_tflite_graph_t *block_config, tflite::Interpreter **interpreter) { + // not in the map yet... + if (!ei_tflite_instances.count(block_config->block_id)) { + ei_config_tflite_graph_t *graph_config = (ei_config_tflite_graph_t*)block_config->graph_config; + ei_tflite_state_t *new_state = new ei_tflite_state_t(); + + auto new_model = tflite::FlatBufferModel::BuildFromBuffer((const char*)graph_config->model, graph_config->model_size); + new_state->model = std::move(new_model); + if (!new_state->model) { + ei_printf("Failed to build TFLite model from buffer\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + tflite::ops::builtin::BuiltinOpResolver resolver; +#if EI_CLASSIFIER_HAS_TREE_ENSEMBLE_CLASSIFIER + resolver.AddCustom("TreeEnsembleClassifier", + tflite::ops::custom::Register_TREE_ENSEMBLE_CLASSIFIER()); +#endif + tflite::InterpreterBuilder builder(*new_state->model, resolver); + builder(&new_state->interpreter); + + if (!new_state->interpreter) { + ei_printf("Failed to construct interpreter\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + if (new_state->interpreter->AllocateTensors() != kTfLiteOk) { + ei_printf("AllocateTensors failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + int hw_thread_count = (int)std::thread::hardware_concurrency(); + hw_thread_count -= 1; // leave one thread free for the other application + if (hw_thread_count < 1) { + hw_thread_count = 1; + } + + if (new_state->interpreter->SetNumThreads(hw_thread_count) != kTfLiteOk) { + ei_printf("SetNumThreads failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + ei_tflite_instances.insert(std::make_pair(block_config->block_id, new_state)); + } + + auto tflite_state = ei_tflite_instances[block_config->block_id]; + *interpreter = tflite_state->interpreter.get(); + return EI_IMPULSE_OK; +} + + +extern "C" EI_IMPULSE_ERROR run_nn_inference_from_dsp( + ei_learning_block_config_tflite_graph_t *block_config, + signal_t *signal, + matrix_t *output_matrix) +{ + tflite::Interpreter *interpreter; + auto interpreter_ret = get_interpreter(block_config, &interpreter); + if (interpreter_ret != EI_IMPULSE_OK) { + return interpreter_ret; + } + + TfLiteTensor *input = interpreter->input_tensor(0); + TfLiteTensor *output = interpreter->output_tensor(0); + + if (!input) { + return EI_IMPULSE_INPUT_TENSOR_WAS_NULL; + } + if (!output) { + return EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL; + } + + auto input_res = fill_input_tensor_from_signal(signal, input); + if (input_res != EI_IMPULSE_OK) { + return input_res; + } + + TfLiteStatus status = interpreter->Invoke(); + if (status != kTfLiteOk) { + ei_printf("ERR: interpreter->Invoke() failed with %d\n", status); + return EI_IMPULSE_TFLITE_ERROR; + } + + auto output_res = fill_output_matrix_from_tensor(output, output_matrix); + if (output_res != EI_IMPULSE_OK) { + return output_res; + } + + // on Linux we're not worried about free'ing (for now) + + return EI_IMPULSE_OK; +} + +__attribute__((unused)) int extract_tflite_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float frequency) { + + ei_dsp_config_tflite_t *dsp_config = (ei_dsp_config_tflite_t*)config_ptr; + + ei_config_tflite_graph_t ei_config_tflite_graph_0 = { + .implementation_version = 1, + .model = dsp_config->model, + .model_size = dsp_config->model_size, + .arena_size = dsp_config->arena_size + }; + + ei_learning_block_config_tflite_graph_t ei_learning_block_config = { + .implementation_version = 1, + .classification_mode = EI_CLASSIFIER_CLASSIFICATION_MODE_DSP, + .block_id = dsp_config->block_id, + .object_detection = false, + .object_detection_last_layer = EI_CLASSIFIER_LAST_LAYER_UNKNOWN, + .output_data_tensor = 0, + .output_labels_tensor = 255, + .output_score_tensor = 255, + .threshold = 0, + .quantized = 0, + .compiled = 1, + .graph_config = &ei_config_tflite_graph_0 + }; + + auto x = run_nn_inference_from_dsp(&ei_learning_block_config, signal, output_matrix); + if (x != 0) { + return x; + } + + return EIDSP_OK; +} + +#endif // EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_AKIDA + +#endif /* EI_CLASSIFIER_INFERENCING_ENGINE_AKIDA_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/anomaly.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/anomaly.h new file mode 100644 index 0000000..7e595bf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/anomaly.h @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EDGE_IMPULSE_INFERENCING_ANOMALY_H_ +#define _EDGE_IMPULSE_INFERENCING_ANOMALY_H_ + +#if (EI_CLASSIFIER_HAS_ANOMALY) + +#include +#include +#include +#include +#include + +#include "edge-impulse-sdk/classifier/ei_classifier_types.h" +#include "edge-impulse-sdk/classifier/ei_aligned_malloc.h" +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/classifier/inferencing_engines/engines.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" + +#ifdef __cplusplus +namespace { +#endif // __cplusplus + +/** + * Standard scaler, scales all values in the input vector + * Note that this *modifies* the array in place! + * @param input Array of input values + * @param scale Array of scale values (obtain from StandardScaler in Python) + * @param mean Array of mean values (obtain from StandardScaler in Python) + * @param input_size Size of input, scale and mean arrays + */ +void standard_scaler(float *input, const float *scale, const float *mean, size_t input_size) { + for (size_t ix = 0; ix < input_size; ix++) { + input[ix] = (input[ix] - mean[ix]) / scale[ix]; + } +} + +/** + * Calculate the distance between input vector and the cluster + * @param input Array of input values (already scaled by standard_scaler) + * @param input_size Size of the input array + * @param cluster A cluster (number of centroids should match input_size) + */ +float calculate_cluster_distance(float *input, size_t input_size, const ei_classifier_anom_cluster_t *cluster) { + // todo: check input_size and centroid size? + + float dist = 0.0f; + for (size_t ix = 0; ix < input_size; ix++) { + dist += pow(input[ix] - cluster->centroid[ix], 2); + } + return sqrt(dist) - cluster->max_error; +} + +/** + * Get minimum distance to a cluster + * @param input Array of input values (already scaled by standard_scaler) + * @param input_size Size of the input array + * @param clusters Array of clusters + * @param cluster_size Size of cluster array + */ +float get_min_distance_to_cluster(float *input, size_t input_size, const ei_classifier_anom_cluster_t *clusters, size_t cluster_size) { + float min = 1000.0f; + for (size_t ix = 0; ix < cluster_size; ix++) { + float dist = calculate_cluster_distance(input, input_size, &clusters[ix]); + if (dist < min) { + min = dist; + } + } + return min; +} + +#ifdef __cplusplus +} +#endif // __cplusplus + + +/** + * Extracts the input values from the feature matrix based on the anomaly axes. + * @param fmatrix Feature matrix + * @param input_block_ids Array of block IDs to extract from the feature matrix + * @param input_block_ids_size Size of input_block_ids array + * @param block_config Anomaly block configuration + * @param input Array to store the extracted input values + * @return EI_IMPULSE_OK if successful, otherwise an error code + */ +EI_IMPULSE_ERROR extract_anomaly_input_values( + ei_feature_t *fmatrix, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + uint32_t anom_axes_size, + const uint16_t *anom_axis, + float *input) +{ + if (input_block_ids_size == 1) { + for (size_t ix = 0; ix < anom_axes_size; ix++) { + input[ix] = fmatrix[0].matrix->buffer[anom_axis[ix]]; + } + } + else { +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + ei::matrix_t* matrix = NULL; +#endif + // tracks where we are now in the combined feature matrix + uint32_t global_buf_pos = 0; + // we add the size of passed matrix to it + uint32_t buf_offset = 0; + // current index of input feature + uint32_t input_pos = 0; + + for (size_t i = 0; i < input_block_ids_size; i++) { +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + size_t cur_mtx = input_block_ids[i]; + if (!find_mtx_by_idx(fmatrix, &matrix, cur_mtx, anom_axes_size)) { + ei_printf("ERR: Cannot find matrix with id %zu\n", cur_mtx); + return EI_IMPULSE_INVALID_SIZE; + } +#else + ei::matrix_t* matrix = fmatrix[0].matrix; +#endif + for (size_t ix = 0; ix < anom_axes_size; ix++) { + global_buf_pos = anom_axis[input_pos]; + if (global_buf_pos <= buf_offset + (matrix->rows * matrix->cols)) { + input[input_pos] = matrix->buffer[anom_axis[input_pos] - buf_offset]; + input_pos++; + if (input_pos >= anom_axes_size) { goto end; } + } + else { + break; + } + } + buf_offset += matrix->rows * matrix->cols; + } + end:; + } + return EI_IMPULSE_OK; +} + + +EI_IMPULSE_ERROR run_kmeans_anomaly( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_anomaly_kmeans_t *block_config = (ei_learning_block_config_anomaly_kmeans_t*)config_ptr; + + uint64_t anomaly_start_us = ei_read_timer_us(); + + float *input = (float*)ei_malloc(block_config->anom_axes_size * sizeof(float)); + if (!input) { + ei_printf("Failed to allocate memory for anomaly input buffer"); + return EI_IMPULSE_OUT_OF_MEMORY; + } + + extract_anomaly_input_values(fmatrix, input_block_ids, input_block_ids_size, block_config->anom_axes_size, block_config->anom_axis, input); + + standard_scaler(input, block_config->anom_scale, block_config->anom_mean, block_config->anom_axes_size); + float anomaly = get_min_distance_to_cluster( + input, block_config->anom_axes_size, block_config->anom_clusters, block_config->anom_cluster_count); + + uint64_t anomaly_end_us = ei_read_timer_us(); + + if (debug) { + ei_printf("Anomaly score (time: %d ms.): ", static_cast(anomaly_end_us - anomaly_start_us)); + ei_printf_float(anomaly); + ei_printf("\n"); + } + + result->timing.anomaly_us = anomaly_end_us - anomaly_start_us; + result->timing.anomaly = (int)(result->timing.anomaly_us/1000); + result->anomaly = anomaly; + ei_free(input); + + return EI_IMPULSE_OK; +} + +#if (EI_CLASSIFIER_INFERENCING_ENGINE != EI_CLASSIFIER_NONE) +EI_IMPULSE_ERROR run_gmm_anomaly( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_anomaly_gmm_t *block_config = (ei_learning_block_config_anomaly_gmm_t*)config_ptr; + + ei_learning_block_config_tflite_graph_t ei_learning_block_config_gmm = { + .implementation_version = 1, + .classification_mode = block_config->classification_mode, + .block_id = 0, + .object_detection = 0, + .object_detection_last_layer = EI_CLASSIFIER_LAST_LAYER_UNKNOWN, + .output_data_tensor = 0, + .output_labels_tensor = 0, + .output_score_tensor = 0, + .threshold = block_config->anomaly_threshold, + .quantized = 0, + .compiled = 0, + .graph_config = block_config->graph_config + }; + + ei_impulse_result_t anomaly_result = { 0 }; + + std::unique_ptr input_ptr(new ei_feature_t[1]); + ei_feature_t* input = input_ptr.get(); + + memset(&anomaly_result, 0, sizeof(ei_impulse_result_t)); + + std::unique_ptr matrix_ptr(new ei::matrix_t(1, block_config->anom_axes_size)); + + if (block_config->classification_mode == EI_CLASSIFIER_CLASSIFICATION_MODE_VISUAL_ANOMALY) { + // [JJ] Here we assume that the feature extractor block is always directly before the GMM block + // if that changes (which I assume it will at some point, e.g. if we have a shared backbone) + // this will break. Would it be better if `run_nn_inference` would get pointers to the input/output + // matrices instead? + input[0].matrix = fmatrix[impulse->dsp_blocks_size + (learn_block_index - 1)].matrix; + input[0].blockId = fmatrix[impulse->dsp_blocks_size + (learn_block_index - 1)].blockId; + + input_block_ids_size = 1; + } + else { + input[0].matrix = matrix_ptr.get(); + input[0].blockId = 0; + + extract_anomaly_input_values(fmatrix, input_block_ids, input_block_ids_size, block_config->anom_axes_size, block_config->anom_axis, input[0].matrix->buffer); + input_block_ids_size = 1; + } + + EI_IMPULSE_ERROR res = run_nn_inference(impulse, input, learn_block_index, input_block_ids, input_block_ids_size, &anomaly_result, (void*)&ei_learning_block_config_gmm, debug); + if (res != EI_IMPULSE_OK) { + return res; + } + + if (debug) { + ei_printf("Anomaly score (time: %d ms.): ", anomaly_result.timing.classification); + ei_printf_float(anomaly_result.classification[0].value); + ei_printf("\n"); + } + + result->timing.anomaly_us = anomaly_result.timing.classification_us; + result->timing.anomaly = anomaly_result.timing.classification; + + if (block_config->classification_mode == EI_CLASSIFIER_CLASSIFICATION_MODE_VISUAL_ANOMALY) { +#if EI_CLASSIFIER_HAS_VISUAL_ANOMALY + result->visual_ad_grid_cells = anomaly_result.visual_ad_grid_cells; + result->visual_ad_count = anomaly_result.visual_ad_count; + result->visual_ad_result.mean_value = anomaly_result.visual_ad_result.mean_value; + result->visual_ad_result.max_value = anomaly_result.visual_ad_result.max_value; +#endif // EI_CLASSIFIER_HAS_VISUAL_ANOMALY + } + else { + result->anomaly = anomaly_result.classification[0].value; + } + + return EI_IMPULSE_OK; +} +#endif // (EI_CLASSIFIER_INFERENCING_ENGINE != EI_CLASSIFIER_NONE) + +#endif //#if (EI_CLASSIFIER_HAS_ANOMALY == 1) +#endif // _EDGE_IMPULSE_INFERENCING_ANOMALY_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/drpai.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/drpai.h new file mode 100644 index 0000000..6ecea7d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/drpai.h @@ -0,0 +1,758 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_DRPAI_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_DRPAI_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI) + +/***************************************** + * includes + ******************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#if ((EI_CLASSIFIER_OBJECT_DETECTION == 1) && (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI)) +// For a YOLOV5_V5_DRPAI model we ran the unsupported layers with TF +#include +#include "tensorflow-lite/tensorflow/lite/c/common.h" +#include "tensorflow-lite/tensorflow/lite/interpreter.h" +#include "tensorflow-lite/tensorflow/lite/kernels/register.h" +#include "tensorflow-lite/tensorflow/lite/model.h" +#include "tensorflow-lite/tensorflow/lite/optional_debug_tools.h" +#endif +#include "edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/classifier/ei_run_dsp.h" +#include "edge-impulse-sdk/porting/ei_logging.h" + +#include +#include + + + +/***************************************** + * Macro + ******************************************/ +/*Maximum DRP-AI Timeout threshold*/ +#define DRPAI_TIMEOUT (5) + +/*Buffer size for writing data to memory via DRP-AI Driver.*/ +#define BUF_SIZE (1024) + +/*Index to access drpai_file_path[]*/ +#define INDEX_D (0) +#define INDEX_C (1) +#define INDEX_P (2) +#define INDEX_A (3) +#define INDEX_W (4) + +/***************************************** + * Public global vars + ******************************************/ +// input and output buffer pointers for memory mapped regions used by DRP-AI +uint8_t *drpai_input_buf = (uint8_t *)NULL; +float *drpai_output_buf = (float *)NULL; + +/***************************************** + * Typedef + ******************************************/ +/* For DRP-AI Address List */ +typedef struct { + unsigned long desc_aimac_addr; + unsigned long desc_aimac_size; + unsigned long desc_drp_addr; + unsigned long desc_drp_size; + unsigned long drp_param_addr; + unsigned long drp_param_size; + unsigned long data_in_addr; + unsigned long data_in_size; + unsigned long data_addr; + unsigned long data_size; + unsigned long work_addr; + unsigned long work_size; + unsigned long data_out_addr; + unsigned long data_out_size; + unsigned long drp_config_addr; + unsigned long drp_config_size; + unsigned long weight_addr; + unsigned long weight_size; +} st_addr_t; + +/***************************************** + * static vars + ******************************************/ +static st_addr_t drpai_address; +static uint64_t udmabuf_address = 0; + +static int drpai_fd = -1; + +drpai_data_t proc[DRPAI_INDEX_NUM]; + +void get_udmabuf_memory_start_addr() +{ /* Obtain udmabuf memory area starting address */ + + int8_t fd = 0; + char addr[1024]; + int32_t read_ret = 0; + errno = 0; + + fd = open("/sys/class/u-dma-buf/udmabuf0/phys_addr", O_RDONLY); + if (0 > fd) + { + fprintf(stderr, "[ERROR] Failed to open udmabuf0/phys_addr : errno=%d\n", errno); + } + + read_ret = read(fd, addr, 1024); + if (0 > read_ret) + { + fprintf(stderr, "[ERROR] Failed to read udmabuf0/phys_addr : errno=%d\n", errno); + close(fd); + } + + sscanf(addr, "%lx", &udmabuf_address); + close(fd); + + /* Filter the bit higher than 32 bit */ + udmabuf_address &=0xFFFFFFFF; +} + +uint8_t drpai_init_mem(uint32_t input_frame_size) { + int32_t i = 0; + + int udmabuf_fd0 = open("/dev/udmabuf0", O_RDWR); + if (udmabuf_fd0 < 0) { + return -1; + } + + // input_frame_size === data_in_size + uint8_t *addr = + (uint8_t *)mmap(NULL, input_frame_size, + PROT_READ | PROT_WRITE, MAP_SHARED, udmabuf_fd0, 0); + + drpai_input_buf = addr; + + /* Write once to allocate physical memory to u-dma-buf virtual space. + * Note: Do not use memset() for this. + * Because it does not work as expected. */ + for (i = 0; i < input_frame_size; i++) { + drpai_input_buf[i] = 0; + } + + + get_udmabuf_memory_start_addr(); + if (0 == udmabuf_address) { + return EI_IMPULSE_DRPAI_INIT_FAILED; + } + + return 0; +} + +/***************************************** + * Function Name : read_addrmap_txt + * Description : Loads address and size of DRP-AI Object files into struct + *addr. Arguments : addr_file = filename of addressmap file (from + *DRP-AI Object files) Return value : 0 if succeeded not 0 otherwise + ******************************************/ +static int8_t read_addrmap_txt() { + // create a stream from the DRP-AI model data without copying + std::istringstream ifs; + ifs.rdbuf()->pubsetbuf((char *)ei_ei_addrmap_intm_txt, ei_ei_addrmap_intm_txt_len); + + std::string str; + unsigned long l_addr; + unsigned long l_size; + std::string element, a, s; + + if (ifs.fail()) { + return -1; + } + + while (getline(ifs, str)) { + std::istringstream iss(str); + iss >> element >> a >> s; + l_addr = strtol(a.c_str(), NULL, 16); + l_size = strtol(s.c_str(), NULL, 16); + + if (element == "drp_config") { + drpai_address.drp_config_addr = l_addr; + drpai_address.drp_config_size = l_size; + } else if (element == "desc_aimac") { + drpai_address.desc_aimac_addr = l_addr; + drpai_address.desc_aimac_size = l_size; + } else if (element == "desc_drp") { + drpai_address.desc_drp_addr = l_addr; + drpai_address.desc_drp_size = l_size; + } else if (element == "drp_param") { + drpai_address.drp_param_addr = l_addr; + drpai_address.drp_param_size = l_size; + } else if (element == "weight") { + drpai_address.weight_addr = l_addr; + drpai_address.weight_size = l_size; + } else if (element == "data_in") { + drpai_address.data_in_addr = l_addr; + drpai_address.data_in_size = l_size; + } else if (element == "data") { + drpai_address.data_addr = l_addr; + drpai_address.data_size = l_size; + } else if (element == "data_out") { + drpai_address.data_out_addr = l_addr; + drpai_address.data_out_size = l_size; + } else if (element == "work") { + drpai_address.work_addr = l_addr; + drpai_address.work_size = l_size; + } + } + + return 0; +} + +/***************************************** + * Function Name : load_data_to_mem + * Description : Loads a binary blob DRP-AI Driver Memory + * Arguments : data_ptr = pointer to the bytes to write + * drpai_fd = file descriptor of DRP-AI Driver + * from = memory start address where the data is + *written size = data size to be written Return value : 0 if succeeded not 0 + *otherwise + ******************************************/ +static int8_t load_data_to_mem(unsigned char *data_ptr, int drpai_fd, + unsigned long from, unsigned long size) { + drpai_data_t drpai_data; + + drpai_data.address = from; + drpai_data.size = size; + + errno = 0; + if (-1 == ioctl(drpai_fd, DRPAI_ASSIGN, &drpai_data)) { + return -1; + } + + errno = 0; + if (-1 == write(drpai_fd, data_ptr, size)) { + return -1; + } + + return 0; +} + +/***************************************** + * Function Name : load_drpai_data + * Description : Loads DRP-AI Object files to memory via DRP-AI Driver. + * Arguments : drpai_fd = file descriptor of DRP-AI Driver + * Return value : 0 if succeeded + * : not 0 otherwise + ******************************************/ +static int load_drpai_data(int drpai_fd) { + unsigned long addr, size; + unsigned char *data_ptr; + for (int i = 0; i < 5; i++) { + switch (i) { + case (INDEX_W): + addr = drpai_address.weight_addr; + size = drpai_address.weight_size; + data_ptr = ei_ei_weight_dat; + break; + case (INDEX_C): + addr = drpai_address.drp_config_addr; + size = drpai_address.drp_config_size; + data_ptr = ei_ei_drpcfg_mem; + break; + case (INDEX_P): + addr = drpai_address.drp_param_addr; + size = drpai_address.drp_param_size; + data_ptr = ei_drp_param_bin; + break; + case (INDEX_A): + addr = drpai_address.desc_aimac_addr; + size = drpai_address.desc_aimac_size; + data_ptr = ei_aimac_desc_bin; + break; + case (INDEX_D): + addr = drpai_address.desc_drp_addr; + size = drpai_address.desc_drp_size; + data_ptr = ei_drp_desc_bin; + break; + default: + return -1; + break; + } + if (0 != load_data_to_mem(data_ptr, drpai_fd, addr, size)) { + return -1; + } + } + return 0; +} + +EI_IMPULSE_ERROR drpai_init_classifier() { + // retval for drpai status + int ret_drpai; + + // Read DRP-AI Object files address and size + if (0 != read_addrmap_txt()) { + ei_printf("ERR: read_addrmap_txt failed : %d\n", errno); + return EI_IMPULSE_DRPAI_INIT_FAILED; + } + + // DRP-AI Driver Open + drpai_fd = open("/dev/drpai0", O_RDWR); + if (drpai_fd < 0) { + ei_printf("ERR: Failed to Open DRP-AI Driver: errno=%d\n", errno); + return EI_IMPULSE_DRPAI_INIT_FAILED; + } + + // Load DRP-AI Data from Filesystem to Memory via DRP-AI Driver + ret_drpai = load_drpai_data(drpai_fd); + if (ret_drpai != 0) { + ei_printf("ERR: Failed to load DRPAI Data\n"); + if (0 != close(drpai_fd)) { + ei_printf("ERR: Failed to Close DRPAI Driver: errno=%d\n", errno); + } + return EI_IMPULSE_DRPAI_INIT_FAILED; + } + + // statically store DRP object file addresses and sizes + proc[DRPAI_INDEX_INPUT].address = (uint32_t)udmabuf_address; + proc[DRPAI_INDEX_INPUT].size = drpai_address.data_in_size; + proc[DRPAI_INDEX_DRP_CFG].address = drpai_address.drp_config_addr; + proc[DRPAI_INDEX_DRP_CFG].size = drpai_address.drp_config_size; + proc[DRPAI_INDEX_DRP_PARAM].address = drpai_address.drp_param_addr; + proc[DRPAI_INDEX_DRP_PARAM].size = drpai_address.drp_param_size; + proc[DRPAI_INDEX_AIMAC_DESC].address = drpai_address.desc_aimac_addr; + proc[DRPAI_INDEX_AIMAC_DESC].size = drpai_address.desc_aimac_size; + proc[DRPAI_INDEX_DRP_DESC].address = drpai_address.desc_drp_addr; + proc[DRPAI_INDEX_DRP_DESC].size = drpai_address.desc_drp_size; + proc[DRPAI_INDEX_WEIGHT].address = drpai_address.weight_addr; + proc[DRPAI_INDEX_WEIGHT].size = drpai_address.weight_size; + proc[DRPAI_INDEX_OUTPUT].address = drpai_address.data_out_addr; + proc[DRPAI_INDEX_OUTPUT].size = drpai_address.data_out_size; + + EI_LOGD("proc[DRPAI_INDEX_INPUT] addr: %p, size: %p\r\n", proc[DRPAI_INDEX_INPUT].address, proc[DRPAI_INDEX_INPUT].size); + EI_LOGD("proc[DRPAI_INDEX_DRP_CFG] addr: %p, size: %p\r\n", proc[DRPAI_INDEX_DRP_CFG].address, proc[DRPAI_INDEX_DRP_CFG].size); + EI_LOGD("proc[DRPAI_INDEX_DRP_PARAM] addr: %p, size: %p\r\n", proc[DRPAI_INDEX_DRP_PARAM].address, proc[DRPAI_INDEX_DRP_PARAM].size); + EI_LOGD("proc[DRPAI_INDEX_AIMAC_DESC] addr: %p, size: %p\r\n", proc[DRPAI_INDEX_AIMAC_DESC].address, proc[DRPAI_INDEX_AIMAC_DESC].size); + EI_LOGD("proc[DRPAI_INDEX_DRP_DESC] addr: %p, size: %p\r\n", proc[DRPAI_INDEX_DRP_DESC].address, proc[DRPAI_INDEX_DRP_DESC].size); + EI_LOGD("proc[DRPAI_INDEX_WEIGHT] addr: %p, size: %p\r\n", proc[DRPAI_INDEX_WEIGHT].address, proc[DRPAI_INDEX_WEIGHT].size); + EI_LOGD("proc[DRPAI_INDEX_OUTPUT] addr: %p, size: %p\r\n", proc[DRPAI_INDEX_OUTPUT].address, proc[DRPAI_INDEX_OUTPUT].size); + + drpai_output_buf = (float *)ei_malloc(drpai_address.data_out_size); + + return EI_IMPULSE_OK; +} + +EI_IMPULSE_ERROR drpai_run_classifier_image_quantized() { +#if EI_CLASSIFIER_COMPILED == 1 +#error "DRP-AI is not compatible with EON Compiler" +#endif + // output data from DRPAI model + drpai_data_t drpai_data; + // status used to query if any internal errors occured during inferencing + drpai_status_t drpai_status; + // descriptor used for checking if DRPAI is done inferencing + fd_set rfds; + // struct used to define DRPAI timeout + struct timespec tv; + // retval for drpai status + int ret_drpai; + // retval when querying drpai status + int inf_status = 0; + + // DRP-AI Output Memory Preparation + drpai_data.address = drpai_address.data_out_addr; + drpai_data.size = drpai_address.data_out_size; + + // Start DRP-AI driver + EI_LOGD("Start DRPAI inference\r\n"); + int ioret = ioctl(drpai_fd, DRPAI_START, &proc[0]); + if (0 != ioret) { + EI_LOGE("Failed to Start DRPAI Inference: %d\n", errno); + return EI_IMPULSE_DRPAI_RUNTIME_FAILED; + } + + // Settings For pselect - this is how DRPAI signals inferencing complete + FD_ZERO(&rfds); + FD_SET(drpai_fd, &rfds); + // Define a timeout for DRP-AI to complete + tv.tv_sec = DRPAI_TIMEOUT; + tv.tv_nsec = 0; + + // Wait until DRP-AI ends + EI_LOGD("Waiting on DRPAI inference results\r\n"); + ret_drpai = pselect(drpai_fd + 1, &rfds, NULL, NULL, &tv, NULL); + if (ret_drpai == 0) { + EI_LOGE("DRPAI Inference pselect() Timeout: %d\n", errno); + return EI_IMPULSE_DRPAI_RUNTIME_FAILED; + } else if (ret_drpai < 0) { + EI_LOGE("DRPAI Inference pselect() Error: %d\n", errno); + return EI_IMPULSE_DRPAI_RUNTIME_FAILED; + } + + // Checks for DRPAI inference status errors + EI_LOGD("Getting DRPAI Status\r\n"); + inf_status = ioctl(drpai_fd, DRPAI_GET_STATUS, &drpai_status); + if (inf_status != 0) { + EI_LOGE("DRPAI Internal Error: %d\n", errno); + return EI_IMPULSE_DRPAI_RUNTIME_FAILED; + } + + EI_LOGD("Getting inference results\r\n"); + if (ioctl(drpai_fd, DRPAI_ASSIGN, &drpai_data) != 0) { + EI_LOGE("Failed to Assign DRPAI data: %d\n", errno); + return EI_IMPULSE_DRPAI_RUNTIME_FAILED; + } + + if (read(drpai_fd, drpai_output_buf, drpai_data.size) < 0) { + EI_LOGE("Failed to read DRPAI output data: %d\n", errno); + return EI_IMPULSE_DRPAI_RUNTIME_FAILED; + } + return EI_IMPULSE_OK; +} + +// close the driver (reset file handles) +EI_IMPULSE_ERROR drpai_close(uint32_t input_frame_size) { + munmap(drpai_input_buf, input_frame_size); + free(drpai_output_buf); + if (drpai_fd > 0) { + if (0 != close(drpai_fd)) { + EI_LOGE("Failed to Close DRP-AI Driver: errno=%d\n", errno); + return EI_IMPULSE_DRPAI_RUNTIME_FAILED; + } + drpai_fd = -1; + } + return EI_IMPULSE_OK; +} + +#if ((EI_CLASSIFIER_OBJECT_DETECTION == 1) && (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI)) +EI_IMPULSE_ERROR drpai_run_yolov5_postprocessing( + const ei_impulse_t *impulse, + ei_learning_block_config_tflite_graph_t *block_config, + signal_t *signal, + ei_impulse_result_t *result, + bool debug = false) +{ + + static std::unique_ptr model = nullptr; + static std::unique_ptr interpreter = nullptr; + + if (!model) { + model = tflite::FlatBufferModel::BuildFromBuffer((const char*)yolov5_part2, yolov5_part2_len); + if (!model) { + ei_printf("Failed to build TFLite model from buffer\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + tflite::ops::builtin::BuiltinOpResolver resolver; + tflite::InterpreterBuilder builder(*model, resolver); + builder(&interpreter); + + if (!interpreter) { + ei_printf("Failed to construct interpreter\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + if (interpreter->AllocateTensors() != kTfLiteOk) { + ei_printf("AllocateTensors failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + int hw_thread_count = (int)std::thread::hardware_concurrency(); + hw_thread_count -= 1; // leave one thread free for the other application + if (hw_thread_count < 1) { + hw_thread_count = 1; + } + + if (interpreter->SetNumThreads(hw_thread_count) != kTfLiteOk) { + ei_printf("SetNumThreads failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + } + + const size_t drpai_buff_size = drpai_address.data_out_size / sizeof(float); + const size_t drpai_features = drpai_buff_size; + + const size_t els_per_grid = drpai_features / ((NUM_GRID_1 * NUM_GRID_1) + (NUM_GRID_2 * NUM_GRID_2) + (NUM_GRID_3 * NUM_GRID_3)); + + const size_t grid_1_offset = 0; + const size_t grid_1_size = (NUM_GRID_1 * NUM_GRID_1) * els_per_grid; + + const size_t grid_2_offset = grid_1_offset + grid_1_size; + const size_t grid_2_size = (NUM_GRID_2 * NUM_GRID_2) * els_per_grid; + + const size_t grid_3_offset = grid_2_offset + grid_2_size; + const size_t grid_3_size = (NUM_GRID_3 * NUM_GRID_3) * els_per_grid; + + // Now we don't know the exact tensor order for some reason + // so let's do that dynamically + for (size_t ix = 0; ix < 3; ix++) { + TfLiteTensor * tensor = interpreter->input_tensor(ix); + size_t tensor_size = 1; + for (size_t ix = 0; ix < tensor->dims->size; ix++) { + tensor_size *= tensor->dims->data[ix]; + } + + EI_LOGD("input tensor %d, tensor_size=%d\n", (int)ix, (int)tensor_size); + + float *input = interpreter->typed_input_tensor(ix); + + if (tensor_size == grid_1_size) { + memcpy(input, drpai_output_buf + grid_1_offset, grid_1_size * sizeof(float)); + } + else if (tensor_size == grid_2_size) { + memcpy(input, drpai_output_buf + grid_2_offset, grid_2_size * sizeof(float)); + } + else if (tensor_size == grid_3_size) { + memcpy(input, drpai_output_buf + grid_3_offset, grid_3_size * sizeof(float)); + } + else { + ei_printf("ERR: Cannot determine which grid to use for input tensor %d with %d tensor size\n", + (int)ix, (int)tensor_size); + return EI_IMPULSE_TFLITE_ERROR; + } + } + + uint64_t ctx_start_us = ei_read_timer_us(); + + interpreter->Invoke(); + + uint64_t ctx_end_us = ei_read_timer_us(); + + EI_LOGD("Invoke took %d ms.\n", (int)((ctx_end_us - ctx_start_us) / 1000)); + + float* out_data = interpreter->typed_output_tensor(0); + + const size_t out_size = impulse->tflite_output_features_count; + + if (debug) { + printf("First 20 bytes: "); + for (size_t ix = 0; ix < 20; ix++) { + ei_printf("%f ", out_data[ix]); + } + ei_printf("\n"); + } + + // printf("Last 5 bytes: "); + // for (size_t ix = out_size - 5; ix < out_size; ix++) { + // printf("%f ", out_data[ix]); + // } + // printf("\n"); + + return fill_result_struct_f32_yolov5(impulse, block_config, result, 5, out_data, out_size); +} +#endif + +/** + * @brief Do neural network inferencing over the processed feature matrix + * + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug) +{ + // dummy, not used for DRPAI +} + +/** + * Special function to run the classifier on images, only works on TFLite models (either interpreter or EON or for tensaiflow) + * that allocates a lot less memory by quantizing in place. This only works if 'can_run_classifier_image_quantized' + * returns EI_IMPULSE_OK. + */ +EI_IMPULSE_ERROR run_nn_inference_image_quantized( + const ei_impulse_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + // this needs to be changed for multi-model, multi-impulse + static bool first_run = true; + uint64_t ctx_start_us; + uint64_t dsp_start_us = ei_read_timer_us(); + + if (first_run) { + // map memory regions to the DRP-AI UDMA. This is required for passing data + // to and from DRP-AI + int t = drpai_init_mem(impulse->nn_input_frame_size); + if (t != 0) { + return EI_IMPULSE_DRPAI_INIT_FAILED; + } + + EI_IMPULSE_ERROR ret = drpai_init_classifier(); + if (ret != EI_IMPULSE_OK) { + drpai_close(impulse->nn_input_frame_size); + return EI_IMPULSE_DRPAI_INIT_FAILED; + } + + EI_LOGI("Initialized input and output buffers:\r\n"); + EI_LOGI("input buf (addr: %p, size: 0x%x)\r\n", drpai_input_buf, drpai_address.data_in_size); + EI_LOGI("output buf (addr: %p, size: 0x%x)\r\n", drpai_output_buf, drpai_address.data_out_size); + EI_LOGI("udmabuf_addr: %p\n", udmabuf_address); + } + + EI_LOGD("Starting DSP...\n"); + int ret; + + EI_LOGD("fmatrix size == Bpp * signal.total_length ( %p == %p * %p = %p )\r\n", proc[DRPAI_INDEX_INPUT].size, 3, signal->total_length, 3 * signal->total_length); + // Creates a features matrix mapped to the DRP-AI UDMA input region + ei::matrix_u8_t features_matrix(1, proc[DRPAI_INDEX_INPUT].size, drpai_input_buf); + + // Grabs the raw image buffer from the signal, DRP-AI will automatically + // extract features + ret = extract_drpai_features_quantized( + signal, + &features_matrix, + impulse->dsp_blocks[0].config, + impulse->frequency); + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to run DSP process (%d)\n", ret); + return EI_IMPULSE_DSP_ERROR; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + result->timing.dsp_us = ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + if (debug) { + ei_printf("Features (%d ms.): ", result->timing.dsp); + for (size_t ix = 0; ix < EI_CLASSIFIER_NN_INPUT_FRAME_SIZE; ix++) { + ei_printf("0x%hhx, ", drpai_input_buf[ix]); + } + ei_printf("\n"); + } + + ctx_start_us = ei_read_timer_us(); + + // Run DRP-AI inference, a static buffer is used to store the raw output + // results + ret = drpai_run_classifier_image_quantized(); + + // close driver to reset memory, file pointer + if (ret != EI_IMPULSE_OK) { + drpai_close(impulse->nn_input_frame_size); + first_run = true; + } + else { + // drpai_reset(); + first_run = false; + } + + EI_IMPULSE_ERROR fill_res = EI_IMPULSE_OK; + + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + if (debug) { + ei_printf("DEBUG: raw drpai output"); + ei_printf("\n["); + for (uint32_t i = 0; i < impulse->tflite_output_features_count; i++) { + ei_printf_float(drpai_output_buf[i]); + ei_printf(" "); + } + ei_printf("]\n"); + } + + fill_res = fill_result_struct_f32_fomo( + impulse, + block_config, + result, + drpai_output_buf, + impulse->fomo_output_size, + impulse->fomo_output_size); + break; + } + case EI_CLASSIFIER_LAST_LAYER_SSD: { + ei_printf("ERR: MobileNet SSD models are not implemented for DRP-AI (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI: { + if (block_config->quantized == 1) { + ei_printf("ERR: YOLOv5 does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + if (debug) { + ei_printf("DEBUG: raw drpai output"); + ei_printf("\n["); + // impulse->tflite_output_features_count can't be used here as this is not the final output + // so print only the first 10 values. + for (uint32_t i = 0; i < 10; i++) { + ei_printf_float(drpai_output_buf[i]); + ei_printf(" "); + } + ei_printf("]\n"); + } + } + +#if ((EI_CLASSIFIER_OBJECT_DETECTION == 1) && (EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI)) + // do post processing + fill_res = drpai_run_yolov5_postprocessing(impulse, block_config, signal, result, debug); +#endif + break; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else { + fill_res = fill_result_struct_f32(impulse, result, drpai_output_buf, debug); + } + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + result->timing.classification_us = ei_read_timer_us() - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + return EI_IMPULSE_OK; +} + +#endif // #if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_DRPAI_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/engines.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/engines.h new file mode 100644 index 0000000..5fa4bd1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/engines.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_ENGINES_H_ +#define _EI_CLASSIFIER_ENGINES_H_ + +#include "edge-impulse-sdk/classifier/ei_model_types.h" + +EI_IMPULSE_ERROR run_kmeans_anomaly( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug); + +EI_IMPULSE_ERROR run_gmm_anomaly( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug); + +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug); + +int extract_tflite_eon_features(signal_t *signal, matrix_t *output_matrix, + void *config_ptr, const float frequency); + +int extract_tflite_features(signal_t *signal, matrix_t *output_matrix, + void *config_ptr, const float frequency); + +#endif // _EI_CLASSIFIER_ENGINES_H_s \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/memryx.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/memryx.h new file mode 100644 index 0000000..5ce2516 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/memryx.h @@ -0,0 +1,476 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef EI_CLASSIFIER_INFERENCING_ENGINE_MEMRYX_H +#define EI_CLASSIFIER_INFERENCING_ENGINE_MEMRYX_H + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_MEMRYX) + +/** + * @brief we are forcing SOFTWARE inference (simulation), + * beacuse use of hardware is not ready + * + */ +#ifndef EI_CLASSIFIER_USE_MEMRYX_SOFTWARE +#define EI_CLASSIFIER_USE_MEMRYX_HARDWARE 1 +#endif + +/** + * @brief Memryx accelerator can leverage up to four MX3 chips for inference. + * Specify here the number of chips to be used for acceleration, + * e.g. set to 4 in order to use all four chips of the M3X board. + */ +#ifndef EI_CLASSIFIER_USE_MEMRYX_CHIPS_COUNT +#define EI_CLASSIFIER_USE_MEMRYX_CHIPS_COUNT 1 +#endif + +#include "model-parameters/model_metadata.h" +#if EI_CLASSIFIER_HAS_MODEL_VARIABLES == 1 +#include "model-parameters/model_variables.h" +#endif + +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "tensorflow-lite/tensorflow/lite/kernels/internal/reference/softmax.h" +#include +#include +#include +#include +#include +#include +#ifdef EI_CLASSIFIER_USE_MEMRYX_SOFTWARE +#include "pybind11/embed.h" +#include "pybind11/numpy.h" +#include "pybind11/stl.h" +#else +#include "memx/memx.h" +#endif +/* Headers below help us bundle the DFP model with EIM in single binary */ +#include "memryx-model/memryx-model.h" +#include "utils/model_header_utils.h" + +/* Result delivered by memryx simulator contains 3 fields, indexes for print */ +#define MX_SIM_RES_OUTPUTS 0 +#define MX_SIM_RES_LATENCY 1 +#define MX_SIM_RES_FPS 2 + +std::stringstream engine_info; + +static bool memryx_initialized = false; + +#ifdef EI_CLASSIFIER_USE_MEMRYX_SOFTWARE +/* brings in the `_a` literals to set args to python API */ +using namespace pybind11::literals; +namespace py = pybind11; +/* PyBind variables for EIM with Simulator */ +static py::module_ memryx; +static py::module_ np; +static py::object zeroes; +static py::object Simulator; +static py::object model; +static py::object device; +static std::vector vec; +#endif + +#ifdef EI_CLASSIFIER_USE_MEMRYX_HARDWARE +/* Variables for EIM with Hardware */ +const uint8_t flow_id = 0; // flow port 0 +const uint8_t model_id = 0; // model 0 +const uint8_t group_id = 0; // MPU device group 0 +const int timeout = 0; // was 200 ms +int argmax = 0; // index with maximum score +#endif + +/* We need a workaround for softmax because + * the MX3+ is not coming out this year, and + * the MX3 does not support the SoftMax layer + */ +static tflite::RuntimeShape softmax_shape; +static tflite::SoftmaxParams dummy_params; + +static bool verbose_debug = 0; + +bool init_memryx(bool debug, const ei_impulse_t *impulse) +{ + /* Unpack DFP model to file system */ + std::string project_file_path = "/tmp/" + std::string(impulse->project_name) + "-" + std::to_string(impulse->project_id) + "-" + std::to_string(impulse->deploy_version); + create_project_if_not_exists(project_file_path, model_h_files, model_h_files_len); + + std::string proj_model_path = project_file_path + "/memryx_trained.dfp"; + const char * model_file_path = proj_model_path.c_str(); +#if (defined(EI_CLASSIFIER_USE_MEMRYX_HARDWARE) && (EI_CLASSIFIER_USE_MEMRYX_HARDWARE == 1)) +#warning "Building EIM for use with MemryX Hardware" + memx_status status = MEMX_STATUS_OK; + // 1. Bind MPU device group 0 as MX3:Cascade to model 0. + status = memx_open(model_id, group_id, MEMX_DEVICE_CASCADE); + if(memx_status_error(status)) { + return false; + } + ei_printf("Memryx device opened.\n"); + + // 2. Download model from a DFP file to MPU device group, input and + // output feature map shape is auto, configured after download complete. + status = memx_download_model(model_id, model_file_path, 0, // model_idx = 0 + MEMX_DOWNLOAD_TYPE_WTMEM_AND_MODEL); + if(memx_status_error(status)) { + return false; + } + ei_printf("Memryx model downloaded.\n"); + + // 3. Enable data transfer of this model to device. Set to no wait here + // since driver will go to data transfer state eventually. + status = memx_set_stream_enable(model_id, 0); + if(memx_status_error(status)) { + return false; + } + ei_printf("Data streaming to and from the MX3 board is enabled\n"); +#elif (defined(EI_CLASSIFIER_USE_MEMRYX_SOFTWARE) && (EI_CLASSIFIER_USE_MEMRYX_SOFTWARE == 1)) +#warning "MEMRYX model will be run in SIMULATION mode (not on real hardware)!" + py::list path; + // import Python's memryx module + try { + memryx = py::module_::import("memryx"); + if(debug) printf("Memryx PyModule init\n"); + } + catch (py::error_already_set &e) { + ei_printf("ERR: Importing 'memryx' library failed:\n%s\n", e.what()); + return false; + } + + Simulator = memryx.attr("Simulator"); + if(debug) printf("Simulator API init\n"); + + // load model + try { + model = Simulator("dfp"_a = model_file_path); + if(debug) printf("Model API init\n"); + } + catch (py::error_already_set &e) { + ei_printf("ERR: Can't load model file from %s\n", model_file_path); + return false; + } +#else +#error "Neither EI_CLASSIFIER_USE_MEMRYX_HARDWARE or EI_CLASSIFIER_USE_MEMRYX_SOFTWARE are defined or set to 1" +#endif + + // clear info + engine_info.str(""); + + return true; +} + + +/** + * @brief Do neural network inferencing over the processed feature matrix + * + * @param impulse Struct describing impulse architecture + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +#if (defined(EI_CLASSIFIER_USE_MEMRYX_HARDWARE) && (EI_CLASSIFIER_USE_MEMRYX_HARDWARE == 1)) +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + memx_status status = MEMX_STATUS_OK; + int32_t ifmap_height, ifmap_width, ifmap_channel_number, ifmap_format; + int32_t ofmap_height, ofmap_width, ofmap_channel_number, ofmap_format; + int32_t z; + uint64_t ctx_start_us = 0; + uint64_t ctx_end_us = 0; + + // check if we've initialized the interpreter and device? + if (memryx_initialized == false) { + if(init_memryx(debug, impulse) == false) { + return EI_IMPULSE_MEMRYX_ERROR; + } + memryx_initialized = true; + } + + /* 4. get input shape - Not needed during runtime, available only for debugging */ + if(verbose_debug) { + status = memx_get_ifmap_size(model_id, flow_id, &ifmap_height, &ifmap_width, &z, &ifmap_channel_number, &ifmap_format); + ei_printf("status = %d, ifmap shape = (%d, %d, %d), format = %d\n", + status, ifmap_height, ifmap_width, ifmap_channel_number, ifmap_format); + } + + // 5. get output shape + status = memx_get_ofmap_size(model_id, flow_id, &ofmap_height, &ofmap_width, &z, &ofmap_channel_number, &ofmap_format); + if(debug) { + ei_printf("status = %d, ofmap shape = (%d, %d, %d), format = %d\n", + status, ofmap_height, ofmap_width, ofmap_channel_number, ofmap_format); + } + if(memx_status_error(status)) { + return EI_IMPULSE_MEMRYX_ERROR; + } + + // 6. Prepare input and output buffers + float* ofmap = new float [ofmap_width * ofmap_height * ofmap_channel_number]; + +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + size_t mtx_size = impulse->dsp_blocks_size + impulse->learning_blocks_size; + ei::matrix_t* matrix = NULL; + + ei::matrix_t combined_matrix(1, impulse->nn_input_frame_size); + uint32_t buf_pos = 0; + + for (size_t i = 0; i < input_block_ids_size; i++) { + size_t cur_mtx = input_block_ids[i]; + + if (!find_mtx_by_idx(fmatrix, &matrix, cur_mtx, mtx_size)) { + ei_printf("ERR: Cannot find matrix with id %zu\n", cur_mtx); + return EI_IMPULSE_INVALID_SIZE; + } + + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + combined_matrix.buffer[buf_pos++] = matrix->buffer[ix]; + } + } + matrix = &combined_matrix; +#else + ei::matrix_t* matrix = fmatrix[0].matrix; +#endif + + float* ifmap = (float*)matrix->buffer; + + if(verbose_debug) { + for(int fidx = 0; fidx < (ofmap_width*ofmap_height); fidx++) { + ei_printf("%f\t", matrix->buffer[fidx]); + if(!(fidx % ofmap_width)) ei_printf("\n"); + } + } + + // TODO stream_ifmap only copies buffer to MX3 board, + // we need a different approach to measure latency + ctx_start_us = ei_read_timer_us(); + // 7. Stream inputs to device and start inference. + status = memx_stream_ifmap(model_id, 0, ifmap, timeout); + ctx_end_us = ei_read_timer_us(); + if(memx_status_error(status)) { + return EI_IMPULSE_MEMRYX_ERROR; + } + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + engine_info.str(""); + engine_info << "Inferences per second: " << (1000000 / result->timing.classification_us); + + // 6. Stream output results from device after inference + status = memx_stream_ofmap(model_id, 0, ofmap, timeout); + if(debug) { + ei_printf(" memx_stream_ofmap (status=%d)\n", status); + } + if(memx_status_error(status)) { + return EI_IMPULSE_MEMRYX_ERROR; + } + + // init softmax shape + std::vector output_shape = {static_cast(ofmap_height),static_cast(ofmap_width), + static_cast(ofmap_channel_number)}; + softmax_shape.BuildFrom(output_shape); + // dumy beta parameter for softmax purposes + dummy_params.beta = 1; + + // apply softmax, becuase MX3 does not support this operation + tflite::reference_ops::Softmax(dummy_params, softmax_shape, ofmap, softmax_shape, ofmap); + + // handle inference outputs + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + ei_printf("FOMO executed on Memryx\n"); + fill_result_struct_f32_fomo( + impulse, + block_config, + result, + ofmap, + impulse->fomo_output_size, + impulse->fomo_output_size); + break; + } + case EI_CLASSIFIER_LAST_LAYER_SSD: { + ei_printf("Mobilenet SSD is not implemented for Edge Impulse MemryX engine, please contact Edge Impulse Support\n"); + break; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else { + fill_result_struct_f32(impulse, result, ofmap, debug); + } + + delete ofmap; + // Device is closed only at EIM exit, therefore we do not use memx_close() + return EI_IMPULSE_OK; +} + +#elif (defined(EI_CLASSIFIER_USE_MEMRYX_SOFTWARE) && (EI_CLASSIFIER_USE_MEMRYX_SOFTWARE == 1)) +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* inputBlockIds, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + // init Python embedded interpreter (should be called once!) + static py::scoped_interpreter guard{}; + + // check if we've initialized the interpreter and device? + if (memryx_initialized == false) { + if(init_memryx(debug, impulse) == false) { + return EI_IMPULSE_MEMRYX_ERROR; + } + memryx_initialized = true; + } + + std::vector input_shape = {1, impulse->input_width, impulse->input_height, 3}; + py::array_t input_data(input_shape); // = zeroes(input_shape, 0); + + printf("impulse->w=%d h=%d\n", impulse->input_width, impulse->input_height); + + /* + * convert features data to the expected shape (4dim) + * For images RGB shape is (width, height, colors) + * For images BW shape is (width, height, 1) + * For Audio shape is (width, height, 1) - spectrogram + */ + auto r = input_data.mutable_unchecked<4>(); + + for (size_t i = 0; i < input_block_ids_size; i++) { + uint16_t cur_mtx = input_block_ids[i]; +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + ei::matrix_t* matrix = NULL; + + if (!find_mtx_by_idx(fmatrix, &matrix, cur_mtx, mtx_size)) { + ei_printf("ERR: Cannot find matrix with id %zu\n", cur_mtx); + return EI_IMPULSE_INVALID_SIZE; + } +#else + ei::matrix_t* matrix = fmatrix[0].matrix; +#endif + for (py::ssize_t x = 0; x < r.shape(1); x++) { + for (py::ssize_t y = 0; y < r.shape(2); y++) { + for(py::ssize_t z = 0; z < r.shape(3); z++) { + r(0, x, y, z) = (float)(fmatrix.buffer[x * r.shape(2) * r.shape(3) + y * r.shape(3) + z]); + } + } + } + } + + py::object runmodel = model.attr("run"); + // result from mx_sim is {np array, float, float} + py::tuple args = py::make_tuple(py::none(), 0.00, 0.00); + // run inference in sumualtor + printf("start inference\n"); + uint64_t ctx_start_us = ei_read_timer_us(); + args = runmodel("inputs"_a=input_data,"frames"_a=1); + uint64_t ctx_end_us = ei_read_timer_us(); + printf("end of inference\n"); + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + engine_info.str(""); + engine_info << "Inferences per second: " << (1000000 / result->timing.classification_us); + + py::array outputs = py::list(args[0]); + py::array_t potentials; + std::vector potentials_v; + + potentials = outputs.squeeze().cast>(); + + if (block_config->object_detection == false) { + potentials_v = outputs.squeeze().cast>(); + } + else { + auto q = potentials.unchecked<>(); + for (py::ssize_t x = 0; x < q.shape(0); x++) { + for (py::ssize_t y = 0; y < q.shape(1); y++) { + for(py::ssize_t z = 0; z < q.shape(2); z++) { + potentials_v.push_back(q(x, y, z)); + } + } + } + } + + if(debug) { + std::string ret_str = py::str(potentials).cast(); + ei_printf("Memryx raw output:\n%s\n", ret_str.c_str()); + } + + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + ei_printf("FOMO executed on Memryx\n"); + fill_result_struct_f32_fomo( + impulse, + block_config, + result, + potentials_v.data(), + impulse->fomo_output_size, + impulse->fomo_output_size); + break; + } + case EI_CLASSIFIER_LAST_LAYER_SSD: { + ei_printf("Mobilenet SSD executed on Memryx\n"); + break; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + impulse->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else { + fill_result_struct_f32(impulse, result, potentials_v.data(), debug); + } + + return EI_IMPULSE_OK; +} +#else +#error "Neither EI_CLASSIFIER_USE_MEMRYX_HARDWARE or EI_CLASSIFIER_USE_MEMRYX_SOFTWARE are defined or set to 1" +#endif // USE_HARDWARE + +#endif // EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_MEMRYX + +#endif /* EI_CLASSIFIER_INFERENCING_ENGINE_MEMRYX_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/onnx_tidl.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/onnx_tidl.h new file mode 100644 index 0000000..acc3e12 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/onnx_tidl.h @@ -0,0 +1,704 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_ONNX_TIDL_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_ONNX_TIDL_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_ONNX_TIDL) && (EI_CLASSIFIER_COMPILED != 1) + +#include "model-parameters/model_metadata.h" +#if EI_CLASSIFIER_HAS_MODEL_VARIABLES == 1 +#include "model-parameters/model_variables.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "itidl_rt.h" +#include +#include +#include + +#include +#include "edge-impulse-sdk/classifier/ei_aligned_malloc.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "edge-impulse-sdk/classifier/ei_model_types.h" + +#include "onnx-model/tidl-model.h" +#include "utils/model_header_utils.h" + +#define TI_PREPROC_DEFAULT_WIDTH 320 +#define TI_PREPROC_DEFAULT_HEIGHT 240 + +using namespace std; + +/** + * \brief returns time in micro sec + * @returns void + */ +double getUs(struct timeval t) +{ + return(t.tv_sec * 1000000 + t.tv_usec); +} + +/** + * \brief print tensor info + * \param session onnx session + * \param input_node_names input array node names + * @returns int status + */ +int printTensorInfo(Ort::Session *session, std::vector *input_node_names, std::vector *output_node_names) +{ + size_t num_input_nodes = (*session).GetInputCount(); + size_t num_output_nodes = (*session).GetOutputCount(); + Ort::TypeInfo type_info = (*session).GetInputTypeInfo(0); + auto tensor_info = type_info.GetTensorTypeAndShapeInfo(); + std::vector input_node_dims = tensor_info.GetShape(); + ei_printf("LOG_INFO: number of inputs:%d \n", num_input_nodes); + ei_printf("LOG_INFO: number of outputs: %d\n", num_output_nodes); + ei_printf("LOG_INFO: input(0) name: %s\n", (*input_node_names)[0]); + + Ort::TypeInfo type_info_out = (*session).GetOutputTypeInfo(0); + auto tensor_info_out = type_info_out.GetTensorTypeAndShapeInfo(); + std::vector output_node_dims = tensor_info_out.GetShape(); + /* iterate over all input nodes */ + for (int i = 0; i < num_input_nodes; i++) + { + /* print input node names */ + ei_printf("LOG_INFO: Input %d : name=%s\n", i, (*input_node_names)[i]); + + /* print input node types */ + Ort::TypeInfo type_info = (*session).GetInputTypeInfo(i); + auto tensor_info = type_info.GetTensorTypeAndShapeInfo(); + + ONNXTensorElementDataType type = tensor_info.GetElementType(); + ei_printf("LOG_INFO: Input %d : type=%d\n", i, type); + /* print input shapes/dims */ + input_node_dims = tensor_info.GetShape(); + ei_printf("LOG_INFO: Input %d : num_dims=%zu\n", i, input_node_dims.size()); + for (int j = 0; j < input_node_dims.size(); j++) + { + ei_printf("LOG_INFO: Input %d : dim %d=%jd\n", i, j, input_node_dims[j]); + } + } + if (num_input_nodes != 1) + { + ei_printf("LOG_INFO: supports only single input model \n"); + return EI_IMPULSE_ONNX_ERROR; + } + + for (int i = 0; i < num_output_nodes; i++) + { + /* print output node names */ + ei_printf("LOG_INFO: Output %d : name=%s\n", i, (*output_node_names)[i]); + + /* print output node types */ + Ort::TypeInfo type_info = (*session).GetOutputTypeInfo(i); + auto tensor_info = type_info.GetTensorTypeAndShapeInfo(); + + ONNXTensorElementDataType type = tensor_info.GetElementType(); + ei_printf("LOG_INFO: Output %d : type=%d\n", i, type); + /* print output shapes/dims */ + output_node_dims = tensor_info.GetShape(); + ei_printf("LOG_INFO: Output %d : num_dims=%zu\n", i, output_node_dims.size()); + for (int j = 0; j < output_node_dims.size(); j++) + { + ei_printf("LOG_INFO: Output %d : dim %d=%jd\n", i, j, output_node_dims[j]); + } + } + return EI_IMPULSE_OK; +} + +void * allocTensorMem(int size, int accel) +{ + void * ptr = NULL; + if (accel) + { + #ifdef DEVICE_AM62 + ei_printf("LOG_INFO: TIDL Delgate mode is not allowed on AM62 devices...\n"); + ei_printf("LOG_ERROR: Could not allocate memory for a Tensor of size %d \n ", size); + exit(0); + #else + ptr = TIDLRT_allocSharedMem(64, size); + #endif + } + else + { + ptr = malloc(size); + } + if (ptr == NULL) + { + ei_printf("LOG_ERROR: Could not allocate memory for a Tensor of size %d \n ", size); + exit(0); + } + return ptr; +} + +void freeTensorMem(void * ptr, int accel) +{ + if (accel) + { + #ifndef DEVICE_AM62 + TIDLRT_freeSharedMem(ptr); + #endif + } + else + { + free(ptr); + } +} + +/** + * Setup the ONNX runtime + * + * @param ctx_start_us Pointer to the start time + * @param input Pointer to input tensor + * @param output Pointer to output tensor + * @param micro_interpreter Pointer to interpreter (for non-compiled models) + * @param micro_tensor_arena Pointer to the arena that will be allocated + * + * @return EI_IMPULSE_OK if successful + */ +static EI_IMPULSE_ERROR inference_onnx_setup( + const ei_impulse_t *impulse, + uint64_t *ctx_start_us, + std::vector* input_tensors, + std::vector* output_tensors, + Ort::Session** session_ptr, + Ort::RunOptions** run_options_ptr, + Ort::IoBinding** binding_ptr) { + + static bool onnx_first_run = true; + // Nothing to do after first run + if (!onnx_first_run) { + return EI_IMPULSE_OK; + } + + std::string proj_artifacts_path = "/tmp/" + std::string(impulse->project_name) + "-" + std::to_string(impulse->project_id) + "-" + std::to_string(impulse->deploy_version); + + create_project_if_not_exists(proj_artifacts_path, model_h_files, model_h_files_len); + + std::string proj_model_path = proj_artifacts_path + "/model.onnx"; + + ei_printf("test onnx tidl: %s\n", __FUNCTION__); + #pragma message ( "test onnx tidl: run_nn_inference") + + /* Initialize enviroment, maintains thread pools and state info */ + Ort::Env env(ORT_LOGGING_LEVEL_WARNING, "test"); + /* Initialize session options */ + Ort::SessionOptions session_options; + //TODO: from where do we load number of threads? + session_options.SetIntraOpNumThreads(1); + + ei_printf("LOG_INFO: model accelerated \n"); + c_api_tidl_options *options = (c_api_tidl_options *)malloc(sizeof(c_api_tidl_options)); + OrtStatus *def_status = OrtSessionsOptionsSetDefault_Tidl(options); + ei_printf("LOG_INFO: artifacts: %s \n", proj_artifacts_path.c_str()); + strcpy(options->artifacts_folder, proj_artifacts_path.c_str()); + if(NULL == options){ + ei_printf("LOG_ERROR: faild to allocate c_api_tidl_options \n"); + return EI_IMPULSE_ONNX_ERROR; + } + OrtStatus *status = OrtSessionOptionsAppendExecutionProvider_Tidl(session_options, options); + + session_options.SetGraphOptimizationLevel(GraphOptimizationLevel::ORT_ENABLE_EXTENDED); + Ort::AllocatorWithDefaultOptions allocator; + + /* ORT Session */ + Ort::Session* session = new Ort::Session(env, proj_model_path.c_str(), session_options); + *session_ptr = session; + ei_printf("LOG_INFO: Loaded model %s\n", proj_model_path.c_str()); + + /* Input information */ + size_t num_input_nodes = session->GetInputCount(); + std::vector input_node_names(num_input_nodes); + Ort::TypeInfo type_info = session->GetInputTypeInfo(0); + auto tensor_info = type_info.GetTensorTypeAndShapeInfo(); + std::vector input_node_dims = tensor_info.GetShape(); + ONNXTensorElementDataType input_tensor_type = tensor_info.GetElementType(); + + /* output information */ + size_t num_output_nodes = session->GetOutputCount(); + std::vector output_node_names(num_output_nodes); + for (int i = 0; i < num_output_nodes; i++) + { + output_node_names[i] = session->GetOutputName(i, allocator); + } + for (int i = 0; i < num_input_nodes; i++) + { + input_node_names[i] = session->GetInputName(i, allocator); + } + + type_info = session->GetOutputTypeInfo(0); + auto output_tensor_info = type_info.GetTensorTypeAndShapeInfo(); + std::vector output_node_dims = output_tensor_info.GetShape(); + size_t output_tensor_size = output_node_dims[1]; + + if (EI_IMPULSE_ONNX_ERROR == printTensorInfo(session, &input_node_names, &output_node_names)) { + ei_printf("LOG_ERROR: print tensor information failed!\n"); + return EI_IMPULSE_ONNX_ERROR; + } + + ssize_t input_tensor_size_bytes; + /* simplify ... using known dim values to calculate size */ + size_t input_tensor_size = impulse->nn_input_frame_size; + void *inData; + if (input_tensor_type == ONNX_TENSOR_ELEMENT_DATA_TYPE_FLOAT) + { + input_tensor_size_bytes = input_tensor_size * sizeof(float); + inData = allocTensorMem(input_tensor_size_bytes, true); + } + else if (input_tensor_type == ONNX_TENSOR_ELEMENT_DATA_TYPE_UINT8) + { + input_tensor_size_bytes = input_tensor_size * sizeof(uint8_t); + inData = allocTensorMem(input_tensor_size_bytes, true); + } + else + { + ei_printf("LOG_ERROR: indata type not supported yet \n "); + return EI_IMPULSE_ONNX_ERROR; + } + auto memory_info = Ort::MemoryInfo::CreateCpu(OrtArenaAllocator, OrtMemTypeDefault); + + Ort::Value input_tensor = Ort::Value::CreateTensor(memory_info, inData, input_tensor_size_bytes, input_node_dims.data(), 4, input_tensor_type); + input_tensors->push_back(std::move(input_tensor)); + + Ort::RunOptions* run_options = new Ort::RunOptions(); + *run_options_ptr = run_options; + run_options->SetRunLogVerbosityLevel(2); + auto output_tensors_warm_up = session->Run(*run_options, input_node_names.data(), input_tensors->data(), 1, output_node_names.data(), num_output_nodes); + + //void *outData = allocTensorMem(output_tensor_size * sizeof(float), true); + Ort::IoBinding* binding = new Ort::IoBinding(*session); + *binding_ptr = binding; + binding->BindInput(input_node_names[0], (*input_tensors)[0]); + + for(int idx=0; idx < num_output_nodes; idx++) + { + auto node_dims = output_tensors_warm_up[idx].GetTypeInfo().GetTensorTypeAndShapeInfo().GetShape(); + size_t tensor_size = 1; + for(int j = node_dims.size()-1; j >= 0; j--) + { + tensor_size *= node_dims[j]; + } + ONNXTensorElementDataType tensor_type = output_tensors_warm_up[idx].GetTypeInfo().GetTensorTypeAndShapeInfo().GetElementType(); + if(tensor_type == ONNX_TENSOR_ELEMENT_DATA_TYPE_FLOAT) + { + tensor_size *= sizeof(float); + } + else if(tensor_type == ONNX_TENSOR_ELEMENT_DATA_TYPE_UINT8) + { + tensor_size *= sizeof(uint8_t); + } + else if(tensor_type == ONNX_TENSOR_ELEMENT_DATA_TYPE_INT64) + { + tensor_size *= sizeof(int64_t); + } + else + { + ei_printf("LOG_ERROR: Un Supported output tensor_type\n"); + return EI_IMPULSE_ONNX_ERROR; + } + + void * outData = allocTensorMem(tensor_size, true); + auto output_tensor = Ort::Value::CreateTensor(memory_info, (void *)outData, tensor_size, node_dims.data(), node_dims.size(),tensor_type); + output_tensors->push_back(std::move(output_tensor)); + binding->BindOutput(output_node_names[idx], (*output_tensors)[idx]); + } + + onnx_first_run = false; + + return EI_IMPULSE_OK; +} + +/** + * Run ONNX model + * + * @param ctx_start_us Start time of the setup function (see above) + * @param output_tensors Output tensors + * @param session ONNX session + * @param run_options ONNX run options + * @param binding IO bindings + * @param debug Whether to print debug info + * + * @return EI_IMPULSE_OK if successful + */ +static EI_IMPULSE_ERROR inference_onnx_run(const ei_impulse_t *impulse, + void *config_ptr, + uint64_t ctx_start_us, + std::vector* input_tensors, + std::vector* output_tensors, + Ort::Session* session, + Ort::RunOptions* run_options, + Ort::IoBinding* binding, + ei_impulse_result_t *result, + bool debug) { + + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + session->Run(*run_options, *binding); + + uint64_t ctx_end_us = ei_read_timer_us(); + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + ONNXTensorElementDataType output_tensor_type = (*output_tensors).at(0).GetTypeInfo().GetTensorTypeAndShapeInfo().GetElementType(); + void *out_data = output_tensors->front().GetTensorMutableData(); + + // get output features count from model + auto node_dims = (*output_tensors).at(0).GetTypeInfo().GetTensorTypeAndShapeInfo().GetShape(); + size_t output_tensor_features_count = 1; + for(int j = node_dims.size()-1; j >= 0; j--) + { + output_tensor_features_count *= node_dims[j]; + } + + // Read the predicted y value from the model's output tensor + if (debug) { + ei_printf("Predictions (time: %d ms.):\n", result->timing.classification); + } + + EI_IMPULSE_ERROR fill_res = EI_IMPULSE_OK; + + // NOTE: for now only yolox object detection supported + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_YOLOX: { + if (block_config->quantized == 1) { + ei_printf("ERR: YOLOX does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + if (debug) { + ei_printf("YOLOX OUTPUT (%d ms.): ", result->timing.classification); + for (size_t ix = 0; ix < output_tensor_features_count; ix++) { + ei_printf_float(((float*)out_data)[ix]); + ei_printf(" "); + } + ei_printf("\n"); + } + fill_res = fill_result_struct_f32_yolox_detect( + impulse, + block_config, + result, + (float*)out_data, + output_tensor_features_count); + } + break; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + break; + } + } + } + else { +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + + switch (output_tensor_type) { + case ONNX_TENSOR_ELEMENT_DATA_TYPE_UINT8: { + fill_res = fill_result_struct_i8(impulse, result, (int8_t*)out_data, impulse->tflite_output_zeropoint, impulse->tflite_output_scale, debug); + break; + } + case ONNX_TENSOR_ELEMENT_DATA_TYPE_INT8: { + fill_res = fill_result_struct_i8(impulse, result, (int8_t*)out_data, impulse->tflite_output_zeropoint, impulse->tflite_output_scale, debug); + break; + } + default: { + ei_printf("ERR: Cannot handle output type (%d)\n", output_tensor_type); + return EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL; + } + } + +#else + switch (output_tensor_type) { + case ONNX_TENSOR_ELEMENT_DATA_TYPE_FLOAT: { + fill_res = fill_result_struct_f32(impulse, result, (float*)out_data, debug); + break; + } + default: { + ei_printf("ERR: Cannot handle output type (%d)\n", output_tensor_type); + return EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL; + } + } +#endif + } + + ///* freeing shared mem*/ + //for (size_t i = 0; i < output_tensors->size(); i++) + //{ + // void *ptr = (*output_tensors)[i].GetTensorMutableData(); + // freeTensorMem(ptr, true); + //} + //for (size_t i = 0; i < input_tensors->size(); i++) + //{ + // void *ptr = (*input_tensors)[i].GetTensorMutableData(); + // freeTensorMem(ptr, true); + //} + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + return EI_IMPULSE_OK; +} + +/** + * @brief Do neural network inferencing over the processed feature matrix + * + * @param fmatrix Processed matrix >> features [array of features] this is input + * @param result Output classifier results >> output + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *afmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + static std::vector input_tensors; + static std::vector output_tensors; + static Ort::Session* session; + static Ort::RunOptions* run_options; + static Ort::IoBinding* binding; + uint64_t ctx_start_us; + + ei_printf("test onnx tidl: %s\n", __FUNCTION__); + #pragma message ( "test onnx tidl: run_nn_inference") + + EI_IMPULSE_ERROR init_res = inference_onnx_setup(impulse, + &ctx_start_us, + &input_tensors, + &output_tensors, + &session, + &run_options, + &binding); + + if (init_res != EI_IMPULSE_OK || session == NULL || run_options == NULL || + binding == NULL) { + ei_printf("LOG_ERROR: ONNX inference setup failed!\n"); + return EI_IMPULSE_ONNX_ERROR; + } + + uint64_t dsp_chw_start_us; + dsp_chw_start_us = ei_read_timer_us(); + + /* + ** Convert to CHW from HWC + */ + // features matrix maps around the input tensor to not allocate any memory + float *input_buffer = input_tensors.front().GetTensorMutableData(); + ei::matrix_t fmatrix(1, impulse->nn_input_frame_size, input_buffer); + + ei_dsp_config_image_t *config = (ei_dsp_config_image_t *)impulse->dsp_blocks[0].config; + + size_t channels = strcmp(config->channels, "Grayscale") == 0 ? 1 : 3; + size_t height = impulse->input_height; + size_t width = impulse->input_width; + + ei::matrix_t* matrix = afmatrix[0].matrix; + + int dest_ix = 0; + for (size_t c=0; c < channels; c++) { + for (size_t h=0; h < height; h++) { + for (size_t w=0; w < width; w++) { + uint32_t src_ix = channels * width * h + w*channels + c; + fmatrix.buffer[dest_ix++] = matrix->buffer[src_ix]; + } + } + } + + uint64_t dsp_chw_end_us = ei_read_timer_us(); + result->timing.dsp_us += dsp_chw_end_us - dsp_chw_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (debug) { + ei_printf("After Features (%ld us.): ", result->timing.dsp_us); + for (size_t ix = 0; ix < fmatrix.cols; ix++) { + ei_printf_float(fmatrix.buffer[ix]); + ei_printf(" "); + } + ei_printf("\n"); + } + + ctx_start_us = ei_read_timer_us(); + EI_IMPULSE_ERROR run_res = inference_onnx_run(impulse, + config_ptr, + ctx_start_us, + &input_tensors, + &output_tensors, + session, + run_options, + binding, + result, debug); + + if (run_res != EI_IMPULSE_OK) { + return run_res; + } + + return EI_IMPULSE_OK; +} + +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 +/** + * Special function to run the classifier on images, only works on TFLite models (either interpreter or EON or for tensaiflow) + * that allocates a lot less memory by quantizing in place. This only works if 'can_run_classifier_image_quantized' + * returns EI_IMPULSE_OK. + */ +EI_IMPULSE_ERROR run_nn_inference_image_quantized( + const ei_impulse_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + static std::vector input_tensors; + static std::vector output_tensors; + static Ort::Session* session; + static Ort::RunOptions* run_options; + static Ort::IoBinding* binding; + uint64_t ctx_start_us; + + ei_printf("test onnx tidl: %s\n", __FUNCTION__); + #pragma message ( "test onnx tidl: run_nn_inference_image_quantized") + + EI_IMPULSE_ERROR init_res = inference_onnx_setup(impulse, + &ctx_start_us, + &input_tensors, &output_tensors, + &session, + &run_options, + &binding); + + if (init_res != EI_IMPULSE_OK || session == NULL || run_options == NULL || + binding == NULL) { + ei_printf("LOG_ERROR: ONNX inference setup failed!\n"); + return EI_IMPULSE_ONNX_ERROR; + } + + ONNXTensorElementDataType input_tensor_type = input_tensors.at(0).GetTypeInfo().GetTensorTypeAndShapeInfo().GetElementType(); + if (input_tensor_type != ONNX_TENSOR_ELEMENT_DATA_TYPE_UINT8 && + input_tensor_type != ONNX_TENSOR_ELEMENT_DATA_TYPE_INT8) { + return EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES; + } + + uint64_t dsp_start_us = ei_read_timer_us(); + + ei::matrix_i8_t a_features_matrix(1, impulse->nn_input_frame_size); + + // run DSP process and quantize automatically + int ret = extract_image_features_quantized(impulse, signal, &a_features_matrix, impulse->dsp_blocks[0].config, impulse->frequency, + impulse->learning_blocks[0].image_scaling); + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to run DSP process (%d)\n", ret); + return EI_IMPULSE_DSP_ERROR; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + if (debug) { + ei_printf("Before Features: "); + for (size_t ix = 0; ix < a_features_matrix.cols; ix++) { + ei_printf("%d", (uint8_t)a_features_matrix.buffer[ix]); + ei_printf(" "); + } + ei_printf("\n"); + } + + /* + ** Convert to CHW from HWC + */ + // features matrix maps around the input tensor to not allocate any memory + uint8_t *input_buffer = input_tensors.front().GetTensorMutableData(); + ei::matrix_i8_t features_matrix(1, impulse->nn_input_frame_size, (int8_t*) input_buffer); + + ei_dsp_config_image_t *config = (ei_dsp_config_image_t *)impulse->dsp_blocks[0].config; + + size_t channels = strcmp(config->channels, "Grayscale") == 0 ? 1 : 3; + size_t height = impulse->input_height; + size_t width = impulse->input_width; + + int dest_ix = 0; + for (size_t c=0; c < channels; c++) { + for (size_t h=0; h < height; h++) { + for (size_t w=0; w < width; w++) { + uint32_t src_ix = channels * width * h + w*channels + c; + features_matrix.buffer[dest_ix++] = a_features_matrix.buffer[src_ix]; + } + } + } + + if (debug) { + ei_printf("After Features: "); + for (size_t ix = 0; ix < features_matrix.cols; ix++) { + ei_printf("%d", (uint8_t)features_matrix.buffer[ix]); + ei_printf(" "); + } + ei_printf("\n"); + } + + result->timing.dsp_us = ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (debug) { + ei_printf("Features (%d ms.): ", result->timing.dsp); + for (size_t ix = 0; ix < features_matrix.cols; ix++) { + // expects scale of (1/255) and zeropoint of 0 + ei_printf_float(static_cast(((uint8_t)features_matrix.buffer[ix] - impulse->tflite_input_zeropoint) * impulse->tflite_input_scale)); + ei_printf(" "); + } + ei_printf("\n"); + } + + ctx_start_us = ei_read_timer_us(); + EI_IMPULSE_ERROR run_res = inference_onnx_run(impulse, + config_ptr, + ctx_start_us, + &input_tensors, + &output_tensors, + session, + run_options, + binding, + result, debug); + + if (run_res != EI_IMPULSE_OK) { + return run_res; + } + + return EI_IMPULSE_OK; +} +#endif // EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + +#endif // #if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_ONNX_TIDL) && (EI_CLASSIFIER_COMPILED != 1) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_ONNX_TIDL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tensaiflow.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tensaiflow.h new file mode 100644 index 0000000..dd6caf6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tensaiflow.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_TENSAILFOW_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_TENSAILFOW_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSAIFLOW) + +#include "model-parameters/model_metadata.h" +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "edge-impulse-sdk/classifier/ei_run_dsp.h" + +#include "mcu.h" + +extern "C" void infer(const void *impulse_arg, uint32_t* time, uint32_t* cycles); +int8_t *processed_features; + +#ifdef EI_CLASSIFIER_NN_OUTPUT_COUNT +int8_t infer_result[EI_CLASSIFIER_NN_OUTPUT_COUNT]; +#else +int8_t infer_result[EI_CLASSIFIER_LABEL_COUNT]; +#endif + +extern "C" void get_data(const void *impulse_arg, int8_t *in_buf_0, uint16_t in_buf_0_dim_0, uint16_t in_buf_0_dim_1, uint16_t in_buf_0_dim_2) +{ + ei_impulse_t *impulse = (ei_impulse_t *) impulse_arg; + + if ((impulse->sensor == EI_CLASSIFIER_SENSOR_CAMERA) && + ((impulse->dsp_blocks_size == 1) || + (impulse->dsp_blocks[0].extract_fn == extract_image_features))) { + + memcpy(in_buf_0, processed_features, impulse->nn_input_frame_size); + } +} + +extern "C" void post_process(const void *impulse_arg, int8_t *out_buf_0, int8_t *out_buf_1) +{ + ei_impulse_t *impulse = (ei_impulse_t *) impulse_arg; + + #ifdef EI_CLASSIFIER_NN_OUTPUT_COUNT + memcpy(infer_result, out_buf_0, impulse->tflite_output_features_count); + #else + memcpy(infer_result, out_buf_0, impulse->label_count); + #endif +} + +/** + * @brief Do neural network inferencing over the processed feature matrix + * + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + ei_config_tensaiflow_graph_t *graph_config = (ei_config_tensaiflow_graph_t*)block_config->graph_config; + + if (block_config->object_detection) { + ei_printf("ERR: Object detection models are not supported with TensaiFlow\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + + uint64_t ctx_start_us = ei_read_timer_us(); + uint32_t time, cycles; + + /* Run tensaiflow inference */ + infer((const void *)impulse, &time, &cycles); + + // Inference results returned by post_process() and copied into infer_results + + result->timing.classification_us = ei_read_timer_us() - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + for (uint32_t ix = 0; ix < impulse->label_count; ix++) { + float value; + // Dequantize the output if it is int8 + value = static_cast(infer_result[ix] - graph_config->output_zeropoint) * + graph_config->output_scale; + + if (debug) { + ei_printf("%s:\t", impulse->categories[ix]); + ei_printf_float(value); + ei_printf("\n"); + } + result->classification[ix].label = impulse->categories[ix]; + result->classification[ix].value = value; + } + + return EI_IMPULSE_OK; + +} + +/** + * Special function to run the classifier on images, only works on TFLite models (either interpreter or EON or for tensaiflow) + * that allocates a lot less memory by quantizing in place. This only works if 'can_run_classifier_image_quantized' + * returns EI_IMPULSE_OK. + */ +EI_IMPULSE_ERROR run_nn_inference_image_quantized( + const ei_impulse_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + ei_config_tensaiflow_graph_t *graph_config = (ei_config_tensaiflow_graph_t*)block_config->graph_config; + + uint64_t ctx_start_us; + uint64_t dsp_start_us = ei_read_timer_us(); + + ei::matrix_i8_t features_matrix(1, impulse->nn_input_frame_size); + processed_features = (int8_t *) features_matrix.buffer; + + // run DSP process and quantize automatically + int ret = extract_image_features_quantized( + signal, + &features_matrix, + impulse->dsp_blocks[0].config, + graph_config->input_scale, + graph_config->input_zeropoint, + impulse->frequency, + impulse->learning_blocks[0].image_scaling); + + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to run DSP process (%d)\n", ret); + return EI_IMPULSE_DSP_ERROR; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + result->timing.dsp_us = ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (debug) { + ei_printf("Features (%d ms.): ", result->timing.dsp); + for (size_t ix = 0; ix < features_matrix.cols; ix++) { + ei_printf_float((features_matrix.buffer[ix] - graph_config->input_zeropoint) * graph_config->input_scale); + ei_printf(" "); + } + ei_printf("\n"); + } + + uint32_t time, cycles; + ctx_start_us = ei_read_timer_us(); + + /* Run tensaiflow inference */ + infer((const void *)impulse, &time, &cycles); + + // Inference results returned by post_process() and copied into infer_results + + EI_IMPULSE_ERROR fill_res = EI_IMPULSE_OK; + + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + if (block_config->quantized == 1) { + fill_res = fill_result_struct_i8_fomo( + impulse, + block_config, + result, + infer_result, + graph_config->output_zeropoint, + graph_config->output_scale, + impulse->fomo_output_size, + impulse->fomo_output_size); + } + else { + ei_printf("ERR: TensaiFlow does not support float32 inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + break; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else { + if (block_config->quantized == 1) { + fill_res = fill_result_struct_i8( + impulse, + result, + infer_result, + graph_config->output_zeropoint, + graph_config->output_scale, + debug); + } + else { + ei_printf("ERR: TensaiFlow does not support float32 inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + result->timing.classification_us = ei_read_timer_us() - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + return EI_IMPULSE_OK; + +} + +#endif // #if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSAILFOW) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_TENSAILFOW_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tensorrt.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tensorrt.h new file mode 100644 index 0000000..d9fbb29 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tensorrt.h @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_TENSORRT_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_TENSORRT_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSORRT) + +#include "model-parameters/model_metadata.h" + +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" + +#include +#include +#include +#include +#include +#include +#include "tflite/linux-jetson-nano/libeitrt.h" + +#if __APPLE__ +#include +#else +#include +#endif + +EiTrt *ei_trt_handle = NULL; + +inline bool file_exists(char *model_file_name) +{ + if (FILE *file = fopen(model_file_name, "r")) { + fclose(file); + return true; + } + else { + return false; + } +} + +/** + * @brief Do neural network inferencing over the processed feature matrix + * + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + ei_config_tflite_graph_t *graph_config = (ei_config_tflite_graph_t*)block_config->graph_config; + + #if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + #error "TensorRT requires an unquantized network" + #endif + + static char current_exe_path[PATH_MAX] = { 0 }; + +#if __APPLE__ + uint32_t len = PATH_MAX; + if (_NSGetExecutablePath(current_exe_path, &len) != 0) { + current_exe_path[0] = '\0'; // buffer too small + } + else { + // resolve symlinks, ., .. if possible + char *canonical_path = realpath(current_exe_path, NULL); + if (canonical_path != NULL) + { + strncpy(current_exe_path, canonical_path, len); + free(canonical_path); + } + } +#else + int readlink_res = readlink("/proc/self/exe", current_exe_path, PATH_MAX); + if (readlink_res < 0) { + printf("readlink_res = %d\n", readlink_res); + current_exe_path[0] = '\0'; // failed to find location + } +#endif + + static char model_file_name[PATH_MAX]; + + if (strlen(current_exe_path) == 0) { + // could not determine current exe path, use /tmp for the engine file + snprintf( + model_file_name, + PATH_MAX, + "/tmp/ei-%d-%d.engine", + impulse->project_id, + impulse->deploy_version); + } + else { + std::filesystem::path p(current_exe_path); + snprintf( + model_file_name, + PATH_MAX, + "%s/%s-project%d-v%d.engine", + p.parent_path().c_str(), + p.stem().c_str(), + impulse->project_id, + impulse->deploy_version); + } + + static bool first_run = true; + + if (first_run) { + + bool fexists = file_exists(model_file_name); + if (!fexists) { + ei_printf("INFO: Model file '%s' does not exist, creating...\n", model_file_name); + + FILE *file = fopen(model_file_name, "w"); + if (!file) { + ei_printf("ERR: TensorRT init failed to open '%s'\n", model_file_name); + return EI_IMPULSE_TENSORRT_INIT_FAILED; + } + + if (fwrite(graph_config->model, graph_config->model_size, 1, file) != 1) { + ei_printf("ERR: TensorRT init fwrite failed.\n"); + return EI_IMPULSE_TENSORRT_INIT_FAILED; + } + + if (fclose(file) != 0) { + ei_printf("ERR: TensorRT init fclose failed.\n"); + return EI_IMPULSE_TENSORRT_INIT_FAILED; + } + } + + first_run = false; + } + + uint32_t out_data_size = 0; + + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_TAO_SSD: + case EI_CLASSIFIER_LAST_LAYER_TAO_RETINANET: + case EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3: + case EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4: + case EI_CLASSIFIER_LAST_LAYER_FOMO: + case EI_CLASSIFIER_LAST_LAYER_YOLOV5: + case EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI: { + out_data_size = impulse->tflite_output_features_count; + break; + } + default: { + ei_printf( + "ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else { + out_data_size = impulse->label_count; + } + + float *out_data = (float*)ei_malloc(out_data_size * sizeof(float)); + if (out_data == nullptr) { + ei_printf("ERR: Cannot allocate memory for output data \n"); + } + + // lazy initialize tensorRT context + if (ei_trt_handle == nullptr) { + ei_trt_handle = libeitrt::create_EiTrt(model_file_name, debug); + } + +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + size_t mtx_size = impulse->dsp_blocks_size + impulse->learning_blocks_size; + ei::matrix_t* matrix = NULL; + + ei::matrix_t combined_matrix(1, impulse->nn_input_frame_size); + uint32_t buf_pos = 0; + + for (size_t i = 0; i < input_block_ids_size; i++) { + size_t cur_mtx = input_block_ids[i]; + + if (!find_mtx_by_idx(fmatrix, &matrix, cur_mtx, mtx_size)) { + ei_printf("ERR: Cannot find matrix with id %zu\n", cur_mtx); + return EI_IMPULSE_INVALID_SIZE; + } + + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + combined_matrix.buffer[buf_pos++] = matrix->buffer[ix]; + } + } + matrix = &combined_matrix; +#else + ei::matrix_t* matrix = fmatrix[0].matrix; +#endif + + uint64_t ctx_start_us = ei_read_timer_us(); + + libeitrt::infer(ei_trt_handle, matrix->buffer, out_data, out_data_size); + + uint64_t ctx_end_us = ei_read_timer_us(); + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + EI_IMPULSE_ERROR fill_res = EI_IMPULSE_OK; + + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + fill_res = fill_result_struct_f32_fomo( + impulse, + block_config, + result, + out_data, + impulse->fomo_output_size, + impulse->fomo_output_size); + break; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOV5: + case EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI: { + int version = block_config->object_detection_last_layer == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI ? + 5 : 6; + fill_res = fill_result_struct_f32_yolov5( + impulse, + block_config, + result, + version, + out_data, + impulse->tflite_output_features_count); + break; + } + case EI_CLASSIFIER_LAST_LAYER_TAO_SSD: + case EI_CLASSIFIER_LAST_LAYER_TAO_RETINANET: { + fill_res = fill_result_struct_f32_tao_decode_detections( + impulse, + block_config, + result, + out_data, + impulse->tflite_output_features_count, + debug); + break; + } + case EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3: + fill_res = fill_result_struct_f32_tao_yolov3( + impulse, + block_config, + result, + out_data, + impulse->tflite_output_features_count, + debug); + break; + case EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4: { + fill_res = fill_result_struct_f32_tao_yolov4( + impulse, + block_config, + result, + out_data, + impulse->tflite_output_features_count, + debug); + break; + } + default: { + ei_printf( + "ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else { + fill_res = fill_result_struct_f32(impulse, result, out_data, debug); + } + + ei_free(out_data); + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + return EI_IMPULSE_OK; +} + +/** + * Special function to run the classifier on images for quantized models + * that allocates a lot less memory by quantizing in place. This only works if 'can_run_classifier_image_quantized' + * returns EI_IMPULSE_OK. + */ +EI_IMPULSE_ERROR run_nn_inference_image_quantized( + const ei_impulse_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; +} + +#endif // #if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TENSORRT) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_TENSORRT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_eon.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_eon.h new file mode 100644 index 0000000..2eacaa9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_eon.h @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_EON_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_EON_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) && (EI_CLASSIFIER_COMPILED == 1) + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/classifier/ei_aligned_malloc.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/classifier/inferencing_engines/tflite_helper.h" +#include "edge-impulse-sdk/classifier/ei_run_dsp.h" + +/** + * Setup the TFLite runtime + * + * @param ctx_start_us Pointer to the start time + * @param input Pointer to input tensor + * @param output Pointer to output tensor + * @param micro_tensor_arena Pointer to the arena that will be allocated + * + * @return EI_IMPULSE_OK if successful + */ +static EI_IMPULSE_ERROR inference_tflite_setup( + ei_learning_block_config_tflite_graph_t *block_config, + uint64_t *ctx_start_us, + TfLiteTensor* input, + TfLiteTensor* output, + TfLiteTensor* output_labels, + TfLiteTensor* output_scores, + ei_unique_ptr_t& p_tensor_arena) { + + ei_config_tflite_eon_graph_t *graph_config = (ei_config_tflite_eon_graph_t*)block_config->graph_config; + + *ctx_start_us = ei_read_timer_us(); + + TfLiteStatus init_status = graph_config->model_init(ei_aligned_calloc); + if (init_status != kTfLiteOk) { + ei_printf("Failed to initialize the model (error code %d)\n", init_status); + return EI_IMPULSE_TFLITE_ARENA_ALLOC_FAILED; + } + + TfLiteStatus status; + + status = graph_config->model_input(0, input); + if (status != kTfLiteOk) { + return EI_IMPULSE_TFLITE_ERROR; + } + status = graph_config->model_output(block_config->output_data_tensor, output); + if (status != kTfLiteOk) { + return EI_IMPULSE_TFLITE_ERROR; + } + + if (block_config->object_detection_last_layer == EI_CLASSIFIER_LAST_LAYER_SSD) { + status = graph_config->model_output(block_config->output_score_tensor, output_scores); + if (status != kTfLiteOk) { + return EI_IMPULSE_TFLITE_ERROR; + } + status = graph_config->model_output(block_config->output_labels_tensor, output_labels); + if (status != kTfLiteOk) { + return EI_IMPULSE_TFLITE_ERROR; + } + } + + return EI_IMPULSE_OK; +} + +/** + * Run TFLite model + * + * @param ctx_start_us Start time of the setup function (see above) + * @param output Output tensor + * @param interpreter TFLite interpreter (non-compiled models) + * @param tensor_arena Allocated arena (will be freed) + * @param result Struct for results + * @param debug Whether to print debug info + * + * @return EI_IMPULSE_OK if successful + */ +static EI_IMPULSE_ERROR inference_tflite_run( + const ei_impulse_t *impulse, + ei_learning_block_config_tflite_graph_t *block_config, + uint64_t ctx_start_us, + TfLiteTensor* output, + TfLiteTensor* labels_tensor, + TfLiteTensor* scores_tensor, + uint8_t* tensor_arena, + ei_impulse_result_t *result, + bool debug) { + + ei_config_tflite_eon_graph_t *graph_config = (ei_config_tflite_eon_graph_t*)block_config->graph_config; + + if (graph_config->model_invoke() != kTfLiteOk) { + return EI_IMPULSE_TFLITE_ERROR; + } + + uint64_t ctx_end_us = ei_read_timer_us(); + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + // Read the predicted y value from the model's output tensor + if (debug) { + ei_printf("Predictions (time: %d ms.):\n", result->timing.classification); + } + + EI_IMPULSE_ERROR fill_res = fill_result_struct_from_output_tensor_tflite( + impulse, block_config, output, labels_tensor, scores_tensor, result, debug); + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + return EI_IMPULSE_OK; +} + +/** + * @brief Do neural network inferencing over a signal (from the DSP) + * + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference_from_dsp( + ei_learning_block_config_tflite_graph_t *block_config, + signal_t *signal, + matrix_t *output_matrix) +{ + TfLiteTensor input; + TfLiteTensor output; + TfLiteTensor output_scores; + TfLiteTensor output_labels; + uint64_t ctx_start_us = ei_read_timer_us(); + ei_unique_ptr_t p_tensor_arena(nullptr, ei_aligned_free); + ei_config_tflite_eon_graph_t *graph_config = (ei_config_tflite_eon_graph_t*)block_config->graph_config; + + EI_IMPULSE_ERROR init_res = inference_tflite_setup( + block_config, + &ctx_start_us, + &input, + &output, + &output_labels, + &output_scores, + p_tensor_arena); + + if (init_res != EI_IMPULSE_OK) { + return init_res; + } + + auto input_res = fill_input_tensor_from_signal(signal, &input); + if (input_res != EI_IMPULSE_OK) { + return input_res; + } + + // invoke the model + if (graph_config->model_invoke() != kTfLiteOk) { + return EI_IMPULSE_TFLITE_ERROR; + } + + auto output_res = fill_output_matrix_from_tensor(&output, output_matrix); + if (output_res != EI_IMPULSE_OK) { + return output_res; + } + + if (graph_config->model_reset(ei_aligned_free) != kTfLiteOk) { + return EI_IMPULSE_TFLITE_ERROR; + } + + return EI_IMPULSE_OK; +} + +/** + * @brief Do neural network inferencing over a feature matrix + * + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + ei_config_tflite_eon_graph_t *graph_config = (ei_config_tflite_eon_graph_t*)block_config->graph_config; + + TfLiteTensor input; + TfLiteTensor output; + TfLiteTensor output_scores; + TfLiteTensor output_labels; + + uint64_t ctx_start_us = ei_read_timer_us(); + ei_unique_ptr_t p_tensor_arena(nullptr, ei_aligned_free); + + EI_IMPULSE_ERROR init_res = inference_tflite_setup( + block_config, + &ctx_start_us, + &input, + &output, + &output_labels, + &output_scores, + p_tensor_arena); + + if (init_res != EI_IMPULSE_OK) { + return init_res; + } + + uint8_t* tensor_arena = static_cast(p_tensor_arena.get()); + + size_t mtx_size = impulse->dsp_blocks_size + impulse->learning_blocks_size; + auto input_res = fill_input_tensor_from_matrix(fmatrix, &input, input_block_ids, input_block_ids_size, mtx_size); + if (input_res != EI_IMPULSE_OK) { + return input_res; + } + + EI_IMPULSE_ERROR run_res = inference_tflite_run( + impulse, + block_config, + ctx_start_us, + &output, + &output_labels, + &output_scores, + tensor_arena, result, debug); + + if (result->copy_output) { + auto output_res = fill_output_matrix_from_tensor(&output, fmatrix[impulse->dsp_blocks_size + learn_block_index].matrix); + if (output_res != EI_IMPULSE_OK) { + return output_res; + } + } + + graph_config->model_reset(ei_aligned_free); + + if (run_res != EI_IMPULSE_OK) { + return run_res; + } + + return EI_IMPULSE_OK; +} + +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 +/** + * Special function to run the classifier on images, only works on TFLite models (either interpreter or EON or for tensaiflow) + * that allocates a lot less memory by quantizing in place. This only works if 'can_run_classifier_image_quantized' + * returns EI_IMPULSE_OK. + */ +EI_IMPULSE_ERROR run_nn_inference_image_quantized( + const ei_impulse_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) { + + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + ei_config_tflite_eon_graph_t *graph_config = (ei_config_tflite_eon_graph_t*)block_config->graph_config; + + memset(result, 0, sizeof(ei_impulse_result_t)); + + uint64_t ctx_start_us; + TfLiteTensor input; + TfLiteTensor output; + TfLiteTensor output_scores; + TfLiteTensor output_labels; + + ei_unique_ptr_t p_tensor_arena(nullptr, ei_aligned_free); + + EI_IMPULSE_ERROR init_res = inference_tflite_setup( + block_config, + &ctx_start_us, + &input, &output, + &output_labels, + &output_scores, + p_tensor_arena); + + if (init_res != EI_IMPULSE_OK) { + return init_res; + } + + if (input.type != TfLiteType::kTfLiteInt8 && input.type != TfLiteType::kTfLiteUInt8) { + return EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES; + } + + uint64_t dsp_start_us = ei_read_timer_us(); + + // features matrix maps around the input tensor to not allocate any memory + ei::matrix_i8_t features_matrix(1, impulse->nn_input_frame_size, input.data.int8); + + // run DSP process and quantize automatically + int ret = extract_image_features_quantized(signal, &features_matrix, impulse->dsp_blocks[0].config, input.params.scale, input.params.zero_point, + impulse->frequency, impulse->learning_blocks[0].image_scaling); + + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to run DSP process (%d)\n", ret); + return EI_IMPULSE_DSP_ERROR; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + result->timing.dsp_us = ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (debug) { + ei_printf("Features (%d ms.): ", result->timing.dsp); + for (size_t ix = 0; ix < features_matrix.cols; ix++) { + ei_printf_float((features_matrix.buffer[ix] - input.params.zero_point) * input.params.scale); + ei_printf(" "); + } + ei_printf("\n"); + } + + ctx_start_us = ei_read_timer_us(); + + EI_IMPULSE_ERROR run_res = inference_tflite_run( + impulse, + block_config, + ctx_start_us, + &output, + &output_labels, + &output_scores, + static_cast(p_tensor_arena.get()), + result, + debug); + + graph_config->model_reset(ei_aligned_free); + + if (run_res != EI_IMPULSE_OK) { + return run_res; + } + + return EI_IMPULSE_OK; +} +#endif // EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + +__attribute__((unused)) int extract_tflite_eon_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float frequency) { + ei_dsp_config_tflite_eon_t *dsp_config = (ei_dsp_config_tflite_eon_t*)config_ptr; + + ei_config_tflite_eon_graph_t ei_config_tflite_graph_0 = { + .implementation_version = 1, + .model_init = dsp_config->init_fn, + .model_invoke = dsp_config->invoke_fn, + .model_reset = dsp_config->reset_fn, + .model_input = dsp_config->input_fn, + .model_output = dsp_config->output_fn, + }; + + ei_learning_block_config_tflite_graph_t ei_learning_block_config = { + .implementation_version = 1, + .classification_mode = EI_CLASSIFIER_CLASSIFICATION_MODE_DSP, + .block_id = dsp_config->block_id, + .object_detection = false, + .object_detection_last_layer = EI_CLASSIFIER_LAST_LAYER_UNKNOWN, + .output_data_tensor = 0, + .output_labels_tensor = 255, + .output_score_tensor = 255, + .threshold = 0, + .quantized = 0, + .compiled = 1, + .graph_config = &ei_config_tflite_graph_0 + }; + + auto x = run_nn_inference_from_dsp(&ei_learning_block_config, signal, output_matrix); + if (x != 0) { + return x; + } + + return EIDSP_OK; +} + +#endif // (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) && (EI_CLASSIFIER_COMPILED == 1) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_EON_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_full.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_full.h new file mode 100644 index 0000000..e1f0d42 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_full.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_FULL_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_FULL_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL) + +#include "model-parameters/model_metadata.h" +#include "tflite-model/trained_model_ops_define.h" + +#include +#include "tensorflow-lite/tensorflow/lite/c/common.h" +#include "tensorflow-lite/tensorflow/lite/interpreter.h" +#include "tensorflow-lite/tensorflow/lite/kernels/register.h" +#include "tensorflow-lite/tensorflow/lite/model.h" +#include "tensorflow-lite/tensorflow/lite/optional_debug_tools.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/classifier/inferencing_engines/tflite_helper.h" + +typedef struct { + std::unique_ptr model; + std::unique_ptr interpreter; +} ei_tflite_state_t; + +std::map ei_tflite_instances; + +/** + * Construct a tflite interpreter (creates it if needed) + */ +static EI_IMPULSE_ERROR get_interpreter(ei_learning_block_config_tflite_graph_t *block_config, tflite::Interpreter **interpreter) { + // not in the map yet... + if (!ei_tflite_instances.count(block_config->block_id)) { + ei_config_tflite_graph_t *graph_config = (ei_config_tflite_graph_t*)block_config->graph_config; + ei_tflite_state_t *new_state = new ei_tflite_state_t(); + + auto new_model = tflite::FlatBufferModel::BuildFromBuffer((const char*)graph_config->model, graph_config->model_size); + new_state->model = std::move(new_model); + if (!new_state->model) { + ei_printf("Failed to build TFLite model from buffer\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + tflite::ops::builtin::BuiltinOpResolver resolver; +#if EI_CLASSIFIER_HAS_TREE_ENSEMBLE_CLASSIFIER + resolver.AddCustom("TreeEnsembleClassifier", + tflite::ops::custom::Register_TREE_ENSEMBLE_CLASSIFIER()); +#endif + tflite::InterpreterBuilder builder(*new_state->model, resolver); + builder(&new_state->interpreter); + + if (!new_state->interpreter) { + ei_printf("Failed to construct interpreter\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + if (new_state->interpreter->AllocateTensors() != kTfLiteOk) { + ei_printf("AllocateTensors failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + int hw_thread_count = (int)std::thread::hardware_concurrency(); + hw_thread_count -= 1; // leave one thread free for the other application + if (hw_thread_count < 1) { + hw_thread_count = 1; + } + + if (new_state->interpreter->SetNumThreads(hw_thread_count) != kTfLiteOk) { + ei_printf("SetNumThreads failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + ei_tflite_instances.insert(std::make_pair(block_config->block_id, new_state)); + } + + auto tflite_state = ei_tflite_instances[block_config->block_id]; + *interpreter = tflite_state->interpreter.get(); + return EI_IMPULSE_OK; +} + +extern "C" EI_IMPULSE_ERROR run_nn_inference_from_dsp( + ei_learning_block_config_tflite_graph_t *block_config, + signal_t *signal, + matrix_t *output_matrix) +{ + tflite::Interpreter *interpreter; + auto interpreter_ret = get_interpreter(block_config, &interpreter); + if (interpreter_ret != EI_IMPULSE_OK) { + return interpreter_ret; + } + + TfLiteTensor *input = interpreter->input_tensor(0); + TfLiteTensor *output = interpreter->output_tensor(0); + + if (!input) { + return EI_IMPULSE_INPUT_TENSOR_WAS_NULL; + } + if (!output) { + return EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL; + } + + auto input_res = fill_input_tensor_from_signal(signal, input); + if (input_res != EI_IMPULSE_OK) { + return input_res; + } + + TfLiteStatus status = interpreter->Invoke(); + if (status != kTfLiteOk) { + ei_printf("ERR: interpreter->Invoke() failed with %d\n", status); + return EI_IMPULSE_TFLITE_ERROR; + } + + auto output_res = fill_output_matrix_from_tensor(output, output_matrix); + if (output_res != EI_IMPULSE_OK) { + return output_res; + } + + // on Linux we're not worried about free'ing (for now) + + return EI_IMPULSE_OK; +} + +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + tflite::Interpreter *interpreter; + auto interpreter_ret = get_interpreter(block_config, &interpreter); + if (interpreter_ret != EI_IMPULSE_OK) { + return interpreter_ret; + } + + TfLiteTensor *input = interpreter->input_tensor(0); + TfLiteTensor *output = interpreter->output_tensor(block_config->output_data_tensor); + + if (!input) { + return EI_IMPULSE_INPUT_TENSOR_WAS_NULL; + } + if (!output) { + return EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL; + } + + size_t mtx_size = impulse->dsp_blocks_size + impulse->learning_blocks_size; + auto input_res = fill_input_tensor_from_matrix(fmatrix, input, input_block_ids, input_block_ids_size, mtx_size); + if (input_res != EI_IMPULSE_OK) { + return input_res; + } + + uint64_t ctx_start_us = ei_read_timer_us(); + + TfLiteStatus status = interpreter->Invoke(); + if (status != kTfLiteOk) { + ei_printf("ERR: interpreter->Invoke() failed with %d\n", status); + return EI_IMPULSE_TFLITE_ERROR; + } + + uint64_t ctx_end_us = ei_read_timer_us(); + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + if (result->copy_output) { + auto output_res = fill_output_matrix_from_tensor(output, fmatrix[impulse->dsp_blocks_size + learn_block_index].matrix); + if (output_res != EI_IMPULSE_OK) { + return output_res; + } + } + + if (debug) { + ei_printf("Predictions (time: %d ms.):\n", result->timing.classification); + } + + TfLiteTensor *scores_tensor = interpreter->output_tensor(block_config->output_score_tensor); + TfLiteTensor *labels_tensor = interpreter->output_tensor(block_config->output_labels_tensor); + + EI_IMPULSE_ERROR fill_res = fill_result_struct_from_output_tensor_tflite( + impulse, block_config, output, labels_tensor, scores_tensor, result, debug); + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + // on Linux we're not worried about free'ing (for now) + + return EI_IMPULSE_OK; +} + +__attribute__((unused)) int extract_tflite_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float frequency) { + + ei_dsp_config_tflite_t *dsp_config = (ei_dsp_config_tflite_t*)config_ptr; + + ei_config_tflite_graph_t ei_config_tflite_graph_0 = { + .implementation_version = 1, + .model = dsp_config->model, + .model_size = dsp_config->model_size, + .arena_size = dsp_config->arena_size + }; + + ei_learning_block_config_tflite_graph_t ei_learning_block_config = { + .implementation_version = 1, + .classification_mode = EI_CLASSIFIER_CLASSIFICATION_MODE_DSP, + .block_id = dsp_config->block_id, + .object_detection = false, + .object_detection_last_layer = EI_CLASSIFIER_LAST_LAYER_UNKNOWN, + .output_data_tensor = 0, + .output_labels_tensor = 255, + .output_score_tensor = 255, + .threshold = 0, + .quantized = 0, + .compiled = 0, + .graph_config = &ei_config_tflite_graph_0 + }; + + auto x = run_nn_inference_from_dsp(&ei_learning_block_config, signal, output_matrix); + if (x != 0) { + return x; + } + + return EIDSP_OK; +} + +#endif // (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_FULL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_helper.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_helper.h new file mode 100644 index 0000000..c567805 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_helper.h @@ -0,0 +1,574 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_HELPER_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_HELPER_H_ + +#include "edge-impulse-sdk/classifier/ei_quantize.h" +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL) || (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) + +#if EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL +#include +#include "tensorflow-lite/tensorflow/lite/c/common.h" +#include "tensorflow-lite/tensorflow/lite/interpreter.h" +#include "tensorflow-lite/tensorflow/lite/kernels/register.h" +#include "tensorflow-lite/tensorflow/lite/model.h" +#include "tensorflow-lite/tensorflow/lite/optional_debug_tools.h" +#endif // EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL + +#if EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE +#include +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#endif // EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE + +EI_IMPULSE_ERROR fill_input_tensor_from_matrix( + ei_feature_t *fmatrix, + TfLiteTensor *input, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + size_t mtx_size +) { + size_t matrix_els = 0; + uint32_t input_idx = 0; + + for (size_t i = 0; i < input_block_ids_size; i++) { +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + size_t cur_mtx = input_block_ids[i]; + ei::matrix_t* matrix = NULL; + + if (!find_mtx_by_idx(fmatrix, &matrix, cur_mtx, mtx_size)) { + ei_printf("ERR: Cannot find matrix with id %zu\n", cur_mtx); + return EI_IMPULSE_INVALID_SIZE; + } +#else + ei::matrix_t* matrix = fmatrix[0].matrix; +#endif + + matrix_els += matrix->rows * matrix->cols; + + switch (input->type) { + case kTfLiteFloat32: { + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + input->data.f[input_idx++] = matrix->buffer[ix]; + } + break; + } + case kTfLiteInt8: { + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + float val = (float)matrix->buffer[ix]; + input->data.int8[input_idx++] = static_cast( + pre_cast_quantize(val, input->params.scale, input->params.zero_point, true)); + } + break; + } + case kTfLiteUInt8: { + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + float val = (float)matrix->buffer[ix]; + input->data.uint8[input_idx++] = static_cast( + pre_cast_quantize(val, input->params.scale, input->params.zero_point, false)); } + break; + } + default: { + ei_printf("ERR: Cannot handle input type (%d)\n", input->type); + return EI_IMPULSE_INPUT_TENSOR_WAS_NULL; + } + } + } + + if (input->bytes / 4 != matrix_els && input->bytes != matrix_els) { + ei_printf("ERR: input tensor has size %d bytes, but input matrix has has size %d bytes\n", + (int)input->bytes, (int)matrix_els); + return EI_IMPULSE_INVALID_SIZE; + } + + return EI_IMPULSE_OK; +} + +EI_IMPULSE_ERROR fill_input_tensor_from_signal( + signal_t *signal, + TfLiteTensor *input +) { + switch (input->type) { + case kTfLiteFloat32: { + if (input->bytes / 4 != signal->total_length) { + ei_printf("ERR: input tensor has size %d, but signal has size %d\n", + (int)input->bytes / 4, (int)signal->total_length); + return EI_IMPULSE_INVALID_SIZE; + } + + auto x = signal->get_data(0, signal->total_length, input->data.f); + if (x != EIDSP_OK) { + return EI_IMPULSE_DSP_ERROR; + } + break; + } + case kTfLiteInt8: + case kTfLiteUInt8: { + // we don't have a good signaling way here (this is DSP blocks where + // we don't understand the input very well; guess whether this is an RGB input) + bool is_rgb = input->bytes / 3 == signal->total_length; + + if (!is_rgb) { + // otherwise expect an exact match in length + if (input->bytes != signal->total_length) { + ei_printf("ERR: input tensor has size %d, but signal has size %d\n", + (int)input->bytes, (int)signal->total_length); + return EI_IMPULSE_INVALID_SIZE; + } + } + + float scale = input->params.scale; + int zero_point = input->params.zero_point; + if (scale == 0.0f) { // not quantized? + if (is_rgb) { + scale = 0.003921568859368563f; + } + else { + scale = 1.0f; + } + + if (input->type == kTfLiteInt8 && zero_point == 0) { + zero_point = -128; + } + } + + size_t output_ix = 0; + const size_t page_size = 1024; + + // buffered read from the signal + size_t bytes_left = signal->total_length; + for (size_t ix = 0; ix < signal->total_length; ix += page_size) { + size_t elements_to_read = bytes_left > page_size ? page_size : bytes_left; + + matrix_t input_matrix(elements_to_read, 1); + if (!input_matrix.buffer) { + return EI_IMPULSE_ALLOC_FAILED; + } + signal->get_data(ix, elements_to_read, input_matrix.buffer); + + for (size_t jx = 0; jx < elements_to_read; jx++) { + if (is_rgb) { + uint32_t value = static_cast(input_matrix.buffer[jx]); + + // fast code path + if (scale == 0.003921568859368563f && zero_point == -128) { + int32_t r = static_cast(value >> 16 & 0xff); + int32_t g = static_cast(value >> 8 & 0xff); + int32_t b = static_cast(value & 0xff); + + if (input->type == kTfLiteInt8) { + input->data.int8[output_ix++] = static_cast(r + zero_point); + input->data.int8[output_ix++] = static_cast(g + zero_point); + input->data.int8[output_ix++] = static_cast(b + zero_point); + } + else { + input->data.uint8[output_ix++] = static_cast(r + zero_point); + input->data.uint8[output_ix++] = static_cast(g + zero_point); + input->data.uint8[output_ix++] = static_cast(b + zero_point); + } + } + // slow code path + else { + float r = static_cast(value >> 16 & 0xff) / 255.0f; + float g = static_cast(value >> 8 & 0xff) / 255.0f; + float b = static_cast(value & 0xff) / 255.0f; + + if (input->type == kTfLiteInt8) { + input->data.int8[output_ix++] = static_cast(round(r / scale) + zero_point); + input->data.int8[output_ix++] = static_cast(round(g / scale) + zero_point); + input->data.int8[output_ix++] = static_cast(round(b / scale) + zero_point); + } + else { + input->data.uint8[output_ix++] = static_cast(round(r / scale) + zero_point); + input->data.uint8[output_ix++] = static_cast(round(g / scale) + zero_point); + input->data.uint8[output_ix++] = static_cast(round(b / scale) + zero_point); + } + } + } + else { + float value = input_matrix.buffer[jx]; + if (input->type == kTfLiteInt8) { + input->data.int8[output_ix++] = static_cast(round(value / scale) + zero_point); + } + else { // uint8 + input->data.uint8[output_ix++] = static_cast((value / scale) + zero_point); + } + } + } + } + break; + } + default: { + ei_printf("ERR: Cannot handle input type (%d)\n", input->type); + return EI_IMPULSE_INPUT_TENSOR_WAS_NULL; + } + } + + return EI_IMPULSE_OK; +} + +EI_IMPULSE_ERROR fill_output_matrix_from_tensor( + TfLiteTensor *output, + matrix_t *output_matrix +) { + const size_t matrix_els = output_matrix->rows * output_matrix->cols; + + switch (output->type) { + case kTfLiteFloat32: { + if (output->bytes / 4 != matrix_els) { + ei_printf("ERR: output tensor has size %d, but input matrix has has size %d\n", + (int)output->bytes / 4, (int)matrix_els); + return EI_IMPULSE_INVALID_SIZE; + } + + memcpy(output_matrix->buffer, output->data.f, output->bytes); + break; + } + case kTfLiteInt8: { + if (output->bytes != matrix_els) { + ei_printf("ERR: output tensor has size %d, but input matrix has has size %d\n", + (int)output->bytes, (int)matrix_els); + return EI_IMPULSE_INVALID_SIZE; + } + + for (size_t ix = 0; ix < output->bytes; ix++) { + float value = static_cast(output->data.int8[ix] - output->params.zero_point) * output->params.scale; + output_matrix->buffer[ix] = value; + } + break; + } + case kTfLiteUInt8: { + if (output->bytes != matrix_els) { + ei_printf("ERR: output tensor has size %d, but input matrix has has size %d\n", + (int)output->bytes, (int)matrix_els); + return EI_IMPULSE_INVALID_SIZE; + } + + for (size_t ix = 0; ix < output->bytes; ix++) { + float value = static_cast(output->data.uint8[ix] - output->params.zero_point) * output->params.scale; + output_matrix->buffer[ix] = value; + } + break; + } + default: { + ei_printf("ERR: Cannot handle output type (%d)\n", output->type); + return EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL; + } + } + + return EI_IMPULSE_OK; +} + +EI_IMPULSE_ERROR fill_result_struct_from_output_tensor_tflite( + const ei_impulse_t *impulse, + ei_learning_block_config_tflite_graph_t *block_config, + TfLiteTensor* output, + TfLiteTensor* labels_tensor, + TfLiteTensor* scores_tensor, + ei_impulse_result_t *result, + bool debug +) { + EI_IMPULSE_ERROR fill_res = EI_IMPULSE_OK; + + if (block_config->classification_mode == EI_CLASSIFIER_CLASSIFICATION_MODE_OBJECT_DETECTION) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + bool int8_output = output->type == TfLiteType::kTfLiteInt8; + if (int8_output) { + fill_res = fill_result_struct_i8_fomo( + impulse, + block_config, + result, + output->data.int8, + output->params.zero_point, + output->params.scale, + impulse->fomo_output_size, + impulse->fomo_output_size); + } + else { + fill_res = fill_result_struct_f32_fomo( + impulse, + block_config, + result, + output->data.f, + impulse->fomo_output_size, + impulse->fomo_output_size); + } + break; + } +#if EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL + case EI_CLASSIFIER_LAST_LAYER_SSD: { + if (!scores_tensor->data.f) { + return EI_IMPULSE_SCORE_TENSOR_WAS_NULL; + } + if (!labels_tensor->data.f) { + return EI_IMPULSE_LABEL_TENSOR_WAS_NULL; + } + if (output->type == kTfLiteFloat32) { + fill_res = fill_result_struct_f32_object_detection( + impulse, + block_config, + result, + output->data.f, + scores_tensor->data.f, + labels_tensor->data.f, + debug); + } + else { + ei_printf("ERR: MobileNet SSD does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + break; + } +#else + case EI_CLASSIFIER_LAST_LAYER_SSD: { + ei_printf("ERR: MobileNet SSD is not supported in EON or TensorFlow Lite Micro\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } +#endif // EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL + case EI_CLASSIFIER_LAST_LAYER_YOLOV5: + case EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI: { + int version = block_config->object_detection_last_layer == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI ? + 5 : 6; + + if (output->type == kTfLiteInt8) { + fill_res = fill_result_struct_quantized_yolov5( + impulse, + block_config, + result, + version, + output->data.int8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteUInt8) { + fill_res = fill_result_struct_quantized_yolov5( + impulse, + block_config, + result, + version, + output->data.uint8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteFloat32) { + fill_res = fill_result_struct_f32_yolov5( + impulse, + block_config, + result, + version, + output->data.f, + impulse->tflite_output_features_count, + debug); + } + else { + ei_printf("ERR: Invalid output type (%d) for YOLOv5 last layer\n", output->type); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOX: { + if (block_config->quantized == 1) { + ei_printf("ERR: YOLOX does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + fill_res = fill_result_struct_f32_yolox( + impulse, + block_config, + result, + output->data.f, + impulse->tflite_output_features_count, + debug); + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOV7: { + if (block_config->quantized == 1) { + ei_printf("ERR: YOLOV7 does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + size_t output_feature_count = 1; + for (int ix = 0; ix < output->dims->size; ix++) { + output_feature_count *= output->dims->data[ix]; + } + fill_res = fill_result_struct_f32_yolov7( + impulse, + block_config, + result, + output->data.f, + output_feature_count); + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_TAO_SSD: + case EI_CLASSIFIER_LAST_LAYER_TAO_RETINANET: { + + if (output->type == kTfLiteInt8) { + fill_res = fill_result_struct_quantized_tao_decode_detections( + impulse, + block_config, + result, + output->data.int8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteUInt8) { + fill_res = fill_result_struct_quantized_tao_decode_detections( + impulse, + block_config, + result, + output->data.uint8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteFloat32) { + fill_res = fill_result_struct_f32_tao_decode_detections( + impulse, + block_config, + result, + output->data.f, + impulse->tflite_output_features_count, + debug); + } + else { + ei_printf("ERR: Invalid output type (%d) for TAO last layer\n", output->type); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV3: { + + if (output->type == kTfLiteInt8) { + fill_res = fill_result_struct_quantized_tao_yolov3( + impulse, + block_config, + result, + output->data.int8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteUInt8) { + fill_res = fill_result_struct_quantized_tao_yolov3( + impulse, + block_config, + result, + output->data.uint8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteFloat32) { + fill_res = fill_result_struct_f32_tao_yolov3( + impulse, + block_config, + result, + output->data.f, + impulse->tflite_output_features_count, + debug); + } + else { + ei_printf("ERR: Invalid output type (%d) for TAO YOLOv3 layer\n", output->type); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_TAO_YOLOV4: { + + if (output->type == kTfLiteInt8) { + fill_res = fill_result_struct_quantized_tao_yolov4( + impulse, + block_config, + result, + output->data.int8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteUInt8) { + fill_res = fill_result_struct_quantized_tao_yolov4( + impulse, + block_config, + result, + output->data.uint8, + output->params.zero_point, + output->params.scale, + impulse->tflite_output_features_count, + debug); + } + else if (output->type == kTfLiteFloat32) { + fill_res = fill_result_struct_f32_tao_yolov4( + impulse, + block_config, + result, + output->data.f, + impulse->tflite_output_features_count, + debug); + } + else { + ei_printf("ERR: Invalid output type (%d) for TAO YOLOv4 layer\n", output->type); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + break; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + } + } + else if (block_config->classification_mode == EI_CLASSIFIER_CLASSIFICATION_MODE_VISUAL_ANOMALY) + { + if (!result->copy_output) { + fill_res = fill_result_visual_ad_struct_f32(impulse, result, output->data.f, block_config->threshold, debug); + } + } + // if we copy the output, we don't need to process it as classification + else + { + if (!result->copy_output) { + bool int8_output = output->type == TfLiteType::kTfLiteInt8; + if (int8_output) { + fill_res = fill_result_struct_i8(impulse, result, output->data.int8, output->params.zero_point, output->params.scale, debug); + } + else { + fill_res = fill_result_struct_f32(impulse, result, output->data.f, debug); + } + } + } + + return fill_res; +} +#endif // #if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_FULL) || (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) + +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_HELPER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_micro.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_micro.h new file mode 100644 index 0000000..4710b74 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_micro.h @@ -0,0 +1,466 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_MICRO_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_MICRO_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) && (EI_CLASSIFIER_COMPILED != 1) + +#include "model-parameters/model_metadata.h" + +#include +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h" +#include "edge-impulse-sdk/classifier/ei_aligned_malloc.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/classifier/inferencing_engines/tflite_helper.h" + +#if defined(EI_CLASSIFIER_HAS_TFLITE_OPS_RESOLVER) && EI_CLASSIFIER_HAS_TFLITE_OPS_RESOLVER == 1 +#include "tflite-model/tflite-resolver.h" +#endif // EI_CLASSIFIER_HAS_TFLITE_OPS_RESOLVER + +#ifdef EI_CLASSIFIER_ALLOCATION_STATIC +#if defined __GNUC__ +#define ALIGN(X) __attribute__((aligned(X))) +#elif defined _MSC_VER +#define ALIGN(X) __declspec(align(X)) +#elif defined __TASKING__ +#define ALIGN(X) __align(X) +#endif +#endif + +/** + * Setup the TFLite runtime + * + * @param ctx_start_us Pointer to the start time + * @param input Pointer to input tensor + * @param output Pointer to output tensor + * @param micro_interpreter Pointer to interpreter (for non-compiled models) + * @param micro_tensor_arena Pointer to the arena that will be allocated + * + * @return EI_IMPULSE_OK if successful + */ +static EI_IMPULSE_ERROR inference_tflite_setup( + ei_learning_block_config_tflite_graph_t *block_config, + uint64_t *ctx_start_us, + TfLiteTensor** input, + TfLiteTensor** output, + TfLiteTensor** output_labels, + TfLiteTensor** output_scores, + tflite::MicroInterpreter** micro_interpreter, + ei_unique_ptr_t& p_tensor_arena) { + + *ctx_start_us = ei_read_timer_us(); + + ei_config_tflite_graph_t *graph_config = (ei_config_tflite_graph_t*)block_config->graph_config; + +#ifdef EI_CLASSIFIER_ALLOCATION_STATIC + // Assign a no-op lambda to the "free" function in case of static arena + static uint8_t tensor_arena[EI_CLASSIFIER_TFLITE_ARENA_SIZE] ALIGN(16); + p_tensor_arena = ei_unique_ptr_t(tensor_arena, [](void*){}); +#else + // Create an area of memory to use for input, output, and intermediate arrays. + uint8_t *tensor_arena = (uint8_t*)ei_aligned_calloc(16, graph_config->arena_size); + if (tensor_arena == NULL) { + ei_printf("Failed to allocate TFLite arena (%zu bytes)\n", graph_config->arena_size); + return EI_IMPULSE_TFLITE_ARENA_ALLOC_FAILED; + } + p_tensor_arena = ei_unique_ptr_t(tensor_arena, ei_aligned_free); +#endif + + static bool tflite_first_run = true; + static uint8_t *model_arr = NULL; + + if (model_arr != graph_config->model) { + tflite_first_run = true; + model_arr = (uint8_t*)graph_config->model; + } + + static const tflite::Model* model = nullptr; + + // ====== + // Initialization code start + // This part can be run once, but that would require the TFLite arena + // to be allocated at all times, which is not ideal (e.g. when doing MFCC) + // ====== + if (tflite_first_run) { + // Map the model into a usable data structure. This doesn't involve any + // copying or parsing, it's a very lightweight operation. + model = tflite::GetModel(graph_config->model); + if (model->version() != TFLITE_SCHEMA_VERSION) { + ei_printf( + "Model provided is schema version %d not equal " + "to supported version %d.", + model->version(), TFLITE_SCHEMA_VERSION); + return EI_IMPULSE_TFLITE_ERROR; + } + tflite_first_run = false; + } + +#ifdef EI_TFLITE_RESOLVER + EI_TFLITE_RESOLVER +#else + static tflite::AllOpsResolver resolver; // needs static to match the life of the interpreter +#endif + + // Build an interpreter to run the model with. + tflite::MicroInterpreter *interpreter = new tflite::MicroInterpreter( + model, resolver, tensor_arena, graph_config->arena_size); + + *micro_interpreter = interpreter; + + // Allocate memory from the tensor_arena for the model's tensors. + TfLiteStatus allocate_status = interpreter->AllocateTensors(true); + if (allocate_status != kTfLiteOk) { + ei_printf("AllocateTensors() failed"); + return EI_IMPULSE_TFLITE_ERROR; + } + + // Obtain pointers to the model's input and output tensors. + *input = interpreter->input(0); + *output = interpreter->output(block_config->output_data_tensor); + + if (block_config->object_detection_last_layer == EI_CLASSIFIER_LAST_LAYER_SSD) { + *output_scores = interpreter->output(block_config->output_score_tensor); + *output_labels = interpreter->output(block_config->output_labels_tensor); + } + + if (tflite_first_run) { + tflite_first_run = false; + } + + return EI_IMPULSE_OK; +} + +/** + * Run TFLite model + * + * @param ctx_start_us Start time of the setup function (see above) + * @param output Output tensor + * @param interpreter TFLite interpreter (non-compiled models) + * @param tensor_arena Allocated arena (will be freed) + * @param result Struct for results + * @param debug Whether to print debug info + * + * @return EI_IMPULSE_OK if successful + */ +static EI_IMPULSE_ERROR inference_tflite_run( + const ei_impulse_t *impulse, + ei_learning_block_config_tflite_graph_t *block_config, + uint64_t ctx_start_us, + TfLiteTensor* output, + TfLiteTensor* labels_tensor, + TfLiteTensor* scores_tensor, + tflite::MicroInterpreter* interpreter, + uint8_t* tensor_arena, + ei_impulse_result_t *result, + bool debug) { + + + // Run inference, and report any error + TfLiteStatus invoke_status = interpreter->Invoke(); + if (invoke_status != kTfLiteOk) { + delete interpreter; + ei_printf("Invoke failed (%d)\n", invoke_status); + return EI_IMPULSE_TFLITE_ERROR; + } + + uint64_t ctx_end_us = ei_read_timer_us(); + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + + // Read the predicted y value from the model's output tensor + if (debug) { + ei_printf("Predictions (time: %d ms.):\n", result->timing.classification); + } + + EI_IMPULSE_ERROR fill_res = fill_result_struct_from_output_tensor_tflite( + impulse, block_config, output, labels_tensor, scores_tensor, result, debug); + + delete interpreter; + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + return EI_IMPULSE_OK; +} + + +/** + * @brief Do neural network inferencing over a signal (from the DSP) + * + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference_from_dsp( + ei_learning_block_config_tflite_graph_t *config, + signal_t *signal, + matrix_t *output_matrix) +{ + TfLiteTensor* input; + TfLiteTensor* output; + TfLiteTensor* output_scores; + TfLiteTensor* output_labels; + uint64_t ctx_start_us = ei_read_timer_us(); + ei_unique_ptr_t p_tensor_arena(nullptr, ei_aligned_free); + + tflite::MicroInterpreter* interpreter; + EI_IMPULSE_ERROR init_res = inference_tflite_setup( + config, + &ctx_start_us, + &input, &output, + &output_labels, + &output_scores, + &interpreter, p_tensor_arena); + + if (init_res != EI_IMPULSE_OK) { + return init_res; + } + + auto input_res = fill_input_tensor_from_signal(signal, input); + if (input_res != EI_IMPULSE_OK) { + return input_res; + } + + // Run inference, and report any error + TfLiteStatus invoke_status = interpreter->Invoke(); + if (invoke_status != kTfLiteOk) { + ei_printf("Invoke failed (%d)\n", invoke_status); + return EI_IMPULSE_TFLITE_ERROR; + } + + auto output_res = fill_output_matrix_from_tensor(output, output_matrix); + if (output_res != EI_IMPULSE_OK) { + return output_res; + } + + delete interpreter; + + return EI_IMPULSE_OK; +} + +/** + * @brief Do neural network inferencing over the processed feature matrix + * + * @param fmatrix Processed matrix + * @param result Output classifier results + * @param[in] debug Debug output enable + * + * @return The ei impulse error. + */ +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + TfLiteTensor* input; + TfLiteTensor* output; + TfLiteTensor* output_scores; + TfLiteTensor* output_labels; + uint64_t ctx_start_us = ei_read_timer_us(); + ei_unique_ptr_t p_tensor_arena(nullptr, ei_aligned_free); + + tflite::MicroInterpreter* interpreter; + EI_IMPULSE_ERROR init_res = inference_tflite_setup( + block_config, + &ctx_start_us, + &input, &output, + &output_labels, + &output_scores, + &interpreter, + p_tensor_arena); + + if (init_res != EI_IMPULSE_OK) { + return init_res; + } + + uint8_t* tensor_arena = static_cast(p_tensor_arena.get()); + + size_t mtx_size = impulse->dsp_blocks_size + impulse->learning_blocks_size; + auto input_res = fill_input_tensor_from_matrix(fmatrix, input, input_block_ids, input_block_ids_size, mtx_size); + if (input_res != EI_IMPULSE_OK) { + return input_res; + } + + EI_IMPULSE_ERROR run_res = inference_tflite_run( + impulse, + block_config, + ctx_start_us, + output, + output_labels, + output_scores, + interpreter, tensor_arena, result, debug); + + if (result->copy_output) { + auto output_res = fill_output_matrix_from_tensor(output, fmatrix[impulse->dsp_blocks_size + learn_block_index].matrix); + if (output_res != EI_IMPULSE_OK) { + return output_res; + } + } + + if (run_res != EI_IMPULSE_OK) { + return run_res; + } + + return EI_IMPULSE_OK; +} + +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 +/** + * Special function to run the classifier on images, only works on TFLite models (either interpreter or EON or for tensaiflow) + * that allocates a lot less memory by quantizing in place. This only works if 'can_run_classifier_image_quantized' + * returns EI_IMPULSE_OK. + */ +EI_IMPULSE_ERROR run_nn_inference_image_quantized( + const ei_impulse_t *impulse, + signal_t *signal, + ei_impulse_result_t *result, + void *config_ptr, + bool debug = false) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + memset(result, 0, sizeof(ei_impulse_result_t)); + + uint64_t ctx_start_us; + TfLiteTensor* input; + TfLiteTensor* output; + TfLiteTensor* output_scores; + TfLiteTensor* output_labels; + ei_unique_ptr_t p_tensor_arena(nullptr, ei_aligned_free); + + tflite::MicroInterpreter* interpreter; + EI_IMPULSE_ERROR init_res = inference_tflite_setup( + block_config, + &ctx_start_us, + &input, &output, + &output_labels, + &output_scores, + &interpreter, + p_tensor_arena); + + if (init_res != EI_IMPULSE_OK) { + return init_res; + } + + if (input->type != TfLiteType::kTfLiteInt8 && input->type != TfLiteType::kTfLiteUInt8) { + return EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES; + } + + uint64_t dsp_start_us = ei_read_timer_us(); + + // features matrix maps around the input tensor to not allocate any memory + ei::matrix_i8_t features_matrix(1, impulse->nn_input_frame_size, input->data.int8); + + // run DSP process and quantize automatically + int ret = extract_image_features_quantized(signal, &features_matrix, impulse->dsp_blocks[0].config, input->params.scale, input->params.zero_point, + impulse->frequency, impulse->learning_blocks[0].image_scaling); + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to run DSP process (%d)\n", ret); + return EI_IMPULSE_DSP_ERROR; + } + + if (ei_run_impulse_check_canceled() == EI_IMPULSE_CANCELED) { + return EI_IMPULSE_CANCELED; + } + + result->timing.dsp_us = ei_read_timer_us() - dsp_start_us; + result->timing.dsp = (int)(result->timing.dsp_us / 1000); + + if (debug) { + ei_printf("Features (%d ms.): ", result->timing.dsp); + for (size_t ix = 0; ix < features_matrix.cols; ix++) { + ei_printf_float((features_matrix.buffer[ix] - input->params.zero_point) * input->params.scale); + ei_printf(" "); + } + ei_printf("\n"); + } + + ctx_start_us = ei_read_timer_us(); + + EI_IMPULSE_ERROR run_res = inference_tflite_run(impulse, + block_config, + ctx_start_us, + output, + output_labels, + output_scores, + interpreter, + static_cast(p_tensor_arena.get()), + result, debug); + + if (run_res != EI_IMPULSE_OK) { + return run_res; + } + + return EI_IMPULSE_OK; +} +#endif // EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + +__attribute__((unused)) int extract_tflite_features(signal_t *signal, matrix_t *output_matrix, void *config_ptr, const float frequency) { + ei_dsp_config_tflite_t *dsp_config = (ei_dsp_config_tflite_t*)config_ptr; + + ei_config_tflite_graph_t ei_config_tflite_graph_0 = { + .implementation_version = 1, + .model = dsp_config->model, + .model_size = dsp_config->model_size, + .arena_size = dsp_config->arena_size + }; + + ei_learning_block_config_tflite_graph_t ei_learning_block_config = { + .implementation_version = 1, + .classification_mode = EI_CLASSIFIER_CLASSIFICATION_MODE_DSP, + .block_id = dsp_config->block_id, + .object_detection = false, + .object_detection_last_layer = EI_CLASSIFIER_LAST_LAYER_UNKNOWN, + .output_data_tensor = 0, + .output_labels_tensor = 255, + .output_score_tensor = 255, + .threshold = 0, + .quantized = 0, + .compiled = 0, + .graph_config = &ei_config_tflite_graph_0 + }; + + auto x = run_nn_inference_from_dsp(&ei_learning_block_config, signal, output_matrix); + if (x != 0) { + return x; + } + + return EIDSP_OK; +} + +#endif // (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) && (EI_CLASSIFIER_COMPILED != 1) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_MICRO_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_tidl.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_tidl.h new file mode 100644 index 0000000..5d78201 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/classifier/inferencing_engines/tflite_tidl.h @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_TIDL_H_ +#define _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_TIDL_H_ + +#if (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_TIDL) + +#include "model-parameters/model_metadata.h" + +#include +#include "tensorflow-lite/tensorflow/lite/c/common.h" +#include "tensorflow-lite/tensorflow/lite/interpreter.h" +#include "tensorflow-lite/tensorflow/lite/kernels/register.h" +#include "tensorflow-lite/tensorflow/lite/model.h" +#include "tensorflow-lite/tensorflow/lite/optional_debug_tools.h" +#include "edge-impulse-sdk/classifier/ei_fill_result_struct.h" +#include "edge-impulse-sdk/classifier/ei_model_types.h" + +#include "itidl_rt.h" +#if ARMNN_ENABLE +#include "DelegateOptions.hpp" +#include "armnn_delegate.hpp" +#endif + +#include + +// old models don't have this, add this here +#ifndef EI_CLASSIFIER_TFLITE_OUTPUT_DATA_TENSOR +#define EI_CLASSIFIER_TFLITE_OUTPUT_DATA_TENSOR 0 +#endif // not defined EI_CLASSIFIER_TFLITE_OUTPUT_DATA_TENSOR + +#include "tflite-model/tidl-model.h" +#include "utils/model_header_utils.h" + +void *in_ptrs[16] = {NULL}; +void *out_ptrs[16] = {NULL}; + +EI_IMPULSE_ERROR run_nn_inference( + const ei_impulse_t *impulse, + ei_feature_t *fmatrix, + uint32_t learn_block_index, + uint32_t* input_block_ids, + uint32_t input_block_ids_size, + ei_impulse_result_t *result, + void *config_ptr, + bool debug) +{ + ei_learning_block_config_tflite_graph_t *block_config = (ei_learning_block_config_tflite_graph_t*)config_ptr; + + static std::unique_ptr model = nullptr; + static std::unique_ptr interpreter = nullptr; + static std::vector inputs; + static std::vector outputs; + + if (!model) { + + std::string proj_artifacts_path = "/tmp/" + std::string(impulse->project_name) + "-" + std::to_string(impulse->project_id) + "-" + std::to_string(impulse->deploy_version); + + create_project_if_not_exists(proj_artifacts_path, model_h_files, model_h_files_len); + + std::string proj_model_path = proj_artifacts_path + "/trained.tflite"; + + model = tflite::FlatBufferModel::BuildFromFile(proj_model_path.c_str()); + if (!model) { + ei_printf("Failed to build TFLite model from buffer\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + tflite::ops::builtin::BuiltinOpResolver resolver; + tflite::InterpreterBuilder builder(*model, resolver); + builder(&interpreter); + + if (!interpreter) { + ei_printf("Failed to construct interpreter\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + /* This part creates the dlg_ptr */ + ei_printf("TIDL delegate mode\n"); + typedef TfLiteDelegate *(*tflite_plugin_create_delegate)(char **, char **, size_t, void (*report_error)(const char *)); + tflite_plugin_create_delegate tflite_plugin_dlg_create; + char *keys[] = {(char *)"artifacts_folder", (char *)"num_tidl_subgraphs", (char *)"debug_level"}; + char *values[] = {(char *)proj_artifacts_path.c_str(), (char *)"16", (char *)"0"}; + void *lib = dlopen("libtidl_tfl_delegate.so", RTLD_NOW); + assert(lib); + tflite_plugin_dlg_create = (tflite_plugin_create_delegate)dlsym(lib, "tflite_plugin_create_delegate"); + TfLiteDelegate *dlg_ptr = tflite_plugin_dlg_create(keys, values, 3, NULL); + interpreter->ModifyGraphWithDelegate(dlg_ptr); + ei_printf("ModifyGraphWithDelegate - Done \n"); + + + if (interpreter->AllocateTensors() != kTfLiteOk) { + ei_printf("AllocateTensors failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + + int hw_thread_count = (int)std::thread::hardware_concurrency(); + hw_thread_count -= 1; // leave one thread free for the other application + if (hw_thread_count < 1) { + hw_thread_count = 1; + } + + if (interpreter->SetNumThreads(hw_thread_count) != kTfLiteOk) { + ei_printf("SetNumThreads failed\n"); + return EI_IMPULSE_TFLITE_ERROR; + } + } + + inputs = interpreter->inputs(); + outputs = interpreter->outputs(); + + ei_printf("device mem enabled\n"); + for (uint32_t i = 0; i < inputs.size(); i++) + { + const TfLiteTensor *tensor = interpreter->input_tensor(i); + in_ptrs[i] = TIDLRT_allocSharedMem(tflite::kDefaultTensorAlignment, tensor->bytes); + if (in_ptrs[i] == NULL) + { + ei_printf("Could not allocate Memory for input: %s\n", tensor->name); + } + interpreter->SetCustomAllocationForTensor(inputs[i], {in_ptrs[i], tensor->bytes}); + } + for (uint32_t i = 0; i < outputs.size(); i++) + { + const TfLiteTensor *tensor = interpreter->output_tensor(i); + out_ptrs[i] = TIDLRT_allocSharedMem(tflite::kDefaultTensorAlignment, tensor->bytes); + if (out_ptrs[i] == NULL) + { + ei_printf("Could not allocate Memory for ouput: %s\n", tensor->name); + } + interpreter->SetCustomAllocationForTensor(outputs[i], {out_ptrs[i], tensor->bytes}); + } + + // Obtain pointers to the model's input and output tensors. +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + int8_t* input = interpreter->typed_input_tensor(0); +#else + float* input = interpreter->typed_input_tensor(0); +#endif + + if (!input) { + return EI_IMPULSE_INPUT_TENSOR_WAS_NULL; + } + + size_t mtx_size = impulse->dsp_blocks_size + impulse->learning_blocks_size; + + for (size_t i = 0; i < input_block_ids_size; i++) { +#if EI_CLASSIFIER_SINGLE_FEATURE_INPUT == 0 + uint16_t cur_mtx = input_block_ids[i]; + ei::matrix_t* matrix = NULL; + + if (!find_mtx_by_idx(fmatrix, &matrix, cur_mtx, mtx_size)) { + ei_printf("ERR: Cannot find matrix with id %zu\n", cur_mtx); + return EI_IMPULSE_INVALID_SIZE; + } +#else + ei::matrix_t* matrix = fmatrix[0].matrix; +#endif + + for (uint32_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + if (block_config->object_detection) { +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + float pixel = (float)matrix->buffer[ix]; + input[ix] = static_cast((pixel / input->tflite_input_scale) + input->tflite_input_zeropoint); +#else + input[ix] = matrix->buffer[ix]; +#endif + } + else { +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + input[ix] = static_cast(round(matrix->buffer[ix] / input->tflite_input_scale) + input->tflite_input_zeropoint); +#else + input[ix] = matrix->buffer[ix]; +#endif + } + } + } + + uint64_t ctx_start_us = ei_read_timer_us(); + + interpreter->Invoke(); + + uint64_t ctx_end_us = ei_read_timer_us(); + + result->timing.classification_us = ctx_end_us - ctx_start_us; + result->timing.classification = (int)(result->timing.classification_us / 1000); + +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + int8_t* out_data = interpreter->typed_output_tensor(block_config->output_data_tensor); +#else + float* out_data = interpreter->typed_output_tensor(block_config->output_data_tensor); +#endif + + if (debug) { + ei_printf("LOG_INFO tensors size: %ld \n", interpreter->tensors_size()); + ei_printf("LOG_INFO nodes size: %ld\n", interpreter->nodes_size()); + ei_printf("LOG_INFO number of inputs: %ld\n", inputs.size()); + ei_printf("LOG_INFO number of outputs: %ld\n", outputs.size()); + ei_printf("LOG_INFO input(0) name: %s\n", interpreter->GetInputName(0)); + + int t_size = interpreter->tensors_size(); + for (int i = 0; i < t_size; i++) + { + if (interpreter->tensor(i)->name) { + ei_printf("LOG_INFO %d: %s,%ld,%d,%f,%d,size(", i, interpreter->tensor(i)->name, + interpreter->tensor(i)->bytes, + interpreter->tensor(i)->type, + interpreter->tensor(i)->params.scale, + interpreter->tensor(i)->params.zero_point); + + for (int k=0; k < interpreter->tensor(i)->dims->size; k++) { + if (k == interpreter->tensor(i)->dims->size - 1) { + ei_printf("%d", interpreter->tensor(i)->dims->data[k]); + } else { + ei_printf("%d,", interpreter->tensor(i)->dims->data[k]); + } + } + ei_printf(")\n"); + } + } + } + + if (!out_data) { + return EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL; + } + + if (debug) { + ei_printf("Predictions (time: %d ms.):\n", result->timing.classification); + } + + EI_IMPULSE_ERROR fill_res = EI_IMPULSE_OK; + + if (block_config->object_detection) { + switch (block_config->object_detection_last_layer) { + case EI_CLASSIFIER_LAST_LAYER_FOMO: { + if (block_config->quantized == 1) { +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + fill_res = fill_result_struct_i8_fomo( + impulse, + block_config, + result, + out_data, + out_data->tflite_output_zeropoint, + out_data->tflite_output_scale, + impulse->fomo_output_size, + impulse->fomo_output_size); +#endif + } + else { + fill_res = fill_result_struct_f32_fomo( + impulse, + block_config, + result, + out_data, + impulse->fomo_output_size, + impulse->fomo_output_size); + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_SSD: { + float *scores_tensor = interpreter->typed_output_tensor(block_config->output_score_tensor); + float *label_tensor = interpreter->typed_output_tensor(block_config->output_labels_tensor); + if (!scores_tensor) { + return EI_IMPULSE_SCORE_TENSOR_WAS_NULL; + } + if (!label_tensor) { + return EI_IMPULSE_LABEL_TENSOR_WAS_NULL; + } + if (block_config->quantized == 1) { + ei_printf("ERR: MobileNet SSD does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + fill_res = fill_result_struct_f32_object_detection( + impulse, + block_config, + result, + out_data, + scores_tensor, + label_tensor, + debug); + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOV5: + case EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI: { + if (block_config->quantized == 1) { + ei_printf("ERR: YOLOv5 does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + int version = block_config->object_detection_last_layer == EI_CLASSIFIER_LAST_LAYER_YOLOV5_V5_DRPAI ? + 5 : 6; + fill_res = fill_result_struct_f32_yolov5( + impulse, + block_config, + result, + version, + out_data, + impulse->tflite_output_features_count, + debug); + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOX: { + if (block_config->quantized == 1) { + ei_printf("ERR: YOLOX does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + fill_res = fill_result_struct_f32_yolox( + impulse, + block_config, + result, + out_data, + impulse->tflite_output_features_count, + debug); + } + break; + } + case EI_CLASSIFIER_LAST_LAYER_YOLOV7: { + if (block_config->quantized == 1) { + ei_printf("ERR: YOLOV7 does not support quantized inference\n"); + return EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE; + } + else { + TfLiteTensor *output = interpreter->output_tensor(0); + size_t output_feature_count = 1; + for (int ix = 0; ix < output->dims->size; ix++) { + output_feature_count *= output->dims->data[ix]; + } + fill_res = fill_result_struct_f32_yolov7( + impulse, + block_config, + result, + output->data.f, + output_feature_count); + } + break; + } + default: { + ei_printf("ERR: Unsupported object detection last layer (%d)\n", + block_config->object_detection_last_layer); + break; + } + } + } + else { +#if EI_CLASSIFIER_QUANTIZATION_ENABLED == 1 + fill_res = fill_result_struct_i8(impulse, result, out_data, out_data->tflite_output_zeropoint, out_data->tflite_output_scale, debug); +#else + fill_res = fill_result_struct_f32(impulse, result, out_data, debug); +#endif + } + + for (uint32_t i = 0; i < inputs.size(); i++) + { + if (in_ptrs[i]) + { + TIDLRT_freeSharedMem(in_ptrs[i]); + } + } + for (uint32_t i = 0; i < outputs.size(); i++) + { + if (out_ptrs[i]) + { + TIDLRT_freeSharedMem(out_ptrs[i]); + } + } + + if (fill_res != EI_IMPULSE_OK) { + return fill_res; + } + + // on Linux we're not worried about free'ing (for now) + + return EI_IMPULSE_OK; +} + +#endif // (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE_TIDL) +#endif // _EI_CLASSIFIER_INFERENCING_ENGINE_TFLITE_TIDL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/cmake/utils.cmake b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/cmake/utils.cmake new file mode 100644 index 0000000..02cf739 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/cmake/utils.cmake @@ -0,0 +1,155 @@ +MACRO(RECURSIVE_FIND_DIR return_list dir pattern) + FILE(GLOB_RECURSE new_list "${dir}/${pattern}") + SET(dir_list "") + FOREACH(file_path ${new_list}) + GET_FILENAME_COMPONENT(dir_path ${file_path} PATH) + SET(dir_list ${dir_list} ${dir_path}) + ENDFOREACH() + LIST(REMOVE_DUPLICATES dir_list) + SET(${return_list} ${dir_list}) +ENDMACRO() + +MACRO(RECURSIVE_FIND_FILE return_list dir pattern) + FILE(GLOB_RECURSE new_list "${dir}/${pattern}") + SET(dir_list "") + FOREACH(file_path ${new_list}) + SET(dir_list ${dir_list} ${file_path}) + ENDFOREACH() + LIST(REMOVE_DUPLICATES dir_list) + SET(${return_list} ${dir_list}) +ENDMACRO() + +MACRO(RECURSIVE_FIND_FILE_EXCLUDE_DIR return_list dir exclude_dir pattern) + FILE(GLOB_RECURSE new_list "${dir}/${pattern}") + SET(dir_list "") + FOREACH(file_path ${new_list}) + IF (file_path MATCHES ".*\/${exclude_dir}\/.*") + continue() + endif() + SET(dir_list ${dir_list} ${file_path}) + ENDFOREACH() + LIST(REMOVE_DUPLICATES dir_list) + SET(${return_list} ${dir_list}) +ENDMACRO() + +MACRO(RECURSIVE_FIND_FILE_APPEND return_list dir pattern) + RECURSIVE_FIND_FILE( append_list ${dir} ${pattern} ) + LIST(APPEND ${return_list} ${append_list}) +ENDMACRO() + +MACRO(SOURCE_FILES return_list dir pattern) + FILE(GLOB new_list "${dir}/${pattern}") + SET(dir_list "") + FOREACH(file_path ${new_list}) + LIST(APPEND dir_list ${file_path}) + ENDFOREACH() + LIST(REMOVE_DUPLICATES dir_list) + SET(${return_list} ${dir_list}) +ENDMACRO() + +function(EXTRACT_JSON_ARRAY json_file json_field_path fields values) + set(VALUES "") + set(FIELDS "") + foreach(var ${${json_file}}) + # extract any cmd line definitions specified in the json object, and add them + # if it is not prefixed by json_field_path, do not consider the key. + if("${var}" MATCHES "${json_field_path}") + string(REGEX MATCH "[^${json_field_path}]([A-Z,a-z,0-9,_,]+)" VALUE "${var}") + # never quote the value - gives more flexibility + list(APPEND FIELDS ${VALUE}) + list(APPEND VALUES "${${var}}") + endif() + endforeach() + set(${fields} ${FIELDS} PARENT_SCOPE) + set(${values} ${VALUES} PARENT_SCOPE) +endfunction() + +function(FORM_DEFINITIONS fields values definitions) + set(DEFINITIONS "") + list(LENGTH ${fields} LEN) + # - 1 for for loop index... + MATH(EXPR LEN "${LEN}-1") + foreach(i RANGE ${LEN}) + list(GET ${fields} ${i} DEFINITION) + list(GET ${values} ${i} VALUE) + set(DEFINITIONS "${DEFINITIONS} #define ${DEFINITION}\t ${VALUE}\n") + endforeach() + set(${definitions} ${DEFINITIONS} PARENT_SCOPE) +endfunction() + +function(UNIQUE_JSON_KEYS priority_fields priority_values secondary_fields secondary_values merged_fields merged_values) + # always keep the first fields and values + set(MERGED_FIELDS ${${priority_fields}}) + set(MERGED_VALUES ${${priority_values}}) + # measure the second set... + list(LENGTH ${secondary_fields} LEN) + # - 1 for for loop index... + MATH(EXPR LEN "${LEN}-1") + # iterate, dropping any duplicate fields regardless of the value + foreach(i RANGE ${LEN}) + list(GET ${secondary_fields} ${i} FIELD) + list(GET ${secondary_values} ${i} VALUE) + list(FIND MERGED_FIELDS ${FIELD} INDEX) + if (${INDEX} GREATER -1) + continue() + endif() + list(APPEND MERGED_FIELDS ${FIELD}) + list(APPEND MERGED_VALUES ${VALUE}) + endforeach() + set(${merged_fields} ${MERGED_FIELDS} PARENT_SCOPE) + set(${merged_values} ${MERGED_VALUES} PARENT_SCOPE) +endfunction() + +MACRO(HEADER_FILES return_list dir) + FILE(GLOB new_list "${dir}/*.h") + SET(${return_list} ${new_list}) +ENDMACRO() + +function(INSTALL_DEPENDENCY dir name url branch type) + if(NOT EXISTS "${CMAKE_CURRENT_LIST_DIR}/${dir}") + message("Creating libraries folder") + FILE(MAKE_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${dir}") + endif() + if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${dir}/${name}") + message("${name} is already installed") + return() + endif() + if(${type} STREQUAL "git") + message("Cloning into: ${url}") + # git clone -b doesn't work with SHAs + execute_process( + COMMAND git clone --recurse-submodules ${url} ${name} + WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/${dir} + ) + if(NOT "${branch}" STREQUAL "") + message("Checking out branch: ${branch}") + execute_process( + COMMAND git -c advice.detachedHead=false checkout ${branch} + WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/${dir}/${name} + ) + execute_process( + COMMAND git submodule update --init + WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/${dir}/${name} + ) + execute_process( + COMMAND git submodule sync + WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/${dir}/${name} + ) + execute_process( + COMMAND git submodule update + WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/${dir}/${name} + ) + endif() + else() + message("No mechanism exists to install this library.") + endif() +endfunction() + +MACRO(SUB_DIRS return_dirs dir) + FILE(GLOB list "${PROJECT_SOURCE_DIR}/${dir}/*") + SET(dir_list "") + FOREACH(file_path ${list}) + SET(dir_list ${dir_list} ${file_path}) + ENDFOREACH() + set(${return_dirs} ${dir_list}) +ENDMACRO() diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/cmake/zephyr/CMakeLists.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/cmake/zephyr/CMakeLists.txt new file mode 100644 index 0000000..5a5e49e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/cmake/zephyr/CMakeLists.txt @@ -0,0 +1,32 @@ +cmake_minimum_required(VERSION 3.13.1) + +if(NOT TARGET app) + message(FATAL_ERROR "Please create a target named 'app' (ex: add_executable(app)) before adding this file") +endif() + +set(CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_STANDARD_REQUIRED ON) + +set(EI_SDK_FOLDER ../../) + +include(${EI_SDK_FOLDER}/cmake/utils.cmake) + +target_include_directories(app PRIVATE + ${EI_SDK_FOLDER} +) + +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}" "*.cpp") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}" "*.cc") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}" "*.s") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/TransformFunctions" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/CommonTables" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/BasicMathFunctions" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/ComplexMathFunctions" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/FastMathFunctions" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/SupportFunctions" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/MatrixFunctions" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/DSP/Source/StatisticsFunctions" "*.c") +RECURSIVE_FIND_FILE_APPEND(EI_SOURCE_FILES "${EI_SDK_FOLDER}/CMSIS/NN/Source" "*.c") +LIST(APPEND EI_SOURCE_FILES "${EI_SDK_FOLDER}/tensorflow/lite/c/common.c") + +target_sources(app PRIVATE ${EI_SOURCE_FILES}) \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/create-arduino-library.sh b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/create-arduino-library.sh new file mode 100644 index 0000000..df70161 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/create-arduino-library.sh @@ -0,0 +1,55 @@ +# Run this script to convert the edge-impulse-sdk folder into a library that can be consumed by the Arduino IDE +# it renames files (e.g. *.cpp to *.c), removes features (uTensor), and updates include paths + +# exit when any command fails +set -e + +cleanup() { + echo "" + echo "Terminated by user" + exit 1 +} +trap cleanup INT TERM + +SCRIPTPATH="$( cd "$(dirname "$0")" ; pwd -P )" + +if [[ "$OSTYPE" == "darwin"* ]]; then + SEDCMD="sed -i '' -e" + ECHOCMD="echo" + LC_CTYPE=C + LANG=C +else + SEDCMD="sed -i -e" + ECHOCMD="echo -e" +fi + +rm -rf $SCRIPTPATH/tensorflow/lite/micro/mbed/ +rm -rf $SCRIPTPATH/porting/mbed/ +rm -rf $SCRIPTPATH/porting/mingw32/ +rm -rf $SCRIPTPATH/porting/posix/ +rm -rf $SCRIPTPATH/porting/silabs/ +rm -rf $SCRIPTPATH/porting/stm32-cubeai/ +rm -rf $SCRIPTPATH/porting/zephyr/ +rm -rf $SCRIPTPATH/porting/sony/ +rm -rf $SCRIPTPATH/porting/ti/ +rm -rf $SCRIPTPATH/porting/lib/ +rm -rf $SCRIPTPATH/porting/raspberry/ +rm -rf $SCRIPTPATH/porting/himax/ +rm -rf $SCRIPTPATH/porting/synaptics/ +rm -rf $SCRIPTPATH/porting/brickml/ +rm -rf $SCRIPTPATH/porting/renesas-ra/ +rm -rf $SCRIPTPATH/classifier/ei_run_classifier_c* +rm -rf $SCRIPTPATH/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S +rm -rf $SCRIPTPATH/third_party/arc_mli_package/ + +# rename all .cc files to .cpp, and do an inplace change of the headers +find . -name '*.cc' -exec sh -c 'mv "$0" "${0%.cc}.cpp"' {} \; + +# make sure that abs is undefined on arduino +find $SCRIPTPATH/ -name 'compatibility.h' -exec bash -c "$SEDCMD 's/#include /#include \\ +#include \"edge-impulse-sdk\/tensorflow\/lite\/portable_type_to_tflitetype.h\"/' {}" {} \; +find $SCRIPTPATH/ -name 'micro_utils.h' -exec bash -c "$SEDCMD 's/#include /#include \\ +#include \"edge-impulse-sdk\/tensorflow\/lite\/portable_type_to_tflitetype.h\"/' {}" {} \; + +# remove all the -e files +find $SCRIPTPATH/ -name "*-e" -exec rm -f {} \; diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/README.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/README.md new file mode 100644 index 0000000..6bf484f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/README.md @@ -0,0 +1,3 @@ +See notes in the various block folders in studio/dsp-pipeline + +studio/dsp-pipeline/mfcc/README.md \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/config.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/config.hpp new file mode 100644 index 0000000..86f638c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/config.hpp @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_CPP_CONFIG_H_ +#define _EIDSP_CPP_CONFIG_H_ + +// clang-format off +#ifndef EIDSP_USE_CMSIS_DSP // __ARM_ARCH_PROFILE is a predefine of arm-gcc. __TARGET_* is armcc +#if defined(__MBED__) || __ARM_ARCH_PROFILE == 'M' || defined(__TARGET_CPU_CORTEX_M0) || defined(__TARGET_CPU_CORTEX_M0PLUS) || defined(__TARGET_CPU_CORTEX_M3) || defined(__TARGET_CPU_CORTEX_M4) || defined(__TARGET_CPU_CORTEX_M7) || defined(USE_HAL_DRIVER) || defined(ARDUINO_NRF52_ADAFRUIT) + // Mbed OS versions before 5.7 are not based on CMSIS5, disable CMSIS-DSP and CMSIS-NN instructions + #if defined(__MBED__) + #include "mbed_version.h" + #if (MBED_VERSION < MBED_ENCODE_VERSION((5), (7), (0))) + #define EIDSP_USE_CMSIS_DSP 0 + #else + #define EIDSP_USE_CMSIS_DSP 1 + #endif // Mbed OS 5.7 version check + + // Arduino on Mbed targets prior to Mbed OS 6.0.0 ship their own CMSIS-DSP sources + #if defined(ARDUINO) && (MBED_VERSION < MBED_ENCODE_VERSION((6), (0), (0))) + #define EIDSP_LOAD_CMSIS_DSP_SOURCES 0 + #else + #define EIDSP_LOAD_CMSIS_DSP_SOURCES 1 + #endif // Mbed OS 6.0 version check + #else + #define EIDSP_USE_CMSIS_DSP 1 + #define EIDSP_LOAD_CMSIS_DSP_SOURCES 1 + #endif +#else + #define EIDSP_USE_CMSIS_DSP 0 +#endif // Mbed / ARM Core check +#endif // ifndef EIDSP_USE_CMSIS_DSP + +#if EIDSP_USE_CMSIS_DSP == 1 +#define EIDSP_i32 int32_t +#define EIDSP_i16 int16_t +#define EIDSP_i8 q7_t +#define ARM_MATH_ROUNDING 1 +#else +#define EIDSP_i32 int32_t +#define EIDSP_i16 int16_t +#define EIDSP_i8 int8_t +#endif // EIDSP_USE_CMSIS_DSP + +#ifndef EIDSP_USE_ASSERTS +#define EIDSP_USE_ASSERTS 0 +#endif // EIDSP_USE_ASSERTS + +#if EIDSP_USE_ASSERTS == 1 +#include +#define EIDSP_ERR(err_code) ei_printf("ERR: %d (%s)\n", err_code, #err_code); assert(false) +#else // EIDSP_USE_ASSERTS == 0 +#define EIDSP_ERR(err_code) return(err_code) +#endif + +// To save memory you can quantize the filterbanks, +// this has an effect on runtime speed as CMSIS-DSP does not have optimized instructions +// for q7 matrix multiplication and matrix transformation... +#ifndef EIDSP_QUANTIZE_FILTERBANK +#define EIDSP_QUANTIZE_FILTERBANK 1 +#endif // EIDSP_QUANTIZE_FILTERBANK + +// prints buffer allocations to stdout, useful when debugging +#ifndef EIDSP_TRACK_ALLOCATIONS +#define EIDSP_TRACK_ALLOCATIONS 0 +#endif // EIDSP_TRACK_ALLOCATIONS + +// set EIDSP_TRACK_ALLOCATIONS=1 and EIDSP_PRINT_ALLOCATIONS=0 +// to track but not print allocations +#ifndef EIDSP_PRINT_ALLOCATIONS +#define EIDSP_PRINT_ALLOCATIONS 1 +#endif + +#ifndef EIDSP_SIGNAL_C_FN_POINTER +#define EIDSP_SIGNAL_C_FN_POINTER 0 +#endif // EIDSP_SIGNAL_C_FN_POINTER + +// clang-format on +#endif // _EIDSP_CPP_CONFIG_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/.clang-format b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/.clang-format new file mode 100644 index 0000000..20ffce8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/.clang-format @@ -0,0 +1,2 @@ +"DisableFormat": true +"SortIncludes": false diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/LICENSE b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/LICENSE new file mode 100644 index 0000000..08a96e9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/LICENSE @@ -0,0 +1,18 @@ +Copyright (c) 2018 Project Nayuki. (MIT License) +https://www.nayuki.io/page/fast-discrete-cosine-transform-algorithms + +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: +- The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. +- The Software is provided "as is", without warranty of any kind, express or + implied, including but not limited to the warranties of merchantability, + fitness for a particular purpose and noninfringement. In no event shall the + authors or copyright holders be liable for any claim, damages or other + liability, whether in an action of contract, tort or otherwise, arising from, + out of or in connection with the Software or the use or other dealings in the + Software. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/README.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/README.md new file mode 100644 index 0000000..90be487 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/README.md @@ -0,0 +1,3 @@ +# Fast discrete cosine transform algorithms (C) + +DCT type 2 and type 3 algorithms based on https://www.nayuki.io/page/fast-discrete-cosine-transform-algorithms. These are modified to use KissFFT or hardware accelerated RFFT support with CMSIS-DSP. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/fast-dct-fft.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/fast-dct-fft.cpp new file mode 100644 index 0000000..27420ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/fast-dct-fft.cpp @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2022 Project Nayuki. (MIT License) + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "fast-dct-fft.h" +#include "../returntypes.hpp" +#include "../numpy.hpp" +#include "../memory.hpp" + +#ifndef M_PI +#define M_PI 3.14159265358979323846264338327950288 +#endif // M_PI + +// DCT type II, unscaled +int ei::dct::transform(float vector[], size_t len) { + const size_t fft_data_out_size = (len / 2 + 1) * sizeof(ei::fft_complex_t); + const size_t fft_data_in_size = len * sizeof(float); + + // Allocate KissFFT input / output buffer + fft_complex_t *fft_data_out = + (ei::fft_complex_t*)ei_dsp_calloc(fft_data_out_size, 1); + if (!fft_data_out) { + return ei::EIDSP_OUT_OF_MEM; + } + + float *fft_data_in = (float*)ei_dsp_calloc(fft_data_in_size, 1); + if (!fft_data_in) { + ei_dsp_free(fft_data_out, fft_data_out_size); + return ei::EIDSP_OUT_OF_MEM; + } + + // Preprocess the input buffer with the data from the vector + size_t halfLen = len / 2; + for (size_t i = 0; i < halfLen; i++) { + fft_data_in[i] = vector[i * 2]; + fft_data_in[len - 1 - i] = vector[i * 2 + 1]; + } + if (len % 2 == 1) { + fft_data_in[halfLen] = vector[len - 1]; + } + + int r = ei::numpy::rfft(fft_data_in, len, fft_data_out, (len / 2 + 1), len); + if (r != 0) { + ei_dsp_free(fft_data_in, fft_data_in_size); + ei_dsp_free(fft_data_out, fft_data_out_size); + return r; + } + + size_t i = 0; + for (; i < len / 2 + 1; i++) { + float temp = i * M_PI / (len * 2); + vector[i] = fft_data_out[i].r * cos(temp) + fft_data_out[i].i * sin(temp); + } + //take advantage of hermetian symmetry to calculate remainder of signal + for (; i < len; i++) { + float temp = i * M_PI / (len * 2); + int conj_idx = len-i; + // second half bins not calculated would have just been the conjugate of the first half (note minus of imag) + vector[i] = fft_data_out[conj_idx].r * cos(temp) - fft_data_out[conj_idx].i * sin(temp); + } + ei_dsp_free(fft_data_in, fft_data_in_size); + ei_dsp_free(fft_data_out, fft_data_out_size); + + return 0; +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/fast-dct-fft.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/fast-dct-fft.h new file mode 100644 index 0000000..e31efe1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/dct/fast-dct-fft.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2022 Project Nayuki. (MIT License) + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __FAST_DCT_FFT__H__ +#define __FAST_DCT_FFT__H__ + + +#include +#include +#include "../kissfft/kiss_fft.h" + +namespace ei { +namespace dct { + +int transform(float vector[], size_t len); +int inverse_transform(float vector[], size_t len); + +} // namespace dct +} // namespace ei + +#endif //!__FAST-DCT-FFT__H__ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_alloc.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_alloc.h new file mode 100644 index 0000000..6690570 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_alloc.h @@ -0,0 +1,79 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef __EI_ALLOC__H__ +#define __EI_ALLOC__H__ + +#include "memory.hpp" + +#if EIDSP_TRACK_ALLOCATIONS +#include +#endif + +namespace ei { + +template +struct EiAlloc +{ + typedef T value_type; + EiAlloc() = default; + template + constexpr EiAlloc(const EiAlloc &) noexcept {} + + T *allocate(size_t n) + { + auto bytes = n * sizeof(T); + auto ptr = ei_dsp_malloc(bytes); +#if EIDSP_TRACK_ALLOCATIONS + get_allocs()[ptr] = bytes; +#endif + return (T *)ptr; + } + + void deallocate(T *p, size_t n) noexcept + { +#if EIDSP_TRACK_ALLOCATIONS + auto size_p = get_allocs().find(p); + ei_dsp_free(p,size_p->second); + get_allocs().erase(size_p); +#else + ei_dsp_free(p,0); +#endif + } +#if EIDSP_TRACK_ALLOCATIONS + private: + // [address] -> size requested + typedef std::map map_t; + static map_t& get_allocs() { + static map_t allocs; + return allocs; + } +#endif +}; + +template +bool operator==(const EiAlloc &, const EiAlloc &) { return true; } +template +bool operator!=(const EiAlloc &, const EiAlloc &) { return false; } +} + +#endif //!__EI_ALLOC__H__ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_dsp_handle.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_dsp_handle.h new file mode 100644 index 0000000..462117a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_dsp_handle.h @@ -0,0 +1,58 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef __EI_DSP_HANDLE__H__ +#define __EI_DSP_HANDLE__H__ + +#include "edge-impulse-sdk/dsp/config.hpp" +#include "edge-impulse-sdk/dsp/numpy_types.h" + +class DspHandle { +public: + /** + * @brief Override and call ei_printf to print debug information, especially the current state + * + * @return int + */ + virtual int print() = 0; + + /** + * @brief Override and convert raw data into processed features. Any state should live inside your custom class. + * Provide a constructor to initialize your state. + * + * @param signal Callback object to get raw data from + * @param output_matrix Output matrix to write features to + * @param config Configuration object, generated by Studio based on your DSP block parameters + * @param frequency Sampling frequency, as set in your project + * @return int 0 on success, anything else for failure + */ + virtual int extract(ei::signal_t *signal, ei::matrix_t *output_matrix, void *config, const float frequency) = 0; + + // Must declare so user can override + /** + * @brief If you call new or ei_malloc anywhere in your class, you must override this function and delete your objects + * + */ + virtual ~DspHandle() {}; +}; + +#endif //!__EI_DSP_HANDLE__H__ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_flatten.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_flatten.h new file mode 100644 index 0000000..d7586b2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_flatten.h @@ -0,0 +1,198 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef __EI_FLATTEN__H__ +#define __EI_FLATTEN__H__ + +#include "edge-impulse-sdk/dsp/ei_vector.h" +#include "edge-impulse-sdk/dsp/returntypes.hpp" +#include "edge-impulse-sdk/dsp/ei_dsp_handle.h" +#include "model-parameters/model_metadata.h" +#include "edge-impulse-sdk/dsp/numpy.hpp" +#include "edge-impulse-sdk/dsp/config.hpp" + +class flatten_class : public DspHandle { +public: + int print() override { + ei_printf("means: "); + for(int axis = 0; (size_t)axis < this->means.size(); axis++) { + ei_printf("axis: %i\n", axis); + for (size_t i = 0; i < this->means.size(); i++) { + ei_printf("%f ", this->means[axis][i]); + } + } + ei_printf("\n"); + return ei::EIDSP_OK; + } + + int extract(ei::signal_t *signal, ei::matrix_t *output_matrix, void *config_ptr, const float frequency) override { + using namespace ei; + + ei_dsp_config_flatten_t config = *((ei_dsp_config_flatten_t*)config_ptr); + + uint32_t expected_matrix_size = 0; + if (config.average) expected_matrix_size += config.axes; + if (config.minimum) expected_matrix_size += config.axes; + if (config.maximum) expected_matrix_size += config.axes; + if (config.rms) expected_matrix_size += config.axes; + if (config.stdev) expected_matrix_size += config.axes; + if (config.skewness) expected_matrix_size += config.axes; + if (config.kurtosis) expected_matrix_size += config.axes; + if (config.moving_avg_num_windows) expected_matrix_size += config.axes; + + if (output_matrix->rows * output_matrix->cols != expected_matrix_size) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + int ret; + + // input matrix from the raw signal + matrix_t input_matrix(signal->total_length / config.axes, config.axes); + if (!input_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + signal->get_data(0, signal->total_length, input_matrix.buffer); + + // scale the signal + ret = numpy::scale(&input_matrix, config.scale_axes); + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to scale signal (%d)\n", ret); + EIDSP_ERR(ret); + } + + // transpose the matrix so we have one row per axis + numpy::transpose_in_place(&input_matrix); + + size_t out_matrix_ix = 0; + + for (size_t row = 0; row < input_matrix.rows; row++) { + matrix_t row_matrix(1, input_matrix.cols, input_matrix.buffer + (row * input_matrix.cols)); + + float mean; // to use with moving average + + if (config.average || config.moving_avg_num_windows) { + float fbuffer; + matrix_t out_matrix(1, 1, &fbuffer); + numpy::mean(&row_matrix, &out_matrix); + mean = out_matrix.buffer[0]; + if (config.average) { + output_matrix->buffer[out_matrix_ix++] = mean; + } + } + + if (config.minimum) { + float fbuffer; + matrix_t out_matrix(1, 1, &fbuffer); + numpy::min(&row_matrix, &out_matrix); + output_matrix->buffer[out_matrix_ix++] = out_matrix.buffer[0]; + } + + if (config.maximum) { + float fbuffer; + matrix_t out_matrix(1, 1, &fbuffer); + numpy::max(&row_matrix, &out_matrix); + output_matrix->buffer[out_matrix_ix++] = out_matrix.buffer[0]; + } + + if (config.rms) { + float fbuffer; + matrix_t out_matrix(1, 1, &fbuffer); + numpy::rms(&row_matrix, &out_matrix); + output_matrix->buffer[out_matrix_ix++] = out_matrix.buffer[0]; + } + + if (config.stdev) { + float fbuffer; + matrix_t out_matrix(1, 1, &fbuffer); + numpy::stdev(&row_matrix, &out_matrix); + output_matrix->buffer[out_matrix_ix++] = out_matrix.buffer[0]; + } + + if (config.skewness) { + float fbuffer; + matrix_t out_matrix(1, 1, &fbuffer); + numpy::skew(&row_matrix, &out_matrix); + output_matrix->buffer[out_matrix_ix++] = out_matrix.buffer[0]; + } + + if (config.kurtosis) { + float fbuffer; + matrix_t out_matrix(1, 1, &fbuffer); + numpy::kurtosis(&row_matrix, &out_matrix); + output_matrix->buffer[out_matrix_ix++] = out_matrix.buffer[0]; + } + + if (config.moving_avg_num_windows) { + push_mean(row, mean); + output_matrix->buffer[out_matrix_ix++] = numpy::mean(means[row].data(), means[row].size()); + } + } + + // flatten again + output_matrix->cols = output_matrix->rows * output_matrix->cols; + output_matrix->rows = 1; + + return EIDSP_OK; + } + + static DspHandle* create(void* config, float _sampling_frequency); + + void* operator new(size_t size) { + // Custom memory allocation logic here + return ei_malloc(size); + } + + void operator delete(void* ptr) { + // Custom memory deallocation logic here + ei_free(ptr); + } + +private: + ei_vector> means; + ei_vector head_indexes; + size_t moving_avg_num_windows; + + flatten_class(int moving_avg_num_windows, int axes_count) : means(axes_count), head_indexes(axes_count, 0) { + this->moving_avg_num_windows = moving_avg_num_windows; + } + + void push_mean(int axis, float mean) { + auto& head = head_indexes[axis]; + if (head_indexes[axis] >= means[axis].size()) { + means[axis].push_back(mean); + } else { + means[axis][head] = mean; + } + head = head + 1; + // This is a lot cheaper than mod (%) + if (head >= moving_avg_num_windows) { + head = 0; + } + } +}; + +DspHandle* flatten_class::create(void* config_in, float _sampling_frequency) { // NOLINT def in header is OK at EI + auto config = reinterpret_cast(config_in); + return new flatten_class(config->moving_avg_num_windows, config->axes); +}; + +#endif //!__EI_FLATTEN__H__ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_hr.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_hr.hpp new file mode 100644 index 0000000..816191e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_hr.hpp @@ -0,0 +1,156 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef HR_PPG_HPP +#define HR_PPG_HPP + +#include "edge-impulse-sdk/dsp/numpy.hpp" +#include "edge-impulse-sdk/dsp/ei_dsp_handle.h" +#include "edge-impulse-enterprise/hr/hr_ppg.hpp" +#include "edge-impulse-enterprise/hr/hrv.hpp" +#include "edge-impulse-sdk/dsp/memory.hpp" + +// Need a wrapper to get ei_malloc used +// cppyy didn't like this override for some reason +class hrv_wrap : public ei::hrv::beats_to_hrv { +public: + // Boilerplate below here + void* operator new(size_t size) { + // Custom memory allocation logic here + return ei_malloc(size); + } + + void operator delete(void* ptr) { + // Custom memory deallocation logic here + ei_free(ptr); + } + // end boilerplate + + // Use the same constructor as the parent + using ei::hrv::beats_to_hrv::beats_to_hrv; +}; + +class hr_class : public DspHandle { +public: + int print() override { + ei_printf("Last HR: %f\n", ppg._res.hr); + return ei::EIDSP_OK; + } + + int extract(ei::signal_t *signal, ei::matrix_t *output_matrix, void *config_ptr, const float frequency) override { + using namespace ei; + + // Using reference avoids a copy + ei_dsp_config_hr_t& config = *((ei_dsp_config_hr_t*)config_ptr); + size_t floats_per_inc = ppg.win_inc_samples * ppg.axes; + size_t hrv_inc_samples = config.hrv_update_interval_s * frequency * ppg.axes; + // Greater than b/c can have multiple increments (HRs) per window + assert(signal->total_length >= floats_per_inc); + + int out_idx = 0; + size_t hrv_count = 0; + for(size_t i = 0; i < signal->total_length; i += floats_per_inc) { + // TODO ask for smaller increments and bp them into place + // Copy into the end of the buffer + matrix_t temp(ppg.win_inc_samples, ppg.axes); + signal->get_data(i, floats_per_inc, temp.buffer); + auto hr = ppg.stream(&temp); + if(!hrv || (hrv && config.include_hr)) { + output_matrix->buffer[out_idx++] = hr; + } + if(hrv) { + auto peaks = ppg.get_peaks(); + hrv->add_streaming_beats(peaks); + hrv_count += floats_per_inc; + if(hrv_count >= hrv_inc_samples) { + fvec features = hrv->get_hrv_features(0); + for(size_t j = 0; j < features.size(); j++) { + output_matrix->buffer[out_idx++] = features[j]; + } + hrv_count = 0; + } + } + } + return EIDSP_OK; + } + + hr_class(ei_dsp_config_hr_t* config, float frequency) + : ppg(frequency, + config->axes, + frequency * 8, // TODO variable window + frequency * 2, // TODO variable overlap + config->filter_preset, + config->acc_resting_std, + config->sensitivity, + true), hrv(nullptr) + { + auto table = config->named_axes; + for( size_t i = 0; i < config->named_axes_size; i++ ) { + ppg.set_offset_table(i, table[i].axis); + } + // if not "none" + if(strcmp(config->hrv_features,"none") != 0) { + // new is overloaded to use ei_malloc + hrv = new hrv_wrap( + frequency, + config->hrv_features, + config->hrv_update_interval_s, + config->hrv_win_size_s, + 2); // TODO variable window? + } + } + + ~hr_class() { + if(hrv) { + // delete is overloaded to use ei_free + delete hrv; + } + } + + // Boilerplate below here + static DspHandle* create(void* config, float frequency); + + void* operator new(size_t size) { + // Custom memory allocation logic here + return ei_malloc(size); + } + + void operator delete(void* ptr) { + // Custom memory deallocation logic here + ei_free(ptr); + } + // end boilerplate +private: + ei::hr_ppg ppg; + hrv_wrap* hrv; // pointer b/c we don't always need it +}; + +DspHandle* hr_class::create(void* config_in, float frequency) { // NOLINT def in header is OK at EI + auto config = reinterpret_cast(config_in); + return new hr_class(config, frequency); +}; + +/* +NOTE, contact EI sales for license and source to use EI heart rate and heart rate variance functions in deployment +*/ + +#endif \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_profiler.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_profiler.h new file mode 100644 index 0000000..365d9e0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_profiler.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EIPROFILER__H__ +#define __EIPROFILER__H__ + +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" + +class EiProfiler { +public: + EiProfiler() + { + reset(); + } + void reset() + { + timestamp = ei_read_timer_ms(); + } + void report(const char *message) + { + ei_printf("%s took %llu\r\n", message, ei_read_timer_ms() - timestamp); + timestamp = ei_read_timer_ms(); //read again to not count printf time + } + +private: + uint64_t timestamp; +}; + +#endif //!__EIPROFILER__H__ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_utils.h new file mode 100644 index 0000000..2a2c5e8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/ei_utils.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __EI_UTILS__H__ +#define __EI_UTILS__H__ + +#define ARRAY_LENGTH(array) (sizeof((array))/sizeof((array)[0])) + +// Stringify +#define ei_xstr(a) ei_str(a) +#define ei_str(a) #a + +// Bit manipulation + +//Set bit y (0-indexed) of x to '1' by generating a a mask with a '1' in the proper bit location and ORing x with the mask. +#define SET_BIT_POS(x,y) (x |= (1 << y)) + +//Set bit y (0-indexed) of x to '0' by generating a mask with a '0' in the y position and 1's elsewhere then ANDing the mask with x. +#define CLEAR_BIT_POS(x,y) (x &= ~(1<< y)) + +//Return '1' if the bit value at position y within x is '1' and '0' if it's 0 by ANDing x with a bit mask where the bit in y's position is '1' and '0' elsewhere and comparing it to all 0's. Returns '1' in least significant bit position if the value of the bit is '1', '0' if it was '0'. +#define TEST_BIT_POS(x,y) ((0u == (x & (1< + +template +using ei_vector = std::vector>; + +#endif //!__EI_VECTOR__H__ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/image.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/image.hpp new file mode 100644 index 0000000..12c0da4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/image.hpp @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_IMAGE_H_ +#define _EIDSP_IMAGE_H_ + +#include "edge-impulse-sdk/dsp/image/processing.hpp" + +#endif \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/processing.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/processing.cpp new file mode 100644 index 0000000..5ff30c6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/processing.cpp @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EIDSP_IMAGE_PROCESSING__H__ +#define __EIDSP_IMAGE_PROCESSING__H__ + +#include "edge-impulse-sdk/dsp/ei_utils.h" +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/dsp/returntypes.hpp" +#include "edge-impulse-sdk/dsp/image/processing.hpp" + +namespace ei { namespace image { namespace processing { + +enum YUV_OPTIONS +{ + BIG_ENDIAN_ORDER = 1, //RGB reading from low to high memory. Otherwise, uses native encoding + PAD_4B = 2, // pad 0x00 on the high B. ie 0x00RRGGBB +}; + +/** + * @brief Convert YUV to RGB + * + * @param rgb_out Output buffer (can be the same as yuv_in if big enough) + * @param yuv_in Input buffer + * @param in_size_B Size of input image in B + * @param opts Note, only BIG_ENDIAN_ORDER supported presently + */ +int yuv422_to_rgb888( + unsigned char *rgb_out, + unsigned const char *yuv_in, + unsigned int in_size_B, + YUV_OPTIONS opts) +{ + + // Clamp out of range values + #define EI_CLAMP(t) (((t) > 255) ? 255 : (((t) < 0) ? 0 : (t))) + + // Color space conversion for RGB + #define EI_GET_R_FROM_YUV(y, u, v) ((298 * y + 409 * v + 128) >> 8) + #define EI_GET_G_FROM_YUV(y, u, v) ((298 * y - 100 * u - 208 * v + 128) >> 8) + #define EI_GET_B_FROM_YUV(y, u, v) ((298 * y + 516 * u + 128) >> 8) + + unsigned int in_size_pixels = in_size_B / 4; + yuv_in += in_size_B - 1; + + int rgb_end = TEST_BIT_MASK(opts, PAD_4B) ? 2 * in_size_B : (6 * in_size_B) / 4; + rgb_out += rgb_end - 1; + + // Going backwards probably looks strange, but + // This allows us to do the algorithm in place! + // User needs to put the YUV image into a larger buffer than necessary + // But going backwards means we don't overwrite the YUV bytes + // until we don't need them anymore + for (unsigned int i = 0; i < in_size_pixels; ++i) { + int y2 = *yuv_in-- - 16; + int v = *yuv_in-- - 128; + int y0 = *yuv_in-- - 16; + int u0 = *yuv_in-- - 128; + + if (TEST_BIT_MASK(opts, BIG_ENDIAN_ORDER)) { + *rgb_out-- = EI_CLAMP(EI_GET_B_FROM_YUV(y2, u0, v)); + *rgb_out-- = EI_CLAMP(EI_GET_G_FROM_YUV(y2, u0, v)); + *rgb_out-- = EI_CLAMP(EI_GET_R_FROM_YUV(y2, u0, v)); + if (TEST_BIT_MASK(opts, PAD_4B)) { + *rgb_out-- = 0; + } + + *rgb_out-- = EI_CLAMP(EI_GET_B_FROM_YUV(y0, u0, v)); + *rgb_out-- = EI_CLAMP(EI_GET_G_FROM_YUV(y0, u0, v)); + *rgb_out-- = EI_CLAMP(EI_GET_R_FROM_YUV(y0, u0, v)); + if (TEST_BIT_MASK(opts, PAD_4B)) { + *rgb_out-- = 0; + } + } + else { + // not yet supported + return EIDSP_NOT_SUPPORTED; + } + } + return EIDSP_OK; +} + +/** + * @brief Crops an image. Can be in-place. 4B alignment for best performance + * (Alignment is tested, will fall back to B by B movement) + * + * @param srcWidth X dimension in pixels + * @param srcHeight Y dimension in pixels + * @param srcImage Input buffer + * @param startX X coord of first pixel to keep + * @param startY Y coord of the first pixel to keep + * @param dstWidth Desired X dimension in pixels (should be smaller than srcWidth) + * @param dstHeight Desired Y dimension in pixels (should be smaller than srcHeight) + * @param dstImage Output buffer, can be the same as srcImage + * @param iBpp 8 or 16 for bits per pixel + */ +int cropImage( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + int startX, + int startY, + uint8_t *dstImage, + int dstWidth, + int dstHeight, + int iBpp) +{ + uint32_t *s32, *d32; + int x, y; + + if (startX < 0 || startX >= srcWidth || startY < 0 || startY >= srcHeight || + (startX + dstWidth) > srcWidth || (startY + dstHeight) > srcHeight) { + return EIDSP_PARAMETER_INVALID; // invalid parameters + } + if (iBpp != 8 && iBpp != 16) { + return EIDSP_PARAMETER_INVALID; + } + + if (iBpp == 8) { + const uint8_t *s; + uint8_t *d; + for (y = 0; y < dstHeight; y++) { + s = &srcImage[srcWidth * (y + startY) + startX]; + d = &dstImage[(dstWidth * y)]; + x = 0; + if ((intptr_t)s & 3 || (intptr_t)d & 3) { // either src or dst pointer is not aligned + for (; x < dstWidth; x++) { + *d++ = *s++; // have to do it byte-by-byte + } + } + else { + // move 4 bytes at a time if aligned or alignment not enforced + s32 = (uint32_t *)s; + d32 = (uint32_t *)d; + for (; x < dstWidth - 3; x += 4) { + *d32++ = *s32++; + } + // any remaining stragglers? + s = (uint8_t *)s32; + d = (uint8_t *)d32; + for (; x < dstWidth; x++) { + *d++ = *s++; + } + } + } // for y + } // 8-bpp + else { + uint16_t *s, *d; + for (y = 0; y < dstHeight; y++) { + s = (uint16_t *)&srcImage[2 * srcWidth * (y + startY) + startX * 2]; + d = (uint16_t *)&dstImage[(dstWidth * y * 2)]; + x = 0; + if ((intptr_t)s & 2 || (intptr_t)d & 2) { // either src or dst pointer is not aligned + for (; x < dstWidth; x++) { + *d++ = *s++; // have to do it 16-bits at a time + } + } + else { + // move 4 bytes at a time if aligned or alignment no enforced + s32 = (uint32_t *)s; + d32 = (uint32_t *)d; + for (; x < dstWidth - 1; x += 2) { // we can move 2 pixels at a time + *d32++ = *s32++; + } + // any remaining stragglers? + s = (uint16_t *)s32; + d = (uint16_t *)d32; + for (; x < dstWidth; x++) { + *d++ = *s++; + } + } + } // for y + } // 16-bpp case + + return EIDSP_OK; +} /* cropImage() */ + +/** + * @copydoc cropImage( + int srcWidth, + int srcHeight, + const uint8_t *srcImage, + int startX, + int startY, + int dstWidth, + int dstHeight, + uint8_t *dstImage, + int iBpp) + */ +int crop_image_rgb888_packed( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + int startX, + int startY, + uint8_t *dstImage, + int dstWidth, + int dstHeight) +{ + // use 8 bpp mode, but do everything *3 for RGB + return cropImage( + srcImage, + srcWidth * 3, + srcHeight, + startX * 3, + startY, + dstImage, + dstWidth * 3, + dstHeight, + 8); +} + +/** + * @brief Resize an image using interpolation + * Can be used to resize the image smaller or larger + * If resizing much smaller than 1/3 size, then a more rubust algorithm should average all of the pixels + * This algorithm uses bilinear interpolation - averages a 2x2 region to generate each new pixel + * + * @param srcWidth Input image width in pixels + * @param srcHeight Input image height in pixels + * @param srcImage Input buffer + * @param dstWidth Output image width in pixels + * @param dstHeight Output image height in pixels + * @param dstImage Output buffer, can be same as input buffer + * @param pixel_size_B Size of pixels in Bytes. 3 for RGB, 1 for mono + */ +int resize_image( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + uint8_t *dstImage, + int dstWidth, + int dstHeight, + int pixel_size_B) +{ +// Copied from ei_camera.cpp in firmware-eta-compute +// Modified for RGB888 +// This needs to be < 16 or it won't fit. Cortex-M4 only has SIMD for signed multiplies + constexpr int FRAC_BITS = 14; + constexpr int FRAC_VAL = (1 << FRAC_BITS); + constexpr int FRAC_MASK = (FRAC_VAL - 1); + + uint32_t src_x_accum, src_y_accum; // accumulators and fractions for scaling the image + uint32_t x_frac, nx_frac, y_frac, ny_frac; + int x, y, ty; + + if (srcHeight < 2) { + return EIDSP_PARAMETER_INVALID; + } + + // start at 1/2 pixel in to account for integer downsampling which might miss pixels + src_y_accum = FRAC_VAL / 2; + const uint32_t src_x_frac = (srcWidth * FRAC_VAL) / dstWidth; + const uint32_t src_y_frac = (srcHeight * FRAC_VAL) / dstHeight; + + //from here out, *3 b/c RGB + srcWidth *= pixel_size_B; + //srcHeight not used for indexing + //dstWidth still needed as is + //dstHeight shouldn't be scaled + + const uint8_t *s; + uint8_t *d; + + for (y = 0; y < dstHeight; y++) { + // do indexing computations + ty = src_y_accum >> FRAC_BITS; // src y + y_frac = src_y_accum & FRAC_MASK; + src_y_accum += src_y_frac; + ny_frac = FRAC_VAL - y_frac; // y fraction and 1.0 - y fraction + + s = &srcImage[ty * srcWidth]; + d = &dstImage[y * dstWidth * pixel_size_B]; //not scaled above + // start at 1/2 pixel in to account for integer downsampling which might miss pixels + src_x_accum = FRAC_VAL / 2; + for (x = 0; x < dstWidth; x++) { + uint32_t tx, p00, p01, p10, p11; + // do indexing computations + tx = (src_x_accum >> FRAC_BITS) * pixel_size_B; + x_frac = src_x_accum & FRAC_MASK; + nx_frac = FRAC_VAL - x_frac; // x fraction and 1.0 - x fraction + src_x_accum += src_x_frac; + + //interpolate and write out + for (int color = 0; color < pixel_size_B; + color++) // do pixel_size_B times for pixel_size_B colors + { + p00 = s[tx]; + p10 = s[tx + pixel_size_B]; + p01 = s[tx + srcWidth]; + p11 = s[tx + srcWidth + pixel_size_B]; + p00 = ((p00 * nx_frac) + (p10 * x_frac) + FRAC_VAL / 2) >> FRAC_BITS; // top line + p01 = ((p01 * nx_frac) + (p11 * x_frac) + FRAC_VAL / 2) >> FRAC_BITS; // bottom line + p00 = ((p00 * ny_frac) + (p01 * y_frac) + FRAC_VAL / 2) >> FRAC_BITS; //top + bottom + *d++ = (uint8_t)p00; // store new pixel + //ready next loop + tx++; + } + } // for x + } // for y + return EIDSP_OK; +} // resizeImage() + +/** + * @brief Calculate new dims that match the aspect ratio of destination + * This prevents a squashed look + * The smallest axis is held constant + * + * @param srcWidth Input width in pixels + * @param srcHeight Input height in pixels + * @param dstWidth Ultimate width in pixels + * @param dstHeight Ultimate height in pixels + * @param[out] cropWidth Width in pixels that matches the aspect ratio + * @param[out] cropHeight Height in pixels that matches the aspect ratio + */ +void calculate_crop_dims( + int srcWidth, + int srcHeight, + int dstWidth, + int dstHeight, + int &cropWidth, + int &cropHeight) +{ + //first, trim the largest axis to match destination aspect ratio + //calculate by fixing the smaller axis + if (srcWidth > srcHeight) { + cropWidth = (uint32_t)(dstWidth * srcHeight) / dstHeight; //cast in case int is small + cropHeight = srcHeight; + } + else { + cropHeight = (uint32_t)(dstHeight * srcWidth) / dstWidth; + cropWidth = srcWidth; + } +} + +int crop_and_interpolate_rgb888( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + uint8_t *dstImage, + int dstWidth, + int dstHeight) +{ + int cropWidth, cropHeight; + // What are dimensions that maintain aspect ratio? + calculate_crop_dims(srcWidth, srcHeight, dstWidth, dstHeight, cropWidth, cropHeight); + // Now crop to that dimension + int res = crop_image_rgb888_packed( + srcImage, + srcWidth, + srcHeight, + (srcWidth - cropWidth) / 2, + (srcHeight - cropHeight) / 2, + dstImage, + cropWidth, + cropHeight); + + if( res != EIDSP_OK) { return res; } + // Finally, interpolate down to desired dimensions, in place + return resize_image(dstImage, cropWidth, cropHeight, dstImage, dstWidth, dstHeight, 3); +} + +int crop_and_interpolate_image( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + uint8_t *dstImage, + int dstWidth, + int dstHeight, + int pixel_size_B) +{ + int cropWidth, cropHeight; + // What are dimensions that maintain aspect ratio? + calculate_crop_dims(srcWidth, srcHeight, dstWidth, dstHeight, cropWidth, cropHeight); + + // Now crop to that dimension + int res = cropImage( + srcImage, + srcWidth * pixel_size_B, + srcHeight, + ((srcWidth - cropWidth) / 2) * pixel_size_B, + (srcHeight - cropHeight) / 2, + dstImage, + cropWidth * pixel_size_B, + cropHeight, + 8); + + if( res != EIDSP_OK) { return res; } + + // Finally, interpolate down to desired dimensions, in place + return resize_image(dstImage, cropWidth, cropHeight, dstImage, dstWidth, dstHeight, pixel_size_B); +} + +}}} //namespaces +#endif //!__EI_IMAGE_PROCESSING__H__ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/processing.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/processing.hpp new file mode 100644 index 0000000..de8a3be --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/image/processing.hpp @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EIDSP_IMAGE_PROCESSING__H__ +#define __EIDSP_IMAGE_PROCESSING__H__ + +#include "edge-impulse-sdk/dsp/ei_utils.h" +#include "edge-impulse-sdk/porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/dsp/returntypes.hpp" + +namespace ei { namespace image { namespace processing { + +enum YUV_OPTIONS +{ + BIG_ENDIAN_ORDER = 1, //RGB reading from low to high memory. Otherwise, uses native encoding + PAD_4B = 2, // pad 0x00 on the high B. ie 0x00RRGGBB +}; + +/** + * @brief Convert YUV to RGB + * + * @param rgb_out Output buffer (can be the same as yuv_in if big enough) + * @param yuv_in Input buffer + * @param in_size_B Size of input image in B + * @param opts Note, only BIG_ENDIAN_ORDER supported presently + */ +int yuv422_to_rgb888( + unsigned char *rgb_out, + unsigned const char *yuv_in, + unsigned int in_size_B, + YUV_OPTIONS opts); + +/** + * @brief Crops an image. Can be in-place. 4B alignment for best performance + * (Alignment is tested, will fall back to B by B movement) + * + * @param srcWidth X dimension in pixels + * @param srcHeight Y dimension in pixels + * @param srcImage Input buffer + * @param startX X coord of first pixel to keep + * @param startY Y coord of the first pixel to keep + * @param dstWidth Desired X dimension in pixels (should be smaller than srcWidth) + * @param dstHeight Desired Y dimension in pixels (should be smaller than srcHeight) + * @param dstImage Output buffer, can be the same as srcImage + * @param iBpp 8 or 16 for bits per pixel + */ +int cropImage( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + int startX, + int startY, + uint8_t *dstImage, + int dstWidth, + int dstHeight, + int iBpp); + +/** + * @copydoc cropImage( + int srcWidth, + int srcHeight, + const uint8_t *srcImage, + int startX, + int startY, + int dstWidth, + int dstHeight, + uint8_t *dstImage, + int iBpp) + */ +void crop_image_rgb888_packed( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + int startX, + int startY, + uint8_t *dstImage, + int dstWidth, + int dstHeight); + +constexpr int RGB888_B_SIZE = 3; +constexpr int MONO_B_SIZE = 1; + +/** + * @brief Resize an image using interpolation + * Can be used to resize the image smaller or larger + * If resizing much smaller than 1/3 size, then a more rubust algorithm should average all of the pixels + * This algorithm uses bilinear interpolation - averages a 2x2 region to generate each new pixel + * + * @param srcWidth Input image width in pixels + * @param srcHeight Input image height in pixels + * @param srcImage Input buffer + * @param dstWidth Output image width in pixels + * @param dstHeight Output image height in pixels + * @param dstImage Output buffer, can be same as input buffer + * @param pixel_size_B Size of pixels in Bytes. 3 for RGB, 1 for mono + */ +void resize_image( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + uint8_t *dstImage, + int dstWidth, + int dstHeight, + int pixel_size_B); + +/** + * @brief Calculate new dims that match the aspect ratio of destination + * This prevents a squashed look + * The smallest axis is held constant + * + * @param srcWidth Input width in pixels + * @param srcHeight Input height in pixels + * @param dstWidth Ultimate width in pixels + * @param dstHeight Ultimate height in pixels + * @param[out] cropWidth Width in pixels that matches the aspect ratio + * @param[out] cropHeight Height in pixels that matches the aspect ratio + */ +void calculate_crop_dims( + int srcWidth, + int srcHeight, + int dstWidth, + int dstHeight, + int &cropWidth, + int &cropHeight); + +/** + * @brief Crops, then interpolates to a desired new image size + * Can be done in place (set srcImage == dstImage) + * + * @param srcImage Input image buffer + * @param srcWidth Input width in pixels + * @param srcHeight Input height in pixels + * @param dstImage Output image buffer, can be same as input buffer + * @param dstWidth Desired new width in pixels + * @param dstHeight Desired new height in pixels + */ +int crop_and_interpolate_rgb888( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + uint8_t *dstImage, + int dstWidth, + int dstHeight); + +/** + * @brief Crops, then interpolates to a desired new image size + * Can be done in place (set srcImage == dstImage) + * A more beneric version of the previously used + * crop_and_interpolate_rgb888 + * + * @param srcImage Input image buffer + * @param srcWidth Input width in pixels + * @param srcHeight Input height in pixels + * @param dstImage Output image buffer, can be same as input buffer + * @param dstWidth Desired new width in pixels + * @param dstHeight Desired new height in pixels + * @param pixel_size_B Size of pixels in Bytes. 3 for RGB, 1 for mono + */ +int crop_and_interpolate_image( + const uint8_t *srcImage, + int srcWidth, + int srcHeight, + uint8_t *dstImage, + int dstWidth, + int dstHeight, + int pixel_size_B); + +}}} //namespaces +#endif //!__EI_IMAGE_PROCESSING__H__ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/.clang-format b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/.clang-format new file mode 100644 index 0000000..20ffce8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/.clang-format @@ -0,0 +1,2 @@ +"DisableFormat": true +"SortIncludes": false diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/LICENSE b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/LICENSE new file mode 100644 index 0000000..d95f124 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/LICENSE @@ -0,0 +1,4 @@ +Revised BSD License, see COPYING for verbiage. +Basically, "free to use&change, give credit where due, no guarantees" +Note this license is compatible with GPL at one end of the spectrum and closed, commercial software at +the other end. See http://www.fsf.org/licensing/licenses diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/README.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/README.md new file mode 100644 index 0000000..333e1fe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/README.md @@ -0,0 +1,3 @@ +# KissFFT + +Software FFT library used for devices that do not have hardware accelerated RFFT, or where we want to use mixed-radix FFT. Based off of https://github.com/mborgerding/kissfft. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/_kiss_fft_guts.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/_kiss_fft_guts.h new file mode 100755 index 0000000..754896a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/_kiss_fft_guts.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2003-2010, Mark Borgerding. All rights reserved. + * This file is part of KISS FFT - https://github.com/mborgerding/kissfft + * + * SPDX-License-Identifier: BSD-3-Clause + * See COPYING file for more information. + */ + +/* kiss_fft.h + defines kiss_fft_scalar as either short or a float type + and defines + typedef struct { kiss_fft_scalar r; kiss_fft_scalar i; }kiss_fft_cpx; */ +#pragma once + +#include "kiss_fft.h" +#include + +#define MAXFACTORS 32 +/* e.g. an fft of length 128 has 4 factors + as far as kissfft is concerned + 4*4*4*2 + */ + +struct kiss_fft_state{ + int nfft; + int inverse; + int factors[2*MAXFACTORS]; + kiss_fft_cpx twiddles[1]; +}; + +/* + Explanation of macros dealing with complex math: + + C_MUL(m,a,b) : m = a*b + C_FIXDIV( c , div ) : if a fixed point impl., c /= div. noop otherwise + C_SUB( res, a,b) : res = a - b + C_SUBFROM( res , a) : res -= a + C_ADDTO( res , a) : res += a + * */ +#ifdef FIXED_POINT +#include +#if (FIXED_POINT==32) +# define FRACBITS 31 +# define SAMPPROD int64_t +#define SAMP_MAX INT32_MAX +#define SAMP_MIN INT32_MIN +#else +# define FRACBITS 15 +# define SAMPPROD int32_t +#define SAMP_MAX INT16_MAX +#define SAMP_MIN INT16_MIN +#endif + +#if defined(CHECK_OVERFLOW) +# define CHECK_OVERFLOW_OP(a,op,b) \ + if ( (SAMPPROD)(a) op (SAMPPROD)(b) > SAMP_MAX || (SAMPPROD)(a) op (SAMPPROD)(b) < SAMP_MIN ) { \ + fprintf(stderr,"WARNING:overflow @ " __FILE__ "(%d): (%d " #op" %d) = %ld\n",__LINE__,(a),(b),(SAMPPROD)(a) op (SAMPPROD)(b) ); } +#endif + + +# define smul(a,b) ( (SAMPPROD)(a)*(b) ) +# define sround( x ) (kiss_fft_scalar)( ( (x) + (1<<(FRACBITS-1)) ) >> FRACBITS ) + +# define S_MUL(a,b) sround( smul(a,b) ) + +# define C_MUL(m,a,b) \ + do{ (m).r = sround( smul((a).r,(b).r) - smul((a).i,(b).i) ); \ + (m).i = sround( smul((a).r,(b).i) + smul((a).i,(b).r) ); }while(0) + +# define DIVSCALAR(x,k) \ + (x) = sround( smul( x, SAMP_MAX/k ) ) + +# define C_FIXDIV(c,div) \ + do { DIVSCALAR( (c).r , div); \ + DIVSCALAR( (c).i , div); }while (0) + +# define C_MULBYSCALAR( c, s ) \ + do{ (c).r = sround( smul( (c).r , s ) ) ;\ + (c).i = sround( smul( (c).i , s ) ) ; }while(0) + +#else /* not FIXED_POINT*/ + +# define S_MUL(a,b) ( (a)*(b) ) +#define C_MUL(m,a,b) \ + do{ (m).r = (a).r*(b).r - (a).i*(b).i;\ + (m).i = (a).r*(b).i + (a).i*(b).r; }while(0) +# define C_FIXDIV(c,div) /* NOOP */ +# define C_MULBYSCALAR( c, s ) \ + do{ (c).r *= (s);\ + (c).i *= (s); }while(0) +#endif + +#ifndef CHECK_OVERFLOW_OP +# define CHECK_OVERFLOW_OP(a,op,b) /* noop */ +#endif + +#define C_ADD( res, a,b)\ + do { \ + CHECK_OVERFLOW_OP((a).r,+,(b).r)\ + CHECK_OVERFLOW_OP((a).i,+,(b).i)\ + (res).r=(a).r+(b).r; (res).i=(a).i+(b).i; \ + }while(0) +#define C_SUB( res, a,b)\ + do { \ + CHECK_OVERFLOW_OP((a).r,-,(b).r)\ + CHECK_OVERFLOW_OP((a).i,-,(b).i)\ + (res).r=(a).r-(b).r; (res).i=(a).i-(b).i; \ + }while(0) +#define C_ADDTO( res , a)\ + do { \ + CHECK_OVERFLOW_OP((res).r,+,(a).r)\ + CHECK_OVERFLOW_OP((res).i,+,(a).i)\ + (res).r += (a).r; (res).i += (a).i;\ + }while(0) + +#define C_SUBFROM( res , a)\ + do {\ + CHECK_OVERFLOW_OP((res).r,-,(a).r)\ + CHECK_OVERFLOW_OP((res).i,-,(a).i)\ + (res).r -= (a).r; (res).i -= (a).i; \ + }while(0) + + +#ifdef FIXED_POINT +# define KISS_FFT_COS(phase) floor(.5+SAMP_MAX * cos (phase)) +# define KISS_FFT_SIN(phase) floor(.5+SAMP_MAX * sin (phase)) +# define HALF_OF(x) ((x)>>1) +#elif defined(USE_SIMD) +# define KISS_FFT_COS(phase) _mm_set1_ps( cos(phase) ) +# define KISS_FFT_SIN(phase) _mm_set1_ps( sin(phase) ) +# define HALF_OF(x) ((x)*_mm_set1_ps(.5)) +#else +# define KISS_FFT_COS(phase) (kiss_fft_scalar) cos(phase) +# define KISS_FFT_SIN(phase) (kiss_fft_scalar) sin(phase) +# define HALF_OF(x) ((x)*.5) +#endif + +#define kf_cexp(x,phase) \ + do{ \ + (x)->r = KISS_FFT_COS(phase);\ + (x)->i = KISS_FFT_SIN(phase);\ + }while(0) + + +/* a debugging function */ +#define pcpx(c)\ + fprintf(stderr,"%g + %gi\n",(double)((c)->r),(double)((c)->i) ) + + +#ifdef KISS_FFT_USE_ALLOCA +// define this to allow use of alloca instead of malloc for temporary buffers +// Temporary buffers are used in two case: +// 1. FFT sizes that have "bad" factors. i.e. not 2,3 and 5 +// 2. "in-place" FFTs. Notice the quotes, since kissfft does not really do an in-place transform. +#include +#define KISS_FFT_TMP_ALLOC(nbytes) alloca(nbytes) +#define KISS_FFT_TMP_FREE(ptr) +#else +#define KISS_FFT_TMP_ALLOC(nbytes) KISS_FFT_MALLOC(nbytes) +#define KISS_FFT_TMP_FREE(ptr) KISS_FFT_FREE(ptr) +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fft.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fft.cpp new file mode 100755 index 0000000..9393357 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fft.cpp @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2003-2010, Mark Borgerding. All rights reserved. + * This file is part of KISS FFT - https://github.com/mborgerding/kissfft + * + * SPDX-License-Identifier: BSD-3-Clause + * See COPYING file for more information. + */ + + +#include "edge-impulse-sdk/dsp/kissfft/_kiss_fft_guts.h" +/* The guts header contains all the multiplication and addition macros that are defined for + fixed or floating point complex numbers. It also delares the kf_ internal functions. + */ + +static void kf_bfly2( + kiss_fft_cpx * Fout, + const size_t fstride, + const kiss_fft_cfg st, + int m + ) +{ + kiss_fft_cpx * Fout2; + kiss_fft_cpx * tw1 = st->twiddles; + kiss_fft_cpx t; + Fout2 = Fout + m; + do{ + C_FIXDIV(*Fout,2); C_FIXDIV(*Fout2,2); + + C_MUL (t, *Fout2 , *tw1); + tw1 += fstride; + C_SUB( *Fout2 , *Fout , t ); + C_ADDTO( *Fout , t ); + ++Fout2; + ++Fout; + }while (--m); +} + +static void kf_bfly4( + kiss_fft_cpx * Fout, + const size_t fstride, + const kiss_fft_cfg st, + const size_t m + ) +{ + kiss_fft_cpx *tw1,*tw2,*tw3; + kiss_fft_cpx scratch[6]; + size_t k=m; + const size_t m2=2*m; + const size_t m3=3*m; + + + tw3 = tw2 = tw1 = st->twiddles; + + do { + C_FIXDIV(*Fout,4); C_FIXDIV(Fout[m],4); C_FIXDIV(Fout[m2],4); C_FIXDIV(Fout[m3],4); + + C_MUL(scratch[0],Fout[m] , *tw1 ); + C_MUL(scratch[1],Fout[m2] , *tw2 ); + C_MUL(scratch[2],Fout[m3] , *tw3 ); + + C_SUB( scratch[5] , *Fout, scratch[1] ); + C_ADDTO(*Fout, scratch[1]); + C_ADD( scratch[3] , scratch[0] , scratch[2] ); + C_SUB( scratch[4] , scratch[0] , scratch[2] ); + C_SUB( Fout[m2], *Fout, scratch[3] ); + tw1 += fstride; + tw2 += fstride*2; + tw3 += fstride*3; + C_ADDTO( *Fout , scratch[3] ); + + if(st->inverse) { + Fout[m].r = scratch[5].r - scratch[4].i; + Fout[m].i = scratch[5].i + scratch[4].r; + Fout[m3].r = scratch[5].r + scratch[4].i; + Fout[m3].i = scratch[5].i - scratch[4].r; + }else{ + Fout[m].r = scratch[5].r + scratch[4].i; + Fout[m].i = scratch[5].i - scratch[4].r; + Fout[m3].r = scratch[5].r - scratch[4].i; + Fout[m3].i = scratch[5].i + scratch[4].r; + } + ++Fout; + }while(--k); +} + +static void kf_bfly3( + kiss_fft_cpx * Fout, + const size_t fstride, + const kiss_fft_cfg st, + size_t m + ) +{ + size_t k=m; + const size_t m2 = 2*m; + kiss_fft_cpx *tw1,*tw2; + kiss_fft_cpx scratch[5]; + kiss_fft_cpx epi3; + epi3 = st->twiddles[fstride*m]; + + tw1=tw2=st->twiddles; + + do{ + C_FIXDIV(*Fout,3); C_FIXDIV(Fout[m],3); C_FIXDIV(Fout[m2],3); + + C_MUL(scratch[1],Fout[m] , *tw1); + C_MUL(scratch[2],Fout[m2] , *tw2); + + C_ADD(scratch[3],scratch[1],scratch[2]); + C_SUB(scratch[0],scratch[1],scratch[2]); + tw1 += fstride; + tw2 += fstride*2; + + Fout[m].r = Fout->r - HALF_OF(scratch[3].r); + Fout[m].i = Fout->i - HALF_OF(scratch[3].i); + + C_MULBYSCALAR( scratch[0] , epi3.i ); + + C_ADDTO(*Fout,scratch[3]); + + Fout[m2].r = Fout[m].r + scratch[0].i; + Fout[m2].i = Fout[m].i - scratch[0].r; + + Fout[m].r -= scratch[0].i; + Fout[m].i += scratch[0].r; + + ++Fout; + }while(--k); +} + +static void kf_bfly5( + kiss_fft_cpx * Fout, + const size_t fstride, + const kiss_fft_cfg st, + int m + ) +{ + kiss_fft_cpx *Fout0,*Fout1,*Fout2,*Fout3,*Fout4; + int u; + kiss_fft_cpx scratch[13]; + kiss_fft_cpx * twiddles = st->twiddles; + kiss_fft_cpx *tw; + kiss_fft_cpx ya,yb; + ya = twiddles[fstride*m]; + yb = twiddles[fstride*2*m]; + + Fout0=Fout; + Fout1=Fout0+m; + Fout2=Fout0+2*m; + Fout3=Fout0+3*m; + Fout4=Fout0+4*m; + + tw=st->twiddles; + for ( u=0; ur += scratch[7].r + scratch[8].r; + Fout0->i += scratch[7].i + scratch[8].i; + + scratch[5].r = scratch[0].r + S_MUL(scratch[7].r,ya.r) + S_MUL(scratch[8].r,yb.r); + scratch[5].i = scratch[0].i + S_MUL(scratch[7].i,ya.r) + S_MUL(scratch[8].i,yb.r); + + scratch[6].r = S_MUL(scratch[10].i,ya.i) + S_MUL(scratch[9].i,yb.i); + scratch[6].i = -S_MUL(scratch[10].r,ya.i) - S_MUL(scratch[9].r,yb.i); + + C_SUB(*Fout1,scratch[5],scratch[6]); + C_ADD(*Fout4,scratch[5],scratch[6]); + + scratch[11].r = scratch[0].r + S_MUL(scratch[7].r,yb.r) + S_MUL(scratch[8].r,ya.r); + scratch[11].i = scratch[0].i + S_MUL(scratch[7].i,yb.r) + S_MUL(scratch[8].i,ya.r); + scratch[12].r = - S_MUL(scratch[10].i,yb.i) + S_MUL(scratch[9].i,ya.i); + scratch[12].i = S_MUL(scratch[10].r,yb.i) - S_MUL(scratch[9].r,ya.i); + + C_ADD(*Fout2,scratch[11],scratch[12]); + C_SUB(*Fout3,scratch[11],scratch[12]); + + ++Fout0;++Fout1;++Fout2;++Fout3;++Fout4; + } +} + +/* perform the butterfly for one stage of a mixed radix FFT */ +static void kf_bfly_generic( + kiss_fft_cpx * Fout, + const size_t fstride, + const kiss_fft_cfg st, + int m, + int p + ) +{ + int u,k,q1,q; + kiss_fft_cpx * twiddles = st->twiddles; + kiss_fft_cpx t; + int Norig = st->nfft; + + kiss_fft_cpx * scratch = (kiss_fft_cpx*)KISS_FFT_TMP_ALLOC(sizeof(kiss_fft_cpx)*p); + + for ( u=0; u=Norig) twidx-=Norig; + C_MUL(t,scratch[q] , twiddles[twidx] ); + C_ADDTO( Fout[ k ] ,t); + } + k += m; + } + } + KISS_FFT_TMP_FREE(scratch); +} + +static +void kf_work( + kiss_fft_cpx * Fout, + const kiss_fft_cpx * f, + const size_t fstride, + int in_stride, + int * factors, + const kiss_fft_cfg st + ) +{ + kiss_fft_cpx * Fout_beg=Fout; + const int p=*factors++; /* the radix */ + const int m=*factors++; /* stage's fft length/p */ + const kiss_fft_cpx * Fout_end = Fout + p*m; + +#ifdef _OPENMP + // use openmp extensions at the + // top-level (not recursive) + if (fstride==1 && p<=5) + { + int k; + + // execute the p different work units in different threads +# pragma omp parallel for + for (k=0;k floor_sqrt) + p = n; /* no more factors, skip to end */ + } + n /= p; + *facbuf++ = p; + *facbuf++ = n; + } while (n > 1); +} + +/* + * + * User-callable function to allocate all necessary storage space for the fft. + * + * The return value is a contiguous block of memory, allocated with malloc. As such, + * It can be freed with free(), rather than a kiss_fft-specific function. + * */ +kiss_fft_cfg kiss_fft_alloc(int nfft,int inverse_fft,void * mem,size_t * lenmem,size_t * memallocated ) +{ + kiss_fft_cfg st=NULL; + size_t memneeded = sizeof(struct kiss_fft_state) + + sizeof(kiss_fft_cpx)*(nfft-1); /* twiddle factors*/ + + if ( lenmem==NULL ) { + st = ( kiss_fft_cfg)KISS_FFT_MALLOC( memneeded ); + }else{ + if (mem != NULL && *lenmem >= memneeded) + st = (kiss_fft_cfg)mem; + *lenmem = memneeded; + } + if (st) { + int i; + st->nfft=nfft; + st->inverse = inverse_fft; + if (inverse_fft) + { + for (i=0;itwiddles+i, phase ); + } + } else { + for (i=0;itwiddles+i, phase ); + } + } + + kf_factor(nfft,st->factors); + } + + if (memallocated != NULL) { + *memallocated = memneeded; + } + + return st; +} + + +void kiss_fft_stride(kiss_fft_cfg st,const kiss_fft_cpx *fin,kiss_fft_cpx *fout,int in_stride) +{ + if (fin == fout) { + //NOTE: this is not really an in-place FFT algorithm. + //It just performs an out-of-place FFT into a temp buffer + kiss_fft_cpx * tmpbuf = (kiss_fft_cpx*)KISS_FFT_TMP_ALLOC( sizeof(kiss_fft_cpx)*st->nfft); + kf_work(tmpbuf,fin,1,in_stride, st->factors,st); + memcpy(fout,tmpbuf,sizeof(kiss_fft_cpx)*st->nfft); + KISS_FFT_TMP_FREE(tmpbuf); + }else{ + kf_work( fout, fin, 1,in_stride, st->factors,st ); + } +} + +void kiss_fft(kiss_fft_cfg cfg,const kiss_fft_cpx *fin,kiss_fft_cpx *fout) +{ + kiss_fft_stride(cfg,fin,fout,1); +} + + +void kiss_fft_cleanup(void) +{ + // nothing needed any more +} + +int kiss_fft_next_fast_size(int n) +{ + while(1) { + int m=n; + while ( (m%2) == 0 ) m/=2; + while ( (m%3) == 0 ) m/=3; + while ( (m%5) == 0 ) m/=5; + if (m<=1) + break; /* n is completely factorable by twos, threes, and fives */ + n++; + } + return n; +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fft.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fft.h new file mode 100755 index 0000000..301687a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fft.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2003-2010, Mark Borgerding. All rights reserved. + * This file is part of KISS FFT - https://github.com/mborgerding/kissfft + * + * SPDX-License-Identifier: BSD-3-Clause + * See COPYING file for more information. + */ + +#ifndef KISS_FFT_H +#define KISS_FFT_H + +#include +#include +#include +#include +#include "../../porting/ei_classifier_porting.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + ATTENTION! + If you would like a : + -- a utility that will handle the caching of fft objects + -- real-only (no imaginary time component ) FFT + -- a multi-dimensional FFT + -- a command-line utility to perform ffts + -- a command-line utility to perform fast-convolution filtering + + Then see kfc.h kiss_fftr.h kiss_fftnd.h fftutil.c kiss_fastfir.c + in the tools/ directory. +*/ + +#ifdef USE_SIMD +# include +# define kiss_fft_scalar __m128 +#define KISS_FFT_MALLOC(nbytes) _mm_malloc(nbytes,16) +#define KISS_FFT_FREE _mm_free +#else +#define KISS_FFT_MALLOC ei_malloc +#define KISS_FFT_FREE ei_free +#endif + + +#ifdef FIXED_POINT +#include +# if (FIXED_POINT == 32) +# define kiss_fft_scalar int32_t +# else +# define kiss_fft_scalar int16_t +# endif +#else +# ifndef kiss_fft_scalar +/* default is float */ +# define kiss_fft_scalar float +# endif +#endif + +typedef struct { + kiss_fft_scalar r; + kiss_fft_scalar i; +}kiss_fft_cpx; + +typedef struct kiss_fft_state* kiss_fft_cfg; + +/* + * kiss_fft_alloc + * + * Initialize a FFT (or IFFT) algorithm's cfg/state buffer. + * + * typical usage: kiss_fft_cfg mycfg=kiss_fft_alloc(1024,0,NULL,NULL); + * + * The return value from fft_alloc is a cfg buffer used internally + * by the fft routine or NULL. + * + * If lenmem is NULL, then kiss_fft_alloc will allocate a cfg buffer using malloc. + * The returned value should be free()d when done to avoid memory leaks. + * + * The state can be placed in a user supplied buffer 'mem': + * If lenmem is not NULL and mem is not NULL and *lenmem is large enough, + * then the function places the cfg in mem and the size used in *lenmem + * and returns mem. + * + * If lenmem is not NULL and ( mem is NULL or *lenmem is not large enough), + * then the function returns NULL and places the minimum cfg + * buffer size in *lenmem. + * */ + +kiss_fft_cfg kiss_fft_alloc(int nfft,int inverse_fft,void * mem,size_t * lenmem,size_t * memallocated = NULL); + +/* + * kiss_fft(cfg,in_out_buf) + * + * Perform an FFT on a complex input buffer. + * for a forward FFT, + * fin should be f[0] , f[1] , ... ,f[nfft-1] + * fout will be F[0] , F[1] , ... ,F[nfft-1] + * Note that each element is complex and can be accessed like + f[k].r and f[k].i + * */ +void kiss_fft(kiss_fft_cfg cfg,const kiss_fft_cpx *fin,kiss_fft_cpx *fout); + +/* + A more generic version of the above function. It reads its input from every Nth sample. + * */ +void kiss_fft_stride(kiss_fft_cfg cfg,const kiss_fft_cpx *fin,kiss_fft_cpx *fout,int fin_stride); + +/* If kiss_fft_alloc allocated a buffer, it is one contiguous + buffer and can be simply free()d when no longer needed*/ +#define kiss_fft_free KISS_FFT_FREE + +/* + Cleans up some memory that gets managed internally. Not necessary to call, but it might clean up + your compiler output to call this before you exit. +*/ +void kiss_fft_cleanup(void); + + +/* + * Returns the smallest integer k, such that k>=n and k has only "fast" factors (2,3,5) + */ +int kiss_fft_next_fast_size(int n); + +/* for real ffts, we need an even size */ +#define kiss_fftr_next_fast_size_real(n) \ + (kiss_fft_next_fast_size( ((n)+1)>>1)<<1) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fftr.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fftr.cpp new file mode 100644 index 0000000..b448730 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fftr.cpp @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2003-2010, Mark Borgerding. All rights reserved. + * This file is part of KISS FFT - https://github.com/mborgerding/kissfft + * + * SPDX-License-Identifier: BSD-3-Clause + * See COPYING file for more information. + */ + +#include "edge-impulse-sdk/dsp/kissfft/kiss_fftr.h" +#include "edge-impulse-sdk/dsp/kissfft/_kiss_fft_guts.h" + +struct kiss_fftr_state{ + kiss_fft_cfg substate; + kiss_fft_cpx * tmpbuf; + kiss_fft_cpx * super_twiddles; +#ifdef USE_SIMD + void * pad; +#endif +}; + +kiss_fftr_cfg kiss_fftr_alloc(int nfft,int inverse_fft,void * mem,size_t * lenmem,size_t * memallocated) +{ + int i; + kiss_fftr_cfg st = NULL; + size_t subsize = 0, memneeded; + + if (nfft & 1) { + ei_printf("FFT length must be even\n"); + return NULL; + } + nfft >>= 1; + + kiss_fft_alloc (nfft, inverse_fft, NULL, &subsize); + memneeded = sizeof(struct kiss_fftr_state) + subsize + sizeof(kiss_fft_cpx) * ( nfft * 3 / 2); + + if (lenmem == NULL) { + st = (kiss_fftr_cfg) KISS_FFT_MALLOC (memneeded); + } else { + if (*lenmem >= memneeded) + st = (kiss_fftr_cfg) mem; + *lenmem = memneeded; + } + if (!st) + return NULL; + + st->substate = (kiss_fft_cfg) (st + 1); /*just beyond kiss_fftr_state struct */ + st->tmpbuf = (kiss_fft_cpx *) (((char *) st->substate) + subsize); + st->super_twiddles = st->tmpbuf + nfft; + kiss_fft_alloc(nfft, inverse_fft, st->substate, &subsize); + + if (inverse_fft) { + for (i = 0; i < nfft/2; ++i) { + double phase = + 3.14159265358979323846264338327 * ((double) (i+1) / nfft + .5); + kf_cexp (st->super_twiddles+i,phase); + } + } else { + for (i = 0; i < nfft/2; ++i) { + double phase = + -3.14159265358979323846264338327 * ((double) (i+1) / nfft + .5); + kf_cexp (st->super_twiddles+i,phase); + } + } + + if (memallocated != NULL) { + *memallocated = memneeded; + } + + return st; +} + +void kiss_fftr(kiss_fftr_cfg st,const kiss_fft_scalar *timedata,kiss_fft_cpx *freqdata) +{ + /* input buffer timedata is stored row-wise */ + int k,ncfft; + kiss_fft_cpx fpnk,fpk,f1k,f2k,tw,tdc; + + if ( st->substate->inverse) { + ei_printf("kiss fft usage error: improper alloc\n"); + } + + ncfft = st->substate->nfft; + + /*perform the parallel fft of two real signals packed in real,imag*/ + kiss_fft( st->substate , (const kiss_fft_cpx*)timedata, st->tmpbuf ); + /* The real part of the DC element of the frequency spectrum in st->tmpbuf + * contains the sum of the even-numbered elements of the input time sequence + * The imag part is the sum of the odd-numbered elements + * + * The sum of tdc.r and tdc.i is the sum of the input time sequence. + * yielding DC of input time sequence + * The difference of tdc.r - tdc.i is the sum of the input (dot product) [1,-1,1,-1... + * yielding Nyquist bin of input time sequence + */ + + tdc.r = st->tmpbuf[0].r; + tdc.i = st->tmpbuf[0].i; + C_FIXDIV(tdc,2); + CHECK_OVERFLOW_OP(tdc.r ,+, tdc.i); + CHECK_OVERFLOW_OP(tdc.r ,-, tdc.i); + freqdata[0].r = tdc.r + tdc.i; + freqdata[ncfft].r = tdc.r - tdc.i; +#ifdef USE_SIMD + freqdata[ncfft].i = freqdata[0].i = _mm_set1_ps(0); +#else + freqdata[ncfft].i = freqdata[0].i = 0; +#endif + + for ( k=1;k <= ncfft/2 ; ++k ) { + fpk = st->tmpbuf[k]; + fpnk.r = st->tmpbuf[ncfft-k].r; + fpnk.i = - st->tmpbuf[ncfft-k].i; + C_FIXDIV(fpk,2); + C_FIXDIV(fpnk,2); + + C_ADD( f1k, fpk , fpnk ); + C_SUB( f2k, fpk , fpnk ); + C_MUL( tw , f2k , st->super_twiddles[k-1]); + + freqdata[k].r = HALF_OF(f1k.r + tw.r); + freqdata[k].i = HALF_OF(f1k.i + tw.i); + freqdata[ncfft-k].r = HALF_OF(f1k.r - tw.r); + freqdata[ncfft-k].i = HALF_OF(tw.i - f1k.i); + } +} + +void kiss_fftri(kiss_fftr_cfg st,const kiss_fft_cpx *freqdata,kiss_fft_scalar *timedata) +{ + /* input buffer timedata is stored row-wise */ + int k, ncfft; + + if (st->substate->inverse == 0) { + ei_printf("kiss fft usage error: improper alloc\n"); + } + + ncfft = st->substate->nfft; + + st->tmpbuf[0].r = freqdata[0].r + freqdata[ncfft].r; + st->tmpbuf[0].i = freqdata[0].r - freqdata[ncfft].r; + C_FIXDIV(st->tmpbuf[0],2); + + for (k = 1; k <= ncfft / 2; ++k) { + kiss_fft_cpx fk, fnkc, fek, fok, tmp; + fk = freqdata[k]; + fnkc.r = freqdata[ncfft - k].r; + fnkc.i = -freqdata[ncfft - k].i; + C_FIXDIV( fk , 2 ); + C_FIXDIV( fnkc , 2 ); + + C_ADD (fek, fk, fnkc); + C_SUB (tmp, fk, fnkc); + C_MUL (fok, tmp, st->super_twiddles[k-1]); + C_ADD (st->tmpbuf[k], fek, fok); + C_SUB (st->tmpbuf[ncfft - k], fek, fok); +#ifdef USE_SIMD + st->tmpbuf[ncfft - k].i *= _mm_set1_ps(-1.0); +#else + st->tmpbuf[ncfft - k].i *= -1; +#endif + } + kiss_fft (st->substate, st->tmpbuf, (kiss_fft_cpx *) timedata); +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fftr.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fftr.h new file mode 100644 index 0000000..49f0fd9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kiss_fftr.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2003-2010, Mark Borgerding. All rights reserved. + * This file is part of KISS FFT - https://github.com/mborgerding/kissfft + * + * SPDX-License-Identifier: BSD-3-Clause + * See COPYING file for more information. + */ + +#ifndef KISS_FTR_H +#define KISS_FTR_H + +#include "kiss_fft.h" +#ifdef __cplusplus +extern "C" { +#endif + + +/* + + Real optimized version can save about 45% cpu time vs. complex fft of a real seq. + + + + */ + +typedef struct kiss_fftr_state *kiss_fftr_cfg; + + +kiss_fftr_cfg kiss_fftr_alloc(int nfft,int inverse_fft,void * mem, size_t * lenmem, size_t * memallocated = NULL); +/* + nfft must be even + + If you don't care to allocate space, use mem = lenmem = NULL +*/ + + +void kiss_fftr(kiss_fftr_cfg cfg,const kiss_fft_scalar *timedata,kiss_fft_cpx *freqdata); +/* + input timedata has nfft scalar points + output freqdata has nfft/2+1 complex points +*/ + +void kiss_fftri(kiss_fftr_cfg cfg,const kiss_fft_cpx *freqdata,kiss_fft_scalar *timedata); +/* + input freqdata has nfft/2+1 complex points + output timedata has nfft scalar points +*/ + +#define kiss_fftr_free KISS_FFT_FREE + +#ifdef __cplusplus +} +#endif +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kissfft.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kissfft.h new file mode 100644 index 0000000..3619c00 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/kissfft/kissfft.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2003-2010, Mark Borgerding. All rights reserved. + * This file is part of KISS FFT - https://github.com/mborgerding/kissfft + * + * SPDX-License-Identifier: BSD-3-Clause + * See COPYING file for more information. + */ + +#ifndef KISSFFT_CLASS_HH +#define KISSFFT_CLASS_HH +#include +#include +#include "edge-impulse-sdk/dsp/ei_vector.h" + + +template +class kissfft +{ + public: + + typedef std::complex cpx_t; + + kissfft( const std::size_t nfft, + const bool inverse ) + :_nfft(nfft) + ,_inverse(inverse) + { + // fill twiddle factors + _twiddles.resize(_nfft); + const scalar_t phinc = (_inverse?2:-2)* std::acos( (scalar_t) -1) / _nfft; + for (std::size_t i=0;i<_nfft;++i) + _twiddles[i] = std::exp( cpx_t(0,i*phinc) ); + + //factorize + //start factoring out 4's, then 2's, then 3,5,7,9,... + std::size_t n= _nfft; + std::size_t p=4; + do { + while (n % p) { + switch (p) { + case 4: p = 2; break; + case 2: p = 3; break; + default: p += 2; break; + } + if (p*p>n) + p = n;// no more factors + } + n /= p; + _stageRadix.push_back(p); + _stageRemainder.push_back(n); + }while(n>1); + } + + + /// Changes the FFT-length and/or the transform direction. + /// + /// @post The @c kissfft object will be in the same state as if it + /// had been newly constructed with the passed arguments. + /// However, the implementation may be faster than constructing a + /// new fft object. + void assign( const std::size_t nfft, + const bool inverse ) + { + if ( nfft != _nfft ) + { + kissfft tmp( nfft, inverse ); // O(n) time. + std::swap( tmp, *this ); // this is O(1) in C++11, O(n) otherwise. + } + else if ( inverse != _inverse ) + { + // conjugate the twiddle factors. + for ( typename ei_vector::iterator it = _twiddles.begin(); + it != _twiddles.end(); ++it ) + it->imag( -it->imag() ); + } + } + + /// Calculates the complex Discrete Fourier Transform. + /// + /// The size of the passed arrays must be passed in the constructor. + /// The sum of the squares of the absolute values in the @c dst + /// array will be @c N times the sum of the squares of the absolute + /// values in the @c src array, where @c N is the size of the array. + /// In other words, the l_2 norm of the resulting array will be + /// @c sqrt(N) times as big as the l_2 norm of the input array. + /// This is also the case when the inverse flag is set in the + /// constructor. Hence when applying the same transform twice, but with + /// the inverse flag changed the second time, then the result will + /// be equal to the original input times @c N. + void transform(const cpx_t * fft_in, cpx_t * fft_out, const std::size_t stage = 0, const std::size_t fstride = 1, const std::size_t in_stride = 1) const + { + const std::size_t p = _stageRadix[stage]; + const std::size_t m = _stageRemainder[stage]; + cpx_t * const Fout_beg = fft_out; + cpx_t * const Fout_end = fft_out + p*m; + + if (m==1) { + do{ + *fft_out = *fft_in; + fft_in += fstride*in_stride; + }while(++fft_out != Fout_end ); + }else{ + do{ + // recursive call: + // DFT of size m*p performed by doing + // p instances of smaller DFTs of size m, + // each one takes a decimated version of the input + transform(fft_in, fft_out, stage+1, fstride*p,in_stride); + fft_in += fstride*in_stride; + }while( (fft_out += m) != Fout_end ); + } + + fft_out=Fout_beg; + + // recombine the p smaller DFTs + switch (p) { + case 2: kf_bfly2(fft_out,fstride,m); break; + case 3: kf_bfly3(fft_out,fstride,m); break; + case 4: kf_bfly4(fft_out,fstride,m); break; + case 5: kf_bfly5(fft_out,fstride,m); break; + default: kf_bfly_generic(fft_out,fstride,m,p); break; + } + } + + /// Calculates the Discrete Fourier Transform (DFT) of a real input + /// of size @c 2*N. + /// + /// The 0-th and N-th value of the DFT are real numbers. These are + /// stored in @c dst[0].real() and @c dst[1].imag() respectively. + /// The remaining DFT values up to the index N-1 are stored in + /// @c dst[1] to @c dst[N-1]. + /// The other half of the DFT values can be calculated from the + /// symmetry relation + /// @code + /// DFT(src)[2*N-k] == conj( DFT(src)[k] ); + /// @endcode + /// The same scaling factors as in @c transform() apply. + /// + /// @note For this to work, the types @c scalar_t and @c cpx_t + /// must fulfill the following requirements: + /// + /// For any object @c z of type @c cpx_t, + /// @c reinterpret_cast(z)[0] is the real part of @c z and + /// @c reinterpret_cast(z)[1] is the imaginary part of @c z. + /// For any pointer to an element of an array of @c cpx_t named @c p + /// and any valid array index @c i, @c reinterpret_cast(p)[2*i] + /// is the real part of the complex number @c p[i], and + /// @c reinterpret_cast(p)[2*i+1] is the imaginary part of the + /// complex number @c p[i]. + /// + /// Since C++11, these requirements are guaranteed to be satisfied for + /// @c scalar_ts being @c float, @c double or @c long @c double + /// together with @c cpx_t being @c std::complex. + void transform_real( const scalar_t * const src, + cpx_t * const dst ) const + { + const std::size_t N = _nfft; + if ( N == 0 ) + return; + + // perform complex FFT + transform( reinterpret_cast(src), dst ); + + // post processing for k = 0 and k = N + dst[0] = cpx_t( dst[0].real() + dst[0].imag(), + dst[0].real() - dst[0].imag() ); + + // post processing for all the other k = 1, 2, ..., N-1 + const scalar_t pi = std::acos( (scalar_t) -1); + const scalar_t half_phi_inc = ( _inverse ? pi : -pi ) / N; + const cpx_t twiddle_mul = std::exp( cpx_t(0, half_phi_inc) ); + for ( std::size_t k = 1; 2*k < N; ++k ) + { + const cpx_t w = (scalar_t)0.5 * cpx_t( + dst[k].real() + dst[N-k].real(), + dst[k].imag() - dst[N-k].imag() ); + const cpx_t z = (scalar_t)0.5 * cpx_t( + dst[k].imag() + dst[N-k].imag(), + -dst[k].real() + dst[N-k].real() ); + const cpx_t twiddle = + k % 2 == 0 ? + _twiddles[k/2] : + _twiddles[k/2] * twiddle_mul; + dst[ k] = w + twiddle * z; + dst[N-k] = std::conj( w - twiddle * z ); + } + if ( N % 2 == 0 ) + dst[N/2] = std::conj( dst[N/2] ); + } + + private: + + void kf_bfly2( cpx_t * Fout, const size_t fstride, const std::size_t m) const + { + for (std::size_t k=0;k _scratchbuf.size()) _scratchbuf.resize(p); + + for ( std::size_t u=0; u=_nfft) + twidx-=_nfft; + Fout[ k ] += _scratchbuf[q] * twiddles[twidx]; + } + k += m; + } + } + } + + std::size_t _nfft; + bool _inverse; + ei_vector _twiddles; + ei_vector _stageRadix; + ei_vector _stageRemainder; + mutable ei_vector _scratchbuf; +}; +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/memory.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/memory.cpp new file mode 100644 index 0000000..299694a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/memory.cpp @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "memory.hpp" + +size_t ei_memory_in_use = 0; +size_t ei_memory_peak_use = 0; diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/memory.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/memory.hpp new file mode 100644 index 0000000..2ce95a7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/memory.hpp @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_MEMORY_H_ +#define _EIDSP_MEMORY_H_ + +// clang-format off +#include +#include +#include "../porting/ei_classifier_porting.h" +#include "edge-impulse-sdk/classifier/ei_aligned_malloc.h" +#include "config.hpp" + +extern size_t ei_memory_in_use; +extern size_t ei_memory_peak_use; + +#if EIDSP_PRINT_ALLOCATIONS == 1 +#define ei_dsp_printf printf +#else +#define ei_dsp_printf (void) +#endif + +typedef std::unique_ptr ei_unique_ptr_t; +#define EI_ALLOCATE_AUTO_POINTER(ptr, size) \ + ptr = static_cast(ei_calloc(size,sizeof(*ptr))); \ + ei_unique_ptr_t __ptr__(ptr,ei_free); + +#define EI_ERR_AND_RETURN_ON_NULL(ptr,code) \ + if( ! (ptr) ) { \ + ei_printf("Null check failed\n"); \ + return code; \ + } + +namespace ei { + +/** + * These are macros used to track allocations when running DSP processes. + * Enable memory tracking through the EIDSP_TRACK_ALLOCATIONS macro. + */ + +#if EIDSP_TRACK_ALLOCATIONS + /** + * Register a manual allocation (malloc or calloc). + * Typically you want to use ei::matrix_t types, as they keep track automatically. + * @param bytes Number of bytes allocated + */ + #define ei_dsp_register_alloc_internal(fn, file, line, bytes, ptr) \ + ei_memory_in_use += bytes; \ + if (ei_memory_in_use > ei_memory_peak_use) { \ + ei_memory_peak_use = ei_memory_in_use; \ + } \ + ei_dsp_printf("alloc %lu bytes (in_use=%lu, peak=%lu) (%s@ %s:%d) %p\n", \ + (unsigned long)bytes, (unsigned long)ei_memory_in_use, (unsigned long)ei_memory_peak_use, fn, file, line, ptr); + + /** + * Register a matrix allocation. Don't call this function yourself, + * matrices already track this automatically. + * @param rows Number of rows + * @param cols Number of columns + * @param type_size Size of the data type + */ + #define ei_dsp_register_matrix_alloc_internal(fn, file, line, rows, cols, type_size, ptr) \ + ei_memory_in_use += (rows * cols * type_size); \ + if (ei_memory_in_use > ei_memory_peak_use) { \ + ei_memory_peak_use = ei_memory_in_use; \ + } \ + ei_dsp_printf("alloc matrix %lu x %lu = %lu bytes (in_use=%lu, peak=%lu) (%s@ %s:%d) %p\n", \ + (unsigned long)rows, (unsigned long)cols, (unsigned long)(rows * cols * type_size), (unsigned long)ei_memory_in_use, \ + (unsigned long)ei_memory_peak_use, fn, file, line, ptr); + + /** + * Register free'ing manually allocated memory (allocated through malloc/calloc) + * @param bytes Number of bytes free'd + */ + #define ei_dsp_register_free_internal(fn, file, line, bytes, ptr) \ + ei_memory_in_use -= bytes; \ + ei_dsp_printf("free %lu bytes (in_use=%lu, peak=%lu) (%s@ %s:%d) %p\n", \ + (unsigned long)bytes, (unsigned long)ei_memory_in_use, (unsigned long)ei_memory_peak_use, fn, file, line, ptr); + + /** + * Register a matrix free. Don't call this function yourself, + * matrices already track this automatically. + * @param rows Number of rows + * @param cols Number of columns + * @param type_size Size of the data type + */ + #define ei_dsp_register_matrix_free_internal(fn, file, line, rows, cols, type_size, ptr) \ + ei_memory_in_use -= (rows * cols * type_size); \ + ei_dsp_printf("free matrix %lu x %lu = %lu bytes (in_use=%lu, peak=%lu) (%s@ %s:%d) %p\n", \ + (unsigned long)rows, (unsigned long)cols, (unsigned long)(rows * cols * type_size), \ + (unsigned long)ei_memory_in_use, (unsigned long)ei_memory_peak_use, fn, file, line, ptr); + + #define ei_dsp_register_alloc(...) ei_dsp_register_alloc_internal(__func__, __FILE__, __LINE__, __VA_ARGS__) + #define ei_dsp_register_matrix_alloc(...) ei_dsp_register_matrix_alloc_internal(__func__, __FILE__, __LINE__, __VA_ARGS__) + #define ei_dsp_register_free(...) ei_dsp_register_free_internal(__func__, __FILE__, __LINE__, __VA_ARGS__) + #define ei_dsp_register_matrix_free(...) ei_dsp_register_matrix_free_internal(__func__, __FILE__, __LINE__, __VA_ARGS__) + #define ei_dsp_malloc(...) memory::ei_wrapped_malloc(__func__, __FILE__, __LINE__, __VA_ARGS__) + #define ei_dsp_calloc(...) memory::ei_wrapped_calloc(__func__, __FILE__, __LINE__, __VA_ARGS__) + #define ei_dsp_free(...) memory::ei_wrapped_free(__func__, __FILE__, __LINE__, __VA_ARGS__) + #define EI_DSP_MATRIX(name, ...) matrix_t name(__VA_ARGS__, NULL, __func__, __FILE__, __LINE__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } + #define EI_DSP_MATRIX_B(name, ...) matrix_t name(__VA_ARGS__, __func__, __FILE__, __LINE__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } + #define EI_DSP_QUANTIZED_MATRIX(name, ...) quantized_matrix_t name(__VA_ARGS__, NULL, __func__, __FILE__, __LINE__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } + #define EI_DSP_QUANTIZED_MATRIX_B(name, ...) quantized_matrix_t name(__VA_ARGS__, __func__, __FILE__, __LINE__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } +#else + #define ei_dsp_register_alloc(...) (void)0 + #define ei_dsp_register_matrix_alloc(...) (void)0 + #define ei_dsp_register_free(...) (void)0 + #define ei_dsp_register_matrix_free(...) (void)0 + #define ei_dsp_malloc ei_malloc + #define ei_dsp_calloc ei_calloc + #define ei_dsp_free(ptr, size) ei_free(ptr) + #define EI_DSP_MATRIX(name, ...) matrix_t name(__VA_ARGS__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } + #define EI_DSP_MATRIX_B(name, ...) matrix_t name(__VA_ARGS__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } + #define EI_DSP_QUANTIZED_MATRIX(name, ...) quantized_matrix_t name(__VA_ARGS__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } + #define EI_DSP_QUANTIZED_MATRIX_B(name, ...) quantized_matrix_t name(__VA_ARGS__); if (!name.buffer) { EIDSP_ERR(EIDSP_OUT_OF_MEM); } +#endif + +#if EIDSP_TRACK_ALLOCATIONS +class memory { + + +public: + /** + * Allocate a new block of memory + * @param size The size of the memory block, in bytes. + */ + static void *ei_wrapped_malloc(const char *fn, const char *file, int line, size_t size) { + void *ptr = ei_malloc(size); + if (ptr) { + ei_dsp_register_alloc_internal(fn, file, line, size, ptr); + } + return ptr; + } + + /** + * Allocates a block of memory for an array of num elements, each of them size bytes long, + * and initializes all its bits to zero. + * @param num Number of elements to allocate + * @param size Size of each element + */ + static void *ei_wrapped_calloc(const char *fn, const char *file, int line, size_t num, size_t size) { + void *ptr = ei_calloc(num, size); + if (ptr) { + ei_dsp_register_alloc_internal(fn, file, line, num * size, ptr); + } + return ptr; + } + + /** + * Deallocate memory previously allocated by a call to calloc, malloc, or realloc. + * @param ptr Pointer to a memory block previously allocated with malloc, calloc or realloc. + * @param size Size of the block of memory previously allocated. + */ + static void ei_wrapped_free(const char *fn, const char *file, int line, void *ptr, size_t size) { + ei_free(ptr); + ei_dsp_register_free_internal(fn, file, line, size, ptr); + } +}; +#endif // #if EIDSP_TRACK_ALLOCATIONS + +} // namespace ei + +// clang-format on +#endif // _EIDSP_MEMORY_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/numpy.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/numpy.hpp new file mode 100644 index 0000000..1c92fe5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/numpy.hpp @@ -0,0 +1,2650 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_NUMPY_H_ +#define _EIDSP_NUMPY_H_ + +// it's valid to include the SDK without a model, but there's information that we need +// in model_metadata.h (like the FFT tables used). +// if the compiler does not support the __has_include directive we'll assume that the +// file exists. +#ifndef __has_include +#define __has_include 1 +#endif // __has_include + +#include +#include +#include +#include +#include "ei_vector.h" +#include +#include "numpy_types.h" +#include "config.hpp" +#include "returntypes.hpp" +#include "memory.hpp" +#include "ei_utils.h" +#include "dct/fast-dct-fft.h" +#include "kissfft/kiss_fftr.h" +#if __has_include("model-parameters/model_metadata.h") +#include "model-parameters/model_metadata.h" +#endif +#if EIDSP_USE_CMSIS_DSP +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_math.h" +#include "edge-impulse-sdk/CMSIS/DSP/Include/arm_const_structs.h" +#endif + +// For the following CMSIS includes, we want to use the C fallback, so include whether or not we set the CMSIS flag +#include "edge-impulse-sdk/CMSIS/DSP/Include/dsp/statistics_functions.h" + +#ifdef __MBED__ +#include "mbed.h" +#else +#include +#endif // __MBED__ + +#define EI_MAX_UINT16 65535 + +namespace ei { + +using fvec = ei_vector; +using ivec = ei_vector; + +// clang-format off +// lookup table for quantized values between 0.0f and 1.0f +static constexpr float quantized_values_one_zero[] = { (0.0f / 1.0f), (1.0f / 100.0f), (2.0f / 100.0f), (3.0f / 100.0f), (4.0f / 100.0f), (1.0f / 22.0f), (1.0f / 21.0f), (1.0f / 20.0f), (1.0f / 19.0f), (1.0f / 18.0f), (1.0f / 17.0f), (6.0f / 100.0f), (1.0f / 16.0f), (1.0f / 15.0f), (7.0f / 100.0f), (1.0f / 14.0f), (1.0f / 13.0f), (8.0f / 100.0f), (1.0f / 12.0f), (9.0f / 100.0f), (1.0f / 11.0f), (2.0f / 21.0f), (1.0f / 10.0f), (2.0f / 19.0f), (11.0f / 100.0f), (1.0f / 9.0f), (2.0f / 17.0f), (12.0f / 100.0f), (1.0f / 8.0f), (13.0f / 100.0f), (2.0f / 15.0f), (3.0f / 22.0f), (14.0f / 100.0f), (1.0f / 7.0f), (3.0f / 20.0f), (2.0f / 13.0f), (3.0f / 19.0f), (16.0f / 100.0f), (1.0f / 6.0f), (17.0f / 100.0f), (3.0f / 17.0f), (18.0f / 100.0f), (2.0f / 11.0f), (3.0f / 16.0f), (19.0f / 100.0f), (4.0f / 21.0f), (1.0f / 5.0f), (21.0f / 100.0f), (4.0f / 19.0f), (3.0f / 14.0f), (22.0f / 100.0f), (2.0f / 9.0f), (5.0f / 22.0f), (23.0f / 100.0f), (3.0f / 13.0f), (4.0f / 17.0f), (5.0f / 21.0f), (24.0f / 100.0f), (1.0f / 4.0f), (26.0f / 100.0f), (5.0f / 19.0f), (4.0f / 15.0f), (27.0f / 100.0f), (3.0f / 11.0f), (5.0f / 18.0f), (28.0f / 100.0f), (2.0f / 7.0f), (29.0f / 100.0f), (5.0f / 17.0f), (3.0f / 10.0f), (4.0f / 13.0f), (31.0f / 100.0f), (5.0f / 16.0f), (6.0f / 19.0f), (7.0f / 22.0f), (32.0f / 100.0f), (33.0f / 100.0f), (1.0f / 3.0f), (34.0f / 100.0f), (7.0f / 20.0f), (6.0f / 17.0f), (5.0f / 14.0f), (36.0f / 100.0f), (4.0f / 11.0f), (7.0f / 19.0f), (37.0f / 100.0f), (3.0f / 8.0f), (38.0f / 100.0f), (8.0f / 21.0f), (5.0f / 13.0f), (7.0f / 18.0f), (39.0f / 100.0f), (2.0f / 5.0f), (9.0f / 22.0f), (41.0f / 100.0f), (7.0f / 17.0f), (5.0f / 12.0f), (42.0f / 100.0f), (8.0f / 19.0f), (3.0f / 7.0f), (43.0f / 100.0f), (7.0f / 16.0f), (44.0f / 100.0f), (4.0f / 9.0f), (9.0f / 20.0f), (5.0f / 11.0f), (46.0f / 100.0f), (6.0f / 13.0f), (7.0f / 15.0f), (47.0f / 100.0f), (8.0f / 17.0f), (9.0f / 19.0f), (10.0f / 21.0f), (48.0f / 100.0f), (49.0f / 100.0f), (1.0f / 2.0f), (51.0f / 100.0f), (52.0f / 100.0f), (11.0f / 21.0f), (10.0f / 19.0f), (9.0f / 17.0f), (53.0f / 100.0f), (8.0f / 15.0f), (7.0f / 13.0f), (54.0f / 100.0f), (6.0f / 11.0f), (11.0f / 20.0f), (5.0f / 9.0f), (56.0f / 100.0f), (9.0f / 16.0f), (57.0f / 100.0f), (4.0f / 7.0f), (11.0f / 19.0f), (58.0f / 100.0f), (7.0f / 12.0f), (10.0f / 17.0f), (59.0f / 100.0f), (13.0f / 22.0f), (3.0f / 5.0f), (61.0f / 100.0f), (11.0f / 18.0f), (8.0f / 13.0f), (13.0f / 21.0f), (62.0f / 100.0f), (5.0f / 8.0f), (63.0f / 100.0f), (12.0f / 19.0f), (7.0f / 11.0f), (64.0f / 100.0f), (9.0f / 14.0f), (11.0f / 17.0f), (13.0f / 20.0f), (66.0f / 100.0f), (2.0f / 3.0f), (67.0f / 100.0f), (68.0f / 100.0f), (15.0f / 22.0f), (13.0f / 19.0f), (11.0f / 16.0f), (69.0f / 100.0f), (9.0f / 13.0f), (7.0f / 10.0f), (12.0f / 17.0f), (71.0f / 100.0f), (5.0f / 7.0f), (72.0f / 100.0f), (13.0f / 18.0f), (8.0f / 11.0f), (73.0f / 100.0f), (11.0f / 15.0f), (14.0f / 19.0f), (74.0f / 100.0f), (3.0f / 4.0f), (76.0f / 100.0f), (16.0f / 21.0f), (13.0f / 17.0f), (10.0f / 13.0f), (77.0f / 100.0f), (17.0f / 22.0f), (7.0f / 9.0f), (78.0f / 100.0f), (11.0f / 14.0f), (15.0f / 19.0f), (79.0f / 100.0f), (4.0f / 5.0f), (17.0f / 21.0f), (81.0f / 100.0f), (13.0f / 16.0f), (9.0f / 11.0f), (82.0f / 100.0f), (14.0f / 17.0f), (83.0f / 100.0f), (5.0f / 6.0f), (84.0f / 100.0f), (16.0f / 19.0f), (11.0f / 13.0f), (17.0f / 20.0f), (6.0f / 7.0f), (86.0f / 100.0f), (19.0f / 22.0f), (13.0f / 15.0f), (87.0f / 100.0f), (7.0f / 8.0f), (88.0f / 100.0f), (15.0f / 17.0f), (8.0f / 9.0f), (89.0f / 100.0f), (17.0f / 19.0f), (9.0f / 10.0f), (19.0f / 21.0f), (10.0f / 11.0f), (91.0f / 100.0f), (11.0f / 12.0f), (92.0f / 100.0f), (12.0f / 13.0f), (13.0f / 14.0f), (93.0f / 100.0f), (14.0f / 15.0f), (15.0f / 16.0f), (94.0f / 100.0f), (16.0f / 17.0f), (17.0f / 18.0f), (18.0f / 19.0f), (19.0f / 20.0f), (20.0f / 21.0f), (21.0f / 22.0f), (96.0f / 100.0f), (97.0f / 100.0f), (98.0f / 100.0f), (99.0f / 100.0f), (1.0f / 1.0f) , + 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f, 1.0f }; +// clang-format on + +class numpy { +public: + + static float sqrt(float x) { +#if EIDSP_USE_CMSIS_DSP + float temp; + arm_sqrt_f32(x, &temp); + return temp; +#else + return sqrtf(x); +#endif + } + + /** + * Roll array elements along a given axis. + * Elements that roll beyond the last position are re-introduced at the first. + * @param input_array + * @param input_array_size + * @param shift The number of places by which elements are shifted. + * @returns EIDSP_OK if OK + */ + static int roll(float *input_array, size_t input_array_size, int shift) { + if (shift < 0) { + shift = input_array_size + shift; + } + + if (shift == 0) { + return EIDSP_OK; + } + + // so we need to allocate a buffer of the size of shift... + EI_DSP_MATRIX(shift_matrix, 1, shift); + + // we copy from the end of the buffer into the shift buffer + memcpy(shift_matrix.buffer, input_array + input_array_size - shift, shift * sizeof(float)); + + // now we do a memmove to shift the array + memmove(input_array + shift, input_array, (input_array_size - shift) * sizeof(float)); + + // and copy the shift buffer back to the beginning of the array + memcpy(input_array, shift_matrix.buffer, shift * sizeof(float)); + + return EIDSP_OK; + } + + /** + * Roll array elements along a given axis. + * Elements that roll beyond the last position are re-introduced at the first. + * @param input_array + * @param input_array_size + * @param shift The number of places by which elements are shifted. + * @returns EIDSP_OK if OK + */ + static int roll(int *input_array, size_t input_array_size, int shift) { + if (shift < 0) { + shift = input_array_size + shift; + } + + if (shift == 0) { + return EIDSP_OK; + } + + // so we need to allocate a buffer of the size of shift... + EI_DSP_MATRIX(shift_matrix, 1, shift); + + // we copy from the end of the buffer into the shift buffer + memcpy(shift_matrix.buffer, input_array + input_array_size - shift, shift * sizeof(int)); + + // now we do a memmove to shift the array + memmove(input_array + shift, input_array, (input_array_size - shift) * sizeof(int)); + + // and copy the shift buffer back to the beginning of the array + memcpy(input_array, shift_matrix.buffer, shift * sizeof(int)); + + return EIDSP_OK; + } + + /** + * Roll array elements along a given axis. + * Elements that roll beyond the last position are re-introduced at the first. + * @param input_array + * @param input_array_size + * @param shift The number of places by which elements are shifted. + * @returns EIDSP_OK if OK + */ + static int roll(int16_t *input_array, size_t input_array_size, int shift) { + if (shift < 0) { + shift = input_array_size + shift; + } + + if (shift == 0) { + return EIDSP_OK; + } + + // so we need to allocate a buffer of the size of shift... + EI_DSP_MATRIX(shift_matrix, 1, shift); + + // we copy from the end of the buffer into the shift buffer + memcpy(shift_matrix.buffer, input_array + input_array_size - shift, shift * sizeof(int16_t)); + + // now we do a memmove to shift the array + memmove(input_array + shift, input_array, (input_array_size - shift) * sizeof(int16_t)); + + // and copy the shift buffer back to the beginning of the array + memcpy(input_array, shift_matrix.buffer, shift * sizeof(int16_t)); + + return EIDSP_OK; + } + + static float sum(float *input_array, size_t input_array_size) { + float res = 0.0f; + for (size_t ix = 0; ix < input_array_size; ix++) { + res += input_array[ix]; + } + return res; + } + + /** + * Multiply two matrices (MxN * NxK matrix) + * @param matrix1 Pointer to matrix1 (MxN) + * @param matrix2 Pointer to matrix2 (NxK) + * @param out_matrix Pointer to out matrix (MxK) + * @returns EIDSP_OK if OK + */ + static int dot(matrix_t *matrix1, matrix_t *matrix2, matrix_t *out_matrix) { + if (matrix1->cols != matrix2->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + // no. of rows in matrix1 determines the + if (matrix1->rows != out_matrix->rows || matrix2->cols != out_matrix->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + +#if EIDSP_USE_CMSIS_DSP + if (matrix1->rows > EI_MAX_UINT16 || matrix1->cols > EI_MAX_UINT16 || matrix2->rows > EI_MAX_UINT16 || + matrix2->cols > EI_MAX_UINT16 || out_matrix->rows > EI_MAX_UINT16 || out_matrix->cols > EI_MAX_UINT16) { + return EIDSP_NARROWING; + } + + const arm_matrix_instance_f32 m1 = { static_cast(matrix1->rows), static_cast(matrix1->cols), matrix1->buffer }; + const arm_matrix_instance_f32 m2 = { static_cast(matrix2->rows), static_cast(matrix2->cols), matrix2->buffer }; + arm_matrix_instance_f32 mo = { static_cast(out_matrix->rows), static_cast(out_matrix->cols), out_matrix->buffer }; + int status = arm_mat_mult_f32(&m1, &m2, &mo); + if (status != ARM_MATH_SUCCESS) { + EIDSP_ERR(status); + } +#else + memset(out_matrix->buffer, 0, out_matrix->rows * out_matrix->cols * sizeof(float)); + + for (size_t i = 0; i < matrix1->rows; i++) { + dot_by_row(i, + matrix1->buffer + (i * matrix1->cols), + matrix1->cols, + matrix2, + out_matrix); + } +#endif + + return EIDSP_OK; + } + + /** + * Multiply two matrices (MxN * NxK matrix) + * @param matrix1 Pointer to matrix1 (MxN) + * @param matrix2 Pointer to quantized matrix2 (NxK) + * @param out_matrix Pointer to out matrix (MxK) + * @returns EIDSP_OK if OK + */ + static int dot(matrix_t *matrix1, + quantized_matrix_t *matrix2, + matrix_t *out_matrix) + { + if (matrix1->cols != matrix2->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + // no. of rows in matrix1 determines the + if (matrix1->rows != out_matrix->rows || matrix2->cols != out_matrix->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + memset(out_matrix->buffer, 0, out_matrix->rows * out_matrix->cols * sizeof(float)); + + for (size_t i = 0; i < matrix1->rows; i++) { + dot_by_row(i, + matrix1->buffer + (i * matrix1->cols), + matrix1->cols, + matrix2, + out_matrix); + } + + return EIDSP_OK; + } + + /** + * Multiply two matrices lazily per row in matrix 1 (MxN * NxK matrix) + * @param i matrix1 row index + * @param row matrix1 row + * @param matrix1_cols matrix1 row size (1xN) + * @param matrix2 Pointer to matrix2 (NxK) + * @param out_matrix Pointer to out matrix (MxK) + * @returns EIDSP_OK if OK + */ + static int dot_by_row(int i, float *row, uint32_t matrix1_cols, matrix_t *matrix2, matrix_t *out_matrix) { + if (matrix1_cols != matrix2->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + +#if EIDSP_USE_CMSIS_DSP + if (matrix1_cols > EI_MAX_UINT16 || matrix2->rows > EI_MAX_UINT16 || matrix2->cols > EI_MAX_UINT16 || + out_matrix->cols > EI_MAX_UINT16) { + return EIDSP_NARROWING; + } + + const arm_matrix_instance_f32 m1 = { 1, static_cast(matrix1_cols), row }; + const arm_matrix_instance_f32 m2 = { static_cast(matrix2->rows), static_cast(matrix2->cols), matrix2->buffer }; + arm_matrix_instance_f32 mo = { 1, static_cast(out_matrix->cols), out_matrix->buffer + (i * out_matrix->cols) }; + int status = arm_mat_mult_f32(&m1, &m2, &mo); + if (status != ARM_MATH_SUCCESS) { + EIDSP_ERR(status); + } +#else + for (size_t j = 0; j < matrix2->cols; j++) { + float tmp = 0.0f; + for (size_t k = 0; k < matrix1_cols; k++) { + tmp += row[k] * matrix2->buffer[k * matrix2->cols + j]; + } + out_matrix->buffer[i * matrix2->cols + j] += tmp; + } +#endif + + return EIDSP_OK; + } + + /** + * Multiply two matrices lazily per row in matrix 1 (MxN * NxK matrix) + * @param i matrix1 row index + * @param row matrix1 row + * @param matrix1_cols matrix1 row size + * @param matrix2 Pointer to matrix2 (NxK) + * @param out_matrix Pointer to out matrix (MxK) + * @returns EIDSP_OK if OK + */ + static int dot_by_row(int i, float *row, size_t matrix1_cols, + quantized_matrix_t *matrix2, matrix_t *out_matrix) + { + if (matrix1_cols != matrix2->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (uint16_t j = 0; j < matrix2->cols; j++) { + float tmp = 0.0; + for (uint16_t k = 0; k < matrix1_cols; k++) { + uint8_t u8 = matrix2->buffer[k * matrix2->cols + j]; + if (u8) { // this matrix appears to be very sparsely populated + tmp += row[k] * quantized_values_one_zero[u8]; + } + } + out_matrix->buffer[i * matrix2->cols + j] = tmp; + } + + return EIDSP_OK; + } + + static void transpose_in_place(matrix_t *matrix) { + // Don't bother if either dim is one, just need to swap the dimension sizes + if( matrix->rows != 1 && matrix->cols != 1) { + size_t size = matrix->cols * matrix->rows - 1; + float temp; // temp for swap + size_t next; // next item to swap + size_t cycleBegin; // index of start of cycle + size_t i; // location in matrix + size_t all_done_mark = 1; + ei_vector done(size+1,false); + + i = 1; // Note that matrix[0] and last element of matrix won't move + while (1) + { + cycleBegin = i; + temp = matrix->buffer[i]; + do + { + size_t col = i % matrix->cols; + size_t row = i / matrix->cols; + // swap row and col to make new idx, b/c we want to know where in the transposed matrix + next = col*matrix->rows + row; + float temp2 = matrix->buffer[next]; + matrix->buffer[next] = temp; + temp = temp2; + done[next] = true; + i = next; + } + while (i != cycleBegin); + + // start next cycle by find next not done + for (i = all_done_mark; done[i]; i++) { + all_done_mark++; // move the high water mark so we don't look again + if(i>=size) { goto LOOP_END; } + } + } + } + LOOP_END: + // finally, swap the row and column dimensions + std::swap(matrix->rows, matrix->cols); + } + + /** + * Transpose an array, souce is destination (from MxN to NxM) + * Note: this temporary allocates a copy of the matrix on the heap. + * @param matrix + * @param rows + * @param columns + * @deprecated You probably want to use transpose_in_place + * @returns EIDSP_OK if OK + */ + static int transpose(matrix_t *matrix) { + int r = transpose(matrix->buffer, matrix->cols, matrix->rows); + if (r != 0) { + return r; + } + + uint16_t old_rows = matrix->rows; + uint16_t old_cols = matrix->cols; + + matrix->rows = old_cols; + matrix->cols = old_rows; + + return EIDSP_OK; + } + + /** + * Transpose an array, source is destination (from MxN to NxM) + * @param matrix + * @param rows + * @param columns + * @deprecated You probably want to use transpose_in_place + * @returns EIDSP_OK if OK + */ + static int transpose(float *matrix, int rows, int columns) { + EI_DSP_MATRIX(temp_matrix, rows, columns); + if (!temp_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + +#if EIDSP_USE_CMSIS_DSP + if (rows > EI_MAX_UINT16 || columns > EI_MAX_UINT16) { + return EIDSP_NARROWING; + } + + const arm_matrix_instance_f32 i_m = { + static_cast(columns), + static_cast(rows), + matrix + }; + arm_matrix_instance_f32 o_m = { + static_cast(rows), + static_cast(columns), + temp_matrix.buffer + }; + arm_status status = arm_mat_trans_f32(&i_m, &o_m); + if (status != ARM_MATH_SUCCESS) { + return status; + } +#else + for (int j = 0; j < rows; j++){ + for (int i = 0; i < columns; i++){ + temp_matrix.buffer[j * columns + i] = matrix[i * rows + j]; + } + } +#endif + + memcpy(matrix, temp_matrix.buffer, rows * columns * sizeof(float)); + + return EIDSP_OK; + } + + /** + * Transpose an array in place (from MxN to NxM) + * Note: this temporary allocates a copy of the matrix on the heap. + * @param matrix + * @param rows + * @param columns + * @returns EIDSP_OK if OK + */ + static int transpose(quantized_matrix_t *matrix) { + int r = transpose(matrix->buffer, matrix->cols, matrix->rows); + if (r != 0) { + return r; + } + + uint16_t old_rows = matrix->rows; + uint16_t old_cols = matrix->cols; + + matrix->rows = old_cols; + matrix->cols = old_rows; + + return EIDSP_OK; + } + + /** + * Transpose an array in place (from MxN to NxM) + * @param matrix + * @param rows + * @param columns + * @returns EIDSP_OK if OK + */ + static int transpose(uint8_t *matrix, int rows, int columns) { + // dequantization function is not used actually... + EI_DSP_QUANTIZED_MATRIX(temp_matrix, rows, columns, &dequantize_zero_one); + if (!temp_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + for (int j = 0; j < rows; j++){ + for (int i = 0; i < columns; i++){ + temp_matrix.buffer[j * columns + i] = matrix[i * rows + j]; + } + } + + memcpy(matrix, temp_matrix.buffer, rows * columns * sizeof(uint8_t)); + + return EIDSP_OK; + } + + /** + * Return the Discrete Cosine Transform of arbitrary type sequence 2. + * @param input Input array (of size N) + * @param N number of items in input and output array + * @returns EIDSP_OK if OK + */ + static int dct2(float *input, size_t N, DCT_NORMALIZATION_MODE normalization = DCT_NORMALIZATION_NONE) { + if (N == 0) { + return EIDSP_OK; + } + + int ret = ei::dct::transform(input, N); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + // for some reason the output is 2x too low... + for (size_t ix = 0; ix < N; ix++) { + input[ix] *= 2; + } + + if (normalization == DCT_NORMALIZATION_ORTHO) { + input[0] = input[0] * sqrt(1.0f / static_cast(4 * N)); + for (size_t ix = 1; ix < N; ix++) { + input[ix] = input[ix] * sqrt(1.0f / static_cast(2 * N)); + } + } + + return EIDSP_OK; + } + + /** + * Discrete Cosine Transform of arbitrary type sequence 2 on a matrix. + * @param matrix + * @returns EIDSP_OK if OK + */ + static int dct2(matrix_t *matrix, DCT_NORMALIZATION_MODE normalization = DCT_NORMALIZATION_NONE) { + for (size_t row = 0; row < matrix->rows; row++) { + int r = dct2(matrix->buffer + (row * matrix->cols), matrix->cols, normalization); + if (r != EIDSP_OK) { + return r; + } + } + + return EIDSP_OK; + } + + /** + * Quantize a float value between zero and one + * @param value Float value + */ + static uint8_t quantize_zero_one(float value) { + const size_t length = sizeof(quantized_values_one_zero) / sizeof(float); + + // look in the table + for (size_t ix = 0; ix < length; ix++) { + if (quantized_values_one_zero[ix] == value) return ix; + } + + // no match? + + if (value < quantized_values_one_zero[0]) { + return quantized_values_one_zero[0]; + } + if (value > quantized_values_one_zero[length - 1]) { + return quantized_values_one_zero[length - 1]; + } + + int lo = 0; + int hi = length - 1; + + while (lo <= hi) { + int mid = (hi + lo) / 2; + + if (value < quantized_values_one_zero[mid]) { + hi = mid - 1; + } else if (value > quantized_values_one_zero[mid]) { + lo = mid + 1; + } else { + return quantized_values_one_zero[mid]; + } + } + + // lo == hi + 1 + return (quantized_values_one_zero[lo] - value) < (value - quantized_values_one_zero[hi]) ? + lo : + hi; + } + + /** + * Dequantize a float value between zero and one + * @param value + */ + static float dequantize_zero_one(uint8_t value) { + return quantized_values_one_zero[value]; + } + + /** + * Pad an array. + * Pads with the reflection of the vector mirrored along the edge of the array. + * @param input Input matrix (MxN) + * @param output Output matrix of size (M+pad_before+pad_after x N) + * @param pad_before Number of items to pad before + * @param pad_after Number of items to pad after + * @returns 0 if OK + */ + static int pad_1d_symmetric(matrix_t *input, matrix_t *output, uint16_t pad_before, uint16_t pad_after) { + if (output->cols != input->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output->rows != input->rows + pad_before + pad_after) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (input->rows == 0) { + EIDSP_ERR(EIDSP_INPUT_MATRIX_EMPTY); + } + + uint32_t pad_before_index = 0; + bool pad_before_direction_up = true; + + for (int32_t ix = pad_before - 1; ix >= 0; ix--) { + memcpy(output->buffer + (input->cols * ix), + input->buffer + (pad_before_index * input->cols), + input->cols * sizeof(float)); + + if (pad_before_index == 0 && !pad_before_direction_up) { + pad_before_direction_up = true; + } + else if (pad_before_index == input->rows - 1 && pad_before_direction_up) { + pad_before_direction_up = false; + } + else if (pad_before_direction_up) { + pad_before_index++; + } + else { + pad_before_index--; + } + } + + memcpy(output->buffer + (input->cols * pad_before), + input->buffer, + input->rows * input->cols * sizeof(float)); + + int32_t pad_after_index = input->rows - 1; + bool pad_after_direction_up = false; + + for (int32_t ix = 0; ix < pad_after; ix++) { + memcpy(output->buffer + (input->cols * (ix + pad_before + input->rows)), + input->buffer + (pad_after_index * input->cols), + input->cols * sizeof(float)); + + if (pad_after_index == 0 && !pad_after_direction_up) { + pad_after_direction_up = true; + } + else if (pad_after_index == static_cast(input->rows) - 1 && pad_after_direction_up) { + pad_after_direction_up = false; + } + else if (pad_after_direction_up) { + pad_after_index++; + } + else { + pad_after_index--; + } + } + + return EIDSP_OK; + } + + /** + * Scale a matrix in place + * @param matrix + * @param scale + * @returns 0 if OK + */ + static int scale(matrix_t *matrix, float scale) { + if (scale == 1.0f) return EIDSP_OK; + +#if EIDSP_USE_CMSIS_DSP + if (matrix->rows > EI_MAX_UINT16 || matrix->cols > EI_MAX_UINT16) { + return EIDSP_NARROWING; + } + + const arm_matrix_instance_f32 mi = { static_cast(matrix->rows), static_cast(matrix->cols), matrix->buffer }; + arm_matrix_instance_f32 mo = { static_cast(matrix->rows), static_cast(matrix->cols), matrix->buffer }; + int status = arm_mat_scale_f32(&mi, scale, &mo); + if (status != ARM_MATH_SUCCESS) { + return status; + } +#else + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + matrix->buffer[ix] *= scale; + } +#endif + return EIDSP_OK; + } + + + /** + * Scale a matrix in place, per row + * @param matrix Input matrix (MxN) + * @param scale_matrix Scale matrix (Mx1) + * @returns 0 if OK + */ + static int scale(matrix_t *matrix, matrix_t *scale_matrix) { + if (matrix->rows != scale_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (scale_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < matrix->rows; row++) { + EI_DSP_MATRIX_B(temp, 1, matrix->cols, matrix->buffer + (row * matrix->cols)); + int ret = scale(&temp, scale_matrix->buffer[row]); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + } + + return EIDSP_OK; + } + + /** + * Add on matrix in place + * @param matrix + * @param addition + * @returns 0 if OK + */ + static int add(matrix_t *matrix, float addition) { + for (uint32_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + matrix->buffer[ix] += addition; + } + return EIDSP_OK; + } + + /** + * Add on a matrix in place, per row + * @param matrix Input matrix (MxN) + * @param add Scale matrix (Mx1) + * @returns 0 if OK + */ + static int add(matrix_t *matrix, matrix_t *add_matrix) { + if (matrix->rows != add_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (add_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < matrix->rows; row++) { + EI_DSP_MATRIX_B(temp, 1, matrix->cols, matrix->buffer + (row * matrix->cols)); + int ret = add(&temp, add_matrix->buffer[row]); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + } + + return EIDSP_OK; + } + + /** + * Subtract from matrix in place + * @param matrix + * @param subtraction + * @returns 0 if OK + */ + static int subtract(matrix_t *matrix, float subtraction) { + for (uint32_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + matrix->buffer[ix] -= subtraction; + } + return EIDSP_OK; + } + + /** + * Add on a matrix in place, per row + * @param matrix Input matrix (MxN) + * @param add Scale matrix (Mx1) + * @returns 0 if OK + */ + static int subtract(matrix_t *matrix, matrix_t *subtract_matrix) { + if (matrix->rows != subtract_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (subtract_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < matrix->rows; row++) { + EI_DSP_MATRIX_B(temp, 1, matrix->cols, matrix->buffer + (row * matrix->cols)); + int ret = subtract(&temp, subtract_matrix->buffer[row]); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + } + + return EIDSP_OK; + } + + /** + * Calculate the root mean square of a matrix, one per row + * @param matrix Matrix of size (MxN) + * @param output_matrix Matrix of size (Mx1) + * @returns 0 if OK + */ + static int rms(matrix_t *matrix, matrix_t *output_matrix) { + if (matrix->rows != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < matrix->rows; row++) { +#if EIDSP_USE_CMSIS_DSP + float rms_result; + arm_rms_f32(matrix->buffer + (row * matrix->cols), matrix->cols, &rms_result); + output_matrix->buffer[row] = rms_result; +#else + float sum = 0.0; + for(size_t ix = 0; ix < matrix->cols; ix++) { + float v = matrix->buffer[(row * matrix->cols) + ix]; + sum += v * v; + } + output_matrix->buffer[row] = sqrt(sum / static_cast(matrix->cols)); +#endif + } + + return EIDSP_OK; + } + + /** + * Calculate the mean over a matrix per row + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Mx1) + */ + static int mean(matrix_t *input_matrix, matrix_t *output_matrix) { + if (input_matrix->rows != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < input_matrix->rows; row++) { +#if EIDSP_USE_CMSIS_DSP + float mean; + arm_mean_f32(input_matrix->buffer + (row * input_matrix->cols), input_matrix->cols, &mean); + output_matrix->buffer[row] = mean; +#else + float sum = 0.0f; + + for (size_t col = 0; col < input_matrix->cols; col++) { + sum += input_matrix->buffer[( row * input_matrix->cols ) + col]; + } + + output_matrix->buffer[row] = sum / input_matrix->cols; +#endif + } + + return EIDSP_OK; + } + + /** + * Calculate the mean over a matrix on axis 0 + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Nx1) + * @returns 0 if OK + */ + static int mean_axis0(matrix_t *input_matrix, matrix_t *output_matrix) { + if (input_matrix->cols != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t col = 0; col < input_matrix->cols; col++) { + // Note - not using CMSIS-DSP here + // gathering up the current columnand moving it into sequential memory to use + // SIMD to calculate the mean would take more time than the simple loop + // so disable this case. The alternative is to use 2 transposes and on a "big" ARM + // platform that will take more time + + float sum = 0.0f; + + for (size_t row = 0; row < input_matrix->rows; row++) { + sum += input_matrix->buffer[( row * input_matrix->cols ) + col]; + } + + output_matrix->buffer[col] = sum / input_matrix->rows; + } + + return EIDSP_OK; + } + + /** + * Calculate the standard deviation over a matrix on axis 0 + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Nx1) + * @returns 0 if OK + */ + static int std_axis0(matrix_t *input_matrix, matrix_t *output_matrix) { +#if EIDSP_USE_CMSIS_DSP + return std_axis0_CMSIS(input_matrix, output_matrix); +#else + + if (input_matrix->cols != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t col = 0; col < input_matrix->cols; col++) { + float sum = 0.0f; + + for (size_t row = 0; row < input_matrix->rows; row++) { + sum += input_matrix->buffer[(row * input_matrix->cols) + col]; + } + + float mean = sum / input_matrix->rows; + + float std = 0.0f; + float tmp; + for (size_t row = 0; row < input_matrix->rows; row++) { + tmp = input_matrix->buffer[(row * input_matrix->cols) + col] - mean; + std += tmp * tmp; + } + + output_matrix->buffer[col] = sqrt(std / input_matrix->rows); + } + + return EIDSP_OK; +#endif + } + + /** + * Get the minimum value in a matrix per row + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Mx1) + */ + static int min(matrix_t *input_matrix, matrix_t *output_matrix) { + if (input_matrix->rows != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < input_matrix->rows; row++) { +#if EIDSP_USE_CMSIS_DSP + float min; + uint32_t ix; + arm_min_f32(input_matrix->buffer + (row * input_matrix->cols), input_matrix->cols, &min, &ix); + output_matrix->buffer[row] = min; +#else + float min = FLT_MAX; + + for (size_t col = 0; col < input_matrix->cols; col++) { + float v = input_matrix->buffer[( row * input_matrix->cols ) + col]; + if (v < min) { + min = v; + } + } + + output_matrix->buffer[row] = min; +#endif + } + + return EIDSP_OK; + } + + /** + * Get the maximum value in a matrix per row + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Mx1) + */ + static int max(matrix_t *input_matrix, matrix_t *output_matrix) { + if (input_matrix->rows != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < input_matrix->rows; row++) { +#if EIDSP_USE_CMSIS_DSP + float max; + uint32_t ix; + arm_max_f32(input_matrix->buffer + (row * input_matrix->cols), input_matrix->cols, &max, &ix); + output_matrix->buffer[row] = max; +#else + float max = -FLT_MAX; + + for (size_t col = 0; col < input_matrix->cols; col++) { + float v = input_matrix->buffer[( row * input_matrix->cols ) + col]; + if (v > max) { + max = v; + } + } + + output_matrix->buffer[row] = max; +#endif + } + + return EIDSP_OK; + } + + /** + * Get the stdev value in a matrix per row + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Mx1) + */ + static int stdev(matrix_t *input_matrix, matrix_t *output_matrix) { + if (input_matrix->rows != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < input_matrix->rows; row++) { +#if EIDSP_USE_CMSIS_DSP + float std; + float var; + cmsis_arm_variance(&input_matrix->buffer[(row * input_matrix->cols)], input_matrix->cols, &var); + arm_sqrt_f32(var, &std); + output_matrix->buffer[row] = std; +#else + float sum = 0.0f; + + for (size_t col = 0; col < input_matrix->cols; col++) { + sum += input_matrix->buffer[(row * input_matrix->cols) + col]; + } + + float mean = sum / input_matrix->cols; + + float std = 0.0f; + + for (size_t col = 0; col < input_matrix->cols; col++) { + float diff; + diff = input_matrix->buffer[(row * input_matrix->cols) + col] - mean; + std += diff * diff; + } + + output_matrix->buffer[row] = sqrt(std / input_matrix->cols); +#endif + } + + return EIDSP_OK; + } + + /** + * Get the skewness value in a matrix per row + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Mx1) + */ + static int skew(matrix_t *input_matrix, matrix_t *output_matrix) { + if (input_matrix->rows != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < input_matrix->rows; row++) { +#if EIDSP_USE_CMSIS_DSP + float mean; + float var; + + // Calculate the mean & variance + arm_mean_f32(input_matrix->buffer + (row * input_matrix->cols), input_matrix->cols, &mean); + cmsis_arm_variance(&input_matrix->buffer[(row * input_matrix->cols)], input_matrix->cols, &var); + + // Calculate m_3 + float m_3; + cmsis_arm_third_moment(&input_matrix->buffer[(row * input_matrix->cols)], input_matrix->cols, mean, &m_3); + + // Calculate (variance)^(3/2) + arm_sqrt_f32(var * var * var, &var); + + // Calculate skew = (m_3) / (variance)^(3/2) + if (var == 0.0f) { + output_matrix->buffer[row] = 0.0f; + } else { + output_matrix->buffer[row] = m_3 / var; + } +#else + float sum = 0.0f; + float mean; + + // Calculate the mean + for (size_t col = 0; col < input_matrix->cols; col++) { + sum += input_matrix->buffer[( row * input_matrix->cols ) + col]; + } + mean = sum / input_matrix->cols; + + // Calculate the m values + float m_3 = 0.0f; + float m_2 = 0.0f; + + for (size_t col = 0; col < input_matrix->cols; col++) { + float diff; + diff = input_matrix->buffer[( row * input_matrix->cols ) + col] - mean; + m_3 += diff * diff * diff; + m_2 += diff * diff; + } + m_3 = m_3 / input_matrix->cols; + m_2 = m_2 / input_matrix->cols; + + // Calculate (m_2)^(3/2) + m_2 = sqrt(m_2 * m_2 * m_2); + + // Calculate skew = (m_3) / (m_2)^(3/2) + if (m_2 == 0.0f) { + output_matrix->buffer[row] = 0.0f; + } else { + output_matrix->buffer[row] = m_3 / m_2; + } +#endif + } + + return EIDSP_OK; + } + + /** + * Get the kurtosis value in a matrix per row + * @param input_matrix Input matrix (MxN) + * @param output_matrix Output matrix (Mx1) + */ + static int kurtosis(matrix_t *input_matrix, matrix_t *output_matrix) { + if (input_matrix->rows != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (size_t row = 0; row < input_matrix->rows; row++) { +#if EIDSP_USE_CMSIS_DSP + float mean; + float var; + + // Calculate mean & variance + arm_mean_f32(input_matrix->buffer + (row * input_matrix->cols), input_matrix->cols, &mean); + cmsis_arm_variance(&input_matrix->buffer[(row * input_matrix->cols)], input_matrix->cols, &var); + + // Calculate m_4 + float m_4; + cmsis_arm_fourth_moment(&input_matrix->buffer[(row * input_matrix->cols)], input_matrix->cols, mean, &m_4); + + // Calculate Fisher kurtosis = (m_4 / variance^2) - 3 + var = var * var; + if (var == 0.0f) { + output_matrix->buffer[row] = -3.0f; + } else { + output_matrix->buffer[row] = (m_4 / var) - 3.0f; + } +#else + // Calculate the mean + float mean = 0.0f; + float sum = 0.0f; + + for (size_t col = 0; col < input_matrix->cols; col++) { + sum += input_matrix->buffer[( row * input_matrix->cols ) + col]; + } + mean = sum / input_matrix->cols; + + // Calculate m_4 & variance + float m_4 = 0.0f; + float variance = 0.0f; + + for (size_t col = 0; col < input_matrix->cols; col++) { + float diff; + diff = input_matrix->buffer[(row * input_matrix->cols) + col] - mean; + float square_diff = diff * diff; + variance += square_diff; + m_4 += square_diff * square_diff; + } + m_4 = m_4 / input_matrix->cols; + variance = variance / input_matrix->cols; + + // Square the variance + variance = variance * variance; + // Calculate Fisher kurtosis = (m_4 / variance^2) - 3 + if (variance == 0.0f) { + output_matrix->buffer[row] = -3.0f; + } else { + output_matrix->buffer[row] = (m_4 / variance) - 3.0f; + } +#endif + } + + return EIDSP_OK; + } + + + /** + * Compute the one-dimensional discrete Fourier Transform for real input. + * This function computes the one-dimensional n-point discrete Fourier Transform (DFT) of + * a real-valued array by means of an efficient algorithm called the Fast Fourier Transform (FFT). + * @param src Source buffer + * @param src_size Size of the source buffer + * @param output Output buffer + * @param output_size Size of the output buffer, should be n_fft / 2 + 1 + * @returns 0 if OK + */ + static int rfft(const float *src, size_t src_size, float *output, size_t output_size, size_t n_fft) { + size_t n_fft_out_features = (n_fft / 2) + 1; + if (output_size != n_fft_out_features) { + EIDSP_ERR(EIDSP_BUFFER_SIZE_MISMATCH); + } + + // truncate if needed + if (src_size > n_fft) { + src_size = n_fft; + } + + // declare input and output arrays + EI_DSP_MATRIX(fft_input, 1, n_fft); + if (!fft_input.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + // copy from src to fft_input + memcpy(fft_input.buffer, src, src_size * sizeof(float)); + // pad to the rigth with zeros + memset(fft_input.buffer + src_size, 0, (n_fft - src_size) * sizeof(kiss_fft_scalar)); + +#if EIDSP_USE_CMSIS_DSP + if (n_fft != 32 && n_fft != 64 && n_fft != 128 && n_fft != 256 && + n_fft != 512 && n_fft != 1024 && n_fft != 2048 && n_fft != 4096) { + int ret = software_rfft(fft_input.buffer, output, n_fft, n_fft_out_features); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + } + else { + // hardware acceleration only works for the powers above... + arm_rfft_fast_instance_f32 rfft_instance; + int status = cmsis_rfft_init_f32(&rfft_instance, n_fft); + if (status != ARM_MATH_SUCCESS) { + return status; + } + + EI_DSP_MATRIX(fft_output, 1, n_fft); + if (!fft_output.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + arm_rfft_fast_f32(&rfft_instance, fft_input.buffer, fft_output.buffer, 0); + + output[0] = fft_output.buffer[0]; + output[n_fft_out_features - 1] = fft_output.buffer[1]; + + size_t fft_output_buffer_ix = 2; + for (size_t ix = 1; ix < n_fft_out_features - 1; ix += 1) { + float rms_result; + arm_rms_f32(fft_output.buffer + fft_output_buffer_ix, 2, &rms_result); + output[ix] = rms_result * sqrt(2); + + fft_output_buffer_ix += 2; + } + } +#else + int ret = software_rfft(fft_input.buffer, output, n_fft, n_fft_out_features); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } +#endif + + return EIDSP_OK; + } + + + /** + * Compute the one-dimensional discrete Fourier Transform for real input. + * This function computes the one-dimensional n-point discrete Fourier Transform (DFT) of + * a real-valued array by means of an efficient algorithm called the Fast Fourier Transform (FFT). + * @param src Source buffer + * @param src_size Size of the source buffer + * @param output Output buffer + * @param output_size Size of the output buffer, should be n_fft / 2 + 1 + * @returns 0 if OK + */ + static int rfft(const float *src, size_t src_size, fft_complex_t *output, size_t output_size, size_t n_fft) { + size_t n_fft_out_features = (n_fft / 2) + 1; + if (output_size != n_fft_out_features) { + EIDSP_ERR(EIDSP_BUFFER_SIZE_MISMATCH); + } + + // truncate if needed + if (src_size > n_fft) { + src_size = n_fft; + } + + // declare input and output arrays + float *fft_input_buffer = NULL; + if (src_size == n_fft) { + fft_input_buffer = (float*)src; + } + + EI_DSP_MATRIX_B(fft_input, 1, n_fft, fft_input_buffer); + if (!fft_input.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + if (!fft_input_buffer) { + // copy from src to fft_input + memcpy(fft_input.buffer, src, src_size * sizeof(float)); + // pad to the rigth with zeros + memset(fft_input.buffer + src_size, 0, (n_fft - src_size) * sizeof(float)); + } + +#if EIDSP_USE_CMSIS_DSP + if (n_fft != 32 && n_fft != 64 && n_fft != 128 && n_fft != 256 && + n_fft != 512 && n_fft != 1024 && n_fft != 2048 && n_fft != 4096) { + int ret = software_rfft(fft_input.buffer, output, n_fft, n_fft_out_features); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + } + else { + // hardware acceleration only works for the powers above... + arm_rfft_fast_instance_f32 rfft_instance; + int status = cmsis_rfft_init_f32(&rfft_instance, n_fft); + if (status != ARM_MATH_SUCCESS) { + return status; + } + + EI_DSP_MATRIX(fft_output, 1, n_fft); + if (!fft_output.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + arm_rfft_fast_f32(&rfft_instance, fft_input.buffer, fft_output.buffer, 0); + + output[0].r = fft_output.buffer[0]; + output[0].i = 0.0f; + output[n_fft_out_features - 1].r = fft_output.buffer[1]; + output[n_fft_out_features - 1].i = 0.0f; + + size_t fft_output_buffer_ix = 2; + for (size_t ix = 1; ix < n_fft_out_features - 1; ix += 1) { + output[ix].r = fft_output.buffer[fft_output_buffer_ix]; + output[ix].i = fft_output.buffer[fft_output_buffer_ix + 1]; + + fft_output_buffer_ix += 2; + } + } +#else + int ret = software_rfft(fft_input.buffer, output, n_fft, n_fft_out_features); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } +#endif + + return EIDSP_OK; + } + + + /** + * Return evenly spaced numbers over a specified interval. + * Returns num evenly spaced samples, calculated over the interval [start, stop]. + * The endpoint of the interval can optionally be excluded. + * + * Based on https://github.com/ntessore/algo/blob/master/linspace.c + * Licensed in public domain (see LICENSE in repository above) + * + * @param start The starting value of the sequence. + * @param stop The end value of the sequence. + * @param number Number of samples to generate. + * @param out Out array, with size `number` + * @returns 0 if OK + */ + static int linspace(float start, float stop, uint32_t number, float *out) + { + if (number < 1 || !out) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + if (number == 1) { + out[0] = start; + return EIDSP_OK; + } + + // step size + float step = (stop - start) / (number - 1); + + // do steps + for (uint32_t ix = 0; ix < number - 1; ix++) { + out[ix] = start + ix * step; + } + + // last entry always stop + out[number - 1] = stop; + + return EIDSP_OK; + } + + /** + * Return evenly spaced q31 numbers over a specified interval. + * Returns num evenly spaced samples, calculated over the interval [start, stop]. + * The endpoint of the interval can optionally be excluded. + * + * Based on https://github.com/ntessore/algo/blob/master/linspace.c + * Licensed in public domain (see LICENSE in repository above) + * + * @param start The starting value of the sequence. + * @param stop The end value of the sequence. + * @param number Number of samples to generate. + * @param out Out array, with size `number` + * @returns 0 if OK + */ + static int linspace(EIDSP_i32 start, EIDSP_i32 stop, uint32_t number, EIDSP_i32 *out) + { + if (number < 1 || !out) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + if (number == 1) { + out[0] = start; + return EIDSP_OK; + } + + // step size + EIDSP_i32 step = (stop - start) / (number - 1); + + // do steps + for (uint32_t ix = 0; ix < number - 1; ix++) { + out[ix] = start + ix * step; + } + + // last entry always stop + out[number - 1] = stop; + + return EIDSP_OK; + } + + /** + * Convert an int16_t buffer into a float buffer + * @param input + * @param output + * @param length + * @returns 0 if OK + */ + static int int16_to_float(const EIDSP_i16 *input, float *output, size_t length) { + for (size_t ix = 0; ix < length; ix++) { + output[ix] = static_cast((input[ix])); + } + return EIDSP_OK; + } + + /** + * Convert an int8_t buffer into a float buffer + * @param input + * @param output + * @param length + * @returns 0 if OK + */ + static int int8_to_float(const EIDSP_i8 *input, float *output, size_t length) { + for (size_t ix = 0; ix < length; ix++) { + output[ix] = static_cast((input[ix])); + } + return EIDSP_OK; + } + +#if EIDSP_SIGNAL_C_FN_POINTER == 0 + /** + * Create a signal structure from a buffer. + * This is useful for data that you keep in memory anyway. If you need to load from + * flash, then create the structure yourself. + * @param data Buffer, make sure to keep this pointer alive + * @param data_size Size of the buffer + * @param signal Output signal + * @returns EIDSP_OK if ok + */ + static int signal_from_buffer(const float *data, size_t data_size, signal_t *signal) + { + signal->total_length = data_size; +#ifdef __MBED__ + signal->get_data = mbed::callback(&numpy::signal_get_data, data); +#else + signal->get_data = [data](size_t offset, size_t length, float *out_ptr) { + return numpy::signal_get_data(data, offset, length, out_ptr); + }; +#endif + return EIDSP_OK; + } + +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + /** + * > 50% faster then the math.h log() function + * in return for a small loss in accuracy (0.00001 average diff with log()) + * From: https://stackoverflow.com/questions/39821367/very-fast-approximate-logarithm-natural-log-function-in-c/39822314#39822314 + * Licensed under the CC BY-SA 3.0 + * @param a Input number + * @returns Natural log value of a + */ + __attribute__((always_inline)) static inline float log(float a) + { + int32_t g = (int32_t) * ((int32_t *)&a); + int32_t e = (g - 0x3f2aaaab) & 0xff800000; + g = g - e; + float m = (float) * ((float *)&g); + float i = (float)e * 1.19209290e-7f; // 0x1.0p-23 + /* m in [2/3, 4/3] */ + float f = m - 1.0f; + float s = f * f; + /* Compute log1p(f) for f in [-1/3, 1/3] */ + float r = fmaf(0.230836749f, f, -0.279208571f); // 0x1.d8c0f0p-3, -0x1.1de8dap-2 + float t = fmaf(0.331826031f, f, -0.498910338f); // 0x1.53ca34p-2, -0x1.fee25ap-2 + r = fmaf(r, s, t); + r = fmaf(r, s, f); + r = fmaf(i, 0.693147182f, r); // 0x1.62e430p-1 // log(2) + + return r; + } + + /** + * Fast log10 and log2 functions, significantly faster than the ones from math.h (~6x for log10 on M4F) + * From https://community.arm.com/developer/tools-software/tools/f/armds-forum/4292/cmsis-dsp-new-functionality-proposal/22621#22621 + * @param a Input number + * @returns Log2 value of a + */ + __attribute__((always_inline)) static inline float log2(float a) + { + int e; + float f = frexpf(fabsf(a), &e); + float y = 1.23149591368684f; + y *= f; + y += -4.11852516267426f; + y *= f; + y += 6.02197014179219f; + y *= f; + y += -3.13396450166353f; + y += e; + return y; + } + + /** + * Fast log10 and log2 functions, significantly faster than the ones from math.h (~6x for log10 on M4F) + * From https://community.arm.com/developer/tools-software/tools/f/armds-forum/4292/cmsis-dsp-new-functionality-proposal/22621#22621 + * @param a Input number + * @returns Log10 value of a + */ + __attribute__((always_inline)) static inline float log10(float a) + { + return numpy::log2(a) * 0.3010299956639812f; + } +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + + /** + * Calculate the natural log value of a matrix. Does an in-place replacement. + * @param matrix Matrix (MxN) + * @returns 0 if OK + */ + static int log(matrix_t *matrix) + { + for (uint32_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + matrix->buffer[ix] = numpy::log(matrix->buffer[ix]); + } + + return EIDSP_OK; + } + + /** + * Calculate the log10 of a matrix. Does an in-place replacement. + * @param matrix Matrix (MxN) + * @returns 0 if OK + */ + static int log10(matrix_t *matrix) + { + for (uint32_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + matrix->buffer[ix] = numpy::log10(matrix->buffer[ix]); + } + + return EIDSP_OK; + } + + /** + * @brief Signed Saturate + * + * @param[in] val The value to be saturated + * @param[in] sat Bit position to saturate to (1..32) + * + * @return Saturated value + */ + static int32_t saturate(int64_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) { + int64_t max = (int64_t)((1U << (sat - 1U)) - 1U); + int64_t min = -1 - max; + if (val > max) { + return (int32_t)max; + } else if (val < min) { + return (int32_t)min; + } + } + return (int32_t)val; + } + + /** + * Normalize a matrix to 0..1. Does an in-place replacement. + * Normalization done per row. + * @param matrix + */ + static int normalize(matrix_t *matrix) { + // Python implementation: + // matrix = (matrix - np.min(matrix)) / (np.max(matrix) - np.min(matrix)) + int r; + + matrix_t temp_matrix(1, matrix->rows * matrix->cols, matrix->buffer); + + matrix_t min_matrix(1, 1); + if (!min_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + r = min(&temp_matrix, &min_matrix); + if (r != EIDSP_OK) { + EIDSP_ERR(r); + } + + matrix_t max_matrix(1, 1); + if (!max_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + r = max(&temp_matrix, &max_matrix); + if (r != EIDSP_OK) { + EIDSP_ERR(r); + } + + float min_max_diff = (max_matrix.buffer[0] - min_matrix.buffer[0]); + /* Prevent divide by 0 by setting minimum value for divider */ + float row_scale = min_max_diff < 0.001 ? 1.0f : 1.0f / min_max_diff; + + r = subtract(&temp_matrix, min_matrix.buffer[0]); + if (r != EIDSP_OK) { + EIDSP_ERR(r); + } + + r = scale(&temp_matrix, row_scale); + if (r != EIDSP_OK) { + EIDSP_ERR(r); + } + + return EIDSP_OK; + } + + /** + * Clip (limit) the values in an array. Does an in-place replacement. + * Values outside the interval are clipped to the interval edges. + * For example, if an interval of [0, 1] is specified, values smaller than 0 become 0, + * and values larger than 1 become 1. + * @param matrix + * @param min Min value to be clipped + * @param max Max value to be clipped + */ + static int clip(matrix_t *matrix, float min, float max) { + if (max < min) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + if (matrix->buffer[ix] < min) { + matrix->buffer[ix] = min; + } + else if (matrix->buffer[ix] > max) { + matrix->buffer[ix] = max; + } + } + + return EIDSP_OK; + } + + /** + * Cut the data behind the comma on a matrix. Does an in-place replacement. + * E.g. around([ 3.01, 4.89 ]) becomes [3, 4] + * @param matrix + */ + static int round(matrix_t *matrix) { + for (size_t ix = 0; ix < matrix->rows * matrix->cols; ix++) { + matrix->buffer[ix] = ::round(matrix->buffer[ix]); + } + + return EIDSP_OK; + } + + static int software_rfft(float *fft_input, float *output, size_t n_fft, size_t n_fft_out_features) { + kiss_fft_cpx *fft_output = (kiss_fft_cpx*)ei_dsp_malloc(n_fft_out_features * sizeof(kiss_fft_cpx)); + if (!fft_output) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + size_t kiss_fftr_mem_length; + + // create fftr context + kiss_fftr_cfg cfg = kiss_fftr_alloc(n_fft, 0, NULL, NULL, &kiss_fftr_mem_length); + if (!cfg) { + ei_dsp_free(fft_output, n_fft_out_features * sizeof(kiss_fft_cpx)); + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + ei_dsp_register_alloc(kiss_fftr_mem_length, cfg); + + // execute the rfft operation + kiss_fftr(cfg, fft_input, fft_output); + + // and write back to the output + for (size_t ix = 0; ix < n_fft_out_features; ix++) { + output[ix] = sqrt(pow(fft_output[ix].r, 2) + pow(fft_output[ix].i, 2)); + } + + ei_dsp_free(cfg, kiss_fftr_mem_length); + ei_dsp_free(fft_output, n_fft_out_features * sizeof(kiss_fft_cpx)); + + return EIDSP_OK; + } + + static int software_rfft(float *fft_input, fft_complex_t *output, size_t n_fft, size_t n_fft_out_features) + { + // create fftr context + size_t kiss_fftr_mem_length; + + kiss_fftr_cfg cfg = kiss_fftr_alloc(n_fft, 0, NULL, NULL, &kiss_fftr_mem_length); + if (!cfg) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + ei_dsp_register_alloc(kiss_fftr_mem_length, cfg); + + // execute the rfft operation + kiss_fftr(cfg, fft_input, (kiss_fft_cpx*)output); + + ei_dsp_free(cfg, kiss_fftr_mem_length); + + return EIDSP_OK; + } + + static int signal_get_data(const float *in_buffer, size_t offset, size_t length, float *out_ptr) + { + memcpy(out_ptr, in_buffer + offset, length * sizeof(float)); + return 0; + } + + static int signal_get_data_i16(int16_t *in_buffer, size_t offset, size_t length, int16_t *out_ptr) + { + memcpy(out_ptr, in_buffer + offset, length * sizeof(int16_t)); + return 0; + } + +#if EIDSP_USE_CMSIS_DSP + /** + * @brief The CMSIS std variance function with the same behaviour as the NumPy + * implementation + * @details Variance in CMSIS version is calculated using fSum / (float32_t)(blockSize - 1) + * @param[in] pSrc Pointer to float block + * @param[in] blockSize Number of floats in block + * @param pResult The variance + */ + static void cmsis_arm_variance(const float32_t *pSrc, uint32_t blockSize, float32_t *pResult) + { + uint32_t blkCnt; + float32_t sum = 0.0f; + float32_t fSum = 0.0f; + float32_t fMean, fValue; + const float32_t *pInput = pSrc; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) { + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) { + sum += *pInput++; + blkCnt--; + } + + fMean = sum / (float32_t)blockSize; + + pInput = pSrc; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float32_t)(blockSize); + } + + /** + * @brief Copy of the numpy version explicitely using the CMSIS lib + * for STD and Matrix transpose + * @param input_matrix The input matrix + * @param output_matrix The output matrix + * + * @return EIDSP error + */ + static int std_axis0_CMSIS(matrix_t *input_matrix, matrix_t *output_matrix) + { + arm_matrix_instance_f32 arm_in_matrix, arm_transposed_matrix; + + if (input_matrix->cols != output_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + /* Copy input matrix to arm matrix */ + arm_in_matrix.numRows = input_matrix->rows; + arm_in_matrix.numCols = input_matrix->cols; + arm_in_matrix.pData = &input_matrix->buffer[0]; + /* Create transposed matrix */ + arm_transposed_matrix.numRows = input_matrix->cols; + arm_transposed_matrix.numCols = input_matrix->rows; + arm_transposed_matrix.pData = (float *)ei_calloc(input_matrix->cols * input_matrix->rows * sizeof(float), 1); + + if (arm_transposed_matrix.pData == NULL) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + int ret = arm_mat_trans_f32(&arm_in_matrix, &arm_transposed_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + for (size_t row = 0; row < arm_transposed_matrix.numRows; row++) { + float std; + float var; + + cmsis_arm_variance(arm_transposed_matrix.pData + (row * arm_transposed_matrix.numCols), + arm_transposed_matrix.numCols, &var); + arm_sqrt_f32(var, &std); + + output_matrix->buffer[row] = std; + } + + ei_free(arm_transposed_matrix.pData); + + return EIDSP_OK; + } + + /** + * @brief A copy of the CMSIS power function, adapted to calculate the third central moment + * @details Calculates the sum of cubes of a block with the mean value subtracted. + * @param[in] pSrc Pointer to float block + * @param[in] blockSize Number of floats in block + * @param[in] mean The mean to subtract from each value before cubing + * @param pResult The third central moment of the input + */ + static void cmsis_arm_third_moment(const float32_t * pSrc, uint32_t blockSize, float32_t mean, float32_t * pResult) + { + uint32_t blkCnt; + float32_t sum = 0.0f; + float32_t in; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) { + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + sum += in * in * in; + + in = *pSrc++; + in = in - mean; + sum += in * in * in; + + in = *pSrc++; + in = in - mean; + sum += in * in * in; + + in = *pSrc++; + in = in - mean; + sum += in * in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) { + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + sum += in * in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + sum = sum / blockSize; + /* Store result to destination */ + *pResult = sum; + } + + /** + * @brief A copy of the CMSIS power function, adapted to calculate the fourth central moment + * @details Calculates the sum of fourth powers of a block with the mean value subtracted. + * @param[in] pSrc Pointer to float block + * @param[in] blockSize Number of floats in block + * @param[in] mean The mean to subtract from each value before calculating fourth power + * @param pResult The fourth central moment of the input + */ + static void cmsis_arm_fourth_moment(const float32_t * pSrc, uint32_t blockSize, float32_t mean, float32_t * pResult) + { + uint32_t blkCnt; + float32_t sum = 0.0f; + float32_t in; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) { + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + float square; + square = in * in; + sum += square * square; + + in = *pSrc++; + in = in - mean; + square = in * in; + sum += square * square; + + in = *pSrc++; + in = in - mean; + square = in * in; + sum += square * square; + + in = *pSrc++; + in = in - mean; + square = in * in; + sum += square * square; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) { + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + float square; + square = in * in; + sum += square * square; + + /* Decrement loop counter */ + blkCnt--; + } + + sum = sum / blockSize; + /* Store result to destination */ + *pResult = sum; + } +#endif // EIDSP_USE_CMSIS_DSP + + static uint8_t count_leading_zeros(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + +#if EIDSP_USE_CMSIS_DSP + /** + * Initialize a CMSIS-DSP fast rfft structure + * We do it this way as this means we can compile out fast_init calls which hints the compiler + * to which tables can be removed + */ + static int cmsis_rfft_init_f32(arm_rfft_fast_instance_f32 *rfft_instance, const size_t n_fft) + { +// ARM cores (ex M55) with Helium extensions (MVEF) need special treatment (Issue 2843) +#if EI_CLASSIFIER_HAS_FFT_INFO == 1 && !defined(ARM_MATH_MVEF) && !defined(EI_CLASSIFIER_LOAD_ALL_FFTS) + arm_status status; + switch (n_fft) { +#if EI_CLASSIFIER_LOAD_FFT_32 == 1 + case 32: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 16U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len16.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len16.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len16.pTwiddle; + rfft_instance->fftLenRFFT = 32U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32; + status = ARM_MATH_SUCCESS; + break; + } +#endif +#if EI_CLASSIFIER_LOAD_FFT_64 == 1 + case 64: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 32U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len32.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len32.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len32.pTwiddle; + rfft_instance->fftLenRFFT = 64U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64; + status = ARM_MATH_SUCCESS; + break; + } +#endif +#if EI_CLASSIFIER_LOAD_FFT_128 == 1 + case 128: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 64U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len64.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len64.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len64.pTwiddle; + rfft_instance->fftLenRFFT = 128U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128; + status = ARM_MATH_SUCCESS; + break; + } +#endif +#if EI_CLASSIFIER_LOAD_FFT_256 == 1 + case 256: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 128U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len128.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len128.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len128.pTwiddle; + rfft_instance->fftLenRFFT = 256U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256; + status = ARM_MATH_SUCCESS; + break; + } +#endif +#if EI_CLASSIFIER_LOAD_FFT_512 == 1 + case 512: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 256U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len256.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len256.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len256.pTwiddle; + rfft_instance->fftLenRFFT = 512U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512; + status = ARM_MATH_SUCCESS; + break; + } +#endif +#if EI_CLASSIFIER_LOAD_FFT_1024 == 1 + case 1024: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 512U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len512.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len512.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len512.pTwiddle; + rfft_instance->fftLenRFFT = 1024U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024; + status = ARM_MATH_SUCCESS; + break; + } +#endif +#if EI_CLASSIFIER_LOAD_FFT_2048 == 1 + case 2048: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 1024U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len1024.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len1024.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len1024.pTwiddle; + rfft_instance->fftLenRFFT = 2048U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048; + status = ARM_MATH_SUCCESS; + break; + } +#endif +#if EI_CLASSIFIER_LOAD_FFT_4096 == 1 + case 4096: { + arm_cfft_instance_f32 *S = &(rfft_instance->Sint); + S->fftLen = 2048U; + S->pTwiddle = NULL; + S->bitRevLength = arm_cfft_sR_f32_len2048.bitRevLength; + S->pBitRevTable = arm_cfft_sR_f32_len2048.pBitRevTable; + S->pTwiddle = arm_cfft_sR_f32_len2048.pTwiddle; + rfft_instance->fftLenRFFT = 4096U; + rfft_instance->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096; + status = ARM_MATH_SUCCESS; + break; + } +#endif + default: + return EIDSP_FFT_TABLE_NOT_LOADED; + } + + return status; +#else + return arm_rfft_fast_init_f32(rfft_instance, n_fft); +#endif + } +#endif // #if EIDSP_USE_CMSIS_DSP + + /** + * Power spectrum of a frame + * @param frame Row of a frame + * @param frame_size Size of the frame + * @param out_buffer Out buffer, size should be fft_points + * @param out_buffer_size Buffer size + * @param fft_points (int): The length of FFT. If fft_length is greater than frame_len, the frames will be zero-padded. + * @returns EIDSP_OK if OK + */ + static int power_spectrum( + float *frame, + size_t frame_size, + float *out_buffer, + size_t out_buffer_size, + uint16_t fft_points) + { + if (out_buffer_size != static_cast(fft_points / 2 + 1)) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + int r = numpy::rfft(frame, frame_size, out_buffer, out_buffer_size, fft_points); + if (r != EIDSP_OK) { + return r; + } + + for (size_t ix = 0; ix < out_buffer_size; ix++) { + out_buffer[ix] = (1.0 / static_cast(fft_points)) * + (out_buffer[ix] * out_buffer[ix]); + } + + return EIDSP_OK; + } + + static int welch_max_hold( + float *input, + size_t input_size, + float *output, + size_t start_bin, + size_t stop_bin, + size_t fft_points, + bool do_overlap) + { + // save off one point to put back, b/c we're going to calculate in place + float saved_point = 0; + bool do_saved_point = false; + size_t fft_out_size = fft_points / 2 + 1; + float *fft_out; + ei_unique_ptr_t p_fft_out(nullptr, ei_free); + if (input_size < fft_points) { + fft_out = (float *)ei_calloc(fft_out_size, sizeof(float)); + p_fft_out.reset(fft_out); + } + else { + // set input as output for in place operation + fft_out = input; + // save off one point to put back, b/c we're going to calculate in place + saved_point = input[fft_points / 2]; + do_saved_point = true; + } + + // init the output to zeros + memset(output, 0, sizeof(float) * (stop_bin - start_bin)); + int input_ix = 0; + while (input_ix < (int)input_size) { + // Figure out if we need any zero padding + size_t n_input_points = input_ix + fft_points <= input_size ? fft_points + : input_size - input_ix; + EI_TRY(power_spectrum( + input + input_ix, + n_input_points, + fft_out, + fft_points / 2 + 1, + fft_points)); + int j = 0; + // keep the max of the last frame and everything before + for (size_t i = start_bin; i < stop_bin; i++) { + output[j] = std::max(output[j], fft_out[i]); + j++; + } + if (do_overlap) { + if (do_saved_point) { + // This step only matters first time through + input[fft_points / 2] = saved_point; + do_saved_point = false; + } + input_ix += fft_points / 2; + } + else { + input_ix += fft_points; + } + } + + return EIDSP_OK; + } + + static float variance(float *input, size_t size) + { + // Use CMSIS either way. Will fall back to straight C when needed + float temp; +#if EIDSP_USE_CMSIS_DSP + arm_var_f32(input, size, &temp); +#else + float mean = 0.0f; + for (size_t i = 0; i < size; i++) { + mean += input[i]; + } + mean /= size; + + temp = 0.0f; + for (size_t i = 0; i < size; i++) { + temp += (input[i] - mean) * (input[i] - mean); + } + temp /= (size - 1); +#endif + return temp; + } + + /** + * This function handle the issue with zero values if the are exposed + * to become an argument for any log function. + * @param input Array + * @param input_size Size of array + * @returns void + */ + static void zero_handling(float *input, size_t input_size) + { + for (size_t ix = 0; ix < input_size; ix++) { + if (input[ix] == 0) { + input[ix] = 1e-10; + } + } + } + + /** + * This function handle the issue with zero values if the are exposed + * to become an argument for any log function. + * @param input Matrix + * @returns void + */ + static void zero_handling(matrix_t *input) + { + zero_handling(input->buffer, input->rows * input->cols); + } + + /** + * This function handle the underflow float values. + * @param input Array + * @param input_size Size of array + * @param epsilon Smallest valid non-zero value + * @returns void + */ + static void underflow_handling(float* input, size_t input_size, float epsilon = 1e-07f) + { + for (size_t ix = 0; ix < input_size; ix++) { + if (fabs(input[ix]) < epsilon) { + input[ix] = 0.0f; + } + } + } + + __attribute__((unused)) static void scale(fvec& v, float scale) { + for (auto& x : v) { + x *= scale; + } + } + + __attribute__((unused)) static void sub(fvec& v, float b) { + for (auto& x : v) { + x -= b; + } + } + + __attribute__((unused)) static void mul(float* y, const float* x, float* b, size_t n) { + for (size_t i = 0; i < n; i++) { + y[i] = x[i] * b[i]; + } + } + + __attribute__((unused)) static fvec diff(const float* v, size_t n) { + fvec d(n - 1); + for (size_t i = 0; i < d.size(); i++) { + d[i] = v[i + 1] - v[i]; + } + return d; + } + + __attribute__((unused)) static float sum(const float* v, size_t n) { + float sum = 0; + for (size_t i = 0; i < n; i++) { + sum += v[i]; + } + return sum; + } + + static float mean(const fvec& v) { + float mean = 0; + for (auto x : v) { + mean += x; + } + mean /= v.size(); + return mean; + } + + static float mean(const float* v, size_t n) { + float mean = 0; + for (size_t i = 0; i < n; i++) { + mean += v[i]; + } + mean /= n; + return mean; + } + + static float median(const float* v, size_t n) { + fvec vc(n); + std::copy(v, v + n, vc.begin()); + std::sort(vc.begin(), vc.end()); + if (vc.size() % 2 == 0) { + return (vc[vc.size() / 2 - 1] + vc[vc.size() / 2]) / 2; + } + return vc[vc.size() / 2]; + } + + __attribute__((unused)) static float median(const fvec& v) { + return median(v.data(), v.size()); + } + + static float stddev(const float* v, size_t n, float m /* mean */, int ddof = 0) { + float var = 0; + for (size_t i = 0; i < n; i++) { + var += (v[i] - m) * (v[i] - m); + } + var /= n - ddof; + return sqrt(var); + } + + __attribute__((unused)) static float stddev(const float* v, size_t n) { + return stddev(v, n, mean(v, n), 0); + } + + __attribute__((unused)) static float stddev(const float* v, size_t n, int ddof) { + return stddev(v, n, mean(v, n), ddof); + } + + __attribute__((unused)) static float stddev(const fvec& v, int ddof = 0) { + return stddev(v.data(), v.size(), mean(v), ddof); + } + + static float rms(const float* v, size_t n) { + float rms = 0; + for (size_t i = 0; i < n; i++) { + rms += v[i] * v[i]; + } + rms /= n; + return sqrt(rms); + } + + __attribute__((unused)) static float rms(const fvec& v) { + return rms(v.data(), v.size()); + } + + template + static float max(const ei_vector& v) { + return *std::max_element(v.begin(), v.end()); + } + + __attribute__((unused)) static float max(const float* v, size_t n) { + return *std::max_element(v, v + n); + } + + template + static float min(const ei_vector& v) { + return *std::min_element(v.begin(), v.end()); + } + + __attribute__((unused)) static float min(const float* v, size_t n) { + return *std::min_element(v, v + n); + } + + __attribute__((unused)) static int argmax(const fvec& v, int start, int end) { + return std::max_element(v.begin() + start, v.begin() + end) - v.begin(); + } + + __attribute__((unused)) static fvec divide(float num, const float* den, size_t n) { + fvec v(n); + for (size_t i = 0; i < n; i++) { + v[i] = num / den[i]; + } + return v; + } + + __attribute__((unused)) static ivec histogram(const float* x, size_t n, int a, int b, int inc) { + int num_bins = (b - a) / inc; + ivec bins(num_bins, 0); + for (size_t i = 0; i < n; i++) { + int bin = (int)((x[i] - a) / inc); + if (bin >= 0 && bin < num_bins) { + bins[bin]++; + } + } + return bins; + } + + __attribute__((unused)) static fvec cumsum(const float* v, size_t n) { + fvec c(n); + c[0] = v[0]; + for (size_t i = 1; i < n; i++) { + c[i] = c[i - 1] + v[i]; + } + return c; + } + + __attribute__((unused)) static fvec arange(float start, float end, float step) { + assert(start < end); + assert(step > 0); + fvec v(::round((end - start) / step)); + for (size_t i = 0; i < v.size(); i++) { + v[i] = start + i * step; + } + return v; + } + + __attribute__((unused)) static void add(fvec& v, fvec& b) { + for (size_t i = 0; i < v.size(); i++) { + v[i] += b[i]; + } + } + + __attribute__((unused)) static float trapz(const fvec& x, const fvec& y, size_t lo, size_t hi) { + float area = 0; + for (size_t i = lo; i < hi; i++) { + area += (x[i + 1] - x[i]) * (y[i + 1] + y[i]) / 2; + } + return area; + } + + __attribute__((unused)) static fvec quantile(const fvec& v, size_t start, size_t end, const fvec& q) { + end = std::min(end, v.size()); + fvec vc(end - start); + std::copy(v.begin() + start, v.begin() + end, vc.begin()); + std::sort(vc.begin(), vc.end()); + fvec res(q.size()); + for (size_t i = 0; i < q.size(); i++) { + res[i] = vc[q[i] * vc.size()]; + } + return res; + } + + __attribute__((unused)) static fvec quantile(const float* v, size_t n, const fvec& q) { + fvec vc(n); + std::copy(v, v + n, vc.begin()); + std::sort(vc.begin(), vc.end()); + fvec res(q.size()); + for (size_t i = 0; i < q.size(); i++) { + res[i] = vc[q[i] * vc.size()]; + } + return res; + } + + static float dot(const float* x, const float* y, size_t n) { + float res = 0; + for (size_t i = 0; i < n; i++) { + res += x[i] * y[i]; + } + return res; + } + + + __attribute__((unused)) static float cosine_similarity(const fvec& x, const fvec& y) { + float xy = dot(x.data(), y.data(), x.size()); + float magx = dot(x.data(), x.data(), x.size()); + float magy = dot(y.data(), y.data(), y.size()); + xy /= sqrt(magx * magy); + return xy; + } + + __attribute__((unused)) static void ln(fvec& v) { + for (auto& x : v) { + x = log(x); + } + } + + static size_t next_power_of_2(size_t x) { + size_t res = 1; + while (res < x) { + res *= 2; + } + return res; + } + + static void detrend(float* data, size_t n) { + // Calculate the mean of the data points + float mean = 0.0; + for (size_t i = 0; i < n; i++) { + mean += data[i]; + } + mean /= n; + + // Calculate the slope of the best-fit line + float x_mean = (n + 1) / 2.0; + float y_mean = mean; + float numerator = 0.0; + float denominator = 0.0; + for (size_t i = 0; i < n; i++) { + numerator += (i + 1 - x_mean) * (data[i] - y_mean); + denominator += (i + 1 - x_mean) * (i + 1 - x_mean); + } + float slope = numerator / denominator; + + // Subtract the best-fit line from the data points to get the detrended data + for (size_t i = 0; i < n; i++) { + data[i] = data[i] - (slope * (i + 1)); + } + + // Calculate the mean of the detrended data + float detrended_mean = 0.0; + for (size_t i = 0; i < n; i++) { + detrended_mean += data[i]; + } + detrended_mean /= n; + + // Subtract the mean of the detrended data from each element + for (size_t i = 0; i < n; i++) { + data[i] -= detrended_mean; + } + } + + static fvec detrend(const fvec& data) { + auto ret = data; + detrend(ret.data(), ret.size()); + return ret; + } + +}; + +struct fmat { + ei_matrix* mat = nullptr; + fmat(size_t rows, size_t cols) { + mat = new ei_matrix(rows, cols); + assert(mat); + } + + ~fmat() { + delete mat; + } + + void resize(size_t rows, size_t cols) { + delete mat; + mat = new ei_matrix(rows, cols); + } + + float* operator[](size_t i) { + if (mat == nullptr || i >= mat->rows) { + return nullptr; + } + return mat->get_row_ptr(i); + } + + void fill(float x) { + if (mat == nullptr) { + return; + } + for (size_t i = 0; i < mat->rows; i++) { + for (size_t j = 0; j < mat->cols; j++) { + (*this)[i][j] = x; + } + } + } + + void fill_col(size_t col, float x) { + if (mat == nullptr) { + return; + } + for (size_t i = 0; i < mat->rows; i++) { + (*this)[i][col] = x; + } + } + + void fill_row(size_t row, float x) { + if (mat == nullptr) { + return; + } + for (size_t i = 0; i < mat->cols; i++) { + (*this)[row][i] = x; + } + } +}; +} // namespace ei + +#endif // _EIDSP_NUMPY_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/numpy_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/numpy_types.h new file mode 100644 index 0000000..98b9c78 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/numpy_types.h @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_NUMPY_TYPES_H_ +#define _EIDSP_NUMPY_TYPES_H_ + +#include +#include +#include +#include +#ifdef __cplusplus +#include +#include "edge-impulse-sdk/dsp/ei_vector.h" +#ifdef __MBED__ +#include "mbed.h" +#endif // __MBED__ +#endif // __cplusplus +#include "config.hpp" +#include "edge-impulse-sdk/dsp/returntypes.h" + +#if EIDSP_TRACK_ALLOCATIONS +#include "memory.hpp" +#endif + +#ifdef __cplusplus +namespace ei { +#endif // __cplusplus + +typedef struct { + float r; + float i; +} fft_complex_t; + +typedef struct { + int32_t r; + int32_t i; +} fft_complex_i32_t; +/** + * A matrix structure that allocates a matrix on the **heap**. + * Freeing happens by calling `delete` on the object or letting the object go out of scope. + */ +typedef struct ei_matrix { + float *buffer; + uint32_t rows; + uint32_t cols; + bool buffer_managed_by_me; + +#if EIDSP_TRACK_ALLOCATIONS + const char *_fn; + const char *_file; + int _line; + uint32_t _originally_allocated_rows; + uint32_t _originally_allocated_cols; +#endif + +#ifdef __cplusplus + /** + * Create a new matrix + * @param n_rows Number of rows + * @param n_cols Number of columns + * @param a_buffer Buffer, if not provided we'll alloc on the heap + */ + ei_matrix( + uint32_t n_rows, + uint32_t n_cols, + float *a_buffer = NULL +#if EIDSP_TRACK_ALLOCATIONS + , + const char *fn = NULL, + const char *file = NULL, + int line = 0 +#endif + ) + { + if (a_buffer) { + buffer = a_buffer; + buffer_managed_by_me = false; + } + else { + buffer = (float*)ei_calloc(n_rows * n_cols * sizeof(float), 1); + buffer_managed_by_me = true; + } + rows = n_rows; + cols = n_cols; + + if (!a_buffer) { +#if EIDSP_TRACK_ALLOCATIONS + _fn = fn; + _file = file; + _line = line; + _originally_allocated_rows = rows; + _originally_allocated_cols = cols; + if (_fn) { + ei_dsp_register_matrix_alloc_internal(fn, file, line, rows, cols, sizeof(float), buffer); + } + else { + ei_dsp_register_matrix_alloc(rows, cols, sizeof(float), buffer); + } +#endif + } + } + + ~ei_matrix() { + if (buffer && buffer_managed_by_me) { + ei_free(buffer); + +#if EIDSP_TRACK_ALLOCATIONS + if (_fn) { + ei_dsp_register_matrix_free_internal(_fn, _file, _line, _originally_allocated_rows, + _originally_allocated_cols, sizeof(float), buffer); + } + else { + ei_dsp_register_matrix_free(_originally_allocated_rows, _originally_allocated_cols, + sizeof(float), buffer); + } +#endif + } + } + + /** + * @brief Get a pointer to the buffer advanced by n rows + * + * @param row Numer of rows to advance the returned buffer pointer + * @return float* Pointer to the buffer at the start of row n + */ + float *get_row_ptr(size_t row) + { + return buffer + row * cols; + } + + ei_matrix(ei_vector &in) : ei_matrix(1, in.size(), in.data()) { + } +#endif // #ifdef __cplusplus +} matrix_t; + + +/** + * A matrix structure that allocates a matrix on the **heap**. + * Freeing happens by calling `delete` on the object or letting the object go out of scope. + */ +typedef struct ei_matrix_i8 { + int8_t *buffer; + uint32_t rows; + uint32_t cols; + bool buffer_managed_by_me; + +#if EIDSP_TRACK_ALLOCATIONS + const char *_fn; + const char *_file; + int _line; + uint32_t _originally_allocated_rows; + uint32_t _originally_allocated_cols; +#endif + +#ifdef __cplusplus + /** + * Create a new matrix + * @param n_rows Number of rows + * @param n_cols Number of columns + * @param a_buffer Buffer, if not provided we'll alloc on the heap + */ + ei_matrix_i8( + uint32_t n_rows, + uint32_t n_cols, + int8_t *a_buffer = NULL +#if EIDSP_TRACK_ALLOCATIONS + , + const char *fn = NULL, + const char *file = NULL, + int line = 0 +#endif + ) + { + if (a_buffer) { + buffer = a_buffer; + buffer_managed_by_me = false; + } + else { + buffer = (int8_t*)ei_calloc(n_rows * n_cols * sizeof(int8_t), 1); + buffer_managed_by_me = true; + } + rows = n_rows; + cols = n_cols; + + if (!a_buffer) { +#if EIDSP_TRACK_ALLOCATIONS + _fn = fn; + _file = file; + _line = line; + _originally_allocated_rows = rows; + _originally_allocated_cols = cols; + if (_fn) { + ei_dsp_register_matrix_alloc_internal(fn, file, line, rows, cols, sizeof(int8_t), buffer); + } + else { + ei_dsp_register_matrix_alloc(rows, cols, sizeof(int8_t), buffer); + } +#endif + } + } + + ~ei_matrix_i8() { + if (buffer && buffer_managed_by_me) { + ei_free(buffer); + +#if EIDSP_TRACK_ALLOCATIONS + if (_fn) { + ei_dsp_register_matrix_free_internal(_fn, _file, _line, _originally_allocated_rows, + _originally_allocated_cols, sizeof(int8_t), buffer); + } + else { + ei_dsp_register_matrix_free(_originally_allocated_rows, _originally_allocated_cols, + sizeof(int8_t), buffer); + } +#endif + } + } + + /** + * @brief Get a pointer to the buffer advanced by n rows + * + * @param row Numer of rows to advance the returned buffer pointer + * @return float* Pointer to the buffer at the start of row n + */ + int8_t *get_row_ptr(size_t row) + { + return buffer + row * cols; + } + +#endif // #ifdef __cplusplus +} matrix_i8_t; + +/** + * A matrix structure that allocates a matrix on the **heap**. + * Freeing happens by calling `delete` on the object or letting the object go out of scope. + */ +typedef struct ei_matrix_i32 { + int32_t *buffer; + uint32_t rows; + uint32_t cols; + bool buffer_managed_by_me; + +#if EIDSP_TRACK_ALLOCATIONS + const char *_fn; + const char *_file; + int _line; + uint32_t _originally_allocated_rows; + uint32_t _originally_allocated_cols; +#endif + +#ifdef __cplusplus + /** + * Create a new matrix + * @param n_rows Number of rows + * @param n_cols Number of columns + * @param a_buffer Buffer, if not provided we'll alloc on the heap + */ + ei_matrix_i32( + uint32_t n_rows, + uint32_t n_cols, + int32_t *a_buffer = NULL +#if EIDSP_TRACK_ALLOCATIONS + , + const char *fn = NULL, + const char *file = NULL, + int line = 0 +#endif + ) + { + if (a_buffer) { + buffer = a_buffer; + buffer_managed_by_me = false; + } + else { + buffer = (int32_t*)ei_calloc(n_rows * n_cols * sizeof(int32_t), 1); + buffer_managed_by_me = true; + } + rows = n_rows; + cols = n_cols; + + if (!a_buffer) { +#if EIDSP_TRACK_ALLOCATIONS + _fn = fn; + _file = file; + _line = line; + _originally_allocated_rows = rows; + _originally_allocated_cols = cols; + if (_fn) { + ei_dsp_register_matrix_alloc_internal(fn, file, line, rows, cols, sizeof(int32_t), buffer); + } + else { + ei_dsp_register_matrix_alloc(rows, cols, sizeof(int32_t), buffer); + } +#endif + } + } + + ~ei_matrix_i32() { + if (buffer && buffer_managed_by_me) { + ei_free(buffer); + +#if EIDSP_TRACK_ALLOCATIONS + if (_fn) { + ei_dsp_register_matrix_free_internal(_fn, _file, _line, _originally_allocated_rows, + _originally_allocated_cols, sizeof(int32_t), buffer); + } + else { + ei_dsp_register_matrix_free(_originally_allocated_rows, _originally_allocated_cols, + sizeof(int32_t), buffer); + } +#endif + } + } + + /** + * @brief Get a pointer to the buffer advanced by n rows + * + * @param row Numer of rows to advance the returned buffer pointer + * @return float* Pointer to the buffer at the start of row n + */ + int32_t *get_row_ptr(size_t row) + { + return buffer + row * cols; + } + +#endif // #ifdef __cplusplus +} matrix_i32_t; + +/** + * Another matrix structure that allocates a matrix on the **heap**. + * Freeing happens by calling `delete` on the object or letting the object go out of scope. + * We use this for the filterbanks, as we quantize these operations to save memory. + */ +typedef struct ei_quantized_matrix { + uint8_t *buffer; + uint32_t rows; + uint32_t cols; + bool buffer_managed_by_me; +#ifdef __MBED__ + mbed::Callback dequantization_fn; +#else + float (*dequantization_fn)(uint8_t); +#endif + +#if EIDSP_TRACK_ALLOCATIONS + const char *_fn; + const char *_file; + int _line; + uint32_t _originally_allocated_rows; + uint32_t _originally_allocated_cols; +#endif + +#ifdef __cplusplus + /** + * Create a quantized matrix + * @param n_rows Number of rows + * @param n_cols Number of columns + * @param a_dequantization_fn How to dequantize the values in this matrix + * @param a_buffer Optional: a buffer, if set we won't allocate memory ourselves + */ + ei_quantized_matrix(uint32_t n_rows, + uint32_t n_cols, +#ifdef __MBED__ + mbed::Callback a_dequantization_fn, +#else + float (*a_dequantization_fn)(uint8_t), +#endif + uint8_t *a_buffer = NULL +#if EIDSP_TRACK_ALLOCATIONS + , + const char *fn = NULL, + const char *file = NULL, + int line = 0 +#endif + ) + { + if (a_buffer) { + buffer = a_buffer; + buffer_managed_by_me = false; + } + else { + buffer = (uint8_t*)ei_calloc(n_rows * n_cols * sizeof(uint8_t), 1); + buffer_managed_by_me = true; + } + rows = n_rows; + cols = n_cols; + dequantization_fn = a_dequantization_fn; + if (!a_buffer) { +#if EIDSP_TRACK_ALLOCATIONS + _fn = fn; + _file = file; + _line = line; + _originally_allocated_rows = rows; + _originally_allocated_cols = cols; + if (_fn) { + ei_dsp_register_matrix_alloc_internal(fn, file, line, rows, cols, sizeof(uint8_t), buffer); + } + else { + ei_dsp_register_matrix_alloc(rows, cols, sizeof(uint8_t), buffer); + } +#endif + } + } + + ~ei_quantized_matrix() { + if (buffer && buffer_managed_by_me) { + ei_free(buffer); + +#if EIDSP_TRACK_ALLOCATIONS + if (_fn) { + ei_dsp_register_matrix_free_internal(_fn, _file, _line, _originally_allocated_rows, + _originally_allocated_cols, sizeof(uint8_t), buffer); + } + else { + ei_dsp_register_matrix_free(_originally_allocated_rows, _originally_allocated_cols, + sizeof(uint8_t), buffer); + } +#endif + } + } + + /** + * @brief Get a pointer to the buffer advanced by n rows + * + * @param row Numer of rows to advance the returned buffer pointer + * @return float* Pointer to the buffer at the start of row n + */ + uint8_t *get_row_ptr(size_t row) + { + return buffer + row * cols; + } + +#endif // #ifdef __cplusplus +} quantized_matrix_t; + +/** + * A matrix structure that allocates a matrix on the **heap**. + * Freeing happens by calling `delete` on the object or letting the object go out of scope. + */ +typedef struct ei_matrix_u8 { + uint8_t *buffer; + uint32_t rows; + uint32_t cols; + bool buffer_managed_by_me; + +#if EIDSP_TRACK_ALLOCATIONS + const char *_fn; + const char *_file; + int _line; + uint32_t _originally_allocated_rows; + uint32_t _originally_allocated_cols; +#endif + +#ifdef __cplusplus + /** + * Create a new matrix + * @param n_rows Number of rows + * @param n_cols Number of columns + * @param a_buffer Buffer, if not provided we'll alloc on the heap + */ + ei_matrix_u8( + uint32_t n_rows, + uint32_t n_cols, + uint8_t *a_buffer = NULL +#if EIDSP_TRACK_ALLOCATIONS + , + const char *fn = NULL, + const char *file = NULL, + int line = 0 +#endif + ) + { + if (a_buffer) { + buffer = a_buffer; + buffer_managed_by_me = false; + } + else { + buffer = (uint8_t*)ei_calloc(n_rows * n_cols * sizeof(uint8_t), 1); + buffer_managed_by_me = true; + } + rows = n_rows; + cols = n_cols; + + if (!a_buffer) { +#if EIDSP_TRACK_ALLOCATIONS + _fn = fn; + _file = file; + _line = line; + _originally_allocated_rows = rows; + _originally_allocated_cols = cols; + if (_fn) { + ei_dsp_register_matrix_alloc_internal(fn, file, line, rows, cols, sizeof(uint8_t), buffer); + } + else { + ei_dsp_register_matrix_alloc(rows, cols, sizeof(uint8_t), buffer); + } +#endif + } + } + + ~ei_matrix_u8() { + if (buffer && buffer_managed_by_me) { + ei_free(buffer); + +#if EIDSP_TRACK_ALLOCATIONS + if (_fn) { + ei_dsp_register_matrix_free_internal(_fn, _file, _line, _originally_allocated_rows, + _originally_allocated_cols, sizeof(uint8_t), buffer); + } + else { + ei_dsp_register_matrix_free(_originally_allocated_rows, _originally_allocated_cols, + sizeof(uint8_t), buffer); + } +#endif + } + } + + /** + * @brief Get a pointer to the buffer advanced by n rows + * + * @param row Numer of rows to advance the returned buffer pointer + * @return float* Pointer to the buffer at the start of row n + */ + uint8_t *get_row_ptr(size_t row) + { + return buffer + row * cols; + } + +#endif // #ifdef __cplusplus +} matrix_u8_t; + +/** + * Size of a matrix + */ +typedef struct { + uint32_t rows; + uint32_t cols; +} matrix_size_t; + +typedef enum { + DCT_NORMALIZATION_NONE, + DCT_NORMALIZATION_ORTHO +} DCT_NORMALIZATION_MODE; + +/** + * @addtogroup ei_structs + * @{ + */ + +/** + * @brief Holds the callback pointer for retrieving raw data and the length + * of data to be retrieved. + * + * Holds the callback function, `get_data(size_t offset, size_t length, float + * *out_ptr)`. This callback should be implemented by the user and fills the memory + * location given by `*out_ptr` with raw features. Features must be flattened to a + * 1-dimensional vector, as described in + * [this guide](https://docs.edgeimpulse.com/docs/deploy-your-model-as-a-c-library#signal-structure). + * + * `get_data()` may be called multiple times during preprocessing or inference (e.g. + * during execution of + * [run_classifier()](https://docs.edgeimpulse.com/reference/run_classifier) or + * [run_classifier_continuous()](https://docs.edgeimpulse.com/reference/run_classifier_continuous)). + * The `offset` argument will update to point to new data, and `length` data must + * be copied into the location specified by `out_ptr`. This scheme allows raw features + * to be stored in RAM or flash memory and paged in as necessary. + * + * Note that `get_data()` (even after multiple calls during a single execution of + * `run_classifier()` or `run_classifier_continuous()`) will never request more than a + * total number of features as given by `total_length`. + * + * **Source**: [dsp/numpy_types.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/dsp/numpy_types.h) + * + * **Example**: [standalone inferencing main.cpp](https://github.com/edgeimpulse/example-standalone-inferencing/blob/master/source/main.cpp) + */ +typedef struct ei_signal_t { + /** + * Callback function to be implemented by the user. Parameters are given as + * `get_data(size_t offset, size_t length, float *out_ptr)` and should return an + * int (e.g. `EIDSP_OK` if copying completed successfully). No bytes will be + * requested outside of the `total_length`. + * Callback parameters: + * `offset`: The offset in the signal + * `length`: The number of samples to write into `out_ptr` + * `out_ptr`: An out buffer to set the signal data + */ +#if EIDSP_SIGNAL_C_FN_POINTER == 1 + int (*get_data)(size_t, size_t, float *); +#else +#ifdef __MBED__ + mbed::Callback get_data; +#else + std::function get_data; +#endif // __MBED__ +#endif // EIDSP_SIGNAL_C_FN_POINTER == 1 + + /** + * Total number of samples the user will provide (via get_data). This value should match either the total number of raw features required for a full window (ie, the window size in Studio, but in samples), OR, if using run_classifier_continuous(), the number of samples in a single slice) + * for a new slice (`run_classifier_continuous()`) in order to perform + * preprocessing and inference. + */ + size_t total_length; +} signal_t; + +/** @} */ + +#ifdef __cplusplus +} // namespace ei { +#endif // __cplusplus + +// required on Adafruit nRF52 +#if defined(__cplusplus) && defined(ARDUINO_NRF52_ADAFRUIT) +namespace std { + __attribute__((weak)) void __throw_bad_function_call() { while(1); }; + __attribute__((weak)) void __throw_length_error(char const*) { while(1); }; +} +#endif // __cplusplus + +#endif // _EIDSP_NUMPY_TYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/returntypes.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/returntypes.h new file mode 100644 index 0000000..a7e7191 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/returntypes.h @@ -0,0 +1,48 @@ +#ifndef _EIDSP_RETURN_TYPES_H_ +#define _EIDSP_RETURN_TYPES_H_ + +#include + +/** + * @defgroup ei_returntypes Return codes + * + * Return codes for Edge Impulse functions. + * + * **Source**: [dsp/returntypes.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/dsp/returntypes.h) + * + * @addtogroup ei_returntypes + * @{ + */ + +// outside of namespace for backwards compat +typedef enum { + EI_IMPULSE_OK = 0, /**< Success */ + EI_IMPULSE_ERROR_SHAPES_DONT_MATCH = -1, /**< The shape of data does not match the shape of input layer. */ + EI_IMPULSE_CANCELED = -2, /**< Impulse execution is cancelled by user. */ + EI_IMPULSE_TFLITE_ERROR = -3, /**< Error in TesnorFlow Lite inference engine */ + EI_IMPULSE_DSP_ERROR = -5, /**< Error in processing portion of impulse */ + EI_IMPULSE_TFLITE_ARENA_ALLOC_FAILED = -6, /**< Failed to allocate memory in TensorFlow Lite arena, often caused by a lack of available heap memory. */ + EI_IMPULSE_CUBEAI_ERROR = -7, /**< Error in CubeAI inference engine (STM32) */ + EI_IMPULSE_ALLOC_FAILED = -8, /**< Memory allocation failed. Could be caused by a fragmented heap. Try to increase heap size. */ + EI_IMPULSE_ONLY_SUPPORTED_FOR_IMAGES = -9, /**< This function is only supported for impulses with an image input. */ + EI_IMPULSE_UNSUPPORTED_INFERENCING_ENGINE = -10, /**< The chosen inference engine (e.g. in Studio) is incapable of running this impulse. */ + EI_IMPULSE_OUT_OF_MEMORY = -11, /**< Out of memory. Could be caused by a fragmented heap. Try to increase heap size. */ + EI_IMPULSE_INPUT_TENSOR_WAS_NULL = -13, /**< Input tensor was null */ + EI_IMPULSE_OUTPUT_TENSOR_WAS_NULL = -14, /**< Output tensor was null */ + EI_IMPULSE_SCORE_TENSOR_WAS_NULL = -15, /**< Score tensor is null (for SSD Object Detection models). */ + EI_IMPULSE_LABEL_TENSOR_WAS_NULL = -16, /**< Label tensor is null (for SSD Object Detection models). */ + EI_IMPULSE_TENSORRT_INIT_FAILED = -17, /**< TensorRT (NVIDIA) initialization failed. */ + EI_IMPULSE_DRPAI_INIT_FAILED = -18, /**< DRP-AI (Renesas) initialization failed. */ + EI_IMPULSE_DRPAI_RUNTIME_FAILED = -19, /**< DRP-AI (Renesas) runtime failed. */ + EI_IMPULSE_DEPRECATED_MODEL = -20, /**< The model is deprecated and cannot be used. You should re-export the impulse from Studio. */ + EI_IMPULSE_LAST_LAYER_NOT_AVAILABLE = -21, /**< The last layer is not available in the model. */ + EI_IMPULSE_INFERENCE_ERROR = -22, /**< Error during inference. */ + EI_IMPULSE_AKIDA_ERROR = -23, /**< Error in Akida inference engine (BrainChip) */ + EI_IMPULSE_INVALID_SIZE = -24, /** +#include "returntypes.h" + +namespace ei { + +typedef enum { + EIDSP_OK = 0, + EIDSP_OUT_OF_MEM = -1002, + EIDSP_SIGNAL_SIZE_MISMATCH = -1003, + EIDSP_MATRIX_SIZE_MISMATCH = -1004, + EIDSP_DCT_ERROR = -1005, + EIDSP_INPUT_MATRIX_EMPTY = -1006, + EIDSP_BUFFER_SIZE_MISMATCH = -1007, + EIDSP_PARAMETER_INVALID = -1008, + EIDSP_UNEXPECTED_NEXT_OFFSET = -1009, + EIDSP_OUT_OF_BOUNDS = -1010, + EIDSP_UNSUPPORTED_FILTER_CONFIG = -1011, + EIDSP_NARROWING = -1012, + EIDSP_BLOCK_VERSION_INCORRECT = -1013, + EIDSP_NOT_SUPPORTED = -1014, + EIDSP_REQUIRES_CMSIS_DSP = -1015, + EIDSP_FFT_TABLE_NOT_LOADED = -1016, + EIDSP_INFERENCE_ERROR = -1017 +} EIDSP_RETURN_T; + +} // namespace ei + +#endif // _EIDSP_RETURN_TYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/feature.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/feature.hpp new file mode 100644 index 0000000..aada87e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/feature.hpp @@ -0,0 +1,679 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPECTRAL_FEATURE_H_ +#define _EIDSP_SPECTRAL_FEATURE_H_ + +#include +#include "processing.hpp" +#include "wavelet.hpp" +#include "signal.hpp" +#include "edge-impulse-sdk/dsp/ei_utils.h" +#include "model-parameters/model_metadata.h" + +namespace ei { +namespace spectral { + +typedef enum { + filter_none = 0, + filter_lowpass = 1, + filter_highpass = 2 +} filter_t; + +class feature { +public: + + /** + * Calculate the spectral features over a signal. + * @param out_features Output matrix. Use `calculate_spectral_buffer_size` to calculate + * the size required. Needs as many rows as `raw_data`. + * @param input_matrix Signal, with one row per axis + * @param sampling_freq Sampling frequency of the signal + * @param filter_type Filter type + * @param filter_cutoff Filter cutoff frequency + * @param filter_order Filter order + * @param fft_length Length of the FFT signal + * @param fft_peaks Number of FFT peaks to find + * @param fft_peaks_threshold Minimum threshold + * @param edges_matrix Spectral power edges + * @returns 0 if OK + */ + static int spectral_analysis( + matrix_t *out_features, + matrix_t *input_matrix, + float sampling_freq, + filter_t filter_type, + float filter_cutoff, + uint8_t filter_order, + uint16_t fft_length, + uint8_t fft_peaks, + float fft_peaks_threshold, + matrix_t *edges_matrix_in + ) { + if (out_features->rows != input_matrix->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (out_features->cols != calculate_spectral_buffer_size(true, fft_peaks, edges_matrix_in->rows)) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (edges_matrix_in->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + int ret; + + size_t axes = input_matrix->rows; + + EI_TRY(processing::subtract_mean(input_matrix) ); + + // apply filter + if (filter_type == filter_lowpass) { + ret = spectral::processing::butterworth_lowpass_filter( + input_matrix, sampling_freq, filter_cutoff, filter_order); + if (ret != EIDSP_OK) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + } + else if (filter_type == filter_highpass) { + ret = spectral::processing::butterworth_highpass_filter( + input_matrix, sampling_freq, filter_cutoff, filter_order); + if (ret != EIDSP_OK) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + } + + // calculate RMS + EI_DSP_MATRIX(rms_matrix, axes, 1); + ret = numpy::rms(input_matrix, &rms_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + // find peaks in FFT + EI_DSP_MATRIX(peaks_matrix, axes, fft_peaks * 2); + + for (size_t row = 0; row < input_matrix->rows; row++) { + // per axis code + + // get a slice of the current axis + EI_DSP_MATRIX_B(axis_matrix, 1, input_matrix->cols, input_matrix->buffer + (row * input_matrix->cols)); + + // calculate FFT + EI_DSP_MATRIX(fft_matrix, 1, fft_length / 2 + 1); + ret = numpy::rfft(axis_matrix.buffer, axis_matrix.cols, fft_matrix.buffer, fft_matrix.cols, fft_length); + if (ret != EIDSP_OK) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + // multiply by 2/N + numpy::scale(&fft_matrix, (2.0f / static_cast(fft_length))); + + // we're now using the FFT matrix to calculate peaks etc. + EI_DSP_MATRIX(peaks_matrix, fft_peaks, 2); + ret = spectral::processing::find_fft_peaks(&fft_matrix, &peaks_matrix, + sampling_freq, fft_peaks_threshold, fft_length); + if (ret != EIDSP_OK) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + // calculate periodogram for spectral power buckets + EI_DSP_MATRIX(period_fft_matrix, 1, fft_length / 2 + 1); + EI_DSP_MATRIX(period_freq_matrix, 1, fft_length / 2 + 1); + ret = spectral::processing::periodogram(&axis_matrix, + &period_fft_matrix, &period_freq_matrix, sampling_freq, fft_length); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + EI_DSP_MATRIX(edges_matrix_out, edges_matrix_in->rows - 1, 1); + ret = spectral::processing::spectral_power_edges( + &period_fft_matrix, + &period_freq_matrix, + edges_matrix_in, + &edges_matrix_out, + sampling_freq); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + float *features_row = out_features->buffer + (row * out_features->cols); + + size_t fx = 0; + + features_row[fx++] = rms_matrix.buffer[row]; + for (size_t peak_row = 0; peak_row < peaks_matrix.rows; peak_row++) { + features_row[fx++] = peaks_matrix.buffer[peak_row * peaks_matrix.cols + 0]; + features_row[fx++] = peaks_matrix.buffer[peak_row * peaks_matrix.cols + 1]; + } + for (size_t edge_row = 0; edge_row < edges_matrix_out.rows; edge_row++) { + features_row[fx++] = edges_matrix_out.buffer[edge_row * edges_matrix_out.cols] / 10.0f; + } + } + + return EIDSP_OK; + } + + + /** + * Calculate the buffer size for Spectral Analysis + * @param rms: Whether to calculate the RMS as part of the features + * @param peaks_count: Number of FFT peaks + * @param spectral_edges_count: Number of spectral edges + */ + static size_t calculate_spectral_buffer_size( + bool rms, size_t peaks_count, size_t spectral_edges_count) + { + size_t count = 0; + if (rms) count++; + count += (peaks_count * 2); + if (spectral_edges_count > 0) { + count += (spectral_edges_count - 1); + } + return count; + } + + static int extract_spectral_analysis_features_v1( + matrix_t *input_matrix, + matrix_t *output_matrix, + ei_dsp_config_spectral_analysis_t *config_ptr, + const float sampling_freq) + { + // scale the signal + int ret = numpy::scale(input_matrix, config_ptr->scale_axes); + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to scale signal (%d)\n", ret); + EIDSP_ERR(ret); + } + + // transpose the matrix so we have one row per axis (nifty!) + ret = numpy::transpose(input_matrix); + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to transpose matrix (%d)\n", ret); + EIDSP_ERR(ret); + } + + // the spectral edges that we want to calculate + matrix_t edges_matrix_in(64, 1); + size_t edge_matrix_ix = 0; + + char spectral_str[128] = { 0 }; + if (strlen(config_ptr->spectral_power_edges) > sizeof(spectral_str) - 1) { + EIDSP_ERR(EIDSP_PARAMETER_INVALID); + } + memcpy( + spectral_str, + config_ptr->spectral_power_edges, + strlen(config_ptr->spectral_power_edges)); + + // convert spectral_power_edges (string) into float array + char *spectral_ptr = spectral_str; + while (spectral_ptr != NULL) { + while ((*spectral_ptr) == ' ') { + spectral_ptr++; + } + + edges_matrix_in.buffer[edge_matrix_ix++] = atof(spectral_ptr); + + // find next (spectral) delimiter (or '\0' character) + while ((*spectral_ptr != ',')) { + spectral_ptr++; + if (*spectral_ptr == '\0') + break; + } + + if (*spectral_ptr == '\0') { + spectral_ptr = NULL; + } + else { + spectral_ptr++; + } + } + edges_matrix_in.rows = edge_matrix_ix; + + // calculate how much room we need for the output matrix + size_t output_matrix_cols = spectral::feature::calculate_spectral_buffer_size( + true, + config_ptr->spectral_peaks_count, + edges_matrix_in.rows); + // ei_printf("output_matrix_size %hux%zu\n", input_matrix.rows, output_matrix_cols); + if (output_matrix->cols * output_matrix->rows != + static_cast(output_matrix_cols * config_ptr->axes)) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + output_matrix->cols = output_matrix_cols; + output_matrix->rows = config_ptr->axes; + + spectral::filter_t filter_type; + if (strcmp(config_ptr->filter_type, "low") == 0) { + filter_type = spectral::filter_lowpass; + } + else if (strcmp(config_ptr->filter_type, "high") == 0) { + filter_type = spectral::filter_highpass; + } + else { + filter_type = spectral::filter_none; + } + + ret = spectral::feature::spectral_analysis( + output_matrix, + input_matrix, + sampling_freq, + filter_type, + config_ptr->filter_cutoff, + config_ptr->filter_order, + config_ptr->fft_length, + config_ptr->spectral_peaks_count, + config_ptr->spectral_peaks_threshold, + &edges_matrix_in); + if (ret != EIDSP_OK) { + ei_printf("ERR: Failed to calculate spectral features (%d)\n", ret); + EIDSP_ERR(ret); + } + + // flatten again + output_matrix->cols = config_ptr->axes * output_matrix_cols; + output_matrix->rows = 1; + + return EIDSP_OK; + } + + static void get_start_stop_bin( + float sampling_freq, + size_t fft_length, + float filter_cutoff, + size_t *start_bin, + size_t *stop_bin, + bool is_high_pass) + { + // we want to find n such that fcutoff < sample_f / fft * n ( or > for high pass ) + // also, + - half bin width (sample_f/(fft*2)) for high / low pass + if (filter_cutoff > sampling_freq / 2) { + filter_cutoff = sampling_freq / 2; + } + float bin = filter_cutoff * fft_length / sampling_freq; + if (is_high_pass) { + *start_bin = static_cast(bin - 0.5) + 1; // add one b/c we want to always round up + // don't use the DC bin b/c it's zero + *start_bin = *start_bin == 0 ? 1 : *start_bin; + *stop_bin = fft_length / 2 + 1; // go one past + } + else { + *start_bin = 1; + *stop_bin = static_cast(bin + 0.5) + 1; // go one past + } + } + + /** + * @brief Calculates the spectral analysis features. + * + * @return the number of features calculated + */ + static size_t extract_spec_features( + matrix_t *input_matrix, + matrix_t *output_matrix, + ei_dsp_config_spectral_analysis_t *config, + const float sampling_freq, + const bool remove_mean = true, + const bool transpose_and_scale_input = true) + { + if (transpose_and_scale_input) { + // transpose the matrix so we have one row per axis + numpy::transpose_in_place(input_matrix); + + // func tests for scale of 1 and does a no op in that case + EI_TRY(numpy::scale(input_matrix, config->scale_axes)); + } + + bool do_filter = false; + bool is_high_pass; + + // apply filter, if enabled + // "zero" order filter allowed. will still remove unwanted fft bins later + if (strcmp(config->filter_type, "low") == 0) { + if( config->filter_order ) { + EI_TRY(spectral::processing::butterworth_lowpass_filter( + input_matrix, + sampling_freq, + config->filter_cutoff, + config->filter_order)); + } + do_filter = true; + is_high_pass = false; + } + else if (strcmp(config->filter_type, "high") == 0) { + if( config->filter_order ) { + EI_TRY(spectral::processing::butterworth_highpass_filter( + input_matrix, + sampling_freq, + config->filter_cutoff, + config->filter_order)); + } + do_filter = true; + is_high_pass = true; + } + + if (remove_mean){ + EI_TRY(processing::subtract_mean(input_matrix)); + } + + // Figure bins we remove based on filter cutoff + size_t start_bin, stop_bin; + if (do_filter) { + get_start_stop_bin( + sampling_freq, + config->fft_length, + config->filter_cutoff, + &start_bin, + &stop_bin, + is_high_pass); + } + else { + start_bin = 1; + stop_bin = config->fft_length / 2 + 1; + } + size_t num_bins = stop_bin - start_bin; + + float *feature_out = output_matrix->buffer; + const float *feature_out_ori = feature_out; + for (size_t row = 0; row < input_matrix->rows; row++) { + float *data_window = input_matrix->get_row_ptr(row); + size_t data_size = input_matrix->cols; + + matrix_t rms_in_matrix(1, data_size, data_window); + matrix_t rms_out_matrix(1, 1, feature_out); + EI_TRY(numpy::rms(&rms_in_matrix, &rms_out_matrix)); + + feature_out++; + + // Standard Deviation + float stddev = *(feature_out-1); //= sqrt(numpy::variance(data_window, data_size)); + if (stddev == 0.0f) { + stddev = 1e-10f; + } + // Don't add std dev as a feature b/c it's the same as RMS + // Skew and Kurtosis w/ shortcut: + // See definition at https://en.wikipedia.org/wiki/Skewness + // See definition at https://en.wikipedia.org/wiki/Kurtosis + // Substitute 0 for mean (b/c it is subtracted out above) + // Skew becomes: mean(X^3) / stddev^3 + // Kurtosis becomes: mean(X^4) / stddev^4 + // Note, this is the Fisher definition of Kurtosis, so subtract 3 + // (see https://docs.scipy.org/doc/scipy/reference/generated/scipy.stats.kurtosis.html) + float s_sum = 0; + float k_sum = 0; + float temp; + for (size_t i = 0; i < data_size; i++) { + temp = data_window[i] * data_window[i] * data_window[i]; + s_sum += temp; + k_sum += temp * data_window[i]; + } + // Skewness out + temp = stddev * stddev * stddev; + *feature_out++ = (s_sum / data_size) / temp; + // Kurtosis out + *feature_out++ = ((k_sum / data_size) / (temp * stddev)) - 3; + + if (config->implementation_version == 4) { + + size_t fft_out_size = config->fft_length / 2 + 1; + ei_vector fft_out(fft_out_size); + EI_TRY(numpy::welch_max_hold( + data_window, + data_size, + fft_out.data(), + 0, + fft_out_size, + config->fft_length, + config->do_fft_overlap)); + + matrix_t x(1, fft_out.size(), const_cast(fft_out.data())); + matrix_t out(1, 1); + + *feature_out++ = (numpy::skew(&x, &out) == EIDSP_OK) ? (out.get_row_ptr(0)[0]) : 0.0f; + *feature_out++ = (numpy::kurtosis(&x, &out) == EIDSP_OK) ? (out.get_row_ptr(0)[0]) : 0.0f; + + for (size_t i = start_bin; i < stop_bin; i++) { + feature_out[i - start_bin] = fft_out[i]; + } + } else { + EI_TRY(numpy::welch_max_hold( + data_window, + data_size, + feature_out, + start_bin, + stop_bin, + config->fft_length, + config->do_fft_overlap)); + } + if (config->do_log) { + numpy::zero_handling(feature_out, num_bins); + ei_matrix temp(num_bins, 1, feature_out); + numpy::log10(&temp); + } + feature_out += num_bins; + } + size_t num_features = feature_out - feature_out_ori; + return num_features; + } + + static int extract_spectral_analysis_features_v2( + matrix_t *input_matrix, + matrix_t *output_matrix, + ei_dsp_config_spectral_analysis_t *config, + const float sampling_freq) + { + size_t n_features = + extract_spec_features(input_matrix, output_matrix, config, sampling_freq); + return n_features == output_matrix->cols ? EIDSP_OK : EIDSP_MATRIX_SIZE_MISMATCH; + } + + static int extract_spectral_analysis_features_v3( + matrix_t *input_matrix, + matrix_t *output_matrix, + ei_dsp_config_spectral_analysis_t *config, + const float sampling_freq) + { + if (strcmp(config->analysis_type, "Wavelet") == 0) { + return wavelet::extract_wavelet_features(input_matrix, output_matrix, config, sampling_freq); + } else { + return extract_spectral_analysis_features_v2(input_matrix, output_matrix, config, sampling_freq); + } + } + + static ei_vector get_ratio_combo(int r) + { + if (r == 1 || r == 3 || r == 10) { + return {r}; + } else if (r == 30) { + return {3, 10}; + } else if (r == 100) { + return {10, 10}; + } else if (r == 1000) { + return {10, 10, 10}; + } else { + assert(0); + } + return {0}; // to make linter happy + } + + // can do in-place or out-of-place + static size_t _decimate(matrix_t *input_matrix, matrix_t *output_matrix, size_t ratio) + { + // generated by build_sav4_header in prepare.py + static float sos_deci_3[] = { + 3.4799547399084973e-05f, 6.959909479816995e-05f, 3.4799547399084973e-05f, 1.0f, -1.416907422639627f, 0.5204552955670066f, 1.0f, 2.0f, 1.0f, 1.0f, -1.3342748248687593f, 0.594631953081447f, 1.0f, 2.0f, 1.0f, 1.0f, -1.237675162600336f, 0.7259326611233617f, 1.0f, 2.0f, 1.0f, 1.0f, -1.2180861262950025f, 0.8987833581253264}; + static float sos_zi_deci_3[] = { 0.0013094887094341828f, -0.0006648423946383296f, + 0.0193087012128479f, -0.010936639208493802f, + 0.1485445305451165f, -0.10217301649013415f, + 0.8250625539381586f, -0.7244268881025758 }; + static float sos_deci_10[] = { 3.5863243209995215e-09f, + 7.172648641999043e-09f, + 3.5863243209995215e-09f, + 1.0f, + -1.8204968644767618f, + 0.8308597403796137f, + 1.0f, + 2.0f, + 1.0f, + 1.0f, + -1.8289505620176847f, + 0.8553173710387741f, + 1.0f, + 2.0f, + 1.0f, + 1.0f, + -1.8517334482627625f, + 0.9015161055713813f, + 1.0f, + 2.0f, + 1.0f, + 1.0f, + -1.8965395961864169f, + 0.9644245584642932 }; + static float sos_zi_deci_10[] = { 1.38071060429997e-06f, -1.146570262401316e-06f, + 0.00020862168862901534f, -0.0001782374705409433f, + 0.016663820918116152f, -0.015002020730727955f, + 0.9773862470492868f, -0.9420150059170858 }; + + assert(ratio == 3 || ratio == 10); + + float* sos = ratio == 3 ? sos_deci_3 : sos_deci_10; + float* sos_zi = ratio == 3 ? sos_zi_deci_3 : sos_zi_deci_10; + + const size_t out_size = signal::get_decimated_size(input_matrix->cols, ratio); + + for (size_t row = 0; row < input_matrix->rows; row++) { + const float *x = input_matrix->get_row_ptr(row); + float *y = output_matrix->get_row_ptr(row); + signal::sosfilt sosfilt(sos, sos_zi, 4); + signal::decimate_simple( + x, + input_matrix->cols, + y, + output_matrix->cols, + ratio, + sosfilt); + } + + return out_size; + } + + static int extract_spectral_analysis_features_v4( + matrix_t *input_matrix, + matrix_t *output_matrix, + ei_dsp_config_spectral_analysis_t *config_p, + const float sampling_freq) + { + auto config_copy = *config_p; + auto config = &config_copy; + if (strcmp(config->analysis_type, "Wavelet") == 0) { + return wavelet::extract_wavelet_features(input_matrix, output_matrix, config, sampling_freq); + } + else if (config->extra_low_freq == false && config->input_decimation_ratio == 1) { + size_t n_features = + extract_spec_features(input_matrix, output_matrix, config, sampling_freq); + return n_features == output_matrix->cols ? EIDSP_OK : EIDSP_MATRIX_SIZE_MISMATCH; + } + else { + numpy::transpose_in_place(input_matrix); + EI_TRY(numpy::scale(input_matrix, config->scale_axes)); + + if (config->input_decimation_ratio > 1) { + ei_vector ratio_combo = get_ratio_combo(config->input_decimation_ratio); + size_t out_size = input_matrix->cols; + for (int r : ratio_combo) { + out_size = _decimate(input_matrix, input_matrix, r); + } + + // rearrange input matrix to be in the right shape after decimation + float* out = input_matrix->get_row_ptr(0) + out_size; + for(uint32_t r = 1; r < input_matrix->rows; r++) { + float *row = input_matrix->get_row_ptr(r); + for(size_t c = 0; c < out_size; c++) { + *out++ = row[c]; + } + } + input_matrix->cols = out_size; + } + + float new_sampling_freq = sampling_freq / config->input_decimation_ratio; + + // filter here, before decimating, instead of inside extract_spec_features + if (strcmp(config->filter_type, "low") == 0) { + if( config->filter_order ) { + EI_TRY(spectral::processing::butterworth_lowpass_filter( + input_matrix, + new_sampling_freq, + config->filter_cutoff, + config->filter_order)); + } + } + else if (strcmp(config->filter_type, "high") == 0) { + if( config->filter_order ) { + EI_TRY(spectral::processing::butterworth_highpass_filter( + input_matrix, + new_sampling_freq, + config->filter_cutoff, + config->filter_order)); + } + } + + // set the filter order to 0, so that we won't double filter + config->filter_order = 0; + + // do this before extract_spec_features because extract_spec_features modifies the matrix + constexpr size_t decimation = 10; + const size_t decimated_size = + signal::get_decimated_size(input_matrix->cols, decimation); + matrix_t lf_signal(input_matrix->rows, decimated_size); + _decimate(input_matrix, &lf_signal, decimation); + + size_t n_features = extract_spec_features( + input_matrix, + output_matrix, + config, + new_sampling_freq, + true, + false); + + if (n_features > 0 && config->extra_low_freq) { + // disable filtering post decimation + matrix_t lf_features(1, output_matrix->rows * output_matrix->cols - n_features, + output_matrix->buffer + n_features); + + n_features += extract_spec_features( + &lf_signal, + &lf_features, + config, + new_sampling_freq / decimation, + true, + false); + } + return n_features == output_matrix->cols ? EIDSP_OK : EIDSP_MATRIX_SIZE_MISMATCH; + } + } +}; + +} // namespace spectral +} // namespace ei + + + +#endif // _EIDSP_SPECTRAL_FEATURE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/filters.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/filters.hpp new file mode 100644 index 0000000..c400fcf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/filters.hpp @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPECTRAL_FILTERS_H_ +#define _EIDSP_SPECTRAL_FILTERS_H_ + +#include +#include "../numpy.hpp" + +#ifndef M_PI +#define M_PI 3.14159265358979323846264338327950288 +#endif // M_PI + +namespace ei { +namespace spectral { +namespace filters { + /** + * The Butterworth filter has maximally flat frequency response in the passband. + * @param filter_order Even filter order (between 2..8) + * @param sampling_freq Sample frequency of the signal + * @param cutoff_freq Cut-off frequency of the signal + * @param src Source array + * @param dest Destination array + * @param size Size of both source and destination arrays + */ + static void butterworth_lowpass( + int filter_order, + float sampling_freq, + float cutoff_freq, + const float *src, + float *dest, + size_t size) + { + int n_steps = filter_order / 2; + float a = tan(M_PI * cutoff_freq / sampling_freq); + float a2 = pow(a, 2); + float *A = (float*)ei_calloc(n_steps, sizeof(float)); + float *d1 = (float*)ei_calloc(n_steps, sizeof(float)); + float *d2 = (float*)ei_calloc(n_steps, sizeof(float)); + float *w0 = (float*)ei_calloc(n_steps, sizeof(float)); + float *w1 = (float*)ei_calloc(n_steps, sizeof(float)); + float *w2 = (float*)ei_calloc(n_steps, sizeof(float)); + + // Calculate the filter parameters + for(int ix = 0; ix < n_steps; ix++) { + float r = sin(M_PI * ((2.0 * ix) + 1.0) / (2.0 * filter_order)); + sampling_freq = a2 + (2.0 * a * r) + 1.0; + A[ix] = a2 / sampling_freq; + d1[ix] = 2.0 * (1 - a2) / sampling_freq; + d2[ix] = -(a2 - (2.0 * a * r) + 1.0) / sampling_freq; + } + + // Apply the filter + for (size_t sx = 0; sx < size; sx++) { + dest[sx] = src[sx]; + + for (int i = 0; i < n_steps; i++) { + w0[i] = d1[i] * w1[i] + d2[i] * w2[i] + dest[sx]; + dest[sx] = A[i] * (w0[i] + (2.0 * w1[i]) + w2[i]); + w2[i] = w1[i]; + w1[i] = w0[i]; + } + } + + ei_free(A); + ei_free(d1); + ei_free(d2); + ei_free(w0); + ei_free(w1); + ei_free(w2); + } + + /** + * The Butterworth filter has maximally flat frequency response in the passband. + * @param filter_order Even filter order (between 2..8) + * @param sampling_freq Sample frequency of the signal + * @param cutoff_freq Cut-off frequency of the signal + * @param src Source array + * @param dest Destination array + * @param size Size of both source and destination arrays + */ + static void butterworth_highpass( + int filter_order, + float sampling_freq, + float cutoff_freq, + const float *src, + float *dest, + size_t size) + { + int n_steps = filter_order / 2; + float a = tan(M_PI * cutoff_freq / sampling_freq); + float a2 = pow(a, 2); + float *A = (float*)ei_calloc(n_steps, sizeof(float)); + float *d1 = (float*)ei_calloc(n_steps, sizeof(float)); + float *d2 = (float*)ei_calloc(n_steps, sizeof(float)); + float *w0 = (float*)ei_calloc(n_steps, sizeof(float)); + float *w1 = (float*)ei_calloc(n_steps, sizeof(float)); + float *w2 = (float*)ei_calloc(n_steps, sizeof(float)); + + // Calculate the filter parameters + for (int ix = 0; ix < n_steps; ix++) { + float r = sin(M_PI * ((2.0 * ix) + 1.0) / (2.0 * filter_order)); + sampling_freq = a2 + (2.0 * a * r) + 1.0; + A[ix] = 1.0f / sampling_freq; + d1[ix] = 2.0 * (1 - a2) / sampling_freq; + d2[ix] = -(a2 - (2.0 * a * r) + 1.0) / sampling_freq; + } + + // Apply the filter + for (size_t sx = 0; sx < size; sx++) { + dest[sx] = src[sx]; + + for (int i = 0; i < n_steps; i++) { + w0[i] = d1[i] * w1[i] + d2[i] * w2[i] + dest[sx]; + dest[sx] = A[i] * (w0[i] - (2.0 * w1[i]) + w2[i]); + w2[i] = w1[i]; + w1[i] = w0[i]; + } + } + + ei_free(A); + ei_free(d1); + ei_free(d2); + ei_free(w0); + ei_free(w1); + ei_free(w2); + } + +} // namespace filters +} // namespace spectral +} // namespace ei + +#endif // _EIDSP_SPECTRAL_FILTERS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/fir_filter.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/fir_filter.hpp new file mode 100644 index 0000000..52c5874 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/fir_filter.hpp @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __FIR_FILTER__H__ +#define __FIR_FILTER__H__ + +#include +#include +#include "filters.hpp" //for M_PI +#include + +/** + * @brief + * + * @tparam input_t Type of input array. Either matrix_i16_t, or matrix_i32_t + * @tparam acc_t Accumulator size that matches above. 64bit for i16 + */ +template +class fir_filter +{ +private: + /** + * @brief Set the taps lowpass object + * + * @param cutoff_normalized Should be in the range 0..0.5 (0.5 being the nyquist) + */ + void set_taps_lowpass(float cutoff_normalized, std::vector &f_taps) + { + //http://www.dspguide.com/ch16/2.htm + float sine_scale = 2 * M_PI * cutoff_normalized; + // offset is M/2...M is filter order -1. so truncation is desired + int offset = filter_size / 2; + for (int i = 0; i < filter_size / 2; i++) + { + f_taps[i] = sin(sine_scale * (i - offset)) / (i - offset); + } + f_taps[filter_size / 2] = sine_scale; + for (int i = filter_size / 2 + 1; i < filter_size; i++) + { + f_taps[i] = sin(sine_scale * (i - offset)) / (i - offset); + } + } + + void apply_hamming(std::vector &f_taps) + { + for (int i = 0; i < filter_size; i++) + { + f_taps[i] *= 0.54 - 0.46 * cos(2 * M_PI * i / (filter_size - 1)); + } + } + + void scale_to_unity_gain(std::vector &f_taps) + { + //find the sum of taps + float sum = 0; + for (auto tap : f_taps) + { + sum += tap; + } + //scale down + for (auto &tap : f_taps) + { + tap /= sum; + } + } + + void convert_lowpass_to_highpass(std::vector &f_taps) + { + for (size_t i = 0; i < f_taps.size(); i += 2) + { + f_taps[i] *= -1; + } + } + +public: + /** + * @brief Perform in place filtering on the input matrix + * @param sampling_frequency Sampling freqency of data + * @param filter_size Number of taps desired (note, filter order +1) + * @param lowpass_cutoff Lowpass cutoff freqency. If 0, will be a high pass filter + * @param highpass_cutoff Highpass cutoff. If 0, will just be a lowpass. If both lowpass and higpass, bandpass + * @param decimation_ratio To downsample, ratio of samples to get rid of. + * For example, 4 to go from sample rate of 40k to 10k. LOWPASS CUTOFF MUST MATCH THIS + * If you don't filter the high frequencies, they WILL alias into the passband + * So in the above example, you would want to cutoff at 5K (so you have some buffer) + */ + fir_filter( + float sampling_frequency, + uint8_t filter_size, + float lowpass_cutoff, + float highpass_cutoff = 0, + int decimation_ratio = 1) : taps(filter_size) , history(filter_size, 0) + { + this->filter_size = filter_size; + std::vector f_taps(filter_size, 0); + if( highpass_cutoff == 0 && lowpass_cutoff == 0 ) + { + ei_printf("You must choose either a lowpass or highpass cutoff"); + return; // return a filter that will return zeros always + } + if (highpass_cutoff == 0) + { + // use normalized frequency + set_taps_lowpass(lowpass_cutoff / sampling_frequency, f_taps); + } + if (lowpass_cutoff == 0) + { + //for highpass, we'll just design a lowpass filter, then invert its spectrum + set_taps_lowpass(highpass_cutoff / sampling_frequency, f_taps); + } + //todo bandpass + apply_hamming(f_taps); + //scale to unity gain in passband (this prevents overflow) + scale_to_unity_gain(f_taps); + // aka if highpass filter + if (lowpass_cutoff == 0) + { + //now invert the spectrum + convert_lowpass_to_highpass(f_taps); + } + // scale and write into fixed point taps + for (int i = 0; i < filter_size; i++) + { + taps[i] = f_taps[i] * 32767; + } + } + +/** + * @brief Apply the filter to the input data. You can do this blockwise, as the object preserves memory of old samples + * Call reset if there's a gap in the data + * + * @param src Source array + * @param dest Output array (can be the same as source for in place) + * @param size Number of samples to process + */ + void apply_filter( + const input_t *src, + input_t *dest, + size_t size) + { + for (size_t i = 0; i < size; i++) + { + history[write_index] = src[i]; + int read_index = write_index; + //minus one b/c of the sign bit + int shift = (sizeof(input_t) * 8) - 1; + //stuff a 1 into one less than we're going to shift to effectively round + //this is essentially resetting the accumulator back to zero otherwise + acc_t accumulator = 1 << (shift - 1); + for (auto tap : taps) + { + accumulator += static_cast(tap) * history[read_index]; + //wrap the read index + read_index = read_index == 0 ? filter_size - 1 : read_index - 1; + } + //wrap the write index + write_index++; + if (write_index == filter_size) + { + write_index = 0; + } + + accumulator >>= shift; + //saturate if overflow + if (accumulator > std::numeric_limits::max()) + { + dest[i] = std::numeric_limits::max(); + } + else if (accumulator < std::numeric_limits::min()) + { + dest[i] = std::numeric_limits::min(); + } + else + { + dest[i] = accumulator; + } + } + } + + /** + * @brief Reset the filter (when changing rows for instance, for a new signal) + * This simply clears the filter history + * + */ + void reset() + { + std::fill(history.begin(), history.end(), 0); + } + +private: + std::vector taps; + std::vector history; + int write_index = 0; + int filter_size; + + friend class AccelerometerQuantizedTestCase; + +}; +#endif //!__FIR_FILTER__H__ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/processing.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/processing.hpp new file mode 100644 index 0000000..c70d516 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/processing.hpp @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPECTRAL_PROCESSING_H_ +#define _EIDSP_SPECTRAL_PROCESSING_H_ + +#include "edge-impulse-sdk/dsp/ei_vector.h" +#include +#include "../numpy.hpp" +#include "filters.hpp" + +namespace ei { +namespace spectral { + +namespace processing { + /** + * Scaling on the signal. + * @param signal: The input signal. + * @param scaling (int): To scale by which factor (e.g. 10 here means multiply by 10) + */ + class scale { +public: + scale(ei_signal_t *signal, float scaling = 1.0f) + : _signal(signal), _scaling(scaling) + { + } + + /** + * Get scaled data from the underlying sensor buffer... + * This retrieves data from the signal then scales it. + * @param offset Offset in the audio signal + * @param length Length of the audio signal + */ + int get_data(size_t offset, size_t length, float *out_buffer) { + if (offset + length > _signal->total_length) { + EIDSP_ERR(EIDSP_OUT_OF_BOUNDS); + } + + int ret = _signal->get_data(offset, length, out_buffer); + if (ret != 0) { + EIDSP_ERR(ret); + } + + EI_DSP_MATRIX_B(temp, 1, length, out_buffer); + return numpy::scale(&temp, _scaling); + } + +private: + ei_signal_t *_signal; + float _scaling; + }; +} + +namespace processing { + typedef struct { + float freq; + float amplitude; + } freq_peak_t; + + typedef struct { + EIDSP_i32 freq; + EIDSP_i32 amplitude; + } freq_peak_i32_t; + + /** + * Scale a the signal. This modifies the signal in place! + * For memory consumption reasons you **probably** want the scaling class, + * which lazily loads the signal in. + * @param signal (array): The input signal. + * @param signal_size: The length of the signal. + * @param scale (float): The scaling factor (multiplies by this number). + * @returns 0 when successful + */ + __attribute__((unused)) static int scale(float *signal, size_t signal_size, float scale = 1) + { + EI_DSP_MATRIX_B(temp, 1, signal_size, signal); + return numpy::scale(&temp, scale); + } + + /** + * Filter data along one-dimension with an IIR or FIR filter using + * Butterworth digital and analog filter design. + * This modifies the matrix in-place (per row) + * @param matrix Input matrix + * @param sampling_freq Sampling frequency + * @param filter_cutoff + * @param filter_order + * @returns 0 when successful + */ + static int butterworth_lowpass_filter( + matrix_t *matrix, + float sampling_frequency, + float filter_cutoff, + uint8_t filter_order) + { + for (size_t row = 0; row < matrix->rows; row++) { + filters::butterworth_lowpass( + filter_order, + sampling_frequency, + filter_cutoff, + matrix->buffer + (row * matrix->cols), + matrix->buffer + (row * matrix->cols), + matrix->cols); + } + + return EIDSP_OK; + } + + /** + * Filter data along one-dimension with an IIR or FIR filter using + * Butterworth digital and analog filter design. + * This modifies the matrix in-place (per row) + * @param matrix Input matrix + * @param sampling_freq Sampling frequency + * @param filter_cutoff + * @param filter_order + * @returns 0 when successful + */ + static int butterworth_highpass_filter( + matrix_t *matrix, + float sampling_frequency, + float filter_cutoff, + uint8_t filter_order) + { + for (size_t row = 0; row < matrix->rows; row++) { + filters::butterworth_highpass( + filter_order, + sampling_frequency, + filter_cutoff, + matrix->buffer + (row * matrix->cols), + matrix->buffer + (row * matrix->cols), + matrix->cols); + } + + return EIDSP_OK; + } + + /** + * Find peaks in a FFT spectrum + * threshold is *normalized* threshold + * (I'm still not completely sure if this matches my Python code but it looks OK) + * @param input_matrix Matrix with FFT data of size 1xM + * @param output_matrix Output matrix with N rows for every peak you want to find. + * @param threshold Minimum threshold + * @param peaks_found Out parameter with the number of peaks found + * @returns 0 if OK + */ + static int find_peak_indexes( + matrix_t *input_matrix, + matrix_t *output_matrix, + float threshold, + uint16_t *peaks_found) + { + if (input_matrix->rows != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + uint16_t out_ix = 0; + size_t in_size = input_matrix->cols; + float *in = input_matrix->buffer; + size_t out_size = output_matrix->rows; + float *out = output_matrix->buffer; + + // for normalized threshold calculation + float min = FLT_MAX, max = 0.0f; + for (size_t ix = 0; ix < in_size - 1; ix++) { + if (in[ix] < min) { + min = in[ix]; + } + if (in[ix] > max) { + max = in[ix]; + } + } + + + float prev = in[0]; + + // so.... + for (size_t ix = 1; ix < in_size - 1; ix++) { + // first make sure it's actually a peak... + if (in[ix] > prev && in[ix] > in[ix+1]) { + // then make sure the threshold is met (on both?) + float height = (in[ix] - prev) + (in[ix] - in[ix + 1]); + // printf("%d inx: %f height: %f threshold: %f\r\n", ix, in[ix], height, threshold); + if (height > threshold) { + out[out_ix] = ix; + out_ix++; + if (out_ix == out_size) break; + } + } + + prev = in[ix]; + } + + *peaks_found = out_ix; + + return EIDSP_OK; + } + + /** + * Find peaks in FFT + * @param fft_matrix Matrix of FFT numbers (1xN) + * @param output_matrix Matrix for the output (Mx2), one row per output you want and two colums per row + * @param sampling_freq How often we sample (in Hz) + * @param threshold Minimum threshold (default: 0.1) + * @returns + */ + static int find_fft_peaks( + matrix_t *fft_matrix, + matrix_t *output_matrix, + float sampling_freq, + float threshold, + uint16_t fft_length) + { + if (fft_matrix->rows != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->cols != 2) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->rows == 0) { + return EIDSP_OK; + } + + int ret; + + int N = static_cast(fft_length); + float T = 1.0f / sampling_freq; + + EI_DSP_MATRIX(freq_space, 1, fft_matrix->cols); + ret = numpy::linspace(0.0f, 1.0f / (2.0f * T), floor(N / 2), freq_space.buffer); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + EI_DSP_MATRIX(peaks_matrix, output_matrix->rows * 10, 1); + + uint16_t peak_count; + ret = find_peak_indexes(fft_matrix, &peaks_matrix, 0.0f, &peak_count); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + // turn this into C++ vector and sort it based on amplitude + ei_vector peaks; + for (uint8_t ix = 0; ix < peak_count; ix++) { + freq_peak_t d; + + d.freq = freq_space.buffer[static_cast(peaks_matrix.buffer[ix])]; + d.amplitude = fft_matrix->buffer[static_cast(peaks_matrix.buffer[ix])]; + // printf("freq %f : %f amp: %f\r\n", peaks_matrix.buffer[ix], d.freq, d.amplitude); + if (d.amplitude < threshold) { + d.freq = 0.0f; + d.amplitude = 0.0f; + } + peaks.push_back(d); + } + sort(peaks.begin(), peaks.end(), + [](const freq_peak_t & a, const freq_peak_t & b) -> bool + { + return a.amplitude > b.amplitude; + }); + + // fill with zeros at the end (if needed) + for (size_t ix = peaks.size(); ix < output_matrix->rows; ix++) { + freq_peak_t d; + d.freq = 0; + d.amplitude = 0; + peaks.push_back(d); + } + + for (size_t row = 0; row < output_matrix->rows; row++) { + // col 0 is freq, col 1 is ampl + output_matrix->buffer[row * output_matrix->cols + 0] = peaks[row].freq; + output_matrix->buffer[row * output_matrix->cols + 1] = peaks[row].amplitude; + } + + return EIDSP_OK; + } + + + /** + * Calculate spectral power edges in a singal + * @param fft_matrix FFT matrix (1xM) + * @param input_matrix_cols Number of columns in the input matrix + * @param edges_matrix The power edges (Nx1) where N=is number of edges + * (e.g. [0.1, 0.5, 1.0, 2.0, 5.0]) + * @param output_matrix Output matrix of size (N-1 x 1) + * @param sampling_freq Sampling frequency + * @returns 0 if OK + */ + int spectral_power_edges( + matrix_t *fft_matrix, + matrix_t *freq_matrix, + matrix_t *edges_matrix, + matrix_t *output_matrix, + float sampling_freq + ) { + if (fft_matrix->rows != 1 || freq_matrix->rows != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (edges_matrix->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (output_matrix->rows != edges_matrix->rows - 1 || output_matrix->cols != edges_matrix->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (fft_matrix->cols != freq_matrix->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + EI_DSP_MATRIX(buckets, 1, edges_matrix->rows - 1); + EI_DSP_MATRIX(bucket_count, 1, edges_matrix->rows - 1); + + for (uint16_t ix = 0; ix < freq_matrix->cols; ix++) { + float t = freq_matrix->buffer[ix]; + float v = fft_matrix->buffer[ix]; + + // does this fit between any edges? + for (uint16_t ex = 0; ex < edges_matrix->rows - 1; ex++) { + if (t >= edges_matrix->buffer[ex] && t < edges_matrix->buffer[ex + 1]) { + buckets.buffer[ex] += v; + bucket_count.buffer[ex]++; + break; + } + } + } + + // average out and push to vector + for (uint16_t ex = 0; ex < edges_matrix->rows - 1; ex++) { + if (bucket_count.buffer[ex] == 0.0f) { + output_matrix->buffer[ex] = 0.0f; + } + else { + output_matrix->buffer[ex] = buckets.buffer[ex] / bucket_count.buffer[ex]; + } + } + + return EIDSP_OK; + } + + + /** + * Estimate power spectral density using a periodogram using Welch's method. + * @param input_matrix Of size 1xN + * @param out_fft_matrix Output matrix of size 1x(n_fft/2+1) with frequency data + * @param out_freq_matrix Output matrix of size 1x(n_fft/2+1) with frequency data + * @param sampling_freq The sampling frequency + * @param n_fft Number of FFT buckets + * @returns 0 if OK + */ + int periodogram(matrix_t *input_matrix, matrix_t *out_fft_matrix, matrix_t *out_freq_matrix, float sampling_freq, uint16_t n_fft) + { + if (input_matrix->rows != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (out_fft_matrix->rows != 1 || out_fft_matrix->cols != static_cast(n_fft / 2 + 1)) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (out_freq_matrix->rows != 1 || out_freq_matrix->cols != static_cast(n_fft / 2 + 1)) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (input_matrix->buffer == NULL) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + if (out_fft_matrix->buffer == NULL) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + if (out_freq_matrix->buffer == NULL) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + // map over the input buffer, so we can manipulate the number of columns + EI_DSP_MATRIX_B(welch_matrix, input_matrix->rows, input_matrix->cols, input_matrix->buffer); + + uint16_t nperseg = n_fft; + + if (n_fft > input_matrix->cols) { + nperseg = input_matrix->cols; + } + // make the column align to nperseg in this case + else if (n_fft < input_matrix->cols) { + welch_matrix.cols = n_fft; + } + + EI_DSP_MATRIX(triage_segments, 1, nperseg); + for (uint16_t ix = 0; ix < nperseg; ix++) { + triage_segments.buffer[ix] = 1.0f; + } + + float scale = 1.0f / (sampling_freq * nperseg); + + for (uint16_t ix = 0; ix < n_fft / 2 + 1; ix++) { + out_freq_matrix->buffer[ix] = static_cast(ix) * (1.0f / (n_fft * (1.0f / sampling_freq))); + } + + int ret; + + // now we need to detrend... which is done constant so just subtract the mean + EI_DSP_MATRIX(mean_matrix, 1, 1); + ret = numpy::mean(&welch_matrix, &mean_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + ret = numpy::subtract(&welch_matrix, &mean_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + fft_complex_t *fft_output = (fft_complex_t*)ei_dsp_calloc((n_fft / 2 + 1) * sizeof(fft_complex_t), 1); + ret = numpy::rfft(welch_matrix.buffer, welch_matrix.cols, fft_output, n_fft / 2 + 1, n_fft); + if (ret != EIDSP_OK) { + ei_dsp_free(fft_output, (n_fft / 2 + 1) * sizeof(fft_complex_t)); + EIDSP_ERR(ret); + } + + // conjugate and then multiply with itself and scale + for (uint16_t ix = 0; ix < n_fft / 2 + 1; ix++) { + fft_output[ix].r = (fft_output[ix].r * fft_output[ix].r) + + (abs(fft_output[ix].i * fft_output[ix].i)); + fft_output[ix].i = 0.0f; + + fft_output[ix].r *= scale; + + if (ix != n_fft / 2) { + fft_output[ix].r *= 2; + } + + // then multiply by itself... + out_fft_matrix->buffer[ix] = fft_output[ix].r; + } + + ei_dsp_free(fft_output, (n_fft / 2 + 1) * sizeof(fft_complex_t)); + + return EIDSP_OK; + } + + static int subtract_mean(matrix_t* input_matrix) { + // calculate the mean + EI_DSP_MATRIX(mean_matrix, input_matrix->rows, 1); + int ret = numpy::mean(input_matrix, &mean_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + // scale by the mean + ret = numpy::subtract(input_matrix, &mean_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + return EIDSP_OK; + } +} // namespace processing +} // namespace spectral +} // namespace ei + +#endif // _EIDSP_SPECTRAL_PROCESSING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/signal.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/signal.hpp new file mode 100644 index 0000000..bf1e5b4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/signal.hpp @@ -0,0 +1,370 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#include "edge-impulse-sdk/dsp/ei_vector.h" +#include +#include + +namespace ei { + +/** + * @brief Class for signal processing. + * tries to mimic scipy.signal + * + * @todo: call CMSIS DSP functions if available + */ +class signal { +public: + using fvec = ei_vector; + + static void scale(fvec& x, float a) + { + for (size_t ix = 0; ix < x.size(); ix++) { + x[ix] *= a; + } + } + + /** + * @brief Decimate a signal using a IIR filter + * This is the counterpart of scipy.signal.decimate with zero-phase=false. This function + * is not recommended for larger decimation factors, as it will have stability issues. + * Use the SOS version instead. + * @param input Input signal + * @param output Output signal + * @param factor Decimation factor + * @param b Numerator coefficients + * @param a Denominator coefficients + * @param zi Initial conditions + */ + static void decimate_simple( + const fvec& input, + fvec& output, + size_t factor, + const fvec& b, + const fvec& a, + const fvec& zi) + { + fvec d = zi; + scale(d, input[0]); + + fvec filtered(input.size()); + lfilter(b, a, input, filtered, d); + + size_t output_size = input.size() / factor; + output.resize(output_size); + + for (size_t ix = 0; ix < output_size; ix++) { + output[ix] = filtered[ix * factor]; + } + } + + static size_t get_decimated_size(size_t input_size, size_t factor) + { + return (input_size + factor - 1) / factor; + } + + struct sosfilt { + const float* coeff = nullptr; // 6 * num_sections coefficients + fvec zi_vec; // 2 * num_sections initial conditions + size_t num_sections = 0; + + sosfilt(const float* coeff_, const float* zi_, size_t num_sections_) + : coeff(coeff_), + zi_vec(zi_, zi_ + (num_sections_ * 2)), + num_sections(num_sections_) + { + } + + sosfilt() + { + } + + void update(const float* coeff_, const float* zi_) + { + assert(num_sections > 0); + coeff = coeff_; + zi_vec.assign(zi_, zi_ + (num_sections * 2)); + } + + void update(const float* coeff_, const float* zi_, size_t num_sections_) + { + num_sections = num_sections_; + coeff = coeff_; + zi_vec.assign(zi_, zi_ + (num_sections * 2)); + } + + /** + * @brief IIR filters in second-order sections. + * This is the counterpart of scipy.signal.sosfilt . + * @param input Input signal + * @param output Output signal. Can be the same as input for in place + * @param x_size Minimum size of input and output signal + */ + void run(const float* input, const size_t size, float* output) + { + assert(num_sections > 0); + + iir2(input, output, size, coeff, coeff + 3, zi_vec.data()); + + for (size_t sect = 1; sect < num_sections; sect++) { + iir2( + output, + output, + size, + coeff + sect * 6, + coeff + sect * 6 + 3, + zi_vec.data() + sect * 2); + } + } + + void init(float x0) + { + for (size_t sect = 0; sect < num_sections; sect++) { + zi_vec[sect * 2] *= x0; + zi_vec[sect * 2 + 1] *= x0; + } + } + }; + + /** + * @brief Decimate a signal using a IIR filter with second-order sections + * This is the counterpart of scipy.signal.decimate with zero-phase=false. + * @param input Input signal + * @param output Output signal + * @param factor Decimation factor + * @param sos Second-order section + */ + static void decimate_simple( + const float* input, + const size_t input_size, + float* output, + const size_t output_size, + size_t factor, + sosfilt& sos) + { + sos.init(input[0]); + + fvec filtered(input_size); + sos.run(input, input_size, filtered.data()); + + size_t expected_size = get_decimated_size(input_size, factor); + assert(output_size >= expected_size); + + for (size_t ix = 0; ix < expected_size; ix++) { + output[ix] = filtered[ix * factor]; + } + } + + /** + * @brief Linear filter. + * This is the counterpart of scipy.signal.lfilter with zero-phase=false. This function + * is not recommended for high order filters or cutoff close to boundaries, as it will + * have stability issues. Use the sosfilt instead. + * @param input Input signal + * @param output Output signal + * @param b Numerator coefficients + * @param a Denominator coefficients + * @param zi Initial conditions + */ + static void lfilter(const fvec& b, const fvec& a, const fvec& x, fvec& y, fvec& d) + { + /* + a[0]*y[n] = b[0] * x[n] + d[0][n-1] + d[0][n] = b[1] * x[n] - a[1] * y[n] + d[1][n-1] + d[1][n] = b[2] * x[n] - a[2] * y[n] + d[2][n-1] + ... + d[N-2][n] = b[N-1]*x[n] - a[N-1]*y[n] + d[N-1][n-1] + d[N-1][n] = b[N] * x[n] - a[N] * y[n] + */ + + assert(b.size() == a.size() && b.size() == d.size() + 1); + assert(d.size() > 0); + assert(y.size() >= x.size()); + assert(a[0] != 0.0f); + + const float one_over_a0 = 1.0f / a[0]; + for (size_t ix = 0; ix < x.size(); ix++) { + const float xx = x[ix]; + y[ix] = b[0] * xx + d[0]; + y[ix] *= one_over_a0; + size_t jx; + for (jx = 1; jx < b.size() - 1; jx++) { + d[jx - 1] = b[jx] * xx - a[jx] * y[ix] + d[jx]; + } + d[jx - 1] = b[jx] * xx - a[jx] * y[ix]; + } + } + + static void iir2(const float* x, float* y, size_t n, const float* b, const float* a, float* d) + { + /* + a[0]*y[n] = b[0] * x[n] + d[0][n-1] + d[0][n] = b[1] * x[n] - a[1] * y[n] + d[1][n-1] + d[1][n] = b[2] * x[n] - a[2] * y[n] + */ + const float one_over_a0 = 1.0f / a[0]; + for (size_t ix = 0; ix < n; ix++) { + const float xx = x[ix]; + y[ix] = b[0] * xx + d[0]; + y[ix] *= one_over_a0; + d[0] = b[1] * xx - a[1] * y[ix] + d[1]; + d[1] = b[2] * xx - a[2] * y[ix]; + } + } + + static int gcd(int a, int b) + { + if (b == 0) + return a; + return gcd(b, a % b); + } + + /** + * @brief Upsample, FIR and downsample. + * This is the counterpart of scipy.signal.upfirdn without the padding. + * @param y Input signal + * @param y Output signal + * @param h FIR coefficients + */ + static void upfirdn(const float* x, size_t x_size, fvec& y, int up, int down, const fvec& h) + { + assert(up > 0); + assert(down > 0); + assert(h.size() > 0); + +#if 0 // bug in optimized version + const int N = (h.size() - 1) / 2; + + for (size_t n = 0; n < y.size(); n++) { + float acc = 0.0f; + for (size_t k = 0; k < h.size(); k += up) { + const size_t x_ind = n * down + k - N; + if (x_ind >= 0 && x_ind < x.size()) { + acc += h[k] * x[x_ind]; + } + } + y[n] = acc; + } +#else + int nx = x_size; + int nh = h.size(); + + // Upsample the input signal by inserting zeros + fvec r(up * nx); + for (int i = 0; i < nx; i++) + { + r[i * up] = x[i]; + } + + // Filter the upsampled signal using the given filter coefficients + fvec z(nh + up * nx - 1); + for (int i = 0; i < up * nx; i++) + { + for (int j = 0; j < nh; j++) + { + if (i - j >= 0 && i - j < up * nx) + { + z[i] += r[i - j] * h[j]; + } + } + } + + // Downsample the filtered signal by skipping samples + int skip = (nh - 1) / 2; + for (size_t i = 0; i < y.size(); i++) + { + y[i] = z[i * down + skip]; + } +#endif + + } + + /** + * @brief Resample using a polyphase FIR. + * This is the counterpart of scipy.signal.resample_poly. + * @param input Input signal + * @param output Output signal, will be moved from an internal vector sized correctly. + * @param window FIR coefficients. e.g. signal.firwin(2 * half_len + 1, f_c, window=('kaiser', 5.0)) + */ + static void resample_poly(const float* input, size_t input_size, fvec& output, int up, int down, const fvec& window) + { + assert(up > 0); + assert(down > 0); + assert(window.size() > 0 && (window.size() % 2) == 1); + + int gcd_up_down = gcd(up, down); + up /= gcd_up_down; + down /= gcd_up_down; + + if (up == 1 && down == 1) { + // output = std::move(fvec(input, input + input_size)); + output = fvec(input, input + input_size); + return; + } + + int n_out = (input_size * up); + n_out = n_out / down + (n_out % down == 0 ? 0 : 1); + + fvec h = window; + scale(h, float(up)); + + output.resize(n_out); + upfirdn(input, input_size, output, up, down, h); + } + + static void calc_decimation_ratios( + const char* filter_type, + float filter_cutoff, + float sample_rate, + std::vector& ratios) + { + if (strcmp(filter_type, "low") == 0) { + ratios = { 1 }; + return; + } + + static const std::vector supported = { 1000, 100, 30, 10, 3 }; + for (size_t i = 0; i < supported.size(); i++) { + const int r = supported[i]; + if (sample_rate * 0.5f / r > filter_cutoff) { + if (r == 3 || r == 10) { + ratios = { r }; + } + else if (r == 30) { + ratios = { 3, 10 }; + } + else if (r == 100) { + ratios = { 10, 10 }; + } + else if (r == 1000) { + ratios = { 10, 10, 10 }; + } + return; + } + } + + } +}; + +} // namespace ei diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/spectral.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/spectral.hpp new file mode 100644 index 0000000..0c8b876 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/spectral.hpp @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPECTRAL_SPECTRAL_H_ +#define _EIDSP_SPECTRAL_SPECTRAL_H_ + +#include "../config.hpp" +#include "processing.hpp" +#include "feature.hpp" + +#endif // _EIDSP_SPECTRAL_SPECTRAL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/wavelet.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/wavelet.hpp new file mode 100644 index 0000000..ba19b29 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/wavelet.hpp @@ -0,0 +1,354 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#include "edge-impulse-sdk/dsp/ei_vector.h" + +#include "processing.hpp" +#include "wavelet_coeff.hpp" + +namespace ei { +namespace spectral { + +using fvec = ei_vector; + +inline float dot(const float *x, const float *y, size_t sz) +{ + float sum = 0.0f; + for (size_t i = 0; i < sz; i++) { + sum += x[i] * y[i]; + } + return sum; +} + +inline void histo(const fvec &x, size_t nbins, fvec &h, bool normalize = false) +{ + float min = *std::min_element(x.begin(), x.end()); + float max = *std::max_element(x.begin(), x.end()); + float step = (max - min) / nbins; + h.resize(nbins); + for (size_t i = 0; i < x.size(); i++) { + size_t bin = (x[i] - min) / step; + if (bin >= nbins) + bin = nbins - 1; + h[bin]++; + } + if (normalize) { + float s = numpy::sum(h.data(), h.size()); + for (size_t i = 0; i < nbins; i++) { + h[i] /= s; + } + } +} + +class wavelet { + + static constexpr size_t NUM_FEATHERS_PER_COMP = 14; + + template + static void get_filter(const std::array, 2> wav, fvec &h, fvec &g) + { + size_t n = wav[0].size(); + h.resize(n); + g.resize(n); + for (size_t i = 0; i < n; i++) { + h[i] = wav[0][n - i - 1]; + g[i] = wav[1][n - i - 1]; + } + } + + static void find_filter(const char *wav, fvec &h, fvec &g) + { + if (strcmp(wav, "bior1.3") == 0) get_filter<6>(bior1p3, h, g); + else if (strcmp(wav, "bior1.5") == 0) get_filter<10>(bior1p5, h, g); + else if (strcmp(wav, "bior2.2") == 0) get_filter<6>(bior2p2, h, g); + else if (strcmp(wav, "bior2.4") == 0) get_filter<10>(bior2p4, h, g); + else if (strcmp(wav, "bior2.6") == 0) get_filter<14>(bior2p6, h, g); + else if (strcmp(wav, "bior2.8") == 0) get_filter<18>(bior2p8, h, g); + else if (strcmp(wav, "bior3.1") == 0) get_filter<4>(bior3p1, h, g); + else if (strcmp(wav, "bior3.3") == 0) get_filter<8>(bior3p3, h, g); + else if (strcmp(wav, "bior3.5") == 0) get_filter<12>(bior3p5, h, g); + else if (strcmp(wav, "bior3.7") == 0) get_filter<16>(bior3p7, h, g); + else if (strcmp(wav, "bior3.9") == 0) get_filter<20>(bior3p9, h, g); + else if (strcmp(wav, "bior4.4") == 0) get_filter<10>(bior4p4, h, g); + else if (strcmp(wav, "bior5.5") == 0) get_filter<12>(bior5p5, h, g); + else if (strcmp(wav, "bior6.8") == 0) get_filter<18>(bior6p8, h, g); + else if (strcmp(wav, "coif1") == 0) get_filter<6>(coif1, h, g); + else if (strcmp(wav, "coif2") == 0) get_filter<12>(coif2, h, g); + else if (strcmp(wav, "coif3") == 0) get_filter<18>(coif3, h, g); + else if (strcmp(wav, "db2") == 0) get_filter<4>(db2, h, g); + else if (strcmp(wav, "db3") == 0) get_filter<6>(db3, h, g); + else if (strcmp(wav, "db4") == 0) get_filter<8>(db4, h, g); + else if (strcmp(wav, "db5") == 0) get_filter<10>(db5, h, g); + else if (strcmp(wav, "db6") == 0) get_filter<12>(db6, h, g); + else if (strcmp(wav, "db7") == 0) get_filter<14>(db7, h, g); + else if (strcmp(wav, "db8") == 0) get_filter<16>(db8, h, g); + else if (strcmp(wav, "db9") == 0) get_filter<18>(db9, h, g); + else if (strcmp(wav, "db10") == 0) get_filter<20>(db10, h, g); + else if (strcmp(wav, "haar") == 0) get_filter<2>(haar, h, g); + else if (strcmp(wav, "rbio1.3") == 0) get_filter<6>(rbio1p3, h, g); + else if (strcmp(wav, "rbio1.5") == 0) get_filter<10>(rbio1p5, h, g); + else if (strcmp(wav, "rbio2.2") == 0) get_filter<6>(rbio2p2, h, g); + else if (strcmp(wav, "rbio2.4") == 0) get_filter<10>(rbio2p4, h, g); + else if (strcmp(wav, "rbio2.6") == 0) get_filter<14>(rbio2p6, h, g); + else if (strcmp(wav, "rbio2.8") == 0) get_filter<18>(rbio2p8, h, g); + else if (strcmp(wav, "rbio3.1") == 0) get_filter<4>(rbio3p1, h, g); + else if (strcmp(wav, "rbio3.3") == 0) get_filter<8>(rbio3p3, h, g); + else if (strcmp(wav, "rbio3.5") == 0) get_filter<12>(rbio3p5, h, g); + else if (strcmp(wav, "rbio3.7") == 0) get_filter<16>(rbio3p7, h, g); + else if (strcmp(wav, "rbio3.9") == 0) get_filter<20>(rbio3p9, h, g); + else if (strcmp(wav, "rbio4.4") == 0) get_filter<10>(rbio4p4, h, g); + else if (strcmp(wav, "rbio5.5") == 0) get_filter<12>(rbio5p5, h, g); + else if (strcmp(wav, "rbio6.8") == 0) get_filter<18>(rbio6p8, h, g); + else if (strcmp(wav, "sym2") == 0) get_filter<4>(sym2, h, g); + else if (strcmp(wav, "sym3") == 0) get_filter<6>(sym3, h, g); + else if (strcmp(wav, "sym4") == 0) get_filter<8>(sym4, h, g); + else if (strcmp(wav, "sym5") == 0) get_filter<10>(sym5, h, g); + else if (strcmp(wav, "sym6") == 0) get_filter<12>(sym6, h, g); + else if (strcmp(wav, "sym7") == 0) get_filter<14>(sym7, h, g); + else if (strcmp(wav, "sym8") == 0) get_filter<16>(sym8, h, g); + else if (strcmp(wav, "sym9") == 0) get_filter<18>(sym9, h, g); + else if (strcmp(wav, "sym10") == 0) get_filter<20>(sym10, h, g); + else assert(0); // wavelet not in the list + } + + static void calculate_entropy(const fvec &y, fvec &features) + { + fvec h; + histo(y, 100, h, true); + // entropy = -sum(prob * log(prob) + float entropy = 0.0f; + for (size_t i = 0; i < h.size(); i++) { + if (h[i] > 0.0f) { + entropy -= h[i] * log(h[i]); + } + } + features.push_back(entropy); + } + + static float get_percentile_from_sorted(const fvec &sorted, float percentile) + { + // adding 0.5 is a trick to get rounding out of C flooring behavior during cast + size_t index = (size_t) ((percentile * (sorted.size()-1)) + 0.5); + return sorted[index]; + } + + static void calculate_statistics(const fvec &y, fvec &features, float mean) + { + fvec sorted = y; + std::sort(sorted.begin(), sorted.end()); + features.push_back(get_percentile_from_sorted(sorted,0.05)); + features.push_back(get_percentile_from_sorted(sorted,0.25)); + features.push_back(get_percentile_from_sorted(sorted,0.75)); + features.push_back(get_percentile_from_sorted(sorted,0.95)); + features.push_back(get_percentile_from_sorted(sorted,0.5)); + + matrix_t x(1, y.size(), const_cast(y.data())); + matrix_t out(1, 1); + + features.push_back(mean); + if (numpy::stdev(&x, &out) == EIDSP_OK) + features.push_back(out.get_row_ptr(0)[0]); + features.push_back(numpy::variance(const_cast(y.data()), y.size())); + if (numpy::rms(&x, &out) == EIDSP_OK) + features.push_back(out.get_row_ptr(0)[0]); + if (numpy::skew(&x, &out) == EIDSP_OK) + features.push_back(out.get_row_ptr(0)[0]); + if (numpy::kurtosis(&x, &out) == EIDSP_OK) + features.push_back(out.get_row_ptr(0)[0]); + } + + static void calculate_crossings(const fvec &y, fvec &features, float mean) + { + size_t zc = 0; + for (size_t i = 1; i < y.size(); i++) { + if (y[i] * y[i - 1] < 0) { + zc++; + } + } + features.push_back(zc / (float)y.size()); + + size_t mc = 0; + for (size_t i = 1; i < y.size(); i++) { + if ((y[i] - mean) * (y[i - 1] - mean) < 0) { + mc++; + } + } + features.push_back(mc / (float)y.size()); + } + + static void + dwt(const float *x, size_t nx, const float *h, const float *g, size_t nh, fvec &a, fvec &d) + { + assert(nh <= 20 && nh > 0 && nx > 0); + size_t nx_padded = nx + nh * 2 - 2; + fvec x_padded(nx_padded); + + // symmetric padding (default in PyWavelet) + for (size_t i = 0; i < nh - 2; i++) + x_padded[i] = x[nh - 3 - i]; + for (size_t i = 0; i < nx; i++) + x_padded[i + nh - 2] = x[i]; + for (size_t i = 0; i < nh; i++) + x_padded[i + nx + nh - 2] = x[nx - 1 - i]; + + size_t ny = (nx + nh - 1) / 2; + a.resize(ny); + d.resize(ny); + + // decimate and filter + const float *xx = x_padded.data(); + for (size_t i = 0; i < ny; i++) { + a[i] = dot(xx + 2 * i, h, nh); + d[i] = dot(xx + 2 * i, g, nh); + } + + numpy::underflow_handling(d.data(), d.size()); + numpy::underflow_handling(a.data(), a.size()); + } + + static void extract_features(fvec& y, fvec &features) + { + matrix_t x(1, y.size(), const_cast(y.data())); + matrix_t out(1, 1); + if (numpy::mean(&x, &out) != EIDSP_OK) + assert(0); + float mean = out.get_row_ptr(0)[0]; + + calculate_entropy(y, features); + calculate_crossings(y, features, mean); + calculate_statistics(y, features, mean); + } + + static void + wavedec_features(const float *x, int len, const char *wav, int level, fvec &features) + { + assert(level > 0 && level < 8); + + fvec h; + fvec g; + find_filter(wav, h, g); + + features.clear(); + fvec a; + fvec d; + dwt(x, len, h.data(), g.data(), h.size(), a, d); + extract_features(d, features); + + for (int l = 1; l < level; l++) { + dwt(a.data(), a.size(), h.data(), g.data(), h.size(), a, d); + extract_features(d, features); + } + + extract_features(a, features); + + for (int l = 0; l <= level / 2; l++) { // reverse order to match python results. + for (int i = 0; i < (int)NUM_FEATHERS_PER_COMP; i++) { + std::swap( + features[l * NUM_FEATHERS_PER_COMP + i], + features[(level - l) * NUM_FEATHERS_PER_COMP + i]); + } + } + } + + static int dwt_features(const float *x, int len, const char *wav, int level, fvec &features) + { + assert(level <= 7); + + assert(features.size() == 0); // make sure features is empty + features.reserve((level + 1) * NUM_FEATHERS_PER_COMP); + + wavedec_features(x, len, wav, level, features); + + return features.size(); + } + + static bool check_min_size(int len, int level) + { + int min_size = 32 * (1 << level); + return (len >= min_size); + } + +public: + static int extract_wavelet_features( + matrix_t *input_matrix, + matrix_t *output_matrix, + ei_dsp_config_spectral_analysis_t *config, + const float sampling_freq) + { + // transpose the matrix so we have one row per axis + numpy::transpose_in_place(input_matrix); + + // func tests for scale of 1 and does a no op in that case + EI_TRY(numpy::scale(input_matrix, config->scale_axes)); + + // apply filter, if enabled + // "zero" order filter allowed. will still remove unwanted fft bins later + if (strcmp(config->filter_type, "low") == 0) { + if (config->filter_order) { + EI_TRY(spectral::processing::butterworth_lowpass_filter( + input_matrix, + sampling_freq, + config->filter_cutoff, + config->filter_order)); + } + } + else if (strcmp(config->filter_type, "high") == 0) { + if (config->filter_order) { + EI_TRY(spectral::processing::butterworth_highpass_filter( + input_matrix, + sampling_freq, + config->filter_cutoff, + config->filter_order)); + } + } + + EI_TRY(processing::subtract_mean(input_matrix)); + + int out_idx = 0; + for (size_t row = 0; row < input_matrix->rows; row++) { + float *data_window = input_matrix->get_row_ptr(row); + size_t data_size = input_matrix->cols; + + if (!check_min_size(data_size, config->wavelet_level)) + EIDSP_ERR(EIDSP_BUFFER_SIZE_MISMATCH); + + fvec features; + size_t num_features = dwt_features( + data_window, + data_size, + config->wavelet, + config->wavelet_level, + features); + + assert(num_features == output_matrix->cols / input_matrix->rows); + for (size_t i = 0; i < num_features; i++) { + output_matrix->buffer[out_idx++] = features[i]; + } + } + return EIDSP_OK; + } +}; + +} +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/wavelet_coeff.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/wavelet_coeff.hpp new file mode 100644 index 0000000..63616fc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/spectral/wavelet_coeff.hpp @@ -0,0 +1,282 @@ +/* Edge Impulse inferencing library + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +#include + +namespace ei{ +namespace spectral{ +//generated by autotune.export + +static const std::array, 2> bior1p3 = {{ + {{-0.08838834764831845, 0.08838834764831845, 0.7071067811865476, 0.7071067811865476, 0.08838834764831845, -0.08838834764831845}}, + {{-0.0, 0.0, -0.7071067811865476, 0.7071067811865476, -0.0, 0.0}} +}}; + +static const std::array, 2> bior1p5 = {{ + {{0.016572815184059706, -0.016572815184059706, -0.12153397801643785, 0.12153397801643785, 0.7071067811865476, 0.7071067811865476, 0.12153397801643785, -0.12153397801643785, -0.016572815184059706, 0.016572815184059706}}, + {{-0.0, 0.0, -0.0, 0.0, -0.7071067811865476, 0.7071067811865476, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> bior2p2 = {{ + {{0.0, -0.1767766952966369, 0.3535533905932738, 1.0606601717798212, 0.3535533905932738, -0.1767766952966369}}, + {{-0.0, 0.3535533905932738, -0.7071067811865476, 0.3535533905932738, -0.0, 0.0}} +}}; + +static const std::array, 2> bior2p4 = {{ + {{0.0, 0.03314563036811941, -0.06629126073623882, -0.1767766952966369, 0.4198446513295126, 0.9943689110435825, 0.4198446513295126, -0.1767766952966369, -0.06629126073623882, 0.03314563036811941}}, + {{-0.0, 0.0, -0.0, 0.3535533905932738, -0.7071067811865476, 0.3535533905932738, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> bior2p6 = {{ + {{0.0, -0.006905339660024878, 0.013810679320049757, 0.04695630968816917, -0.1077232986963881, -0.16987135563661201, 0.4474660099696121, 0.966747552403483, 0.4474660099696121, -0.16987135563661201, -0.1077232986963881, 0.04695630968816917, 0.013810679320049757, -0.006905339660024878}}, + {{-0.0, 0.0, -0.0, 0.0, -0.0, 0.3535533905932738, -0.7071067811865476, 0.3535533905932738, -0.0, 0.0, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> bior2p8 = {{ + {{0.0, 0.0015105430506304422, -0.0030210861012608843, -0.012947511862546647, 0.02891610982635418, 0.05299848189069094, -0.13491307360773605, -0.16382918343409023, 0.46257144047591653, 0.9516421218971786, 0.46257144047591653, -0.16382918343409023, -0.13491307360773605, 0.05299848189069094, 0.02891610982635418, -0.012947511862546647, -0.0030210861012608843, 0.0015105430506304422}}, + {{-0.0, 0.0, -0.0, 0.0, -0.0, 0.0, -0.0, 0.3535533905932738, -0.7071067811865476, 0.3535533905932738, -0.0, 0.0, -0.0, 0.0, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> bior3p1 = {{ + {{-0.3535533905932738, 1.0606601717798212, 1.0606601717798212, -0.3535533905932738}}, + {{-0.1767766952966369, 0.5303300858899106, -0.5303300858899106, 0.1767766952966369}} +}}; + +static const std::array, 2> bior3p3 = {{ + {{0.06629126073623882, -0.1988737822087165, -0.15467960838455727, 0.9943689110435825, 0.9943689110435825, -0.15467960838455727, -0.1988737822087165, 0.06629126073623882}}, + {{-0.0, 0.0, -0.1767766952966369, 0.5303300858899106, -0.5303300858899106, 0.1767766952966369, -0.0, 0.0}} +}}; + +static const std::array, 2> bior3p5 = {{ + {{-0.013810679320049757, 0.04143203796014927, 0.052480581416189075, -0.26792717880896527, -0.07181553246425873, 0.966747552403483, 0.966747552403483, -0.07181553246425873, -0.26792717880896527, 0.052480581416189075, 0.04143203796014927, -0.013810679320049757}}, + {{-0.0, 0.0, -0.0, 0.0, -0.1767766952966369, 0.5303300858899106, -0.5303300858899106, 0.1767766952966369, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> bior3p7 = {{ + {{0.0030210861012608843, -0.009063258303782653, -0.01683176542131064, 0.074663985074019, 0.03133297870736289, -0.301159125922835, -0.02649924094534547, 0.9516421218971786, 0.9516421218971786, -0.02649924094534547, -0.301159125922835, 0.03133297870736289, 0.074663985074019, -0.01683176542131064, -0.009063258303782653, 0.0030210861012608843}}, + {{-0.0, 0.0, -0.0, 0.0, -0.0, 0.0, -0.1767766952966369, 0.5303300858899106, -0.5303300858899106, 0.1767766952966369, -0.0, 0.0, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> bior3p9 = {{ + {{-0.0006797443727836989, 0.002039233118351097, 0.005060319219611981, -0.020618912641105536, -0.014112787930175844, 0.09913478249423216, 0.012300136269419315, -0.32019196836077857, 0.0020500227115698858, 0.9421257006782068, 0.9421257006782068, 0.0020500227115698858, -0.32019196836077857, 0.012300136269419315, 0.09913478249423216, -0.014112787930175844, -0.020618912641105536, 0.005060319219611981, 0.002039233118351097, -0.0006797443727836989}}, + {{-0.0, 0.0, -0.0, 0.0, -0.0, 0.0, -0.0, 0.0, -0.1767766952966369, 0.5303300858899106, -0.5303300858899106, 0.1767766952966369, -0.0, 0.0, -0.0, 0.0, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> bior4p4 = {{ + {{0.0, 0.03782845550726404, -0.023849465019556843, -0.11062440441843718, 0.37740285561283066, 0.8526986790088938, 0.37740285561283066, -0.11062440441843718, -0.023849465019556843, 0.03782845550726404}}, + {{-0.0, -0.06453888262869706, 0.04068941760916406, 0.41809227322161724, -0.7884856164055829, 0.41809227322161724, 0.04068941760916406, -0.06453888262869706, -0.0, 0.0}} +}}; + +static const std::array, 2> bior5p5 = {{ + {{0.0, 0.0, 0.03968708834740544, 0.007948108637240322, -0.05446378846823691, 0.34560528195603346, 0.7366601814282105, 0.34560528195603346, -0.05446378846823691, 0.007948108637240322, 0.03968708834740544, 0.0}}, + {{-0.013456709459118716, -0.002694966880111507, 0.13670658466432914, -0.09350469740093886, -0.47680326579848425, 0.8995061097486484, -0.47680326579848425, -0.09350469740093886, 0.13670658466432914, -0.002694966880111507, -0.013456709459118716, 0.0}} +}}; + +static const std::array, 2> bior6p8 = {{ + {{0.0, 0.0019088317364812906, -0.0019142861290887667, -0.016990639867602342, 0.01193456527972926, 0.04973290349094079, -0.07726317316720414, -0.09405920349573646, 0.4207962846098268, 0.8259229974584023, 0.4207962846098268, -0.09405920349573646, -0.07726317316720414, 0.04973290349094079, 0.01193456527972926, -0.016990639867602342, -0.0019142861290887667, 0.0019088317364812906}}, + {{-0.0, 0.0, -0.0, 0.014426282505624435, -0.014467504896790148, -0.07872200106262882, 0.04036797903033992, 0.41784910915027457, -0.7589077294536541, 0.41784910915027457, 0.04036797903033992, -0.07872200106262882, -0.014467504896790148, 0.014426282505624435, -0.0, 0.0, -0.0, 0.0}} +}}; + +static const std::array, 2> coif1 = {{ + {{-0.015655728135791993, -0.07273261951252645, 0.3848648468648578, 0.8525720202116004, 0.3378976624574818, -0.07273261951252645}}, + {{0.07273261951252645, 0.3378976624574818, -0.8525720202116004, 0.3848648468648578, 0.07273261951252645, -0.015655728135791993}} +}}; + +static const std::array, 2> coif2 = {{ + {{-0.000720549445520347, -0.0018232088709110323, 0.005611434819368834, 0.02368017194684777, -0.05943441864643109, -0.07648859907828076, 0.4170051844232391, 0.8127236354494135, 0.3861100668227629, -0.0673725547237256, -0.04146493678687178, 0.01638733646320364}}, + {{-0.01638733646320364, -0.04146493678687178, 0.0673725547237256, 0.3861100668227629, -0.8127236354494135, 0.4170051844232391, 0.07648859907828076, -0.05943441864643109, -0.02368017194684777, 0.005611434819368834, 0.0018232088709110323, -0.000720549445520347}} +}}; + +static const std::array, 2> coif3 = {{ + {{-3.459977319727278e-05, -7.0983302506379e-05, 0.0004662169598204029, 0.0011175187708306303, -0.0025745176881367972, -0.009007976136730624, 0.015880544863669452, 0.03455502757329774, -0.08230192710629983, -0.07179982161915484, 0.42848347637737, 0.7937772226260872, 0.40517690240911824, -0.06112339000297255, -0.06577191128146936, 0.023452696142077168, 0.007782596425672746, -0.003793512864380802}}, + {{0.003793512864380802, 0.007782596425672746, -0.023452696142077168, -0.06577191128146936, 0.06112339000297255, 0.40517690240911824, -0.7937772226260872, 0.42848347637737, 0.07179982161915484, -0.08230192710629983, -0.03455502757329774, 0.015880544863669452, 0.009007976136730624, -0.0025745176881367972, -0.0011175187708306303, 0.0004662169598204029, 7.0983302506379e-05, -3.459977319727278e-05}} +}}; + +static const std::array, 2> db2 = {{ + {{-0.12940952255126037, 0.2241438680420134, 0.8365163037378079, 0.48296291314453416}}, + {{-0.48296291314453416, 0.8365163037378079, -0.2241438680420134, -0.12940952255126037}} +}}; + +static const std::array, 2> db3 = {{ + {{0.03522629188570953, -0.08544127388202666, -0.13501102001025458, 0.45987750211849154, 0.8068915093110925, 0.33267055295008263}}, + {{-0.33267055295008263, 0.8068915093110925, -0.45987750211849154, -0.13501102001025458, 0.08544127388202666, 0.03522629188570953}} +}}; + +static const std::array, 2> db4 = {{ + {{-0.010597401785069032, 0.0328830116668852, 0.030841381835560764, -0.18703481171909309, -0.027983769416859854, 0.6308807679298589, 0.7148465705529157, 0.2303778133088965}}, + {{-0.2303778133088965, 0.7148465705529157, -0.6308807679298589, -0.027983769416859854, 0.18703481171909309, 0.030841381835560764, -0.0328830116668852, -0.010597401785069032}} +}}; + +static const std::array, 2> db5 = {{ + {{0.0033357252854737712, -0.012580751999081999, -0.006241490212798274, 0.07757149384004572, -0.032244869584638375, -0.24229488706638203, 0.13842814590132074, 0.7243085284377729, 0.6038292697971896, 0.16010239797419293}}, + {{-0.16010239797419293, 0.6038292697971896, -0.7243085284377729, 0.13842814590132074, 0.24229488706638203, -0.032244869584638375, -0.07757149384004572, -0.006241490212798274, 0.012580751999081999, 0.0033357252854737712}} +}}; + +static const std::array, 2> db6 = {{ + {{-0.0010773010853084796, 0.004777257510945511, 0.0005538422011614961, -0.03158203931748603, 0.027522865530305727, 0.09750160558732304, -0.12976686756726194, -0.22626469396543983, 0.31525035170919763, 0.7511339080210954, 0.49462389039845306, 0.11154074335010947}}, + {{-0.11154074335010947, 0.49462389039845306, -0.7511339080210954, 0.31525035170919763, 0.22626469396543983, -0.12976686756726194, -0.09750160558732304, 0.027522865530305727, 0.03158203931748603, 0.0005538422011614961, -0.004777257510945511, -0.0010773010853084796}} +}}; + +static const std::array, 2> db7 = {{ + {{0.00035371379997452024, -0.0018016407040474908, 0.0004295779729213665, 0.01255099855609984, -0.01657454163066688, -0.03802993693501441, 0.08061260915108308, 0.07130921926683026, -0.22403618499387498, -0.14390600392856498, 0.4697822874051931, 0.7291320908462351, 0.3965393194819173, 0.07785205408500918}}, + {{-0.07785205408500918, 0.3965393194819173, -0.7291320908462351, 0.4697822874051931, 0.14390600392856498, -0.22403618499387498, -0.07130921926683026, 0.08061260915108308, 0.03802993693501441, -0.01657454163066688, -0.01255099855609984, 0.0004295779729213665, 0.0018016407040474908, 0.00035371379997452024}} +}}; + +static const std::array, 2> db8 = {{ + {{-0.00011747678412476953, 0.0006754494064505693, -0.00039174037337694705, -0.004870352993451574, 0.008746094047405777, 0.013981027917398282, -0.044088253930794755, -0.017369301001807547, 0.12874742662047847, 0.0004724845739132828, -0.2840155429615469, -0.015829105256349306, 0.5853546836542067, 0.6756307362972898, 0.31287159091429995, 0.05441584224310401}}, + {{-0.05441584224310401, 0.31287159091429995, -0.6756307362972898, 0.5853546836542067, 0.015829105256349306, -0.2840155429615469, -0.0004724845739132828, 0.12874742662047847, 0.017369301001807547, -0.044088253930794755, -0.013981027917398282, 0.008746094047405777, 0.004870352993451574, -0.00039174037337694705, -0.0006754494064505693, -0.00011747678412476953}} +}}; + +static const std::array, 2> db9 = {{ + {{3.93473203162716e-05, -0.0002519631889427101, 0.00023038576352319597, 0.0018476468830562265, -0.00428150368246343, -0.004723204757751397, 0.022361662123679096, 0.00025094711483145197, -0.06763282906132997, 0.03072568147933338, 0.14854074933810638, -0.09684078322297646, -0.2932737832791749, 0.13319738582500756, 0.6572880780513005, 0.6048231236901112, 0.24383467461259034, 0.038077947363878345}}, + {{-0.038077947363878345, 0.24383467461259034, -0.6048231236901112, 0.6572880780513005, -0.13319738582500756, -0.2932737832791749, 0.09684078322297646, 0.14854074933810638, -0.03072568147933338, -0.06763282906132997, -0.00025094711483145197, 0.022361662123679096, 0.004723204757751397, -0.00428150368246343, -0.0018476468830562265, 0.00023038576352319597, 0.0002519631889427101, 3.93473203162716e-05}} +}}; + +static const std::array, 2> db10 = {{ + {{-1.3264202894521244e-05, 9.358867032006959e-05, -0.00011646685512928545, -0.0006858566949597116, 0.001992405295185056, 0.001395351747052901, -0.010733175483330575, 0.0036065535669561697, 0.033212674059341, -0.029457536821875813, -0.07139414716639708, 0.09305736460357235, 0.12736934033579325, -0.19594627437737705, -0.24984642432731538, 0.2811723436605775, 0.6884590394536035, 0.5272011889317256, 0.1881768000776915, 0.026670057900555554}}, + {{-0.026670057900555554, 0.1881768000776915, -0.5272011889317256, 0.6884590394536035, -0.2811723436605775, -0.24984642432731538, 0.19594627437737705, 0.12736934033579325, -0.09305736460357235, -0.07139414716639708, 0.029457536821875813, 0.033212674059341, -0.0036065535669561697, -0.010733175483330575, -0.001395351747052901, 0.001992405295185056, 0.0006858566949597116, -0.00011646685512928545, -9.358867032006959e-05, -1.3264202894521244e-05}} +}}; + +static const std::array, 2> haar = {{ + {{0.7071067811865476, 0.7071067811865476}}, + {{-0.7071067811865476, 0.7071067811865476}} +}}; + +static const std::array, 2> rbio1p3 = {{ + {{0.0, 0.0, 0.7071067811865476, 0.7071067811865476, 0.0, 0.0}}, + {{0.08838834764831845, 0.08838834764831845, -0.7071067811865476, 0.7071067811865476, -0.08838834764831845, -0.08838834764831845}} +}}; + +static const std::array, 2> rbio1p5 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.7071067811865476, 0.7071067811865476, 0.0, 0.0, 0.0, 0.0}}, + {{-0.016572815184059706, -0.016572815184059706, 0.12153397801643785, 0.12153397801643785, -0.7071067811865476, 0.7071067811865476, -0.12153397801643785, -0.12153397801643785, 0.016572815184059706, 0.016572815184059706}} +}}; + +static const std::array, 2> rbio2p2 = {{ + {{0.0, 0.0, 0.3535533905932738, 0.7071067811865476, 0.3535533905932738, 0.0}}, + {{0.1767766952966369, 0.3535533905932738, -1.0606601717798212, 0.3535533905932738, 0.1767766952966369, 0.0}} +}}; + +static const std::array, 2> rbio2p4 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.3535533905932738, 0.7071067811865476, 0.3535533905932738, 0.0, 0.0, 0.0}}, + {{-0.03314563036811941, -0.06629126073623882, 0.1767766952966369, 0.4198446513295126, -0.9943689110435825, 0.4198446513295126, 0.1767766952966369, -0.06629126073623882, -0.03314563036811941, 0.0}} +}}; + +static const std::array, 2> rbio2p6 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.3535533905932738, 0.7071067811865476, 0.3535533905932738, 0.0, 0.0, 0.0, 0.0, 0.0}}, + {{0.006905339660024878, 0.013810679320049757, -0.04695630968816917, -0.1077232986963881, 0.16987135563661201, 0.4474660099696121, -0.966747552403483, 0.4474660099696121, 0.16987135563661201, -0.1077232986963881, -0.04695630968816917, 0.013810679320049757, 0.006905339660024878, 0.0}} +}}; + +static const std::array, 2> rbio2p8 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.3535533905932738, 0.7071067811865476, 0.3535533905932738, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0}}, + {{-0.0015105430506304422, -0.0030210861012608843, 0.012947511862546647, 0.02891610982635418, -0.05299848189069094, -0.13491307360773605, 0.16382918343409023, 0.46257144047591653, -0.9516421218971786, 0.46257144047591653, 0.16382918343409023, -0.13491307360773605, -0.05299848189069094, 0.02891610982635418, 0.012947511862546647, -0.0030210861012608843, -0.0015105430506304422, 0.0}} +}}; + +static const std::array, 2> rbio3p1 = {{ + {{0.1767766952966369, 0.5303300858899106, 0.5303300858899106, 0.1767766952966369}}, + {{0.3535533905932738, 1.0606601717798212, -1.0606601717798212, -0.3535533905932738}} +}}; + +static const std::array, 2> rbio3p3 = {{ + {{0.0, 0.0, 0.1767766952966369, 0.5303300858899106, 0.5303300858899106, 0.1767766952966369, 0.0, 0.0}}, + {{-0.06629126073623882, -0.1988737822087165, 0.15467960838455727, 0.9943689110435825, -0.9943689110435825, -0.15467960838455727, 0.1988737822087165, 0.06629126073623882}} +}}; + +static const std::array, 2> rbio3p5 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.1767766952966369, 0.5303300858899106, 0.5303300858899106, 0.1767766952966369, 0.0, 0.0, 0.0, 0.0}}, + {{0.013810679320049757, 0.04143203796014927, -0.052480581416189075, -0.26792717880896527, 0.07181553246425873, 0.966747552403483, -0.966747552403483, -0.07181553246425873, 0.26792717880896527, 0.052480581416189075, -0.04143203796014927, -0.013810679320049757}} +}}; + +static const std::array, 2> rbio3p7 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.1767766952966369, 0.5303300858899106, 0.5303300858899106, 0.1767766952966369, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0}}, + {{-0.0030210861012608843, -0.009063258303782653, 0.01683176542131064, 0.074663985074019, -0.03133297870736289, -0.301159125922835, 0.02649924094534547, 0.9516421218971786, -0.9516421218971786, -0.02649924094534547, 0.301159125922835, 0.03133297870736289, -0.074663985074019, -0.01683176542131064, 0.009063258303782653, 0.0030210861012608843}} +}}; + +static const std::array, 2> rbio3p9 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.1767766952966369, 0.5303300858899106, 0.5303300858899106, 0.1767766952966369, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0}}, + {{0.0006797443727836989, 0.002039233118351097, -0.005060319219611981, -0.020618912641105536, 0.014112787930175844, 0.09913478249423216, -0.012300136269419315, -0.32019196836077857, -0.0020500227115698858, 0.9421257006782068, -0.9421257006782068, 0.0020500227115698858, 0.32019196836077857, 0.012300136269419315, -0.09913478249423216, -0.014112787930175844, 0.020618912641105536, 0.005060319219611981, -0.002039233118351097, -0.0006797443727836989}} +}}; + +static const std::array, 2> rbio4p4 = {{ + {{0.0, 0.0, -0.06453888262869706, -0.04068941760916406, 0.41809227322161724, 0.7884856164055829, 0.41809227322161724, -0.04068941760916406, -0.06453888262869706, 0.0}}, + {{-0.03782845550726404, -0.023849465019556843, 0.11062440441843718, 0.37740285561283066, -0.8526986790088938, 0.37740285561283066, 0.11062440441843718, -0.023849465019556843, -0.03782845550726404, 0.0}} +}}; + +static const std::array, 2> rbio5p5 = {{ + {{0.0, 0.013456709459118716, -0.002694966880111507, -0.13670658466432914, -0.09350469740093886, 0.47680326579848425, 0.8995061097486484, 0.47680326579848425, -0.09350469740093886, -0.13670658466432914, -0.002694966880111507, 0.013456709459118716}}, + {{-0.0, 0.03968708834740544, -0.007948108637240322, -0.05446378846823691, -0.34560528195603346, 0.7366601814282105, -0.34560528195603346, -0.05446378846823691, -0.007948108637240322, 0.03968708834740544, -0.0, 0.0}} +}}; + +static const std::array, 2> rbio6p8 = {{ + {{0.0, 0.0, 0.0, 0.0, 0.014426282505624435, 0.014467504896790148, -0.07872200106262882, -0.04036797903033992, 0.41784910915027457, 0.7589077294536541, 0.41784910915027457, -0.04036797903033992, -0.07872200106262882, 0.014467504896790148, 0.014426282505624435, 0.0, 0.0, 0.0}}, + {{-0.0019088317364812906, -0.0019142861290887667, 0.016990639867602342, 0.01193456527972926, -0.04973290349094079, -0.07726317316720414, 0.09405920349573646, 0.4207962846098268, -0.8259229974584023, 0.4207962846098268, 0.09405920349573646, -0.07726317316720414, -0.04973290349094079, 0.01193456527972926, 0.016990639867602342, -0.0019142861290887667, -0.0019088317364812906, 0.0}} +}}; + +static const std::array, 2> sym2 = {{ + {{-0.12940952255092145, 0.22414386804185735, 0.836516303737469, 0.48296291314469025}}, + {{-0.48296291314469025, 0.836516303737469, -0.22414386804185735, -0.12940952255092145}} +}}; + +static const std::array, 2> sym3 = {{ + {{0.035226291882100656, -0.08544127388224149, -0.13501102001039084, 0.4598775021193313, 0.8068915093133388, 0.3326705529509569}}, + {{-0.3326705529509569, 0.8068915093133388, -0.4598775021193313, -0.13501102001039084, 0.08544127388224149, 0.035226291882100656}} +}}; + +static const std::array, 2> sym4 = {{ + {{-0.07576571478927333, -0.02963552764599851, 0.49761866763201545, 0.8037387518059161, 0.29785779560527736, -0.09921954357684722, -0.012603967262037833, 0.0322231006040427}}, + {{-0.0322231006040427, -0.012603967262037833, 0.09921954357684722, 0.29785779560527736, -0.8037387518059161, 0.49761866763201545, 0.02963552764599851, -0.07576571478927333}} +}}; + +static const std::array, 2> sym5 = {{ + {{0.027333068345077982, 0.029519490925774643, -0.039134249302383094, 0.1993975339773936, 0.7234076904024206, 0.6339789634582119, 0.01660210576452232, -0.17532808990845047, -0.021101834024758855, 0.019538882735286728}}, + {{-0.019538882735286728, -0.021101834024758855, 0.17532808990845047, 0.01660210576452232, -0.6339789634582119, 0.7234076904024206, -0.1993975339773936, -0.039134249302383094, -0.029519490925774643, 0.027333068345077982}} +}}; + +static const std::array, 2> sym6 = {{ + {{0.015404109327027373, 0.0034907120842174702, -0.11799011114819057, -0.048311742585633, 0.4910559419267466, 0.787641141030194, 0.3379294217276218, -0.07263752278646252, -0.021060292512300564, 0.04472490177066578, 0.0017677118642428036, -0.007800708325034148}}, + {{0.007800708325034148, 0.0017677118642428036, -0.04472490177066578, -0.021060292512300564, 0.07263752278646252, 0.3379294217276218, -0.787641141030194, 0.4910559419267466, 0.048311742585633, -0.11799011114819057, -0.0034907120842174702, 0.015404109327027373}} +}}; + +static const std::array, 2> sym7 = {{ + {{0.002681814568257878, -0.0010473848886829163, -0.01263630340325193, 0.03051551316596357, 0.0678926935013727, -0.049552834937127255, 0.017441255086855827, 0.5361019170917628, 0.767764317003164, 0.2886296317515146, -0.14004724044296152, -0.10780823770381774, 0.004010244871533663, 0.010268176708511255}}, + {{-0.010268176708511255, 0.004010244871533663, 0.10780823770381774, -0.14004724044296152, -0.2886296317515146, 0.767764317003164, -0.5361019170917628, 0.017441255086855827, 0.049552834937127255, 0.0678926935013727, -0.03051551316596357, -0.01263630340325193, 0.0010473848886829163, 0.002681814568257878}} +}}; + +static const std::array, 2> sym8 = {{ + {{-0.0033824159510061256, -0.0005421323317911481, 0.03169508781149298, 0.007607487324917605, -0.1432942383508097, -0.061273359067658524, 0.4813596512583722, 0.7771857517005235, 0.3644418948353314, -0.05194583810770904, -0.027219029917056003, 0.049137179673607506, 0.003808752013890615, -0.01495225833704823, -0.0003029205147213668, 0.0018899503327594609}}, + {{-0.0018899503327594609, -0.0003029205147213668, 0.01495225833704823, 0.003808752013890615, -0.049137179673607506, -0.027219029917056003, 0.05194583810770904, 0.3644418948353314, -0.7771857517005235, 0.4813596512583722, 0.061273359067658524, -0.1432942383508097, -0.007607487324917605, 0.03169508781149298, 0.0005421323317911481, -0.0033824159510061256}} +}}; + +static const std::array, 2> sym9 = {{ + {{0.0014009155259146807, 0.0006197808889855868, -0.013271967781817119, -0.01152821020767923, 0.03022487885827568, 0.0005834627461258068, -0.05456895843083407, 0.238760914607303, 0.717897082764412, 0.6173384491409358, 0.035272488035271894, -0.19155083129728512, -0.018233770779395985, 0.06207778930288603, 0.008859267493400484, -0.010264064027633142, -0.0004731544986800831, 0.0010694900329086053}}, + {{-0.0010694900329086053, -0.0004731544986800831, 0.010264064027633142, 0.008859267493400484, -0.06207778930288603, -0.018233770779395985, 0.19155083129728512, 0.035272488035271894, -0.6173384491409358, 0.717897082764412, -0.238760914607303, -0.05456895843083407, -0.0005834627461258068, 0.03022487885827568, 0.01152821020767923, -0.013271967781817119, -0.0006197808889855868, 0.0014009155259146807}} +}}; + +static const std::array, 2> sym10 = {{ + {{0.0007701598091144901, 9.563267072289475e-05, -0.008641299277022422, -0.0014653825813050513, 0.0459272392310922, 0.011609893903711381, -0.15949427888491757, -0.07088053578324385, 0.47169066693843925, 0.7695100370211071, 0.38382676106708546, -0.03553674047381755, -0.0319900568824278, 0.04999497207737669, 0.005764912033581909, -0.02035493981231129, -0.0008043589320165449, 0.004593173585311828, 5.7036083618494284e-05, -0.0004593294210046588}}, + {{0.0004593294210046588, 5.7036083618494284e-05, -0.004593173585311828, -0.0008043589320165449, 0.02035493981231129, 0.005764912033581909, -0.04999497207737669, -0.0319900568824278, 0.03553674047381755, 0.38382676106708546, -0.7695100370211071, 0.47169066693843925, 0.07088053578324385, -0.15949427888491757, -0.011609893903711381, 0.0459272392310922, 0.0014653825813050513, -0.008641299277022422, -9.563267072289475e-05, 0.0007701598091144901}} +}}; + +} +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/feature.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/feature.hpp new file mode 100644 index 0000000..89765b2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/feature.hpp @@ -0,0 +1,807 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPEECHPY_FEATURE_H_ +#define _EIDSP_SPEECHPY_FEATURE_H_ + +#include +#include "../../porting/ei_classifier_porting.h" +#include "../ei_utils.h" +#include "functions.hpp" +#include "processing.hpp" +#include "../memory.hpp" +#include "../returntypes.hpp" +#include "../ei_vector.h" + +namespace ei { +namespace speechpy { + +class feature { +public: + /** + * Compute the Mel-filterbanks. Each filter will be stored in one rows. + * The columns correspond to fft bins. + * + * @param filterbanks Matrix of size num_filter * coefficients + * @param num_filter the number of filters in the filterbank + * @param coefficients (fftpoints//2 + 1) + * @param sampling_freq the samplerate of the signal we are working + * with. It affects mel spacing. + * @param low_freq lowest band edge of mel filters, default 0 Hz + * @param high_freq highest band edge of mel filters, default samplerate / 2 + * @param output_transposed If set to true this will transpose the matrix (memory efficient). + * This is more efficient than calling this function and then transposing + * as the latter requires the filterbank to be allocated twice (for a short while). + * @returns EIDSP_OK if OK + */ + static int filterbanks( +#if EIDSP_QUANTIZE_FILTERBANK + quantized_matrix_t *filterbanks, +#else + matrix_t *filterbanks, +#endif + uint16_t num_filter, int coefficients, uint32_t sampling_freq, + uint32_t low_freq, uint32_t high_freq, + bool output_transposed = false + ) + { + const size_t mels_mem_size = (num_filter + 2) * sizeof(float); + const size_t hertz_mem_size = (num_filter + 2) * sizeof(float); + const size_t freq_index_mem_size = (num_filter + 2) * sizeof(int); + + float *mels = (float*)ei_dsp_malloc(mels_mem_size); + if (!mels) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + if (filterbanks->rows != num_filter || filterbanks->cols != static_cast(coefficients)) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + +#if EIDSP_QUANTIZE_FILTERBANK + memset(filterbanks->buffer, 0, filterbanks->rows * filterbanks->cols * sizeof(uint8_t)); +#else + memset(filterbanks->buffer, 0, filterbanks->rows * filterbanks->cols * sizeof(float)); +#endif + + // Computing the Mel filterbank + // converting the upper and lower frequencies to Mels. + // num_filter + 2 is because for num_filter filterbanks we need + // num_filter+2 point. + numpy::linspace( + functions::frequency_to_mel(static_cast(low_freq)), + functions::frequency_to_mel(static_cast(high_freq)), + num_filter + 2, + mels); + + // we should convert Mels back to Hertz because the start and end-points + // should be at the desired frequencies. + float *hertz = (float*)ei_dsp_malloc(hertz_mem_size); + if (!hertz) { + ei_dsp_free(mels, mels_mem_size); + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + for (uint16_t ix = 0; ix < num_filter + 2; ix++) { + hertz[ix] = functions::mel_to_frequency(mels[ix]); + if (hertz[ix] < low_freq) { + hertz[ix] = low_freq; + } + if (hertz[ix] > high_freq) { + hertz[ix] = high_freq; + } + + // here is a really annoying bug in Speechpy which calculates the frequency index wrong for the last bucket + // the last 'hertz' value is not 8,000 (with sampling rate 16,000) but 7,999.999999 + // thus calculating the bucket to 64, not 65. + // we're adjusting this here a tiny bit to ensure we have the same result + if (ix == num_filter + 2 - 1) { + hertz[ix] -= 0.001; + } + } + ei_dsp_free(mels, mels_mem_size); + + // The frequency resolution required to put filters at the + // exact points calculated above should be extracted. + // So we should round those frequencies to the closest FFT bin. + int *freq_index = (int*)ei_dsp_malloc(freq_index_mem_size); + if (!freq_index) { + ei_dsp_free(hertz, hertz_mem_size); + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + for (uint16_t ix = 0; ix < num_filter + 2; ix++) { + freq_index[ix] = static_cast(floor((coefficients + 1) * hertz[ix] / sampling_freq)); + } + ei_dsp_free(hertz, hertz_mem_size); + + for (size_t i = 0; i < num_filter; i++) { + int left = freq_index[i]; + int middle = freq_index[i + 1]; + int right = freq_index[i + 2]; + + EI_DSP_MATRIX(z, 1, (right - left + 1)); + if (!z.buffer) { + ei_dsp_free(freq_index, freq_index_mem_size); + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + numpy::linspace(left, right, (right - left + 1), z.buffer); + functions::triangle(z.buffer, (right - left + 1), left, middle, right); + + // so... z now contains some values that we need to overwrite in the filterbank + for (int zx = 0; zx < (right - left + 1); zx++) { + size_t index = (i * filterbanks->cols) + (left + zx); + + if (output_transposed) { + index = ((left + zx) * filterbanks->rows) + i; + } + +#if EIDSP_QUANTIZE_FILTERBANK + filterbanks->buffer[index] = numpy::quantize_zero_one(z.buffer[zx]); +#else + filterbanks->buffer[index] = z.buffer[zx]; +#endif + } + } + + if (output_transposed) { + uint16_t r = filterbanks->rows; + filterbanks->rows = filterbanks->cols; + filterbanks->cols = r; + } + + ei_dsp_free(freq_index, freq_index_mem_size); + + return EIDSP_OK; + } + + /** + * @brief Get the fft bin index from hertz + * + * @param fft_size Size of fft + * @param hertz Desired hertz + * @param sampling_freq In Hz + * @return int the index of the bin closest to the hertz + */ + static int get_fft_bin_from_hertz(uint16_t fft_size, float hertz, uint32_t sampling_freq) + { + return static_cast(floor((fft_size + 1) * hertz / sampling_freq)); + } + + /** + * Compute Mel-filterbank energy features from an audio signal. + * @param out_features Use `calculate_mfe_buffer_size` to allocate the right matrix. + * @param out_energies A matrix in the form of Mx1 where M is the rows from `calculate_mfe_buffer_size` + * @param signal: audio signal structure with functions to retrieve data from a signal + * @param sampling_frequency (int): the sampling frequency of the signal + * we are working with. + * @param frame_length (float): the length of each frame in seconds. + * Default is 0.020s + * @param frame_stride (float): the step between successive frames in seconds. + * Default is 0.02s (means no overlap) + * @param num_filters (int): the number of filters in the filterbank, + * default 40. + * @param fft_length (int): number of FFT points. Default is 512. + * @param low_frequency (int): lowest band edge of mel filters. + * In Hz, default is 0. + * @param high_frequency (int): highest band edge of mel filters. + * In Hz, default is samplerate/2 + * @EIDSP_OK if OK + */ + static int mfe(matrix_t *out_features, matrix_t *out_energies, + signal_t *signal, + uint32_t sampling_frequency, + float frame_length, float frame_stride, uint16_t num_filters, + uint16_t fft_length, uint32_t low_frequency, uint32_t high_frequency, + uint16_t version + ) + { + int ret = 0; + + if (high_frequency == 0) { + high_frequency = sampling_frequency / 2; + } + + if (version<4) { + if (low_frequency == 0) { + low_frequency = 300; + } + } + + stack_frames_info_t stack_frame_info = { 0 }; + stack_frame_info.signal = signal; + + ret = processing::stack_frames( + &stack_frame_info, + sampling_frequency, + frame_length, + frame_stride, + false, + version + ); + if (ret != 0) { + EIDSP_ERR(ret); + } + + if (stack_frame_info.frame_ixs.size() != out_features->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (num_filters != out_features->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (out_energies) { + if (stack_frame_info.frame_ixs.size() != out_energies->rows || out_energies->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + } + + for (uint32_t i = 0; i < out_features->rows * out_features->cols; i++) { + *(out_features->buffer + i) = 0; + } + + const size_t power_spectrum_frame_size = (fft_length / 2 + 1); + // Computing the Mel filterbank + // converting the upper and lower frequencies to Mels. + // num_filter + 2 is because for num_filter filterbanks we need + // num_filter+2 point. + float *mels; + const int MELS_SIZE = num_filters + 2; + mels = (float*)ei_calloc(MELS_SIZE, sizeof(float)); + EI_ERR_AND_RETURN_ON_NULL(mels, EIDSP_OUT_OF_MEM); + ei_unique_ptr_t __ptr__(mels,ei_free); + uint16_t* bins = reinterpret_cast(mels); // alias the mels array so we can reuse the space + + numpy::linspace( + functions::frequency_to_mel(static_cast(low_frequency)), + functions::frequency_to_mel(static_cast(high_frequency)), + num_filters + 2, + mels); + + uint16_t max_bin = version >= 4 ? fft_length : power_spectrum_frame_size; // preserve a bug in v<4 + // go to -1 size b/c special handling, see after + for (uint16_t ix = 0; ix < MELS_SIZE-1; ix++) { + mels[ix] = functions::mel_to_frequency(mels[ix]); + if (mels[ix] < low_frequency) { + mels[ix] = low_frequency; + } + if (mels[ix] > high_frequency) { + mels[ix] = high_frequency; + } + bins[ix] = get_fft_bin_from_hertz(max_bin, mels[ix], sampling_frequency); + } + + // here is a really annoying bug in Speechpy which calculates the frequency index wrong for the last bucket + // the last 'hertz' value is not 8,000 (with sampling rate 16,000) but 7,999.999999 + // thus calculating the bucket to 64, not 65. + // we're adjusting this here a tiny bit to ensure we have the same result + mels[MELS_SIZE-1] = functions::mel_to_frequency(mels[MELS_SIZE-1]); + if (mels[MELS_SIZE-1] > high_frequency) { + mels[MELS_SIZE-1] = high_frequency; + } + mels[MELS_SIZE-1] -= 0.001; + bins[MELS_SIZE-1] = get_fft_bin_from_hertz(max_bin, mels[MELS_SIZE-1], sampling_frequency); + + EI_DSP_MATRIX(power_spectrum_frame, 1, power_spectrum_frame_size); + if (!power_spectrum_frame.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + // get signal data from the audio file + EI_DSP_MATRIX(signal_frame, 1, stack_frame_info.frame_length); + + for (size_t ix = 0; ix < stack_frame_info.frame_ixs.size(); ix++) { + // don't read outside of the audio buffer... we'll automatically zero pad then + size_t signal_offset = stack_frame_info.frame_ixs.at(ix); + size_t signal_length = stack_frame_info.frame_length; + if (signal_offset + signal_length > stack_frame_info.signal->total_length) { + signal_length = signal_length - + (stack_frame_info.signal->total_length - (signal_offset + signal_length)); + } + + ret = stack_frame_info.signal->get_data( + signal_offset, + signal_length, + signal_frame.buffer + ); + if (ret != 0) { + EIDSP_ERR(ret); + } + + ret = numpy::power_spectrum( + signal_frame.buffer, + stack_frame_info.frame_length, + power_spectrum_frame.buffer, + power_spectrum_frame_size, + fft_length + ); + + if (ret != 0) { + EIDSP_ERR(ret); + } + + float energy = numpy::sum(power_spectrum_frame.buffer, power_spectrum_frame_size); + if (energy == 0) { + energy = 1e-10; + } + + if (out_energies) { + out_energies->buffer[ix] = energy; + } + + auto row_ptr = out_features->get_row_ptr(ix); + for (size_t i = 0; i < num_filters; i++) { + size_t left = bins[i]; + size_t middle = bins[i+1]; + size_t right = bins[i+2]; + + assert(right < power_spectrum_frame_size); + // now we have weights and locations to move from fft to mel sgram + // both left and right become zero weights, so skip them + + // middle always has weight of 1.0 + // since we skip left and right, if left = middle we need to handle that + row_ptr[i] = power_spectrum_frame.buffer[middle]; + + for (size_t bin = left+1; bin < right; bin++) { + if (bin < middle) { + row_ptr[i] += + ((static_cast(bin) - left) / (middle - left)) * // weight * + power_spectrum_frame.buffer[bin]; + } + // intentionally skip middle, handled above + if (bin > middle) { + row_ptr[i] += + ((right - static_cast(bin)) / (right - middle)) * // weight * + power_spectrum_frame.buffer[bin]; + } + } + } + + if (ret != 0) { + EIDSP_ERR(ret); + } + } + + numpy::zero_handling(out_features); + + return EIDSP_OK; + } + + /** + * Compute Mel-filterbank energy features from an audio signal. + * @param out_features Use `calculate_mfe_buffer_size` to allocate the right matrix. + * @param out_energies A matrix in the form of Mx1 where M is the rows from `calculate_mfe_buffer_size` + * @param signal: audio signal structure with functions to retrieve data from a signal + * @param sampling_frequency (int): the sampling frequency of the signal + * we are working with. + * @param frame_length (float): the length of each frame in seconds. + * Default is 0.020s + * @param frame_stride (float): the step between successive frames in seconds. + * Default is 0.02s (means no overlap) + * @param num_filters (int): the number of filters in the filterbank, + * default 40. + * @param fft_length (int): number of FFT points. Default is 512. + * @param low_frequency (int): lowest band edge of mel filters. + * In Hz, default is 0. + * @param high_frequency (int): highest band edge of mel filters. + * In Hz, default is samplerate/2 + * @EIDSP_OK if OK + */ + static int mfe_v3(matrix_t *out_features, matrix_t *out_energies, + signal_t *signal, + uint32_t sampling_frequency, + float frame_length, float frame_stride, uint16_t num_filters, + uint16_t fft_length, uint32_t low_frequency, uint32_t high_frequency, + uint16_t version + ) + { + int ret = 0; + + if (high_frequency == 0) { + high_frequency = sampling_frequency / 2; + } + + if (low_frequency == 0) { + low_frequency = 300; + } + + stack_frames_info_t stack_frame_info = { 0 }; + stack_frame_info.signal = signal; + + ret = processing::stack_frames( + &stack_frame_info, + sampling_frequency, + frame_length, + frame_stride, + false, + version + ); + if (ret != 0) { + EIDSP_ERR(ret); + } + + if (stack_frame_info.frame_ixs.size() != out_features->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (num_filters != out_features->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + if (out_energies) { + if (stack_frame_info.frame_ixs.size() != out_energies->rows || out_energies->cols != 1) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + } + + for (uint32_t i = 0; i < out_features->rows * out_features->cols; i++) { + *(out_features->buffer + i) = 0; + } + + uint16_t coefficients = fft_length / 2 + 1; + + // calculate the filterbanks first... preferably I would want to do the matrix multiplications + // whenever they happen, but OK... +#if EIDSP_QUANTIZE_FILTERBANK + EI_DSP_QUANTIZED_MATRIX(filterbanks, num_filters, coefficients, &numpy::dequantize_zero_one); +#else + EI_DSP_MATRIX(filterbanks, num_filters, coefficients); +#endif + if (!filterbanks.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + ret = feature::filterbanks( + &filterbanks, num_filters, coefficients, sampling_frequency, low_frequency, high_frequency, true); + if (ret != 0) { + EIDSP_ERR(ret); + } + for (size_t ix = 0; ix < stack_frame_info.frame_ixs.size(); ix++) { + size_t power_spectrum_frame_size = (fft_length / 2 + 1); + + EI_DSP_MATRIX(power_spectrum_frame, 1, power_spectrum_frame_size); + if (!power_spectrum_frame.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + // get signal data from the audio file + EI_DSP_MATRIX(signal_frame, 1, stack_frame_info.frame_length); + + // don't read outside of the audio buffer... we'll automatically zero pad then + size_t signal_offset = stack_frame_info.frame_ixs.at(ix); + size_t signal_length = stack_frame_info.frame_length; + if (signal_offset + signal_length > stack_frame_info.signal->total_length) { + signal_length = signal_length - + (stack_frame_info.signal->total_length - (signal_offset + signal_length)); + } + + ret = stack_frame_info.signal->get_data( + signal_offset, + signal_length, + signal_frame.buffer + ); + if (ret != 0) { + EIDSP_ERR(ret); + } + + ret = numpy::power_spectrum( + signal_frame.buffer, + stack_frame_info.frame_length, + power_spectrum_frame.buffer, + power_spectrum_frame_size, + fft_length + ); + + if (ret != 0) { + EIDSP_ERR(ret); + } + + float energy = numpy::sum(power_spectrum_frame.buffer, power_spectrum_frame_size); + if (energy == 0) { + energy = 1e-10; + } + + if (out_energies) { + out_energies->buffer[ix] = energy; + } + + // calculate the out_features directly here + ret = numpy::dot_by_row( + ix, + power_spectrum_frame.buffer, + power_spectrum_frame_size, + &filterbanks, + out_features + ); + + if (ret != 0) { + EIDSP_ERR(ret); + } + } + + numpy::zero_handling(out_features); + + return EIDSP_OK; + } + + /** + * Compute spectrogram from a sensor signal. + * @param out_features Use `calculate_mfe_buffer_size` to allocate the right matrix. + * @param signal: audio signal structure with functions to retrieve data from a signal + * @param sampling_frequency (int): the sampling frequency of the signal + * we are working with. + * @param frame_length (float): the length of each frame in seconds. + * Default is 0.020s + * @param frame_stride (float): the step between successive frames in seconds. + * Default is 0.02s (means no overlap) + * @param fft_length (int): number of FFT points. Default is 512. + * @EIDSP_OK if OK + */ + static int spectrogram(matrix_t *out_features, + signal_t *signal, float sampling_frequency, + float frame_length, float frame_stride, uint16_t fft_length, + uint16_t version + ) + { + int ret = 0; + + stack_frames_info_t stack_frame_info = { 0 }; + stack_frame_info.signal = signal; + + ret = processing::stack_frames( + &stack_frame_info, + sampling_frequency, + frame_length, + frame_stride, + false, + version + ); + if (ret != 0) { + EIDSP_ERR(ret); + } + + if (stack_frame_info.frame_ixs.size() != out_features->rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + uint16_t coefficients = fft_length / 2 + 1; + + if (coefficients != out_features->cols) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + for (uint32_t i = 0; i < out_features->rows * out_features->cols; i++) { + *(out_features->buffer + i) = 0; + } + + for (size_t ix = 0; ix < stack_frame_info.frame_ixs.size(); ix++) { + // get signal data from the audio file + EI_DSP_MATRIX(signal_frame, 1, stack_frame_info.frame_length); + + // don't read outside of the audio buffer... we'll automatically zero pad then + size_t signal_offset = stack_frame_info.frame_ixs.at(ix); + size_t signal_length = stack_frame_info.frame_length; + if (signal_offset + signal_length > stack_frame_info.signal->total_length) { + signal_length = signal_length - + (stack_frame_info.signal->total_length - (signal_offset + signal_length)); + } + + ret = stack_frame_info.signal->get_data( + signal_offset, + signal_length, + signal_frame.buffer + ); + if (ret != 0) { + EIDSP_ERR(ret); + } + + // normalize data (only when version is 3) + if (version == 3) { + // it might be that everything is already normalized here... + bool all_between_min_1_and_1 = true; + for (size_t ix = 0; ix < signal_frame.rows * signal_frame.cols; ix++) { + if (signal_frame.buffer[ix] < -1.0f || signal_frame.buffer[ix] > 1.0f) { + all_between_min_1_and_1 = false; + break; + } + } + + if (!all_between_min_1_and_1) { + ret = numpy::scale(&signal_frame, 1.0f / 32768.0f); + if (ret != 0) { + EIDSP_ERR(ret); + } + } + } + + ret = numpy::power_spectrum( + signal_frame.buffer, + stack_frame_info.frame_length, + out_features->buffer + (ix * coefficients), + coefficients, + fft_length + ); + + if (ret != 0) { + EIDSP_ERR(ret); + } + } + + numpy::zero_handling(out_features); + + return EIDSP_OK; + } + + /** + * Calculate the buffer size for MFE + * @param signal_length: Length of the signal. + * @param sampling_frequency (int): The sampling frequency of the signal. + * @param frame_length (float): The length of the frame in second. + * @param frame_stride (float): The stride between frames. + * @param num_filters + */ + static matrix_size_t calculate_mfe_buffer_size( + size_t signal_length, + uint32_t sampling_frequency, + float frame_length, float frame_stride, uint16_t num_filters, + uint16_t version) + { + int32_t rows = processing::calculate_no_of_stack_frames( + signal_length, + sampling_frequency, + frame_length, + frame_stride, + false, + version); + int32_t cols = num_filters; + + matrix_size_t size_matrix; + size_matrix.rows = (uint32_t)rows; + size_matrix.cols = (uint32_t)cols; + return size_matrix; + } + + /** + * Compute MFCC features from an audio signal. + * @param out_features Use `calculate_mfcc_buffer_size` to allocate the right matrix. + * @param signal: audio signal structure from which to compute features. + * has functions to retrieve data from a signal lazily. + * @param sampling_frequency (int): the sampling frequency of the signal + * we are working with. + * @param frame_length (float): the length of each frame in seconds. + * Default is 0.020s + * @param frame_stride (float): the step between successive frames in seconds. + * Default is 0.01s (means no overlap) + * @param num_cepstral (int): Number of cepstral coefficients. + * @param num_filters (int): the number of filters in the filterbank, + * default 40. + * @param fft_length (int): number of FFT points. Default is 512. + * @param low_frequency (int): lowest band edge of mel filters. + * In Hz, default is 0. + * @param high_frequency (int): highest band edge of mel filters. + * In Hz, default is samplerate/2 + * @param dc_elimination Whether the first dc component should + * be eliminated or not. + * @returns 0 if OK + */ + static int mfcc(matrix_t *out_features, signal_t *signal, + uint32_t sampling_frequency, float frame_length, float frame_stride, + uint8_t num_cepstral, uint16_t num_filters, uint16_t fft_length, + uint32_t low_frequency, uint32_t high_frequency, bool dc_elimination, + uint16_t version) + { + if (out_features->cols != num_cepstral) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + matrix_size_t mfe_matrix_size = + calculate_mfe_buffer_size( + signal->total_length, + sampling_frequency, + frame_length, + frame_stride, + num_filters, + version); + + if (out_features->rows != mfe_matrix_size.rows) { + EIDSP_ERR(EIDSP_MATRIX_SIZE_MISMATCH); + } + + int ret = EIDSP_OK; + + // allocate some memory for the MFE result + EI_DSP_MATRIX(features_matrix, mfe_matrix_size.rows, mfe_matrix_size.cols); + if (!features_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + EI_DSP_MATRIX(energy_matrix, mfe_matrix_size.rows, 1); + if (!energy_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + ret = mfe(&features_matrix, &energy_matrix, signal, + sampling_frequency, frame_length, frame_stride, num_filters, fft_length, + low_frequency, high_frequency, version); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + // ok... now we need to calculate the MFCC from this... + // first do log() over all features... + ret = numpy::log(&features_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + // now do DST type 2 + ret = numpy::dct2(&features_matrix, DCT_NORMALIZATION_ORTHO); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + // replace first cepstral coefficient with log of frame energy for DC elimination + if (dc_elimination) { + for (size_t row = 0; row < features_matrix.rows; row++) { + features_matrix.buffer[row * features_matrix.cols] = numpy::log(energy_matrix.buffer[row]); + } + } + + // copy to the output... + for (size_t row = 0; row < features_matrix.rows; row++) { + for(int i = 0; i < num_cepstral; i++) { + *(out_features->buffer + (num_cepstral * row) + i) = *(features_matrix.buffer + (features_matrix.cols * row) + i); + } + } + + return EIDSP_OK; + } + + /** + * Calculate the buffer size for MFCC + * @param signal_length: Length of the signal. + * @param sampling_frequency (int): The sampling frequency of the signal. + * @param frame_length (float): The length of the frame in second. + * @param frame_stride (float): The stride between frames. + * @param num_cepstral + */ + static matrix_size_t calculate_mfcc_buffer_size( + size_t signal_length, + uint32_t sampling_frequency, + float frame_length, float frame_stride, uint16_t num_cepstral, + uint16_t version) + { + int32_t rows = processing::calculate_no_of_stack_frames( + signal_length, + sampling_frequency, + frame_length, + frame_stride, + false, + version); + int32_t cols = num_cepstral; + + matrix_size_t size_matrix; + size_matrix.rows = (uint32_t)rows; + size_matrix.cols = (uint32_t)cols; + return size_matrix; + } +}; + +} // namespace speechpy +} // namespace ei + +#endif // _EIDSP_SPEECHPY_FEATURE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/functions.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/functions.hpp new file mode 100644 index 0000000..733c4ac --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/functions.hpp @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPEECHPY_FUNCTIONS_H_ +#define _EIDSP_SPEECHPY_FUNCTIONS_H_ + +#include +#include "../numpy.hpp" +#include "../returntypes.hpp" + +namespace ei { +namespace speechpy { + +class functions { +public: + /** + * Converting from frequency to Mel scale + * + * @param f The frequency values(or a single frequency) in Hz. + * @returns The mel scale values(or a single mel). + */ + static float frequency_to_mel(float f) { +#if EI_PORTING_RENESASRA65 == 1 + return 1127.0 * log(1.0 + f / 700.0f); +#else + return 1127.0 * numpy::log((1.0 + f / 700.0f)); +#endif + } + + /** + * Converting from Mel scale to frequency. + * + * @param mel The mel scale values(or a single mel). + * @returns The frequency values(or a single frequency) in Hz. + */ + static float mel_to_frequency(float mel) { + return 700.0f * (exp(mel / 1127.0f) - 1.0f); + } + + + + + /** + * Triangle, linear scale from left up to middle, then down to right + * @param x Linspace output, will be overwritten! + * @param x_size Size of the linspace output + * @param left Starting index (assigned 0) + * @param middle Index where 1.0 will be placed + * @param right Ending index (assigned 0) + */ + static int triangle(float *x, size_t x_size, int left, int middle, int right) { + EI_DSP_MATRIX(out, 1, x_size); + + for (size_t ix = 0; ix < x_size; ix++) { + if (x[ix] > left && x[ix] <= middle) { + out.buffer[ix] = (x[ix] - left) / (middle - left); + } + + if (x[ix] < right && middle <= x[ix]) { + out.buffer[ix] = (right - x[ix]) / (right - middle); + } + } + + memcpy(x, out.buffer, x_size * sizeof(float)); + + return EIDSP_OK; + } +}; + +} // namespace speechpy +} // namespace ei + +#endif // _EIDSP_SPEECHPY_FUNCTIONS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/processing.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/processing.hpp new file mode 100644 index 0000000..5b34b1b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/processing.hpp @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPEECHPY_PROCESSING_H_ +#define _EIDSP_SPEECHPY_PROCESSING_H_ + +#include "../numpy.hpp" + +namespace ei { +namespace speechpy { + +// one stack frame returned by stack_frames +typedef struct ei_stack_frames_info { + signal_t *signal; + ei_vector frame_ixs; + int frame_length; +} stack_frames_info_t; + +namespace processing { + /** + * Lazy Preemphasising on the signal. + * @param signal: The input signal. + * @param shift (int): The shift step. + * @param cof (float): The preemphasising coefficient. 0 equals to no filtering. + */ + class preemphasis { +public: + preemphasis(ei_signal_t *signal, int shift, float cof, bool rescale) + : _signal(signal), _shift(shift), _cof(cof), _rescale(rescale) + { + _prev_buffer = (float*)ei_dsp_calloc(shift * sizeof(float), 1); + _end_of_signal_buffer = (float*)ei_dsp_calloc(shift * sizeof(float), 1); + _next_offset_should_be = 0; + + if (shift < 0) { + _shift = signal->total_length + shift; + } + + if (!_prev_buffer || !_end_of_signal_buffer) return; + + // we need to get the shift bytes from the end of the buffer... + signal->get_data(signal->total_length - shift, shift, _end_of_signal_buffer); + } + + /** + * Get preemphasized data from the underlying audio buffer... + * This retrieves data from the signal then preemphasizes it. + * @param offset Offset in the audio signal + * @param length Length of the audio signal + */ + int get_data(size_t offset, size_t length, float *out_buffer) { + if (!_prev_buffer || !_end_of_signal_buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + if (offset + length > _signal->total_length) { + EIDSP_ERR(EIDSP_OUT_OF_BOUNDS); + } + + int ret; + if (static_cast(offset) - _shift >= 0) { + ret = _signal->get_data(offset - _shift, _shift, _prev_buffer); + if (ret != 0) { + EIDSP_ERR(ret); + } + } + // else we'll use the end_of_signal_buffer; so no need to check + + ret = _signal->get_data(offset, length, out_buffer); + if (ret != 0) { + EIDSP_ERR(ret); + } + + // now we have the signal and we can preemphasize + for (size_t ix = 0; ix < length; ix++) { + float now = out_buffer[ix]; + + // under shift? read from end + if (offset + ix < static_cast(_shift)) { + out_buffer[ix] = now - (_cof * _end_of_signal_buffer[offset + ix]); + } + // otherwise read from history buffer + else { + out_buffer[ix] = now - (_cof * _prev_buffer[0]); + } + + // roll through and overwrite last element + if (_shift != 1) { + numpy::roll(_prev_buffer, _shift, -1); + } + _prev_buffer[_shift - 1] = now; + } + + _next_offset_should_be += length; + + // rescale from [-1 .. 1] ? + if (_rescale) { + matrix_t scale_matrix(length, 1, out_buffer); + ret = numpy::scale(&scale_matrix, 1.0f / 32768.0f); + if (ret != 0) { + EIDSP_ERR(ret); + } + } + + return EIDSP_OK; + } + + ~preemphasis() { + if (_prev_buffer) { + ei_dsp_free(_prev_buffer, _shift * sizeof(float)); + } + if (_end_of_signal_buffer) { + ei_dsp_free(_end_of_signal_buffer, _shift * sizeof(float)); + } + } + +private: + ei_signal_t *_signal; + int _shift; + float _cof; + float *_prev_buffer; + float *_end_of_signal_buffer; + size_t _next_offset_should_be; + bool _rescale; + }; +} + +namespace processing { + /** + * Preemphasising on the signal. This modifies the signal in place! + * For memory consumption reasons you **probably** want the preemphasis class, + * which lazily loads the signal in. + * @param signal (array): The input signal. + * @param shift (int): The shift step. + * @param cof (float): The preemphasising coefficient. 0 equals to no filtering. + * @returns 0 when successful + */ + __attribute__((unused)) static int preemphasis(float *signal, size_t signal_size, int shift = 1, float cof = 0.98f) + { + if (shift < 0) { + shift = signal_size + shift; + } + + // so we need to keep some history + float *prev_buffer = (float*)ei_dsp_calloc(shift * sizeof(float), 1); + + // signal - cof * xt::roll(signal, shift) + for (size_t ix = 0; ix < signal_size; ix++) { + float now = signal[ix]; + + // under shift? read from end + if (ix < static_cast(shift)) { + signal[ix] = now - (cof * signal[signal_size - shift + ix]); + } + // otherwise read from history buffer + else { + signal[ix] = now - (cof * prev_buffer[0]); + } + + // roll through and overwrite last element + numpy::roll(prev_buffer, shift, -1); + prev_buffer[shift - 1] = now; + } + + ei_dsp_free(prev_buffer, shift * sizeof(float)); + + return EIDSP_OK; + } + + /** + * frame_length is a float and can thus be off by a little bit, e.g. + * frame_length = 0.018f actually can yield 0.018000011f + * thus screwing up our frame calculations here... + */ + static float ceil_unless_very_close_to_floor(float v) { + if (v > floor(v) && v - floor(v) < 0.001f) { + v = (floor(v)); + } + else { + v = (ceil(v)); + } + return v; + } + + /** + * Calculate the length of a signal that will be sused for the settings provided. + * @param signal_size: The number of frames in the signal + * @param sampling_frequency (int): The sampling frequency of the signal. + * @param frame_length (float): The length of the frame in second. + * @param frame_stride (float): The stride between frames. + * @returns Number of frames required, or a negative number if an error occured + */ + __attribute__((unused)) static int calculate_signal_used( + size_t signal_size, + uint32_t sampling_frequency, + float frame_length, + float frame_stride, + bool zero_padding, + uint16_t version) + { + int frame_sample_length; + int length; + if (version == 1) { + frame_sample_length = static_cast(round(static_cast(sampling_frequency) * frame_length)); + frame_stride = round(static_cast(sampling_frequency) * frame_stride); + length = frame_sample_length; + } + else { + frame_sample_length = static_cast(ceil_unless_very_close_to_floor(static_cast(sampling_frequency) * frame_length)); + float frame_stride_arg = frame_stride; + frame_stride = ceil_unless_very_close_to_floor(static_cast(sampling_frequency) * frame_stride_arg); + length = (frame_sample_length - (int)frame_stride); + } + + volatile int numframes; + volatile int len_sig; + + if (zero_padding) { + // Calculation of number of frames + numframes = static_cast( + ceil(static_cast(signal_size - length) / frame_stride)); + + // Zero padding + len_sig = static_cast(static_cast(numframes) * frame_stride) + frame_sample_length; + } + else { + numframes = static_cast( + floor(static_cast(signal_size - length) / frame_stride)); + len_sig = static_cast( + (static_cast(numframes - 1) * frame_stride + frame_sample_length)); + } + + return len_sig; + } + + /** + * Frame a signal into overlapping frames. + * @param info This is both the base object and where we'll store our results. + * @param sampling_frequency (int): The sampling frequency of the signal. + * @param frame_length (float): The length of the frame in second. + * @param frame_stride (float): The stride between frames. + * @param zero_padding (bool): If the samples is not a multiple of + * frame_length(number of frames sample), zero padding will + * be done for generating last frame. + * @returns EIDSP_OK if OK + */ + static int stack_frames(stack_frames_info_t *info, + float sampling_frequency, + float frame_length, + float frame_stride, + bool zero_padding, + uint16_t version) + { + if (!info->signal || !info->signal->get_data || info->signal->total_length == 0) { + EIDSP_ERR(EIDSP_SIGNAL_SIZE_MISMATCH); + } + + size_t length_signal = info->signal->total_length; + int frame_sample_length; + int length; + if (version == 1) { + frame_sample_length = static_cast(round(static_cast(sampling_frequency) * frame_length)); + frame_stride = round(static_cast(sampling_frequency) * frame_stride); + length = frame_sample_length; + } + else { + frame_sample_length = static_cast(ceil_unless_very_close_to_floor(static_cast(sampling_frequency) * frame_length)); + float frame_stride_arg = frame_stride; + frame_stride = ceil_unless_very_close_to_floor(static_cast(sampling_frequency) * frame_stride_arg); + length = (frame_sample_length - (int)frame_stride); + } + + volatile int numframes; + volatile int len_sig; + + if (zero_padding) { + // Calculation of number of frames + numframes = static_cast( + ceil(static_cast(length_signal - length) / frame_stride)); + + // Zero padding + len_sig = static_cast(static_cast(numframes) * frame_stride) + frame_sample_length; + + info->signal->total_length = static_cast(len_sig); + } + else { + numframes = static_cast( + floor(static_cast(length_signal - length) / frame_stride)); + len_sig = static_cast( + (static_cast(numframes - 1) * frame_stride + frame_sample_length)); + + info->signal->total_length = static_cast(len_sig); + } + + info->frame_ixs.clear(); + + int frame_count = 0; + + for (size_t ix = 0; ix < static_cast(len_sig); ix += static_cast(frame_stride)) { + if (++frame_count > numframes) break; + + info->frame_ixs.push_back(ix); + } + + info->frame_length = frame_sample_length; + + return EIDSP_OK; + } + + /** + * Calculate the number of stack frames for the settings provided. + * This is needed to allocate the right buffer size for the output of f.e. the MFE + * blocks. + * @param signal_size: The number of frames in the signal + * @param sampling_frequency (int): The sampling frequency of the signal. + * @param frame_length (float): The length of the frame in second. + * @param frame_stride (float): The stride between frames. + * @param zero_padding (bool): If the samples is not a multiple of + * frame_length(number of frames sample), zero padding will + * be done for generating last frame. + * @returns Number of frames required, or a negative number if an error occured + */ + static int32_t calculate_no_of_stack_frames( + size_t signal_size, + uint32_t sampling_frequency, + float frame_length, + float frame_stride, + bool zero_padding, + uint16_t version) + { + int frame_sample_length; + int length; + if (version == 1) { + frame_sample_length = static_cast(round(static_cast(sampling_frequency) * frame_length)); + frame_stride = round(static_cast(sampling_frequency) * frame_stride); + length = frame_sample_length; + } + else { + frame_sample_length = static_cast(ceil_unless_very_close_to_floor(static_cast(sampling_frequency) * frame_length)); + float frame_stride_arg = frame_stride; + frame_stride = ceil_unless_very_close_to_floor(static_cast(sampling_frequency) * frame_stride_arg); + length = (frame_sample_length - (int)frame_stride); + } + + volatile int numframes; + + if (zero_padding) { + // Calculation of number of frames + numframes = static_cast( + ceil(static_cast(signal_size - length) / frame_stride)); + } + else { + numframes = static_cast( + floor(static_cast(signal_size - length) / frame_stride)); + } + + return numframes; + } + + /** + * This function performs local cepstral mean and + * variance normalization on a sliding window. The code assumes that + * there is one observation per row. + * @param features_matrix input feature matrix, will be modified in place + * @param win_size The size of sliding window for local normalization. + * Default=301 which is around 3s if 100 Hz rate is + * considered(== 10ms frame stide) + * @param variance_normalization If the variance normilization should + * be performed or not. + * @param scale Scale output to 0..1 + * @returns 0 if OK + */ + static int cmvnw(matrix_t *features_matrix, uint16_t win_size = 301, bool variance_normalization = false, + bool scale = false) + { + if (win_size == 0) { + return EIDSP_OK; + } + + uint16_t pad_size = (win_size - 1) / 2; + + int ret; + float *features_buffer_ptr; + + // mean & variance normalization + EI_DSP_MATRIX(vec_pad, features_matrix->rows + (pad_size * 2), features_matrix->cols); + if (!vec_pad.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + ret = numpy::pad_1d_symmetric(features_matrix, &vec_pad, pad_size, pad_size); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + EI_DSP_MATRIX(mean_matrix, vec_pad.cols, 1); + if (!mean_matrix.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + EI_DSP_MATRIX(window_variance, vec_pad.cols, 1); + if (!window_variance.buffer) { + return EIDSP_OUT_OF_MEM; + } + + for (size_t ix = 0; ix < features_matrix->rows; ix++) { + // create a slice on the vec_pad + EI_DSP_MATRIX_B(window, win_size, vec_pad.cols, vec_pad.buffer + (ix * vec_pad.cols)); + if (!window.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + ret = numpy::mean_axis0(&window, &mean_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + // subtract the mean for the features + for (size_t fm_col = 0; fm_col < features_matrix->cols; fm_col++) { + features_matrix->buffer[(ix * features_matrix->cols) + fm_col] = + features_matrix->buffer[(ix * features_matrix->cols) + fm_col] - mean_matrix.buffer[fm_col]; + } + } + + ret = numpy::pad_1d_symmetric(features_matrix, &vec_pad, pad_size, pad_size); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + for (size_t ix = 0; ix < features_matrix->rows; ix++) { + // create a slice on the vec_pad + EI_DSP_MATRIX_B(window, win_size, vec_pad.cols, vec_pad.buffer + (ix * vec_pad.cols)); + if (!window.buffer) { + EIDSP_ERR(EIDSP_OUT_OF_MEM); + } + + if (variance_normalization == true) { + ret = numpy::std_axis0(&window, &window_variance); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + + features_buffer_ptr = &features_matrix->buffer[ix * vec_pad.cols]; + for (size_t col = 0; col < vec_pad.cols; col++) { + *(features_buffer_ptr) = (*(features_buffer_ptr)) / + (window_variance.buffer[col] + 1e-10); + features_buffer_ptr++; + } + } + } + + if (scale) { + ret = numpy::normalize(features_matrix); + if (ret != EIDSP_OK) { + EIDSP_ERR(ret); + } + } + + return EIDSP_OK; + } + + /** + * Perform normalization for MFE frames, this converts the signal to dB, + * then add a hard filter, and quantize / dequantize the output + * @param features_matrix input feature matrix, will be modified in place + */ + static int mfe_normalization(matrix_t *features_matrix, int noise_floor_db) { + const float noise = static_cast(noise_floor_db * -1); + const float noise_scale = 1.0f / (static_cast(noise_floor_db * -1) + 12.0f); + + for (size_t ix = 0; ix < features_matrix->rows * features_matrix->cols; ix++) { + float f = features_matrix->buffer[ix]; + if (f < 1e-30) { + f = 1e-30; + } + f = numpy::log10(f); + f *= 10.0f; // scale by 10 + f += noise; + f *= noise_scale; + // clip again + + /* Here is the python code we're duplicating: + # Quantize to 8 bits and dequantize back to float32 + mfe = np.uint8(np.around(mfe * 2**8)) + # clip to 2**8 + mfe = np.clip(mfe, 0, 255) + mfe = np.float32(mfe / 2**8) + */ + + f = roundf(f*256)/256; + + if (f < 0.0f) f = 0.0f; + else if (f > 1.0f) f = 1.0f; + features_matrix->buffer[ix] = f; + } + + return EIDSP_OK; + } + + /** + * Perform normalization for spectrogram frames, this converts the signal to dB, + * then add a hard filter + * @param features_matrix input feature matrix, will be modified in place + */ + static int spectrogram_normalization(matrix_t *features_matrix, int noise_floor_db, bool clip_at_one) { + const float noise = static_cast(noise_floor_db * -1); + const float noise_scale = 1.0f / (static_cast(noise_floor_db * -1) + 12.0f); + + for (size_t ix = 0; ix < features_matrix->rows * features_matrix->cols; ix++) { + float f = features_matrix->buffer[ix]; + if (f < 1e-30) { + f = 1e-30; + } + f = numpy::log10(f); + f *= 10.0f; // scale by 10 + f += noise; + f *= noise_scale; + // clip again + if (f < 0.0f) f = 0.0f; + else if (f > 1.0f && clip_at_one) f = 1.0f; + features_matrix->buffer[ix] = f; + } + + return EIDSP_OK; + } +}; + +} // namespace speechpy +} // namespace ei + +#endif // _EIDSP_SPEECHPY_PROCESSING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/speechpy.hpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/speechpy.hpp new file mode 100644 index 0000000..c2ca9b6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/dsp/speechpy/speechpy.hpp @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EIDSP_SPEECHPY_SPEECHPY_H_ +#define _EIDSP_SPEECHPY_SPEECHPY_H_ + +#include "../config.hpp" +#include "feature.hpp" +#include "functions.hpp" +#include "processing.hpp" + +#endif // _EIDSP_SPEECHPY_SPEECHPY_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/.clang-format b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/.clang-format new file mode 100644 index 0000000..20ffce8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/.clang-format @@ -0,0 +1,2 @@ +"DisableFormat": true +"SortIncludes": false diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/arduino/debug_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/arduino/debug_log.cpp new file mode 100644 index 0000000..794710e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/arduino/debug_log.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_ARDUINO == 1 + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include +#include + +// On mbed platforms, we set up a serial port and write to it for debug logging. +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 +void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_ARDUINO diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/arduino/ei_classifier_porting.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/arduino/ei_classifier_porting.cpp new file mode 100644 index 0000000..af64f97 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/arduino/ei_classifier_porting.cpp @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_ARDUINO == 1 + +#include +#include +#include + +#define EI_WEAK_FN __attribute__((weak)) + +EI_WEAK_FN EI_IMPULSE_ERROR ei_run_impulse_check_canceled() { + return EI_IMPULSE_OK; +} + +EI_WEAK_FN EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + delay(time_ms); + return EI_IMPULSE_OK; +} + +uint64_t ei_read_timer_ms() { + return millis(); +} + +uint64_t ei_read_timer_us() { + return micros(); +} + +void ei_serial_set_baudrate(int baudrate) +{ + +} + +EI_WEAK_FN void ei_putchar(char c) +{ + Serial.write(c); +} + +EI_WEAK_FN char ei_getchar() +{ + char ch = 0; + if (Serial.available() > 0) { + ch = Serial.read(); + } + return ch; +} + +/** + * Printf function uses vsnprintf and output using Arduino Serial + */ +__attribute__((weak)) void ei_printf(const char *format, ...) { + static char print_buf[1024] = { 0 }; + + va_list args; + va_start(args, format); + int r = vsnprintf(print_buf, sizeof(print_buf), format, args); + va_end(args); + + if (r > 0) { + Serial.write(print_buf); + } +} + +__attribute__((weak)) void ei_printf_float(float f) { + Serial.print(f, 6); +} + +__attribute__((weak)) void *ei_malloc(size_t size) { + return malloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + return calloc(nitems, size); +} + +__attribute__((weak)) void ei_free(void *ptr) { + free(ptr); +} + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif +__attribute__((weak)) void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_ARDUINO == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ei_classifier_porting.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ei_classifier_porting.h new file mode 100644 index 0000000..c0558e8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ei_classifier_porting.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_CLASSIFIER_PORTING_H_ +#define _EI_CLASSIFIER_PORTING_H_ + +#include +#include +#include "edge-impulse-sdk/dsp/returntypes.h" + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" { +#endif // defined(__cplusplus) + +/* Private functions ------------------------------------------------------- */ + +EI_IMPULSE_ERROR ei_run_impulse_check_canceled(); +void ei_serial_set_baudrate(int baudrate); + +/* Public functions -------------------------------------------------------- */ + +/** + * @defgroup ei_user_functions User-defined functions + * + * These functions are required to be implemented by the user for the target platform. + * See [this porting guide](https://docs.edgeimpulse.com/docs/edge-ai-hardware/porting-guide) for more information. They are declared internally in the Edge Impulse + * C++ SDK library, and they must be defined by the user. + * + * **Source**: [porting/ei_classifier_porting.h](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/ei_classifier_porting.h) + * + * **Examples**: + * The following examples demonstrate possible implementations of this function for + * various platforms. Note the `__attribute__((weak))` in most of the definitions, which + * means that a user could override the implementation elsewhere in the program: + * * [Arduino classifier porting](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/arduino/ei_classifier_porting.cpp) + * * [mbed classifier porting](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/mbed/ei_classifier_porting.cpp) + * * [POSIX classifier porting](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/posix/ei_classifier_porting.cpp) + * * [Silicon Labs classifier porting](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/silabs/ei_classifier_porting.cpp) + * * [STM32 classifier porting](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/stm32-cubeai/ei_classifier_porting.cpp) + * * [TI classifier porting](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/ti/debug_log.cpp) + * * [Zephyr classifier porting](https://github.com/edgeimpulse/inferencing-sdk-cpp/blob/master/porting/zephyr/ei_classifier_porting.cpp) + * + * @addtogroup ei_user_functions + * @{ + */ + +/** + * Cancelable sleep, can be triggered with signal from other thread + */ +/** + * @brief Cancellable sleep, can be triggered with signal from other thread + * + * Allow the processor or thread to sleep or block for the given time. + * + * @param[in] time_ms Time in milliseconds to sleep + * + * @return `EI_IMPULSE_OK` if successful, error code otherwise + */ +EI_IMPULSE_ERROR ei_sleep(int32_t time_ms); + +/** + * Read the millisecond timer + */ +/** + * @brief Read the millisecond timer + * + * This function should return the number of milliseconds that have passed since the + * start of the program. If you do not need to determine the run times for DSP and + * inference blocks, you can simply return 0 from this function. Your impulse will still + * work correctly without timing information. + * + * @return The number of milliseconds that have passed since the start of the program + */ +uint64_t ei_read_timer_ms(); + +/** + * @brief Read the microsecond timer + * + * This function should return the number of milliseconds that have passed since the + * start of the program. If you do not need to determine the run times for DSP and + * inference blocks, you can simply return 0 from this function. Your impulse will still + * work correctly without timing information. + * + * @return The number of microseconds that have passed since the start of the program + */ +uint64_t ei_read_timer_us(); + +/** + * @brief Send a single character to the serial port + * + * @param[in] c The chararater to send + */ +void ei_putchar(char c); + +/** + * @brief Read a single character from the serial port + * + * @return The character read from the serial port + */ +char ei_getchar(void); + +/** + * @brief Print wrapper around printf() + * + * `ei_printf()` is declared internally to the Edge Impulse SDK library so that debugging + * information (e.g. during inference) can be printed out. However, the function must be + * defined by the user, as printing methods can change depending on the platform and use + * case. For example, you may want to print debugging information to stdout in Linux or + * over a UART serial port on a microcontroller. + * + * @param[in] format Pointer to a character array or string that should be printed + * @param[in] ... Other optional arguments may be passed as necessary (e.g. handle to a + * UART object). Note that any calls to `ei_printf()` from within the + * *edge-impulse-sdk* library do not pass anything other than the `format` argument. + */ +__attribute__ ((format (printf, 1, 2))) +void ei_printf(const char *format, ...); + +/** + * @brief Used to print floating point numbers + * + * Some platforms cannot handle directly printing floating point numbers (e.g. to a + * console or over a serial port). If your platform cannot directly print floats, + * provide an implementation of this function to print them as needed (for example, + * construct a string containing scientific notation with integers and call + * `ei_printf()`). + * + * If your platform can print floating point values, the easiest implementation of this + * function is as follows: + * + * ``` + * __attribute__((weak)) void ei_printf_float(float f) { + * printf("%f", f); + * } + * ``` + * + * @param[in] f The floating point number to print + */ +void ei_printf_float(float f); + +/** + * @brief Wrapper around malloc + * + * This function should allocate `size` bytes and return a pointer to the allocated + * memory. In bare-metal implementations, it can simply be a wrapper for `malloc()`. For + * example: + * + * ``` + * __attribute__((weak)) void *ei_malloc(size_t size) { + * return malloc(size); + * } + * ``` + * + * If you intend to run your impulse in a multi-threaded environment, you will need to + * ensure that your implementation of `ei_malloc()` is thread-safe. For example, if you + * are using FreeRTOS, here is one possible implementation: + * + * ``` + * __attribute__((weak)) void *ei_malloc(size_t size) { + * return pvPortMalloc(size); + * } + * ``` + * + * @param[in] size The number of bytes to allocate + */ +void *ei_malloc(size_t size); + +/** + * @brief Wrapper around calloc + * + * This function should allocate `nitems * size` bytes and initialize all bytes in this + * allocated memory to 0. It should return a pointer to the allocated memory. In + * bare-metal implementations, it can simply be a wrapper for `calloc()`. For example: + * + * ``` + * __attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + * return calloc(nitems, size); + * } + * ``` + * + * If you intend to run your impulse in a multi-threaded environment, you will need to + * ensure that your implementation of `ei_calloc()` is thread-safe. For example, if you + * are using FreeRTOS, here is one possible implementation: + * + * ``` + * __attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + * void *ptr = NULL; + * if (size > 0) { + * ptr = pvPortMalloc(nitems * size); + * if(ptr) + * memset(ptr, 0, (nitems * size)); + * } + * return ptr; + * } + * ``` + * + * @param[in] nitems Number of blocks to allocate and clear + * @param[in] size Size (in bytes) of each block + */ +void *ei_calloc(size_t nitems, size_t size); + +/** + * @brief Wrapper around free + * + * This function should free the memory space pointed to by `ptr`. If `ptr` is `NULL`, + * no operation should be performed. In bare-metal implementations, it can simply be a + * wrapper for `free()`. For example: + * + * ``` + * __attribute__((weak)) void ei_free(void *ptr) { + * free(ptr); + * } + * ``` + * + * If you intend to run your impulse in a multi-threaded environment, you will need to + * ensure that your implementation of `ei_free()` is thread-safe. For example, if you + * are using FreeRTOS, here is one possible implementation: + * + * ``` + * __attribute__((weak)) void ei_free(void *ptr) { + * pvPortFree(ptr); + * } + * ``` + * + * @param[in] ptr Pointer to the memory to free + */ +void ei_free(void *ptr); + +/** @} */ + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +} +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 + +// Load porting layer depending on target + +// First check if any of the general frameworks or operating systems are supported/enabled +#ifndef EI_PORTING_ZEPHYR +#if defined(__ZEPHYR__) +#define EI_PORTING_ZEPHYR 1 +#else +#define EI_PORTING_ZEPHYR 0 +#endif +#endif + +#ifndef EI_PORTING_ARDUINO +#ifdef ARDUINO +#define EI_PORTING_ARDUINO 1 +#else +#define EI_PORTING_ARDUINO 0 +#endif +#endif + +#ifndef EI_PORTING_MBED +#ifdef __MBED__ +#define EI_PORTING_MBED 1 +#else +#define EI_PORTING_MBED 0 +#endif +#endif + +// Then check for target spcific build systems + +#ifndef EI_PORTING_ESPRESSIF +#if ((defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S3)) && EI_PORTING_ZEPHYR == 0) +#include "esp_idf_version.h" +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0) +#define portTICK_RATE_MS portTICK_PERIOD_MS +#endif +#define EI_PORTING_ESPRESSIF 1 +#define EI_PORTING_ARDUINO 0 +#else +#define EI_PORTING_ESPRESSIF 0 +#endif +#endif + +#ifndef EI_PORTING_POSIX +#if defined (__unix__) || (defined (__APPLE__) && defined (__MACH__)) +#define EI_PORTING_POSIX 1 +#else +#define EI_PORTING_POSIX 0 +#endif +#endif + +#ifndef EI_PORTING_SILABS +#if defined(EFR32MG12P332F1024GL125) +#define EI_PORTING_SILABS 1 +#else +#define EI_PORTING_SILABS 0 +#endif +#endif + +#ifndef EI_PORTING_RASPBERRY +#ifdef PICO_BOARD +#define EI_PORTING_RASPBERRY 1 +#else +#define EI_PORTING_RASPBERRY 0 +#endif +#endif + + +#ifndef EI_PORTING_STM32_CUBEAI +#if defined(USE_HAL_DRIVER) && !defined(__MBED__) && EI_PORTING_ZEPHYR == 0 +#define EI_PORTING_STM32_CUBEAI 1 +#else +#define EI_PORTING_STM32_CUBEAI 0 +#endif +#endif + +#ifndef EI_PORTING_HIMAX +#ifdef CPU_ARC +#define EI_PORTING_HIMAX 1 +#else +#define EI_PORTING_HIMAX 0 +#endif +#endif + +#ifndef EI_PORTING_MINGW32 +#ifdef __MINGW32__ +#define EI_PORTING_MINGW32 1 +#else +#define EI_PORTING_MINGW32 0 +#endif +#endif +// End load porting layer depending on target + +// Additional configuration for specific architecture +#if defined(__CORTEX_M) + +#if (__CORTEX_M == 55U) +#define EI_MAX_OVERFLOW_BUFFER_COUNT 15 +#endif + +#if (__CORTEX_M == 85U) +#define EI_MAX_OVERFLOW_BUFFER_COUNT 50 +#endif + +#endif + +#if defined(CONFIG_IDF_TARGET_ESP32S3) +#define EI_MAX_OVERFLOW_BUFFER_COUNT 30 +#endif + +// End additional configuration + +#endif // _EI_CLASSIFIER_PORTING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ei_logging.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ei_logging.h new file mode 100644 index 0000000..b69604b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ei_logging.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _EI_LOGGING_H_ +#define _EI_LOGGING_H_ + +#include +#include + +#include "ei_classifier_porting.h" + +#define EI_LOG_LEVEL_NONE 0 /*!< No log output */ +#define EI_LOG_LEVEL_ERROR 1 /*!< Critical errors, software module can not recover on its own */ +#define EI_LOG_LEVEL_WARNING 2 /*!< Error conditions from which recovery measures have been taken */ +#define EI_LOG_LEVEL_INFO 3 /*!< Information messages which describe normal flow of events */ +#define EI_LOG_LEVEL_DEBUG 4 /*!< Extra information which is not necessary for normal use (values, pointers, sizes, etc). */ + +// if we do not want ANY logging, setting EI_LOG_LEVEL to EI_LOG_LEVEL_NONE +// will not generate any code according to +// https://stackoverflow.com/a/25021889 + +#define EI_LOGE(format, ...) (void)0 +#define EI_LOGW(format, ...) (void)0 +#define EI_LOGI(format, ...) (void)0 +#define EI_LOGD(format, ...) (void)0 + +#ifndef EI_LOG_LEVEL + #define EI_LOG_LEVEL EI_LOG_LEVEL_INFO +#endif + +__attribute__((unused)) static const char *debug_msgs[] = +{ + "NONE", // this one will never show + "ERR", + "WARNING", + "INFO", + "DEBUG" +}; + +#if EI_LOG_LEVEL >= EI_LOG_LEVEL_ERROR + #ifdef EI_LOGE + #undef EI_LOGE + #endif // EI_LOGE + #define EI_LOGE(format, ...) ei_printf("%s: ",debug_msgs[EI_LOG_LEVEL_ERROR]); ei_printf(format, ##__VA_ARGS__); +#endif + +#if EI_LOG_LEVEL >= EI_LOG_LEVEL_WARNING + #ifdef EI_LOGW + #undef EI_LOGW + #endif // EI_LOGW + #define EI_LOGW(format, ...) ei_printf("%s: ",debug_msgs[EI_LOG_LEVEL_WARNING]); ei_printf(format, ##__VA_ARGS__); +#endif + +#if EI_LOG_LEVEL >= EI_LOG_LEVEL_INFO + #ifdef EI_LOGI + #undef EI_LOGI + #endif // EI_LOGI + #define EI_LOGI(format, ...) ei_printf("%s: ",debug_msgs[EI_LOG_LEVEL_INFO]); ei_printf(format, ##__VA_ARGS__); +#endif + +#if EI_LOG_LEVEL >= EI_LOG_LEVEL_DEBUG + #ifdef EI_LOGD + #undef EI_LOGD + #endif // EI_LOGD + #define EI_LOGD(format, ...) ei_printf("%s: ",debug_msgs[EI_LOG_LEVEL_DEBUG]); ei_printf(format, ##__VA_ARGS__); +#endif + +#endif // _EI_LOGGING_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/CMakeLists.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/CMakeLists.txt new file mode 100644 index 0000000..736eaf9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/CMakeLists.txt @@ -0,0 +1,51 @@ +cmake_minimum_required(VERSION 3.5) + +set(c_srcs + "src/activation_functions/esp_nn_relu_ansi.c" + "src/basic_math/esp_nn_add_ansi.c" + "src/basic_math/esp_nn_mul_ansi.c" + "src/convolution/esp_nn_conv_ansi.c" + "src/convolution/esp_nn_conv_opt.c" + "src/convolution/esp_nn_depthwise_conv_ansi.c" + "src/convolution/esp_nn_depthwise_conv_opt.c" + "src/fully_connected/esp_nn_fully_connected_ansi.c" + "src/softmax/esp_nn_softmax_ansi.c" + "src/softmax/esp_nn_softmax_opt.c" + "src/pooling/esp_nn_avg_pool_ansi.c" + "src/pooling/esp_nn_max_pool_ansi.c") + +if(CONFIG_IDF_TARGET_ESP32S3) + set(s3_srcs + "src/common/esp_nn_common_functions_esp32s3.S" + "src/common/esp_nn_multiply_by_quantized_mult_esp32s3.S" + "src/common/esp_nn_multiply_by_quantized_mult_ver1_esp32s3.S" + "src/activation_functions/esp_nn_relu_s8_esp32s3.S" + "src/basic_math/esp_nn_add_s8_esp32s3.S" + "src/basic_math/esp_nn_mul_s8_esp32s3.S" + "src/convolution/esp_nn_conv_esp32s3.c" + "src/convolution/esp_nn_depthwise_conv_s8_esp32s3.c" + "src/convolution/esp_nn_conv_s16_mult8_esp32s3.S" + "src/convolution/esp_nn_conv_s8_mult8_1x1_esp32s3.S" + "src/convolution/esp_nn_conv_s16_mult4_1x1_esp32s3.S" + "src/convolution/esp_nn_conv_s8_filter_aligned_input_padded_esp32s3.S" + "src/convolution/esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3.S" + "src/convolution/esp_nn_depthwise_conv_s16_mult1_esp32s3.S" + "src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3.S" + "src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3.S" + "src/convolution/esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3.S" + "src/convolution/esp_nn_depthwise_conv_s16_mult4_esp32s3.S" + "src/convolution/esp_nn_depthwise_conv_s16_mult8_esp32s3.S" + "src/fully_connected/esp_nn_fully_connected_s8_esp32s3.S" + "src/pooling/esp_nn_max_pool_s8_esp32s3.S" + "src/pooling/esp_nn_avg_pool_s8_esp32s3.S") +endif() + +idf_component_register(SRCS "${c_srcs}" + "${s3_srcs}" + INCLUDE_DIRS "include" "src/common") + +if(CONFIG_IDF_TARGET_ESP32S3) + target_compile_options(${COMPONENT_LIB} PRIVATE -mlongcalls -fno-unroll-loops -O2 -Wno-unused-function) +else() + target_compile_options(${COMPONENT_LIB} PRIVATE -O2 -Wno-unused-function) +endif() diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/CONTRIBUTING.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/CONTRIBUTING.md new file mode 100644 index 0000000..b541db7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/CONTRIBUTING.md @@ -0,0 +1,38 @@ +# Contributing + +Contributions to ESP-NN project in the form of pull requests, bug reports, and feature requests are welcome! + +This document covers various topics related to contributions to the ESP-NN projects. Please read it if you plan to submit a PR! + +## CLA + +We require accepting the contributor's license agreement for all pull requests. When opening a pull request the first time you will be prompted to sign the CLA by the [CLA Assistant](https://cla-assistant.io/) service. + +## Large-scale Changes + +If you'd like to propose a change to the existing APIs or a large-scale refactoring of the implementation, we recommend opening an issue first to discuss this. + +## Updating the Benchmarks Table + +The benchmarks table in [README.md](README.md) contains benchmarks for ESP32-S3. The benchmarks are collected by running the app in [test_app](test_app/) directory. Please update this table if you have changed the implementations of some of the functions or added the new ones. + +## Releasing a new version + +Maintainers should follow the steps below to release a new version of ESP-NN component. Assuming the new version is `vX.Y.Z`: + +1. Ensure you are on the latest `master` branch: + ```bash + git checkout master + git pull --ff-only origin master + ``` +1. Create the new tag: + ```bash + git tag -s -a -m "vX.Y.Z" vX.Y.Z + ``` +1. Push the tag and the branch to the internal repository: + ```bash + git push origin vX.Y.Z + ``` +1. CI will automatically push the tag to Github and will upload the new version to the IDF Component Registry. +1. Go to https://github.com/espressif/esp-nn/releases and create a release from the tag vX.Y.Z. +1. Write the release notes and publish the release. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/Kconfig.projbuild b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/Kconfig.projbuild new file mode 100644 index 0000000..a146305 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/Kconfig.projbuild @@ -0,0 +1,29 @@ +menu "ESP-NN" + +choice NN_OPTIMIZATIONS + bool "Optimization for nn functions" + default NN_OPTIMIZED + help + Use ANSI-C versions for verification and debug purpose. + Optimisations are automatically picked up for a chipset. + For ESP32-S3, assembly optimisations are selected. + For other platforms(viz., ESP32, ESP32-C3), generic optimisations are used. + +config NN_ANSI_C + bool "ANSI C" + help + ANSI C versions for verification and debug purposes. +config NN_OPTIMIZED + bool "Optimized versions" + help + Optimisations are automatically picked up for a chipset. + For ESP32-S3, assembly optimisations are selected. + For other platforms(viz., ESP32, ESP32-C3), generic optimisations are used. +endchoice + +config NN_OPTIMIZATIONS + int + default 0 if NN_ANSI_C + default 1 if NN_OPTIMIZED + +endmenu diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/LICENSE b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/LICENSE new file mode 100644 index 0000000..d645695 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/README.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/README.md new file mode 100644 index 0000000..2efde15 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/README.md @@ -0,0 +1 @@ +Internal Edge Impulse fork of ESP-NN. Derived from https://github.com/edgeimpulse/esp-nn/commit/6b3ef8e226a05554a6d874f6456f5ca1771c01c2. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/idf_component.yml b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/idf_component.yml new file mode 100644 index 0000000..b90ac5e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/idf_component.yml @@ -0,0 +1,11 @@ +description: Optimized NN (Neural Network) functions for Espressif chips +url: https://github.com/espressif/esp-nn +repository: https://github.com/espressif/esp-nn.git +issues: https://github.com/espressif/esp-nn/issues +dependencies: + idf: + version: ">=4.2" +files: + exclude: + - test_app + - tests diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h new file mode 100644 index 0000000..3d2ef30 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h @@ -0,0 +1,46 @@ +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#if defined(EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN) +// select apt optimisations +#ifdef CONFIG_IDF_TARGET_ESP32S3 +#define ARCH_ESP32_S3 1 +#endif +#ifdef CONFIG_IDF_TARGET_ESP32 +#define ARCH_ESP32 1 +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* reference kernels included by default */ +#include "esp_nn_ansi_headers.h" + +#if defined(EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN) +#if defined(ARCH_ESP32_S3) +#include "esp_nn_esp32s3.h" +#else // for other platforms use generic optimisations +#include "esp_nn_generic_opt.h" +#endif // #if defined(ARCH_ESP32_S3) +#else +#include "esp_nn_ansi_c.h" +#endif + +#ifdef __cplusplus +} +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_ansi_c.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_ansi_c.h new file mode 100644 index 0000000..8279ebe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_ansi_c.h @@ -0,0 +1,47 @@ +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @file Header definitions to include for ANSI C versions. + * These are just typedefs to pick up ANSI versions. + */ + +#pragma once + +#include "esp_nn_defs.h" +#include "esp_nn_ansi_headers.h" + +#define esp_nn_add_elementwise_s8 esp_nn_add_elementwise_s8_ansi +#define esp_nn_mul_elementwise_s8 esp_nn_mul_elementwise_s8_ansi + +#define esp_nn_depthwise_conv_s8 esp_nn_depthwise_conv_s8_ansi + +#define esp_nn_conv_s8 esp_nn_conv_s8_ansi + +#define esp_nn_get_conv_scratch_size esp_nn_get_conv_scratch_size_ansi +#define esp_nn_set_conv_scratch_buf esp_nn_set_conv_scratch_buf_ansi + +#define esp_nn_get_depthwise_conv_scratch_size esp_nn_get_depthwise_conv_scratch_size_ansi +#define esp_nn_set_depthwise_conv_scratch_buf esp_nn_set_depthwise_conv_scratch_buf_ansi + +#define esp_nn_relu6_s8 esp_nn_relu6_s8_ansi + +#define esp_nn_avg_pool_s8 esp_nn_avg_pool_s8_ansi +#define esp_nn_max_pool_s8 esp_nn_max_pool_s8_ansi + +#define esp_nn_fully_connected_s8 esp_nn_fully_connected_s8_ansi + +#define esp_nn_get_softmax_scratch_size esp_nn_get_softmax_scratch_size_ansi +#define esp_nn_set_softmax_scratch_buf esp_nn_set_softmax_scratch_buf_ansi +#define esp_nn_softmax_s8 esp_nn_softmax_s8_ansi diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_ansi_headers.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_ansi_headers.h new file mode 100644 index 0000000..52ebb68 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_ansi_headers.h @@ -0,0 +1,309 @@ +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file Header definitions to include for esp_nn reference functions + */ + +#include "esp_nn_defs.h" +/************************** Basic math functions ****************************/ + +/** + * @brief elementwise addition + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + * + * shift values are expected to be <= 0 + */ +void esp_nn_add_elementwise_s8_ansi(const int8_t *input1_data, + const int8_t *input2_data, + const int32_t input1_offset, + const int32_t input2_offset, + const int32_t input1_mult, + const int32_t input2_mult, + const int32_t input1_shift, + const int32_t input2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t activation_min, + const int32_t activation_max, + const int32_t size); +/** + * @brief elementwise multiplication + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + * + * output shift is expected to be <= 0 + */ +void esp_nn_mul_elementwise_s8_ansi(const int8_t *input1_data, + const int8_t *input2_data, + const int32_t input1_offset, + const int32_t input2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t activation_min, + const int32_t activation_max, + const int32_t size); + + +/************************** Convolution functions *****************************/ + +/** + * @brief depthwise convolution per channel + * + * @note inputs type: int8_t, output: int8_t + * Version used in tflite is per channel. + * This version follows the same footsprints. + * Meaning, it has per out_channel shift and multiplier for + * requantization + * + * optimization notes: Though input_offset is int32 type, + * offset values are contained in 8 bits [-128, 127] + */ +void esp_nn_depthwise_conv_s8_ansi(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const dw_conv_params_t *conv_params, + const quant_data_t *quant_data); + +/** + * @brief 2d-convolution channelwise + * + * @note operation: result += (input + offset) * filter + * + * inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_conv_s8_ansi(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const conv_params_t *conv_params, + const quant_data_t *quant_data); + +int esp_nn_get_conv_scratch_size_ansi(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const conv_params_t *conv_params); +void esp_nn_set_conv_scratch_buf_ansi(const void *buf); + +int esp_nn_get_depthwise_conv_scratch_size_ansi(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const dw_conv_params_t *conv_params); +void esp_nn_set_depthwise_conv_scratch_buf_ansi(const void *buf); + +/************************** Activation functions *****************************/ + +/** + * @brief relu6 + * + * @note inout: int8_t + */ +void esp_nn_relu6_s8_ansi(int8_t *data, uint16_t size); + +/************************** Pooling functions *****************************/ + + +/** + * @brief max_pool + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_max_pool_s8_ansi(const int8_t *input, + const uint16_t input_wd, + const uint16_t input_ht, + int8_t *output, + const uint16_t output_wd, + const uint16_t output_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t filter_wd, + const uint16_t filter_ht, + const uint16_t pad_wd, + const uint16_t pad_ht, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t channels); + +/** + * @brief avg_pool + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_avg_pool_s8_ansi(const int8_t *input, + const uint16_t input_wd, + const uint16_t input_ht, + int8_t *output, + const uint16_t output_wd, + const uint16_t output_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t filter_wd, + const uint16_t filter_ht, + const uint16_t pad_wd, + const uint16_t pad_ht, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t channels); + + +/************************** Fully connected functions ***********************/ + +/** + * @brief fully connected + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_fully_connected_s8_ansi(const int8_t *input_data, + const int32_t input_offset, + const uint16_t row_len, + const int8_t *filter_data, + const int32_t filter_offset, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_channels, + const int32_t out_offset, + const int32_t out_shift, + const int32_t out_mult, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief Get scratch buffer size needed by softmax function + * + * @param width + * @param height + * @return size in bytes + * + * @note buffer must be 4 byte aligned + */ +int32_t esp_nn_get_softmax_scratch_size_ansi(const int32_t width, const int32_t height); + +/* ANSI C function to be hooked up when optimised version needed */ +int32_t esp_nn_get_softmax_scratch_size_opt(const int32_t width, const int32_t height); + +/** + * @brief Set scratch buffer to be used by softmax function + * + * @param buffer this can be NULL if one needs to unset it + * must be aligned to 4 bytes + */ +void esp_nn_set_softmax_scratch_buf_ansi(void *buffer); + +/** + * @brief reference softmax function + * + * @note inputs type: int8_t, output: int8_t + */ +void esp_nn_softmax_s8_ansi(const int8_t *input_data, + const int32_t height, + const int32_t width, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output_data); + + +//////////////////////////// Generic optimisations ///////////////////////////// + +/************************** Convolution functions *****************************/ + +/** + * @brief 2d-convolution channelwise optimized version + * + * @note operation: result += (input + offset) * filter + * + * inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_conv_s8_opt(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const conv_params_t *conv_params, + const quant_data_t *quant_data); + +/** + * @brief depthwise convolution per channel optimized version + * + * @note inputs type: int8_t, output: int8_t + * Version used in tflite is per channel. + * This version follows the same footsprints. + * Meaning, it has per out_channel shift and multiplier for + * requantization + * + * optimization notes: Though input_offset is int32 type, + * offset values are contained in 8 bits [-128, 127] + */ +void esp_nn_depthwise_conv_s8_opt(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const dw_conv_params_t *conv_params, + const quant_data_t *quant_data); + +int esp_nn_get_conv_scratch_size_opt(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const conv_params_t *conv_params); +void esp_nn_set_conv_scratch_buf_opt(const void *buf); + +int esp_nn_get_depthwise_conv_scratch_size_opt(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const dw_conv_params_t *conv_params); +void esp_nn_set_depthwise_conv_scratch_buf_opt(const void *buf); + +/* ANSI C function to be hooked up when optimised version needed */ +void esp_nn_set_softmax_scratch_buf_opt(void *buffer); + +/** + * @brief optimised version of softmax function + * + * @note the function uses extra buffer (4 * width bytes) + * hence, scratch buffers must be set before calling this. + */ +void esp_nn_softmax_s8_opt(const int8_t *input_data, + const int32_t height, + const int32_t width, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output_data); diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_defs.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_defs.h new file mode 100644 index 0000000..756d8e6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_defs.h @@ -0,0 +1,83 @@ +// Copyright 2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +/** + * @brief structure to club data dims + * this structure can be used for input, output and filter + */ +typedef struct data_dims { + int32_t width; + int32_t height; + int32_t channels; + + int32_t extra; // can be used as batch or any other param +} data_dims_t; + +/** + * @brief 2d data structure (width, height) + * + */ +typedef struct data_2d { + int32_t width; + int32_t height; +} data_2d_t; + +/** + * @brief min/max activation + */ +typedef struct act_params { + int32_t min; + int32_t max; +} act_params_t; + +/** + * @brief per channel quant data + * + * @note number of shift and mult elements are equal to output channels + */ +typedef struct quant_data { + int32_t *shift; + int32_t *mult; +} quant_data_t; + +/** + * @brief params specific to convolution 2d + * + */ +typedef struct conv_params { + int32_t in_offset; + int32_t out_offset; + data_2d_t stride; + data_2d_t padding; + data_2d_t dilation; + act_params_t activation; +} conv_params_t; + +/** + * @brief params specific to depthwise convolution 2d + * + */ +typedef struct dw_conv_params { + int32_t in_offset; + int32_t out_offset; + int32_t ch_mult; // channel multiplier. (in_ch * ch_mult = out_ch) + data_2d_t stride; + data_2d_t padding; + data_2d_t dilation; + act_params_t activation; +} dw_conv_params_t; diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_esp32s3.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_esp32s3.h new file mode 100644 index 0000000..0f52c94 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_esp32s3.h @@ -0,0 +1,231 @@ +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @file Header definitions to include for esp_nn optimized functions for + * the ESP32-S3 platform + */ + +#pragma once + +#include "esp_nn_defs.h" +#include "esp_nn_ansi_headers.h" + +/************************** Basic math functions *****************************/ + + +/** + * @brief elementwise addition + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + * + * shift values are expected to be <= 0 + */ +void esp_nn_add_elementwise_s8_esp32s3(const int8_t *input1_data, + const int8_t *input2_data, + const int32_t input1_offset, + const int32_t input2_offset, + const int32_t input1_mult, + const int32_t input2_mult, + const int32_t input1_shift, + const int32_t input2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t activation_min, + const int32_t activation_max, + const int32_t size); + +/** + * @brief elementwise multiplication + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + * + * output shift is expected to be <= 0 + */ +void esp_nn_mul_elementwise_s8_esp32s3(const int8_t *input1_data, + const int8_t *input2_data, + const int32_t input1_offset, + const int32_t input2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t activation_min, + const int32_t activation_max, + const int32_t size); + + +/************************** Convolution functions *****************************/ + +/** + * @brief depthwise convolution per channel + * + * @note inputs type: int8_t, output: int8_t + * Version used in tflite is per channel. + * This version follows the same footsprints. + * Meaning, it has per out_channel shift and multiplier for + * requantization + * + * optimization notes: Though input_offset is int32 type, + * offset values are contained in 8 bits [-128, 127] + */ +void esp_nn_depthwise_conv_s8_esp32s3(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *output_data, + const dw_conv_params_t *conv_params, + const quant_data_t *quant_data); + +/** + * @brief 2d - convolution channelwise + * + * @note operation: result += (input + offset) * filter + * + * inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_conv_s8_esp32s3(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *output_data, + const conv_params_t *conv_params, + const quant_data_t *quant_data); + +int esp_nn_get_conv_scratch_size_esp32s3(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const conv_params_t *conv_params); +void esp_nn_set_conv_scratch_buf_esp32s3(const void *buf); + +int esp_nn_get_depthwise_conv_scratch_size_esp32s3(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const dw_conv_params_t *conv_params); +void esp_nn_set_depthwise_conv_scratch_buf_esp32s3(const void *buf); + +/************************** Pooling functions *****************************/ + +/** + * @brief max_pool + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_max_pool_s8_esp32s3(const int8_t *input, + const uint16_t input_wd, + const uint16_t input_ht, + int8_t *output, + const uint16_t output_wd, + const uint16_t output_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t filter_wd, + const uint16_t filter_ht, + const uint16_t pad_wd, + const uint16_t pad_ht, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t channels); + +/** + * @brief avg_pool + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + */ +void esp_nn_avg_pool_s8_esp32s3(const int8_t *input, + const uint16_t input_wd, + const uint16_t input_ht, + int8_t *output, + const uint16_t output_wd, + const uint16_t output_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t filter_wd, + const uint16_t filter_ht, + const uint16_t pad_wd, + const uint16_t pad_ht, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t channels); + + +/************************** Fully connected functions *****************************/ + +/** + * @brief fully connected + * + * @note inputs type: int8_t, output: int8_t + * input offsets: although int32_t, they are contained in 8 bits [-128, 127] + * + * Current version works only on aligned input. + * row_len and channels should both be multiple of 8. + */ +void esp_nn_fully_connected_s8_esp32s3(const int8_t *input_data, + const int32_t input_offset, + const uint16_t row_len, + const int8_t *filter_data, + const int32_t filter_offset, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_channels, + const int32_t out_offset, + const int32_t out_shift, + const int32_t out_mult, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief relu6 + * + * @note inout: int8_t + */ +void esp_nn_relu6_s8_esp32s3(int8_t *data, uint16_t size); + +/********************** function defines ***************************/ + +#define esp_nn_add_elementwise_s8 esp_nn_add_elementwise_s8_esp32s3 +#define esp_nn_mul_elementwise_s8 esp_nn_mul_elementwise_s8_esp32s3 + +#define esp_nn_depthwise_conv_s8 esp_nn_depthwise_conv_s8_esp32s3 + +#define esp_nn_get_conv_scratch_size esp_nn_get_conv_scratch_size_esp32s3 +#define esp_nn_set_conv_scratch_buf esp_nn_set_conv_scratch_buf_esp32s3 + +#define esp_nn_get_depthwise_conv_scratch_size esp_nn_get_depthwise_conv_scratch_size_esp32s3 +#define esp_nn_set_depthwise_conv_scratch_buf esp_nn_set_depthwise_conv_scratch_buf_esp32s3 + +#define esp_nn_conv_s8 esp_nn_conv_s8_esp32s3 + +#define esp_nn_relu6_s8 esp_nn_relu6_s8_esp32s3 + +#define esp_nn_avg_pool_s8 esp_nn_avg_pool_s8_esp32s3 +#define esp_nn_max_pool_s8 esp_nn_max_pool_s8_esp32s3 + +#define esp_nn_fully_connected_s8 esp_nn_fully_connected_s8_esp32s3 + +#define esp_nn_get_softmax_scratch_size esp_nn_get_softmax_scratch_size_opt +#define esp_nn_set_softmax_scratch_buf esp_nn_set_softmax_scratch_buf_opt +#define esp_nn_softmax_s8 esp_nn_softmax_s8_opt diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_generic_opt.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_generic_opt.h new file mode 100644 index 0000000..136cba5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn_generic_opt.h @@ -0,0 +1,47 @@ +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/** + * @file Header definitions to include for esp_nn generic optimisations + * For functions which not having optimisations, _ansi versions are picked. + */ + +#pragma once + +#include "esp_nn_defs.h" +#include "esp_nn_ansi_headers.h" + +#define esp_nn_add_elementwise_s8 esp_nn_add_elementwise_s8_ansi +#define esp_nn_mul_elementwise_s8 esp_nn_mul_elementwise_s8_ansi + +#define esp_nn_depthwise_conv_s8 esp_nn_depthwise_conv_s8_opt + +#define esp_nn_conv_s8 esp_nn_conv_s8_opt + +#define esp_nn_get_conv_scratch_size esp_nn_get_conv_scratch_size_opt +#define esp_nn_set_conv_scratch_buf esp_nn_set_conv_scratch_buf_opt + +#define esp_nn_get_depthwise_conv_scratch_size esp_nn_get_depthwise_conv_scratch_size_opt +#define esp_nn_set_depthwise_conv_scratch_buf esp_nn_set_depthwise_conv_scratch_buf_opt + +#define esp_nn_relu6_s8 esp_nn_relu6_s8_ansi + +#define esp_nn_avg_pool_s8 esp_nn_avg_pool_s8_ansi +#define esp_nn_max_pool_s8 esp_nn_max_pool_s8_ansi + +#define esp_nn_fully_connected_s8 esp_nn_fully_connected_s8_ansi + +#define esp_nn_get_softmax_scratch_size esp_nn_get_softmax_scratch_size_opt +#define esp_nn_set_softmax_scratch_buf esp_nn_set_softmax_scratch_buf_opt +#define esp_nn_softmax_s8 esp_nn_softmax_s8_opt diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/activation_functions/esp_nn_relu_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/activation_functions/esp_nn_relu_ansi.c new file mode 100644 index 0000000..2ac260f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/activation_functions/esp_nn_relu_ansi.c @@ -0,0 +1,34 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +#include + +void esp_nn_relu6_s8_ansi(int8_t *data, uint16_t size) +{ + int32_t i; + + for (i = 0; i < size; i++) { + int32_t ip = data[i]; + + ip = max(ip, 0); + data[i] = min(ip, 6); + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/activation_functions/esp_nn_relu_s8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/activation_functions/esp_nn_relu_s8_esp32s3.S new file mode 100644 index 0000000..b020920 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/activation_functions/esp_nn_relu_s8_esp32s3.S @@ -0,0 +1,118 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + + .text + .align 4 + .literal_position + +# in place relu6 function. a2: data, a3: size + # Program Unit: esp_nn_relu6_s8_esp32s3 + .type esp_nn_relu6_s8_esp32s3, @function + .align 4 + .global esp_nn_relu6_s8_esp32s3 + +esp_nn_relu6_s8_esp32s3: + entry a1,48 # + mov.n a9,a2 # [0], data + mov.n a7,a3 # [1], size + + // process multiple of 16 + movi.n a4,6 # [4] + s8i a4,a1,0 # [5] six + addi a10,a3,-7 # [2] + ee.vldbc.8 q1,a1 # [6] id:72 six+0x0 + blti a3,16,.Lt_0_5634 # [7] + + srai a8,a3,4 # [0] + ee.zero.q q2 # [1] + loopgtz a8,.LBB37_esp_nn_relu6_s8_esp32s3 # [3] + + ee.vld.128.ip q0,a2,0 # [0*II+0] id:73 + ee.vmax.s8 q0,q0,q2 # [0*II+2] + ee.vmin.s8 q0,q0,q1 # [0*II+3] + ee.vst.128.ip q0,a2,16 # [0*II+4] id:74 +.LBB37_esp_nn_relu6_s8_esp32s3: # 0x34 + + slli a8,a8,4 # [0] + + // remaining multiple of 8 data + bge a8,a10,.Lt_0_3586 # [1] + +.Lt_0_3842: # 0x3a + sub a6,a7,a8 # [0] + srai a6,a6,3 # [1] + loopgtz a6,.LBB52_esp_nn_relu6_s8_esp32s3 # [2] + + ee.vld.l.64.ip q0,a2,0 # [0*II+0] id:75 + ee.vmax.s8 q0,q0,q2 # [0*II+2] + ee.vmin.s8 q0,q0,q1 # [0*II+3] + ee.vst.l.64.ip q0,a2,8 # [0*II+4] id:76 + +.LBB52_esp_nn_relu6_s8_esp32s3: # 0x4f + addx8 a8,a6,a8 # [0] + +.Lt_0_3586: # 0x52 + // process leftover + bge a8,a7,.Lt_0_6402 # [0] + +.Lt_0_4866: # 0x55 + movi.n a5,0 # [0] + sub a3,a7,a8 # [1] + add.n a2,a8,a9 # [2] + l8ui a6,a2,0 # [3] id:78 + addi.n a3,a3,-1 # [4] + sext a6,a6,7 + max a6,a5,a6 # [6] + min a6,a4,a6 # [7] + s8i a6,a2,0 # [8] id:79 + + loopgtz a3,.LBB67_esp_nn_relu6_s8_esp32s3 # [9] + + l8ui a3,a2,1 # [0*II+0] id:78 + addi.n a2,a2,1 # [1*II+1] + sext a3,a3,7 + max a3,a5,a3 # [0*II+3] + min a3,a4,a3 # [0*II+4] + s8i a3,a2,0 # [0*II+5] id:79 +.LBB67_esp_nn_relu6_s8_esp32s3: # 0x81 + +.Lt_0_6402: # 0x83 + retw.n # [0] + +.Lt_0_5634: # 0x85 + blti a10,1,.Lt_0_5890 # [0] + + movi.n a8,0 # [0] + ee.zero.q q2 # [1] + j .Lt_0_3842 # [2] + +.Lt_0_5890: # 0x90 + beqz.n a3,.Lt_0_6402 # [0] + + movi.n a8,0 # [0] + j .Lt_0_4866 # [1] + + .size esp_nn_relu6_s8_esp32s3, . - esp_nn_relu6_s8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_add_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_add_ansi.c new file mode 100644 index 0000000..b123d62 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_add_ansi.c @@ -0,0 +1,101 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include + +void esp_nn_add_elementwise_u8_ansi(const uint8_t *input1_data, + const uint8_t *input2_data, + const int32_t input1_offset, + const int32_t input2_offset, + const int32_t input1_mult, + const int32_t input2_mult, + const int32_t input1_shift, + const int32_t input2_shift, + const int32_t left_shift, + uint8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t activation_min, + const int32_t activation_max, + const int32_t size) +{ + for (int i = 0; i < size; i++) { + int32_t tmp1 = input1_data[i] + input1_offset; + int32_t tmp2 = input2_data[i] + input2_offset; + + tmp1 <<= left_shift; + tmp2 <<= left_shift; + + tmp1 = esp_nn_sat_round_doubling_high_mul(tmp1, input1_mult); + tmp2 = esp_nn_sat_round_doubling_high_mul(tmp2, input2_mult); + + tmp1 = esp_nn_div_by_power_of_two(tmp1, -input1_shift); + tmp2 = esp_nn_div_by_power_of_two(tmp2, -input2_shift); + + int32_t out = tmp1 + tmp2; + out = esp_nn_sat_round_doubling_high_mul(out, out_mult); + out = esp_nn_div_by_power_of_two(out, -out_shift); + out = out + out_offset; + + out = max(activation_min, min(out, activation_max)); + output[i] = (uint8_t) out; + } +} + +void esp_nn_add_elementwise_s8_ansi(const int8_t *input1_data, + const int8_t *input2_data, + const int32_t input1_offset, + const int32_t input2_offset, + const int32_t input1_mult, + const int32_t input2_mult, + const int32_t input1_shift, + const int32_t input2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t activation_min, + const int32_t activation_max, + const int32_t size) +{ + for (int i = 0; i < size; i++) { + int32_t tmp1 = input1_data[i] + input1_offset; + int32_t tmp2 = input2_data[i] + input2_offset; + + tmp1 <<= left_shift; + tmp2 <<= left_shift; + + tmp1 = esp_nn_sat_round_doubling_high_mul(tmp1, input1_mult); + tmp2 = esp_nn_sat_round_doubling_high_mul(tmp2, input2_mult); + + tmp1 = esp_nn_div_by_power_of_two(tmp1, -input1_shift); + tmp2 = esp_nn_div_by_power_of_two(tmp2, -input2_shift); + + int32_t out = tmp1 + tmp2; + out = esp_nn_sat_round_doubling_high_mul(out, out_mult); + out = esp_nn_div_by_power_of_two(out, -out_shift); + out = out + out_offset; + + out = max(activation_min, min(out, activation_max)); + output[i] = (int8_t) out; + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_add_s8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_add_s8_esp32s3.S new file mode 100644 index 0000000..492254c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_add_s8_esp32s3.S @@ -0,0 +1,638 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2023 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .align 4 + .literal_position + .literal .nudge_val, 1073741824 + + # Program Unit: esp_nn_add_elementwise_s8_esp32s3 + .type esp_nn_add_elementwise_s8_esp32s3, @function + .align 4 + .global esp_nn_add_elementwise_s8_esp32s3 + +esp_nn_add_elementwise_s8_esp32s3: # 0x4 + # temp_neg_out_shift = 0 + # temp_neg_input2_shift = 4 + # temp_neg_input1_shift = 8 + # gra_spill_temp_2 = 12 + # gra_spill_temp_3 = 16 + # gra_spill_temp_4 = 20 + # gra_spill_temp_5 = 24 + # gra_spill_temp_6 = 28 + # gra_spill_temp_7 = 32 + # gra_spill_temp_8 = 36 + # gra_spill_temp_9 = 40 + # gra_spill_temp_10 = 44 + # gra_spill_temp_11 = 48 + # gra_spill_temp_12 = 52 + # gra_spill_temp_13 = 56 + + // a2 : *input1_data + // a3 : *input2_data + // a4 : input1_offset + // a5 : input2_offset + // a6 : input1_mult + // a7 : input2_mult + // On stack: + // 80: input1_shift + // 84: input2_shift + // 88: left_shift + // 92: *output + // 96: out_offset + // 100: out_mult, loaded in `a8` + // 104: out_shift + // 108: activation_min + // 112: activation_max + // 116: size + + entry a1,80 # + s32i.n a4,a1,48 # [10] gra_spill_temp_11, input1_offset + s32i.n a5,a1,52 # [0] gra_spill_temp_12, input2_offset + s32i.n a2,a1,32 # [5] gra_spill_temp_7, input1_data + s32i.n a3,a1,12 # [3] gra_spill_temp_2, input2_data + + l32i a12,a1,116 # [11] id:720 size+0x0 + mov.n a14,a2 # [6] + mov.n a10,a3 # [8] + blti a12,1,.exit # [1] // exit + + l32i a3,a1,80 # [0] id:721 input1_shift+0x0 + l32i a13,a1,84 # [1] id:722 input2_shift+0x0 + l32i a2,a1,104 # [8] id:723 out_shift+0x0 + l32i a8,a1,100 # [1] out_mult + + neg a3,a3 # [12] + neg a13,a13 # [7] + neg a2,a2 # [11] + + s32i.n a3,a1,8 # [12] temp_neg_input1_shift, -input1_shift + s32i.n a13,a1,4 # [7] temp_neg_input2_shift, -input2_shift + s32i.n a2,a1,0 # [16] temp_neg_out_shift, -out_shift + + movi.n a5,1 + addi a9,a3,-1 + ssl a9 + sll a15,a5 + s32i.n a15,a1,16 # gra_spill_temp_3, 1 << (exponent - 1) for input1 + + addi a9,a13,-1 + ssl a9 + sll a15,a5 + s32i.n a15,a1,20 # gra_spill_temp_4, 1 << (exponent - 1) for input2 + + addi a9,a2,-1 + ssl a9 + sll a15,a5 + s32i.n a15,a1,24 # gra_spill_temp_5, 1 << (exponent - 1) for out + + movi.n a2,0 + blti a12,12,.process_leftover # [23] + + // skip to leftover routine if inputs are unaligned + or a9,a14,a10 + extui a9,a9,0,4 + bnez a9,.process_leftover + + l32i a9,a1,92 # [17] id:1279 output+0x0 + + l32i a13,a1,116 # [20] + srai a13,a13,3 # [21] + s32i.n a13,a1,56 # [22] gra_spill_temp_13 + + movi.n a13,8 + s32i.n a13,a1,28 # gra_spill_temp_6, mult_of8 counter + + ee.zero.q q6 # [8] + +.vector_loop: // process 8 values in one go + l32i a15,a1,88 # [6] left_shift + ee.vld.l.64.ip q0,a14,8 # [9] id:729 + s32i.n a9,a1,44 # [10] gra_spill_temp_10, out_ptr + s32i.n a14,a1,40 # [20] gra_spill_temp_9 + wsr.sar a15 # [21] load left shift + + addi.n a15,a1,48 # [14] + ee.vldbc.16 q7,a15 # [21] id:1277 input1_offset + ee.vcmp.lt.s8 q5,q0,q6 # [29] + ee.vzip.8 q0,q5 # [31], 20 bits + ee.vadds.s16 q0,q0,q7 # [34], add offset + ee.vcmp.lt.s16 q2,q0,q6 # [36] + ee.vzip.16 q0,q2 # [39], 32 bits + ee.vsl.32 q0,q0 # [41] left_shift + ee.vsl.32 q2,q2 # [42] left_shift + + l32r a9,.nudge_val # [15], nudge + +// mulhi32 for q0 + ee.movi.32.a q0,a3,2 # [44] + ee.movi.32.a q0,a4,3 # [45] + ee.movi.32.a q0,a14,1 # [46] + ee.movi.32.a q0,a5,0 # [62] + + mulsh a13,a6,a3 # [51] + mull a3,a6,a3 # [53] + + mulsh a12,a6,a4 # [50] + mull a4,a6,a4 # [55] + + mulsh a15,a6,a14 # [48] + mull a14,a6,a14 # [49] + + ssai 31 # [47] + + add a3,a3,a9 + saltu a2,a3,a9 + add.n a13,a13,a2 + src a13,a13,a3 + + add a4,a4,a9 + saltu a2,a4,a9 + add.n a12,a12,a2 + src a12,a12,a4 + ee.movi.32.q q0,a13,2 # [62] + + add a14,a14,a9 + saltu a2,a14,a9 + add.n a15,a15,a2 + src a15,a15,a14 + ee.movi.32.q q0,a12,3 # [62] + + mulsh a13,a6,a5 # [51] + mull a5,a6,a5 # [53] + ee.movi.32.q q0,a15,1 # [62] + + add a5,a5,a9 + saltu a2,a5,a9 + add.n a13,a13,a2 + src a13,a13,a5 + ee.movi.32.q q0,a13,0 # [62] + + +// mulhi32 for q2 + ee.movi.32.a q2,a3,2 # [44] + ee.movi.32.a q2,a4,3 # [45] + ee.movi.32.a q2,a14,1 # [46] + ee.movi.32.a q2,a5,0 # [62] + + mulsh a13,a6,a3 # [51] + mull a3,a6,a3 # [53] + + mulsh a12,a6,a4 # [50] + mull a4,a6,a4 # [55] + + mulsh a15,a6,a14 # [48] + mull a14,a6,a14 # [49] + + ssai 31 # [47] + + add a3,a3,a9 + saltu a2,a3,a9 + add.n a13,a13,a2 + src a13,a13,a3 + + add a4,a4,a9 + saltu a2,a4,a9 + add.n a12,a12,a2 + src a12,a12,a4 + ee.movi.32.q q2,a13,2 # [62] + + add a14,a14,a9 + saltu a2,a14,a9 + add.n a15,a15,a2 + src a15,a15,a14 + ee.movi.32.q q2,a12,3 # [62] + + mulsh a13,a6,a5 # [51] + mull a5,a6,a5 # [53] + ee.movi.32.q q2,a15,1 # [62] + + l32i a3,a1,8 # [12] temp_neg_input1_shift, -input1_shift + add a5,a5,a9 + saltu a2,a5,a9 + add.n a13,a13,a2 + src a13,a13,a5 + ee.movi.32.q q2,a13,0 # [62] + + + blti a3,1, .skip_div_by2_in0 + + addi.n a13,a1,16 + ee.vcmp.lt.s32 q1,q0,q6 + ee.vcmp.lt.s32 q3,q2,q6 + ee.vldbc.32 q5,a13 // 1 << (exponent - 1) + wsr.sar a3 // load right_shift + ee.vadds.s32 q0,q0,q1 // subtract 1 `if (val < 0)` + ee.vadds.s32 q2,q2,q3 // subtract 1 `if (val < 0)` + ee.vadds.s32 q0,q0,q5 + ee.vadds.s32 q2,q2,q5 + ee.vsr.32 q0,q0 + ee.vsr.32 q2,q2 + +.skip_div_by2_in0: + + + ee.vld.l.64.ip q1,a10,8 # [11] id:1290 + addi.n a15,a1,52 # [12] + ee.vldbc.16 q7,a15 # [19] id:1278 input2_offset + l32i a15,a1,88 # [6] left_shift + s32i a10,a1,36 # [14] gra_spill_temp_8 + ee.vcmp.lt.s8 q3,q1,q6 # [271] + wsr.sar a15 # [21], load shift for left shift + ee.vzip.8 q1,q3 # [274], 20 bits + ee.vadds.s16 q1,q1,q7 # [281] + ee.vcmp.lt.s16 q3,q1,q6 # [282] + ee.vzip.16 q1,q3 # [283], 32 bits + ee.vsl.32 q1,q1 # [284] + ee.vsl.32 q3,q3 # [285] + + +// mulhi32 for q1 + ee.movi.32.a q1,a3,2 # [44] + ee.movi.32.a q1,a4,3 # [45] + ee.movi.32.a q1,a14,1 # [46] + ee.movi.32.a q1,a5,0 # [62] + + mulsh a13,a7,a3 # [51] + mull a3,a7,a3 # [53] + + mulsh a12,a7,a4 # [50] + mull a4,a7,a4 # [55] + + mulsh a15,a7,a14 # [48] + mull a14,a7,a14 # [49] + + ssai 31 # [47] + + add a3,a3,a9 + saltu a2,a3,a9 + add.n a13,a13,a2 + src a13,a13,a3 + + add a4,a4,a9 + saltu a2,a4,a9 + add.n a12,a12,a2 + src a12,a12,a4 + ee.movi.32.q q1,a13,2 # [62] + + add a14,a14,a9 + saltu a2,a14,a9 + add.n a15,a15,a2 + src a15,a15,a14 + ee.movi.32.q q1,a12,3 # [62] + + mulsh a13,a7,a5 # [51] + mull a5,a7,a5 # [53] + ee.movi.32.q q1,a15,1 # [62] + + add a5,a5,a9 + saltu a2,a5,a9 + add.n a13,a13,a2 + src a13,a13,a5 + ee.movi.32.q q1,a13,0 # [62] + + +// mulhi32 for q3 + ee.movi.32.a q3,a3,2 # [44] + ee.movi.32.a q3,a4,3 # [45] + ee.movi.32.a q3,a14,1 # [46] + ee.movi.32.a q3,a5,0 # [62] + + mulsh a13,a7,a3 # [51] + mull a3,a7,a3 # [53] + + mulsh a12,a7,a4 # [50] + mull a4,a7,a4 # [55] + + mulsh a15,a7,a14 # [48] + mull a14,a7,a14 # [49] + + ssai 31 # [47] + + add a3,a3,a9 + saltu a2,a3,a9 + add.n a13,a13,a2 + src a13,a13,a3 + + add a4,a4,a9 + saltu a2,a4,a9 + add.n a12,a12,a2 + src a12,a12,a4 + ee.movi.32.q q3,a13,2 # [62] + + add a14,a14,a9 + saltu a2,a14,a9 + add.n a15,a15,a2 + src a15,a15,a14 + ee.movi.32.q q3,a12,3 # [62] + + mulsh a13,a7,a5 # [51] + mull a5,a7,a5 # [53] + ee.movi.32.q q3,a15,1 # [62] + l32i a14,a1,4 # [7] temp_neg_input2_shift, -input2_shift + + add a5,a5,a9 + saltu a2,a5,a9 + add.n a13,a13,a2 + src a13,a13,a5 + ee.movi.32.q q3,a13,0 # [62] + + // multiplication results: q0-q2 & q1-q3 + + + blti a14,1, .skip_div_by2_in1 + + addi.n a5,a1,20 + ee.vcmp.lt.s32 q4,q1,q6 + ee.vcmp.lt.s32 q5,q3,q6 + ee.vldbc.32 q7,a5 // 1 << (exponent - 1) + wsr.sar a14 // load right_shift + ee.vadds.s32 q4,q4,q7 // subtract 1 `if (val < 0)` + ee.vadds.s32 q5,q5,q7 // subtract 1 `if (val < 0)` + ee.vadds.s32 q1,q1,q4 + ee.vadds.s32 q3,q3,q5 + ee.vsr.32 q1,q1 + ee.vsr.32 q3,q3 + +.skip_div_by2_in1: + + ee.vadds.s32 q0,q0,q1 + ee.vadds.s32 q1,q2,q3 + +// mulhi32 for q0 + ee.movi.32.a q0,a3,2 # [44] + ee.movi.32.a q0,a4,3 # [45] + ee.movi.32.a q0,a14,1 # [46] + ee.movi.32.a q0,a5,0 # [62] + + mulsh a13,a8,a3 # [51] + mull a3,a8,a3 # [53] + + mulsh a12,a8,a4 # [50] + mull a4,a8,a4 # [55] + + mulsh a15,a8,a14 # [48] + mull a14,a8,a14 # [49] + + ssai 31 # [47] + + add a3,a3,a9 + saltu a2,a3,a9 + add.n a13,a13,a2 + src a13,a13,a3 + + add a4,a4,a9 + saltu a2,a4,a9 + add.n a12,a12,a2 + src a12,a12,a4 + ee.movi.32.q q0,a13,2 # [62] + + add a14,a14,a9 + saltu a2,a14,a9 + add.n a15,a15,a2 + src a15,a15,a14 + ee.movi.32.q q0,a12,3 # [62] + + mulsh a13,a8,a5 # [51] + mull a5,a8,a5 # [53] + ee.movi.32.q q0,a15,1 # [62] + + add a5,a5,a9 + saltu a2,a5,a9 + add.n a13,a13,a2 + src a13,a13,a5 + ee.movi.32.q q0,a13,0 # [62] + + +// mulhi32 for q1 + ee.movi.32.a q1,a3,2 # [44] + ee.movi.32.a q1,a4,3 # [45] + ee.movi.32.a q1,a14,1 # [46] + ee.movi.32.a q1,a5,0 # [62] + + mulsh a13,a8,a3 # [51] + mull a3,a8,a3 # [53] + + mulsh a12,a8,a4 # [50] + mull a4,a8,a4 # [55] + + mulsh a15,a8,a14 # [48] + mull a14,a8,a14 # [49] + + ssai 31 # [47] + + add a3,a3,a9 + saltu a2,a3,a9 + add.n a13,a13,a2 + src a13,a13,a3 + + add a4,a4,a9 + saltu a2,a4,a9 + add.n a12,a12,a2 + src a12,a12,a4 + ee.movi.32.q q1,a13,2 # [62] + + add a14,a14,a9 + saltu a2,a14,a9 + add.n a15,a15,a2 + src a15,a15,a14 + ee.movi.32.q q1,a12,3 # [62] + + mulsh a13,a8,a5 # [51] + mull a5,a8,a5 # [53] + ee.movi.32.q q1,a15,1 # [62] + l32i a14,a1,0 # [738] temp_neg_out_shift, -out_shift + + add a5,a5,a9 + saltu a2,a5,a9 + add.n a13,a13,a2 + src a13,a13,a5 + ee.movi.32.q q1,a13,0 # [62] + + + //q0-q1 has output + + blti a14,1,.skip_div_by2_out + addi.n a5,a1,24 + ee.vcmp.lt.s32 q2,q0,q6 + ee.vcmp.lt.s32 q3,q1,q6 + ee.vldbc.32 q5,a5 // 1 << (exponent - 1) + wsr.sar a14 // load right shift + ee.vadds.s32 q0,q0,q2 // subtract 1 `if (val < 0)` + ee.vadds.s32 q1,q1,q3 // subtract 1 `if (val < 0)` + ee.vadds.s32 q0,q0,q5 + ee.vadds.s32 q1,q1,q5 + ee.vsr.32 q0,q0 + ee.vsr.32 q1,q1 + +.skip_div_by2_out: + +// add offset and apply activation + addi a15,a1,96 + ee.vldbc.32 q3,a15 # [809] id:802 out_offset + ee.vadds.s32 q0,q0,q3 # [811] + ee.vadds.s32 q1,q1,q3 # [812] + addi a13,a1,108 + addi a14,a1,112 + ee.vldbc.32 q3,a14 # [813] id:803 activation_max + ee.vmin.s32 q0,q0,q3 # [815] + ee.vmin.s32 q1,q1,q3 # [816] + ee.vldbc.32 q3,a13 # [817] id:804 activation_min + l32i a13,a1,4 # [818] temp_neg_input2_shift + ee.vmax.s32 q1,q1,q3 # [819] + ee.vmax.s32 q0,q0,q3 # [820] + +//pack the data and store + l32i.n a9,a1,44 # [784] gra_spill_temp_10 + ee.vunzip.16 q0,q1 # [821] + ee.vunzip.8 q0,q1 # [822] + l32i.n a13,a1,28 # gra_spill_temp_6, multiple of 12 index + ee.vst.l.64.ip q0,a9,8 # [823] id:805 + l32i a15,a1,116 # [1], size + l32i.n a14,a1,40 # [20] gra_spill_temp_9 + l32i.n a10,a1,36 # [14] gra_spill_temp_8 + addi a13,a13,8 + s32i.n a13,a1,28 # gra_spill_temp_6 + bge a15,a13,.vector_loop + + l32i.n a2,a1,56 # [0] gra_spill_temp_13 + +// check for leftover + l32i a10,a1,116 # [1] + slli a2,a2,3 # [2] + bge a2,a10,.exit # [3] // done, exit + +.process_leftover: + l32i.n a3,a1,48 # [1] gra_spill_temp_11 + l32i.n a12,a1,52 # [2] gra_spill_temp_12 + + l32i.n a10,a1,12 # [3] gra_spill_temp_2 + l32i.n a14,a1,32 # [8] gra_spill_temp_7 + add.n a10,a2,a10 # [5] + add.n a14,a2,a14 # [6] + l8ui a14,a14,0 # [7] id:809, input1 + l8ui a10,a10,0 # [12] id:1370, input2 + + sext a14,a14,7 # [9] + sext a10,a10,7 # [10] + add.n a10,a10,a12 # [11] // add offset2 + add.n a14,a14,a3 # [16] // add offset1 + l32i a12,a1,88 # [13] left_shift + + // sat_round_doubling_high_mul step for input1 and input2 + ssl a12 # [15] + sll a10,a10 # [20] + sll a14,a14 # [17] + + l32r a12,.nudge_val # [0], nudge + + // a13,a3 are free, a12: nudge, a6:mult1 + mulsh a13,a14,a6 + mull a9,a14,a6 + ssai 31 + + add a9,a9,a12 + saltu a3,a9,a12 + add.n a13,a13,a3 + src a14,a13,a9 //result in a14 + + mulsh a13,a10,a7 + mull a9,a10,a7 + ssai 31 + + add a9,a9,a12 + saltu a3,a9,a12 + add.n a13,a13,a3 + src a10,a13,a9 //result in a10 + +// divide_by_power_of2_step for input1 (a14), input2 (a10) +// free registers: a13, a12, a9, a3 + + l32i.n a12,a1,8 // -input1_shift + l32i.n a13,a1,4 // -input2_shift + + blti a12,1,.skip_div_by2_in0_remain + l32i.n a3,a1,16 // 1 << (exponent - 1) + extui a9,a14,31,1 + ssr a12 // load right_shift + sub a3,a3,a9 // 1 << (exponent - 1) - (val < 0) + add a14,a14,a3 + sra a14,a14 +.skip_div_by2_in0_remain: + + blti a13,1,.skip_div_by2_in1_remain + l32i.n a3,a1,20 // 1 << (exponent - 1) + extui a9,a10,31,1 + ssr a13 // load right_shift + sub a3,a3,a9 // 1 << (exponent - 1) - (val < 0) + add a10,a10,a3 + sra a10,a10 +.skip_div_by2_in1_remain: + +// process output + l32r a12,.nudge_val # [0], nudge + l32i a13,a1,0 // -out_shift + add.n a10,a10,a14 # [45] + +// multiply and pick high32 + mulsh a3,a10,a8 + mull a10,a10,a8 + ssai 31 # [0] + add a10,a10,a12 + saltu a9,a10,a12 + add a12,a3,a9 + src a12,a12,a10 + +// div by power of 2 for output + + l32i a9,a1,96 # [31] out_offset + blti a13,1,.skip_div_by2_out_remain + l32i.n a3,a1,24 // 1 << (exponent - 1) + extui a14,a12,31,1 + ssr a13 // load right_shift + sub a3,a3,a14 // 1 << (exponent - 1) - (val < 0) + add a12,a12,a3 + sra a12,a12 +.skip_div_by2_out_remain: + +// add offset + add.n a9,a9,a12 # [33] + +// apply activation + l32i a13,a1,112 # [34] activation_max + l32i a12,a1,108 # [35] activation_min + min a13,a13,a9 # [36] + l32i a9,a1,92 # [37] output + max a13,a13,a12 # [38] + add.n a9,a2,a9 # [39] + s8i a13,a9,0 # [40] id:1371 + l32i a12,a1,116 + addi.n a2,a2,1 # [41] + blt a2,a12,.process_leftover + +.exit: + retw.n # [0] + + .size esp_nn_add_elementwise_s8_esp32s3, . - esp_nn_add_elementwise_s8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_mul_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_mul_ansi.c new file mode 100644 index 0000000..477d5c6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_mul_ansi.c @@ -0,0 +1,46 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include + +void esp_nn_mul_elementwise_s8_ansi(const int8_t *input1_data, + const int8_t *input2_data, + const int32_t input1_offset, + const int32_t input2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t activation_min, + const int32_t activation_max, + const int32_t size) +{ + for (int i = 0; i < size; i++) { + int32_t tmp1 = input1_data[i] + input1_offset; + int32_t tmp2 = input2_data[i] + input2_offset; + + int32_t out = tmp1 * tmp2; + out = esp_nn_multiply_by_quantized_mult(out, out_mult, out_shift); + out = out + out_offset; + + out = max(activation_min, min(out, activation_max)); + output[i] = (int8_t) out; + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_mul_s8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_mul_s8_esp32s3.S new file mode 100644 index 0000000..ca28573 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/basic_math/esp_nn_mul_s8_esp32s3.S @@ -0,0 +1,323 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2023 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .align 4 + .literal_position + .literal .LC0_26_123, 1073741824 // `1 << 30` + + # Program Unit: esp_nn_mul_elementwise_s8_esp32s3 + .type esp_nn_mul_elementwise_s8_esp32s3, @function + .align 4 + .global esp_nn_mul_elementwise_s8_esp32s3 + +esp_nn_mul_elementwise_s8_esp32s3: # 0x4 + # to_add = 0 + # gra_spill_temp_0 = 4 + # gra_spill_temp_1 = 8 + # gra_spill_temp_2 = 12 + # gra_spill_temp_3 = 16 + # gra_spill_temp_4 = 20 + # gra_spill_temp_5 = 24 + # gra_spill_temp_6 = 28 + # gra_spill_temp_7 = 32 + # gra_spill_temp_8 = 36 + # gra_spill_temp_<> = 40 + # gra_spill_temp_<> = 44 + # gra_spill_temp_<> = 48 + # gra_spill_temp_13 = 64 + + // registers: + // a2: const int8_t *input1_data + // a3: const int8_t *input2_data + // a4: const int32_t input1_offset + // a5: const int32_t input2_offset + // a6: int8_t *output + // a7: const int32_t out_offset + + // on stack: + // 120: const int32_t out_mult + // 124: const int32_t out_shift + // 128: const int32_t activation_min + // 132: const int32_t activation_max + // 136: const int32_t size + + entry a1,120 # + s32i.n a4,a1,24 # [0] gra_spill_temp_5, input1_offset + s32i.n a5,a1,28 # [1] gra_spill_temp_12, input2_offset + + s32i.n a3,a1,4 # [5] gra_spill_temp_0, input2 + mov.n a10,a3 # [6] + l32i a3,a1,136 # [18] id:361 size+0x0 + mov.n a9,a6 # [2] // out_addr + blti a3,1,.exit # [0] // exit + + s32i.n a2,a1,16 # [9] gra_spill_temp_3, input1 + s32i a7,a1,40 # [4] id:358 out_offset+0x0 + movi.n a11,0 # [3] + mov.n a12,a2 # [10] + s32i a4,a1,44 # [13] id:356 input1_offset+0x0 + s32i a5,a1,48 # [14] id:357 input2_offset+0x0 + movi.n a2,1 # [15] + + l32i a15,a1,124 # [3] id:362 out_shift+0x0 + l32i a13,a1,120 # [4] id:363 out_mult+0x0 + s32i.n a6,a1,8 # [1] gra_spill_temp_1, out_addr + max a14,a15,a11 # [11] left_shift + sub a4,a14,a15 # right_shift + s32i.n a4,a1,20 # [9] gra_spill_temp_4 + + blti a3,8,.process_leftover # [20] + + // skip to leftover routine if inputs are unaligned + or a6,a12,a10 + extui a6,a6,0,4 + bnez a6,.process_leftover + + // `size > 8`, s3 optimisation path... + ee.zero.q q1 # [0] + addi a4,a1,44 # [7] + addi a8,a1,48 # [8] + ee.vldbc.16 q0,a4 # [17] id:359 input1_offset + ee.vldbc.16 q7,a8 # [16] id:360 input2_offset + l32r a4,.LC0_26_123 # [12] + movi a8, 8 + st.qr q0,a1,64 # [19] gra_spill_temp_13 + s32i.n a8,a1,12 # [6] gra_spill_temp_2 + +.Lt_0_7682: # 0x60 + s32i a9,a1,36 # [1] gra_spill_temp_8, out_addr + ld.qr q4,a1,64 # [2] gra_spill_temp_13, input1_offset + ee.vld.l.64.ip q2,a12,8 # [4] id:367, input1_ptr + movi.n a7,16 # [3] + ee.vld.h.64.ip q2,a10,8 # [5] id:368, input2_ptr + wsr.sar a7 # [6] + ee.vcmp.lt.s8 q5,q2,q1 # [7] + ee.vzip.8 q2,q5 # [8] + ee.vadds.s16 q5,q5,q7 # [9] input2_offset + ee.vadds.s16 q4,q2,q4 # [10] input1_offset + ee.vmul.s16 q3,q4,q5 # [11] + wsr.sar a11 # [12] + ee.vmul.s16 q2,q4,q5 # [13] + + wsr.sar a14 # [14] left_shift + ee.vzip.16 q2,q3 # [15] + ee.vsl.32 q6,q2 # [16] left_shift + ssai 31 # [17] + + ee.movi.32.a q6,a3,2 # [18] + ee.movi.32.a q6,a8,3 # [26] + + mulsh a6,a13,a3 # [19] + mull a3,a13,a3 # [20] + mulsh a7,a13,a8 # [27] + add.n a3,a4,a3 # [22] + saltu a2,a3,a4 # [23] + add.n a2,a2,a6 # [24] + src a2,a2,a3 # [25] + + mull a6,a13,a8 # [28] + add.n a6,a4,a6 # [30] + saltu a9,a6,a4 # [31] + add.n a9,a9,a7 # [32] + src a9,a9,a6 # [33] + ee.movi.32.q q2,a2,2 # [53] + ee.movi.32.q q2,a9,3 # [54] + + ee.movi.32.a q6,a6,1 # [34] + mulsh a7,a13,a6 # [35] + mull a6,a13,a6 # [36] + add.n a6,a4,a6 # [38] + saltu a3,a6,a4 # [39] + add.n a3,a3,a7 # [16] + src a3,a3,a6 # [41] + ee.movi.32.a q6,a2,0 # [42] + mulsh a8,a13,a2 # [43] + mull a7,a13,a2 # [4] + add.n a7,a4,a7 # [46] + saltu a6,a7,a4 # [47] + add.n a6,a6,a8 # [24] + src a6,a6,a7 # [49] + ee.movi.32.q q2,a3,1 # [28] + ee.movi.32.q q2,a6,0 # [50] + + wsr.sar a14 # [10] + ee.vsl.32 q4,q3 # [11] + ee.movi.32.a q4,a2,2 # [13] + mulsh a3,a13,a2 # [14] + mull a2,a13,a2 # [15] + ssai 31 # [12] + add.n a2,a4,a2 # [17] + saltu a5,a2,a4 # [18] + add.n a5,a5,a3 # [19] + src a5,a5,a2 # [20] + ee.movi.32.a q4,a3,3 # [21] + mulsh a6,a13,a3 # [22] + mull a3,a13,a3 # [23] + add.n a3,a4,a3 # [25] + saltu a8,a3,a4 # [26] + add.n a8,a8,a6 # [27] + src a8,a8,a3 # [28] + ee.movi.32.q q0,a5,2 # [24] + ee.movi.32.q q0,a8,3 # [51] + + ee.movi.32.a q4,a7,1 # [29] + mulsh a6,a13,a7 # [30] + mull a3,a13,a7 # [31] + add.n a3,a4,a3 # [33] + saltu a2,a3,a4 # [34] + add.n a2,a2,a6 # [35] + src a2,a2,a3 # [36] + ee.movi.32.a q4,a6,0 # [37] + mulsh a7,a13,a6 # [38] + mull a6,a13,a6 # [39] + add.n a6,a4,a6 # [41] + saltu a3,a6,a4 # [42] + add.n a3,a3,a7 # [43] + src a3,a3,a6 # [4] + ee.movi.32.q q0,a2,1 # [47] + ee.movi.32.q q0,a3,0 # [46] + + l32i.n a5,a1,20 # [0] gra_spill_temp_4, right_shift + movi.n a7,1 # [51] + + blti a5,1,.skip_div_by_pow_of_2 +// divide by power of 2 + ee.vcmp.lt.s32 q5,q2,q1 # [56] + ee.vcmp.lt.s32 q6,q0,q1 # [28] + + addi.n a8,a5,-1 # [1] + ssl a8 # [2] + sll a7,a7 # [3] + s32i.n a7,a1,0 # [4] to_add + ee.vldbc.32 q4,a1 # [5] id:376 to_add + + wsr.sar a5 # [6] + ee.vadds.s32 q5,q4,q5 # [7] + ee.vadds.s32 q5,q2,q5 # [8] + ee.vsr.32 q2,q5 # [9] + + wsr.sar a5 # [5] + ee.vadds.s32 q5,q4,q6 # [9] + ee.vadds.s32 q5,q0,q5 # [11] + ee.vsr.32 q0,q5 # [12] +.skip_div_by_pow_of_2: + +// add offset, apply activation + addi a8,a1,132 # [54] + ee.vldbc.32 q4,a8 # [55] id:385 activation_max + addi a5,a1,40 # [8] + ee.vldbc.32 q6,a5 # [10] id:384 out_offset + addi a7,a1,128 # [4] + ee.vadds.s32 q0,q0,q6 # [13] // add out_offset + ee.vadds.s32 q2,q2,q6 # [14] // add out_offset + ee.vldbc.32 q6,a7 # [16] id:386 activation_min + ee.vmin.s32 q0,q0,q4 # [17] + ee.vmin.s32 q2,q2,q4 # [15] + ee.vmax.s32 q0,q0,q6 # [18] + ee.vmax.s32 q2,q2,q6 # [19] + +// pack and store + ee.vunzip.16 q2,q0 # [20] + ee.vunzip.8 q2,q0 # [21] + l32i.n a7,a1,12 // count + l32i a9,a1,36 # [55] gra_spill_temp_8 + l32i.n a3,a1,136 # [1] , size + ee.vst.l.64.ip q2,a9,8 # [22] id:387 + addi a7,a7,8 + s32i.n a7,a1,12 // increment count + bge a3,a7,.Lt_0_7682 + + addi a11,a7,-8 + bge a11,a3,.exit # [3] // exit + +.process_leftover: + sub a8,a3,a11 # [1] + loopgtz a8,.LBB33_esp_nn_mul_elementwise_s8_esp32s3 # [9] + + ssl a14 # [0] left_shift + l32i.n a8,a1,24 # [1] gra_spill_temp_5, input1_offset + l32i.n a10,a1,4 # [2] gra_spill_temp_0, input2 + l32i.n a12,a1,16 # [3] gra_spill_temp_3, input1 + add.n a10,a11,a10 # [4], input2 + add.n a12,a11,a12 # [5], input1 + l8ui a12,a12,0 # [6] id:390 + l8ui a10,a10,0 # [7] id:391 + sext a12,a12,7 # [8] + add.n a12,a12,a8 # [9] + l32i.n a8,a1,28 # [10] gra_spill_temp_12, input2_offset + sext a10,a10,7 # [11] + add.n a10,a10,a8 # [12] + mull a10,a12,a10 # [13] // multiplication result + +// multiply by quantised mult + l32i.n a9,a1,20 # [0] gra_spill_temp_4, load right_shift + + sll a10,a10 # [15] // left shift + + mulsh a3,a10,a13 # [1] + mull a8,a10,a13 # [6] + ssai 31 # [0] + add.n a6,a8,a4 # [8] + saltu a8,a6,a8 # [9] + add.n a8,a8,a3 # [10] + src a3,a8,a6 # [19] // result + + blti a9, 1, .skip_div_by_pow_of_2_remains +// divide by power of 2 + // calculate to_add = `1 << (exponent - 1)` + addi a6,a9,-1 + ssl a6 # [23] + movi a7,1 + sll a7,a7 // to_add + + extui a8,a3,31,1 # [24], sign + add a3,a3,a8 // add sign + add a3,a3,a7 // add to_add + + ssr a9 # [20] load right_shift + sra a3,a3 // right shift +.skip_div_by_pow_of_2_remains: + + l32i.n a6,a1,40 # [32], out_offset + l32i.n a8,a1,132 # [35], act_max + l32i.n a7,a1,128 # [36], act_min + +// add offset and apply activation + add.n a3,a3,a6 # [34], offset added + min a8,a8,a3 # [37] + l32i.n a3,a1,8 # [38] gra_spill_temp_1, load base out_addr + max a8,a8,a7 # [39] + +// store + add.n a3,a11,a3 # [16], add index from `a11` + s8i a8,a3,0 # [41] id:392 // store + addi.n a11,a11,1 # [42] // inc index + +.LBB33_esp_nn_mul_elementwise_s8_esp32s3: # 0x2ed +.exit: + retw.n # [0] + + .size esp_nn_mul_elementwise_s8_esp32s3, . - esp_nn_mul_elementwise_s8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/common_functions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/common_functions.h new file mode 100644 index 0000000..1158e9b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/common_functions.h @@ -0,0 +1,255 @@ +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include + +/** + * c99 standard still doesn't strictly inline functions + * We need to use attribute as well to do this. + */ +#define __NN_FORCE_INLINE__ __attribute((always_inline)) static inline + +/* min/max macros */ +#ifndef max +#define max(a, b) ({ \ + __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a > _b ? _a : _b; \ +}) + +#define min(a, b) ({ \ + __typeof__ (a) _a = (a); \ + __typeof__ (b) _b = (b); \ + _a < _b ? _a : _b; \ +}) +#endif + +__NN_FORCE_INLINE__ int32_t esp_nn_clz32(uint32_t in) +{ +#if CONFIG_IDF_TARGET_ARCH_XTENSA + __asm__ volatile("nsau %0, %0" : "+r" (in)); + return in; +#elif defined(__GNUC__) + return __builtin_clz(in); +#else + int32_t count = 32; + uint32_t x = in, y = in >> 16; + if (y != 0) { + count -= 16; + x = y; + } + y = x >> 8; + if (y != 0) { + count -= 8; + x = y; + } + y = x >> 4; + if (y != 0) { + count -= 4; + x = y; + } + y = x >> 2; + if (y != 0) { + count -= 2; + x = y; + } + y = x >> 1; + if (y != 0) { + return count - 2; + } + return count - x; +#endif +} + +/** + * Signed saturate a 32 bit value to 8 bits keeping output in 32 bit variable. + */ +__NN_FORCE_INLINE__ int32_t esp_nn_saturate8(int32_t in) +{ +#if CONFIG_IDF_TARGET_ARCH_XTENSA + __asm__ volatile("clamps %0, %0, 7" : "+a"(in)); + return in; +#else + return max(INT8_MIN, min(in, INT8_MAX)); +#endif +} + +__NN_FORCE_INLINE__ int32_t esp_nn_pick_sat_high32_of64(int64_t val64) +{ + int32_t sign = (int32_t) (val64 >> 63); + int32_t to_add = sign & ((1ul << 31) - 1); + return (int32_t) ((int64_t) (val64 + to_add) >> 31); +} + +__NN_FORCE_INLINE__ int32_t esp_nn_sat_round_doubling_high_mul(int32_t in0, int32_t in1) +{ + int32_t result; + int64_t in0_64 = (int64_t) in0; + bool overflow = (in0 == in1) && (in0 == (int32_t) INT32_MIN); + + /* Nudge value */ + int64_t nudge_val = 1 << 30; + if ((in0 < 0) ^ (in1 < 0)) { + nudge_val = 1 - nudge_val; + } + + /* Multiply and add nudge */ + int64_t mult = in0_64 * in1 + nudge_val; + + /* Round and pickup 32 bits */ + result = esp_nn_pick_sat_high32_of64(mult); + + return overflow ? INT32_MAX : result; +} + +/** + * fast version + * this will fail for values closer to INT32_MAX and INT32_MIN by `1 << (exponent - 1)`. + * We can afford to do this because we are at the very last stage of filter. + * Also it is pretty rare condition as our output is going to be 8 bit. + */ +__NN_FORCE_INLINE__ int32_t esp_nn_div_by_power_of_two_fast(int32_t val, int32_t exponent) +{ + int32_t to_add = (1 << (exponent - 1)) - (val < 0); + return (int32_t) ((val + to_add) >> exponent); +} + +__NN_FORCE_INLINE__ int32_t esp_nn_div_by_power_of_two(int32_t val, int32_t exponent) +{ + int32_t result; + + const int32_t mask = (1 << exponent) - 1; + const int32_t remainder = val & mask; + + result = val >> exponent; + int32_t threshold = (mask >> 1) + (result < 0); + + if (remainder > threshold) { + result += 1; + } + return result; +} + +__NN_FORCE_INLINE__ int32_t esp_nn_multiply_by_quantized_mult(int32_t x, int32_t mult, int32_t shift) +{ + int32_t left_shift = shift > 0 ? shift : 0; + int32_t right_shift = shift > 0 ? 0 : -shift; + int32_t result = esp_nn_sat_round_doubling_high_mul(x * (1 << left_shift), mult); + return esp_nn_div_by_power_of_two(result, right_shift); +} + +__NN_FORCE_INLINE__ int32_t esp_nn_multiply_by_quantized_mult_fast(int32_t x, int32_t mult, int32_t shift) +{ + int32_t left_shift = max(shift, 0); + int32_t right_shift = left_shift - shift; + + int64_t nudge_val = 1 << 30; + int64_t in0_64 = (int64_t) (x << left_shift); + + /* Multiply and add nudge */ + int64_t mult_64 = in0_64 * mult + nudge_val; + int32_t result = (int32_t) (mult_64 >> 31); + if (right_shift) { + result = esp_nn_div_by_power_of_two_fast(result, right_shift); + } + return result; +} + +static void esp_nn_aligned_s8_pad_with_value(const int8_t *src, int8_t *dst, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const int32_t pad_val, + const uint16_t pad_wd, + const uint16_t pad_ht) +{ + /* memset with pad_val */ + memset(dst, pad_val, ((input_wd + 2 * pad_wd) * (input_ht + 2 * pad_ht)) * channels); + dst += (pad_wd + input_wd + pad_wd) * pad_ht * channels; + + for (int i = 0; i < input_ht; i++) { + dst += pad_wd * channels; + for (int j = 0; j < input_wd * channels; j++) { + *dst++ = *src++; + } + dst += pad_wd * channels; + } +} + +static void esp_nn_aligned_s8_pad_end_with_value(const int8_t *src, int8_t *dst, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const int32_t pad_val, + const uint16_t pad_wd, + const uint16_t pad_ht) +{ + for (int i = 0; i < input_ht; i++) { + for (int j = 0; j < input_wd * channels; j++) { + *dst++ = *src++; + } + if (pad_wd) { + memset(dst, pad_val, pad_wd * channels); + dst += pad_wd * channels; + } + } + /* pad end `pad_ht` lines at end */ + if (pad_ht) { + memset(dst, pad_val, (input_wd + pad_wd) * pad_ht * channels); + } +} + +/** + * @brief convert 8 bit input data to 16 bit + * + * @param src int8_t source data + * @param dst int16_t dst data + * @param size length of data + * @param offset offset to be added to src data. Range: [-128, 127] + */ +__NN_FORCE_INLINE__ void esp_nn_s8_to_s16_with_offset(const int8_t *src, int16_t *dst, + const int size, const int32_t offset) +{ + int i = 0; + for (; i < size; i += 2) { + dst[i + 0] = src[i + 0] + offset; + dst[i + 1] = src[i + 1] + offset; + } + if(i < size) { + dst[i] = src[i] + offset; + } +} + +/** + * @brief convert 8 bit input data to 16 bit + * + * @param src int8_t source data + * @param dst int16_t dst data + * @param size length of data + */ +__NN_FORCE_INLINE__ void esp_nn_s8_to_s16(const int8_t *src, int16_t *dst, const int size) +{ + int i = 0; + for (; i < size; i += 2) { + dst[i + 0] = src[i + 0]; + dst[i + 1] = src[i + 1]; + } + if(i < size) { + dst[i] = src[i]; + } +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_common_functions_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_common_functions_esp32s3.S new file mode 100644 index 0000000..68d1086 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_common_functions_esp32s3.S @@ -0,0 +1,266 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + + # Program Unit: esp_nn_aligned_s8_to_s16_with_offset_esp32s3 + .type esp_nn_aligned_s8_to_s16_with_offset_esp32s3, @function + .align 4 + .global esp_nn_aligned_s8_to_s16_with_offset_esp32s3 + +esp_nn_aligned_s8_to_s16_with_offset_esp32s3: # 0x30d + + entry a1,48 # + mov.n a10,a2 # // src + mov.n a9,a3 # // dst + mov.n a8,a4 # // size + s32i.n a5,a1,12 # [3] // offset + addi.n a2,a1,12 # [4] + + blti a4,32,.Lt_2_6402 # [5] if (size < 32) goto unopt + + addi.n a6,a8,-1 # [0] + ee.zero.q q5 # [1] + ee.vldbc.16 q4,a2 # [2] id:136 offset + mov.n a3,a10 # [3] + mov.n a2,a9 # [4] + ee.vld.128.ip q0,a3,16 # [5] id:137 + ee.vld.128.ip q1,a3,16 # [6] id:138 + ee.vcmp.lt.s8 q2,q0,q5 # [7] + ee.vzip.8 q0,q2 # [8] + ee.vadds.s16 q0,q0,q4 # [9] + ee.vadds.s16.st.incp q0,a2,q0,q2,q4 # [10] id:139 + blti a4,64,.Lt_2_7170 # [11] + + addi a5,a4,-32 # [0] + srai a5,a5,5 # [1] + slli a4,a5,5 # [2] + loopgtz a5,.LBB37_esp_nn_aligned_s8_to_s16_with_offset_esp32s3 # [3] + + ee.vst.128.ip q0,a2,16 # [0*II+0] id:140 + ee.vcmp.lt.s8 q0,q1,q5 # [0*II+1] + ee.vzip.8 q1,q0 # [0*II+2] + ee.vadds.s16.ld.incp q2,a3,q3,q1,q4 # [0*II+3] id:141 + ee.vadds.s16.st.incp q3,a2,q0,q0,q4 # [0*II+4] id:142 + ee.vcmp.lt.s8 q3,q2,q5 # [0*II+5] + ee.vst.128.ip q0,a2,16 # [0*II+6] id:143 + ee.vzip.8 q2,q3 # [0*II+7] + ee.vadds.s16.ld.incp q1,a3,q0,q2,q4 # [0*II+8] id:144 + ee.vadds.s16.st.incp q0,a2,q0,q3,q4 # [0*II+9] id:145 + +.LBB37_esp_nn_aligned_s8_to_s16_with_offset_esp32s3: # 0x36d + addi a4,a4,32 # [0] + +.Lt_2_3842: # 0x370 + ee.vst.128.ip q0,a2,16 # [0] id:146 + ee.vcmp.lt.s8 q2,q1,q5 # [1] + ee.vzip.8 q1,q2 # [2] + ee.vadds.s16 q2,q2,q4 # [3] + ee.vadds.s16 q3,q1,q4 # [4] + ee.vst.128.ip q3,a2,16 # [5] id:147 + ee.vst.128.ip q2,a2,16 # [6] id:148 + bge a4,a6,.Lt_2_4866 # [7] + + l32i.n a5,a1,12 # [0] id:135 offset+0x0 + +.Lt_2_5122: # 0x38a + mov.n a11,a4 # [0] + add.n a2,a4,a10 # [1] + # 576 dst[i + 0] = src[i + 0] + offset; + l8ui a7,a2,0 # [2] id:149 + addx2 a6,a4,a9 # [3] + sext a7,a7,7 # [4] + add.n a7,a7,a5 # [5] + s16i a7,a6,0 # [6] id:150 + # 577 dst[i + 1] = src[i + 1] + offset; + l8ui a3,a2,1 # [7] id:151 + sub a7,a8,a4 # [8] + addi.n a2,a2,2 # [9] + srai a7,a7,1 # [10] + sext a3,a3,7 # [11] + add.n a3,a3,a5 # [12] + s16i a3,a6,2 # [13] id:152 + addi.n a3,a7,-1 # [14] + loopgtz a3,.LBB52_esp_nn_aligned_s8_to_s16_with_offset_esp32s3 # [15] + + l8ui a3,a2,0 # [0*II+0] id:149 + addi.n a6,a6,4 # [1*II+1] + sext a3,a3,7 # [0*II+2] + add.n a3,a3,a5 # [0*II+3] + s16i a3,a6,0 # [0*II+4] id:150 + l8ui a3,a2,1 # [0*II+5] id:151 + addi.n a2,a2,2 # [0*II+6] + sext a3,a3,7 # [0*II+7] + add.n a3,a3,a5 # [0*II+8] + s16i a3,a6,2 # [0*II+9] id:152 + +.LBB52_esp_nn_aligned_s8_to_s16_with_offset_esp32s3: # 0x3ce + addx2 a4,a7,a11 # [0] + +.Lt_2_4866: # 0x3d1 + bge a4,a8,.Lt_2_7682 # [0] + + # 580 dst[i] = src[i] + offset; + addx2 a11,a4,a9 # [0] + add.n a8,a4,a10 # [1] + l8ui a8,a8,0 # [2] id:153 + l32i.n a12,a1,12 # [3] id:135 offset+0x0 + sext a8,a8,7 # [4] + add.n a8,a8,a12 # [5] + s16i a8,a11,0 # [6] id:154 + retw.n # [7] + +.Lt_2_6402: # 0x3e8 + blti a4,2,.Lt_2_6658 # [0] + + movi.n a4,0 # [0] + j .Lt_2_5122 # [1] + +.Lt_2_7682: # 0x3f0 + retw.n # [0] + +.Lt_2_6658: # 0x3f2 + blti a4,1,.Lt_2_7682 # [0] + + l8ui a11,a10,0 # [0] id:153 + sext a11,a11,7 # [2] + add.n a11,a11,a5 # [3] + s16i a11,a3,0 # [4] id:154 + retw.n # [5] + +.Lt_2_7170: # 0x402 + movi.n a4,32 # [0] + j .Lt_2_3842 # [1] + + .size esp_nn_aligned_s8_to_s16_with_offset_esp32s3, . - esp_nn_aligned_s8_to_s16_with_offset_esp32s3 + + + .literal_position + + # Program Unit: esp_nn_s8_to_s16_esp32s3 + .type esp_nn_s8_to_s16_esp32s3, @function + .align 4 + .global esp_nn_s8_to_s16_esp32s3 + +esp_nn_s8_to_s16_esp32s3: # 0x40b + entry a1,32 # + mov.n a9,a2 // src + mov.n a8,a3 // dst + mov.n a7,a4 // size + blti a4,1,.Lt_3_4866 // size == 0 + blti a4,16,.Lt_3_4610 // if (size < 16) jump to unopt path + + // load align_len to sar_byte + extui a2,a2,0,4 # [0] + wur.sar_byte a2 # [1] + mov.n a2,a9 # [2] + + // preload + ee.vld.128.ip q0,a2,16 + ee.vld.128.ip q1,a2,16 + ee.zero.q q4 + # 672 + # 673 for (i = 16; i < size - 15; i += 16) { + blti a4,32,.Lt_3_5378 # [5] + addi a6,a4,-16 # [1] + srai a6,a6,4 # [2] + slli a4,a6,4 # [3] + loopgtz a6,.LBB35_esp_nn_s8_to_s16_esp32s3 # [4] + + ee.src.q.qup q2,q0,q1 # [0*II+0] + ee.vcmp.lt.s8 q3,q2,q4 # [0*II+1] // sign + ee.vld.128.ip q1,a2,16 # [0*II+2] // for next iteration + ee.vzip.8 q2,q3 # [0*II+3] + ee.vst.128.ip q2,a3,16 # [0*II+4] id:93 + ee.vst.128.ip q3,a3,16 # [0*II+5] id:94 + +.LBB35_esp_nn_s8_to_s16_esp32s3: # 0x449 + addi a4,a4,16 # [0] + +.Lt_3_2050: # 0x44c + ee.src.q.qup q5,q0,q1 # [0] + ee.vcmp.lt.s8 q3,q5,q4 # [1] + ee.vzip.8 q5,q3 # [2] + ee.vst.128.ip q5,a3,16 # [3] id:96 + ee.vst.128.ip q3,a3,16 # [4] id:97 + # 687 + # 688 skip_to_remains_s8_to_s16: + # 689 for (; i < size; i += 2) { + bge a4,a7,.Lt_3_4866 # [5] + +.Lt_3_3330: # 0x45e + mov.n a11,a4 # [0] + add.n a2,a4,a9 # [1] + # 690 dst[i + 0] = src[i + 0]; + l8ui a10,a2,0 # [2] id:98 + addx2 a5,a4,a8 # [3] + sext a10,a10,7 # [4] + s16i a10,a5,0 # [5] id:99 + # 691 dst[i + 1] = src[i + 1]; + l8ui a3,a2,1 # [6] id:100 + sub a10,a7,a4 # [7] + addi.n a2,a2,2 # [8] + addi.n a10,a10,1 # [9] + srai a10,a10,1 # [10] + sext a3,a3,7 # [11] + s16i a3,a5,2 # [12] id:101 + addi.n a3,a10,-1 # [13] + loopgtz a3,.LBB50_esp_nn_s8_to_s16_esp32s3 # [14] + + l8ui a3,a2,0 # [0*II+0] id:98 + addi.n a5,a5,4 # [1*II+1] + sext a3,a3,7 # [0*II+2] + s16i a3,a5,0 # [0*II+3] id:99 + l8ui a3,a2,1 # [0*II+4] id:100 + addi.n a2,a2,2 # [0*II+5] + sext a3,a3,7 # [0*II+6] + s16i a3,a5,2 # [0*II+7] id:101 + +.LBB50_esp_nn_s8_to_s16_esp32s3: # 0x49c + addx2 a4,a10,a11 # [0] + # 692 } + # 693 if(i < size) { + bge a4,a7,.Lt_3_4866 # [1] + + # 694 dst[i] = src[i]; + add.n a11,a4,a9 # [0] + l8ui a11,a11,0 # [1] id:102 + addx2 a12,a4,a8 # [2] + sext a11,a11,7 # [3] + s16i a11,a12,0 # [4] id:103 + retw.n # [5] + +.Lt_3_4610: # 0x4b2 + movi.n a4,0 # [0] + j .Lt_3_3330 # [1] + +.Lt_3_4866: # 0x4ba + retw.n # [0] + +.Lt_3_5378: # 0x4bc + movi.n a4,16 # [1] + j .Lt_3_2050 # [2] + + .size esp_nn_s8_to_s16_esp32s3, . - esp_nn_s8_to_s16_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_multiply_by_quantized_mult_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_multiply_by_quantized_mult_esp32s3.S new file mode 100644 index 0000000..08ff1b8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_multiply_by_quantized_mult_esp32s3.S @@ -0,0 +1,127 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// the macro `use_nudge` enables adding rounding factor similar to tflite implementation +// this barely changes any accuracy +// keep this disabled for better performance + +#ifndef SKIP_NUDGE + # set SKIP_NUDGE flag for ~20% faster (but not bit-exact) quantisation + .set use_nudge, 1 +#endif + + .text + .literal_position + .literal .nudge_val, 1073741824 # 1 << 30 + + .type esp_nn_multiply_by_quantized_mult_asm_esp32s3, @function + .align 4 + .global esp_nn_multiply_by_quantized_mult_asm_esp32s3 + +esp_nn_multiply_by_quantized_mult_asm_esp32s3: # 0x4 + # to_add = 4 + + entry a1,32 + wsr.sar a3 + ee.zero.q q2 + + bltz a3, .skip_left_shift + ee.vsl.32 q0,q0 # [13] +.skip_left_shift: + + ssai 31 # [15] + +# move data to general purpose registers + ee.movi.32.a q0,a12,0 # [17] + ee.movi.32.a q0,a13,1 # [16] + ee.movi.32.a q0,a14,2 # [18] + ee.movi.32.a q0,a15,3 # [19] + +.ifdef use_nudge + l32r a6,.nudge_val +.endif + +# perform 64 bit mult + mulsh a4,a2,a12 # [22] + mulsh a11,a2,a13 # [23] + mulsh a10,a2,a14 # [21] + mulsh a8,a2,a15 # [20] + mull a12,a2,a12 # [24] + mull a13,a2,a13 # [25] + mull a14,a2,a14 # [26] + mull a15,a2,a15 # [27] + +# add nudge_val and discard low31 + +.ifdef use_nudge + add.n a14,a6,a14 # [41] + saltu a2,a14,a6 # [44] + add.n a10,a10,a2 # [45] + + add.n a13,a6,a13 # [47] + saltu a9,a13,a6 # [50] + add.n a11,a11,a9 # [51] +.endif + + src a10,a10,a14 # [88] + src a11,a11,a13 # [78] + ee.movi.32.q q0,a10,2 + ee.movi.32.q q0,a11,1 + +.ifdef use_nudge + add.n a15,a6,a15 # [36] + saltu a2,a15,a6 # [39] + add.n a8,a8,a2 # [40] + + add.n a12,a6,a12 # [54] + saltu a10,a12,a6 # [57] + add.n a4,a4,a10 # [58] +.endif + + src a8,a8,a15 # [95] + src a4,a4,a12 # [69] # discard lower 31 bits + ee.movi.32.q q0,a8,3 + ee.movi.32.q q0,a4,0 + + bgez a3, .skip_div_by_power_of_2 + + neg a5,a3 # [0] right_shift/exponent = -shift + ee.vcmp.lt.s32 q2,q0,q2 # [97] + addi.n a7,a5,-1 # [0] exponent - 1 + ssl a7 # [1] + movi.n a6,1 # [92] + sll a6,a6 # [2] + s32i.n a6,a1,4 # [3] to_add + addi.n a4,a1,4 # [94] to_add_addr + ee.vldbc.32 q1,a4 # [4] id:148 to_add + wsr.sar a5 + ee.vadds.s32 q1,q1,q2 + ee.vadds.s32 q0,q0,q1 + ee.vsr.32 q0,q0 + +.skip_div_by_power_of_2: + retw.n # [9] + + .size esp_nn_multiply_by_quantized_mult_asm_esp32s3, . - esp_nn_multiply_by_quantized_mult_asm_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_multiply_by_quantized_mult_ver1_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_multiply_by_quantized_mult_ver1_esp32s3.S new file mode 100644 index 0000000..ed83816 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/common/esp_nn_multiply_by_quantized_mult_ver1_esp32s3.S @@ -0,0 +1,163 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// quantisation version where we deal with different shifts and mults. + + .set use_nudge, 1 + + .text + .literal_position + .literal .LC3_19_48, 1073741824 + + # Program Unit: esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + .type esp_nn_multiply_by_quantized_mult_ver1_esp32s3, @function + .align 4 + .global esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + +esp_nn_multiply_by_quantized_mult_ver1_esp32s3: # 0x1ee + entry a1,32 # + ee.zero.q q3 # [0] + l32i.n a8,a3,0 # [5] id:200 // shift0 + l32i.n a7,a3,4 # [2] id:201 // shift1 + l32i.n a12,a2,0 # [3] id:204 // mult0 + l32i.n a15,a2,4 # [1] id:205 // mult1 + movi.n a10,0 # [7] + + max a6,a10,a8 # [1] // left_shift0 + max a5,a10,a7 # [7] // left_shift1 + sub a8,a6,a8 # [2] // right_shift0 + sub a7,a5,a7 # [8] // right_shift1 + + ee.movi.32.a q0,a9,0 # [4] + ee.movi.32.a q0,a11,1 # [11] + ssl a6 # [3] + sll a9,a9 # [4] + mulsh a4,a12,a9 # [6] + mull a12,a12,a9 # [9] + ssl a5 # [10] + sll a11,a11 # [12] + mulsh a14,a15,a11 # [14] + mull a15,a15,a11 # [16] + l32r a13,.LC3_19_48 # [23] + + ee.movi.32.q q0,a9,0 # [5] + ee.movi.32.q q0,a11,1 # [15] + + + l32i.n a6,a3,8 # [6] id:202 // shift2 + l32i.n a9,a2,8 # [19] id:206 // mult2 + max a5,a10,a6 # [0] // left_shift2 + sub a6,a5,a6 # [24] // right_shift2 + + + ee.movi.32.a q0,a11,2 # [17] + ssl a5 # [13] + sll a11,a11 # [18] + ee.movi.32.q q0,a11,2 # [20] + mulsh a5,a9,a11 # [21] + mull a9,a9,a11 # [22] + mov a11, a5 + +// add nudge to result0 & result1 + add.n a12,a13,a12 # [25] + saltu a5,a12,a13 # [26] + add.n a15,a13,a15 # [27] + add.n a5,a5,a4 # [28] + saltu a4,a15,a13 # [29] + add.n a4,a4,a14 # [30] + + + l32i.n a14,a3,12 # [31] id:203 // shift3 + add.n a9,a13,a9 # [32] // add nudge low2 + max a10,a10,a14 # [33] // left_shift3 + sub a14,a10,a14 # [34] // right_shift3 + ssl a10 # [35] + ee.movi.32.a q0,a10,3 # [36] + sll a10,a10 # [37] + +// select high32 from result0 and resul1 + ssai 31 # [39] + src a5,a5,a12 # [40] + src a4,a4,a15 # [41] + movi.n a12,1 # [42] + ee.movi.32.q q0,a5,0 # [43] + saltu a15,a9,a13 # [44] + add.n a15,a15,a11 # [45] + ee.movi.32.q q0,a4,1 # [46] + l32i.n a11,a2,12 # [47] id:207 // mult3 + src a15,a15,a9 # [48] + ee.movi.32.q q0,a15,2 # [49] + mull a9,a11,a10 # [50] + mulsh a11,a11,a10 # [51] + add.n a9,a13,a9 # [52] + saltu a13,a9,a13 # [53] + add.n a13,a13,a11 # [54] + src a13,a13,a9 # [55] + ee.movi.32.q q0,a13,3 # [57] + +// divide_by_power_of2_step + ssl a8 # [56] + sll a9,a12 # [58] + ssl a7 # [59] + addi.n a9,a9,-1 # [60] + ee.movi.32.q q2,a9,0 # [61] + sll a11,a12 # [62] + addi.n a11,a11,-1 # [63] + ssl a6 # [64] + sll a10,a12 # [65] + ee.movi.32.q q2,a11,1 # [66] + ssl a14 # [67] + addi.n a10,a10,-1 # [68] + ee.movi.32.q q2,a10,2 # [69] + sll a9,a12 # [70] + addi.n a9,a9,-1 # [71] + ee.movi.32.q q2,a9,3 # [74] + ee.andq q1,q0,q2 # [75] + + ssr a8 # [72] + sra a5,a5 # [73] + ssr a7 # [76] + sra a4,a4 # [78] + ssr a6 # [79] + sra a15,a15 # [81] + ssr a14 # [82] + sra a13,a13 # [84] + wsr.sar a12 # [85] + + ee.movi.32.q q7,a5,0 # [77] + ee.movi.32.q q7,a4,1 # [80] + ee.movi.32.q q7,a15,2 # [83] + ee.movi.32.q q7,a13,3 # [86] + + ee.vcmp.lt.s32 q3,q7,q3 # [87] + ee.vsr.32 q2,q2 # [88] + ee.vsubs.s32 q2,q2,q3 # [89] + ee.vcmp.gt.s32 q1,q1,q2 # [90] + ee.vsubs.s32 q0,q7,q1 # [91] + +// return + retw.n # [92] + + .size esp_nn_multiply_by_quantized_mult_ver1_esp32s3, . - esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_ansi.c new file mode 100644 index 0000000..60b6b41 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_ansi.c @@ -0,0 +1,183 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include + +int esp_nn_get_conv_scratch_size_ansi(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const conv_params_t *conv_params) +{ + return 0; +} + +void esp_nn_set_conv_scratch_buf_ansi(const void *buf) +{ + +} + +/** + * Assumption 1: i/p channels == o/p channels + * Assumption 2: Pointers are valid + * Assumption 3: dialation width = 1 + */ +void esp_nn_conv_u8_ansi(const uint8_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t in_channels, + const int32_t input_offset, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint8_t *filter_data, + const uint16_t filter_wd, + const uint16_t filter_ht, + const int32_t filter_offset, + const int32_t *bias, + uint8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const uint16_t out_channels, + const int32_t out_offset, + const int32_t out_shift, + const int32_t out_mult, + const int32_t activation_min, + const int32_t activation_max) +{ + for (int out_y = 0; out_y < out_ht; out_y++) { //height loop + const int16_t base_y = (out_y * stride_ht) - pad_ht; + for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + const int16_t base_x = (out_x * stride_wd) - pad_wd; + for (int out_ch_idx = 0; out_ch_idx < out_channels; out_ch_idx++) {//channel_loop + int32_t result = 0; + + /* Select filter so as the point doesn't lie outside block */ + int filter_y_start = max(0, -base_y); + int filter_x_start = max(0, -base_x); + int filter_y_end = min(filter_ht, input_ht - base_y); + int filter_x_end = min(filter_wd, input_wd - base_x); + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + for (int in_ch_idx = 0; in_ch_idx < in_channels; in_ch_idx++) { + int32_t input_index = (idx_y * input_wd + idx_x) * in_channels + in_ch_idx; + int32_t filter_index = ((out_ch_idx * filter_ht + filter_y_idx) + * filter_wd + filter_x_idx) * in_channels + + in_ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val = filter_data[filter_index] + filter_offset; + result += input_val * filter_val; + } + } + } + if (bias) { + result += bias[out_ch_idx]; + } + result = esp_nn_multiply_by_quantized_mult(result, out_mult, out_shift); + result += out_offset; + result = max(result, activation_min); + result = min(result, activation_max); + + int out_index = (out_y * out_wd + out_x) * out_channels + out_ch_idx; + out_data[out_index] = (uint8_t) result; + } + } + } +} + +/** + * Assumption 1: i/p channels == o/p channels + * Assumption 2: Pointers are valid + * Assumption 3: dialation width = 1 + */ +void esp_nn_conv_s8_ansi(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t in_channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const uint16_t out_channels = output_dims->channels; + const int32_t *out_shift = quant_data->shift; + const int32_t *out_mult = quant_data->mult; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + + int32_t out_ch_idx, out_y, out_x, in_ch_idx, filter_y_idx, filter_x_idx; + + for (out_y = 0; out_y < out_ht; out_y++) { + for (out_x = 0; out_x < out_wd; out_x++) { + for (out_ch_idx = 0; out_ch_idx < out_channels; out_ch_idx++) { + int32_t conv_out = 0; + + const int32_t base_y = stride_ht * out_y - pad_ht; + const int32_t base_x = stride_wd * out_x - pad_wd; + + const int32_t filter_y_start = max(0, -base_y); + const int32_t filter_x_start = max(0, -base_x); + + const int32_t filter_y_end = min(filter_ht, input_ht - base_y); + const int32_t filter_x_end = min(filter_wd, input_wd - base_x); + + for (filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + for (filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t in_row = base_y + filter_y_idx; + const int32_t in_col = base_x + filter_x_idx; + int32_t input_base_offset = (in_row * input_wd + in_col) * in_channels; + int32_t filter_base_offset = out_ch_idx * in_channels * filter_ht * filter_wd + + (filter_y_idx * filter_wd + filter_x_idx) * in_channels; + for (in_ch_idx = 0; in_ch_idx < in_channels; in_ch_idx++) { + conv_out += + (input_data[input_base_offset + in_ch_idx] + input_offset) * + filter_data[filter_base_offset + in_ch_idx]; + } + } + } + if (bias) { + conv_out += bias[out_ch_idx]; + } + conv_out = esp_nn_multiply_by_quantized_mult(conv_out, out_mult[out_ch_idx], out_shift[out_ch_idx]); + conv_out += out_offset; + conv_out = max(conv_out, activation_min); + conv_out = min(conv_out, activation_max); + *out_data++ = (int8_t) conv_out; + } + } + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_esp32s3.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_esp32s3.c new file mode 100644 index 0000000..1ddf4ba --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_esp32s3.c @@ -0,0 +1,273 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * Optimizations strategies used: + * Below optimizations are capable of any size of input/filter: + * + * 1. For filter wdxht = 1x1 (Refer esp_nn_conv_s8_mult8_1x1_esp32s3 function) + * - For this specific version, the strategy we employ: + * > This particular filter has only the channel + * dimension and we have `out_ch` number of such filters. + * > We take 8 input lines at a time and transpose those. + * > Keep loading and multiplying filter values one by one, + * to produce 8 outputs in parallel + * + * 2. General version: (Refer esp_nn_conv_s8_filter_aligned_input_padded_esp32s3) + * - For all other cases: + * > Consider `filter_wd * in_ch` as a single row. These many values can + * be continuosly loaded from inputs as well. + * > multiply accumulate into a single filter output. + * > To speed things up further, we pre-calculate + * (filter * in_offset + bias term) earlier and add it at the end of filter + * + * About ((filter * in_offset + bias term)) accumulate term: + * > The conv operation before requantization is as follows: + * for i in filter_size: + * conv_out += (input + input_offset) * filter; + * conv_out += bias + * + * > where input_offset is constant term hence, we can see that + * this term can be precalculated as: + * for i in filter_size: + * acc_term += input_offset * filter[i]; + * acc_term += bias + * OR + * for i in filter_size: + * acc_term += filter[i]; // accumulate filter values + * acc_term = acc_term * input_offset + bias + * + * + * In both the above versions we align the filter if needed, pad the input with + * -input_offset if needed and extend the channels to make those multiple + * of 8/16 as per function needs + */ + +#include +#include + +#include + +static int16_t *scratch_buffer = NULL; + +extern void esp_nn_conv_s8_mult8_1x1_esp32s3( + const int8_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t in_channels, + const int32_t input_offset, + const int8_t *filter_aligned, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const uint16_t out_channels, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max, + void *buffer /* scratch buffer */); + +extern void esp_nn_conv_s8_filter_aligned_input_padded_esp32s3( + const int8_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t in_channels, + const int32_t input_offset, + const uint16_t stride_wd, + const uint16_t stride_ht, + const int8_t *filter_data, + const uint16_t filter_wd, + const uint16_t filter_ht, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const uint16_t out_channels, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max, + void *scratch_buffer); + +int esp_nn_get_conv_scratch_size_esp32s3(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const conv_params_t *conv_params) +{ + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t in_ch = input_dims->channels; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t out_ch = output_dims->channels; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + + int new_channels = (in_ch + 7) & ~7; + + int input_scratch = input_wd * input_ht * in_ch; + int filter_scratch = filter_wd * filter_ht * in_ch * out_ch; + + int align_buf_size = 32; /* extra buffer for alignment */ + if ((filter_wd == 1 && filter_ht == 1 && pad_wd == 0 && pad_ht == 0) && + (stride_wd == 1 && stride_ht == 1)) { + int transpose_buf_size = 2 * (8 * new_channels); /* to store intermediate data */ + if (input_wd * input_ht < 8) { + transpose_buf_size = 0; // not using this for leftover + } + if (in_ch % 8) { + input_scratch = input_wd * input_ht * new_channels; + } else { + input_scratch = 0; + } + filter_scratch = new_channels * out_ch; + return input_scratch + filter_scratch + transpose_buf_size + align_buf_size; + } else { + new_channels = (in_ch + 15) & ~15; + if (pad_wd == 0 && pad_ht == 0) { + input_scratch = 0; + } else { + input_scratch = (input_wd + 2 * pad_wd) * (input_ht + 2 * pad_ht) * in_ch; + } + filter_scratch = filter_wd * filter_ht * new_channels * out_ch; + int offset_acc_scratch = out_ch * 4; + return input_scratch + filter_scratch + align_buf_size + offset_acc_scratch; + } + return align_buf_size; +} + +void esp_nn_set_conv_scratch_buf_esp32s3(void *buf) +{ + scratch_buffer = (int16_t *) buf; +} + +void esp_nn_conv_s8_esp32s3(const data_dims_t *input_dims, + const int8_t *input, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + if (scratch_buffer == NULL) { + printf("esp_nn_conv error! scratch_buffer not set!\n"); + return; + } + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const uint16_t out_channels = output_dims->channels; + const int32_t *out_shift = quant_data->shift; + const int32_t *out_mult = quant_data->mult; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + + int filter_size = filter_wd * filter_ht * channels * out_channels; + + if (filter_wd == 1 && filter_ht == 1 && pad_wd == 0 && pad_ht == 0 && + stride_wd == 1 && stride_ht == 1) { + + int8_t *input_aligned = (int8_t *) input; + int8_t *scratch_buf = (int8_t *) scratch_buffer; + int8_t *filter_aligned = (int8_t *) scratch_buffer; + int new_channels = channels; + if (channels % 8 == 0) { + if ((int) filter_data & 7) { // if the filter_data is not aligned to 8 bytes + int scratch_offset = (int) (filter_aligned + filter_size); + scratch_buf = (int8_t *) (scratch_offset + 16 - (scratch_offset & 15)); + memcpy(filter_aligned, filter_data, filter_size); // copy to aligned address + } else { + filter_aligned = (int8_t *) filter_data; + } + } else { + // pad extra channel to make it multiple of 8. Both input and filter + new_channels = (channels + 7) & ~7; + for (int out_ch_idx = 0; out_ch_idx < out_channels; out_ch_idx++) { + memcpy(filter_aligned, filter_data, channels); + memset(filter_aligned + channels, 0, new_channels - channels); + filter_aligned += new_channels; + filter_data += channels; + } + filter_aligned = (int8_t *) scratch_buffer; + int filter_data_size = new_channels * out_channels; + input_aligned = filter_aligned + filter_data_size; + for (int input_idx = 0; input_idx < input_ht * input_wd; input_idx++) { + memcpy(input_aligned, input, channels); + memset(input_aligned + channels, 0, new_channels - channels); + input_aligned += new_channels; + input += channels; + } + input_aligned = filter_aligned + filter_data_size; + scratch_buf = input_aligned + input_ht * input_wd * new_channels; + } + esp_nn_conv_s8_mult8_1x1_esp32s3( + input_aligned, input_wd, input_ht, new_channels, input_offset, + filter_aligned, bias, out_data, out_wd, out_ht, out_channels, out_offset, + out_shift, out_mult, activation_min, activation_max, scratch_buf); + } else { + // align the `filter width * channels` to 16 bytes. Do zero padding for the same + int32_t filter_row_size = filter_wd * channels; + int32_t filter_alignment_padding = 16 - (filter_row_size & 15); + int8_t *filter_data_aligned = (int8_t *) filter_data; + int8_t *input_padded = (int8_t *) input; + int8_t *scratch_data = (int8_t *) scratch_buffer; + int new_input_wd = input_wd, new_input_ht = input_ht; + if (filter_alignment_padding != 16) { + // pad filter_data + int32_t new_row_size = filter_wd * channels + filter_alignment_padding; + filter_data_aligned = scratch_data; + int8_t *row_ptr = filter_data_aligned; + for (int32_t ch_idx = 0; ch_idx < out_channels; ch_idx++) { + for (int32_t row_idx = 0; row_idx < filter_ht; row_idx++) { + memcpy(row_ptr, filter_data, filter_row_size); + memset(row_ptr + filter_row_size, 0, new_row_size - filter_row_size); + filter_data += filter_row_size; + row_ptr += new_row_size; + } + } + scratch_data += new_row_size * filter_ht * out_channels; + filter_row_size = new_row_size; + } else if ( (int) filter_data & 15) { + filter_data_aligned = scratch_data; + memcpy(filter_data_aligned, filter_data, filter_size); + scratch_data += filter_size; + } + if (pad_wd != 0 || pad_ht != 0) { // need padding + input_padded = (int8_t *) scratch_data; + esp_nn_aligned_s8_pad_with_value(input, input_padded, input_wd, input_ht, channels, + -input_offset, pad_wd, pad_ht); + new_input_wd = input_wd + 2 * pad_wd; + new_input_ht = input_ht + 2 * pad_ht; + scratch_data += new_input_wd * new_input_ht * channels; + } + esp_nn_conv_s8_filter_aligned_input_padded_esp32s3( + input_padded, new_input_wd, new_input_ht, channels, input_offset, + stride_wd, stride_ht, filter_data_aligned, filter_wd, filter_ht, + bias, out_data, out_wd, out_ht, out_channels, out_offset, + out_shift, out_mult, activation_min, activation_max, scratch_data); + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_opt.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_opt.c new file mode 100644 index 0000000..c1478ba --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_opt.c @@ -0,0 +1,183 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include + +int esp_nn_get_conv_scratch_size_opt(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const conv_params_t *conv_params) +{ + return 0; +} + +void esp_nn_set_conv_scratch_buf_opt(const void *buf) +{ + +} + +__attribute__ ((noinline)) +static void esp_nn_conv_s8_1x1(const data_dims_t *input_dims, + const int8_t *input_data, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + const uint16_t input_wd = input_dims->width; + const uint16_t in_channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const uint16_t out_channels = output_dims->channels; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + + for (int32_t in_row = 0; in_row < out_ht * stride_ht; in_row += stride_ht) { + for (int32_t in_col = 0; in_col < out_wd * stride_wd; in_col += stride_wd) { + const int32_t *out_mult = quant_data->mult; + const int32_t *out_shift = quant_data->shift; + const int8_t *filter_ptr = filter_data; + const int8_t *input_base_ptr = input_data + (in_row * input_wd + in_col) * in_channels; + int32_t out_ch_idx = 0; + for (; out_ch_idx < out_channels; out_ch_idx++) { + int32_t conv_out = 0; + + const int8_t *input_ptr = input_base_ptr; + + int32_t in_ch_idx = 0; + for (; in_ch_idx < in_channels - 3; in_ch_idx += 4) { + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + } + for (; in_ch_idx < in_channels; in_ch_idx ++) { + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + } + if (bias) { + conv_out += bias[out_ch_idx]; + } + conv_out = esp_nn_multiply_by_quantized_mult_fast(conv_out, *out_mult++, *out_shift++); + conv_out += out_offset; + conv_out = max(conv_out, activation_min); + conv_out = min(conv_out, activation_max); + *out_data++ = (int8_t) conv_out; + } + } + } +} + +/** + * Assumption 1: i/p channels == o/p channels + * Assumption 2: Pointers are valid + * Assumption 3: dialation width = 1 + */ +void esp_nn_conv_s8_opt(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + + if (filter_wd == 1 && filter_ht == 1) { + esp_nn_conv_s8_1x1(input_dims, input_data, filter_data, bias, + output_dims, out_data, conv_params, quant_data); + return; + } + + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t in_channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const uint16_t out_channels = output_dims->channels; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + + int32_t out_ch_idx, out_y, out_x, filter_y_idx, filter_x_idx; + + for (out_y = 0; out_y < out_ht; out_y++) { + for (out_x = 0; out_x < out_wd; out_x++) { + const int32_t *out_shift = quant_data->shift; + const int32_t *out_mult = quant_data->mult; + for (out_ch_idx = 0; out_ch_idx < out_channels; out_ch_idx++) { + int32_t conv_out = 0; + + const int32_t base_y = stride_ht * out_y - pad_ht; + const int32_t base_x = stride_wd * out_x - pad_wd; + + const int32_t filter_y_start = max(0, -base_y); + const int32_t filter_x_start = max(0, -base_x); + + const int32_t filter_y_end = min(filter_ht, input_ht - base_y); + const int32_t filter_x_end = min(filter_wd, input_wd - base_x); + + for (filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + for (filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t in_row = base_y + filter_y_idx; + const int32_t in_col = base_x + filter_x_idx; + + const int8_t *input_ptr = input_data + + (in_row * input_wd + in_col) * in_channels; + const int8_t *filter_ptr = filter_data + + out_ch_idx * in_channels * filter_ht * filter_wd + + (filter_y_idx * filter_wd + filter_x_idx) * in_channels; + int32_t in_ch_idx = 0; + for (; in_ch_idx < in_channels - 3; in_ch_idx += 4) { + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + } + for (; in_ch_idx < in_channels; in_ch_idx ++) { + conv_out += (*input_ptr++ + input_offset) * *filter_ptr++; + } + } + } + if (bias) { + conv_out += bias[out_ch_idx]; + } + conv_out = esp_nn_multiply_by_quantized_mult_fast(conv_out, *out_mult++, *out_shift++); + conv_out += out_offset; + conv_out = max(conv_out, activation_min); + conv_out = min(conv_out, activation_max); + *out_data++ = (int8_t) conv_out; + } + } + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s16_mult4_1x1_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s16_mult4_1x1_esp32s3.S new file mode 100644 index 0000000..50c00cc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s16_mult4_1x1_esp32s3.S @@ -0,0 +1,358 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + .literal .nudge_val, 1073741824 + + # Program Unit: esp_nn_conv_s16_mult4_1x1_esp32s3 + .type esp_nn_conv_s16_mult4_1x1_esp32s3, @function + .align 4 + .global esp_nn_conv_s16_mult4_1x1_esp32s3 +esp_nn_conv_s16_mult4_1x1_esp32s3: # 0xa62 + # scratch_buf = 0 + # to_add = 32 + # gra_spill_temp_139 = 36 + # gra_spill_temp_140 = 40 + # gra_spill_temp_141 = 44 + # gra_spill_temp_155 = 48 + # gra_spill_temp_156 = 52 + # gra_spill_temp_144 = 56 + # gra_spill_temp_145 = 60 + # gra_spill_temp_146 = 64 + # gra_spill_temp_147 = 68 + # gra_spill_temp_148 = 72 + # gra_spill_temp_149 = 76 + # gra_spill_temp_150 = 80 + # gra_spill_temp_151 = 84 + # gra_spill_temp_152 = 88 + # gra_spill_temp_153 = 92 + # lgra_spill_temp_165 = 96 + # lgra_spill_temp_166 = 100 + # lgra_spill_temp_167 = 104 + # lgra_spill_temp_168 = 108 + # gra_spill_temp_158 = 112 + # gra_spill_temp_159 = 116 + # gra_spill_temp_160 = 120 + + + // registers: + // a2: int16_t *input_data + // a3: uint16_t input_wd + // a4: uint16_t input_ht + // a5: uint16_t in_channels + // a6: int16_t *filter_data + // a7: int32_t *bias + + // on stack: + // 160: int8_t *out_data + // 164: uint16_t out_wd + // 168: uint16_t out_ht + // 172: uint16_t out_channels + // 176: int32_t out_offset + // 180: int32_t *out_shift + // 184: int32_t *out_mult + // 188: int32_t activation_min + // 192: int32_t activation_max + // 196: *buffer /* scratch buffer */ + + + entry a1,160 # + s32i.n a2,a1,40 # [0] gra_spill_temp_140 + s32i a6,a1,68 # [1] gra_spill_temp_147 + s32i a7,a1,116 # [2] gra_spill_temp_159 + + mul16u a3,a3,a4 # [3] + addi a10,a1,112 # [4] + addmi a11,a1,176 # [5] + addmi a8,a1,176 # [6] + addmi a9,a1,176 # [7] + addi.n a9,a9,12 # [8] + addi a8,a8,16 # [9] + ee.vldbc.32 q5,a11 # [10] id:188 out_offset + ee.vldbc.32 q7,a8 # [12] id:270 activation_max + ee.vldbc.32 q6,a9 # [13] id:269 activation_min + blti a3,4,.Lt_3_6402 # [14] + +.LBB3_esp_nn_conv_s16_mult4_1x1_esp32s3: # 0xa90 + l32i a13,a1,160 # [0] id:280 out_data+0x0 + srai a8,a5,2 # [1] + addi a10,a3,-3 # [2] + addi a9,a5,-3 # [3] + movi.n a12,0 # [4] + slli a11,a5,2 # [5] + slli a15,a5,1 # [6] + l16ui a14,a1,172 # [7] id:271 out_channels+0x0 + s32i.n a15,a1,36 # [9] gra_spill_temp_139 + s32i.n a11,a1,56 # [10] gra_spill_temp_144 + s32i a12,a1,84 # [11] gra_spill_temp_151 + s32i a9,a1,52 # [12] gra_spill_temp_156 + s32i.n a10,a1,60 # [13] gra_spill_temp_145 + s32i a8,a1,88 # [14] gra_spill_temp_152 + movi.n a10,0 # [15] + l32i a8,a1,196 # [16] id:281 buffer+0x0 + slli a11,a11,1 # [19] + l32i a15,a1,184 # [20] id:192 out_mult+0x0 + s32i a11,a1,64 # [22] gra_spill_temp_146 + s32i a8,a1,112 # [25] gra_spill_temp_158 + s32i a10,a1,92 # [26] gra_spill_temp_153 + movi.n a8,0 # [27] + s32i a10,a1,80 # [31] gra_spill_temp_150 + s32i a8,a1,76 # [32] gra_spill_temp_149 + slli a8,a14,1 # [34] + addx2 a9,a14,a14 # [35] + s32i a9,a1,72 # [36] gra_spill_temp_148 + s32i.n a8,a1,44 # [37] gra_spill_temp_141 + addx4 a14,a14,a15 # [38] + s32i a14,a1,48 # [39] gra_spill_temp_155 + j .Lt_3_6914 # [40] + +.Lt_3_8194: # 0xb00 +# Part of loop body line 305, head labeled .Lt_3_6914 + l32i.n a12,a1,60 # [0] gra_spill_temp_145 + l32i.n a9,a1,56 # [1] gra_spill_temp_144 + l32i a8,a1,76 # [2] gra_spill_temp_149 + l32i a15,a1,64 # [3] gra_spill_temp_146 + l32i a11,a1,72 # [4] gra_spill_temp_148 + l32i a14,a1,84 # [5] gra_spill_temp_151 + add.n a13,a13,a11 # [6] + l32i a11,a1,80 # [7] gra_spill_temp_150 + add.n a14,a14,a15 # [8] + add.n a8,a8,a9 # [9] + s32i a8,a1,76 # [10] gra_spill_temp_149 + s32i a14,a1,84 # [11] gra_spill_temp_151 + addi.n a11,a11,4 # [12] + s32i a11,a1,80 # [13] gra_spill_temp_150 + bge a11,a12,.Lt_3_6402 # [14] + +.Lt_3_6914: # 0xb27 + l32i a12,a1,52 # [0] gra_spill_temp_156 + l32i a4,a1,112 # [1] gra_spill_temp_158 + blti a12,1,.Lt_3_7170 # [2] + +.LBB6_esp_nn_conv_s16_mult4_1x1_esp32s3: # 0xb30 + l32i a3,a1,88 # [0] gra_spill_temp_152 + l32i.n a5,a1,40 # [1] gra_spill_temp_140 + l32i a2,a1,84 # [3] gra_spill_temp_151 + add.n a2,a2,a5 # [7] + l32i.n a5,a1,36 # [9] gra_spill_temp_139 + + // load and transose 4 lines of input 4xchannels, + loopgtz a3,.transpose_loop_end + mov.n a3,a2 # [0*II+0] + ee.vld.l.64.xp q0,a3,a5 # [0*II+2] id:282 + ee.vld.l.64.xp q1,a3,a5 # [0*II+3] id:283 + ee.vld.l.64.xp q2,a3,a5 # [0*II+4] id:284 + ee.vld.l.64.xp q3,a3,a5 # [0*II+5] id:285 + ee.vzip.16 q0,q1 # [0*II+6] + ee.vzip.16 q2,q3 # [0*II+7] + ee.vzip.32 q0,q2 # [0*II+8] + ee.vst.128.ip q0,a4,16 # [0*II+9] id:286 + ee.vst.128.ip q2,a4,16 # [0*II+10] id:287 + addi.n a2,a2,8 # [0*II+1] +.transpose_loop_end: + +.Lt_3_7170: # 0xb7c + l32i a2,a1,68 # [0] gra_spill_temp_147 + l32i a9,a1,116 # [1] gra_spill_temp_159 + l16ui a8,a1,172 # [2] out_channels + s32i a9,a1,120 # [3] gra_spill_temp_160 + beqz.n a8,.Lt_3_8194 # [4] + + l32i a9,a1,180 # [0] out_shift + l32i a11,a1,184 # [1] out_mult + l32i a15,a1,72 # [2] gra_spill_temp_148 + l32i.n a14,a1,44 # [3] gra_spill_temp_141 + add.n a15,a15,a13 # [4] + add.n a14,a14,a13 # [5] + j .Lt_3_8706 # [6] + +.Lt_3_10754: # 0xb9a + + movi.n a3,0 # [0] + +.Lt_3_10498: # 0xb9c + +// esp_nn_multiply_by_quantized_mult_esp32s3 + ee.zero.q q0 # [0] + l32i a5,a1,92 # [1] gra_spill_temp_153 + s32i a2,a1,96 # [2] lgra_spill_temp_165 + s32i a11,a1,104 # [3] lgra_spill_temp_167 + s32i a13,a1,108 # [4] lgra_spill_temp_168 + s32i a9,a1,100 # [5] lgra_spill_temp_166 + + movi.n a13,0 # [6] + max a12,a12,a13 # [7] + wsr.sar a12 # [8] + ee.vsl.32 q1,q1 # [9] + ssai 31 # [10] + ee.movi.32.a q1,a7,0 # [11] + ee.movi.32.a q1,a8,1 # [12] + ee.movi.32.a q1,a6,3 # [13] + ee.movi.32.a q1,a9,2 # [14] + mulsh a12,a4,a9 # [15] + mulsh a11,a4,a6 # [16] + mulsh a2,a4,a8 # [17] + mulsh a13,a7,a4 # [18] + mull a8,a4,a8 # [19] + mull a7,a7,a4 # [20] + mull a6,a4,a6 # [24] + + add.n a11,a5,a11 # [21] + add.n a12,a5,a12 # [22] + add.n a2,a5,a2 # [23] + add.n a5,a5,a13 # [25] + + l32r a13,.nudge_val + mull a9,a4,a9 # [27] + + add.n a6,a13,a6 # [28] + add.n a9,a13,a9 # [29] + add.n a10,a13,a7 # [30] + add.n a8,a13,a8 # [32] + + saltu a7,a10,a13 # [33] + add.n a7,a7,a5 # [34] + saltu a5,a8,a13 # [35] + add.n a5,a5,a2 # [36] + src a5,a5,a8 # [37] + saltu a2,a9,a13 # [38] + add.n a2,a2,a12 # [40] + saltu a13,a6,a13 # [41] + addi.n a12,a3,-1 # [42] + src a2,a2,a9 # [43] + ee.movi.32.q q3,a5,1 # [51] + ee.movi.32.q q3,a2,2 # [54] + + add.n a13,a13,a11 # [44] + addi a9,a1,32 # [45] to_add + movi.n a11,1 # [46] + src a7,a7,a10 # [47] + src a13,a13,a6 # [48] + ee.movi.32.q q3,a7,0 # [50] + ee.movi.32.q q3,a13,3 # [57] + + addi a8,a1,112 # [49] + + l32i a7,a1,48 # [52] gra_spill_temp_155 + l16ui a5,a1,172 # [53] out_channels + ssl a12 # [55] + sll a11,a11 # [56] + wsr.sar a3 # [58] + ee.vcmp.lt.s32 q0,q3,q0 # [59] + l32i a13,a1,108 # [60] lgra_spill_temp_168 + s32i.n a11,a1,32 # [61] to_add + ee.vldbc.32 q1,a9 # [62] id:317 to_add + add.n a5,a5,a13 # [63] + l32i a9,a1,100 # [64] lgra_spill_temp_166 + ee.vadds.s32 q1,q1,q0 # [65] + addi.n a9,a9,4 # [66] + ee.vadds.s32 q1,q3,q1 # [67] + ee.vsr.32 q1,q1 # [69] + +# add offset, apply activation and store + ee.vadds.s32 q1,q1,q5 # [70] + ee.vmin.s32 q1,q1,q7 # [72] + ee.vmax.s32 q1,q1,q6 # [73] + ee.vst.128.ip q1,a1,0 # [74] id:320 + l8ui a6,a1,0 # [75] scratch_buf + s8i a6,a13,0 # [76] + addi.n a13,a13,1 # [77] + l8ui a2,a1,4 # [78] scratch_buf+4 + s8i a2,a5,0 # [79] + l8ui a12,a1,8 # [80] scratch_buf+8 + l32i a2,a1,96 # [81] lgra_spill_temp_165 + s8i a12,a14,0 # [82] + addi.n a14,a14,1 # [83] + l8ui a11,a1,12 # [84] scratch_buf+12 + s8i a11,a15,0 # [85] + l32i a11,a1,104 # [86] lgra_spill_temp_167 + addi.n a15,a15,1 # [87] + addi.n a11,a11,4 # [88] + sub a7,a11,a7 # [89] + beqz a7,.Lt_3_8194 # [90] + +.Lt_3_8706: # 0xc97 + ee.zero.qacc # [0] + l32i a8,a1,52 # [1] gra_spill_temp_156 + l32i a3,a1,112 # [2] gra_spill_temp_158 + blti a8,1,.Lt_3_8962 # [3] + + l32i a4,a1,88 # [0] gra_spill_temp_152 + loopgtz a4,.LBB53_esp_nn_conv_s16_mult4_1x1_esp32s3 # [2] + + ee.vld.l.64.ip q0,a2,8 # [0*II+0] id:289 + ee.vld.l.64.ip q1,a3,8 # [0*II+1] id:290 + ee.vld.l.64.ip q2,a3,8 # [0*II+2] id:291 + ee.vsmulas.s16.qacc q1,q0,0 # [0*II+3] + ee.vld.l.64.ip q3,a3,8 # [0*II+4] id:292 + ee.vsmulas.s16.qacc q2,q0,1 # [0*II+5] + ee.vld.l.64.ip q4,a3,8 # [0*II+6] id:293 + ee.vsmulas.s16.qacc q3,q0,2 # [0*II+7] + ee.vsmulas.s16.qacc q4,q0,3 # [0*II+8] + +.LBB53_esp_nn_conv_s16_mult4_1x1_esp32s3: # 0xcc4 + +.Lt_3_8962: # 0xcc4 + +// extract data: + mov a10,a1 + ee.st.qacc_l.l.128.ip a10,16 # [0] id:298 + ee.st.qacc_l.h.32.ip a10,-16 # [1] id:299 + l8ui a12,a1,16 # [2] scratch_buf+16 + l8ui a8,a1,6 # [3] scratch_buf+6 + s8i a8,a1,3 # [4] scratch_buf+3 + s8i a12,a1,7 # [5] scratch_buf+7 + l8ui a8,a1,15 # [6] scratch_buf+15 + l8ui a12,a1,5 # [7] scratch_buf+5 + s8i a12,a1,2 # [8] scratch_buf+2 + s8i a8,a1,6 # [9] scratch_buf+6 + l16ui a12,a1,10 # [10] scratch_buf+10 + movi.n a8,16 # [11] + ee.srcmb.s16.qacc q2,a8,0 # [12] + s16i a12,a1,4 # [13] scratch_buf+4 + ee.vld.l.64.ip q1,a10,0 # [14] id:309 + l32i a12,a1,116 # [15] gra_spill_temp_159, bias + ee.vzip.16 q1,q2 # [16] + + beqz.n a12,.Lt_3_9986 # [17] // skip bias + // add bias: + l32i a8,a1,120 # [0] gra_spill_temp_160 + ee.vldbc.32.ip q0,a8,4 # [2] id:311 + s32i a8,a1,120 # [3] gra_spill_temp_160 + ee.vadds.s32 q1,q1,q0 # [4] +.Lt_3_9986: # 0xd04 + + l32i.n a12,a9,0 # [0] id:313 + l32i.n a4,a11,0 # [1] id:312 + bgei a12,1,.Lt_3_10754 # [2] + + neg a3,a12 # [0] + j .Lt_3_10498 # [1] + +.Lt_3_6402: # 0xd11 + retw.n # [0] + + .size esp_nn_conv_s16_mult4_1x1_esp32s3, . - esp_nn_conv_s16_mult4_1x1_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s16_mult8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s16_mult8_esp32s3.S new file mode 100644 index 0000000..4c49f80 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s16_mult8_esp32s3.S @@ -0,0 +1,489 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + .literal .LC10_28_153, -2147483648 + .literal .LC11_28_154, -1073741823 + .literal .LC12_28_155, 2147483647 + .literal .LC13_28_156, 1073741824 + + # Program Unit: esp_nn_conv_s16_mult8_esp32s3 + .type esp_nn_conv_s16_mult8_esp32s3, @function + .align 4 + .global esp_nn_conv_s16_mult8_esp32s3 +esp_nn_conv_s16_mult8_esp32s3: # 0x6e2 + # qacc_scratch = 0 + # gra_spill_temp_96 = 48 + # gra_spill_temp_97 = 52 + # gra_spill_temp_98 = 56 + # gra_spill_temp_99 = 60 + # gra_spill_temp_100 = 64 + # gra_spill_temp_101 = 68 + # gra_spill_temp_102 = 72 + # gra_spill_temp_103 = 76 + # gra_spill_temp_104 = 80 + # gra_spill_temp_105 = 84 + # gra_spill_temp_106 = 88 + # gra_spill_temp_107 = 92 + # gra_spill_temp_108 = 96 + # gra_spill_temp_109 = 100 + # gra_spill_temp_110 = 104 + # gra_spill_temp_111 = 108 + # gra_spill_temp_112 = 112 + # gra_spill_temp_113 = 116 + # gra_spill_temp_114 = 120 + # gra_spill_temp_115 = 124 + # gra_spill_temp_116 = 128 + # gra_spill_temp_117 = 132 + # gra_spill_temp_118 = 136 + # gra_spill_temp_119 = 140 + # gra_spill_temp_120 = 144 + # gra_spill_temp_121 = 148 + # gra_spill_temp_122 = 152 + # gra_spill_temp_123 = 156 + # gra_spill_temp_124 = 160 + # gra_spill_temp_125 = 164 + # gra_spill_temp_126 = 168 + # gra_spill_temp_127 = 172 + # gra_spill_temp_128 = 176 + # gra_spill_temp_129 = 180 + # gra_spill_temp_130 = 184 + # gra_spill_temp_131 = 188 + # gra_spill_temp_132 = 192 + # gra_spill_temp_133 = 196 + # gra_spill_temp_134 = 200 + # gra_spill_temp_135 = 204 + # gra_spill_temp_136 = 208 + # gra_spill_temp_137 = 212 + + // registers: + // a2: const int16_t *input_data + // a3: const uint16_t input_wd + // a4: const uint16_t input_ht + // a5: const uint16_t in_channels + // a6: const uint16_t pad_wd + // a7: const uint16_t pad_ht + + // on stack: + // const uint16_t stride_wd + // const uint16_t stride_ht + // const int16_t *filter_data + // const uint16_t filter_wd + // const uint16_t filter_ht + // const int32_t *bias + // int8_t *out_data + // const uint16_t out_wd + // const uint16_t out_ht + // const uint16_t out_channels + // const int32_t out_offset + // const int32_t *out_shift + // const int32_t *out_mult + // const int32_t activation_min + // const int32_t activation_max + + + entry a1,256 # + s32i a2,a1,176 # [0] gra_spill_temp_128 + s32i a3,a1,192 # [1] gra_spill_temp_132 + s32i.n a6,a1,60 # [2] gra_spill_temp_99 + l16ui a8,a1,288 # [3] id:282 out_ht+0x0 + s32i a8,a1,68 # [4] gra_spill_temp_101 + beqz.n a8,.Lt_2_11778 # [5] + + s32i a7,a1,76 # [0] gra_spill_temp_103 + s32i a1,a1,156 # [1] gra_spill_temp_123 + l16ui a8,a1,272 # [2] id:285 filter_ht+0x0 + neg a11,a7 # [3] + movi.n a12,0 # [4] + neg a14,a6 # [5] + l16ui a15,a1,268 # [6] id:286 filter_wd+0x0 + l16ui a9,a1,292 # [7] id:283 out_channels+0x0 + l32i a10,a1,304 # [8] id:284 out_mult+0x0 + s32i a10,a1,88 # [9] gra_spill_temp_106 + s32i a9,a1,96 # [10] gra_spill_temp_108 + s32i a15,a1,196 # [11] gra_spill_temp_133 + s32i.n a14,a1,48 # [12] gra_spill_temp_96 + s32i a12,a1,72 # [13] gra_spill_temp_102 + s32i a11,a1,80 # [14] gra_spill_temp_104 + s32i.n a8,a1,52 # [15] gra_spill_temp_97 + sub a13,a3,a14 # [16] + mul16u a8,a5,a8 # [17] + s32i.n a13,a1,56 # [18] gra_spill_temp_98 + sub a11,a4,a11 # [19] + l32i a12,a1,276 # [20] id:292 bias+0x0 + s32i a12,a1,152 # [21] gra_spill_temp_122 + s32i a11,a1,84 # [22] gra_spill_temp_105 + l32i a14,a1,308 # [23] id:290 activation_min+0x0 + l32i a13,a1,312 # [24] id:291 activation_max+0x0 + s32i a13,a1,144 # [25] gra_spill_temp_120 + mull a15,a15,a8 # [26] + addx4 a9,a9,a10 # [27] + s32i a14,a1,140 # [28] gra_spill_temp_119 + l32i a11,a1,300 # [29] id:293 out_shift+0x0 + s32i a11,a1,92 # [30] gra_spill_temp_107 + slli a14,a5,1 # [31] + s32i a9,a1,124 # [32] gra_spill_temp_115 + s32i a15,a1,128 # [33] gra_spill_temp_116 + l32i a8,a1,280 # [34] id:288 out_data+0x0 + movi.n a10,0 # [35] + s32i a10,a1,160 # [36] gra_spill_temp_124 + s32i a8,a1,132 # [37] gra_spill_temp_117 + l32i a15,a1,296 # [38] id:289 out_offset+0x0 + l32i a9,a1,264 # [39] id:287 filter_data+0x0 + s32i a9,a1,180 # [40] gra_spill_temp_129 + s32i a15,a1,136 # [41] gra_spill_temp_118 + l16ui a8,a1,284 # [42] id:296 out_wd+0x0 + l16ui a10,a1,256 # [43] id:294 stride_wd+0x0 + s32i a10,a1,100 # [44] gra_spill_temp_109 + s32i a8,a1,104 # [45] gra_spill_temp_110 + addi.n a15,a5,-1 # [46] + l16ui a9,a1,260 # [47] id:295 stride_ht+0x0 + s32i a9,a1,64 # [48] gra_spill_temp_100 + srai a15,a15,3 # [49] + j .Lt_2_12290 # [50] + +.Lt_2_12546: # 0x788 + l32i a8,a1,68 # [0] gra_spill_temp_101 + l32i a12,a1,80 # [1] gra_spill_temp_104 + l32i a11,a1,84 # [2] gra_spill_temp_105 + l32i a10,a1,64 # [3] gra_spill_temp_100 + l32i a13,a1,72 # [4] gra_spill_temp_102 + l32i a9,a1,76 # [5] gra_spill_temp_103 + addi.n a13,a13,1 # [6] + s32i a13,a1,72 # [7] gra_spill_temp_102 + sub a9,a9,a10 # [8] + sub a11,a11,a10 # [9] + add.n a12,a12,a10 # [10] + s32i a12,a1,80 # [11] gra_spill_temp_104 + s32i a11,a1,84 # [12] gra_spill_temp_105 + s32i a9,a1,76 # [13] gra_spill_temp_103 + sub a13,a13,a8 # [14] + beqz a13,.Lt_2_11778 # [15] + +.Lt_2_12290: # 0x7b6 // width loop + l32i a13,a1,104 # [0] gra_spill_temp_110 + beqz.n a13,.Lt_2_12546 # [2] + + l32i a8,a1,192 # [0] gra_spill_temp_132 + l32i a9,a1,80 # [1] gra_spill_temp_104 + movi.n a11,0 # [2] + l32i a10,a1,76 # [3] gra_spill_temp_103 + l32i.n a12,a1,60 # [4] gra_spill_temp_99 + l32i.n a13,a1,56 # [5] gra_spill_temp_98 + s32i a13,a1,116 # [6] gra_spill_temp_113 + s32i a12,a1,112 # [7] gra_spill_temp_112 + max a10,a10,a11 # [8] + s32i a10,a1,148 # [9] gra_spill_temp_121 + add.n a9,a9,a10 # [10] + l32i.n a11,a1,48 # [11] gra_spill_temp_96 + s32i a11,a1,184 # [12] gra_spill_temp_130 + mull a8,a8,a9 # [13] + l32i a10,a1,84 # [14] gra_spill_temp_105 + s32i a8,a1,120 # [15] gra_spill_temp_114 + l32i.n a9,a1,52 # [16] gra_spill_temp_97 + movi.n a8,0 # [17] + s32i a8,a1,108 # [18] gra_spill_temp_111 + min a9,a9,a10 # [19] + s32i a9,a1,204 # [20] gra_spill_temp_135 + j .Lt_2_13058 # [21] + +.Lt_2_13314: # 0x7f6 +# Part of loop body line 186, head labeled .Lt_2_13058 + l32i a13,a1,104 # [0] gra_spill_temp_110 + l32i a11,a1,112 # [1] gra_spill_temp_112 + l32i a10,a1,184 # [2] gra_spill_temp_130 + l32i a9,a1,100 # [3] gra_spill_temp_109 + l32i a12,a1,108 # [4] gra_spill_temp_111 + l32i a8,a1,116 # [5] gra_spill_temp_113 + addi.n a12,a12,1 # [6] + s32i a12,a1,108 # [7] gra_spill_temp_111 + sub a8,a8,a9 # [8] + add.n a10,a10,a9 # [9] + sub a11,a11,a9 # [10] + s32i a11,a1,112 # [11] gra_spill_temp_112 + s32i a10,a1,184 # [12] gra_spill_temp_130 + s32i a8,a1,116 # [13] gra_spill_temp_113 + beq a12,a13,.Lt_2_12546 # [14] + +.Lt_2_13058: # 0x821 // channel loop + l32i a12,a1,96 # [0] gra_spill_temp_108 + beqz.n a12,.Lt_2_13314 # [2] + + movi.n a11,0 # [0] + l32i a10,a1,112 # [1] gra_spill_temp_112 + l32i a13,a1,92 # [2] gra_spill_temp_107 + l32i a8,a1,152 # [3] gra_spill_temp_122 + movi.n a9,0 # [4] + l32i a12,a1,88 # [5] gra_spill_temp_106 + s32i a12,a1,168 # [6] gra_spill_temp_126 + s32i a9,a1,188 # [7] gra_spill_temp_131 + s32i a8,a1,164 # [8] gra_spill_temp_125 + s32i a13,a1,172 # [9] gra_spill_temp_127 + l32i a8,a1,116 # [10] gra_spill_temp_113 + l32i a13,a1,196 # [11] gra_spill_temp_133 + max a10,a10,a11 # [12] + s32i a10,a1,208 # [13] gra_spill_temp_136 + min a13,a13,a8 # [14] + s32i a13,a1,200 # [15] gra_spill_temp_134 + j .Lt_2_13826 # [16] + +.Lt_2_14082: # 0x857 + +// extract data + l32i a4,a1,156 # [0] gra_spill_temp_123 + ee.st.qacc_l.l.128.ip a4,16 # [2] id:303 + ee.st.qacc_l.h.32.ip a4,0 # [3] id:304 + l8ui a9,a1,15 # [4] qacc_scratch+15 + l16ui a8,a1,10 # [5] qacc_scratch+10 + l8ui a12,a1,16 # [6] qacc_scratch+16 + l8ui a11,a1,6 # [7] qacc_scratch+6 + l8ui a10,a1,5 # [8] qacc_scratch+5 + s8i a10,a1,2 # [9] qacc_scratch+2 + s8i a11,a1,3 # [10] qacc_scratch+3 + s8i a12,a1,7 # [11] qacc_scratch+7 + s16i a8,a1,4 # [12] qacc_scratch+4 + s8i a9,a1,6 # [13] qacc_scratch+6 + + ee.st.qacc_h.l.128.ip a4,16 # [14] id:314 + ee.st.qacc_h.h.32.ip a4,-32 # [15] id:315 + l8ui a13,a1,32 # [16] qacc_scratch+32 + l8ui a9,a1,21 # [17] qacc_scratch+21 + l8ui a12,a1,31 # [18] qacc_scratch+31 + l16ui a11,a1,26 # [19] qacc_scratch+26 + l8ui a10,a1,22 # [20] qacc_scratch+22 + l16ui a8,a1,16 # [21] qacc_scratch+16 + s16i a8,a1,8 # [22] qacc_scratch+8 + s8i a10,a1,11 # [23] qacc_scratch+11 + s16i a11,a1,12 # [24] qacc_scratch+12 + s8i a12,a1,14 # [25] qacc_scratch+14 + s8i a9,a1,10 # [26] qacc_scratch+10 + s8i a13,a1,15 # [27] qacc_scratch+15 + + l32i a9,a1,152 # [28] gra_spill_temp_122, bias + movi.n a13,16 # [29] + ee.srcmb.s16.qacc q1,a13,0 # [30] + ee.vld.128.ip q0,a4,0 # [31] id:327 + s32i a4,a1,156 # [32] gra_spill_temp_123 + ee.vzip.16 q0,q1 # [33] + ee.vadds.s32 q0,q0,q1 # [34] + ee.movi.32.a q0,a12,3 # [35] + ee.movi.32.a q0,a11,2 # [36] + ee.movi.32.a q0,a10,0 # [37] + add.n a11,a11,a12 # [38] + ee.movi.32.a q0,a12,1 # [39] + add.n a10,a10,a12 # [40] + add.n a10,a10,a11 # [41] + + beqz.n a9,.Lt_2_17154 # [42] // skip bias + + l32i a13,a1,164 # [0] gra_spill_temp_125 + l32i.n a13,a13,0 # [2] id:329 + add.n a10,a10,a13 # [4] +.Lt_2_17154: # 0x8d7 + + # 259 conv_out = esp_nn_multiply_by_quantized_mult(conv_out, out_mult[out_ch_idx], out_shift[out_ch_idx]); + l32i a11,a1,172 # [0] gra_spill_temp_127 + l32i a4,a1,168 # [1] gra_spill_temp_126 + l32i.n a11,a11,0 # [2] id:331 + l32i.n a4,a4,0 # [3] id:330 + + blti a11,1,.LBB26_esp_nn_conv_s16_mult8_esp32s3 # [4] + movi.n a13,0 # [0] + j .Lt_2_17666 # [1] +.LBB26_esp_nn_conv_s16_mult8_esp32s3: # 0xa4e + neg a13,a11 # [0] +.Lt_2_17666: # 0x8e6 + + movi.n a12,0 # [0] + max a12,a11,a12 # [1] + movi.n a11,0 # [2] + ssl a12 # [3] + sll a10,a10 # [4] + bne a10,a4,.Lt_2_20994 # [5] + + l32r a9,.LC10_28_153 # [0] + movi.n a8,1 # [1] + sub a9,a10,a9 # [2] + moveqz a11,a8,a9 # [3] + +.Lt_2_20994: # 0x901 + extui a8,a4,31,1 # [0] + extui a12,a10,31,1 # [1] + xor a12,a12,a8 # [2] + extui a12,a12,0,8 # [3] + + beqz.n a12,.Lt_2_18434 # [4] + movi.n a12,-1 # [0] + l32r a9,.LC11_28_154 # [1] + j .Lt_2_18178 # [2] + +.Lt_2_18434: # 0xa54 + movi.n a12,0 # [0] + l32r a9,.LC13_28_156 # [1] +.Lt_2_18178: # 0x914 + + ssai 31 # [0] + l32r a8,.LC12_28_155 # [1] + mulsh a6,a4,a10 # [2] + mull a4,a4,a10 # [3] + add.n a6,a6,a12 # [4] + add.n a7,a4,a9 # [5] + saltu a4,a7,a4 # [6] + add.n a4,a4,a6 # [7] + srai a6,a4,31 # [8] + and a6,a6,a8 # [9] + add.n a7,a6,a7 # [10] + srai a3,a6,31 # [11] + add.n a3,a3,a4 # [12] + saltu a6,a7,a6 # [13] + add.n a6,a6,a3 # [14] + src a6,a6,a7 # [15] + extui a3,a11,0,8 # [16] + movi.n a7,1 # [17] + ssr a13 # [18] + movnez a6,a8,a3 # [19] + sra a8,a6 # [20] + + addi.n a3,a8,1 # [21] + ssl a13 # [22] + sll a7,a7 # [23] + extui a4,a8,31,1 # [24] + addi.n a7,a7,-1 # [25] + and a6,a6,a7 # [26] + srai a7,a7,1 # [27] + add.n a4,a4,a7 # [28] + l32i a7,a1,164 # [29] gra_spill_temp_125 + salt a4,a4,a6 # [30] + movnez a8,a3,a4 # [31] + l32i a6,a1,172 # [32] gra_spill_temp_127 + l32i a4,a1,132 # [33] gra_spill_temp_117 + l32i a3,a1,160 # [34] gra_spill_temp_124 + addi.n a7,a7,4 # [35] + s32i a7,a1,164 # [36] gra_spill_temp_125 + addi.n a6,a6,4 # [37] + s32i a6,a1,172 # [38] gra_spill_temp_127 + l32i a7,a1,136 # [39] gra_spill_temp_118 + l32i a6,a1,140 # [40] gra_spill_temp_119 + add.n a4,a3,a4 # [41] + add.n a7,a7,a8 # [42] + addi.n a3,a3,1 # [43] + l32i a8,a1,128 # [44] gra_spill_temp_116 + max a6,a6,a7 # [45] + s32i a3,a1,160 # [46] gra_spill_temp_124 + l32i a7,a1,188 # [47] gra_spill_temp_131 + l32i a3,a1,144 # [48] gra_spill_temp_120 + add.n a7,a7,a8 # [49] + min a3,a3,a6 # [50] + s8i a3,a4,0 # [51] id:332 + s32i a7,a1,188 # [52] gra_spill_temp_131 + l32i a4,a1,168 # [53] gra_spill_temp_126 + l32i a6,a1,124 # [54] gra_spill_temp_115 + addi.n a4,a4,4 # [55] + s32i a4,a1,168 # [56] gra_spill_temp_126 + sub a4,a4,a6 # [57] + beqz a4,.Lt_2_13314 # [58] + +.Lt_2_13826: # 0x9b4 + ee.zero.qacc # [0] + l32i a9,a1,204 # [1] gra_spill_temp_135 + l32i a8,a1,148 # [2] gra_spill_temp_121 + s32i a8,a1,212 # [3] gra_spill_temp_137 + bge a8,a9,.Lt_2_14082 # [4] + +.LBB12_esp_nn_conv_s16_mult8_esp32s3: # 0x9c3 +# Part of loop body line 187, head labeled .Lt_2_13826 + l32i a8,a1,196 # [0] gra_spill_temp_133 + l32i a7,a1,212 # [1] gra_spill_temp_137 + l32i a13,a1,200 # [2] gra_spill_temp_134 + mull a7,a7,a8 # [3] + l32i a6,a1,120 # [4] gra_spill_temp_114 + add.n a13,a7,a13 # [5] + j .Lt_2_14594 # [6] + +.Lt_2_14850: # 0x9d7 +# Part of loop body line 201, head labeled .Lt_2_14594 + l32i a9,a1,204 # [0] gra_spill_temp_135 + l32i a10,a1,212 # [1] gra_spill_temp_137 + l32i a12,a1,192 # [2] gra_spill_temp_132 + l32i a11,a1,196 # [3] gra_spill_temp_133 + add.n a6,a6,a12 # [4] + add.n a7,a7,a11 # [5] + add.n a13,a13,a11 # [6] + addi.n a10,a10,1 # [7] + s32i a10,a1,212 # [8] gra_spill_temp_137 + sub a9,a9,a10 # [9] + beqz a9,.Lt_2_14082 # [10] + +.Lt_2_14594: # 0x9f4 + l32i a9,a1,200 # [0] gra_spill_temp_134 + l32i a8,a1,208 # [1] gra_spill_temp_136 + bge a8,a9,.Lt_2_14850 # [3] + + l32i a11,a1,176 # [0] gra_spill_temp_128 + l32i a10,a1,184 # [1] gra_spill_temp_130 + add.n a12,a7,a8 # [2] + add.n a10,a10,a8 # [3] + add.n a10,a6,a10 # [4] + mull a10,a5,a10 # [5] + mull a8,a12,a5 # [6] + addx2 a10,a10,a11 # [7] + l32i a11,a1,188 # [8] gra_spill_temp_131 + add.n a11,a11,a8 # [10] + l32i a8,a1,180 # [11] gra_spill_temp_129 + mov.n a2,a10 # [12] + addx2 a11,a11,a8 # [13] + movi.n a8,8 # [14] + mov.n a3,a11 # [15] + j .Lt_2_15362 # [16] + +.LBB18_esp_nn_conv_s16_mult8_esp32s3: # 0xa26 + loopgtz a15,.LBB54_esp_nn_conv_s16_mult8_esp32s3 # [0] + + ee.vmulas.s16.qacc.ld.ip q0,a2,16,q0,q1 # [0*II+0] id:300 + ee.vld.128.ip q1,a3,16 # [0*II+1] id:301 +.LBB54_esp_nn_conv_s16_mult8_esp32s3: # 0xa30 + +.Lt_2_15618: # 0xa30 + ee.vmulas.s16.qacc q0,q1 # [0] + movi.n a8,8 # [1] + add.n a10,a10,a14 # [2] + add.n a11,a11,a14 # [3] + mov.n a3,a11 # [4] + mov.n a2,a10 # [5] + beq a12,a13,.Lt_2_14850 # [6] + +.Lt_2_15362: # 0xa40 + ee.vld.128.ip q1,a3,16 # [0] id:299 + ee.vld.128.ip q0,a2,16 # [1] id:298 + addi.n a12,a12,1 # [2] + bltu a8,a5,.LBB18_esp_nn_conv_s16_mult8_esp32s3 # [3] + + j .Lt_2_15618 # [0] + +.Lt_2_11778: # 0xa5c + retw.n # [0] + + .size esp_nn_conv_s16_mult8_esp32s3, . - esp_nn_conv_s16_mult8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s8_filter_aligned_input_padded_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s8_filter_aligned_input_padded_esp32s3.S new file mode 100644 index 0000000..5545b27 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s8_filter_aligned_input_padded_esp32s3.S @@ -0,0 +1,271 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// +// SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +// +// SPDX-License-Identifier: Apache-2.0 +// + + +// +// Contraints used by this function are: +// 1. pad_wd and pad_ht is 0. For versions needing padding we do this +// explicitly +// 2. All the filter rows are aligned to 16 bytes boundary. To make sure +// this is indeed the case, for filter rows (filter_wd * channels) not +// multiple of 16, we add zeros to fill it till 16 bondary. +// +// The optimized kernel assumes this and skips filter row with following +// size: ((filter_wd * input_ch) + 15) & ~15. + + .text + +.literal_position + .literal .LC1, 1073741824 + + # Program Unit: esp_nn_conv_s8_filter_aligned_input_padded_esp32s3 + .type esp_nn_conv_s8_filter_aligned_input_padded_esp32s3, @function + .align 4 + .global esp_nn_conv_s8_filter_aligned_input_padded_esp32s3 + // registers: + // a2: const int16_t *input_data + // a3: const uint16_t input_wd + // a4: const uint16_t input_ht + // a5: const uint16_t in_ch + // a6: const uint16_t input_offset + // a7: const uint16_t stride_wd + + // on stack: + // const uint16_t stride_ht : 80 + // const int8_t *filter_data : 84 + // const uint16_t filter_wd : 88 + // const uint16_t filter_ht : 92 + // const int32_t *bias : 96 + // int8_t *out_data : 100 + // const uint16_t out_wd : 104 + // const uint16_t out_ht : 108 + // const uint16_t out_channels : 112 + // const int32_t out_offset : 116 + // const int32_t *out_shift : 120 + // const int32_t *out_mult : 124 + // const int32_t activation_min: 128 + // const int32_t activation_max: 132 + // void *scratch_buffer: 136 + +esp_nn_conv_s8_filter_aligned_input_padded_esp32s3: + entry sp, 80 + s32i.n a2, sp, 40 # input_data + mov a11, a6 # input_offset + l16ui a2, sp, 88 # filter_wd + l32i a8, sp, 100 # out_data + l16ui a6, sp, 80 # stride_ht + mov.n a15, a5 + + mull a4, a2, a15 # filter_row_sz + s32i.n a8, sp, 24 # out_data_ptr + movi.n a9, 0 + s32i.n a9, sp, 36 # out_y + + addi.n a4, a4, 15 # to round the size up + srli a2, a4, 4 # (filter_row_sz) >> 4 + slli a12, a2, 4 # ((filter_row_sz) >> 4) << 4 + + mull a4, a6, a3 # stride_ht * input_wd + mull a5, a3, a15 # input_wd * in_ch + l32i.n a10, sp, 112 # out_ch + + mull a9, a7, a15 # stride_wd * in_ch + mull a4, a4, a15 # (stride_ht * input_wd) * in_ch + + slli a3, a10, 2 # out_ch * 4 + + s32i.n a3, sp, 32 # out_ch * 4 + s32i.n a5, sp, 12 # input_wd * in_ch + s32i.n a9, sp, 52 # stride_wd * in_ch + s32i a4, sp, 56 # (stride_ht * input_wd) * in_ch + + l32i.n a3, sp, 92 # filter_ht + l32i a13, sp, 136 # scratch_buf + l32i a5, sp, 84 # filter_data + mull a4, a12, a3 # (filter_wd * filter_ht * in_ch) + srai a4, a4, 1 + addx4 a10, a10, a13 # scratch_buf + 4 * out_ch + l32i a3, sp, 96 + // accumulate filter values per channel into scratch buffer +.L_acc_out_channel_loop: + movi.n a9, 0 // acc + loop a4, .L_acc_filter_size_loop + l8ui a14, a5, 0 + l8ui a7, a5, 1 + addi.n a5, a5, 2 + sext a14, a14, 7 + sext a7, a7, 7 + add a9, a9, a14 + add a9, a9, a7 + .L_acc_filter_size_loop: + + // multiply by offset, add bias and store the acc value per channel + mull a9, a9, a11 + beqz.n a3, .L_skip_bias + l32i a8, a3, 0 + addi a3, a3, 4 // this will remain 0 if bias not present + add a9, a9, a8 +.L_skip_bias: + s32i a9, a13, 0 + addi.n a13, a13, 4 + blt a13, a10, .L_acc_out_channel_loop + + movi.n a4, 0 # 0 + +.L_height_loop: + l32i.n a8, sp, 40 # in_row_ptr + movi.n a9, 0 + l32i.n a10, sp, 104 # out_wd + s32i.n a8, sp, 28 # input_ptr + s32i.n a9, sp, 44 # out_x + +.L_width_loop: + movi.n a9, 0 + l32i a5, sp, 84 # filter_data + s32i.n a9, sp, 20 + l32i a3, sp, 136 # scratch_buf + +.L_out_ch_loop: + movi.n a6, 0 + l32i.n a9, sp, 28 # input_ptr + mov.n a10, a6 + +.L_filter_ht_loop: + add.n a8, a5, a12 + mov.n a13, a9 + + ee.zero.accx + ee.ld.128.usar.ip q0, a13, 16 + ee.vld.128.ip q4, a13, 16 + ee.vld.128.ip q1, a5, 16 + + sub a15, a8, a5 // row_len - 16 + extui a14, a15, 4, 1 // if multiple of 16 and not 32 + srai a15, a15, 5 // multiples of 32 + ee.src.q.qup q2, q0, q4 + beqz a15, .L_vector_32_loop_end + + loop a15, .L_vector_32_loop_end + + ee.vld.128.ip q4, a13, 16 + ee.vmulas.s8.accx.ld.ip.qup q3, a5, 16, q2, q1, q0, q4 + ee.vld.128.ip q2, a13, 16 + ee.vmulas.s8.accx.ld.ip.qup q1, a5, 16, q0, q3, q4, q2 + ee.orq q0, q2, q2 + ee.orq q2, q4, q4 + +.L_vector_32_loop_end: + beqz a14, .L_vector_loop_end + ee.vmulas.s8.accx.ld.ip q4, a13, 16, q2, q1 + ee.src.q.ld.ip q1, a5, 16, q0, q4 + ee.orq q2, q0, q0 + +.L_vector_loop_end: + ee.vmulas.s8.accx q2, q1 + addi a13, a13, -16 // since we incremented by 16 too much + movi a15, 0 + ee.srs.accx a14, a15, 0 + + mov.n a5, a8 + add.n a6, a6, a14 +.L7: + l32i.n a8, sp, 12 # input_wd * in_ch + l32i.n a2, sp, 92 # filter_ht + addi.n a10, a10, 1 # filter_y_idx + add.n a9, a9, a8 + blt a10, a2, .L_filter_ht_loop +.L9: + l32i a7, a3, 0 # load input_offset acc + addi a3, a3, 4 # increment offset acc ptr + l32i.n a8, sp, 20 + add.n a6, a6, a7 # add input_offset accumulation + +.L_multiply_by_quant_mult: + l32i a10, sp, 120 + l32i a9, sp, 124 + add.n a2, a10, a8 + l32i.n a2, a2, 0 + add.n a7, a9, a8 + l32i.n a7, a7, 0 + max a8, a2, a4 + ssl a8 + sll a6, a6 + mull a9, a6, a7 + l32r a10, .LC1 + sub a2, a8, a2 + add.n a8, a9, a10 + mulsh a6, a6, a7 + movi.n a7, 1 + bltu a8, a9, .L13 + movi.n a7, 0 + +.L13: + add.n a6, a7, a6 + slli a6, a6, 1 + extui a8, a8, 31, 1 + or a6, a6, a8 + beqz.n a2, .L_skip_div_by_pow_of_2 + addi.n a7, a2, -1 + movi.n a9, 1 + extui a8, a6, 31, 1 + ssl a7 + sll a7, a9 + sub a7, a7, a8 + add.n a6, a7, a6 + ssr a2 + sra a6, a6 +.L_skip_div_by_pow_of_2: + l32i a10, sp, 116 + l32i a8, sp, 128 + add.n a2, a10, a6 + l32i a9, sp, 132 + l32i.n a10, sp, 24 # out_data_ptr + max a2, a2, a8 + min a2, a2, a9 + s8i a2, a10, 0 + l32i.n a2, sp, 20 + addi.n a10, a10, 1 + addi.n a2, a2, 4 + l32i.n a6, sp, 32 + s32i.n a2, sp, 20 + s32i.n a10, sp, 24 # out_data_ptr + bne a6, a2, .L_out_ch_loop + +.L4: + l32i.n a5, sp, 44 # out_x + l32i.n a6, sp, 28 # input_ptr (was stored by height loop) + l32i.n a8, sp, 52 # stride_wd * in_ch + addi.n a5, a5, 1 + add.n a6, a6, a8 # input_ptr + stride_wd * in_ch + l32i.n a9, sp, 104 # out_wd + s32i.n a5, sp, 44 # out_x + s32i.n a6, sp, 28 # input_ptr + bne a9, a5, .L_width_loop + + l32i.n a10, sp, 36 # out_y + l32i.n a2, sp, 40 # in_row_ptr + l32i a5, sp, 56 # (stride_ht * input_wd) * in_ch + l32i.n a6, sp, 108 # out_ht + addi.n a10, a10, 1 + add.n a2, a2, a5 # in_row_ptr + s32i.n a10, sp, 36 # out_y + s32i.n a2, sp, 40 # in_row_ptr + blt a10, a6, .L_height_loop + // end outer (height) loop + retw.n + + .size esp_nn_conv_s8_filter_aligned_input_padded_esp32s3, .-esp_nn_conv_s8_filter_aligned_input_padded_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s8_mult8_1x1_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s8_mult8_1x1_esp32s3.S new file mode 100644 index 0000000..111fd08 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_conv_s8_mult8_1x1_esp32s3.S @@ -0,0 +1,497 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + .literal .nudge_val, 1073741824 + + # Program Unit: esp_nn_conv_s8_mult8_1x1_esp32s3 + .type esp_nn_conv_s8_mult8_1x1_esp32s3, @function + .align 4 + .global esp_nn_conv_s8_mult8_1x1_esp32s3 + +esp_nn_conv_s8_mult8_1x1_esp32s3: # 0xdbc + # scratch_buf = 0 // to store qacc regs need 36 bytes + # gra_spill_temp_164 = 36, channel itr, (in_channels - 1) >> 3 + # gra_spill_temp_165 = 40, i_out + # gra_spill_temp_166 = 44, in_channels + # gra_spill_temp_167 = 48, in_channels/8 - 1 + # gra_spill_temp_168 = 52, in_channels-7 + # gra_spill_temp_169 = 56, input + # gra_spill_temp_170 = 60, filter_data + # gra_spill_temp_171 = 64, input_offset + # gra_spill_temp_172 = 68, input_ptr + # gra_spill_temp_173 = 72, bias + # gra_spill_temp_174 = 76, in_channels*8 + # gra_spill_temp_175 = 80, size-7 + # gra_spill_temp_176 = 84, size + + // registers: + // a2: int8_t *input_data + // a3: uint16_t input_wd + // a4: uint16_t input_ht + // a5: uint16_t in_channels + // a6: int32_t input_offset + // a7: int16_t *filter_data + + // on stack: + // int32_t *bias // 160 + // int8_t *out_data // 164 + // uint16_t out_wd // 168 + // uint16_t out_ht // 172 + // uint16_t out_channels // 176 + // int32_t out_offset // 180 + // int32_t *out_shift // 184 + // int32_t *out_mult // 188 + // int32_t activation_min // 192 + // int32_t activation_max // 196 + // void *buffer // tmp buf // 200 + + entry a1,160 # + s32i a5,a1,44 # [0] gra_spill_temp_166, in_channels + s32i a6,a1,64 # [2] id:619 input_offset+0x0 + s32i a7,a1,60 # [1] gra_spill_temp_170, filter_data + mul16u a8,a3,a4 # [3] size = input_wd * input_ht; + s32i a2,a1,56 # [0] gra_spill_temp_169, input + l32i a4,a1,164 # [1] id:624 out_data+0x0 + mov.n a3,a1 # [52] scratch_buf + + s32i a8,a1,84 # [4] gra_spill_temp_176, size + blti a8,8,.prepare_leftover # [5] // process remaining lines one by one + addi a9,a8,-7 # [32] + s32i a9,a1,80 # [33] gra_spill_temp_175, size-7 + + s32i a2,a1,68 # [2] gra_spill_temp_172 , input_ptr + srai a15,a5,3 # [7] `in_ch/8` loop_cnt + movi.n a11,0 # [10] + s32i a11,a1,40 # [11] gra_spill_temp_165 + addi a15,a15,-1 # [17] `in_ch/8` loop_cnt - 1 + s32i a15,a1,48 # [18] gra_spill_temp_167 + slli a9,a5,3 # [19] in_channels*8 + s32i a9,a1,76 # [20] gra_spill_temp_174 + addi a15,a5,-7 # [31] + s32i a15,a1,52 # [34] gra_spill_temp_168 + +.outer_loop: // for (; i_out < size - 7; i_out += 8) { + + l32i a10,a1,200 # [1] gra_spill_temp_165, buffer + l32i.n a11,a1,44 # [1] gra_spill_temp_166, input_channels + l32i.n a8,a1,68 # [2] gra_spill_temp_172, input_ptr + srai a9,a11,3 # [7] `in_ch/8` loop_cnt for transpose loop + + ee.zero.q q7 # [0] + addi a12,a1,64 # [6] + ee.vldbc.16 q5,a12 # [0*II+16] id:638 input_offset + + // load and transose 8 lines of input 8xchannels, + // add input offset and store 16 bit data to tmp buffer + loopgtz a9,.transpose_loop_end # [10] + mov.n a9,a8 + ee.vld.l.64.xp q0,a9,a11 + ee.vld.l.64.xp q1,a9,a11 + ee.vld.h.64.xp q0,a9,a11 + ee.vld.h.64.xp q1,a9,a11 + ee.vld.l.64.xp q2,a9,a11 + ee.vzip.8 q0,q1 + ee.vld.l.64.xp q3,a9,a11 + ee.vld.h.64.xp q2,a9,a11 + ee.vld.h.64.ip q3,a9,0 + ee.vzip.16 q0,q1 + ee.vzip.8 q2,q3 + ee.vzip.16 q2,q3 + ee.vzip.32 q0,q2 + ee.vcmp.lt.s8 q4,q2,q7 + ee.vzip.8 q2,q4 + ee.vcmp.lt.s8 q6,q0,q7 + ee.vzip.8 q0,q6 + ee.vadds.s16 q0,q0,q5 + ee.vadds.s16.st.incp q0,a10,q6,q6,q5 + ee.vadds.s16.st.incp q6,a10,q2,q2,q5 + ee.vadds.s16.st.incp q2,a10,q4,q4,q5 + ee.vst.128.ip q4,a10,16 + ee.vzip.32 q1,q3 + ee.vcmp.lt.s8 q4,q3,q7 + ee.vzip.8 q3,q4 + ee.vcmp.lt.s8 q6,q1,q7 + ee.vzip.8 q1,q6 + ee.vadds.s16 q1,q1,q5 + ee.vadds.s16.st.incp q1,a10,q6,q6,q5 + ee.vadds.s16.st.incp q6,a10,q3,q3,q5 + ee.vadds.s16.st.incp q3,a10,q4,q4,q5 + ee.vst.128.ip q4,a10,16 + addi.n a8,a8,8 +.transpose_loop_end: # 0xeeb + + # 468 uint32_t bias_ptr = (uint32_t) bias; + # 469 uint32_t filter_ptr = (uint32_t) (filter_data); + # 470 const int32_t *out_mult_ptr = out_mult; + # 471 const int32_t *out_shift_ptr = out_shift; + l32i a6,a1,184 # [0] out_shift + l32i a2,a1,188 # [1] out_mult + l32i a5,a1,60 # [2] gra_spill_temp_170, filter + l32i a9,a1,160 # [3] gra_spill_temp_170, bias + # 472 for (int32_t out_ch_idx = 0; out_ch_idx < out_channels; out_ch_idx++) { + l16ui a8,a1,176 # [5] id:620 out_channels+0x0 + s32i a9,a1,72 # [5] gra_spill_temp_173 + blti a8,1,.outer_ch_loop_end + + movi.n a7,0 + +.out_ch_loop: # 0xf3e + l32i a8,a1,200 # [4] gra_spill_temp_165, buffer_ptr + ee.zero.qacc # [3] + ee.zero.q q5 # + l32i a10,a1,52 # [1] gra_spill_temp_168, in_channels-7 + l32i a9,a1,48 # [1] gra_spill_temp_167, in_channels/8 - 1 + ee.vld.l.64.ip q7,a5,8 # load filter 8 values + ee.vld.128.ip q0,a8,16 + ee.vld.128.ip q1,a8,16 + ee.vcmp.lt.s8 q6,q7,q5 + ee.vzip.8 q7,q6 + + ee.vsmulas.s16.qacc.ld.incp q2,a8,q0,q7,0 + ee.vsmulas.s16.qacc.ld.incp q3,a8,q1,q7,1 + ee.vsmulas.s16.qacc.ld.incp q0,a8,q2,q7,2 + ee.vsmulas.s16.qacc.ld.incp q1,a8,q3,q7,3 + ee.vsmulas.s16.qacc.ld.incp q2,a8,q0,q7,4 + ee.vsmulas.s16.qacc.ld.incp q3,a8,q1,q7,5 + blti a10,8,.inner_loop_end # [16] + + loopgtz a9,.inner_loop_end # [3] + + ee.vsmulas.s16.qacc.ld.incp q0,a8,q2,q7,6 # [0*II+0] id:657 + ee.vsmulas.s16.qacc.ld.incp q1,a8,q3,q7,7 # [0*II+1] id:658 + ee.vld.l.64.ip q7,a5,8 # [0*II+2] id:659, filter + ee.vcmp.lt.s8 q6,q7,q5 + ee.vzip.8 q7,q6 + ee.vsmulas.s16.qacc.ld.incp q2,a8,q0,q7,0 # [0*II+4] id:660 + ee.vsmulas.s16.qacc.ld.incp q3,a8,q1,q7,1 # [0*II+5] id:661 + ee.vsmulas.s16.qacc.ld.incp q0,a8,q2,q7,2 # [0*II+6] id:662 + ee.vsmulas.s16.qacc.ld.incp q1,a8,q3,q7,3 # [0*II+7] id:663 + ee.vsmulas.s16.qacc.ld.incp q2,a8,q0,q7,4 # [0*II+8] id:664 + ee.vsmulas.s16.qacc.ld.incp q3,a8,q1,q7,5 # [0*II+9] id:665 +.inner_loop_end: # 0xfaf + + ee.vsmulas.s16.qacc q2,q7,6 # [2] + ee.vsmulas.s16.qacc q3,q7,7 # [3] + + # store qacc registers and re-arrange data for low 16 bits + + ee.st.qacc_l.l.128.ip a3,16 # [5] id:668 + ee.st.qacc_l.h.32.ip a3,-16 # [6] id:669 + l32i.n a10, a1, 0 + l32i.n a11, a1, 5 + l32i.n a12, a1, 10 + l32i.n a13, a1, 15 + ee.movi.32.q q0, a10, 0 + ee.movi.32.q q0, a11, 1 + ee.movi.32.q q0, a12, 2 + ee.movi.32.q q0, a13, 3 + + ee.st.qacc_h.l.128.ip a3,16 # [5] id:668 + ee.st.qacc_h.h.32.ip a3,-16 # [6] id:669 + l32i.n a10, a1, 0 + l32i.n a11, a1, 5 + l32i.n a12, a1, 10 + l32i.n a13, a1, 15 + ee.movi.32.q q4, a10, 0 + ee.movi.32.q q4, a11, 1 + ee.movi.32.q q4, a12, 2 + ee.movi.32.q q4, a13, 3 + + l32i a9,a1,160 # [17] gra_spill_temp_170, bias + l32i a10,a1,72 # [0] gra_spill_temp_173, bias_ptr + + # add bias + beqz.n a9,.no_bias + ee.vldbc.32.ip q6,a10,4 + s32i a10,a1,72 # [3] gra_spill_temp_173, bias_ptr + ee.vadds.s32 q0,q0,q6 # [4] + ee.vadds.s32 q4,q4,q6 # [5] +.no_bias: # 0x102e + + l32i.n a11,a6,0 # [1] id:696 + l32i.n a10,a2,0 # [3] id:695 + .global esp_nn_multiply_by_quantized_mult_asm_esp32s3 + call8 esp_nn_multiply_by_quantized_mult_asm_esp32s3 # [4] esp_nn_multiply_by_quantized_mult_asm_esp32s3 + + l32i.n a10,a2,0 # [0] id:697, mult + l32i.n a11,a6,0 # [2] id:698, shift + mv.qr q5,q0 + mv.qr q0,q4 + call8 esp_nn_multiply_by_quantized_mult_asm_esp32s3 # [5] esp_nn_multiply_by_quantized_mult_asm_esp32s3 + + addi.n a6,a6,4 # out_shift_ptr++ + addi.n a2,a2,4 # out_mult_ptr++ + addi a9,a1,180 # [7] + addi a10,a1,192 # [5] + addi a8,a1,196 # [6] + +# load broadcast, activation and out_offset + ee.vldbc.32 q4,a9 # [14] id:699 out_offset + ee.vldbc.32 q2,a10 # [11] id:700 activation_min + ee.vldbc.32 q3,a8 # [12] id:701 activation_max + +# add offset + ee.vadds.s32 q1,q0,q4 # [17] + ee.vadds.s32 q0,q5,q4 # [22] + + # activation + ee.vmin.s32 q1,q1,q3 # [19] + ee.vmax.s32 q1,q1,q2 # [21] + ee.vmin.s32 q0,q0,q3 # [23] + ee.vmax.s32 q0,q0,q2 # [24] + + l16ui a9,a1,176 # [33] out_channels + +# unzip and store + ee.vunzip.16 q0,q1 # [25] + ee.vst.128.ip q0,a3,0 # [26] id:702, scratch_buf + + # a4 = out_data, out_channels = a1+176 + + l8ui a14,a1,0 # [27] + l8ui a11,a1,2 # [30] scratch_buf+2 + add a10,a4,a9 + s8i a14,a4,0 # [28], out_data + s8i a11,a10,0 # [31], out_data + out_channels + + l8ui a14,a1,4 # [32] scratch_buf+4 + l8ui a11,a1,6 # [37] scratch_buf+6 + add a12,a10,a9 + add a10,a12,a9 + s8i a14,a12,0 # [28] + s8i a11,a10,0 # [31] + + l8ui a14,a1,8 # [41] scratch_buf+8 + l8ui a11,a1,10 # [47] scratch_buf+10 + add a12,a10,a9 + add a10,a12,a9 + s8i a14,a12,0 # [28] + s8i a11,a10,0 # [31] + + l8ui a14,a1,12 # [51] scratch_buf+12 + l8ui a11,a1,14 # [55] scratch_buf+14 + add a12,a10,a9 + add a10,a12,a9 + s8i a14,a12,0 # [28] + s8i a11,a10,0 # [31] + + addi.n a4,a4,1 # [29] out_data++; + addi.n a7,a7,1 + bne a7,a9,.out_ch_loop + +.outer_ch_loop_end: + + subx8 a11,a9,a9 # (7 * out_channels); + l32i a10,a1,76 # [1] gra_spill_temp_174, in_channels * 8 + l32i a15,a1,40 # [4] gra_spill_temp_165 + l32i a9,a1,68 # [2] gra_spill_temp_172 + l32i a8,a1,80 # [0] gra_spill_temp_175, size-7 + add.n a4,a4,a11 # [5] out_data += (7 * out_channels); + addi.n a15,a15,8 + s32i a15,a1,40 # [7] gra_spill_temp_165 + add.n a9,a9,a10 # [8] + s32i a9,a1,68 # [9] gra_spill_temp_172 + blt a15,a8,.outer_loop # [10] + + # check if leftover + l32i a15,a1,40 + l32i a13,a1,84 # [1] gra_spill_temp_176, size + l32i a8,a1,44 # [0] gra_spill_temp_166, in_channels + bge a15, a13, .return_function # no leftover + +// This block below processes one input channel line at a time. +.process_leftover: + l32i a15,a1,40 # [1] gra_spill_temp_165, i_out + l32i a14,a1,56 # [2] gra_spill_temp_169, input + mull a15,a15,a8 # [3] in_channels * i_out + addi.n a8,a8,-1 # [4] in_channels - 1 + add.n a14,a14,a15 # [5] input_ptr = in_channels * i_out + input + srai a8,a8,3 # [6] iterations, (in_channels - 1) >> 3 + s32i a8,a1,36 # [7] gra_spill_temp_164, iterations + s32i a14,a1,68 # [8] gra_spill_temp_172, in_channels * i_out + input + addi a12,a1,64 + ee.vldbc.16 q4,a12 # [8] id:716 input_offset + +.leftover_outer_loop: + + l32i a15,a1,184 # [0] out_shift + l32i a2,a1,188 # [1] out_mult + l32i a8,a1,60 # [3] gra_spill_temp_170, filter_data + l32i a5,a1,160 # [0] gra_spill_temp_170, bias + movi.n a11,0 # [2] + +.leftover_out_ch_loop: + + ee.zero.qacc # [0] + ee.zero.q q3 # [1] + l32i.n a9,a1,68 # [4] gra_spill_temp_172, input_ptr + l32i a10,a1,36 # [1] gra_spill_temp_164, iterations, (in_channels - 1) >> 3 + ee.vld.l.64.ip q0,a9,8 # [7] id:717, input + ee.vld.l.64.ip q1,a8,8 # [7] filter + ee.vcmp.lt.s8 q6,q0,q3 + ee.vcmp.lt.s8 q7,q1,q3 + ee.vzip.8 q0,q6 + ee.vzip.8 q1,q7 + ee.vadds.s16 q0,q0,q4 # [11] id:718, add offset + + loopgtz a10,.leftover_inner_loop_end # [3] + + ee.vmulas.s16.qacc q0,q1 # mula(q0,q1) + ee.vld.l.64.ip q0,a9,8 # load 8 input values + ee.vld.l.64.ip q1,a8,8 # [7] load filter + ee.vcmp.lt.s8 q2,q0,q3 # sign + ee.vcmp.lt.s8 q7,q1,q3 + ee.vzip.8 q0,q2 # 16 bit input + ee.vzip.8 q1,q7 # 16 bit filter + ee.vadds.s16 q0,q0,q4 # add offset +.leftover_inner_loop_end: # 0x1262 + +# re-arrange data from qacc in 32 bit q registers + ee.vmulas.s16.qacc q0,q1 # [3] + ee.st.qacc_l.l.128.ip a3,16 # [5] id:722 + ee.st.qacc_l.h.32.ip a3,0 # [6] id:723 + l8ui a10,a1,5 # [11] scratch_buf+5 + l8ui a12,a1,6 # [10] scratch_buf+6 + l16ui a14,a1,10 # [8] scratch_buf+10 + l8ui a9,a1,15 # [7] scratch_buf+15 + l8ui a13,a1,16 # [9] scratch_buf+16 + s8i a10,a1,2 # [12] scratch_buf+2 + s8i a12,a1,3 # [13] scratch_buf+3 + s16i a14,a1,4 # [15] scratch_buf+4 + s8i a9,a1,6 # [16] scratch_buf+6 + s8i a13,a1,7 # [14] scratch_buf+7 + + ee.st.qacc_h.l.128.ip a3,16 # [17] id:724 + ee.st.qacc_h.h.32.ip a3,-32 # [18] id:725 + l16ui a13,a1,16 # [30] scratch_buf+16 + l8ui a14,a1,21 # [23] scratch_buf+21 + l8ui a9,a1,22 # [22] scratch_buf+22 + l16ui a10,a1,26 # [21] scratch_buf+26 + s16i a13,a1,8 # [31] scratch_buf+8 + l8ui a12,a1,31 # [20] scratch_buf+31 + l8ui a13,a1,32 # [19] scratch_buf+32 + s8i a14,a1,10 # [24] scratch_buf+10 + s8i a9,a1,11 # [25] scratch_buf+11 + s16i a10,a1,12 # [26] scratch_buf+12 + s8i a12,a1,14 # [27] scratch_buf+14 + s8i a13,a1,15 # [28] scratch_buf+15 + movi.n a12,16 + +# get data now + ee.vld.128.ip q0,a3,0 + ee.srcmb.s16.qacc q1,a12,0 + ee.vzip.16 q0,q1 + + ee.vadds.s32 q0,q0,q1 + ee.movi.32.a q0,a10,3 + ee.movi.32.a q0,a9,2 + ee.movi.32.a q0,a14,0 + add a9,a9,a10 + ee.movi.32.a q0,a10,1 + add a14,a14,a10 + add a14,a14,a9 + +# a14 contains conv_out + l32i a9,a1,160 # [43] gra_spill_temp_170, bias ptr + l32i.n a6,a15,0 # [44] id:730, shift + beqz.n a9,.leftover_multiply_by_quant_mult # [45] + +# load and add bias + l32i.n a9,a5,0 + add.n a14,a14,a9 + +.leftover_multiply_by_quant_mult: # 0x12e7 + l32i.n a9,a2,0 # [0] id:729, mult + movi.n a10,0 # [1] + max a10,a6,a10 # [2] left_shift + ssl a10 # [3] + sll a14,a14 # [4] (value << left_shift) + + sub a7,a10,a6 # right_shift + + l32r a13,.nudge_val + mulsh a12,a9,a14 + mull a14,a9,a14 + ssai 31 + + addi.n a2,a2,4 # [0] mult + addi.n a15,a15,4 # [1] shift + addi.n a5,a5,4 # [2] bias + addi.n a11,a11,1 # [3] + + add a13,a14,a13 # low part + saltu a14,a13,a14 + add a9,a12,a14 # high part + src a12,a9,a13 + + blti a7,1,.leftover_skip_div_by2 + + addi.n a14,a7,-1 + ssl a14 + movi.n a10,1 + sll a10,a10 # 1 << (exponent - 1) + extui a14,a12,31,1 + ssr a7 + sub a10,a10,a14 # 1 << (exponent - 1) - (val < 0) + add a12,a12,a10 # val += to_add + sra a12,a12 + +.leftover_skip_div_by2: + l32i a10,a1,180 # [26] id:733 out_offset+0x0 + l32i a9,a1,192 # [29] id:732 activation_min+0x0 + l16ui a13,a1,176 # [5] id:620 out_channels+0x0 + l32i a14,a1,196 # [31] id:731 activation_max+0x0 + +// add offset, apply activation and store + add.n a10,a10,a12 + max a9,a9,a10 + min a14,a14,a9 + s8i a14,a4,0 + addi.n a4,a4,1 + + bne a11,a13,.leftover_out_ch_loop + + l32i a15,a1,44 # [0] gra_spill_temp_166, in_channels + l32i a14,a1,68 # [1] gra_spill_temp_172, input_ptr + l32i a13,a1,40 # [2] gra_spill_temp_165, i_out + l32i a12,a1,84 # [3] gra_spill_temp_176, size + addi.n a13,a13,1 # [4] + s32i a13,a1,40 # [5] gra_spill_temp_165, i_out + add a14,a14,a15 # [7] input_ptr += in_channels + s32i a14,a1,68 # [8] gra_spill_temp_172, input_ptr + blt a13,a12,.leftover_outer_loop + +.return_function: + retw.n # [9] + +.prepare_leftover: + l32i a8,a1,44 # [0] gra_spill_temp_166, in_channels + movi.n a15,0 + s32i a15,a1,40 # [7] gra_spill_temp_165, i_out + j .process_leftover + + .size esp_nn_conv_s8_mult8_1x1_esp32s3, . - esp_nn_conv_s8_mult8_1x1_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_ansi.c new file mode 100644 index 0000000..10c31b9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_ansi.c @@ -0,0 +1,104 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +int esp_nn_get_depthwise_conv_scratch_size_ansi(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const dw_conv_params_t *conv_params) +{ + return 0; +} + +void esp_nn_set_depthwise_conv_scratch_buf_ansi(const void *buf) +{ + +} + +void esp_nn_depthwise_conv_s8_ansi(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const dw_conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const int32_t *out_shift = quant_data->shift; + const int32_t *out_mult = quant_data->mult; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + const uint16_t ch_mult = conv_params->ch_mult; + + int out_idx = 0; + for (int out_y = 0; out_y < out_ht; out_y++) { //height loop + const int16_t base_y = (out_y * stride_ht) - pad_ht; + for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + const int16_t base_x = (out_x * stride_wd) - pad_wd; + for (int ch_idx = 0; ch_idx < channels; ch_idx++) {//channel_loop + for (int ch_mult_idx = 0; ch_mult_idx < ch_mult; ch_mult_idx++) { + int32_t result = 0; + const int out_ch_idx = ch_mult_idx + ch_idx * ch_mult; + + /* Select filter so as the point doesn't lie outside block */ + int filter_y_start = max(0, -base_y); + int filter_x_start = max(0, -base_x); + int filter_y_end = min(filter_ht, input_ht - base_y); + int filter_x_end = min(filter_wd, input_wd - base_x); + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * (channels * ch_mult) + out_ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val = filter_data[filter_index]; + result += input_val * filter_val; + } + } + if (bias) { + result += bias[out_ch_idx]; + } + result = esp_nn_multiply_by_quantized_mult(result, out_mult[out_ch_idx], out_shift[out_ch_idx]); + result += out_offset; + result = max(result, activation_min); + result = min(result, activation_max); + + out_data[out_idx++] = result; + } + } + } + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_opt.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_opt.c new file mode 100644 index 0000000..e0cc29d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_opt.c @@ -0,0 +1,295 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +int esp_nn_get_depthwise_conv_scratch_size_opt(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const dw_conv_params_t *conv_params) +{ + return 0; +} + +void esp_nn_set_depthwise_conv_scratch_buf_opt(const void *buf) +{ + +} + +/* common channel multiplier == 1 case */ +__attribute__ ((noinline)) +static void esp_nn_depthwise_conv_s8_ch_mult_1(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const dw_conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + + int out_idx = 0; + for (int out_y = 0; out_y < out_ht; out_y++) { //height loop + const int16_t base_y = (out_y * stride_ht) - pad_ht; + for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + const int16_t base_x = (out_x * stride_wd) - pad_wd; + + const int32_t *out_shift = quant_data->shift; + const int32_t *out_mult = quant_data->mult; + + /* Select filter so as the point doesn't lie outside block */ + int filter_y_start = max(0, -base_y); + int filter_x_start = max(0, -base_x); + int filter_y_end = min(filter_ht, input_ht - base_y); + int filter_x_end = min(filter_wd, input_wd - base_x); + + int ch_idx = 0; + for (; ch_idx < channels - 3; ch_idx += 4) {//channel_loop + int32_t result0 = 0; + int32_t result1 = 0; + int32_t result2 = 0; + int32_t result3 = 0; + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * (channels) + ch_idx; + int32_t input_val0 = input_data[input_index + 0] + input_offset; + int32_t input_val1 = input_data[input_index + 1] + input_offset; + int32_t input_val2 = input_data[input_index + 2] + input_offset; + int32_t input_val3 = input_data[input_index + 3] + input_offset; + int32_t filter_val0 = filter_data[filter_index + 0]; + int32_t filter_val1 = filter_data[filter_index + 1]; + int32_t filter_val2 = filter_data[filter_index + 2]; + int32_t filter_val3 = filter_data[filter_index + 3]; + result0 += input_val0 * filter_val0; + result1 += input_val1 * filter_val1; + result2 += input_val2 * filter_val2; + result3 += input_val3 * filter_val3; + } + } + if (bias) { + result0 += bias[ch_idx + 0]; + result1 += bias[ch_idx + 1]; + result2 += bias[ch_idx + 2]; + result3 += bias[ch_idx + 3]; + } + result0 = esp_nn_multiply_by_quantized_mult_fast(result0, *out_mult++, *out_shift++); + result1 = esp_nn_multiply_by_quantized_mult_fast(result1, *out_mult++, *out_shift++); + result2 = esp_nn_multiply_by_quantized_mult_fast(result2, *out_mult++, *out_shift++); + result3 = esp_nn_multiply_by_quantized_mult_fast(result3, *out_mult++, *out_shift++); + + result0 += out_offset; + result1 += out_offset; + result2 += out_offset; + result3 += out_offset; + + result0 = max(result0, activation_min); + result1 = max(result1, activation_min); + result2 = max(result2, activation_min); + result3 = max(result3, activation_min); + + result0 = min(result0, activation_max); + result1 = min(result1, activation_max); + result2 = min(result2, activation_max); + result3 = min(result3, activation_max); + + out_data[out_idx++] = result0; + out_data[out_idx++] = result1; + out_data[out_idx++] = result2; + out_data[out_idx++] = result3; + } + for (; ch_idx < channels; ch_idx++) {//channel_loop + int32_t result = 0; + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * (channels) + ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val = filter_data[filter_index]; + result += input_val * filter_val; + } + } + if (bias) { + result += bias[ch_idx]; + } + result = esp_nn_multiply_by_quantized_mult_fast(result, *out_mult++, *out_shift++); + result += out_offset; + result = max(result, activation_min); + result = min(result, activation_max); + + out_data[out_idx++] = result; + } + } + } +} + +void esp_nn_depthwise_conv_s8_opt(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const dw_conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + const uint16_t ch_mult = conv_params->ch_mult; + if (ch_mult == 1) { + esp_nn_depthwise_conv_s8_ch_mult_1(input_dims, input_data, filter_dims, filter_data, + bias, output_dims, out_data, conv_params, quant_data); + return; + } + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + + int out_idx = 0; + for (int out_y = 0; out_y < out_ht; out_y++) { //height loop + const int16_t base_y = (out_y * stride_ht) - pad_ht; + for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + const int16_t base_x = (out_x * stride_wd) - pad_wd; + + const int32_t *out_shift = quant_data->shift; + const int32_t *out_mult = quant_data->mult; + + /* Select filter so as the point doesn't lie outside block */ + int filter_y_start = max(0, -base_y); + int filter_x_start = max(0, -base_x); + int filter_y_end = min(filter_ht, input_ht - base_y); + int filter_x_end = min(filter_wd, input_wd - base_x); + + for (int ch_idx = 0; ch_idx < channels; ch_idx++) {//channel_loop + int ch_mult_idx = 0; + for (; ch_mult_idx < ch_mult - 3; ch_mult_idx += 4) { + int32_t result0 = 0; + int32_t result1 = 0; + int32_t result2 = 0; + int32_t result3 = 0; + const int out_ch_idx = ch_idx * ch_mult + ch_mult_idx; + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * (channels * ch_mult) + out_ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val0 = filter_data[filter_index + 0]; + int32_t filter_val1 = filter_data[filter_index + 1]; + int32_t filter_val2 = filter_data[filter_index + 2]; + int32_t filter_val3 = filter_data[filter_index + 3]; + result0 += input_val * filter_val0; + result1 += input_val * filter_val1; + result2 += input_val * filter_val2; + result3 += input_val * filter_val3; + } + } + if (bias) { + result0 += bias[out_ch_idx + 0]; + result1 += bias[out_ch_idx + 1]; + result2 += bias[out_ch_idx + 2]; + result3 += bias[out_ch_idx + 3]; + } + result0 = esp_nn_multiply_by_quantized_mult_fast(result0, *out_mult++, *out_shift++); + result1 = esp_nn_multiply_by_quantized_mult_fast(result1, *out_mult++, *out_shift++); + result2 = esp_nn_multiply_by_quantized_mult_fast(result2, *out_mult++, *out_shift++); + result3 = esp_nn_multiply_by_quantized_mult_fast(result3, *out_mult++, *out_shift++); + + result0 += out_offset; + result1 += out_offset; + result2 += out_offset; + result3 += out_offset; + + result0 = max(result0, activation_min); + result1 = max(result1, activation_min); + result2 = max(result2, activation_min); + result3 = max(result3, activation_min); + result0 = min(result0, activation_max); + result1 = min(result1, activation_max); + result2 = min(result2, activation_max); + result3 = min(result3, activation_max); + + out_data[out_idx++] = result0; + out_data[out_idx++] = result1; + out_data[out_idx++] = result2; + out_data[out_idx++] = result3; + } + for (; ch_mult_idx < ch_mult; ch_mult_idx++) { + int32_t result = 0; + const int out_ch_idx = ch_idx * ch_mult + ch_mult_idx; + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * (channels * ch_mult) + out_ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val = filter_data[filter_index]; + result += input_val * filter_val; + } + } + if (bias) { + result += bias[out_ch_idx]; + } + result = esp_nn_multiply_by_quantized_mult_fast(result, *out_mult++, *out_shift++); + result += out_offset; + result = max(result, activation_min); + result = min(result, activation_max); + + out_data[out_idx++] = result; + } + } + } + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3.S new file mode 100644 index 0000000..2042573 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3.S @@ -0,0 +1,403 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + + # Program Unit: esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3 + .type esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3, @function + .align 4 + .global esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3 + +esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3: # 0x776 + # qacc_scratch = 0 + # gra_spill_temp_35 = 48 + # gra_spill_temp_36 = 52 + # gra_spill_temp_37 = 56 + # gra_spill_temp_38 = 60 + # gra_spill_temp_39 = 64 + # gra_spill_temp_40 = 68 + # gra_spill_temp_41 = 72 + # gra_spill_temp_42 = 76 + # gra_spill_temp_43 = 80 + # gra_spill_temp_44 = 84 + # gra_spill_temp_45 = 88 + # gra_spill_temp_46 = 92 + # gra_spill_temp_47 = 96 + # gra_spill_temp_48 = 100 + # gra_spill_temp_49 = 104 + # gra_spill_temp_50 = 108 + # gra_spill_temp_51 = 112 + # gra_spill_temp_52 = 116 + # gra_spill_temp_53 = 120 + # gra_spill_temp_54 = 124 + # gra_spill_temp_55 = 128 + # gra_spill_temp_56 = 132 + # gra_spill_temp_57 = 136 + # gra_spill_temp_58 = 140 + # gra_spill_temp_59 = 144 + # gra_spill_temp_60 = 148 + # gra_spill_temp_61 = 152 + # gra_spill_temp_62 = 156 + # gra_spill_temp_63 = 160 + # gra_spill_temp_64 = 164 + # gra_spill_temp_65 = 168 + # gra_spill_temp_66 = 176 + # gra_spill_temp_67 = 192 + # gra_spill_temp_68 = 208 + # gra_spill_temp_69 = 224 + # gra_spill_temp_70 = 240 + + // registers: + // a2: const int16_t *input_data + // a3: const uint16_t input_wd + // a4: const uint16_t input_ht + // a5: const uint16_t channels + // a6: const uint16_t pad_wd + // a7: const uint16_t pad_ht + + // on stack + // const uint16_t stride_wd + // const uint16_t stride_ht + // const int16_t *filter_data + // const int32_t *bias + // int8_t *out_data + // const uint16_t out_wd + // const uint16_t out_ht + // const int32_t out_offset + // const int32_t *out_shift + // const int32_t *out_mult + // const int32_t activation_min + // const int32_t activation_max + + entry a1,288 # + s32i a2,a1,104 # [0] gra_spill_temp_49 + s32i a3,a1,112 # [1] gra_spill_temp_51 + s32i a5,a1,116 # [2] gra_spill_temp_52 + s32i.n a6,a1,56 # [3] gra_spill_temp_37 + addi a14,a1,112 # [4] + addmi a11,a1,256 # [5] + addmi a13,a1,256 # [6] + addmi a15,a1,256 # [7] + l32i a9,a1,304 # [8] id:251 out_data+0x0 + l16ui a8,a1,312 # [9] id:252 out_ht+0x0 + s32i a8,a1,64 # [10] gra_spill_temp_39 + s32i a9,a1,156 # [11] gra_spill_temp_62 + addi a15,a15,60 # [12] + addi a13,a13,72 # [13] + addi a11,a11,76 # [14] + ee.vldbc.32 q0,a11 # [15] id:250 activation_max + ee.vldbc.32 q1,a13 # [16] id:249 activation_min + ee.vldbc.32 q2,a15 # [17] id:248 out_offset + st.qr q2,a14,80 # [18] gra_spill_temp_67-112 + st.qr q1,a14,96 # [19] gra_spill_temp_68-112 + st.qr q0,a14,112 # [20] gra_spill_temp_69-112 + beqz.n a8,.Lt_5_7426 # [21] + +.LBB3_esp_nn_depthwise_conv_s16_mult1_3x3: # 0x7b9 + s32i a1,a1,160 # [0] gra_spill_temp_63 + s32i a7,a1,72 # [1] gra_spill_temp_41 + mul16u a6,a3,a5 # [2] + l32i a14,a1,296 # [3] id:254 filter_data+0x0 + l32i a15,a1,300 # [4] id:253 bias+0x0 + l16ui a9,a1,308 # [5] id:259 out_wd+0x0 + l16ui a13,a1,288 # [6] id:255 stride_wd+0x0 + neg a8,a7 # [7] + l16ui a10,a1,292 # [8] id:258 stride_ht+0x0 + l32i a11,a1,324 # [9] id:257 out_mult+0x0 + l32i a12,a1,320 # [10] id:256 out_shift+0x0 + s32i a12,a1,84 # [11] gra_spill_temp_44 + s32i a11,a1,88 # [12] gra_spill_temp_45 + s32i.n a10,a1,60 # [13] gra_spill_temp_38 + s32i a8,a1,124 # [14] gra_spill_temp_54 + s32i a13,a1,80 # [15] gra_spill_temp_43 + s32i a9,a1,92 # [16] gra_spill_temp_46 + s32i a15,a1,140 # [17] gra_spill_temp_58 + s32i a14,a1,108 # [18] gra_spill_temp_50 + slli a6,a6,1 # [19] + movi.n a14,16 # [20] + extui a15,a15,0,4 # [21] + addi a9,a5,-7 # [22] + movi.n a13,0 # [23] + sub a8,a4,a8 # [24] + addx2 a7,a5,a5 # [25] + slli a7,a7,1 # [26] + slli a4,a5,1 # [27] + s32i a13,a1,68 # [28] gra_spill_temp_40 + s32i a9,a1,144 # [29] gra_spill_temp_59 + s32i a15,a1,132 # [30] gra_spill_temp_56 + l32i.n a9,a1,56 # [31] gra_spill_temp_37 + s32i a8,a1,76 # [32] gra_spill_temp_42 + neg a9,a9 # [33] + s32i.n a9,a1,48 # [34] gra_spill_temp_35 + sub a8,a3,a9 # [35] + s32i.n a8,a1,52 # [36] gra_spill_temp_36 + +.Lt_5_7938: # 0x822 + l32i a10,a1,92 # [0] gra_spill_temp_46 + beqz.n a10,.Lt_5_8194 # [2] + +.LBB6_esp_nn_depthwise_conv_s16_mult1_3x3: # 0x827 + l32i.n a5,a1,52 # [0] gra_spill_temp_36 + l32i a11,a1,76 # [1] gra_spill_temp_42 + movi.n a13,0 # [2] + l32i a12,a1,72 # [3] gra_spill_temp_41 + movi.n a15,0 # [4] + l32i.n a8,a1,48 # [5] gra_spill_temp_35 + l32i.n a9,a1,56 # [6] gra_spill_temp_37 + s32i a9,a1,100 # [7] gra_spill_temp_48 + s32i a8,a1,128 # [8] gra_spill_temp_55 + s32i a15,a1,96 # [9] gra_spill_temp_47 + max a12,a12,a13 # [10] + s32i a12,a1,152 # [11] gra_spill_temp_61 + movi.n a13,3 # [12] + min a11,a11,a13 # [13] + s32i a11,a1,136 # [14] gra_spill_temp_57 + sub a11,a11,a12 # [15] + s32i a11,a1,120 # [16] gra_spill_temp_53 + +.Lt_5_8706: # 0x854 + l32i a2,a1,84 # [0] gra_spill_temp_44 + l32i a10,a1,144 # [1] gra_spill_temp_59 + l32i a11,a1,140 # [2] gra_spill_temp_58 + l32i a12,a1,88 # [3] gra_spill_temp_45 + s32i a12,a1,168 # [4] gra_spill_temp_65 + s32i a11,a1,148 # [5] gra_spill_temp_60 + blti a10,1,.Lt_5_8962 # [6] + + movi.n a8,0 # [0] + movi.n a13,0 # [1] + l32i a3,a1,100 # [2] gra_spill_temp_48 + s32i a13,a1,164 # [3] gra_spill_temp_64 + max a3,a3,a8 # [4] + +.Lt_5_9474: # 0x876 + l32i a10,a1,136 # [0] gra_spill_temp_57 + l32i a9,a1,152 # [1] gra_spill_temp_61 + ee.zero.qacc # [2] + bge a9,a10,.Lt_5_9730 # [3] + +.LBB12_esp_nn_depthwise_conv_s16_mult1_3x3: # 0x882 + l32i a12,a1,128 # [0] gra_spill_temp_55 + l32i a15,a1,112 # [1] gra_spill_temp_51 + l32i a10,a1,116 # [2] gra_spill_temp_52 + l32i a13,a1,124 # [3] gra_spill_temp_54 + mull a11,a9,a10 # [4] + add.n a13,a13,a9 # [5] + mull a13,a13,a15 # [6] + addx2 a11,a11,a11 # [7] + l32i a9,a1,164 # [8] gra_spill_temp_64 + add.n a12,a12,a13 # [9] + mull a10,a10,a12 # [10] + add.n a11,a9,a11 # [11] + l32i a12,a1,108 # [12] gra_spill_temp_50 + add.n a9,a9,a10 # [13] + l32i a10,a1,104 # [14] gra_spill_temp_49 + addx2 a11,a11,a12 # [15] + l32i a12,a1,120 # [16] gra_spill_temp_53 + addx2 a9,a9,a10 # [17] + loopgtz a12,.LBB32_esp_nn_depthwise_conv_s16_mult1_3x3 # [18] + + mov.n a13,a9 # [0] + mov.n a12,a11 # [1] + mov.n a9,a11 # [2] + mov.n a11,a13 # [3] + + beqz.n a3,.Lt_5_10498 # [4] if (filter_x_start) + + add.n a11,a4,a13 # [0] + add.n a9,a4,a12 # [1] +.Lt_5_10498: # 0x8c5 + + ee.vld.128.xp q0,a11,a4 # [0] id:261 + ee.vld.128.xp q1,a9,a4 # [1] id:262 + + bnez.n a3,.Lt_5_11010 # [2] if (filter_x_start) + + ee.vmulas.s16.qacc q0,q1 # [0] + ee.vld.128.xp q0,a11,a4 # [1] id:264 + ee.vld.128.xp q1,a9,a4 # [2] id:265 +.Lt_5_11010: # 0x8d6 + + ee.vmulas.s16.qacc q0,q1 # [0] + ee.vld.128.xp q0,a11,a4 # [1] id:267 + ee.vld.128.xp q1,a9,a4 # [2] id:268 + add.n a9,a6,a13 # [3] + + blti a5,3,.Lt_5_11522 # [4] if (filter_x_end) + ee.vmulas.s16.qacc q0,q1 # [0] +.Lt_5_11522: # 0x8e7 + + add.n a11,a7,a12 # [0] + +.LBB32_esp_nn_depthwise_conv_s16_mult1_3x3: # 0x8eb + +.Lt_5_9730: # 0x8eb + // extract data + l32i a9,a1,160 # [0] gra_spill_temp_63 + ee.st.qacc_l.l.128.ip a9,16 # [2] id:270 + ee.st.qacc_l.h.32.ip a9,0 # [3] id:271 + l8ui a11,a1,15 # [4] qacc_scratch+15 + l16ui a10,a1,10 # [5] qacc_scratch+10 + l8ui a15,a1,16 # [6] qacc_scratch+16 + l8ui a13,a1,6 # [7] qacc_scratch+6 + l8ui a12,a1,5 # [8] qacc_scratch+5 + s8i a12,a1,2 # [9] qacc_scratch+2 + s8i a13,a1,3 # [10] qacc_scratch+3 + s8i a15,a1,7 # [11] qacc_scratch+7 + s16i a10,a1,4 # [12] qacc_scratch+4 + s8i a11,a1,6 # [13] qacc_scratch+6 + + ee.st.qacc_h.l.128.ip a9,16 # [14] id:281 + ee.st.qacc_h.h.32.ip a9,-32 # [15] id:282 + ee.srcmb.s16.qacc q1,a14,0 # [16] + l8ui a15,a1,31 # [17] qacc_scratch+31 + l8ui a8,a1,32 # [18] qacc_scratch+32 + l16ui a13,a1,26 # [19] qacc_scratch+26 + l8ui a12,a1,22 # [20] qacc_scratch+22 + l8ui a11,a1,21 # [21] qacc_scratch+21 + l16ui a10,a1,16 # [22] qacc_scratch+16 + s16i a10,a1,8 # [23] qacc_scratch+8 + s8i a11,a1,10 # [24] qacc_scratch+10 + s8i a12,a1,11 # [25] qacc_scratch+11 + s16i a13,a1,12 # [26] qacc_scratch+12 + s8i a8,a1,15 # [27] qacc_scratch+15 + s8i a15,a1,14 # [28] qacc_scratch+14 + + + l32i a8,a1,140 # [29] gra_spill_temp_58 , bias + ee.vld.128.ip q0,a9,0 # [30] id:294 + s32i a9,a1,160 # [31] gra_spill_temp_63 + ee.vzip.16 q0,q1 # [32] + beqz.n a8,.Lt_5_12290 # [33] // skip bias + + addi a8,a1,112 # [0] + l32i a10,a1,132 # [1] gra_spill_temp_56 + l32i a9,a1,148 # [2] gra_spill_temp_60 + wur.sar_byte a10 # [3] + ee.vld.128.ip q4,a9,16 # [4] id:297 + ee.vld.128.ip q7,a9,16 # [5] id:298 + ee.vld.128.ip q5,a9,0 # [6] id:299 + s32i a9,a1,148 # [7] gra_spill_temp_60 + ee.src.q.qup q6,q4,q7 # [8] + ee.vadds.s32 q0,q0,q6 # [9] + ee.src.q.qup q3,q4,q5 # [10] + ee.vadds.s32 q1,q1,q3 # [11] + st.qr q1,a8,64 # [12] gra_spill_temp_66-112 + +.Lt_5_12290: # 0x974 + addi a11,a1,112 # [0] + + # 287 q0 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q0, out_mult_ptr, out_shift_ptr); + l32i a10,a1,168 # [1] gra_spill_temp_65 + st.qr q1,a11,64 # [2] gra_spill_temp_66-112 + mov.n a11,a2 # [3] + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [4] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + # 288 out_mult_ptr += 4; + # 289 out_shift_ptr += 4; + # 290 + # 291 q1 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q1, out_mult_ptr, out_shift_ptr); + l32i a10,a1,168 # [0] gra_spill_temp_65 + addmi a12,a1,256 # [1] + addi a11,a1,112 # [2] + st.qr q0,a12,-16 # [3] gra_spill_temp_70-256 + ld.qr q0,a11,64 # [4] gra_spill_temp_66-112 + addi a10,a10,16 # [5] + addi a11,a2,16 # [6] + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [7] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + +.LBB25_esp_nn_depthwise_conv_s16_mult1_3x3: # 0x99a +# Part of loop body line 216, head labeled .Lt_5_9474 + movi.n a14,16 # [0] + # 292 out_mult_ptr += 4; + # 293 out_shift_ptr += 4; + addi a2,a2,32 # [1] + l32i a15,a1,144 # [2] gra_spill_temp_59 + l32i a9,a1,156 # [3] gra_spill_temp_62 + l32i a8,a1,168 # [4] gra_spill_temp_65 + addmi a12,a1,256 # [5] + addi a13,a1,112 # [6] + ld.qr q3,a13,112 # [7] gra_spill_temp_69-112 + ld.qr q1,a13,80 # [8] gra_spill_temp_67-112 + ld.qr q2,a12,-16 # [9] gra_spill_temp_70-256 + addi a8,a8,32 # [10] + s32i a8,a1,168 # [11] gra_spill_temp_65 + ee.vadds.s32 q2,q2,q1 # [12] + ee.vadds.s32 q1,q0,q1 # [13] + ee.vmin.s32 q0,q2,q3 # [14] + ee.vmin.s32 q1,q1,q3 # [15] + ld.qr q2,a13,96 # [16] gra_spill_temp_68-112 + l32i a13,a1,164 # [17] gra_spill_temp_64 + ee.vmax.s32 q1,q1,q2 # [18] + ee.vmax.s32 q0,q0,q2 # [19] + addi.n a13,a13,8 # [20] + s32i a13,a1,164 # [21] gra_spill_temp_64 + ee.vunzip.16 q0,q1 # [22] + ee.vunzip.8 q0,q1 # [23] + ee.vst.l.64.ip q0,a9,8 # [24] id:302 + s32i a9,a1,156 # [25] gra_spill_temp_62 + blt a13,a15,.Lt_5_9474 # [26] + +.Lt_5_8962: # 0x9e9 +# Part of loop body line 203, head labeled .Lt_5_8706 + l32i a8,a1,92 # [0] gra_spill_temp_46 + l32i a11,a1,100 # [1] gra_spill_temp_48 + l32i a10,a1,128 # [2] gra_spill_temp_55 + l32i a9,a1,80 # [3] gra_spill_temp_43 + l32i a15,a1,96 # [4] gra_spill_temp_47 + sub a5,a5,a9 # [5] + addi.n a15,a15,1 # [6] + s32i a15,a1,96 # [7] gra_spill_temp_47 + add.n a10,a10,a9 # [8] + sub a11,a11,a9 # [9] + s32i a11,a1,100 # [10] gra_spill_temp_48 + s32i a10,a1,128 # [11] gra_spill_temp_55 + sub a15,a15,a8 # [12] + bnez a15,.Lt_5_8706 # [13] + +.Lt_5_8194: # 0xa11 +# Part of loop body line 201, head labeled .Lt_5_7938 + l32i a13,a1,64 # [0] gra_spill_temp_39 + l32i a10,a1,72 # [1] gra_spill_temp_41 + l32i a9,a1,124 # [2] gra_spill_temp_54 + l32i.n a8,a1,60 # [3] gra_spill_temp_38 + l32i a12,a1,68 # [4] gra_spill_temp_40 + l32i a15,a1,76 # [5] gra_spill_temp_42 + addi.n a12,a12,1 # [6] + s32i a12,a1,68 # [7] gra_spill_temp_40 + sub a15,a15,a8 # [8] + add.n a9,a9,a8 # [9] + sub a10,a10,a8 # [10] + s32i a10,a1,72 # [11] gra_spill_temp_41 + s32i a9,a1,124 # [12] gra_spill_temp_54 + s32i a15,a1,76 # [13] gra_spill_temp_42 + sub a12,a12,a13 # [14] + bnez a12,.Lt_5_7938 # [15] + +.Lt_5_7426: # 0xa3e + retw.n # [0] + + .size esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3, . - esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3.S new file mode 100644 index 0000000..06f9307 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3.S @@ -0,0 +1,367 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + + # Program Unit: esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3 + .type esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3, @function + .align 4 + .global esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3 + +esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3: # 0xa42 + # qacc_scratch = 0 + # gra_spill_temp_71 = 48 + # gra_spill_temp_72 = 52 + # gra_spill_temp_73 = 56 + # gra_spill_temp_74 = 60 + # gra_spill_temp_75 = 64 + # gra_spill_temp_76 = 68 + # gra_spill_temp_77 = 72 + # gra_spill_temp_78 = 76 + # gra_spill_temp_79 = 80 + # gra_spill_temp_80 = 84 + # gra_spill_temp_81 = 88 + # gra_spill_temp_82 = 92 + # gra_spill_temp_83 = 96 + # gra_spill_temp_84 = 100 + # gra_spill_temp_85 = 104 + # gra_spill_temp_86 = 108 + # gra_spill_temp_87 = 112 + # gra_spill_temp_88 = 116 + # gra_spill_temp_89 = 120 + # gra_spill_temp_90 = 124 + # gra_spill_temp_91 = 128 + # gra_spill_temp_92 = 132 + # gra_spill_temp_93 = 136 + # gra_spill_temp_94 = 140 + # gra_spill_temp_95 = 144 + # gra_spill_temp_96 = 160 + # gra_spill_temp_97 = 176 + # gra_spill_temp_98 = 192 + # gra_spill_temp_99 = 208 + # gra_spill_temp_100 = 224 + # gra_spill_temp_101 = 240 + # gra_spill_temp_102 = 244 + # gra_spill_temp_103 = 248 + + // registers: + // a2: const int16_t *input_data + // a3: const uint16_t input_wd + // a4: const uint16_t input_ht + // a5: const uint16_t channels + // a6: const uint16_t stride_wd + // a7: const uint16_t stride_ht + + // on stack: + // const int16_t *filter_data + // const int32_t *bias + // int8_t *out_data + // const uint16_t out_wd + // const uint16_t out_ht + // const int32_t out_offset + // const int32_t *out_shift + // const int32_t *out_mult + // const int32_t activation_min + // const int32_t activation_max + + entry a1,288 # + s32i a2,a1,120 # [0] gra_spill_temp_89 + s32i.n a3,a1,48 # [1] gra_spill_temp_71 + s32i a5,a1,76 # [2] gra_spill_temp_78 + s32i a6,a1,84 # [3] gra_spill_temp_80 + s32i.n a7,a1,60 # [4] gra_spill_temp_74 + l32i a12,a1,296 # [5] id:241 out_data+0x0 + addi a14,a1,112 # [6] + addmi a10,a1,256 # [7] + addmi a13,a1,256 # [8] + addmi a15,a1,256 # [9] + + // height loop + l16ui a8,a1,304 # [10] id:242 out_ht+0x0 + s32i.n a8,a1,56 # [11] gra_spill_temp_73 + addi a15,a15,52 # [12] + addi a13,a13,64 # [13] + addi a10,a10,68 # [14] + ee.vldbc.32 q0,a10 # [15] id:240 activation_max + ee.vldbc.32 q1,a13 # [16] id:239 activation_min + ee.vldbc.32 q2,a15 # [17] id:238 out_offset + st.qr q2,a14,64 # [18] gra_spill_temp_97-112 + st.qr q1,a14,80 # [19] gra_spill_temp_98-112 + st.qr q0,a14,96 # [20] gra_spill_temp_99-112 + beqz.n a8,.Lt_6_6914 # [21] + +.LBB3_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad: # 0xa83 + s32i a1,a1,144 # [0] gra_spill_temp_95 + mul16u a7,a3,a5 # [1] + s32i a4,a1,72 # [2] gra_spill_temp_77 + addi a9,a5,-7 # [3] + l16ui a11,a1,300 # [4] id:247 out_wd+0x0 + l32i a10,a1,292 # [5] id:243 bias+0x0 + l32i a15,a1,288 # [6] id:244 filter_data+0x0 + l32i a13,a1,316 # [7] id:246 out_mult+0x0 + l32i a14,a1,312 # [8] id:245 out_shift+0x0 + s32i a14,a1,88 # [9] gra_spill_temp_81 + s32i a13,a1,92 # [10] gra_spill_temp_82 + s32i a15,a1,124 # [11] gra_spill_temp_90 + s32i a10,a1,116 # [12] gra_spill_temp_88 + s32i a11,a1,96 # [13] gra_spill_temp_83 + s32i a9,a1,136 # [14] gra_spill_temp_93 + addx2 a4,a5,a5 # [15] + slli a4,a4,1 # [16] + slli a7,a7,1 # [17] + l32i.n a9,a1,60 # [18] gra_spill_temp_74 + movi.n a11,0 # [19] + extui a10,a10,0,4 # [20] + movi.n a15,0 # [21] + slli a5,a5,1 # [22] + s32i a15,a1,68 # [23] gra_spill_temp_76 + s32i a10,a1,112 # [24] gra_spill_temp_87 + s32i a11,a1,64 # [25] gra_spill_temp_75 + mul16u a8,a3,a9 # [26] + movi.n a11,0 # [27] + s32i a11,a1,80 # [28] gra_spill_temp_79 + s32i.n a8,a1,52 # [29] gra_spill_temp_72 + +.Lt_6_7426: # 0xad8 // width_loop + l32i a8,a1,96 # [0] gra_spill_temp_83 + beqz.n a8,.Lt_6_7682 # [2] + + movi.n a11,3 # [0] + l32i a10,a1,72 # [1] gra_spill_temp_77 + movi.n a9,0 # [2] + movi.n a13,0 # [3] + l32i.n a14,a1,48 # [4] gra_spill_temp_71 + s32i a14,a1,108 # [5] gra_spill_temp_86 + s32i a13,a1,104 # [6] gra_spill_temp_85 + s32i a9,a1,100 # [7] gra_spill_temp_84 + min a10,a10,a11 # [8] + s32i a10,a1,128 # [9] gra_spill_temp_91 + +.Lt_6_8194: # 0xaf7 + l32i a2,a1,88 # [0] gra_spill_temp_81 + l32i a6,a1,92 # [1] gra_spill_temp_82 + l32i a8,a1,116 # [2] gra_spill_temp_88 + +// channel loop + l32i a15,a1,136 # [3] gra_spill_temp_93 + s32i a8,a1,140 # [4] gra_spill_temp_94 + blti a15,1,.Lt_6_8450 # [5] + + movi.n a11,0 # [0] + movi.n a10,0 # [1] + l32i a9,a1,76 # [2] gra_spill_temp_78 + l32i a14,a1,80 # [3] gra_spill_temp_79 + movi.n a8,3 # [4] + l32i a3,a1,108 # [5] gra_spill_temp_86 + l32i a13,a1,104 # [6] gra_spill_temp_85 + min a3,a3,a8 # [7] + add.n a13,a13,a14 # [8] + mull a9,a9,a13 # [9] + s32i a9,a1,132 # [10] gra_spill_temp_92 + +.Lt_6_8962: # 0xb26 + ee.zero.qacc # [0] + l32i a9,a1,132 # [1] gra_spill_temp_92 + l32i a13,a1,120 # [2] gra_spill_temp_89 + add.n a9,a9,a10 # [3] + addx2 a9,a9,a13 # [4] + l32i a13,a1,124 # [5] gra_spill_temp_90 + l32i a14,a1,128 # [6] gra_spill_temp_91 + add.n a13,a11,a13 # [7] + loopgtz a14,.LBB30_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad # [8] + +.Lt_6_9730: # 0xb3f +# Loop body line 360, nesting depth: 4, estimated iterations: 100 + mov.n a14,a13 # [0] + mov.n a15,a9 # [1] + ee.vld.128.xp q0,a15,a5 # [2] id:249 + ee.vld.128.xp q1,a14,a5 # [3] id:250 + add.n a9,a9,a7 # [4] + beqi a3,2,.LBB15_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad # [5] + +.Lt_6_9986: # 0xb4e + beqi a3,3,.LBB17_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad # [0] + +.Lt_6_10498: # 0xb51 + add.n a13,a13,a4 # [0] + ee.vmulas.s16.qacc q0,q1 # [1] + +.LBB30_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad: # 0xb58 + + // extract data + l32i a15,a1,144 # [0] gra_spill_temp_95 + ee.st.qacc_l.l.128.ip a15,16 # [2] id:258 + ee.st.qacc_l.h.32.ip a15,0 # [3] id:259 + l8ui a14,a1,15 # [4] qacc_scratch+15 + l8ui a13,a1,16 # [5] qacc_scratch+16 + l8ui a8,a1,5 # [6] qacc_scratch+5 + l8ui a9,a1,6 # [7] qacc_scratch+6 + s8i a9,a1,3 # [8] qacc_scratch+3 + s8i a8,a1,2 # [9] qacc_scratch+2 + s8i a13,a1,7 # [10] qacc_scratch+7 + s8i a14,a1,6 # [11] qacc_scratch+6 + l16ui a13,a1,10 # [12] qacc_scratch+10 + s16i a13,a1,4 # [13] qacc_scratch+4 + ee.st.qacc_h.l.128.ip a15,16 # [14] id:269 + ee.st.qacc_h.h.32.ip a15,-32 # [15] id:270 + l8ui a9,a1,32 # [16] qacc_scratch+32 + l8ui a13,a1,22 # [17] qacc_scratch+22 + l8ui a8,a1,31 # [18] qacc_scratch+31 + l16ui a14,a1,26 # [19] qacc_scratch+26 + s16i a14,a1,12 # [20] qacc_scratch+12 + s8i a8,a1,14 # [21] qacc_scratch+14 + s8i a13,a1,11 # [22] qacc_scratch+11 + s8i a9,a1,15 # [23] qacc_scratch+15 + + l32i a13,a1,116 # [24] gra_spill_temp_88 + l8ui a9,a1,21 # [25] qacc_scratch+21 + l16ui a8,a1,16 # [26] qacc_scratch+16 + movi.n a14,16 # [27] + ee.srcmb.s16.qacc q1,a14,0 # [28] + s16i a8,a1,8 # [29] qacc_scratch+8 + s8i a9,a1,10 # [30] qacc_scratch+10 + ee.vld.128.ip q0,a15,0 # [31] id:282 + s32i a15,a1,144 # [32] gra_spill_temp_95 + ee.vzip.16 q0,q1 # [33] + + bnez.n a13,.LBB20_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad # [34] + + s32i a12,a1,240 # [0] gra_spill_temp_101 + s32i a11,a1,244 # [1] gra_spill_temp_102 + s32i a10,a1,248 # [2] gra_spill_temp_103 + addi a14,a1,112 # [3] + st.qr q1,a14,48 # [4] gra_spill_temp_96-112 + j .Lt_6_11266 # [5] + +.LBB15_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad: # 0xbce +# Part of loop body line 360, head labeled .Lt_6_9730 + ee.vmulas.s16.qacc.ld.xp q0,a15,a5,q0,q1 # [0] id:251 + ee.vld.128.xp q1,a14,a5 # [1] id:252 + bnei a3,3,.Lt_6_10498 # [2] + +.LBB17_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad: # 0xbd8 + ee.vmulas.s16.qacc.ld.xp q3,a15,a5,q0,q1 # [0] id:253 + ee.vld.128.xp q4,a14,a5 # [1] id:254 + ee.vld.128.xp q1,a14,a5 # [2] id:256 + ee.vmulas.s16.qacc.ld.xp q0,a15,a5,q3,q4 # [3] id:255 + j .Lt_6_10498 # [4] + +.LBB20_esp_nn_depthwise_conv_s16_mult1_3x3_no_pad: # 0xbe9 +# Part of loop body line 358, head labeled .Lt_6_8962 + s32i a12,a1,240 # [0] gra_spill_temp_101 + s32i a11,a1,244 # [1] gra_spill_temp_102 + s32i a10,a1,248 # [2] gra_spill_temp_103 + addi a15,a1,112 # [3] + l32i a9,a1,112 # [4] gra_spill_temp_87 + l32i a8,a1,140 # [5] gra_spill_temp_94 + wur.sar_byte a9 # [6] + ee.vld.128.ip q6,a8,16 # [7] id:285 + ee.vld.128.ip q3,a8,16 # [8] id:286 + ee.vld.128.ip q7,a8,0 # [9] id:287 + s32i a8,a1,140 # [10] gra_spill_temp_94 + ee.src.q.qup q2,q6,q3 # [11] + ee.vadds.s32 q0,q0,q2 # [12] + ee.src.q.qup q5,q6,q7 # [13] + ee.vadds.s32 q1,q1,q5 # [14] + st.qr q1,a15,48 # [15] gra_spill_temp_96-112 + +.Lt_6_11266: # 0xc19 + # 423 q0 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q0, out_mult_ptr, out_shift_ptr); + mov.n a10,a6 # [0] + mov.n a11,a2 # [1] + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [2] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + addi a11,a1,112 # [0] + addi a10,a6,16 # [1] + st.qr q0,a11,112 # [2] gra_spill_temp_100-112 + ld.qr q0,a11,48 # [3] gra_spill_temp_96-112 + addi a11,a2,16 # [4] + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [5] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + addi a6,a6,32 # [0] + addi a2,a2,32 # [1] + + l32i a13,a1,136 # [2] gra_spill_temp_93 + l32i a12,a1,240 # [3] gra_spill_temp_101 + l32i a10,a1,248 # [4] gra_spill_temp_103 + l32i a11,a1,244 # [5] gra_spill_temp_102 + addi a9,a1,112 # [6] + ld.qr q6,a9,80 # [7] gra_spill_temp_98-112 + ld.qr q7,a9,96 # [8] gra_spill_temp_99-112 + ld.qr q5,a9,64 # [9] gra_spill_temp_97-112 + ld.qr q4,a9,112 # [10] gra_spill_temp_100-112 + addi a11,a11,16 # [11] + addi.n a10,a10,8 # [12] + ee.vadds.s32 q4,q4,q5 # [13] + ee.vadds.s32 q5,q0,q5 # [14] + ee.vmin.s32 q4,q4,q7 # [15] + ee.vmax.s32 q4,q4,q6 # [16] + ee.vmin.s32 q5,q5,q7 # [17] + ee.vmax.s32 q5,q5,q6 # [18] + ee.vunzip.16 q4,q5 # [19] + ee.vunzip.8 q4,q5 # [20] + ee.vst.l.64.ip q4,a12,8 # [21] id:290 + blt a10,a13,.Lt_6_8962 # [22] + +.Lt_6_8450: # 0xc76 +# Part of loop body line 348, head labeled .Lt_6_8194 + l32i a11,a1,96 # [0] gra_spill_temp_83 + l32i a15,a1,104 # [1] gra_spill_temp_85 + l32i a14,a1,84 # [2] gra_spill_temp_80 + l32i a10,a1,100 # [3] gra_spill_temp_84 + l32i a13,a1,108 # [4] gra_spill_temp_86 + addi.n a10,a10,1 # [5] + s32i a10,a1,100 # [6] gra_spill_temp_84 + sub a13,a13,a14 # [7] + add.n a15,a15,a14 # [8] + s32i a15,a1,104 # [9] gra_spill_temp_85 + s32i a13,a1,108 # [10] gra_spill_temp_86 + sub a10,a10,a11 # [11] + bnez a10,.Lt_6_8194 # [12] + +.Lt_6_7682: # 0xc9b + l32i.n a9,a1,56 # [0] gra_spill_temp_73 + l32i a15,a1,64 # [1] gra_spill_temp_75 + l32i.n a14,a1,52 # [2] gra_spill_temp_72 + l32i a13,a1,80 # [3] gra_spill_temp_79 + l32i.n a11,a1,60 # [4] gra_spill_temp_74 + l32i a8,a1,68 # [5] gra_spill_temp_76 + l32i a10,a1,72 # [6] gra_spill_temp_77 + addi.n a8,a8,1 # [7] + s32i a8,a1,68 # [8] gra_spill_temp_76 + sub a10,a10,a11 # [9] + add.n a13,a13,a14 # [10] + add.n a15,a15,a11 # [11] + s32i a15,a1,64 # [12] gra_spill_temp_75 + s32i a13,a1,80 # [13] gra_spill_temp_79 + s32i a10,a1,72 # [14] gra_spill_temp_77 + sub a8,a8,a9 # [15] + bnez a8,.Lt_6_7426 # [16] + +.Lt_6_6914: # 0xcc8 + retw.n # [0] + + .size esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3, . - esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_esp32s3.S new file mode 100644 index 0000000..8568df5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult1_esp32s3.S @@ -0,0 +1,345 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + + # Program Unit: esp_nn_depthwise_conv_s16_mult1_esp32s3 + .type esp_nn_depthwise_conv_s16_mult1_esp32s3, @function + .align 4 + .global esp_nn_depthwise_conv_s16_mult1_esp32s3 + +esp_nn_depthwise_conv_s16_mult1_esp32s3: # 0x4c8 + # scratch_buf = 0 + # gra_spill_temp_2 = 48 + # gra_spill_temp_22 = 52 + # gra_spill_temp_4 = 56 + # gra_spill_temp_23 = 60 + # gra_spill_temp_24 = 64 + # gra_spill_temp_7 = 68 + # gra_spill_temp_26 = 72 + # gra_spill_temp_27 = 76 + # gra_spill_temp_28 = 80 + # gra_spill_temp_29 = 84 + # gra_spill_temp_12 = 88 + # gra_spill_temp_13 = 92 + # gra_spill_temp_14 = 96 + # gra_spill_temp_15 = 100 + # gra_spill_temp_21 = 104 + # gra_spill_temp_17 = 108 + # gra_spill_temp_18 = 112 + # gra_spill_temp_20 = 116 + # gra_spill_temp_30 = 0 + # gra_spill_temp_34 = 16 + + // in registers: + // a2: *input_data + // a3: input_wd + // a4: input_ht + // a5: channels + // a6: pad_wd + // a7: pad_ht + + // on stack: + // stride_wd + // stride_ht + // *filter_data + // filter_wd + // filter_ht + // *bias + // *out_data + // out_wd + // out_ht + // out_offset + // *out_shift + // *out_mult + // activation_min + // activation_max + + entry a1,160 # + l32i a9,a1,184 # [7] id:237 out_data+0x0 + l16ui a8,a1,192 # [8] id:238 out_ht+0x0 + s32i a2,a1,52 # [0] gra_spill_temp_22 + s32i.n a4,a1,56 # [1] gra_spill_temp_4 + s32i a5,a1,60 # [2] gra_spill_temp_23 + s32i a9,a1,112 # [10] gra_spill_temp_18 + beqz.n a8,.Lt_4_7170 # [20] + +.LBB3_esp_nn_depthwise_conv_s16_mult1: # 0x508 + l16ui a4,a1,172 # [0] id:240 filter_wd+0x0 + neg a13,a7 # [2] + neg a12,a6 # [3] + sext a12,a12,15 # [16] + sext a13,a13,15 # [17] + s32i a13,a1,92 # [18] gra_spill_temp_13 + s32i.n a12,a1,48 # [19] gra_spill_temp_2 + movi.n a8,0 # [20] + slli a9,a5,1 # [21] + addi a10,a5,-7 # [22] + s32i a10,a1,100 # [23] gra_spill_temp_15 + s32i a9,a1,64 # [24] gra_spill_temp_24 + s32i a8,a1,68 # [25] gra_spill_temp_7 + j .Lt_4_7682 # [30] + +.Lt_4_7938: # 0x561 + l32i a15,a1,192 # [0] out_ht + l32i.n a9,a1,164 # [1] stride_ht + l32i a14,a1,68 # [2] gra_spill_temp_7 + l32i a8,a1,92 # [3] gra_spill_temp_13 + addi.n a14,a14,1 # [4] + s32i a14,a1,68 # [5] gra_spill_temp_7 + add.n a9,a8,a9 # [6] + sub a14,a14,a15 # [7] + sext a8,a9,15 # [8] + s32i a8,a1,92 # [9] gra_spill_temp_13 + beqz a14,.Lt_4_7170 # [10] + +.Lt_4_7682: # 0x57f +# Loop body line 59, nesting depth: 1, estimated iterations: 100 + # 60 const int16_t base_y = (out_y * stride_ht) - pad_ht; + # 61 for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + l32i a10,a1,188 # [0] out_width + beqz.n a10,.Lt_4_7938 # [2] + +.LBB6_esp_nn_depthwise_conv_s16_mult1: # 0x584 +# Part of loop body line 59, head labeled .Lt_4_7682 + movi.n a14,0 # [0] + l32i.n a7,a1,176 # [1] filter_ht + l32i a13,a1,92 # [2] gra_spill_temp_13 + l32i.n a8,a1,56 # [3] gra_spill_temp_4 + movi.n a11,0 # [4] + l32i.n a12,a1,48 # [5] gra_spill_temp_2 + s32i a12,a1,84 # [6] gra_spill_temp_29 + s32i a11,a1,88 # [7] gra_spill_temp_12 + sub a8,a8,a13 # [8] + min a7,a7,a8 # [9] + neg a13,a13 # [10] + max a13,a13,a14 # [11] + s32i a13,a1,96 # [12] gra_spill_temp_14 + j .Lt_4_8450 # [13] + +.Lt_4_8706: # 0x5a9 +# Part of loop body line 61, head labeled .Lt_4_8450 + l32i a10,a1,188 # [0] out_width + l32i a12,a1,160 # [1] stride_wd + l32i a9,a1,88 # [2] gra_spill_temp_12 + l32i a11,a1,84 # [3] gra_spill_temp_29 + addi.n a9,a9,1 # [4] + s32i a9,a1,88 # [5] gra_spill_temp_12 + add.n a12,a11,a12 # [6] + sext a11,a12,15 # [7] + s32i a11,a1,84 # [8] gra_spill_temp_29 + beq a9,a10,.Lt_4_7938 # [9] + +.Lt_4_8450: # 0x5c5 +# Loop body line 61, nesting depth: 2, estimated iterations: 100 + # 69 uint32_t bias_ptr = (uint32_t) bias; + # 70 const int32_t *out_mult_ptr = out_mult; + # 71 const int32_t *out_shift_ptr = out_shift; + # 72 + # 73 for (int ch_idx = 0; ch_idx < channels - 7; ch_idx += 8) {//channel_loop + l32i a13,a1,100 # [0] gra_spill_temp_15 + l32i a14,a1,180 # [1] bias + l32i a15,a1,204 # [2] out_mult + l32i a8,a1,200 # [3] out_shift + s32i a8,a1,104 # [4] gra_spill_temp_21 + s32i a15,a1,116 # [5] gra_spill_temp_20 + s32i a14,a1,108 # [6] gra_spill_temp_17 + blti a13,1,.Lt_4_8706 # [7] + +.LBB9_esp_nn_depthwise_conv_s16_mult1: # 0x5dd +# Part of loop body line 61, head labeled .Lt_4_8450 + movi.n a2,0 # [0] + l32i a5,a1,84 # [1] gra_spill_temp_29 + movi.n a8,0 # [2] + neg a6,a5 # [3] + max a6,a6,a8 # [4] + sub a5,a3,a5 # [5] + min a5,a4,a5 # [6] + sub a9,a5,a6 # [7] + s32i a9,a1,72 # [8] gra_spill_temp_26 + j .Lt_4_9218 # [9] + +.Lt_4_9474: # 0x5f9 + +// extract data + mov a11,a1 + ee.st.qacc_l.l.128.ip a11,16 # [2] id:252 + ee.st.qacc_l.h.32.ip a11,0 # [3] id:253 + l8ui a12,a1,15 # [4] scratch_buf+15 + l16ui a10,a1,10 # [5] scratch_buf+10 + l8ui a13,a1,5 # [6] scratch_buf+5 + l8ui a14,a1,6 # [7] scratch_buf+6 + l8ui a15,a1,16 # [8] scratch_buf+16 + s8i a13,a1,2 # [11] scratch_buf+2 + s8i a14,a1,3 # [10] scratch_buf+3 + s8i a15,a1,7 # [9] scratch_buf+7 + s16i a10,a1,4 # [12] scratch_buf+4 + s8i a12,a1,6 # [13] scratch_buf+6 + + movi.n a10,16 # [14] + ee.st.qacc_h.l.128.ip a11,16 # [15] id:263 + ee.st.qacc_h.h.32.ip a11,-32 # [16] id:264 + ee.srcmb.s16.qacc q1,a10,0 # [17] + l8ui a8,a1,31 # [18] scratch_buf+31 + l8ui a9,a1,32 # [19] scratch_buf+32 + l16ui a12,a1,16 # [20] scratch_buf+16 + l8ui a13,a1,21 # [21] scratch_buf+21 + l8ui a14,a1,22 # [22] scratch_buf+22 + l16ui a15,a1,26 # [23] scratch_buf+26 + s8i a13,a1,10 # [26] scratch_buf+10 + s8i a14,a1,11 # [25] scratch_buf+11 + s16i a15,a1,12 # [24] scratch_buf+12 + s16i a12,a1,8 # [27] scratch_buf+8 + s8i a9,a1,15 # [28] scratch_buf+15 + s8i a8,a1,14 # [29] scratch_buf+14 + + l32i a9,a1,180 # [30] bias + ee.vld.128.ip q0,a11,0 # [31] id:164 + ee.vzip.16 q0,q1 # [33] + beqz.n a9,.Lt_4_11522 # [34] // skip bias + +// add bias + l32i a9,a1,108 # [0] gra_spill_temp_17 + addi a8,a1,112 # [1] + extui a10,a9,0,4 # [2] + wur.sar_byte a10 # [3] + ee.vld.128.ip q4,a9,16 # [4] id:279 + ee.vld.128.ip q7,a9,16 # [5] id:168 + ee.vld.128.ip q5,a9,0 # [6] id:281 + s32i a9,a1,108 # [7] gra_spill_temp_17 + ee.src.q q4,q4,q7 # [8] + ee.src.q q7,q7,q5 # [10] + ee.vadds.s32 q0,q0,q4 # [9] + ee.vadds.s32 q1,q1,q7 # [11] + st.qr q1,a1,0 # [12] gra_spill_temp_30-112 + +.Lt_4_11522: # 0x684 + +// apply quantisation: esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q0, out_mult_ptr, out_shift_ptr); + + l32i a10,a1,116 # [1] gra_spill_temp_20 + l32i a11,a1,104 # [3] gra_spill_temp_21 + st.qr q1,a1,0 # [2] gra_spill_temp_30-112 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [4] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + l32i a10,a1,116 # [2] gra_spill_temp_20 + l32i a11,a1,104 # [0] gra_spill_temp_21 + st.qr q0,a1,16 # [3] gra_spill_temp_34-112 + ld.qr q0,a1,0 # [4] gra_spill_temp_30-112 + addi a10,a10,16 # [5] // out_mult_ptr += 4 + addi a11,a11,16 # [6] // out_shift_ptr += 4 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [7] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + +// add offset, apply activation and store + l32i a13,a1,100 # [0] gra_spill_temp_15 + addi.n a2,a2,8 # [1] + l32i a8,a1,112 # [2] gra_spill_temp_18 + l32i a15,a1,116 # [3] gra_spill_temp_20 + l32i a14,a1,104 # [4] gra_spill_temp_21 + + addi a12,a1,212 + ee.vldbc.32 q3,a12 # [14] id:236 activation_max + addi a12,a1,196 + ee.vldbc.32 q1,a12 # [16] id:234 out_offset + addi a12,a1,208 + + ld.qr q2,a1,16 # [8] gra_spill_temp_34-112 + + addi a14,a14,32 # [9] + addi a15,a15,32 # [10] + s32i a15,a1,116 # [11] gra_spill_temp_20 + ee.vadds.s32 q2,q2,q1 # [12] + s32i a14,a1,104 # [13] gra_spill_temp_21 + ee.vadds.s32 q1,q0,q1 # [14] + ee.vmin.s32 q0,q2,q3 # [15] + ee.vldbc.32 q2,a12 # [16] id:234 out_offset + ee.vmin.s32 q1,q1,q3 # [17] + ee.vmax.s32 q1,q1,q2 # [18] + ee.vmax.s32 q0,q0,q2 # [19] + ee.vunzip.16 q0,q1 # [20] + ee.vunzip.8 q0,q1 # [21] + ee.vst.l.64.ip q0,a8,8 # [22] id:172 + s32i a8,a1,112 # [23] gra_spill_temp_18 + bge a2,a13,.Lt_4_8706 # [24] + +.Lt_4_9218: # 0x6f5 + ee.zero.qacc # [0] + l32i a13,a1,96 # [1] gra_spill_temp_14 + s32i a13,a1,80 # [2] gra_spill_temp_28 + bge a13,a7,.Lt_4_9474 # [3] + +.LBB12_esp_nn_depthwise_conv_s16_mult1: # 0x701 // channel_loop + mull a15,a13,a4 # [0] + l32i a14,a1,92 # [1] gra_spill_temp_13 + add.n a8,a15,a5 # [2] + add.n a14,a14,a13 # [3] + mull a14,a3,a14 # [4] + s32i a8,a1,76 # [5] gra_spill_temp_27 + bge a6,a5,.Lt_4_10242 # [6] + +.LBB15_esp_nn_depthwise_conv_s16_mult1: # 0x714 + l32i a12,a1,64 # [0] gra_spill_temp_24 + l32i a9,a1,168 # [1] filter_data + l32i a10,a1,60 # [2] gra_spill_temp_23 + l32i a11,a1,84 # [3] gra_spill_temp_29 + add.n a8,a15,a6 # [4] + add.n a11,a11,a6 # [5] + mull a8,a8,a10 # [6] + add.n a11,a14,a11 # [7] + mull a10,a10,a11 # [8] + add.n a8,a2,a8 # [9] + l32i a11,a1,52 # [10] gra_spill_temp_22 + addx2 a8,a8,a9 # [11] + add.n a10,a2,a10 # [12] + l32i a9,a1,72 # [13] gra_spill_temp_26 + addx2 a10,a10,a11 # [14] + loopgtz a9,.LBB41_esp_nn_depthwise_conv_s16_mult1 # [15] +// innermost loop + ee.vld.128.xp q0,a10,a12 # [0*II+3] id:249 + ee.vld.128.xp q1,a8,a12 # [0*II+4] id:250 + ee.vmulas.s16.qacc q0,q1 # [0*II+6] +.LBB41_esp_nn_depthwise_conv_s16_mult1: # 0x750 + +.Lt_4_10242: # 0x750 + add.n a14,a14,a3 # [0] + add.n a15,a15,a4 # [1] + l32i a9,a1,80 # [2] gra_spill_temp_28 + l32i a10,a1,76 # [3] gra_spill_temp_27 + addi.n a9,a9,1 # [4] + add.n a10,a10,a4 # [5] + s32i a10,a1,76 # [6] gra_spill_temp_27 + s32i a9,a1,80 # [7] gra_spill_temp_28 + sub a9,a7,a9 # [8] + beqz a9,.Lt_4_9474 # [9] + + blt a6,a5,.LBB15_esp_nn_depthwise_conv_s16_mult1 # [0] + + j .Lt_4_10242 # [0] + +.Lt_4_7170: # 0x770 + retw.n # [0] + + .size esp_nn_depthwise_conv_s16_mult1_esp32s3, . - esp_nn_depthwise_conv_s16_mult1_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult4_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult4_esp32s3.S new file mode 100644 index 0000000..792d137 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult4_esp32s3.S @@ -0,0 +1,416 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + + # Program Unit: esp_nn_depthwise_conv_s16_mult4_esp32s3 + .type esp_nn_depthwise_conv_s16_mult4_esp32s3, @function + .align 4 + .global esp_nn_depthwise_conv_s16_mult4_esp32s3 + +esp_nn_depthwise_conv_s16_mult4_esp32s3: # 0x17c8 + # qacc_scratch = 0 + # gra_spill_temp_220 = 32 + # gra_spill_temp_221 = 36 + # gra_spill_temp_222 = 40 + # gra_spill_temp_223 = 44 + # gra_spill_temp_224 = 48 + # gra_spill_temp_225 = 52 + # gra_spill_temp_226 = 56 + # gra_spill_temp_227 = 60 + # gra_spill_temp_228 = 64 + # gra_spill_temp_229 = 68 + # gra_spill_temp_230 = 72 + # gra_spill_temp_231 = 76 + # gra_spill_temp_232 = 80 + # gra_spill_temp_233 = 84 + # gra_spill_temp_234 = 88 + # gra_spill_temp_235 = 92 + # gra_spill_temp_236 = 96 + # gra_spill_temp_237 = 100 + # gra_spill_temp_238 = 104 + # gra_spill_temp_239 = 108 + # gra_spill_temp_240 = 112 + # gra_spill_temp_241 = 116 + # gra_spill_temp_242 = 120 + # gra_spill_temp_243 = 124 + # gra_spill_temp_244 = 128 + # gra_spill_temp_245 = 132 + # gra_spill_temp_246 = 136 + # gra_spill_temp_247 = 140 + # gra_spill_temp_248 = 144 + # gra_spill_temp_249 = 148 + # gra_spill_temp_250 = 152 + # gra_spill_temp_251 = 156 + # gra_spill_temp_252 = 160 + # gra_spill_temp_253 = 164 + # gra_spill_temp_254 = 168 + # gra_spill_temp_255 = 172 + # gra_spill_temp_256 = 176 + # gra_spill_temp_257 = 192 + # gra_spill_temp_258 = 208 + # gra_spill_temp_259 = 224 + # gra_spill_temp_260 = 240 + + // registers: + // a2: const int16_t *input_data + // a3: const uint16_t input_wd + // a4: const uint16_t input_ht + // a5: const uint16_t channels + // a6: const uint16_t pad_wd + // a7: const uint16_t pad_ht + + // on stack: + // const uint16_t stride_wd + // const uint16_t stride_ht + // const uint16_t ch_mult + // const int16_t *filter_data + // const uint16_t filter_wd + // const uint16_t filter_ht + // const int32_t *bias + // int8_t *out_data + // const uint16_t out_wd + // const uint16_t out_ht + // const int32_t out_offset + // const int32_t *out_shift + // const int32_t *out_mult + // const int32_t activation_min + // const int32_t activation_max + + + entry a1,288 # + s32i a2,a1,136 # [0] gra_spill_temp_246 + s32i.n a4,a1,40 # [1] gra_spill_temp_222 + s32i a5,a1,164 # [2] gra_spill_temp_253 + addi a12,a1,112 # [3] + addmi a10,a1,256 # [4] + addmi a11,a1,256 # [5] + addmi a13,a1,256 # [6] + l16ui a8,a1,324 # [7] id:216 out_ht+0x0 + s32i.n a8,a1,48 # [8] gra_spill_temp_224 + addi a13,a13,72 # [9] + addi a11,a11,88 # [10] + addi a10,a10,84 # [11] + ee.vldbc.32 q0,a10 # [12] id:215 activation_min + ee.vldbc.32 q1,a11 # [13] id:214 activation_max + ee.vldbc.32 q2,a13 # [14] id:213 out_offset + st.qr q2,a12,80 # [15] gra_spill_temp_257-112 + st.qr q1,a12,96 # [16] gra_spill_temp_258-112 + st.qr q0,a12,112 # [17] gra_spill_temp_259-112 + beqz.n a8,.Lt_10_8450 # [18] + + s32i a1,a1,112 # [0] gra_spill_temp_240 + neg a15,a6 # [1] + neg a4,a7 # [2] + addmi a8,a1,256 # [3] + movi.n a9,0 # [4] + movi.n a11,0 # [5] + slli a14,a5,1 # [6] + l16ui a13,a1,296 # [7] id:217 ch_mult+0x0 + l16ui a10,a1,308 # [8] id:227 filter_ht+0x0 + s32i.n a10,a1,36 # [9] gra_spill_temp_221 + s32i a13,a1,76 # [10] gra_spill_temp_231 + s32i a14,a1,148 # [11] gra_spill_temp_249 + s32i.n a11,a1,52 # [12] gra_spill_temp_225 + s32i a9,a1,116 # [13] gra_spill_temp_241 + st.qr q4,a8,-16 # [14] gra_spill_temp_260-256 + sext a4,a4,15 # [15] + sext a15,a15,15 # [16] + s32i.n a15,a1,32 # [17] gra_spill_temp_220 + mul16u a12,a5,a13 # [18] + s32i a4,a1,92 # [19] gra_spill_temp_235 + l16ui a8,a1,320 # [20] id:229 out_wd+0x0 + l16ui a9,a1,292 # [21] id:228 stride_ht+0x0 + l32i a11,a1,336 # [22] id:226 out_mult+0x0 + s32i a11,a1,64 # [23] gra_spill_temp_228 + s32i.n a9,a1,44 # [24] gra_spill_temp_223 + s32i a8,a1,68 # [25] gra_spill_temp_229 + l32i a4,a1,300 # [26] id:218 filter_data+0x0 + s32i a12,a1,140 # [27] gra_spill_temp_247 + l32i a15,a1,316 # [28] id:219 out_data+0x0 + s32i a15,a1,96 # [29] gra_spill_temp_236 + slli a12,a12,1 # [30] + s32i a4,a1,152 # [31] gra_spill_temp_250 + addi a14,a13,-3 # [32] + l16ui a4,a1,304 # [33] id:223 filter_wd+0x0 + s32i a14,a1,108 # [34] gra_spill_temp_239 + s32i a12,a1,144 # [35] gra_spill_temp_248 + slli a13,a13,2 # [36] + s32i a13,a1,80 # [37] gra_spill_temp_232 + l32i a12,a1,332 # [38] id:225 out_shift+0x0 + l32i a14,a1,312 # [39] id:222 bias+0x0 + s32i a14,a1,104 # [40] gra_spill_temp_238 + s32i.n a12,a1,60 # [41] gra_spill_temp_227 + l16ui a13,a1,288 # [42] id:224 stride_wd+0x0 + s32i.n a13,a1,56 # [43] gra_spill_temp_226 + j .Lt_10_8962 # [44] + +.Lt_10_9218: # 0x1880 + l32i.n a9,a1,48 # [0] gra_spill_temp_224 + l32i.n a11,a1,44 # [1] gra_spill_temp_223 + l32i.n a8,a1,52 # [2] gra_spill_temp_225 + l32i a10,a1,92 # [3] gra_spill_temp_235 + addi.n a8,a8,1 # [4] + s32i.n a8,a1,52 # [5] gra_spill_temp_225 + add.n a11,a10,a11 # [6] + sub a8,a8,a9 # [7] + sext a10,a11,15 # [8] + s32i a10,a1,92 # [9] gra_spill_temp_235 + beqz a8,.Lt_10_8450 # [10] + +.Lt_10_8962: # 0x189b +# Loop body line 1223, nesting depth: 1, estimated iterations: 100 + #1224 const int16_t base_y = (out_y * stride_ht) - pad_ht; + #1225 for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + l32i a12,a1,68 # [0] gra_spill_temp_229 + beqz.n a12,.Lt_10_9218 # [2] + +.LBB6_esp_nn_depthwise_conv_s16_mult4: # 0x18a0 + l32i.n a7,a1,36 # [0] gra_spill_temp_221 + movi.n a11,0 # [1] + l32i.n a8,a1,40 # [2] gra_spill_temp_222 + l32i a9,a1,92 # [3] gra_spill_temp_235 + movi.n a13,0 # [4] + l32i.n a14,a1,32 # [5] gra_spill_temp_220 + s32i a14,a1,160 # [6] gra_spill_temp_252 + s32i a13,a1,72 # [7] gra_spill_temp_230 + neg a10,a9 # [8] + sub a8,a8,a9 # [9] + max a10,a10,a11 # [10] + s32i a10,a1,100 # [11] gra_spill_temp_237 + min a7,a7,a8 # [12] + j .Lt_10_9730 # [13] + +.Lt_10_9986: # 0x18c5 + l32i a13,a1,68 # [0] gra_spill_temp_229 + l32i.n a15,a1,56 # [1] gra_spill_temp_226 + l32i a12,a1,72 # [2] gra_spill_temp_230 + l32i a14,a1,160 # [3] gra_spill_temp_252 + addi.n a12,a12,1 # [4] + s32i a12,a1,72 # [5] gra_spill_temp_230 + add.n a15,a14,a15 # [6] + sext a14,a15,15 # [7] + s32i a14,a1,160 # [8] gra_spill_temp_252 + beq a12,a13,.Lt_10_9218 # [9] + +.Lt_10_9730: # 0x18e0 + l32i a8,a1,164 # [0] gra_spill_temp_253 + l32i a9,a1,64 # [1] gra_spill_temp_228 + l32i.n a10,a1,60 # [2] gra_spill_temp_227 + s32i a10,a1,132 # [3] gra_spill_temp_245 + s32i a9,a1,128 # [4] gra_spill_temp_244 + beqz.n a8,.Lt_10_9986 # [5] + + movi.n a8,0 # [0] + l32i a5,a1,160 # [1] gra_spill_temp_252 + movi.n a12,0 # [2] + movi.n a13,0 # [3] + movi.n a14,0 # [4] + s32i a14,a1,84 # [5] gra_spill_temp_233 + s32i a13,a1,88 # [6] gra_spill_temp_234 + s32i a12,a1,176 # [7] gra_spill_temp_256 + neg a6,a5 # [8] + max a6,a6,a8 # [9] + sub a5,a3,a5 # [10] + min a5,a4,a5 # [11] + sub a11,a5,a6 # [12] + s32i a11,a1,156 # [13] gra_spill_temp_251 + j .Lt_10_10498 # [14] + +.Lt_10_10754: # 0x1919 + l32i a10,a1,164 # [0] gra_spill_temp_253 + l32i a14,a1,76 # [1] gra_spill_temp_231 + l32i a13,a1,84 # [2] gra_spill_temp_233 + l32i a12,a1,80 # [3] gra_spill_temp_232 + l32i a9,a1,176 # [4] gra_spill_temp_256 + l32i a11,a1,88 # [5] gra_spill_temp_234 + addi.n a9,a9,1 # [6] + s32i a9,a1,176 # [7] gra_spill_temp_256 + add.n a11,a11,a12 # [8] + add.n a13,a13,a14 # [9] + s32i a13,a1,84 # [10] gra_spill_temp_233 + s32i a11,a1,88 # [11] gra_spill_temp_234 + beq a9,a10,.Lt_10_9986 # [12] + +.Lt_10_10498: # 0x193d + l32i a15,a1,108 # [0] gra_spill_temp_239 + blti a15,1,.Lt_10_10754 # [2] + + l32i a2,a1,84 # [0] gra_spill_temp_233 + l32i a10,a1,104 # [1] gra_spill_temp_238 + l32i a9,a1,88 # [2] gra_spill_temp_234 + movi.n a8,0 # [3] + s32i a8,a1,120 # [4] gra_spill_temp_242 + add.n a9,a9,a10 # [5] + s32i a9,a1,124 # [6] gra_spill_temp_243 + j .Lt_10_11266 # [7] + +.Lt_10_11522: # 0x1959 + addmi a12,a1,256 # [0] + l32i a14,a1,112 # [1] gra_spill_temp_240 + movi.n a13,16 # [2] + ee.st.qacc_l.l.128.ip a14,16 # [3] id:234 + ee.st.qacc_l.h.32.ip a14,-16 # [4] id:235 + ee.srcmb.s16.qacc q5,a13,0 # [5] + l16ui a15,a1,10 # [6] qacc_scratch+10 + l8ui a8,a1,15 # [7] qacc_scratch+15 + l8ui a9,a1,5 # [8] qacc_scratch+5 + l8ui a11,a1,16 # [9] qacc_scratch+16 + l8ui a10,a1,6 # [10] qacc_scratch+6 + s8i a10,a1,3 # [11] qacc_scratch+3 + s8i a11,a1,7 # [12] qacc_scratch+7 + s8i a9,a1,2 # [13] qacc_scratch+2 + + l32i a11,a1,104 # [14] gra_spill_temp_238 + s8i a8,a1,6 # [15] qacc_scratch+6 + s16i a15,a1,4 # [16] qacc_scratch+4 + ee.vld.l.64.ip q0,a14,0 # [17] id:245 + s32i a14,a1,112 # [18] gra_spill_temp_240 + ee.vzip.16 q0,q5 # [19] + st.qr q5,a12,-16 # [20] gra_spill_temp_260-256 + + beqz.n a11,.Lt_10_13570 # [21] // skip_bias + + // add bias + l32i a13,a1,124 # [0] gra_spill_temp_243 + extui a12,a13,0,4 # [2] + ee.vld.128.ip q7,a13,16 # [3] id:248 + ee.vld.128.ip q1,a13,0 # [4] id:249 + wur.sar_byte a12 # [5] + ee.src.q.qup q6,q7,q1 # [6] + ee.vadds.s32 q0,q0,q6 # [7] + +.Lt_10_13570: # 0x19ae + #1287 q0 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q0, out_mult_ptr, out_shift_ptr); + l32i a10,a1,128 # [0] gra_spill_temp_244 + l32i a11,a1,132 # [1] gra_spill_temp_245 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [2] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + addi.n a2,a2,4 # [0] + l32i a13,a1,96 # [1] gra_spill_temp_236 + l32i a11,a1,128 # [2] gra_spill_temp_244 + l32i a10,a1,132 # [3] gra_spill_temp_245 + addi a8,a1,112 # [4] + ld.qr q1,a8,96 # [5] gra_spill_temp_258-112 + ld.qr q2,a8,80 # [6] gra_spill_temp_257-112 + addi a10,a10,16 # [7] + addi a11,a11,16 # [8] + s32i a11,a1,128 # [9] gra_spill_temp_244 + ee.vadds.s32 q0,q0,q2 # [10] + s32i a10,a1,132 # [11] gra_spill_temp_245 + ee.vmin.s32 q0,q0,q1 # [12] + ld.qr q1,a8,112 # [13] gra_spill_temp_259-112 + l32i a8,a1,116 # [14] gra_spill_temp_241 + ee.vmax.s32 q0,q0,q1 # [15] + ee.movi.32.a q0,a14,2 # [16] + ee.movi.32.a q0,a15,1 # [17] + ee.movi.32.a q0,a9,0 # [18] + add.n a13,a8,a13 # [19] + ee.movi.32.a q0,a12,3 # [20] + addi.n a8,a8,4 # [21] + s8i a12,a13,3 # [22] id:254 + s32i a8,a1,116 # [23] gra_spill_temp_241 + s8i a9,a13,0 # [24] id:251 + s8i a15,a13,1 # [25] id:252 + s8i a14,a13,2 # [26] id:253 + l32i a15,a1,108 # [27] gra_spill_temp_239 + l32i a14,a1,120 # [28] gra_spill_temp_242 + l32i a9,a1,124 # [29] gra_spill_temp_243 + addi.n a14,a14,4 # [30] + addi a9,a9,16 # [31] + s32i a9,a1,124 # [32] gra_spill_temp_243 + s32i a14,a1,120 # [33] gra_spill_temp_242 + bge a14,a15,.Lt_10_10754 # [34] + +.Lt_10_11266: # 0x1a1c +# Loop body line 1230, nesting depth: 4, estimated iterations: 100 + ee.zero.qacc # [0] + l32i a9,a1,100 # [1] gra_spill_temp_237 + s32i a9,a1,172 # [2] gra_spill_temp_255 + bge a9,a7,.Lt_10_11522 # [3] + + mull a15,a9,a4 # [0] + l32i a14,a1,92 # [1] gra_spill_temp_235 + add.n a11,a15,a5 # [2] + add.n a14,a14,a9 # [3] + mull a14,a3,a14 # [4] + s32i a11,a1,168 # [5] gra_spill_temp_254 + bge a6,a5,.Lt_10_12290 # [6] + +.LBB18_esp_nn_depthwise_conv_s16_mult4: # 0x1a3b + l32i a10,a1,176 # [0] gra_spill_temp_256 + l32i a11,a1,164 # [1] gra_spill_temp_253 + l32i a12,a1,160 # [2] gra_spill_temp_252 + add.n a9,a15,a6 # [3] + l32i a8,a1,140 # [4] gra_spill_temp_247 + addmi a13,a1,256 # [5] + ld.qr q1,a13,-16 # [6] gra_spill_temp_260-256 + mull a8,a8,a9 # [7] + add.n a12,a12,a6 # [8] + l32i a9,a1,152 # [9] gra_spill_temp_250 + add.n a12,a14,a12 # [10] + mull a11,a11,a12 # [11] + add.n a8,a2,a8 # [12] + l32i a12,a1,148 # [13] gra_spill_temp_249 + addx2 a8,a8,a9 # [14] + add.n a10,a10,a11 # [15] + l32i a11,a1,136 # [16] gra_spill_temp_246 + l32i a9,a1,156 # [17] gra_spill_temp_251 + addx2 a10,a10,a11 # [18] + l32i a11,a1,144 # [19] gra_spill_temp_248 + loopgtz a9,.LBB45_esp_nn_depthwise_conv_s16_mult4 # [20] + + mov.n a9,a8 # [0*II+0] + ee.vldbc.16 q0,a10 # [0*II+1] id:232 + add.n a10,a10,a12 # [0*II+2] + ee.vld.l.64.ip q1,a9,0 # [0*II+3] id:231 + add.n a8,a8,a11 # [0*II+4] + ee.vmulas.s16.qacc q0,q1 # [0*II+5] +.LBB45_esp_nn_depthwise_conv_s16_mult4: # 0x1a84 + + addmi a10,a1,256 # [0] + st.qr q1,a10,-16 # [1] gra_spill_temp_260-256 + +.Lt_10_12290: # 0x1a8a + add.n a14,a14,a3 # [0] + add.n a15,a15,a4 # [1] + l32i a11,a1,172 # [2] gra_spill_temp_255 + l32i a12,a1,168 # [3] gra_spill_temp_254 + addi.n a11,a11,1 # [4] + add.n a12,a12,a4 # [5] + s32i a12,a1,168 # [6] gra_spill_temp_254 + s32i a11,a1,172 # [7] gra_spill_temp_255 + sub a11,a7,a11 # [8] + beqz a11,.Lt_10_11522 # [9] + + blt a6,a5,.LBB18_esp_nn_depthwise_conv_s16_mult4 # [0] + + j .Lt_10_12290 # [0] + +.Lt_10_8450: # 0x1aaa + retw.n # [0] + + .size esp_nn_depthwise_conv_s16_mult4_esp32s3, . - esp_nn_depthwise_conv_s16_mult4_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3.S new file mode 100644 index 0000000..b894713 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3.S @@ -0,0 +1,458 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + + # Program Unit: esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3 + .type esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3, @function + .align 4 + .global esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3 + +esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3: # 0x11b3 + # qacc_scratch = 0 + # gra_spill_temp_142 = 48 + # gra_spill_temp_143 = 52 + # gra_spill_temp_144 = 56 + # gra_spill_temp_145 = 60 + # gra_spill_temp_146 = 64 + # gra_spill_temp_147 = 68 + # gra_spill_temp_148 = 72 + # gra_spill_temp_149 = 76 + # gra_spill_temp_150 = 80 + # gra_spill_temp_151 = 84 + # gra_spill_temp_152 = 88 + # gra_spill_temp_153 = 92 + # gra_spill_temp_154 = 96 + # gra_spill_temp_155 = 100 + # gra_spill_temp_156 = 104 + # gra_spill_temp_157 = 108 + # gra_spill_temp_158 = 112 + # gra_spill_temp_159 = 116 + # gra_spill_temp_160 = 120 + # gra_spill_temp_161 = 124 + # gra_spill_temp_162 = 128 + # gra_spill_temp_163 = 132 + # gra_spill_temp_164 = 136 + # gra_spill_temp_165 = 140 + # gra_spill_temp_166 = 144 + # gra_spill_temp_167 = 148 + # gra_spill_temp_168 = 152 + # gra_spill_temp_169 = 156 + # gra_spill_temp_170 = 160 + # gra_spill_temp_171 = 164 + # gra_spill_temp_172 = 168 + # gra_spill_temp_173 = 172 + # gra_spill_temp_174 = 176 + # gra_spill_temp_175 = 180 + # gra_spill_temp_176 = 184 + # gra_spill_temp_177 = 188 + # gra_spill_temp_178 = 192 + # gra_spill_temp_179 = 208 + # gra_spill_temp_180 = 224 + # gra_spill_temp_181 = 240 + # gra_spill_temp_182 = 256 + + // registers: + // a2: const int16_t *input_data + // a3: const uint16_t input_wd + // a4: const uint16_t input_ht + // a5: const uint16_t channels + // a6: const uint16_t pad_wd + // a7: const uint16_t pad_ht + + // const uint16_t stride_wd + // const uint16_t stride_ht + // const uint16_t ch_mult + // const int16_t *filter_data + // const int32_t *bias + // int8_t *out_data + // const uint16_t out_wd + // const uint16_t out_ht + // const int32_t out_offset + // const int32_t *out_shift + // const int32_t *out_mult + // const int32_t activation_min + // const int32_t activation_max + + entry a1,304 # + s32i a2,a1,116 # [0] gra_spill_temp_159 + s32i a3,a1,120 # [1] gra_spill_temp_160 + s32i a5,a1,144 # [2] gra_spill_temp_166 + s32i.n a6,a1,60 # [3] gra_spill_temp_145 + + addmi a9,a1,256 # [4] + addi a12,a1,112 # [5] + addmi a10,a1,256 # [6] + addmi a11,a1,256 # [7] + addmi a13,a1,256 # [8] + + // height loop + l16ui a8,a1,332 # [9] id:261 out_ht+0x0 + l32i a14,a1,324 # [10] id:257 out_data+0x0 + s32i a14,a1,176 # [11] gra_spill_temp_174 + s32i a8,a1,68 # [12] gra_spill_temp_147 + addi a13,a13,80 # [13] + addi a11,a11,96 # [14] + addi a10,a10,92 # [15] + ee.vldbc.32 q0,a10 # [16] id:260 activation_min + ee.vldbc.32 q1,a11 # [17] id:259 activation_max + ee.vldbc.32 q2,a13 # [18] id:258 out_offset + st.qr q2,a12,96 # [19] gra_spill_temp_179-112 + st.qr q1,a12,112 # [20] gra_spill_temp_180-112 + st.qr q0,a9,-16 # [21] gra_spill_temp_181-256 + beqz.n a8,.Lt_8_8194 # [22] + +.LBB3_esp_nn_depthwise_conv_s16_mult8_3x3: # 0x11f9 + s32i a1,a1,180 # [0] gra_spill_temp_175 + mul16u a6,a3,a5 # [1] + s32i a7,a1,76 # [2] gra_spill_temp_149 + l32i a9,a1,316 # [3] id:264 filter_data+0x0 + l32i a15,a1,320 # [4] id:262 bias+0x0 + l16ui a10,a1,312 # [5] id:263 ch_mult+0x0 + slli a11,a5,1 # [6] + l16ui a12,a1,308 # [7] id:268 stride_ht+0x0 + l32i a13,a1,344 # [8] id:267 out_mult+0x0 + l32i a14,a1,340 # [9] id:266 out_shift+0x0 + s32i a14,a1,88 # [10] gra_spill_temp_152 + s32i a13,a1,92 # [11] gra_spill_temp_153 + s32i a12,a1,64 # [12] gra_spill_temp_146 + s32i a11,a1,124 # [13] gra_spill_temp_161 + s32i a10,a1,108 # [14] gra_spill_temp_157 + s32i a15,a1,160 # [15] gra_spill_temp_170 + s32i a9,a1,128 # [16] gra_spill_temp_162 + neg a7,a7 # [17] + slli a6,a6,1 # [18] + s32i a7,a1,136 # [19] gra_spill_temp_164 + movi.n a9,0 # [20] + extui a15,a15,0,4 # [21] + s32i a15,a1,152 # [22] gra_spill_temp_168 + s32i a9,a1,72 # [23] gra_spill_temp_148 + sub a7,a4,a7 # [24] + l32i.n a9,a1,60 # [25] gra_spill_temp_145 + s32i a7,a1,80 # [26] gra_spill_temp_150 + l16ui a4,a1,328 # [27] id:269 out_wd+0x0 + s32i a4,a1,96 # [28] gra_spill_temp_154 + l16ui a7,a1,304 # [29] id:265 stride_wd+0x0 + s32i a7,a1,84 # [30] gra_spill_temp_151 + mul16u a4,a5,a10 # [31] + neg a9,a9 # [32] + s32i.n a9,a1,52 # [33] gra_spill_temp_143 + sub a8,a3,a9 # [34] + addi a10,a10,-7 # [35] + s32i a10,a1,164 # [36] gra_spill_temp_171 + s32i.n a8,a1,56 # [37] gra_spill_temp_144 + addx2 a7,a4,a4 # [38] + slli a7,a7,1 # [39] + j .Lt_8_8706 # [40] + +.Lt_8_8962: # 0x1270 +# Part of loop body line 933, head labeled .Lt_8_8706 + l32i a10,a1,68 # [0] gra_spill_temp_147 + l32i a14,a1,76 # [1] gra_spill_temp_149 + l32i a13,a1,136 # [2] gra_spill_temp_164 + l32i a12,a1,64 # [3] gra_spill_temp_146 + l32i a9,a1,72 # [4] gra_spill_temp_148 + l32i a11,a1,80 # [5] gra_spill_temp_150 + addi.n a9,a9,1 # [6] + s32i a9,a1,72 # [7] gra_spill_temp_148 + sub a11,a11,a12 # [8] + add.n a13,a13,a12 # [9] + sub a14,a14,a12 # [10] + s32i a14,a1,76 # [11] gra_spill_temp_149 + s32i a13,a1,136 # [12] gra_spill_temp_164 + s32i a11,a1,80 # [13] gra_spill_temp_150 + sub a9,a9,a10 # [14] + beqz a9,.Lt_8_8194 # [15] + +.Lt_8_8706: # 0x129e +# Loop body line 933, nesting depth: 1, estimated iterations: 100 + # 934 const int32_t base_y = (out_y * stride_ht) - pad_ht; + # 935 for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + l32i a15,a1,96 # [0] gra_spill_temp_154 + beqz.n a15,.Lt_8_8962 # [2] + +.LBB6_esp_nn_depthwise_conv_s16_mult8_3x3: # 0x12a3 +# Part of loop body line 933, head labeled .Lt_8_8706 + l32i.n a3,a1,56 # [0] gra_spill_temp_144 + l32i a8,a1,80 # [1] gra_spill_temp_150 + movi.n a10,0 # [2] + l32i a9,a1,76 # [3] gra_spill_temp_149 + movi.n a11,0 # [4] + l32i.n a12,a1,52 # [5] gra_spill_temp_143 + l32i.n a13,a1,60 # [6] gra_spill_temp_145 + s32i a13,a1,104 # [7] gra_spill_temp_156 + s32i a12,a1,140 # [8] gra_spill_temp_165 + s32i a11,a1,100 # [9] gra_spill_temp_155 + max a9,a9,a10 # [10] + movi.n a10,3 # [11] + s32i a9,a1,172 # [12] gra_spill_temp_173 + min a8,a8,a10 # [13] + s32i a8,a1,156 # [14] gra_spill_temp_169 + sub a8,a8,a9 # [15] + s32i a8,a1,132 # [16] gra_spill_temp_163 + j .Lt_8_9474 # [17] + +.Lt_8_9730: # 0x12d3 +# Part of loop body line 935, head labeled .Lt_8_9474 + l32i a15,a1,96 # [0] gra_spill_temp_154 + l32i a10,a1,104 # [1] gra_spill_temp_156 + l32i a9,a1,140 # [2] gra_spill_temp_165 + l32i a8,a1,84 # [3] gra_spill_temp_151 + l32i a14,a1,100 # [4] gra_spill_temp_155 + sub a3,a3,a8 # [5] + addi.n a14,a14,1 # [6] + s32i a14,a1,100 # [7] gra_spill_temp_155 + add.n a9,a9,a8 # [8] + sub a10,a10,a8 # [9] + s32i a10,a1,104 # [10] gra_spill_temp_156 + s32i a9,a1,140 # [11] gra_spill_temp_165 + beq a14,a15,.Lt_8_8962 # [12] + +.Lt_8_9474: # 0x12f8 + # 936 const int32_t base_x = (out_x * stride_wd) - pad_wd; + # 937 const int32_t *out_mult_ptr = out_mult; + # 938 const int32_t *out_shift_ptr = out_shift; + l32i a2,a1,88 # [0] gra_spill_temp_152 + l32i a10,a1,92 # [1] gra_spill_temp_153 + # 939 uint32_t bias_ptr = (uint32_t) (bias); + l32i a12,a1,160 # [2] gra_spill_temp_170 + # 940 + # 941 for (int ch_idx = 0; ch_idx < channels; ch_idx++) {//channel_loop + l32i a11,a1,144 # [3] gra_spill_temp_166 + s32i a12,a1,168 # [4] gra_spill_temp_172 + beqz.n a11,.Lt_8_9730 # [5] + +.LBB9_esp_nn_depthwise_conv_s16_mult8_3x3: # 0x1309 +# Part of loop body line 935, head labeled .Lt_8_9474 + movi.n a8,0 # [0] + l32i a5,a1,104 # [1] gra_spill_temp_156 + movi.n a13,0 # [2] + movi.n a9,0 # [3] + s32i a9,a1,112 # [4] gra_spill_temp_158 + s32i a13,a1,148 # [5] gra_spill_temp_167 + max a5,a5,a8 # [6] + j .Lt_8_10242 # [7] + +.Lt_8_10498: # 0x131e +# Part of loop body line 941, head labeled .Lt_8_10242 + l32i a12,a1,144 # [0] gra_spill_temp_166 + l32i a14,a1,108 # [1] gra_spill_temp_157 + l32i a11,a1,148 # [2] gra_spill_temp_167 + l32i a13,a1,112 # [3] gra_spill_temp_158 + addi.n a11,a11,1 # [4] + s32i a11,a1,148 # [5] gra_spill_temp_167 + add.n a13,a13,a14 # [6] + s32i a13,a1,112 # [7] gra_spill_temp_158 + beq a11,a12,.Lt_8_9730 # [8] + +.Lt_8_10242: # 0x1337 + # 942 for (int ch_mult_idx = 0; ch_mult_idx < ch_mult - 7; ch_mult_idx += 8) { + l32i a15,a1,164 # [0] gra_spill_temp_171 + blti a15,1,.Lt_8_10498 # [2] + + movi.n a8,0 # [0] + l32i a9,a1,112 # [1] gra_spill_temp_158 + s32i a9,a1,188 # [2] gra_spill_temp_177 + s32i a8,a1,184 # [3] gra_spill_temp_176 + j .Lt_8_11010 # [4] + +.LBB23_esp_nn_depthwise_conv_s16_mult8_3x3: # 0x134b + s32i.n a10,a1,48 # [0] gra_spill_temp_142 + addi a11,a1,112 # [1] + l32i a13,a1,152 # [2] gra_spill_temp_168 + l32i a12,a1,168 # [3] gra_spill_temp_172 + wur.sar_byte a13 # [4] + ee.vld.128.ip q4,a12,16 # [5] id:307 + ee.vld.128.ip q7,a12,16 # [6] id:308 + ee.vld.128.ip q5,a12,0 # [7] id:309 + s32i a12,a1,168 # [8] gra_spill_temp_172 + ee.src.q.qup q6,q4,q7 # [9] + ee.vadds.s32 q0,q0,q6 # [10] + ee.src.q.qup q3,q4,q5 # [11] + ee.vadds.s32 q1,q1,q3 # [12] + st.qr q1,a11,80 # [13] gra_spill_temp_178-112 + +.Lt_8_13314: # 0x1374 + #1025 q0 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q0, out_mult_ptr, out_shift_ptr); + l32i.n a10,a1,48 # [0] gra_spill_temp_142 + mov.n a11,a2 # [1] + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + #1026 out_mult_ptr += 4; + #1027 out_shift_ptr += 4; + #1028 + #1029 q1 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q1, out_mult_ptr, out_shift_ptr); + l32i.n a10,a1,48 # [0] gra_spill_temp_142 + addmi a12,a1,256 # [1] + addi a11,a1,112 # [2] + st.qr q0,a12,0 # [3] gra_spill_temp_182-256 + ld.qr q0,a11,80 # [4] gra_spill_temp_178-112 + addi a10,a10,16 # [5] + addi a11,a2,16 # [6] + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + +# Part of loop body line 942, head labeled .Lt_8_11010 + #1030 out_mult_ptr += 4; + #1031 out_shift_ptr += 4; + addi a2,a2,32 # [0] + l32i a14,a1,164 # [1] gra_spill_temp_171 + + l32i a8,a1,176 # [2] gra_spill_temp_174 + l32i a15,a1,188 # [3] gra_spill_temp_177 + l32i a13,a1,184 # [4] gra_spill_temp_176 + l32i.n a10,a1,48 # [5] gra_spill_temp_142 + addmi a11,a1,256 # [6] + addi a12,a1,112 # [7] + ld.qr q3,a12,112 # [8] gra_spill_temp_180-112 + ld.qr q1,a12,96 # [9] gra_spill_temp_179-112 + ld.qr q2,a11,0 # [10] gra_spill_temp_182-256 + addi a10,a10,32 # [11] + addi.n a13,a13,8 # [12] + addi.n a15,a15,8 # [13] + s32i a15,a1,188 # [14] gra_spill_temp_177 + ee.vadds.s32 q2,q2,q1 # [15] + s32i a13,a1,184 # [16] gra_spill_temp_176 + ee.vadds.s32 q1,q0,q1 # [17] + ee.vmin.s32 q0,q2,q3 # [18] + ld.qr q2,a11,-16 # [19] gra_spill_temp_181-256 + ee.vmin.s32 q1,q1,q3 # [20] + ee.vmax.s32 q1,q1,q2 # [21] + ee.vmax.s32 q0,q0,q2 # [22] + ee.vunzip.16 q0,q1 # [23] + ee.vunzip.8 q0,q1 # [24] + ee.vst.l.64.ip q0,a8,8 # [25] id:312 + s32i a8,a1,176 # [26] gra_spill_temp_174 + bge a13,a14,.Lt_8_10498 # [27] + +.Lt_8_11010: # 0x13e3 +# Loop body line 942, nesting depth: 4, estimated iterations: 100 + l32i a14,a1,156 # [0] gra_spill_temp_169 + l32i a13,a1,172 # [1] gra_spill_temp_173 + ee.zero.qacc # [2] + bge a13,a14,.Lt_8_11266 # [3] + +.LBB15_esp_nn_depthwise_conv_s16_mult8_3x3: # 0x13ef +# Part of loop body line 942, head labeled .Lt_8_11010 + l32i a12,a1,124 # [0] gra_spill_temp_161 + l32i a8,a1,140 # [1] gra_spill_temp_165 + l32i a11,a1,120 # [2] gra_spill_temp_160 + l32i a14,a1,188 # [3] gra_spill_temp_177 + l32i a9,a1,136 # [4] gra_spill_temp_164 + mull a15,a4,a13 # [5] + add.n a9,a9,a13 # [6] + addx2 a15,a15,a15 # [7] + l32i a13,a1,148 # [8] gra_spill_temp_167 + add.n a14,a14,a15 # [9] + mull a9,a9,a11 # [10] + l32i a15,a1,144 # [11] gra_spill_temp_166 + add.n a8,a8,a9 # [12] + mull a15,a15,a8 # [13] + l32i a8,a1,128 # [14] gra_spill_temp_162 + add.n a13,a13,a15 # [15] + l32i a15,a1,116 # [16] gra_spill_temp_159 + addx2 a14,a14,a8 # [17] + addx2 a13,a13,a15 # [18] + add.n a11,a12,a13 # [19] + l32i a15,a1,132 # [20] gra_spill_temp_163 + add.n a12,a12,a11 # [21] + loopgtz a15,.LBB34_esp_nn_depthwise_conv_s16_mult8_3x3 # [22] + +.Lt_8_11778: # 0x142e + mov.n a15,a14 # [0] + mov.n a9,a14 # [1] + bnez.n a5,.Lt_8_12034 # [2] + + ee.vldbc.16 q3,a13 # [0] id:271 + mov.n a9,a14 # [1] + ee.vld.128.ip q4,a9,0 # [2] id:272 + ee.vmulas.s16.qacc q3,q4 # [4] + +.Lt_8_12034: # 0x143f + ee.vldbc.16 q5,a11 # [0] id:274 + addx2 a9,a4,a9 # [1] + ee.vld.128.ip q6,a9,0 # [2] id:275 + add.n a13,a13,a6 # [3] + ee.vmulas.s16.qacc q5,q6 # [4] + blti a3,3,.Lt_8_12546 # [5] + + ee.vldbc.16 q7,a12 # [0] id:277 + addx2 a14,a4,a9 # [1] + ee.vld.128.ip q0,a14,0 # [2] id:278 + ee.vmulas.s16.qacc q7,q0 # [4] + +.Lt_8_12546: # 0x145c +# Part of loop body line 953, head labeled .Lt_8_11778 + add.n a11,a11,a6 # [0] + add.n a12,a12,a6 # [1] + add.n a14,a7,a15 # [2] + +.LBB34_esp_nn_depthwise_conv_s16_mult8_3x3: # 0x1464 +.Lt_8_11266: # 0x1464 + + l32i a8,a1,180 # [0] gra_spill_temp_175 + ee.st.qacc_l.l.128.ip a8,16 # [2] id:280 + ee.st.qacc_l.h.32.ip a8,0 # [3] id:281 + l16ui a9,a1,10 # [4] qacc_scratch+10 + l8ui a11,a1,15 # [5] qacc_scratch+15 + l8ui a12,a1,5 # [6] qacc_scratch+5 + l8ui a13,a1,6 # [7] qacc_scratch+6 + l8ui a14,a1,16 # [8] qacc_scratch+16 + s8i a14,a1,7 # [9] qacc_scratch+7 + s8i a13,a1,3 # [10] qacc_scratch+3 + s8i a12,a1,2 # [11] qacc_scratch+2 + s8i a11,a1,6 # [12] qacc_scratch+6 + s16i a9,a1,4 # [13] qacc_scratch+4 + ee.st.qacc_h.l.128.ip a8,16 # [14] id:291 + ee.st.qacc_h.h.32.ip a8,-32 # [15] id:292 + l16ui a9,a1,16 # [16] qacc_scratch+16 + l8ui a15,a1,32 # [17] qacc_scratch+32 + l8ui a12,a1,22 # [18] qacc_scratch+22 + l8ui a11,a1,21 # [19] qacc_scratch+21 + l8ui a14,a1,31 # [20] qacc_scratch+31 + l16ui a13,a1,26 # [21] qacc_scratch+26 + s16i a13,a1,12 # [22] qacc_scratch+12 + s8i a14,a1,14 # [23] qacc_scratch+14 + s8i a11,a1,10 # [24] qacc_scratch+10 + s8i a12,a1,11 # [25] qacc_scratch+11 + s8i a15,a1,15 # [26] qacc_scratch+15 + s16i a9,a1,8 # [27] qacc_scratch+8 + l32i a15,a1,160 # [28] gra_spill_temp_170 + movi.n a9,16 # [29] + ee.srcmb.s16.qacc q1,a9,0 # [30] + ee.vld.128.ip q0,a8,0 # [31] id:304 + s32i a8,a1,180 # [32] gra_spill_temp_175 + ee.vzip.16 q0,q1 # [33] + bnez.n a15,.LBB23_esp_nn_depthwise_conv_s16_mult8_3x3 # [34] + + s32i.n a10,a1,48 # [0] gra_spill_temp_142 + addi a15,a1,112 # [1] + st.qr q1,a15,80 # [2] gra_spill_temp_178-112 + j .Lt_8_13314 # [3] + +.Lt_8_8194: # 0x14d3 + retw.n # [0] + + .size esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3, . - esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult8_esp32s3.S new file mode 100644 index 0000000..4f9143b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s16_mult8_esp32s3.S @@ -0,0 +1,432 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + + # Program Unit: esp_nn_depthwise_conv_s16_mult8_esp32s3 + .type esp_nn_depthwise_conv_s16_mult8_esp32s3, @function + .align 4 + .global esp_nn_depthwise_conv_s16_mult8_esp32s3 + +esp_nn_depthwise_conv_s16_mult8_esp32s3: # 0x14d7 + # qacc_scratch = 0 + # gra_spill_temp_183 = 48 + # gra_spill_temp_184 = 52 + # gra_spill_temp_185 = 56 + # gra_spill_temp_186 = 60 + # gra_spill_temp_187 = 64 + # gra_spill_temp_188 = 68 + # gra_spill_temp_189 = 72 + # gra_spill_temp_190 = 76 + # gra_spill_temp_191 = 80 + # gra_spill_temp_192 = 84 + # gra_spill_temp_193 = 88 + # gra_spill_temp_194 = 92 + # gra_spill_temp_195 = 96 + # gra_spill_temp_196 = 100 + # gra_spill_temp_197 = 104 + # gra_spill_temp_198 = 108 + # gra_spill_temp_199 = 112 + # gra_spill_temp_200 = 116 + # gra_spill_temp_201 = 120 + # gra_spill_temp_202 = 124 + # gra_spill_temp_203 = 128 + # gra_spill_temp_204 = 132 + # gra_spill_temp_205 = 136 + # gra_spill_temp_206 = 140 + # gra_spill_temp_207 = 144 + # gra_spill_temp_208 = 148 + # gra_spill_temp_209 = 152 + # gra_spill_temp_210 = 156 + # gra_spill_temp_211 = 160 + # gra_spill_temp_212 = 164 + # gra_spill_temp_213 = 168 + # gra_spill_temp_214 = 172 + # gra_spill_temp_215 = 176 + # gra_spill_temp_216 = 180 + # gra_spill_temp_217 = 184 + # gra_spill_temp_218 = 192 + # gra_spill_temp_219 = 208 + + // registers: + // a2: const int16_t *input_data + // a3: const uint16_t input_wd + // a4: const uint16_t input_ht + // a5: const uint16_t channels + // a6: const uint16_t pad_wd + // a7: const uint16_t pad_ht + + // on stack: + // const uint16_t stride_wd + // const uint16_t stride_ht + // const uint16_t ch_mult + // const int16_t *filter_data + // const uint16_t filter_wd + // const uint16_t filter_ht + // const int32_t *bias + // int8_t *out_data + // const uint16_t out_wd + // const uint16_t out_ht + // const int32_t out_offset + // const int32_t *out_shift + // const int32_t *out_mult + // const int32_t activation_min + // const int32_t activation_max + + entry a1,256 # + s32i a2,a1,144 # [0] gra_spill_temp_207 + s32i.n a4,a1,56 # [1] gra_spill_temp_185 + s32i a5,a1,172 # [2] gra_spill_temp_214 + l32i a9,a1,284 # [3] id:241 out_data+0x0 + + l16ui a8,a1,292 # [4] id:242 out_ht+0x0 + s32i a8,a1,64 # [5] gra_spill_temp_187 + s32i a9,a1,124 # [6] gra_spill_temp_202 + beqz.n a8,.Lt_9_8450 # [7] + + s32i a1,a1,128 # [0] gra_spill_temp_203 + neg a13,a7 # [1] + movi.n a4,0 # [2] + neg a12,a6 # [3] + l32i a9,a1,280 # [4] id:243 bias+0x0 + slli a11,a5,1 # [5] + l16ui a10,a1,264 # [6] id:244 ch_mult+0x0 + l32i a14,a1,268 # [7] id:245 filter_data+0x0 + s32i a14,a1,160 # [8] gra_spill_temp_211 + s32i a10,a1,92 # [9] gra_spill_temp_194 + s32i a11,a1,156 # [10] gra_spill_temp_210 + s32i a9,a1,112 # [11] gra_spill_temp_199 + sext a12,a12,15 # [12] + s32i a4,a1,68 # [13] gra_spill_temp_188 + sext a13,a13,15 # [14] + l16ui a4,a1,272 # [15] id:246 filter_wd+0x0 + s32i a13,a1,100 # [16] gra_spill_temp_196 + s32i.n a12,a1,48 # [17] gra_spill_temp_183 + mul16u a8,a5,a10 # [18] + extui a9,a9,0,4 # [19] + l32i a11,a1,304 # [20] id:249 out_mult+0x0 + s32i a11,a1,80 # [21] gra_spill_temp_191 + s32i a9,a1,104 # [22] gra_spill_temp_197 + s32i a8,a1,148 # [23] gra_spill_temp_208 + addi a10,a10,-7 # [24] + l32i a12,a1,300 # [25] id:248 out_shift+0x0 + l16ui a13,a1,256 # [26] id:247 stride_wd+0x0 + s32i a13,a1,72 # [27] gra_spill_temp_189 + s32i a12,a1,76 # [28] gra_spill_temp_190 + s32i a10,a1,116 # [29] gra_spill_temp_200 + slli a8,a8,1 # [30] + l16ui a9,a1,260 # [31] id:251 stride_ht+0x0 + s32i.n a9,a1,60 # [32] gra_spill_temp_186 + s32i a8,a1,152 # [33] gra_spill_temp_209 + l16ui a10,a1,276 # [34] id:250 filter_ht+0x0 + s32i.n a10,a1,52 # [35] gra_spill_temp_184 + l16ui a8,a1,288 # [36] id:252 out_wd+0x0 + s32i a8,a1,84 # [37] gra_spill_temp_192 + j .Lt_9_8962 # [38] + +.Lt_9_9218: # 0x1561 +# Part of loop body line 1083, head labeled .Lt_9_8962 + l32i a15,a1,64 # [0] gra_spill_temp_187 + l32i.n a9,a1,60 # [1] gra_spill_temp_186 + l32i a14,a1,68 # [2] gra_spill_temp_188 + l32i a8,a1,100 # [3] gra_spill_temp_196 + addi.n a14,a14,1 # [4] + s32i a14,a1,68 # [5] gra_spill_temp_188 + add.n a9,a8,a9 # [6] + sub a14,a14,a15 # [7] + sext a8,a9,15 # [8] + s32i a8,a1,100 # [9] gra_spill_temp_196 + beqz a14,.Lt_9_8450 # [10] + +.Lt_9_8962: # 0x157f + l32i a10,a1,84 # [0] gra_spill_temp_192 + beqz.n a10,.Lt_9_9218 # [2] + + l32i.n a7,a1,52 # [0] gra_spill_temp_184 + movi.n a11,0 # [1] + l32i.n a8,a1,56 # [2] gra_spill_temp_185 + l32i a9,a1,100 # [3] gra_spill_temp_196 + l32i.n a12,a1,48 # [4] gra_spill_temp_183 + s32i a12,a1,168 # [5] gra_spill_temp_213 + neg a10,a9 # [6] + sub a8,a8,a9 # [7] + max a10,a10,a11 # [8] + s32i a10,a1,108 # [9] gra_spill_temp_198 + min a7,a7,a8 # [10] + movi.n a11,0 # [11] + s32i a11,a1,88 # [12] gra_spill_temp_193 + j .Lt_9_9730 # [13] + +.Lt_9_9986: # 0x15a9 +# Part of loop body line 1085, head labeled .Lt_9_9730 + l32i a13,a1,84 # [0] gra_spill_temp_192 + l32i a15,a1,72 # [1] gra_spill_temp_189 + l32i a12,a1,88 # [2] gra_spill_temp_193 + l32i a14,a1,168 # [3] gra_spill_temp_213 + addi.n a12,a12,1 # [4] + s32i a12,a1,88 # [5] gra_spill_temp_193 + add.n a15,a14,a15 # [6] + sext a14,a15,15 # [7] + s32i a14,a1,168 # [8] gra_spill_temp_213 + beq a12,a13,.Lt_9_9218 # [9] + +.Lt_9_9730: # 0x15c5 +# Loop body line 1085, nesting depth: 2, estimated iterations: 100 + #1086 const int16_t base_x = (out_x * stride_wd) - pad_wd; + #1087 const int32_t *out_mult_ptr = out_mult; + #1088 const int32_t *out_shift_ptr = out_shift; + #1089 uint32_t bias_ptr = (uint32_t) (bias); + #1090 for (int ch_idx = 0; ch_idx < channels; ch_idx++) {//channel_loop + l32i a8,a1,172 # [0] gra_spill_temp_214 + l32i a9,a1,80 # [1] gra_spill_temp_191 + l32i a10,a1,76 # [2] gra_spill_temp_190 + l32i a11,a1,112 # [3] gra_spill_temp_199 + s32i a11,a1,120 # [4] gra_spill_temp_201 + s32i a10,a1,140 # [5] gra_spill_temp_206 + s32i a9,a1,136 # [6] gra_spill_temp_205 + beqz.n a8,.Lt_9_9986 # [7] + +.LBB9_esp_nn_depthwise_conv_s16_mult8: # 0x15dc +# Part of loop body line 1085, head labeled .Lt_9_9730 + movi.n a8,0 # [0] + l32i a5,a1,168 # [1] gra_spill_temp_213 + movi.n a13,0 # [2] + movi.n a14,0 # [3] + s32i a14,a1,96 # [4] gra_spill_temp_195 + s32i a13,a1,184 # [5] gra_spill_temp_217 + neg a6,a5 # [6] + max a6,a6,a8 # [7] + sub a5,a3,a5 # [8] + min a5,a4,a5 # [9] + sub a12,a5,a6 # [10] + s32i a12,a1,164 # [11] gra_spill_temp_212 + j .Lt_9_10498 # [12] + +.Lt_9_10754: # 0x1600 +# Part of loop body line 1090, head labeled .Lt_9_10498 + l32i a10,a1,172 # [0] gra_spill_temp_214 + l32i a12,a1,92 # [1] gra_spill_temp_194 + l32i a9,a1,184 # [2] gra_spill_temp_217 + l32i a11,a1,96 # [3] gra_spill_temp_195 + addi.n a9,a9,1 # [4] + s32i a9,a1,184 # [5] gra_spill_temp_217 + add.n a11,a11,a12 # [6] + s32i a11,a1,96 # [7] gra_spill_temp_195 + beq a9,a10,.Lt_9_9986 # [8] + +.Lt_9_10498: # 0x1619 +# Loop body line 1090, nesting depth: 3, estimated iterations: 100 + #1091 for (int ch_mult_idx = 0; ch_mult_idx < ch_mult - 7; ch_mult_idx += 8) { + l32i a13,a1,116 # [0] gra_spill_temp_200 + blti a13,1,.Lt_9_10754 # [2] + +.LBB12_esp_nn_depthwise_conv_s16_mult8: # 0x161f +# Part of loop body line 1090, head labeled .Lt_9_10498 + l32i a2,a1,96 # [0] gra_spill_temp_195 + movi.n a14,0 # [1] + s32i a14,a1,132 # [2] gra_spill_temp_204 + j .Lt_9_11266 # [3] + +.Lt_9_11522: # 0x162a + l32i a9,a1,128 # [0] gra_spill_temp_203 + ee.st.qacc_l.l.128.ip a9,16 # [2] id:257 + ee.st.qacc_l.h.32.ip a9,0 # [3] id:258 + l8ui a10,a1,15 # [4] qacc_scratch+15 + l16ui a8,a1,10 # [5] qacc_scratch+10 + l8ui a13,a1,16 # [6] qacc_scratch+16 + l8ui a12,a1,6 # [7] qacc_scratch+6 + l8ui a11,a1,5 # [8] qacc_scratch+5 + s8i a11,a1,2 # [9] qacc_scratch+2 + s8i a12,a1,3 # [10] qacc_scratch+3 + s8i a13,a1,7 # [11] qacc_scratch+7 + s16i a8,a1,4 # [12] qacc_scratch+4 + s8i a10,a1,6 # [13] qacc_scratch+6 + + movi.n a8,16 # [14] + ee.st.qacc_h.l.128.ip a9,16 # [15] id:268 + ee.st.qacc_h.h.32.ip a9,-32 # [16] id:269 + ee.srcmb.s16.qacc q1,a8,0 # [17] + l16ui a13,a1,26 # [18] qacc_scratch+26 + l8ui a15,a1,32 # [19] qacc_scratch+32 + l8ui a12,a1,22 # [20] qacc_scratch+22 + l8ui a11,a1,21 # [21] qacc_scratch+21 + l16ui a10,a1,16 # [22] qacc_scratch+16 + l8ui a14,a1,31 # [23] qacc_scratch+31 + s8i a14,a1,14 # [24] qacc_scratch+14 + s16i a10,a1,8 # [25] qacc_scratch+8 + s8i a11,a1,10 # [26] qacc_scratch+10 + s8i a12,a1,11 # [27] qacc_scratch+11 + s8i a15,a1,15 # [28] qacc_scratch+15 + s16i a13,a1,12 # [29] qacc_scratch+12 + #1138 EE_VZIP_16(q0, q1); /* 4x32 */ + #1139 + #1140 if (bias) { + l32i a15,a1,112 # [30] gra_spill_temp_199 + ee.vld.128.ip q0,a9,0 # [31] id:281 + s32i a9,a1,128 # [32] gra_spill_temp_203 + ee.vzip.16 q0,q1 # [33] + beqz.n a15,.Lt_9_13570 # [34] + +.LBB23_esp_nn_depthwise_conv_s16_mult8: # 0x168e +# Part of loop body line 1091, head labeled .Lt_9_11266 + addi a14,a1,112 # [0] + l32i a8,a1,104 # [1] gra_spill_temp_197 + l32i a15,a1,120 # [2] gra_spill_temp_201 + wur.sar_byte a8 # [3] + ee.vld.128.ip q3,a15,16 # [4] id:284 + ee.vld.128.ip q6,a15,16 # [5] id:285 + ee.vld.128.ip q4,a15,0 # [6] id:286 + s32i a15,a1,120 # [7] gra_spill_temp_201 + ee.src.q.qup q5,q3,q6 # [8] + ee.vadds.s32 q0,q0,q5 # [9] + ee.src.q.qup q2,q3,q4 # [10] + ee.vadds.s32 q1,q1,q2 # [11] + st.qr q1,a14,96 # [12] gra_spill_temp_219-112 + +.Lt_9_13570: # 0x16b5 + #1158 q0 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q0, out_mult_ptr, out_shift_ptr); + l32i a10,a1,136 # [0] gra_spill_temp_205 + l32i a11,a1,140 # [1] gra_spill_temp_206 + addi a9,a1,112 # [2] + st.qr q1,a9,96 # [3] gra_spill_temp_219-112 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + #1159 out_mult_ptr += 4; + #1160 out_shift_ptr += 4; + #1161 + #1162 q1 = esp_nn_multiply_by_quantized_mult_ver1_esp32s3(q1, out_mult_ptr, out_shift_ptr); + l32i a11,a1,140 # [0] gra_spill_temp_206 + addi a12,a1,112 # [1] + l32i a10,a1,136 # [2] gra_spill_temp_205 + st.qr q0,a12,80 # [3] gra_spill_temp_218-112 + ld.qr q0,a12,96 # [4] gra_spill_temp_219-112 + addi a10,a10,16 # [5] + addi a11,a11,16 # [6] + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + addi.n a2,a2,8 # [0] + l32i a14,a1,116 # [1] gra_spill_temp_200 + l32i a15,a1,124 # [2] gra_spill_temp_202 + l32i a13,a1,132 # [3] gra_spill_temp_204 + l32i a10,a1,140 # [4] gra_spill_temp_206 + l32i a11,a1,136 # [5] gra_spill_temp_205 + addmi a9,a1,256 # [6] + addi a8,a1,112 # [7] + ld.qr q7,a8,80 # [8] gra_spill_temp_218-112 + addi a9,a9,56 # [9] + ee.vldbc.32 q2,a9 # [10] id:290 activation_max + addi a11,a11,32 # [11] + addi a10,a10,32 # [12] + addi.n a13,a13,8 # [13] + s32i a13,a1,132 # [14] gra_spill_temp_204 + s32i a10,a1,140 # [15] gra_spill_temp_206 + s32i a11,a1,136 # [16] gra_spill_temp_205 + addmi a10,a1,256 # [17] + addmi a11,a1,256 # [18] + addi a11,a11,52 # [19] + addi a10,a10,40 # [20] + ee.vldbc.32 q3,a10 # [21] id:289 out_offset + ee.vldbc.32 q1,a11 # [22] id:291 activation_min + ee.vadds.s32 q0,q0,q3 # [23] + ee.vadds.s32 q7,q7,q3 # [24] + ee.vmin.s32 q7,q7,q2 # [25] + ee.vmin.s32 q0,q0,q2 # [26] + ee.vmax.s32 q0,q0,q1 # [27] + ee.vmax.s32 q7,q7,q1 # [28] + ee.vunzip.16 q7,q0 # [29] + ee.vunzip.8 q7,q0 # [30] + ee.vst.l.64.ip q7,a15,8 # [31] id:292 + s32i a15,a1,124 # [32] gra_spill_temp_202 + bge a13,a14,.Lt_9_10754 # [33] + +.Lt_9_11266: # 0x1740 + + ee.zero.qacc # [0] + l32i a12,a1,108 # [1] gra_spill_temp_198 + s32i a12,a1,180 # [2] gra_spill_temp_216 + bge a12,a7,.Lt_9_11522 # [3] + + mull a15,a12,a4 # [0] + l32i a14,a1,100 # [1] gra_spill_temp_196 + add.n a8,a15,a5 # [2] + add.n a14,a14,a12 # [3] + mull a14,a3,a14 # [4] + s32i a8,a1,176 # [5] gra_spill_temp_215 + bge a6,a5,.Lt_9_12290 # [6] + +.LBB18_esp_nn_depthwise_conv_s16_mult8: # 0x175f +# Part of loop body line 1091, head labeled .Lt_9_11266 + l32i a10,a1,184 # [0] gra_spill_temp_217 + l32i a11,a1,172 # [1] gra_spill_temp_214 + l32i a12,a1,168 # [2] gra_spill_temp_213 + l32i a8,a1,148 # [3] gra_spill_temp_208 + add.n a9,a15,a6 # [4] + mull a8,a8,a9 # [5] + add.n a12,a12,a6 # [6] + l32i a9,a1,160 # [7] gra_spill_temp_211 + add.n a12,a14,a12 # [8] + mull a11,a11,a12 # [9] + add.n a8,a2,a8 # [10] + l32i a12,a1,156 # [11] gra_spill_temp_210 + addx2 a8,a8,a9 # [12] + add.n a10,a10,a11 # [13] + l32i a11,a1,144 # [14] gra_spill_temp_207 + l32i a9,a1,164 # [15] gra_spill_temp_212 + addx2 a10,a10,a11 # [16] + l32i a11,a1,152 # [17] gra_spill_temp_209 + loopgtz a9,.LBB45_esp_nn_depthwise_conv_s16_mult8 # [18] + + mov.n a9,a8 # [0*II+0] + ee.vldbc.16 q0,a10 # [0*II+1] id:255 + ee.vld.128.ip q1,a9,0 # [0*II+2] id:254 + add.n a10,a10,a12 # [0*II+3] + add.n a8,a8,a11 # [0*II+4] + ee.vmulas.s16.qacc q0,q1 # [0*II+5] + +.LBB45_esp_nn_depthwise_conv_s16_mult8: # 0x17a2 + +.Lt_9_12290: # 0x17a2 + + add.n a14,a14,a3 # [0] + add.n a15,a15,a4 # [1] + l32i a10,a1,180 # [2] gra_spill_temp_216 + l32i a11,a1,176 # [3] gra_spill_temp_215 + addi.n a10,a10,1 # [4] + add.n a11,a11,a4 # [5] + s32i a11,a1,176 # [6] gra_spill_temp_215 + s32i a10,a1,180 # [7] gra_spill_temp_216 + sub a10,a7,a10 # [8] + beqz a10,.Lt_9_11522 # [9] + +.Lt_9_12034: # 0x17bc + blt a6,a5,.LBB18_esp_nn_depthwise_conv_s16_mult8 # [0] + + j .Lt_9_12290 # [0] + +.Lt_9_8450: # 0x17c2 + retw.n # [0] + + .size esp_nn_depthwise_conv_s16_mult8_esp32s3, . - esp_nn_depthwise_conv_s16_mult8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s8_esp32s3.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s8_esp32s3.c new file mode 100644 index 0000000..abb11d3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s8_esp32s3.c @@ -0,0 +1,547 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +#include + +static int16_t *scratch_buffer = NULL; + +extern void esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3(const int16_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t ch_mult, + const int16_t *filter_data, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max); + +extern void esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3(const int8_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const int32_t input_offset, + const uint16_t stride_wd, + const uint16_t stride_ht, + const int8_t *filter_data, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max); + +extern void esp_nn_depthwise_conv_s16_mult1_3x3_no_pad_esp32s3(const int16_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const uint16_t stride_wd, + const uint16_t stride_ht, + const int16_t *filter_data, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max); + +extern void esp_nn_depthwise_conv_s16_mult8_esp32s3(const int16_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t ch_mult, + const int16_t *filter_data, + const uint16_t filter_wd, + const uint16_t filter_ht, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max); + +extern void esp_nn_depthwise_conv_s16_mult4_esp32s3(const int16_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t ch_mult, + const int16_t *filter_data, + const uint16_t filter_wd, + const uint16_t filter_ht, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max); + +extern void esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3(const int16_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const int16_t *filter_data, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max); + +extern void esp_nn_depthwise_conv_s16_mult1_esp32s3(const int16_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const int16_t *filter_data, + const uint16_t filter_wd, + const uint16_t filter_ht, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max); + +extern void esp_nn_s8_to_s16_esp32s3(const int8_t *src, int16_t *dst, const int size); + +extern void esp_nn_aligned_s8_to_s16_with_offset_esp32s3(const int8_t *src, int16_t *dst, + const int size, const int32_t offset); + +static void esp_nn_depthwise_conv_s8_unrolled(const int8_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const int32_t input_offset, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t ch_mult, + const int8_t *filter_data, + const uint16_t filter_wd, + const uint16_t filter_ht, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max) +{ + int out_idx = 0; + for (int out_y = 0; out_y < out_ht; out_y++) { //height loop + const int16_t base_y = (out_y * stride_ht) - pad_ht; + for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + const int16_t base_x = (out_x * stride_wd) - pad_wd; + for (int ch_idx = 0; ch_idx < channels; ch_idx++) {//channel_loop + int ch_mult_idx = 0; + for (; ch_mult_idx < ch_mult - 3; ch_mult_idx += 4) { + int32_t result0 = 0, result1 = 0, result2 = 0, result3 = 0; + const int out_ch_idx = ch_mult_idx + ch_idx * ch_mult; + + /* Select filter so as the point doesn't lie outside block */ + int filter_y_start = max(0, -base_y); + int filter_x_start = max(0, -base_x); + int filter_y_end = min(filter_ht, input_ht - base_y); + int filter_x_end = min(filter_wd, input_wd - base_x); + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * (channels * ch_mult) + out_ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val0 = filter_data[filter_index + 0]; + int32_t filter_val1 = filter_data[filter_index + 1]; + int32_t filter_val2 = filter_data[filter_index + 2]; + int32_t filter_val3 = filter_data[filter_index + 3]; + result0 += input_val * filter_val0; + result1 += input_val * filter_val1; + result2 += input_val * filter_val2; + result3 += input_val * filter_val3; + } + } + if (bias) { + result0 += bias[out_ch_idx + 0]; + result1 += bias[out_ch_idx + 1]; + result2 += bias[out_ch_idx + 2]; + result3 += bias[out_ch_idx + 3]; + } + result0 = esp_nn_multiply_by_quantized_mult(result0, + out_mult[out_ch_idx + 0], out_shift[out_ch_idx + 0]); + result1 = esp_nn_multiply_by_quantized_mult(result1, + out_mult[out_ch_idx + 1], out_shift[out_ch_idx + 1]); + result2 = esp_nn_multiply_by_quantized_mult(result2, + out_mult[out_ch_idx + 2], out_shift[out_ch_idx + 2]); + result3 = esp_nn_multiply_by_quantized_mult(result3, + out_mult[out_ch_idx + 3], out_shift[out_ch_idx + 3]); + + result0 += out_offset; + result1 += out_offset; + result2 += out_offset; + result3 += out_offset; + + result0 = max(result0, activation_min); + result1 = max(result1, activation_min); + result2 = max(result2, activation_min); + result3 = max(result3, activation_min); + + result0 = min(result0, activation_max); + result1 = min(result1, activation_max); + result2 = min(result2, activation_max); + result3 = min(result3, activation_max); + + out_data[out_idx++] = result0; + out_data[out_idx++] = result1; + out_data[out_idx++] = result2; + out_data[out_idx++] = result3; + } + + /* left-over */ + for (; ch_mult_idx < ch_mult; ch_mult_idx++) { + int32_t result = 0; + const int out_ch_idx = ch_mult_idx + ch_idx * ch_mult; + + /* Select filter so as the point doesn't lie outside block */ + int filter_y_start = max(0, -base_y); + int filter_x_start = max(0, -base_x); + int filter_y_end = min(filter_ht, input_ht - base_y); + int filter_x_end = min(filter_wd, input_wd - base_x); + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * (channels * ch_mult) + out_ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val = filter_data[filter_index]; + result += input_val * filter_val; + } + } + if (bias) { + result += bias[out_ch_idx]; + } + result = esp_nn_multiply_by_quantized_mult(result, out_mult[out_ch_idx], out_shift[out_ch_idx]); + result += out_offset; + result = max(result, activation_min); + result = min(result, activation_max); + + out_data[out_idx++] = result; + } + } + } + } +} + +void esp_nn_depthwise_conv_s8_ch_mult1(const int8_t *input_data, + const uint16_t input_wd, + const uint16_t input_ht, + const uint16_t channels, + const int32_t input_offset, + const uint16_t pad_wd, + const uint16_t pad_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const int8_t *filter_data, + const uint16_t filter_wd, + const uint16_t filter_ht, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_wd, + const uint16_t out_ht, + const int32_t out_offset, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t activation_min, + const int32_t activation_max) +{ + int out_idx = 0; + for (int out_y = 0; out_y < out_ht; out_y++) { //height loop + const int16_t base_y = (out_y * stride_ht) - pad_ht; + for (int out_x = 0; out_x < out_wd; out_x++) { //width_loop + const int16_t base_x = (out_x * stride_wd) - pad_wd; + for (int ch_idx = 0; ch_idx < channels; ch_idx++) {//channel_loop + int32_t result = 0; + /* Select filter so as the point doesn't lie outside block */ + int filter_y_start = max(0, -base_y); + int filter_x_start = max(0, -base_x); + int filter_y_end = min(filter_ht, input_ht - base_y); + int filter_x_end = min(filter_wd, input_wd - base_x); + + for (int filter_y_idx = filter_y_start; filter_y_idx < filter_y_end; filter_y_idx++) { + const int32_t idx_y = base_y + filter_y_idx; + for (int filter_x_idx = filter_x_start; filter_x_idx < filter_x_end; filter_x_idx++) { + const int32_t idx_x = base_x + filter_x_idx; + int32_t input_index = (idx_y * input_wd + idx_x) * channels + ch_idx; + int32_t filter_index = (filter_y_idx * filter_wd + filter_x_idx) * channels + ch_idx; + int32_t input_val = input_data[input_index] + input_offset; + int32_t filter_val = filter_data[filter_index]; + result += input_val * filter_val; + } + } + if (bias) { + result += bias[ch_idx]; + } + result = esp_nn_multiply_by_quantized_mult(result, out_mult[ch_idx], out_shift[ch_idx]); + result += out_offset; + result = max(result, activation_min); + result = min(result, activation_max); + + out_data[out_idx++] = result; + } + } + } +} + +int esp_nn_get_depthwise_conv_scratch_size_esp32s3(const data_dims_t *input_dims, + const data_dims_t *filter_dims, + const data_dims_t *output_dims, + const dw_conv_params_t *conv_params) +{ + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t channels = input_dims->channels; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t ch_mult = conv_params->ch_mult; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + + int filter_size = filter_wd * filter_ht * channels * ch_mult; + int pad_width = 0, pad_height = 0; + + if ((ch_mult == 1) && (channels % 8 == 0) && (filter_wd == 3) && (filter_ht == 3)) { + if (channels % 16 == 0) { + if (pad_wd || pad_ht) { + pad_width = pad_wd * 2; + pad_height = pad_ht * 2; + } else { + // check if we need to pad additionally + pad_width = (out_wd * stride_wd + filter_wd - 1) - input_wd; + pad_height = (out_ht * stride_ht + filter_ht - 1) - input_ht; + // printf("in(%d %d %d), out(%d %d), filter (%d %d) stride (%d %d), pad (%d %d)", + // input_wd, input_ht, channels, out_wd, out_ht, filter_wd, filter_ht, + // stride_wd, stride_ht, pad_wd, pad_ht); + } + if (pad_width || pad_height) { + int input_size = (input_wd + pad_width) * (input_ht + pad_height) * channels; + // printf("ask1 %d\n", filter_size + input_size + 16); + return filter_size + input_size + 16; // 16 for alignment + } else { + // printf("ask2 %d\n", filter_size + 16); + return filter_size + 16; // 16 for alignment + } + } else { + int input_size = input_wd * input_ht * channels; + // printf("ask3 %d\n", 2 * (filter_size + input_size) + 16); + return 2 * (filter_size + input_size) + 16; // 16 for alignment + } + } else if (ch_mult % 4 == 0) { + int input_size = input_wd * input_ht * channels; + // printf("ask4 %d\n", 2 * (filter_size + input_size) + 16); + return 2 * (filter_size + input_size) + 16; // 16 for alignment + } + return 32; // just few bytes +} + +void esp_nn_set_depthwise_conv_scratch_buf_esp32s3(void *buf) +{ + scratch_buffer = (int16_t *) buf; +} + +/** + * Assumption 1: i/p channels == o/p channels + * Assumption 2: Pointers are valid + * Assumption 3: dialation width = 1 + */ + + + +void esp_nn_depthwise_conv_s8_esp32s3(const data_dims_t *input_dims, + const int8_t *input_data, + const data_dims_t *filter_dims, + const int8_t *filter_data, + const int32_t *bias, + const data_dims_t *output_dims, + int8_t *out_data, + const dw_conv_params_t *conv_params, + const quant_data_t *quant_data) +{ + const uint16_t input_wd = input_dims->width; + const uint16_t input_ht = input_dims->height; + const uint16_t channels = input_dims->channels; + const int32_t input_offset = conv_params->in_offset; + const int32_t out_offset = conv_params->out_offset; + const uint16_t pad_wd = conv_params->padding.width; + const uint16_t pad_ht = conv_params->padding.height; + const uint16_t stride_wd = conv_params->stride.width; + const uint16_t stride_ht = conv_params->stride.height; + const uint16_t filter_wd = filter_dims->width; + const uint16_t filter_ht = filter_dims->height; + const uint16_t out_wd = output_dims->width; + const uint16_t out_ht = output_dims->height; + const int32_t *out_shift = quant_data->shift; + const int32_t *out_mult = quant_data->mult; + const int32_t activation_min = conv_params->activation.min; + const int32_t activation_max = conv_params->activation.max; + const uint16_t ch_mult = conv_params->ch_mult; + + int filter_size = filter_wd * filter_ht * channels * ch_mult; + int align_len = 16 - (filter_size & 15); + int input_size = input_wd * input_ht * channels; + int16_t *filter_data16 = scratch_buffer; + int16_t *input_data16 = scratch_buffer + filter_size + align_len; + if (scratch_buffer == NULL) { + printf("esp_nn_depthwise_conv error! scratch_buffer not set!\n"); + return; + } + + if ((ch_mult == 1) && (channels % 8 == 0)) { + if ((filter_wd == 3) && (filter_ht == 3)) { + if ((channels % 16 == 0) && (pad_wd == 1) && (pad_ht == 1)) { + /* process in 8 bits */ + int8_t *filter_aligned = (int8_t *) scratch_buffer; + int8_t *input_padded = (int8_t *) scratch_buffer + filter_size + align_len; + memcpy(filter_aligned, filter_data, filter_size); + esp_nn_aligned_s8_pad_with_value(input_data, input_padded, input_wd, input_ht, channels, + -input_offset, pad_wd, pad_ht); + esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3(input_padded, input_wd + 2 * pad_wd, + input_ht + 2 * pad_ht, channels, input_offset, + stride_wd, stride_ht, filter_aligned, bias, + out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } else if ((channels % 16 == 0) && (pad_wd == 0) && (pad_ht == 0)) { + /* process in 8 bits */ + int8_t *filter_aligned = (int8_t *) scratch_buffer; + int8_t *input_padded = (int8_t *) scratch_buffer + filter_size + align_len; + + // check if we need to pad additionally + int pad_right = (out_wd * stride_wd + filter_wd - 1) - input_wd; + int pad_bottom = (out_ht * stride_ht + filter_ht - 1) - input_ht; + if (pad_right || pad_bottom) { // pad right and bottom + esp_nn_aligned_s8_pad_end_with_value(input_data, input_padded, input_wd, input_ht, + channels, -input_offset, pad_right, pad_bottom); + } else { + input_padded = (int8_t *) input_data; + } + memcpy(filter_aligned, filter_data, filter_size); + esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3(input_padded, input_wd + pad_right, + input_ht + pad_bottom, channels, input_offset, + stride_wd, stride_ht, filter_aligned, bias, + out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } else { /* (channels % 8) == 0 */ + esp_nn_s8_to_s16_esp32s3(filter_data, filter_data16, filter_size); + esp_nn_aligned_s8_to_s16_with_offset_esp32s3(input_data, input_data16, input_size, input_offset); + esp_nn_depthwise_conv_s16_mult1_3x3_esp32s3(input_data16, input_wd, input_ht, channels, + pad_wd, pad_ht, stride_wd, stride_ht, filter_data16, + bias, out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } + } else { // all other ch_mult == 1, `channels % 8 == 0` + esp_nn_depthwise_conv_s8_ch_mult1(input_data, input_wd, input_ht, channels, input_offset, + pad_wd, pad_ht, stride_wd, stride_ht, + filter_data, filter_wd, filter_ht, + bias, out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } + } else if (ch_mult % 8 == 0) { + esp_nn_s8_to_s16_esp32s3(filter_data, filter_data16, filter_size); + esp_nn_aligned_s8_to_s16_with_offset_esp32s3(input_data, input_data16, input_size, input_offset); + if (filter_wd == 3 && filter_ht == 3) { + esp_nn_depthwise_conv_s16_mult8_3x3_esp32s3(input_data16, input_wd, input_ht, channels, + pad_wd, pad_ht, stride_wd, stride_ht, ch_mult, + filter_data16, bias, + out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } else { + esp_nn_depthwise_conv_s16_mult8_esp32s3(input_data16, input_wd, input_ht, channels, + pad_wd, pad_ht, stride_wd, stride_ht, ch_mult, + filter_data16, filter_wd, filter_ht, bias, + out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } + } else if (ch_mult % 4 == 0) { + esp_nn_s8_to_s16_esp32s3(filter_data, filter_data16, filter_size); + esp_nn_aligned_s8_to_s16_with_offset_esp32s3(input_data, input_data16, input_size, input_offset); + esp_nn_depthwise_conv_s16_mult4_esp32s3(input_data16, input_wd, input_ht, channels, + pad_wd, pad_ht, stride_wd, stride_ht, ch_mult, + filter_data16, filter_wd, filter_ht, bias, + out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } else { + esp_nn_depthwise_conv_s8_unrolled(input_data, input_wd, input_ht, channels, input_offset, + pad_wd, pad_ht, stride_wd, stride_ht, ch_mult, + filter_data, filter_wd, filter_ht, + bias, out_data, out_wd, out_ht, out_offset, out_shift, + out_mult, activation_min, activation_max); + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3.S new file mode 100644 index 0000000..c9240d4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/convolution/esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3.S @@ -0,0 +1,512 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .literal_position + +// processes multiple of 16 channels +// already padded version. no additional padding needed +// simply keep sliding filter window by stride_size + + # Program Unit: esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3 + .type esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3, @function + .align 4 + .global esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3 + +esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3: # 0xccc + # qacc_scratch = 0 + # gra_spill_temp_103 = 40 // stride_wd*channels + # gra_spill_temp_104 = 44 // bias_align + # gra_spill_temp_107 = 48 // input_offset + # gra_spill_temp_105 = 52 // out_mult_ptr + # gra_spill_temp_106 = 56 // out_shift_ptr + # gra_spill_temp_108 = 60 // ch_idx + # gra_spill_temp_109 = 64 // out_ch + # gra_spill_temp_110 = 68 // bias_ptr + # gra_spill_temp_111 = 72 // 2 * (input_wd * channels) + # gra_spill_temp_112 = 76 // input_data + # gra_spill_temp_118 = 96 + # gra_spill_temp_119 = 100 + # gra_spill_temp_120 = 104 + # gra_spill_temp_121 = 108 + # gra_spill_temp_113 = 112 // input_wd * channels + # gra_spill_temp_114 = 116 // input_wd + # gra_spill_temp_130 = 120 + + # gra_spill_temp_141 = 0 + # gra_spill_temp_120 = 16 + # gra_spill_temp_137 = 80 + +// offset+bias factor + # gra_spill_temp_134 = 128 //256-128 + # gra_spill_temp_135 = 144 //256-112 + # gra_spill_temp_133 = 160 //256-96 + # gra_spill_temp_132 = 176 //256-80 + + + // registers: + // a2: input_data + // a3: input_wd + // a4: input_ht + // a5: channels + // a6: input_offset + // a7: stride_wd + + // on stack: + + // 320: stride_ht + // 324: filter_data + // 328: *bias + // 332: *out_data + // 336: out_wd + // 340: out_ht + // 344: out_offset + // 348: *out_shift + // 352: *out_mult + // 356: activation_min + // 360: activation_max + + entry a1,320 # + mul16u a7,a7,a5 + s32i a3,a1,116 # [0] gra_spill_temp_114, input_wd + s32i a6,a1,48 # [1] gra_spill_temp_107, input_offset + s32i a7,a1,40 # gra_spill_temp_103, stride_wd*channels + + addi a8,a5,-15 # [2] + s32i a2,a1,76 # [3] gra_spill_temp_112, input_data + l32i a9,a1,328 # [4] id:664 bias+0x0 + mov.n a2,a5 # [5] + s32i a8,a1,64 # [7] gra_spill_temp_109 + s32i a9,a1,68 # [8] gra_spill_temp_110, bias_ptr + blti a8,1,.Lt_7_4610 # [9] + + l32i a12,a1,348 # [4] id:666 out_shift+0x0 + mul16u a15,a3,a5 # [1] + movi.n a9,0 # [13] + s32i a12,a1,56 # [9] gra_spill_temp_106 // out_shift_ptr + s32i a9,a1,60 # [14] gra_spill_temp_108, ch_idx + s32i a15,a1,112 # [12] gra_spill_temp_113, input_wd*channels + l32i a9,a1,352 # [24] id:665 out_mult+0x0 + slli a15,a15,1 # [15] + s32i a15,a1,72 # [23] gra_spill_temp_111, 2 * (input_wd * channels) + s32i a9,a1,52 # [25] gra_spill_temp_105, out_mult_ptr + +// outer most out_ch loop +.Lt_7_5122: # 0xd57 + l32i a13,a1,324 # [1] filter_data + l32i a6,a1,60 # [2] gra_spill_temp_108, ch_idx + l32i a9,a1,48 # [0] gra_spill_temp_107, input_offset + ee.zero.q q2 # [3] + add.n a13,a6,a13 # [4] + s32i a13,a1,108 # [5] gra_spill_temp_121 + +// multiply accumulate filter points + ee.vld.128.xp q1,a13,a2 # [6] id:673 + ee.vld.128.xp q3,a13,a2 # [7] id:674 + ee.vcmp.lt.s8 q0,q1,q2 # [8] + ee.vcmp.lt.s8 q4,q3,q2 # [9] + ee.vzip.8 q1,q0 # [10] + ee.vzip.8 q3,q4 # [11] + ee.vadds.s16 q0,q0,q4 # [12] + ee.vld.128.xp q4,a13,a2 # [13] id:675 + ee.vadds.s16 q1,q1,q3 # [14] + ee.vcmp.lt.s8 q3,q4,q2 # [15] + ee.vzip.8 q4,q3 # [16] + ee.vadds.s16 q1,q1,q4 # [17] + ee.vld.128.xp q4,a13,a2 # [18] id:676 + ee.vadds.s16 q0,q0,q3 # [19] + ee.vcmp.lt.s8 q3,q4,q2 # [20] + ee.vzip.8 q4,q3 # [21] + ee.vadds.s16 q0,q0,q3 # [22] + ee.vld.128.xp q3,a13,a2 # [23] id:677 + ee.vadds.s16 q1,q1,q4 # [24] + ee.vcmp.lt.s8 q4,q3,q2 # [25] + ee.vzip.8 q3,q4 # [26] + ee.vadds.s16 q1,q1,q3 # [27] + ee.vld.128.xp q3,a13,a2 # [28] id:678 + ee.vadds.s16 q0,q0,q4 # [29] + ee.vcmp.lt.s8 q4,q3,q2 # [30] + ee.vzip.8 q3,q4 # [31] + ee.vadds.s16 q0,q0,q4 # [32] + ee.vld.128.xp q4,a13,a2 # [33] id:679 + ee.vadds.s16 q1,q1,q3 # [34] + ee.vcmp.lt.s8 q3,q4,q2 # [35] + ee.vzip.8 q4,q3 # [36] + ee.vadds.s16 q1,q1,q4 # [37] + ee.vld.128.xp q4,a13,a2 # [38] id:680 + ee.vadds.s16 q0,q0,q3 # [39] + ee.vcmp.lt.s8 q3,q4,q2 # [40] + ee.vzip.8 q4,q3 # [41] + ee.vadds.s16 q0,q0,q3 # [42] + ee.vld.128.xp q3,a13,a2 # [44] id:681 + ee.vadds.s16 q1,q1,q4 # [43] + ee.vcmp.lt.s8 q2,q3,q2 # [47] + ee.vzip.8 q3,q2 # [48] + ee.vadds.s16 q0,q0,q2 # [49] + ee.vadds.s16 q1,q1,q3 # [50] + + ee.movi.32.a q1,a15,1 # [51] + ee.movi.32.a q1,a8,3 # [52] + ee.movi.32.a q0,a10,3 # [54] + ee.movi.32.a q0,a13,1 # [55] + srai a11,a10,16 # [56] + srai a12,a8,16 # [57] + mull a12,a9,a12 # [58] + mull a11,a9,a11 # [59] + sext a8,a8,15 # [328] + sext a10,a10,15 # [61] + srai a14,a13,16 # [62] + mull a14,a9,a14 # [63] + mull a10,a9,a10 # [64] + mull a8,a9,a8 # [65] + sext a13,a13,15 # [66] + mull a13,a9,a13 # [67] + ee.movi.32.q q3,a11,3 # [68] + ee.movi.32.q q4,a12,3 # [69] + ee.movi.32.q q4,a8,2 # [70] + ee.movi.32.q q3,a10,2 # [71] + ee.movi.32.a q1,a11,2 # [72] + srai a12,a11,16 # [74] + srai a8,a15,16 # [75] + mull a8,a9,a8 # [76] + mull a12,a9,a12 # [77] + sext a15,a15,15 # [78] + sext a11,a11,15 # [79] + mull a11,a9,a11 # [80] + mull a15,a9,a15 # [81] + ee.movi.32.q q4,a12,1 # [82] + ee.movi.32.q q1,a8,3 # [83] + ee.movi.32.q q1,a15,2 # [84] + ee.movi.32.q q4,a11,0 # [85] + ee.movi.32.a q0,a15,2 # [86] + ee.movi.32.q q0,a14,3 # [88] + ee.movi.32.q q0,a13,2 # [91] + srai a8,a15,16 # [89] + mull a8,a9,a8 # [90] + sext a15,a15,15 # [92] + mull a15,a9,a15 # [93] + # 526 MUL_IN_OFFSET_EXPAND(q_sum2, 0, q_sum2, 0); + ee.movi.32.a q0,a11,0 # [94] + srai a13,a11,16 # [95] + ee.movi.32.q q3,a8,1 # [96] + ee.movi.32.q q3,a15,0 # [100] + sext a11,a11,15 # [97] + mull a13,a9,a13 # [98] + l32i a8,a1,332 # [99] + ee.movi.32.a q1,a10,0 # [103] + ee.movi.32.q q0,a13,1 # [100] + srai a12,a10,16 # [105] + sext a10,a10,15 # [106] + mull a12,a9,a12 # [107] + mull a10,a9,a10 # [108] + mull a9,a9,a11 # [109] + ee.movi.32.q q1,a12,1 # [110] + ee.movi.32.q q1,a10,0 # [111] + + l32i a11,a1,328 // load bias + add.n a6,a6,a8 # [102] + ee.movi.32.q q0,a9,0 # [113] + beqz.n a11,.Lt_7_5378 # [114] + +// add bias + l32i a8,a1,68 # [0] gra_spill_temp_110, bias_ptr + extui a11,a11,0,4 # [2] // bias_align + wur.sar_byte a11 # [4] + ee.vld.128.ip q5,a8,16 # [5] id:683 + ee.vld.128.ip q6,a8,16 # [6] id:684 + ee.vld.128.ip q7,a8,16 # [7] id:685 + addmi a10,a1,256 # [2] + ee.src.q.ld.ip q2,a8,16,q5,q6 # [9] + ee.vadds.s32 q1,q1,q5 # [12] + ee.src.q.ld.ip q5,a8,0,q6,q7 # [13] + s32i a8,a1,68 # [11] gra_spill_temp_110, bias_ptr + ee.vadds.s32 q4,q4,q6 # [18] + ee.src.q q7,q7,q2 # [9] + ee.src.q q2,q2,q5 # [13] + ee.vadds.s32 q0,q0,q7 # [12] + ee.vadds.s32 q3,q3,q2 # [12] +.Lt_7_5378: # 0xeef + +// store offset+bias factor (q1,q4,q0,q3) + st.qr q4,a10,-112 # [17] gra_spill_temp_135-256 + st.qr q3,a10,-128 # [21] gra_spill_temp_134-256 + st.qr q1,a10,-96 # [7] gra_spill_temp_133-256 + st.qr q0,a10,-80 # [8] gra_spill_temp_132-256 + +// prepare height loop + movi.n a15,0 # [1] + movi.n a8,0 # [2] + movi.n a9,0 # [3] + s32i a9,a1,100 # [4] gra_spill_temp_119 + s32i a8,a1,104 # [5] gra_spill_temp_120 + s32i a15,a1,96 # [6] gra_spill_temp_118 + +// height loop +.Lt_7_6402: # 0xf0c + l32i a4,a1,104 # [2] gra_spill_temp_120 // out_y * (input_wd * stride_ht) * channels) + l32i a8,a1,100 # [3] gra_spill_temp_119 // initialised to 0 before height loop + l32i a5,a1,76 # [1] gra_spill_temp_112, input_data + l32i a3,a1,60 # [0] gra_spill_temp_108, ch_idx + l32i a7,a1,112 # [1] gra_spill_temp_113, input_wd*channels + l32i a10,a1,336 # [0] out_wd + add.n a4,a4,a5 # [4] // input_data + (out_y * stride_ht) * input_wd * channels + mov.n a5,a8 # [5] // index + add.n a3,a3,a4 # [6] // input_row0 + l32i a4,a1,72 # [9] gra_spill_temp_111, 2 * (input_wd * channels) + add.n a7,a7,a3 # [7] // input_row1 = (input_wd * channels) + add.n a8,a8,a10 # [8] + s32i a8,a1,120 # [10] gra_spill_temp_130 + add.n a4,a4,a3 # [11] // input_row2 + +// width loop +.Lt_7_7170: # 0xf32 + l32i a9,a1,108 # [3] gra_spill_temp_121, filter_ptr + ee.zero.qacc # [2] + mov.n a12,a3 # [4] + mov.n a11,a7 # [1] + mov.n a10,a4 # [0] + ee.vld.128.xp q0,a12,a2 # [5] id:693 + ee.vld.128.xp q6,a12,a2 # [6] id:695 + ee.vld.128.xp q1,a9,a2 # [7] id:694 + ee.vld.128.xp q7,a9,a2 # [8] id:696 + ee.vld.128.xp q5,a9,a2 # [9] id:698 + ee.vld.128.xp q3,a9,a2 # [10] id:700 + ee.vmulas.s8.qacc.ld.xp q4,a12,a2,q0,q1 # [11] id:697 + ee.vmulas.s8.qacc.ld.xp q2,a11,a2,q6,q7 # [13] id:699 + ee.vld.128.xp q1,a9,a2 # [14] id:702 + ee.vmulas.s8.qacc.ld.xp q0,a11,a2,q4,q5 # [15] id:701 + ee.vmulas.s8.qacc.ld.xp q6,a11,a2,q2,q3 # [16] id:703 + ee.vld.128.xp q7,a9,a2 # [17] id:704 + ee.vld.128.xp q3,a9,a2 # [18] id:706 + ee.vmulas.s8.qacc.ld.xp q0,a10,a2,q0,q1 # [19] id:705 + ee.vmulas.s8.qacc.ld.xp q1,a10,a2,q6,q7 # [20] id:707 + ee.vmulas.s8.qacc.ld.xp q4,a10,a2,q0,q3 # [21] id:709 + ee.vld.128.xp q6,a9,a2 # [22] id:708 + ee.vld.128.xp q5,a9,a2 # [23] id:710 + ee.vmulas.s8.qacc q1,q6 # [24] + ee.vmulas.s8.qacc q4,q5 # [25] + + // extract data + mov a12,a1 //// scratch + ee.st.qacc_l.l.128.ip a12,16 # [27] id:713 + ee.st.qacc_l.h.32.ip a12,-16 # [28] id:714 + + l32i.n a9,a1,8 # [29] qacc_scratch+8 + l32i.n a11,a1,4 # [30] qacc_scratch+4 + l32i.n a15,a1,0 # [31] qacc_scratch + slli a14,a11,24 # [32] + sext a8,a15,19 # [33] + slli a10,a9,16 # [34] + slli a13,a11,4 # [35] + extui a9,a9,16,16 # [36] + srai a13,a13,12 # [37] + extui a15,a15,20,12 # [39] + srai a14,a14,12 # [40] + srai a10,a10,12 # [41] + extui a11,a11,28,4 # [42] + or a10,a10,a11 # [43] + or a14,a14,a15 # [44] + +// insert to q0 + ee.movi.32.q q0,a8,0 # [38] + ee.movi.32.q q0,a14,1 # [45] + ee.movi.32.q q0,a13,2 # [48] + ee.movi.32.q q0,a10,3 # [49] + + l32i.n a11,a1,16 # [46] qacc_scratch+16 + l32i.n a14,a1,12 # [47] qacc_scratch+12 + slli a13,a11,20 # [50] + + ee.st.qacc_h.l.128.ip a12,16 # [51] id:720 + ee.st.qacc_h.h.32.ip a12,-16 # [55] id:721 + srai a11,a11,12 # [52] + srai a13,a13,12 # [53] + slli a8,a14,28 # [54] + slli a15,a14,8 # [56] + srai a15,a15,12 # [57] + srai a8,a8,12 # [59] + + l32i.n a12,a1,8 # [328] qacc_scratch+8 + or a8,a8,a9 # [61] + extui a14,a14,24,8 # [62] + l32i.n a9,a1,0 # [63] qacc_scratch + or a13,a13,a14 # [64] +//insert to q3 + ee.movi.32.q q3,a8,0 # [65] + ee.movi.32.q q3,a15,1 # [67] + ee.movi.32.q q3,a13,2 # [69] + ee.movi.32.q q3,a11,3 # [70] + + l32i.n a14,a1,4 # [66] qacc_scratch+4 + sext a10,a9,19 # [68] + extui a9,a9,20,12 # [72] + slli a13,a12,16 # [73] + slli a8,a14,24 # [74] + extui a12,a12,16,16 # [75] + srai a13,a13,12 # [76] + srai a8,a8,12 # [77] + slli a15,a14,4 # [78] + srai a15,a15,12 # [79] + or a8,a8,a9 # [80] + extui a14,a14,28,4 # [81] + l32i.n a9,a1,12 # [82] qacc_scratch+12 + or a13,a13,a14 # [83] +// insert to q1 + ee.movi.32.q q1,a10,0 # [71] + ee.movi.32.q q1,a8,1 # [84] + ee.movi.32.q q1,a15,2 # [85] + ee.movi.32.q q1,a13,3 # [88] + +// load in_offset+bias factor + addmi a14,a1,256 # [86] + ld.qr q7,a14,-128 # [87] gra_spill_temp_134-256 + ld.qr q4,a14,-112 # [89] gra_spill_temp_135-256 + l32i.n a15,a1,16 # [90] qacc_scratch+16 + ld.qr q2,a14,-96 # [91] gra_spill_temp_133-256 + slli a11,a9,28 # [92] + slli a10,a9,8 # [93] + srai a10,a10,12 # [94] + srai a11,a11,12 # [95] + extui a9,a9,24,8 # [96] + or a11,a11,a12 # [97] + ee.vadds.s32 q0,q0,q2 # [98] + slli a8,a15,20 # [99] + ee.vadds.s32 q3,q3,q4 # [100] + st.qr q3,a1,80 # [101] gra_spill_temp_137-256 + srai a15,a15,12 # [102] + ld.qr q2,a14,-80 # [103] gra_spill_temp_132-256 + srai a8,a8,12 # [105] + or a8,a8,a9 # [108] + +// insert to q6 + ee.movi.32.q q6,a11,0 # [100] + ee.movi.32.q q6,a10,1 # [107] + ee.movi.32.q q6,a8,2 # [112] + ee.movi.32.q q6,a15,3 # [113] + + ee.vadds.s32 q1,q1,q2 # [110] + ee.vadds.s32 q6,q6,q7 # [114] + st.qr q1,a1,16 # [111] gra_spill_temp_120 + s32i.n a7,a1,32 # [0] // tmp + s32i.n a6,a1,36 # [106] // tmp + l32i a7,a1,52 # [109] gra_spill_temp_105, out_mult_ptr + l32i a6,a1,56 # [106] gra_spill_temp_106, out_shift_ptr + addi.n a10,a7,0 + addi.n a11,a6,0 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [116] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + mv.qr q5,q0 + ld.qr q0,a1,80 # [4] gra_spill_temp_137-256 + addi.n a10,a7,16 + addi.n a11,a6,16 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [5] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + mv.qr q4,q0 + ld.qr q0,a1,16 # [5] gra_spill_temp_120 + addi.n a10,a7,32 + addi.n a11,a6,32 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [6] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + st.qr q0,a1,0 # [3] gra_spill_temp_141 + mv.qr q0,q6 + addi.n a10,a7,48 + addi.n a11,a6,48 + call8 esp_nn_multiply_by_quantized_mult_ver1_esp32s3 # [6] esp_nn_multiply_by_quantized_mult_ver1_esp32s3 + + + l32i.n a6,a1,36 # [106] // tmp + l32i.n a7,a1,32 # [0] // tmp + l32i a15,a1,40 # gra_spill_temp_103, stride_wd * channels + l32i a11,a1,120 # [3] gra_spill_temp_130 + + add.n a3,a3,a15 # [0] + add.n a4,a4,a15 # [1] + add.n a7,a7,a15 # [2] + addi.n a5,a5,1 # [4] + + // add offset, apply activation and store + addmi a13,a1,256 # [8] + ld.qr q3,a1,0 # [10] gra_spill_temp_141 + mv.qr q2,q5 + addi a8,a13,88 # [14] + addi a9,a13,100 # [15] + addi a15,a13,104 # [13] + ee.vldbc.32 q6,a9 # [17] id:723 activation_min + ee.vldbc.32 q1,a8 # [18] id:722 out_offset + ee.vldbc.32 q7,a15 # [19] id:724 activation_max + ee.vadds.s32 q4,q4,q1 # [20] + ee.vadds.s32 q2,q2,q1 # [21] + ee.vadds.s32 q5,q0,q1 # [22] + ee.vadds.s32 q3,q3,q1 # [23] + ee.vmin.s32 q3,q3,q7 # [24] + ee.vmin.s32 q5,q5,q7 # [25] + ee.vmin.s32 q2,q2,q7 # [26] + ee.vmin.s32 q4,q4,q7 # [27] + ee.vmax.s32 q4,q4,q6 # [28] + ee.vmax.s32 q2,q2,q6 # [29] + ee.vmax.s32 q5,q5,q6 # [30] + ee.vmax.s32 q3,q3,q6 # [31] + ee.vunzip.16 q3,q5 # [32] + ee.vunzip.16 q2,q4 # [33] + ee.vunzip.8 q2,q3 # [34] + ee.vst.128.xp q2,a6,a2 # [35] id:725 + bne a5,a11,.Lt_7_7170 # [36] + +.Lt_7_6658: # 0x112f +# Part of loop body line 548, head labeled .Lt_7_6402 + l32i a15,a1,112 # [3] gra_spill_temp_113, input_wd*channels + l32i a10,a1,320 # gra_spill_temp_103 + l32i a13,a1,340 # [0] // out_ht + l32i a9,a1,116 # [1] gra_spill_temp_114, input_wd + l32i a12,a1,96 # [4] gra_spill_temp_118 + mull a15,a10,a15 # // (input_wd * stride_ht) * channels + l32i a14,a1,104 # [5] gra_spill_temp_120 + l32i a8,a1,100 # [2] gra_spill_temp_119 + + addi.n a12,a12,1 # [6] + s32i a12,a1,96 # [7] gra_spill_temp_118 + add.n a14,a14,a15 # [8] + add.n a8,a8,a9 # [9] + s32i a8,a1,100 # [10] gra_spill_temp_119 + s32i a14,a1,104 # [11] gra_spill_temp_120, (input_wd * stride_wd) * channels + bne a12,a13,.Lt_7_6402 # [13] // iterate over height loop + +# Part of loop body line 348, head labeled .Lt_7_5122 + l32i a11,a1,56 # [6] gra_spill_temp_106 // out_shift_ptr + l32i a15,a1,52 # [2] gra_spill_temp_105, out_mult_ptr + l32i a10,a1,60 # [24] gra_spill_temp_108, ch_idx + addi a11,a11,64 # [8] + addi a15,a15,64 # [13] + s32i a11,a1,56 # [23] gra_spill_temp_106 + s32i a15,a1,52 # [18] gra_spill_temp_105, out_mult_ptr + l32i a11,a1,64 # [25] gra_spill_temp_109 + addi a10,a10,16 # [26] + s32i a10,a1,60 # [27] gra_spill_temp_108, ch_idx + blt a10,a11,.Lt_7_5122 # [28] // iterate over outer most out_ch loop + +.Lt_7_4610: # 0x11ad + retw.n # [0] + + .size esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3, . - esp_nn_depthwise_conv_s8_mult1_3x3_padded_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/fully_connected/esp_nn_fully_connected_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/fully_connected/esp_nn_fully_connected_ansi.c new file mode 100644 index 0000000..788a65b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/fully_connected/esp_nn_fully_connected_ansi.c @@ -0,0 +1,54 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include + +void esp_nn_fully_connected_s8_ansi(const int8_t *input_data, + const int32_t input_offset, + const uint16_t row_len, + const int8_t *filter_data, + const int32_t filter_offset, + const int32_t *bias, + int8_t *out_data, + const uint16_t out_channels, + const int32_t out_offset, + const int32_t out_shift, + const int32_t out_mult, + const int32_t activation_min, + const int32_t activation_max) +{ + for (int32_t out_c = 0; out_c < out_channels; ++out_c) { + int32_t result = 0; + for (int32_t data_idx = 0; data_idx < row_len; data_idx++) { + int32_t filter_index = row_len * out_c + data_idx; + int32_t input_val = input_data[data_idx]; + int32_t filter_val = filter_data[filter_index]; + result += (filter_val + filter_offset) * (input_val + input_offset); + } + if (bias) { + result += bias[out_c]; + } + result = esp_nn_multiply_by_quantized_mult(result, out_mult, out_shift); + result += out_offset; + result = max(result, activation_min); + result = min(result, activation_max); + out_data[out_c] = (int8_t) result; + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/fully_connected/esp_nn_fully_connected_s8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/fully_connected/esp_nn_fully_connected_s8_esp32s3.S new file mode 100644 index 0000000..9c1a835 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/fully_connected/esp_nn_fully_connected_s8_esp32s3.S @@ -0,0 +1,220 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// +// SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD +// +// SPDX-License-Identifier: Apache-2.0 +// + .text + .align 4 + .literal_position + .literal .LC3_26_101, 1073741824 // nudge (1 << 30) + + # Program Unit: esp_nn_fully_connected_s8_esp32s3 + .type esp_nn_fully_connected_s8_esp32s3, @function + .align 4 + .global esp_nn_fully_connected_s8_esp32s3 + +// a2: input_data +// a3: input_offset +// a4: row_len +// a5: filter_data +// a6: filter_offset +// a7: bias +// on stack: out_data +// on stack: out_channels +// on stack: out_offset +// on stack: out_shift +// on stack: out_mult +// on stack: activation_min +// on stack: activation_max + +esp_nn_fully_connected_s8_esp32s3: # 0x4 + # qacc_scratch = 0 + // 40, filter_offset + // 44, input_offset + # gra_spill_temp_7 = 48 + # gra_spill_temp_0 = 52 + # gra_spill_temp_1 = 56 + # gra_spill_temp_2 = 60 + # gra_spill_temp_3 = 64 + # gra_spill_temp_4 = 68 + # gra_spill_temp_5 = 72 + # gra_spill_temp_6 = 76 + + entry a1,112 # + s32i.n a5,a1,60 # [0] gra_spill_temp_2, filter_data + s32i a7,a1,48 # [1] gra_spill_temp_7, bias + s32i a6,a1,40 # [2] id:252 filter_offset+0x0 + s32i a3,a1,44 # [3] id:251 input_offset+0x0 + mov.n a13,a2 # [5] + mov.n a12,a4 # [6] + + // out_channel loop + l16ui a2,a1,116 # [7] id:255 out_channels+0x0 + addi a4,a1,40 # [8] + addi a8,a1,44 # [9] + ee.vldbc.16 q5,a8 # [10] id:253 input_offset + ee.vldbc.16 q6,a4 # [12] id:254 filter_offset + beqz.n a2,.Lt_0_7938 # [13] + + ee.zero.q q7 # [0] + srai a11,a12,3 # [2] + l32i a10,a1,128 # [5] id:257 out_mult+0x0 + l32i a8,a1,112 # [6] id:259 out_data+0x0 + addi a9,a12,-7 # [7] + s32i a9,a1,76 # [8] gra_spill_temp_6 + s32i a8,a1,72 # [9] gra_spill_temp_5 + s32i a11,a1,64 # [14] gra_spill_temp_3 + slli a11,a11,3 # [16] + s32i a11,a1,68 # [18] gra_spill_temp_4 + l32i a10,a1,124 # [25] id:256 out_shift+0x0 + movi.n a15,0 # [17] + mov.n a14,a7 # [15] + max a11,a10,a15 # [29] + s32i a11,a1,52 # [30] gra_spill_temp_0 // left_shift + sub a10,a11,a10 # // right_shift + s32i.n a10,a1,56 # [28] gra_spill_temp_1 // right_shift + mov.n a11,a5 # [31] + movi.n a10,0 # [32] + mov.n a2,a11 # [33] + +.Lt_0_8450: # 0x12b + + l32i a9,a1,76 # [2] gra_spill_temp_6 + extui a5,a11,0,3 # [34] + ee.zero.accx + slli a5,a5,1 # [3] + bgei a9,0,.LBB6_esp_nn_fully_connected_s8_esp32s3 # [9] + + mov.n a5,a10 # [6] + movi.n a2,0 # [0] + j .Lt_0_8706 # [1] + +.LBB6_esp_nn_fully_connected_s8_esp32s3: # 0x147 + wur.sar_byte a5 # [5] + ee.vld.l.64.ip q4,a2,8 # [4] id:267 + l32i a4,a1,64 # [0] gra_spill_temp_3 + mov.n a3,a13 # [1] + addx8 a5,a4,a10 # [2] + ee.vcmp.lt.s8 q2,q4,q7 # [7] + ee.vzip.8 q4,q2 # [8] + loopgtz a4,.LBB45_esp_nn_fully_connected_s8_esp32s3 # [3] + + ee.vld.l.64.ip q0,a2,8 # [0*II+0] id:268 + ee.vld.l.64.ip q1,a3,8 # [0*II+1] id:270 + ee.vcmp.lt.s8 q2,q0,q7 # [0*II+2] + ee.vcmp.lt.s8 q3,q1,q7 # [0*II+3] + ee.vzip.8 q0,q2 # [0*II+4] + ee.vzip.8 q1,q3 # [0*II+5] + ee.vadds.s16 q1,q1,q5 # [0*II+6] + ee.src.q.qup q2,q4,q0 # [0*II+7] + ee.vadds.s16 q2,q2,q6 # [0*II+8] + ee.vmulas.s16.accx q1,q2 # [0*II+9] + +.LBB45_esp_nn_fully_connected_s8_esp32s3: # 0x170 + l32i a2,a1,68 # [0] gra_spill_temp_4 + +.Lt_0_8706: # 0x173 + movi a9, 0 + ee.srs.accx a6, a9, 0 + + bge a2,a12,.Lt_0_9730 # [38] + +// prepare remaining loop + l32i a8,a1,44 # [0] id:251 input_offset+0x0 + l32i a7,a1,40 # [1] id:252 filter_offset+0x0 + sub a3,a12,a2 # [2] + l32i.n a4,a1,60 # [3] gra_spill_temp_2 + add.n a2,a2,a13 # [4] + add.n a4,a4,a5 # [5] + loopgtz a3,.LBB60_esp_nn_fully_connected_s8_esp32s3 # [6] + +// remaining c loop + l8ui a3,a2,0 # [0*II+0] id:299 + l8ui a5,a4,0 # [0*II+1] id:300 + sext a3,a3,7 # [0*II+2] + sext a5,a5,7 # [0*II+3] + add.n a5,a5,a7 # [0*II+5] + add.n a3,a3,a8 # [0*II+6] + mull a3,a3,a5 # [0*II+7] + addi.n a2,a2,1 # [0*II+8] + addi.n a4,a4,1 # [0*II+4] + add.n a6,a6,a3 # [0*II+9] + +.LBB60_esp_nn_fully_connected_s8_esp32s3: # 0x20f + +// add bias +.Lt_0_9730: # 0x20f + l32i a8,a1,48 # [0] gra_spill_temp_7, bias + beqz.n a8,.Lt_0_10754 # [2], skip_bias + + l32i.n a9,a14,0 # [0] id:301 + add.n a6,a6,a9 # [2] + +// apply quantization +.Lt_0_10754: # 0x218 + l32i a2,a1,52 # [1] gra_spill_temp_0 // left_shift + l32i a5,a1,56 # [2] gra_spill_temp_1 // right_shift + ssl a2 # [3] + sll a6,a6 # [5] // x * (1 << left_shift) + + l32r a3,.LC3_26_101 # [0] + + add.n a10,a10,a12 # [0] + addi.n a14,a14,4 # [1] + + l32i a4,a1,128 # [2] gra_spill_temp_10 //out_mult + add.n a11,a11,a12 # [6] + +// multiply add nudge and pick high32 + ssai 31 + mulsh a7,a4,a6 # [4] + mull a4,a4,a6 # [5] + + mov.n a2,a11 # [27] + add a4,a4,a3 + saltu a8,a4,a3 + add.n a7,a7,a8 + src a3,a7,a4 + +// divide_by_power_of2_step + blti a5,1,.skip_divide_by2 + movi.n a8,1 # [28] + addi a4,a5,-1 + ssl a4 // load left_shift + sll a8,a8 // to_add factor ( 1 << (exponent - 1)) + extui a6,a3,31,1 # [33] + sub a8,a8,a6 // modified to_add factor ( 1 << (exponent - 1) - (val < 0)) + add a3,a3,a8 // val + to_add + ssr a5 # [29] //load right_shift + sra a3,a3 # [31] +.skip_divide_by2: + + l32i a8,a1,120 # [41] out_offset + l32i a7,a1,132 # [44] // activation_min + l32i a4,a1,136 # [45] // activation_max + + add.n a8,a8,a3 # [46] // add out_offset + l32i a6,a1,72 # [47] gra_spill_temp_5 + l32i.n a3,a1,116 # [48] out_channels + max a7,a7,a8 # [49] + add.n a6,a15,a6 # [50] + min a4,a4,a7 # [51] + addi.n a15,a15,1 # [52] + s8i a4,a6,0 # [53] id:302 + bne a3,a15,.Lt_0_8450 # [55] + +.Lt_0_7938: # 0x25c + retw.n # [0] + + .size esp_nn_fully_connected_s8_esp32s3, . - esp_nn_fully_connected_s8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_avg_pool_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_avg_pool_ansi.c new file mode 100644 index 0000000..84bb786 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_avg_pool_ansi.c @@ -0,0 +1,76 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include + +void esp_nn_avg_pool_s8_ansi(const int8_t *input, + const uint16_t input_wd, + const uint16_t input_ht, + int8_t *output, + const uint16_t output_wd, + const uint16_t output_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t filter_wd, + const uint16_t filter_ht, + const uint16_t pad_wd, + const uint16_t pad_ht, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t channels) +{ + int32_t base_y = -pad_ht; + for (int32_t out_y = 0; out_y < output_ht; out_y++, base_y += stride_ht) { + int32_t base_x = -pad_wd; + for (int32_t out_x = 0; out_x < output_wd; out_x++, base_x += stride_wd) { + for (int32_t ch_idx = 0; ch_idx < channels; ch_idx++) { + int32_t result = 0; + int32_t filter_cnt = 0; + /* Make sure filter does not cross the input box */ + int32_t filter_y_start = max(0, -base_y); + int32_t filter_x_start = max(0, -base_x); + + int32_t filter_y_end = min(filter_ht, input_ht - base_y); + int32_t filter_x_end = min(filter_wd, input_wd - base_x); + + for (int32_t filter_y = filter_y_start; filter_y < filter_y_end; filter_y++) { + for (int32_t filter_x = filter_x_start; filter_x < filter_x_end; filter_x++) { + int32_t in_x_idx = base_x + filter_x; + int32_t in_y_idx = base_y + filter_y; + int32_t input_index = (in_y_idx * input_wd + in_x_idx) * channels + ch_idx; + result += input[input_index]; + filter_cnt++; + } + } + + /* Rounded average */ + result = result > 0 ? (result + filter_cnt / 2) / filter_cnt + : (result - filter_cnt / 2) / filter_cnt; + + /* Activation function */ + result = max(result, activation_min); + result = min(result, activation_max); + + int32_t output_index = (out_y * output_wd + out_x) * channels + ch_idx; + output[output_index] = (int8_t) result; + } + } + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_avg_pool_s8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_avg_pool_s8_esp32s3.S new file mode 100644 index 0000000..9e76a1e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_avg_pool_s8_esp32s3.S @@ -0,0 +1,686 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .align 4 + .literal_position + + # Program Unit: esp_nn_avg_pool_s8_esp32s3 + .type esp_nn_avg_pool_s8_esp32s3, @function + .align 4 + .global esp_nn_avg_pool_s8_esp32s3 + +// no of channels must be multiple of 4. + +// a2: input +// a3: input_wd +// a4: input_ht +// a5: output +// a6: output_wd +// a7: output_ht +// on stack: stride_wd +// on stack: stride_ht +// on stack: filter_wd +// on stack: filter_ht +// on stack: pad_wd +// on stack: pad_ht +// on stack: activation_min +// on stack: activation_max +// on stack: channels + +esp_nn_avg_pool_s8_esp32s3: # 0x4 + # activation_min = 0 + # activation_max = 4 + # gra_spill_temp_0 = 8 + # gra_spill_temp_1 = 12 + # gra_spill_temp_2 = 16 + # gra_spill_temp_3 = 20 + # gra_spill_temp_4 = 24 + # gra_spill_temp_5 = 28 + # gra_spill_temp_6 = 32 + # gra_spill_temp_7 = 36 + # gra_spill_temp_8 = 40 + # gra_spill_temp_9 = 44 + # gra_spill_temp_10 = 48 + # gra_spill_temp_11 = 52 + # gra_spill_temp_12 = 56 + # gra_spill_temp_13 = 60 + # gra_spill_temp_14 = 64 + # gra_spill_temp_15 = 68 + # gra_spill_temp_16 = 72 + # gra_spill_temp_17 = 76 + # gra_spill_temp_18 = 80 + # gra_spill_temp_19 = 84 + # gra_spill_temp_20 = 88 + # gra_spill_temp_21 = 92 + # gra_spill_temp_22 = 96 + # gra_spill_temp_23 = 100 + # gra_spill_temp_24 = 104 + # gra_spill_temp_25 = 108 + # gra_spill_temp_26 = 112 + # gra_spill_temp_27 = 116 + # gra_spill_temp_28 = 120 + # gra_spill_temp_29 = 124 + # gra_spill_temp_30 = 128 + # gra_spill_temp_31 = 132 + # gra_spill_temp_32 = 136 + # gra_spill_temp_33 = 140 + # gra_spill_temp_34 = 144 + # gra_spill_temp_35 = 148 + # gra_spill_temp_36 = 152 + # gra_spill_temp_37 = 156 + # gra_spill_temp_38 = 160 + # gra_spill_temp_39 = 164 + # gra_spill_temp_40 = 168 + # gra_spill_temp_41 = 172 + # gra_spill_temp_43 = 180 + + entry a1,240 # + mov.n a11,a3 # [0] + mov.n a12,a2 # [1] + s32i a5,a1,136 # [4] gra_spill_temp_30 + s32i a6,a1,128 # [3] gra_spill_temp_32 + + l16ui a5,a1,272 # [5] id:663 channels+0x0 + s32i a7,a1,72 # [6] gra_spill_temp_16 + + l32i a9,a1,264 # [1] id:664 activation_min+0x0 + l32i a10,a1,268 # [2] id:666 activation_max+0x0 + s32i.n a9,a1,0 # [4] activation_min + s32i.n a10,a1,4 # [3] activation_max + addi.n a8,a1,4 # [0] activation_max + ee.vldbc.32 q7,a1 # [5] id:668 activation_min + ee.vldbc.32 q6,a8 # [6] id:669 activation_max + ee.zero.q q4 # [0] + + extui a10,a5,0,3 # [7] + beqz.n a10,.LBB3_esp_nn_avg_pool_s8_esp32s3 # [8], if (channels % 8 == 0) + + extui a13,a5,0,2 # [0] + beqz.n a13,.LBB52_esp_nn_avg_pool_s8_esp32s3 # [1], if (channels % 4 == 0) + +// exit +.Lt_0_44546: # 0x1e9 + retw.n # [0] + +.LBB3_esp_nn_avg_pool_s8_esp32s3: # 0x1eb // if (channels % 8 == 0) + + l16ui a7,a1,256 # [1] id:671 pad_wd+0x0 + l16ui a10,a1,260 # [5] id:670 pad_ht+0x0 + l32i a15,a1,72 # [12] gra_spill_temp_16 + movi.n a14,0 # [13] + movi.n a8,0 # [14] + neg a10,a10 # [15] + s32i a10,a1,56 # [16] gra_spill_temp_12 + s32i a8,a1,44 # [17] gra_spill_temp_9 + s32i.n a14,a1,20 # [18] gra_spill_temp_3 + sub a9,a4,a10 # [19] + s32i a9,a1,40 # [20] gra_spill_temp_8 + mul16u a15,a15,a5 # [21] + neg a13,a7 # [22] + s32i a13,a1,104 # [23] gra_spill_temp_24 + s32i.n a15,a1,16 # [24] gra_spill_temp_2 + sub a13,a3,a13 # [25] + s32i.n a13,a1,12 # [26] gra_spill_temp_1 + j .Lt_0_28162 # [27] + +.Lt_0_28418: # 0x24e +# Part of loop body line 44, head labeled .Lt_0_28162 + l32i a15,a1,260 # [0] pad_ht + l32i a14,a1,56 # [1] gra_spill_temp_12 + l32i.n a9,a1,16 # [2] gra_spill_temp_2 + l32i a13,a1,244 # [3] stride_ht + l32i a10,a1,40 # [4] gra_spill_temp_8 + l32i a8,a1,44 # [5] gra_spill_temp_9 + sub a10,a10,a13 # [6] + add.n a8,a8,a9 # [7] + add.n a14,a14,a13 # [8] + sub a15,a15,a13 # [9] + s32i a15,a1,260 # [10] pad_ht + s32i a14,a1,56 # [11] gra_spill_temp_12 + s32i a8,a1,44 # [12] gra_spill_temp_9 + s32i a10,a1,40 # [13] gra_spill_temp_8 + l32i.n a8,a1,20 # [14] gra_spill_temp_3 + l32i a9,a1,72 # [15] gra_spill_temp_16 + addi.n a8,a8,1 # [16] + s32i.n a8,a1,20 # [17] gra_spill_temp_3 + beq a8,a9,.Lt_0_44546 # [18] + +.Lt_0_28162: # 0x281 + l32i a10,a1,128 # [0] gra_spill_temp_32 + beqz.n a10,.Lt_0_28418 # [2] + +.LBB7_esp_nn_avg_pool_s8_esp32s3: # 0x286 +# Part of loop body line 44, head labeled .Lt_0_28162 + s32i a7,a1,112 # [0] gra_spill_temp_26 + movi.n a10,0 # [1] + l32i a9,a1,260 # [2] pad_ht + l32i.n a6,a1,12 # [3] gra_spill_temp_1 + l32i a8,a1,44 # [4] gra_spill_temp_9 + movi.n a13,0 # [5] + l32i a15,a1,104 # [6] gra_spill_temp_24 + s32i a15,a1,116 # [7] gra_spill_temp_27 + s32i a13,a1,48 # [8] gra_spill_temp_10 + s32i a8,a1,124 # [9] gra_spill_temp_29 + s32i a6,a1,120 # [10] gra_spill_temp_28 + l32i a8,a1,40 # [11] gra_spill_temp_8 + l32i a6,a1,252 # [12] filter_ht + movi.n a13,0 # [13] + max a9,a9,a10 # [14] + s32i a9,a1,160 # [15] gra_spill_temp_38 + s32i a13,a1,92 # [16] gra_spill_temp_21 + min a6,a6,a8 # [17] + bnez.n a5,.LBB10_esp_nn_avg_pool_s8_esp32s3 # [18] + +.Lt_0_29186: # 0x2ba + l32i a8,a1,116 # [0] gra_spill_temp_27 + l32i a15,a1,120 # [1] gra_spill_temp_28 + l32i a9,a1,48 # [2] gra_spill_temp_10 + l32i a14,a1,240 # [3] stride_wd + l32i a10,a1,124 # [4] gra_spill_temp_29 + l32i a13,a1,112 # [5] gra_spill_temp_26 + add.n a10,a10,a5 # [6] + s32i a10,a1,124 # [7] gra_spill_temp_29 + sub a13,a13,a14 # [8] + add.n a9,a9,a14 # [9] + sub a15,a15,a14 # [10] + add.n a8,a8,a14 # [11] + s32i a8,a1,116 # [12] gra_spill_temp_27 + s32i a15,a1,120 # [13] gra_spill_temp_28 + s32i a9,a1,48 # [14] gra_spill_temp_10 + s32i a13,a1,112 # [15] gra_spill_temp_26 + l32i a9,a1,92 # [16] gra_spill_temp_21 + l32i a10,a1,128 # [17] gra_spill_temp_32 + addi.n a9,a9,1 # [18] + s32i a9,a1,92 # [19] gra_spill_temp_21 + beq a9,a10,.Lt_0_28418 # [20] + +.Lt_0_28930: # 0x2f5 +# Part of loop body line 46, head labeled .Lt_0_29186 + beqz.n a5,.Lt_0_29186 # [0] + +.LBB10_esp_nn_avg_pool_s8_esp32s3: # 0x2f7 +# Part of loop body line 44, head labeled .Lt_0_28162 + l32i a14,a1,120 # [0] gra_spill_temp_28 + l32i a13,a1,248 # [1] filter_wd + l32i a9,a1,136 # [2] gra_spill_temp_30 + l32i a8,a1,124 # [3] gra_spill_temp_29 + movi.n a15,0 # [4] + s32i a15,a1,24 # [5] gra_spill_temp_60 + add.n a10,a8,a5 # [6] + movi.n a15,0 # [7] + add.n a8,a8,a9 # [8] + min a13,a13,a14 # [9] + add.n a10,a9,a10 # [10] + s32i a10,a1,180 # [11] gra_spill_temp_43 + s32i a13,a1,76 # [12] gra_spill_temp_17 + l32i a14,a1,112 # [13] gra_spill_temp_26 + s32i a8,a1,148 # [14] gra_spill_temp_45 + max a14,a14,a15 # [15] + l32i a15,a1,116 # [16] gra_spill_temp_27 + s32i a14,a1,152 # [17] gra_spill_temp_63 + add.n a8,a15,a14 # [18] + s32i a8,a1,36 # [19] gra_spill_temp_7 + add.n a15,a15,a13 # [20] + s32i a15,a1,204 # [21] gra_spill_temp_39 + sub a13,a13,a14 # [22] + s32i a13,a1,280 # [23] gra_spill_temp_58 + j .Lt_0_29698 # [24] + +.LBB13_esp_nn_avg_pool_s8_esp32s3: # 0x33b +# Part of loop body line 16, head labeled .Lt_0_29698 + l32i a10,a1,56 # [0] gra_spill_temp_12 + l32i a14,a1,204 # [1] gra_spill_temp_39 + add.n a10,a10,a15 # [2] + mull a10,a11,a10 # [3] + movi.n a15,0 # [4] + add.n a14,a10,a14 # [5] + +.Lt_0_30466: # 0x34a +# Loop body line 61, nesting depth: 4, estimated iterations: 252 + l32i a9,a1,76 # [0] gra_spill_temp_17 + l32i a8,a1,152 # [1] gra_spill_temp_63 + add.n a14,a14,a11 # [2] + bge a8,a9,.Lt_0_30722 # [3] + +.LBB16_esp_nn_avg_pool_s8_esp32s3: # 0x355 +# Part of loop body line 61, head labeled .Lt_0_30466 + l32i a3,a1,36 # [0] gra_spill_temp_7 + l32i a2,a1,24 # [1] gra_spill_temp_4 + add.n a3,a3,a10 # [2] + mull a3,a3,a5 # [3] + movi.n a8,0 # [4] + add.n a2,a2,a3 # [5] + l32i a3,a1,280 # [6] gra_spill_temp_58 + add.n a2,a12,a2 # [7] + loopgtz a3,.LBB140_esp_nn_avg_pool_s8_esp32s3 # [8] + + ee.vld.l.64.xp q0,a2,a5 # [0*II+1] id:677 + ee.vcmp.lt.s8 q1,q0,q4 # [0*II+3] + ee.vzip.8 q0,q1 # [0*II+4] + ee.vcmp.lt.s16 q1,q0,q4 # [0*II+5] + ee.vzip.16 q0,q1 # [0*II+6] + ee.vadds.s32 q2,q2,q1 # [0*II+7] + ee.vadds.s32 q3,q3,q0 # [0*II+8] + + +.LBB140_esp_nn_avg_pool_s8_esp32s3: # 0x385 +# Part of loop body line 61, head labeled .Lt_0_30466 + l32i a2,a1,48 # [0] gra_spill_temp_10 + sub a9,a7,a2 # [2] + sub a2,a2,a7 # [3] + max a9,a9,a8 # [4] + l32i a8,a1,248 # [5] filter_wd + sub a2,a11,a2 # [6] + min a8,a8,a2 # [7] + sub a8,a8,a9 # [8] + add.n a15,a15,a8 # [9] + +.Lt_0_30722: # 0x39f +# Part of loop body line 61, head labeled .Lt_0_30466 + add.n a10,a10,a11 # [0] + addi.n a13,a13,1 # [1] + bne a6,a13,.Lt_0_30466 # [2] + +.Lt_0_29954: # 0x3a6 + srai a2,a15,1 # [3] + +// move data to general purpose registers and average + ee.movi.32.a q3,a9,0 # [0] + ee.movi.32.a q3,a4,1 # [0] + + blti a9,1,.Lt_0_32258 # [4] + add.n a9,a9,a2 # [0] + j .Lt_0_32002 # [2] +.Lt_0_32258: # 0x45e + sub a9,a9,a2 # [0] +.Lt_0_32002: # 0x3b9 + + blti a4,1,.Lt_0_32770 # [1] + add.n a4,a2,a4 # [0] + j .Lt_0_32514 # [2] +.Lt_0_32770: + sub a4,a4,a2 # [0] +.Lt_0_32514: # 0x3c4 + + quos a9,a9,a15 # [1] + quos a4,a4,a15 # [1] + ee.movi.32.q q3,a9,0 # [0] + ee.movi.32.q q3,a4,1 # [1] + + ee.movi.32.a q3,a9,2 # [2] + ee.movi.32.a q3,a14,3 # [0] + + blti a9,1,.Lt_0_33282 # [3] + add.n a9,a9,a2 # [0] + j .Lt_0_33026 # [2] +.Lt_0_33282: # 0x470 + sub a9,a9,a2 # [0] +.Lt_0_33026: # 0x3d5 + + blti a14,1,.Lt_0_33794 # [1] + add.n a14,a2,a14 # [0] + j .Lt_0_33538 # [2] +.Lt_0_33794: # 0x479 + sub a14,a14,a2 # [0] +.Lt_0_33538: # 0x3e0 + + quos a9,a9,a15 # [1] + quos a14,a14,a15 # [1] + ee.movi.32.q q3,a9,2 # [0] + ee.movi.32.q q3,a14,3 # [1] + + + ee.movi.32.a q2,a9,0 # [0] + ee.movi.32.a q2,a4,1 # [0] + + blti a9,1,.Lt_0_34306 # [3] + add.n a9,a9,a2 # [0] + j .Lt_0_34050 # [2] +.Lt_0_34306: # 0x482 + sub a9,a9,a2 # [0] +.Lt_0_34050: # 0x3f1 + + blti a4,1,.Lt_0_34818 # [1] + add.n a4,a2,a4 # [0] + j .Lt_0_34562 # [2] +.Lt_0_34818: # 0x48b + sub a4,a4,a2 # [0] +.Lt_0_34562: # 0x3fc + + quos a9,a9,a15 # [1] + quos a4,a4,a15 # [1] + ee.movi.32.q q2,a9,0 # [0] + ee.movi.32.q q2,a4,1 # [1] + + ee.movi.32.a q2,a9,2 # [2] + ee.movi.32.a q2,a14,3 # [0] + + blti a9,1,.Lt_0_35330 # [3] + add.n a9,a9,a2 # [0] + j .Lt_0_35074 # [2] +.Lt_0_35330: # 0x494 + sub a9,a9,a2 # [0] +.Lt_0_35074: # 0x40d + + blti a14,1,.Lt_0_35842 # [1] + add.n a14,a2,a14 # [0] + j .Lt_0_35586 # [2] +.Lt_0_35842: # 0x49d + sub a14,a14,a2 # [0] +.Lt_0_35586: # 0x418 + + quos a9,a9,a15 # [1] + quos a14,a14,a15 # [1] + ee.movi.32.q q2,a9,2 # [0] + ee.movi.32.q q2,a14,3 # [1] + + + l32i a9,a1,180 # [0] gra_spill_temp_43 + l32i a14,a1,24 # [1] gra_spill_temp_4 + l32i a13,a1,148 # [2] gra_spill_temp_45 + ee.vmin.s32 q1,q3,q6 # [4] + ee.vmax.s32 q1,q1,q7 # [5] + ee.vmin.s32 q5,q2,q6 # [8] + addi.n a14,a14,8 # [9] + s32i a14,a1,24 # [10] gra_spill_temp_4 + ee.vmax.s32 q5,q5,q7 # [11] + addi.n a8,a13,8 # [12] + s32i a8,a1,148 # [13] gra_spill_temp_45 + ee.vunzip.16 q1,q5 # [14] + ee.vunzip.8 q1,q5 # [15] + ee.vst.l.64.ip q1,a13,0 # [16] id:678 + bge a8,a9,.Lt_0_29186 # [17] + +.Lt_0_29698: # 0x44b +# Loop body line 16, nesting depth: 3, estimated iterations: 252 + mv.qr q3,q4 # [0] + l32i a15,a1,160 # [1] gra_spill_temp_38 + mv.qr q2,q4 # [2] + mov.n a13,a15 # [3] + blt a15,a6,.LBB13_esp_nn_avg_pool_s8_esp32s3 # [4] + +.Lt_0_51458: # 0x459 +# Part of loop body line 16, head labeled .Lt_0_29698 + movi.n a15,0 # [0] + j .Lt_0_29954 # [1] + + +.LBB52_esp_nn_avg_pool_s8_esp32s3: # 0x4a6 // if (channels % 4 == 0) + + l16ui a7,a1,256 # [1] id:671 pad_wd+0x0 + l16ui a13,a1,260 # [5] id:670 pad_ht+0x0 + s32i a13,a1,64 # [8] gra_spill_temp_4 + l32i a8,a1,72 # [12] gra_spill_temp_16 + movi.n a15,0 # [13] + movi.n a9,0 # [14] + neg a13,a13 # [15] + s32i a13,a1,192 # [16] gra_spill_temp_36 + s32i a9,a1,32 # [17] gra_spill_temp_6 + s32i.n a15,a1,8 # [18] gra_spill_temp_0 + sub a10,a4,a13 # [19] + s32i a10,a1,28 # [20] gra_spill_temp_5 + mul16u a8,a8,a5 # [21] + neg a14,a7 # [22] + s32i a14,a1,104 # [23] gra_spill_temp_24 + s32i.n a8,a1,16 # [24] gra_spill_temp_2 + sub a14,a3,a14 # [25] + s32i.n a14,a1,12 # [26] gra_spill_temp_1 + j .Lt_0_37890 # [27] + +.Lt_0_38146: # 0x50b +# Part of loop body line 161, head labeled .Lt_0_37890 + l32i a15,a1,64 # [0] gra_spill_temp_4 + l32i a14,a1,192 # [1] gra_spill_temp_36 + l32i.n a9,a1,16 # [2] gra_spill_temp_2 + l32i a13,a1,244 # [3] stride_ht + l32i a10,a1,28 # [4] gra_spill_temp_5 + l32i a8,a1,32 # [5] gra_spill_temp_6 + sub a10,a10,a13 # [6] + add.n a8,a8,a9 # [7] + add.n a14,a14,a13 # [8] + sub a15,a15,a13 # [9] + s32i a15,a1,64 # [10] gra_spill_temp_4 + s32i a14,a1,192 # [11] gra_spill_temp_36 + s32i a8,a1,32 # [12] gra_spill_temp_6 + s32i a10,a1,28 # [13] gra_spill_temp_5 + l32i.n a8,a1,8 # [14] gra_spill_temp_0 + l32i a9,a1,72 # [15] gra_spill_temp_16 + addi.n a8,a8,1 # [16] + s32i.n a8,a1,8 # [17] gra_spill_temp_0 + sub a8,a8,a9 # [18] + beqz a8,.Lt_0_44546 # [19] + +.Lt_0_37890: # 0x541 +# Loop body line 161, nesting depth: 1, estimated iterations: 252 + l32i a10,a1,128 # [0] gra_spill_temp_32 + beqz.n a10,.Lt_0_38146 # [2] + +# Part of loop body line 161, head labeled .Lt_0_37890 + s32i a7,a1,96 # [0] gra_spill_temp_22 + movi.n a10,0 # [1] + l32i a9,a1,64 # [2] gra_spill_temp_4 + l32i.n a6,a1,12 # [3] gra_spill_temp_1 + l32i a8,a1,32 # [4] gra_spill_temp_6 + movi.n a13,0 # [5] + l32i a15,a1,104 # [6] gra_spill_temp_24 + s32i a15,a1,100 # [7] gra_spill_temp_23 + s32i a13,a1,148 # [8] gra_spill_temp_35 + s32i a8,a1,108 # [9] gra_spill_temp_25 + s32i a6,a1,144 # [10] gra_spill_temp_24 + l32i a8,a1,28 # [11] gra_spill_temp_5 + l32i a6,a1,252 # [12] filter_ht + max a9,a9,a10 # [14] + s32i a9,a1,168 # [15] gra_spill_temp_40 + s32i a13,a1,88 # [16] gra_spill_temp_20 + min a6,a6,a8 # [17] + bnez.n a5,.LBB59_esp_nn_avg_pool_s8_esp32s3 # [18] + +.Lt_0_38914: # 0x57a +# Loop body line 163 + l32i a8,a1,100 # [0] gra_spill_temp_23 + l32i a15,a1,144 # [1] gra_spill_temp_24 + l32i a9,a1,148 # [2] gra_spill_temp_35 + l32i a14,a1,240 # [3] stride_wd + l32i a10,a1,108 # [4] gra_spill_temp_25 + l32i a13,a1,96 # [5] gra_spill_temp_22 + add.n a10,a10,a5 # [6] + s32i a10,a1,108 # [7] gra_spill_temp_25 + sub a13,a13,a14 # [8] + add.n a9,a9,a14 # [9] + sub a15,a15,a14 # [10] + add.n a8,a8,a14 # [11] + s32i a8,a1,100 # [12] gra_spill_temp_23 + s32i a15,a1,144 # [13] gra_spill_temp_24 + s32i a9,a1,148 # [14] gra_spill_temp_35 + s32i a13,a1,96 # [15] gra_spill_temp_22 + l32i a9,a1,88 # [16] gra_spill_temp_20 + l32i a10,a1,128 # [17] gra_spill_temp_32 + addi.n a9,a9,1 # [18] + s32i a9,a1,88 # [19] gra_spill_temp_20 + beq a9,a10,.Lt_0_38146 # [20] + + beqz.n a5,.Lt_0_38914 # [0] + +.LBB59_esp_nn_avg_pool_s8_esp32s3: # 0x5b7 +# Part of loop body line 161, head labeled .Lt_0_37890 + l32i a14,a1,144 # [0] gra_spill_temp_24 + l32i a13,a1,248 # [1] filter_wd + l32i a9,a1,136 # [2] gra_spill_temp_30 + l32i a8,a1,108 # [3] gra_spill_temp_25 + movi.n a15,0 # [4] + s32i a15,a1,216 # [5] gra_spill_temp_52 + add.n a10,a8,a5 # [6] + add.n a8,a8,a9 # [8] + min a13,a13,a14 # [9] + add.n a10,a9,a10 # [10] + s32i a10,a1,172 # [11] gra_spill_temp_41 + s32i a13,a1,132 # [12] gra_spill_temp_31 + l32i a14,a1,96 # [13] gra_spill_temp_22 + s32i a8,a1,164 # [14] gra_spill_temp_39 + max a14,a14,a15 # [15] + l32i a15,a1,100 # [16] gra_spill_temp_23 + s32i a14,a1,208 # [17] gra_spill_temp_50 + add.n a8,a15,a14 # [18] + s32i a8,a1,60 # [19] gra_spill_temp_13 + add.n a15,a15,a13 # [20] + s32i a15,a1,196 # [21] gra_spill_temp_37 + sub a13,a13,a14 # [22] + s32i a13,a1,52 # [23] gra_spill_temp_11 + j .Lt_0_39426 # [24] + +.LBB62_esp_nn_avg_pool_s8_esp32s3: # 0x5fb +# Part of loop body line 173, head labeled .Lt_0_39426 + l32i a10,a1,192 # [0] gra_spill_temp_36 + l32i a14,a1,196 # [1] gra_spill_temp_37 + add.n a10,a10,a15 # [2] + mull a10,a11,a10 # [3] + movi.n a15,0 # [4] + add.n a14,a10,a14 # [5] + +.Lt_0_40194: # 0x60a +# Loop body line 178, nesting depth: 4, estimated iterations: 252 + l32i a9,a1,132 # [0] gra_spill_temp_31 + l32i a8,a1,208 # [1] gra_spill_temp_50 + add.n a14,a14,a11 # [2] + bge a8,a9,.Lt_0_40450 # [3] + +.LBB65_esp_nn_avg_pool_s8_esp32s3: # 0x615 +# Part of loop body line 178, head labeled .Lt_0_40194 + l32i a3,a1,60 # [0] gra_spill_temp_13 + l32i a2,a1,216 # [1] gra_spill_temp_52 + add.n a3,a3,a10 # [2] + mull a3,a3,a5 # [3] + l32i a4,a1,52 # [4] gra_spill_temp_11 + add.n a2,a2,a3 # [5] + add.n a2,a12,a2 # [6] + loopgtz a4,.LBB155_esp_nn_avg_pool_s8_esp32s3 # [7] + + ee.vldbc.32.xp q0,a2,a5 # [0*II+0] id:684 + ee.vcmp.lt.s8 q1,q0,q4 # [0*II+2] + ee.vzip.8 q0,q1 # [0*II+3] + ee.vcmp.lt.s16 q1,q0,q4 # [0*II+4] + ee.vzip.16 q0,q1 # [0*II+5] + ee.vadds.s32 q2,q2,q0 # [0*II+6] + +.LBB155_esp_nn_avg_pool_s8_esp32s3: # 0x63e +# Part of loop body line 178, head labeled .Lt_0_40194 + l32i a2,a1,148 # [0] gra_spill_temp_35 + movi.n a8,0 # [1] + sub a9,a7,a2 # [2] + sub a2,a2,a7 # [3] + max a9,a9,a8 # [4] + l32i a8,a1,248 # [5] filter_wd + sub a2,a11,a2 # [6] + min a8,a8,a2 # [7] + sub a8,a8,a9 # [8] + add.n a15,a15,a8 # [9] + +.Lt_0_40450: # 0x65a +# Part of loop body line 178, head labeled .Lt_0_40194 + add.n a10,a10,a11 # [0] + addi.n a13,a13,1 # [1] + bne a6,a13,.Lt_0_40194 # [2] + +.Lt_0_39682: # 0x661 +# Part of loop body line 173, head labeled .Lt_0_39426 + srai a2,a15,1 # [5] + +// move to gp registers and average + + ee.movi.32.a q2,a9,0 # [0] + ee.movi.32.a q2,a4,1 # [0] + + blti a9,1,.Lt_0_41986 # [3] + add.n a9,a9,a2 # [0] + j .Lt_0_41730 # [2] +.Lt_0_41986: # 0x482 + sub a9,a9,a2 # [0] +.Lt_0_41730: # 0x3f1 + + blti a4,1,.Lt_0_42498 # [1] + add.n a4,a2,a4 # [0] + j .Lt_0_42242 # [2] +.Lt_0_42498: # 0x48b + sub a4,a4,a2 # [0] +.Lt_0_42242: # 0x3fc + + + quos a9,a9,a15 # [1] + quos a4,a4,a15 # [1] + ee.movi.32.q q2,a9,0 # [0] + ee.movi.32.q q2,a4,1 # [1] + + ee.movi.32.a q2,a9,2 # [2] + ee.movi.32.a q2,a14,3 # [0] + + blti a9,1,.Lt_0_43010 # [3] + add.n a9,a9,a2 # [0] + j .Lt_0_42754 # [2] +.Lt_0_43010: # 0x494 + sub a9,a9,a2 # [0] +.Lt_0_42754: # 0x40d + + + blti a14,1,.Lt_0_43522 # [1] + add.n a14,a2,a14 # [0] + j .Lt_0_43266 # [2] +.Lt_0_43522: # 0x49d + sub a14,a14,a2 # [0] +.Lt_0_43266: # 0x418 + + quos a9,a9,a15 # [1] + quos a14,a14,a15 # [1] + ee.movi.32.q q2,a9,2 # [0] + ee.movi.32.q q2,a14,3 # [1] + + + l32i a9,a1,172 # [0] gra_spill_temp_41 + l32i a8,a1,164 # [1] gra_spill_temp_39 + l32i a14,a1,216 # [2] gra_spill_temp_52 + addi.n a14,a14,4 # [5] + ee.vmin.s32 q2,q2,q6 # [6] + s32i a14,a1,216 # [7] gra_spill_temp_52 + ee.vmax.s32 q2,q2,q7 # [8] + ee.vunzip.16 q2,q1 # [9] + ee.vunzip.8 q2,q1 # [10] + ee.vst.l.64.ip q2,a1,0 # [11] id:691 + l32i.n a13,a1,0 # [12] id:692 + s32i.n a13,a8,0 # [13] id:693 + addi.n a8,a8,4 # [14] + s32i a8,a1,164 # [15] gra_spill_temp_39 + bge a8,a9,.Lt_0_38914 # [16] + +.Lt_0_39426: # 0x6cb + l32i a15,a1,168 # [0] gra_spill_temp_40 + mv.qr q2,q4 # [1] + mov.n a13,a15 # [2] + blt a15,a6,.LBB62_esp_nn_avg_pool_s8_esp32s3 # [3] + +.Lt_0_52738: # 0x6d6 + movi.n a15,0 # [0] + j .Lt_0_39682 # [1] + + .size esp_nn_avg_pool_s8_esp32s3, . - esp_nn_avg_pool_s8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_max_pool_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_max_pool_ansi.c new file mode 100644 index 0000000..94d2344 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_max_pool_ansi.c @@ -0,0 +1,70 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include + +#include + +void esp_nn_max_pool_s8_ansi(const int8_t *input, + const uint16_t input_wd, + const uint16_t input_ht, + int8_t *output, + const uint16_t output_wd, + const uint16_t output_ht, + const uint16_t stride_wd, + const uint16_t stride_ht, + const uint16_t filter_wd, + const uint16_t filter_ht, + const uint16_t pad_wd, + const uint16_t pad_ht, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t channels) +{ + int32_t base_y = -pad_ht; + for (int32_t out_y = 0; out_y < output_ht; out_y++, base_y += stride_ht) { + int32_t base_x = -pad_wd; + for (int32_t out_x = 0; out_x < output_wd; out_x++, base_x += stride_wd) { + /* Make sure filter does not cross the input box */ + int32_t filter_y_start = max(0, -base_y); + int32_t filter_x_start = max(0, -base_x); + int32_t filter_y_end = min(filter_ht, input_ht - base_y); + int32_t filter_x_end = min(filter_wd, input_wd - base_x); + + for (int32_t ch_idx = 0; ch_idx < channels; ch_idx++) { + int8_t result = INT8_MIN; + + for (int32_t filter_y = filter_y_start; filter_y < filter_y_end; filter_y++) { + for (int32_t filter_x = filter_x_start; filter_x < filter_x_end; filter_x++) { + int32_t in_x_idx = base_x + filter_x; + int32_t in_y_idx = base_y + filter_y; + int32_t input_index = (in_y_idx * input_wd + in_x_idx) * channels + ch_idx; + result = max(input[input_index], result); + } + } + + /* Activation function */ + result = max(result, activation_min); + result = min(result, activation_max); + + int32_t output_index = (out_y * output_wd + out_x) * channels + ch_idx; + output[output_index] = result; + } + } + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_max_pool_s8_esp32s3.S b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_max_pool_s8_esp32s3.S new file mode 100644 index 0000000..722e0db --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/pooling/esp_nn_max_pool_s8_esp32s3.S @@ -0,0 +1,449 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 +// Copyright 2021-2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + .text + .align 4 + .literal_position + + # Program Unit: esp_nn_max_pool_s8_esp32s3 + .type esp_nn_max_pool_s8_esp32s3, @function + .align 4 + .global esp_nn_max_pool_s8_esp32s3 + +// no of channels must be multiple of 4 + +esp_nn_max_pool_s8_esp32s3: # 0x4 + # int8_min = 0 + # gra_spill_temp_0 = 4 + # gra_spill_temp_1 = 8 + # gra_spill_temp_2 = 12 + # gra_spill_temp_3 = 16 + # gra_spill_temp_4 = 20 + # gra_spill_temp_5 = 24 + # gra_spill_temp_6 = 28 + # gra_spill_temp_7 = 32 + # gra_spill_temp_8 = 36 + # gra_spill_temp_9 = 40 + # gra_spill_temp_10 = 44 + # gra_spill_temp_11 = 48 + # gra_spill_temp_12 = 52 + # gra_spill_temp_13 = 56 + # gra_spill_temp_14 = 60 + # gra_spill_temp_15 = 64 + # gra_spill_temp_16 = 68 + # gra_spill_temp_17 = 72 + # gra_spill_temp_18 = 76 + # gra_spill_temp_19 = 80 + # gra_spill_temp_20 = 84 + # gra_spill_temp_21 = 88 + # gra_spill_temp_22 = 92 + # gra_spill_temp_23 = 96 + +// a2: input +// a3: input_wd +// a4: input_ht +// a5: output +// a6: output_wd +// a7: output_ht +// on stack: stride_wd = 120 +// on stack: stride_ht = 124 +// on stack: filter_wd = 128 +// on stack: filter_ht = 132 +// on stack: pad_wd = 136 +// on stack: pad_ht = 140 +// on stack: activation_min +// on stack: activation_max +// on stack: channels + + + entry a1,120 # + mov.n a12,a2 # [0] + s32i a6,a1,4 # [2] gra_spill_temp_0 + s32i a7,a1,68 # [3] gra_spill_temp_16 + mov.n a11,a3 # [4] + s32i a5,a1,96 # [5] gra_spill_temp_23 + + l16ui a5,a1,152 # [6] id:465 channels+0x0 + movi a3,-128 # [7] + s32i.n a3,a1,0 # [1] int8_min + + addi.n a9,a1,148 # [0] activation_max + addi.n a15,a1,144 # [1] activation_min + ee.vldbc.8 q3,a1 # [7] id:473 int8_min+0x0 + ee.vldbc.8 q5,a15 # [8] id:470 activation_min+0x0 + ee.vldbc.8 q4,a9 # [9] id:471 activation_max+0x0 + + extui a8,a5,0,3 # [8] + beqz.n a8,.LBB3_esp_nn_max_pool_s8_esp32s3 # [9] // if (channels % 8 == 0) + + extui a14,a5,0,2 # [0] + beqz.n a14,.LBB25_esp_nn_max_pool_s8_esp32s3 # [1] // if (channels % 4 == 0) + + retw.n # [0] // exit + +.LBB3_esp_nn_max_pool_s8_esp32s3: # 0x1c5 // if (channels % 8 == 0) + + l16ui a15,a1,136 # [1] id:475 pad_wd+0x0 + l16ui a14,a1,140 # [4] id:474 pad_ht+0x0 + movi.n a8,0 # [13] + movi.n a10,0 # [15] + s32i a14,a1,44 # [7] gra_spill_temp_10 + neg a15,a15 # [12] + mul16u a9,a6,a5 # [14] + neg a14,a14 # [16] + s32i a14,a1,92 # [17] gra_spill_temp_22 + s32i a10,a1,52 # [18] gra_spill_temp_12 + s32i a9,a1,60 # [19] gra_spill_temp_14 + s32i.n a8,a1,36 # [16] gra_spill_temp_8 + s32i a15,a1,56 # [21] gra_spill_temp_13 + sub a13,a4,a14 # [22] + s32i a13,a1,48 # [23] gra_spill_temp_11 + sub a15,a11,a15 # [24] + s32i.n a15,a1,40 # [25] gra_spill_temp_9 + +.Lt_0_21506: # 0x229 + l32i a8,a1,4 # [0] gra_spill_temp_0 + beqz.n a8,.Lt_0_21762 # [2] + + movi.n a10,0 # [0] + l32i a9,a1,44 # [1] gra_spill_temp_10 + l32i.n a15,a1,40 # [2] gra_spill_temp_9 + l32i a8,a1,52 # [3] gra_spill_temp_12 + l32i.n a13,a1,136 # [4] ,pad_wd + l32i a14,a1,56 # [5] gra_spill_temp_13 + s32i a14,a1,80 # [6] gra_spill_temp_19 + s32i a13,a1,76 # [7] gra_spill_temp_18 + s32i a8,a1,88 # [8] gra_spill_temp_21 + s32i a15,a1,84 # [9] gra_spill_temp_20 + l32i a8,a1,48 # [10] gra_spill_temp_11 + max a9,a9,a10 # [11] + l32i a15,a1,132 # [12] filter_ht + s32i a9,a1,8 # [13] gra_spill_temp_1 + movi.n a9,0 # [14] + min a15,a15,a8 # [15] + s32i a9,a1,64 # [16] gra_spill_temp_15 + +.Lt_0_22274: # 0x25d + beqz.n a5,.Lt_0_22530 # [0] + +.LBB10_esp_nn_max_pool_s8_esp32s3: # 0x25f +# Part of loop body line 46, head labeled .Lt_0_22274 + l32i a6,a1,76 # [0] gra_spill_temp_18 + l32i a13,a1,96 # [1] gra_spill_temp_23 + l32i a8,a1,84 # [2] gra_spill_temp_20 + l32i a7,a1,128 # [3] filter_wd + l32i a10,a1,88 # [4] gra_spill_temp_21 + movi.n a9,0 # [5] + s32i a9,a1,20 # [6] gra_spill_temp_4 + add.n a14,a10,a5 # [7] + min a7,a7,a8 # [8] + add.n a10,a10,a13 # [9] + add.n a14,a13,a14 # [10] + s32i a14,a1,12 # [11] gra_spill_temp_2 + s32i a10,a1,16 # [12] gra_spill_temp_3 + movi.n a8,0 # [13] + l32i a10,a1,80 # [14] gra_spill_temp_19 + max a6,a6,a8 # [15] + sub a9,a7,a6 # [16] + s32i a9,a1,28 # [17] gra_spill_temp_6 + add.n a13,a10,a6 # [18] + s32i a13,a1,24 # [19] gra_spill_temp_5 + add.n a10,a10,a7 # [16] + s32i a10,a1,72 # [21] gra_spill_temp_17 + +.Lt_0_23042: # 0x29a + l32i a8,a1,8 # [0] gra_spill_temp_1 + mv.qr q1,q3 # [1] + mov.n a13,a8 # [2] + bge a8,a15,.Lt_0_23298 # [3] + +.LBB13_esp_nn_max_pool_s8_esp32s3: # 0x2a5 +# Part of loop body line 40, head labeled .Lt_0_23042 + l32i a10,a1,92 # [0] gra_spill_temp_22 + l32i a14,a1,72 # [1] gra_spill_temp_17 + add.n a10,a10,a8 # [2] + mull a10,a11,a10 # [3] + add.n a14,a10,a14 # [5] + +.Lt_0_23810: # 0x2b2 + add.n a14,a14,a11 # [0] + addi.n a13,a13,1 # [1] + bge a6,a7,.Lt_0_24066 # [2] + +.LBB16_esp_nn_max_pool_s8_esp32s3: # 0x2b9 + l32i a3,a1,24 # [0] gra_spill_temp_5 + l32i a2,a1,20 # [1] gra_spill_temp_4 + add.n a3,a3,a10 # [2] + mull a3,a3,a5 # [3] + add.n a2,a2,a3 # [5] + l32i a3,a1,28 # [6] gra_spill_temp_6 + add.n a2,a12,a2 # [7] + loopgtz a3,.LBB93_esp_nn_max_pool_s8_esp32s3 # [8] + + ee.vld.l.64.ip q0,a2,0 # [0*II+1] id:481 + add.n a2,a2,a5 # [0*II+2] + ee.vmax.s8 q1,q1,q0 # [0*II+3] +.LBB93_esp_nn_max_pool_s8_esp32s3: # 0x2d8 + +.Lt_0_24066: # 0x2d8 + add.n a10,a10,a11 # [0] + bne a15,a13,.Lt_0_23810 # [1] + +.Lt_0_23298: # 0x2dd + l32i a9,a1,12 # [0] gra_spill_temp_2 + l32i a13,a1,20 # [1] gra_spill_temp_4 + l32i a8,a1,16 # [2] gra_spill_temp_3 + ee.vmin.s8 q2,q1,q4 # [3] + ee.vmax.s8 q2,q2,q5 # [4] + mov.n a10,a8 # [5] + addi.n a13,a13,8 # [6] + s32i a13,a1,20 # [7] gra_spill_temp_4 + ee.vst.l.64.ip q2,a10,0 # [8] id:482 + addi.n a8,a8,8 # [9] + s32i a8,a1,16 # [10] gra_spill_temp_3 + blt a8,a9,.Lt_0_23042 # [11] + +.Lt_0_22530: # 0x2fe + l32i a13,a1,84 # [0] gra_spill_temp_20 + l32i a14,a1,80 # [1] gra_spill_temp_19 + l32i a10,a1,120 # [2] stride_wd + l32i a8,a1,88 # [3] gra_spill_temp_21 + l32i a9,a1,76 # [4] gra_spill_temp_18 + add.n a8,a8,a5 # [5] + s32i a8,a1,88 # [6] gra_spill_temp_21 + sub a9,a9,a10 # [7] + add.n a14,a14,a10 # [8] + sub a13,a13,a10 # [9] + s32i a13,a1,84 # [10] gra_spill_temp_20 + s32i a14,a1,80 # [11] gra_spill_temp_19 + s32i a9,a1,76 # [12] gra_spill_temp_18 + l32i a14,a1,64 # [13] gra_spill_temp_15 + l32i a8,a1,4 # [14] gra_spill_temp_0 + addi.n a14,a14,1 # [15] + s32i a14,a1,64 # [16] gra_spill_temp_15 + sub a14,a14,a8 # [17] + bnez a14,.Lt_0_22274 # [18] + +.Lt_0_21762: # 0x334 +# Part of loop body line 20, head labeled .Lt_0_21506 + l32i a8,a1,44 # [0] gra_spill_temp_10 + l32i a15,a1,92 # [1] gra_spill_temp_22 + l32i a10,a1,60 # [2] gra_spill_temp_14 + l32i a14,a1,124 # [3] stride_ht + l32i a13,a1,48 # [4] gra_spill_temp_11 + l32i a9,a1,52 # [5] gra_spill_temp_12 + sub a13,a13,a14 # [6] + add.n a9,a9,a10 # [7] + add.n a15,a15,a14 # [8] + sub a8,a8,a14 # [9] + s32i a8,a1,44 # [10] gra_spill_temp_10 + s32i a15,a1,92 # [11] gra_spill_temp_22 + s32i a9,a1,52 # [12] gra_spill_temp_12 + s32i a13,a1,48 # [13] gra_spill_temp_11 + l32i.n a9,a1,36 # [14] gra_spill_temp_8 + l32i a10,a1,68 # [15] gra_spill_temp_16 + addi.n a9,a9,1 # [16] + s32i.n a9,a1,36 # [17] gra_spill_temp_8 + sub a9,a9,a10 # [18] + bnez a9,.Lt_0_21506 # [19] + + retw.n # [0] // exit + +.LBB25_esp_nn_max_pool_s8_esp32s3: # 0x36d // if (channels % 4 == 0) + + l16ui a10,a1,136 # [1] id:475 pad_wd+0x0 + l16ui a9,a1,140 # [4] id:474 pad_ht+0x0 + movi.n a13,0 # [13] + movi.n a15,0 # [15] + neg a10,a10 # [12] + s32i a9,a1,44 # [7] gra_spill_temp_10 + mul16u a14,a6,a5 # [14] + neg a9,a9 # [16] + s32i a9,a1,92 # [17] gra_spill_temp_22 + s32i a15,a1,52 # [18] gra_spill_temp_12 + s32i a14,a1,60 # [19] gra_spill_temp_14 + s32i.n a13,a1,36 # [16] gra_spill_temp_8 + s32i a10,a1,56 # [21] gra_spill_temp_13 + sub a8,a4,a9 # [22] + s32i a8,a1,48 # [23] gra_spill_temp_11 + sub a10,a11,a10 # [24] + s32i.n a10,a1,40 # [25] gra_spill_temp_9 + +.Lt_0_27138: # 0x3d5 + l32i a13,a1,4 # [0] gra_spill_temp_0 + beqz.n a13,.Lt_0_27394 # [2] + +.LBB29_esp_nn_max_pool_s8_esp32s3: # 0x3da +# Part of loop body line 107, head labeled .Lt_0_27138 + movi.n a10,0 # [0] + l32i a9,a1,44 # [1] gra_spill_temp_10 + l32i.n a15,a1,40 # [2] gra_spill_temp_9 + l32i a8,a1,52 # [3] gra_spill_temp_12 + l32i a14,a1,56 # [4] gra_spill_temp_13 + l32i.n a13,a1,136 # [5] pad_wd + s32i a13,a1,76 # [6] gra_spill_temp_18 + s32i a14,a1,80 # [7] gra_spill_temp_19 + s32i a8,a1,88 # [8] gra_spill_temp_21 + s32i a15,a1,84 # [9] gra_spill_temp_20 + l32i a8,a1,48 # [10] gra_spill_temp_11 + l32i a15,a1,132 # [11] filter_ht + movi.n a14,0 # [12] + max a9,a9,a10 # [13] + s32i a9,a1,8 # [14] gra_spill_temp_1 + s32i a14,a1,64 # [15] gra_spill_temp_15 + min a15,a15,a8 # [16] + +.Lt_0_27906: # 0x409 +# Loop body line 109, nesting depth: 2, estimated iterations: 56 + beqz.n a5,.Lt_0_28162 # [0] + +.LBB32_esp_nn_max_pool_s8_esp32s3: # 0x40b +# Part of loop body line 109, head labeled .Lt_0_27906 + l32i a6,a1,76 # [0] gra_spill_temp_18 + l32i a13,a1,96 # [1] gra_spill_temp_23 + l32i a8,a1,84 # [2] gra_spill_temp_20 + l32i a7,a1,128 # [3] filter_wd + l32i a10,a1,88 # [4] gra_spill_temp_21 + movi.n a9,0 # [5] + s32i a9,a1,32 # [6] gra_spill_temp_7 + add.n a14,a10,a5 # [7] + min a7,a7,a8 # [8] + add.n a10,a10,a13 # [9] + add.n a14,a13,a14 # [10] + s32i a14,a1,12 # [11] gra_spill_temp_2 + s32i a10,a1,16 # [12] gra_spill_temp_3 + movi.n a8,0 # [13] + l32i a10,a1,80 # [14] gra_spill_temp_19 + max a6,a6,a8 # [15] + sub a9,a7,a6 # [16] + s32i a9,a1,28 # [17] gra_spill_temp_6 + add.n a13,a10,a6 # [18] + s32i a13,a1,24 # [19] gra_spill_temp_5 + add.n a10,a10,a7 # [16] + s32i a10,a1,72 # [21] gra_spill_temp_17 + +.Lt_0_28674: # 0x446 +# Loop body line 8, nesting depth: 3, estimated iterations: 56 + l32i a8,a1,8 # [0] gra_spill_temp_1 + mv.qr q1,q3 # [1] + mov.n a13,a8 # [2] + bge a8,a15,.Lt_0_28930 # [3] + +.LBB35_esp_nn_max_pool_s8_esp32s3: # 0x451 +# Part of loop body line 8, head labeled .Lt_0_28674 + l32i a10,a1,92 # [0] gra_spill_temp_22 + l32i a14,a1,72 # [1] gra_spill_temp_17 + add.n a10,a10,a8 # [2] + mull a10,a11,a10 # [3] + add.n a14,a10,a14 # [5] + +.Lt_0_29442: # 0x45e + add.n a14,a14,a11 # [0] + addi.n a13,a13,1 # [1] + bge a6,a7,.Lt_0_29698 # [2] + +.LBB38_esp_nn_max_pool_s8_esp32s3: # 0x465 + l32i a3,a1,24 # [0] gra_spill_temp_5 + l32i a2,a1,32 # [1] gra_spill_temp_7 + add.n a3,a3,a10 # [2] + mull a3,a3,a5 # [3] + l32i a4,a1,28 # [4] gra_spill_temp_6 + add.n a2,a2,a3 # [5] + add.n a2,a12,a2 # [6] + loopgtz a4,.LBB108_esp_nn_max_pool_s8_esp32s3 # [7] + + ee.vldbc.32 q0,a2 # [0*II+0] id:489 + add.n a2,a2,a5 # [0*II+1] + ee.vmax.s8 q1,q1,q0 # [0*II+2] +.LBB108_esp_nn_max_pool_s8_esp32s3: # 0x482 + +.Lt_0_29698: # 0x482 + add.n a10,a10,a11 # [0] + bne a15,a13,.Lt_0_29442 # [1] + +.Lt_0_28930: # 0x487 +# Part of loop body line 8, head labeled .Lt_0_28674 + l32i a9,a1,12 # [0] gra_spill_temp_2 + l32i a8,a1,16 # [1] gra_spill_temp_3 + l32i a10,a1,32 # [3] gra_spill_temp_7 + + ee.vmin.s8 q5,q1,q4 # [4] + ee.vmax.s8 q5,q5,q5 # [5] + addi.n a10,a10,4 # [6] + ee.movi.32.a q5,a13,0 + s32i a10,a1,32 # [9] gra_spill_temp_7 + s32i.n a13,a8,0 # [10] id:492 + addi.n a8,a8,4 # [11] + s32i a8,a1,16 # [12] gra_spill_temp_3 + blt a8,a9,.Lt_0_28674 # [13] + +.Lt_0_28162: # 0x4ad +# Part of loop body line 109, head labeled .Lt_0_27906 + l32i a13,a1,84 # [0] gra_spill_temp_20 + l32i a14,a1,80 # [1] gra_spill_temp_19 + l32i a10,a1,120 # [2] stride_wd + l32i a8,a1,88 # [3] gra_spill_temp_21 + l32i a9,a1,76 # [4] gra_spill_temp_18 + add.n a8,a8,a5 # [5] + s32i a8,a1,88 # [6] gra_spill_temp_21 + sub a9,a9,a10 # [7] + add.n a14,a14,a10 # [8] + sub a13,a13,a10 # [9] + s32i a13,a1,84 # [10] gra_spill_temp_20 + s32i a14,a1,80 # [11] gra_spill_temp_19 + s32i a9,a1,76 # [12] gra_spill_temp_18 + l32i a14,a1,64 # [13] gra_spill_temp_15 + l32i a8,a1,4 # [14] gra_spill_temp_0 + addi.n a14,a14,1 # [15] + s32i a14,a1,64 # [16] gra_spill_temp_15 + sub a14,a14,a8 # [17] + bnez a14,.Lt_0_27906 # [18] + +.Lt_0_27394: # 0x4e3 +# Part of loop body line 107, head labeled .Lt_0_27138 + l32i a8,a1,44 # [0] gra_spill_temp_10 + l32i a15,a1,92 # [1] gra_spill_temp_22 + l32i a10,a1,60 # [2] gra_spill_temp_14 + l32i a14,a1,124 # [3] stride_ht + l32i a13,a1,48 # [4] gra_spill_temp_11 + l32i a9,a1,52 # [5] gra_spill_temp_12 + sub a13,a13,a14 # [6] + add.n a9,a9,a10 # [7] + add.n a15,a15,a14 # [8] + sub a8,a8,a14 # [9] + s32i a8,a1,44 # [10] gra_spill_temp_10 + s32i a15,a1,92 # [11] gra_spill_temp_22 + s32i a9,a1,52 # [12] gra_spill_temp_12 + s32i a13,a1,48 # [13] gra_spill_temp_11 + l32i.n a9,a1,36 # [14] gra_spill_temp_8 + l32i a10,a1,68 # [15] gra_spill_temp_16 + addi.n a9,a9,1 # [16] + s32i.n a9,a1,36 # [17] gra_spill_temp_8 + sub a9,a9,a10 # [18] + bnez a9,.Lt_0_27138 # [19] + + retw.n # [0] // exit + + .size esp_nn_max_pool_s8_esp32s3, . - esp_nn_max_pool_s8_esp32s3 + +#elif defined(WIO_TERMINAL) +// dummy code, added for old ARM toolchain +.syntax unified +.thumb +.cpu cortex-m0 + +.section .text +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN && EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN_S3 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/esp_nn_softmax_ansi.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/esp_nn_softmax_ansi.c new file mode 100644 index 0000000..219f3c0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/esp_nn_softmax_ansi.c @@ -0,0 +1,92 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "softmax_common.h" + +int32_t esp_nn_get_softmax_scratch_size_ansi(const int32_t width, const int32_t height) +{ + (void) width; + (void) height; + return 0; +} + +void esp_nn_set_softmax_scratch_buf_ansi(void *buffer) +{ + (void) buffer; + return; +} + +void esp_nn_softmax_s8_ansi(const int8_t *input_data, + const int32_t height, + const int32_t width, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output_data) +{ + // The representation chosen for the input to the exp() function is Q5.26. + // We need to leave extra space since values that we skip might be as large as + // -32 before multiplying by input mult, and therefore as large as + // -16 afterwards. Note that exp(-8) is definitely not insignificant to + // accumulation, but exp(-16) definitely is. +#define ACCUM_BITS 12 +#define DIFF_BITS 5 + + const int32_t mask = (1 << shift); + int32_t col = 0; + const int8_t *in_ptr = input_data; + int8_t *out_ptr = output_data; + + for (int row_idx = 0; row_idx < height; row_idx++) { + int8_t max_in_row = in_ptr[0]; + for (col = 1; col < width; col++) { + max_in_row = max(max_in_row, in_ptr[col]); + } + + int32_t input_diff = 0; + int32_t sum_of_exps = 0; + + for (col = 0; col < width; col++) { + input_diff = in_ptr[col] - max_in_row; + if (input_diff >= diff_min) { + const int32_t input_diff_rescaled = SAT_HIGH_MUL(input_diff * mask, mult); + const int32_t exp_raw = esp_nn_exp_on_negative_values(input_diff_rescaled); + sum_of_exps += DIV_POW2(exp_raw, ACCUM_BITS); + } + } + + const int32_t headroom_plus1 = esp_nn_clz32((uint32_t) sum_of_exps); + const int32_t shifted_scale = ONE_OVER_ONE_X((sum_of_exps << headroom_plus1) - (1 << 31)); + const int32_t bits_over_unit = ACCUM_BITS - headroom_plus1 + 31 - sizeof(int8_t) * 8; + + for (col = 0; col < width; col++) { + input_diff = in_ptr[col] - max_in_row; + if (input_diff >= diff_min) { + const int32_t input_diff_rescaled = SAT_HIGH_MUL(input_diff * mask, mult); + const int32_t exp_raw = esp_nn_exp_on_negative_values(input_diff_rescaled); + const int32_t shifted_output = SAT_HIGH_MUL(shifted_scale, exp_raw); + const int32_t result = DIV_POW2(shifted_output, bits_over_unit) - 128; + out_ptr[col] = (int8_t) esp_nn_saturate8(result); + } else { + out_ptr[col] = -128; + } + } + in_ptr += width; + out_ptr += width; + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/esp_nn_softmax_opt.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/esp_nn_softmax_opt.c new file mode 100644 index 0000000..8d001eb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/esp_nn_softmax_opt.c @@ -0,0 +1,112 @@ +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN +// Copyright 2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "softmax_common.h" +#include + +static int32_t *scratch_buf = NULL; + +/** + * @brief Get scratch buffer size needed by softmax function + * + * @param width + * @param height + * @return size in bytes + * + * @note buffer must be 4 byte aligned + */ +int32_t esp_nn_get_softmax_scratch_size_opt(const int32_t width, const int32_t height) +{ + (void) height; + return width * 4; +} + +/** + * @brief Set scratch buffer to be used by softmax function + * + * @param buffer this can be NULL if one needs to unset it + * must be aligned to 4 bytes + */ +void esp_nn_set_softmax_scratch_buf_opt(void *buffer) +{ + scratch_buf = (int32_t *) buffer; +} + +void esp_nn_softmax_s8_opt(const int8_t *input_data, + const int32_t height, + const int32_t width, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output_data) +{ + if (scratch_buf == NULL) { + printf("%s error! scratch buffer not set\n", __FUNCTION__); + return; + } + // The representation chosen for the input to the exp() function is Q5.26. + // We need to leave extra space since values that we skip might be as large as + // -32 before multiplying by input mult, and therefore as large as + // -16 afterwards. Note that exp(-8) is definitely not insignificant to + // accumulation, but exp(-16) definitely is. +#define ACCUM_BITS 12 +#define DIFF_BITS 5 + + const int32_t mask = (1 << shift); + int32_t col = 0; + const int8_t *in_ptr = input_data; + int8_t *out_ptr = output_data; + + for (int row_idx = 0; row_idx < height; row_idx++) { + int8_t max_in_row = in_ptr[0]; + for (col = 1; col < width; col++) { + max_in_row = max(max_in_row, in_ptr[col]); + } + + int32_t input_diff = 0; + int32_t sum_of_exps = 0; + + for (col = 0; col < width; col++) { + input_diff = in_ptr[col] - max_in_row; + if (input_diff >= diff_min) { + const int32_t input_diff_rescaled = SAT_HIGH_MUL(input_diff * mask, mult); + const int32_t exp_raw = esp_nn_exp_on_negative_values(input_diff_rescaled); + scratch_buf[col] = exp_raw; // store to avoid duplicate calculation later + sum_of_exps += DIV_POW2(exp_raw, ACCUM_BITS); + } + } + + const int32_t headroom_plus1 = esp_nn_clz32((uint32_t) sum_of_exps); + const int32_t shifted_scale = ONE_OVER_ONE_X((sum_of_exps << headroom_plus1) - (1 << 31)); + const int32_t bits_over_unit = ACCUM_BITS - headroom_plus1 + 31 - sizeof(int8_t) * 8; + + for (col = 0; col < width; col++) { + input_diff = in_ptr[col] - max_in_row; + if (input_diff >= diff_min) { + int32_t exp_raw = scratch_buf[col]; + const int32_t shifted_output = SAT_HIGH_MUL(shifted_scale, exp_raw); + const int32_t result = DIV_POW2(shifted_output, bits_over_unit) - 128; + out_ptr[col] = (int8_t) esp_nn_saturate8(result); + } else { + out_ptr[col] = -128; + } + } + in_ptr += width; + out_ptr += width; + } +} + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/softmax_common.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/softmax_common.h new file mode 100644 index 0000000..6d1847a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ESP-NN/src/softmax/softmax_common.h @@ -0,0 +1,104 @@ +// Copyright 2022 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include + +#define MASK_IF_ZERO(x) (x) == 0 ? ~0 : 0 +#define MASK_IF_NON_ZERO(x) (x) != 0 ? ~0 : 0 +#define SELECT_USING_MASK(mask, a, b) ((mask) & (a)) ^ (~(mask) & (b)) +#define SAT_HIGH_MUL(x, y) esp_nn_sat_round_doubling_high_mul((x), (y)) +#define DIV_POW2(x,y) esp_nn_div_by_power_of_two((x), (y)) + +__NN_FORCE_INLINE__ int32_t mul_power_of_2(int val, int exp) +{ + const int32_t thresh = ((1 << (31 - exp)) - 1); + int32_t result = val << exp; + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val > thresh), INT32_MAX, result); + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val < -thresh), INT32_MIN, result); + return result; +} + +/** + * @brief Calculate `1 / (1 + x)` for x in [0, 1] + * + * @param val input value to calculate `1/(1+x)` for + * @return `int32_t` result + * @note Newton-Raphson division + * + * https://en.wikipedia.org/wiki/Division_algorithm#Newton.E2.80.93Raphson_division + * Refer to that page for the logic behind the 48/17 and 32/17 constants. + * Pseudocode: https://en.wikipedia.org/wiki/Division_algorithm#Pseudocode + */ +__NN_FORCE_INLINE__ int32_t esp_nn_one_over_one_plus_x_for_x_in_0_1(int32_t val) +{ + const int64_t sum = (int64_t) val + INT32_MAX; + const int32_t half_denominator = (int32_t) ((sum + (sum >= 0 ? 1 : -1)) / 2L); + int32_t constant_48_over_17 = 1515870810; + int32_t constant_neg_32_over_17 = -1010580540; + int32_t x = constant_48_over_17 + SAT_HIGH_MUL(half_denominator, constant_neg_32_over_17); + const int32_t fixed_2_one = (1 << 29); + + x += mul_power_of_2(SAT_HIGH_MUL(x, fixed_2_one - SAT_HIGH_MUL(half_denominator, x)), 2); + x += mul_power_of_2(SAT_HIGH_MUL(x, fixed_2_one - SAT_HIGH_MUL(half_denominator, x)), 2); + x += mul_power_of_2(SAT_HIGH_MUL(x, fixed_2_one - SAT_HIGH_MUL(half_denominator, x)), 2); + + return mul_power_of_2(x, 1); +} + +#define ONE_OVER_ONE_X(x) esp_nn_one_over_one_plus_x_for_x_in_0_1((x)) + +/** + * @brief Return exp(x) for x < 0. + * + */ +__NN_FORCE_INLINE__ int32_t esp_nn_exp_on_negative_values(int32_t val) +{ + int32_t shift = 24; + + const int32_t one_quarter = (1 << shift); + int32_t mask = one_quarter - 1; + const int32_t val_mod_minus_quarter = (val & mask) - one_quarter; + const int32_t remainder = val_mod_minus_quarter - val; + + // calculate exponent for x in [-1/4, 0) in `result` + const int32_t x = (val_mod_minus_quarter << 5) + (1 << 28); + const int32_t x2 = SAT_HIGH_MUL(x, x); + const int32_t x3 = SAT_HIGH_MUL(x2, x); + const int32_t x4 = SAT_HIGH_MUL(x2, x2); + const int32_t one_over_3 = 715827883; + const int32_t one_over_8 = 1895147668; + + const int32_t x4_over_4 = DIV_POW2(x4, 2); + const int32_t x4_over_4_plus_x3_over_6_plus_x2_over_2 = DIV_POW2(SAT_HIGH_MUL(x4_over_4 + x3, one_over_3) + x2, 1); + int32_t result = one_over_8 + SAT_HIGH_MUL(one_over_8, x + x4_over_4_plus_x3_over_6_plus_x2_over_2); + +#define SELECT_IF_NON_ZERO(x) { \ + mask = MASK_IF_NON_ZERO(remainder & (1 << shift++)); \ + result = SELECT_USING_MASK(mask, SAT_HIGH_MUL(result, x), result); \ +} + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mask = MASK_IF_ZERO(val); + return SELECT_USING_MASK(mask, INT32_MAX, result); +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/debug_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/debug_log.cpp new file mode 100644 index 0000000..be789c9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/debug_log.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_ESPRESSIF == 1 + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include +#include + +// On mbed platforms, we set up a serial port and write to it for debug logging. +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 +void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_ESPRESSIF diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ei_classifier_porting.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ei_classifier_porting.cpp new file mode 100644 index 0000000..840ebe6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/espressif/ei_classifier_porting.cpp @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_ESPRESSIF == 1 + +#include +#include +#include +#include +// Include FreeRTOS for delay +#include +#include + +// for millis and micros +#include "esp_timer.h" +#include "esp_idf_version.h" + +// memory handling +#include "esp_heap_caps.h" + +#define EI_WEAK_FN __attribute__((weak)) + +EI_WEAK_FN EI_IMPULSE_ERROR ei_run_impulse_check_canceled() { + return EI_IMPULSE_OK; +} + +EI_WEAK_FN EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + vTaskDelay(time_ms / portTICK_RATE_MS); + return EI_IMPULSE_OK; +} + +uint64_t ei_read_timer_ms() { + return esp_timer_get_time()/1000; +} + +uint64_t ei_read_timer_us() { + return esp_timer_get_time(); +} + +void ei_putchar(char c) +{ + /* Send char to serial output */ + putchar(c); +} + +/** + * Printf function uses vsnprintf and output using USB Serial + */ +__attribute__((weak)) void ei_printf(const char *format, ...) { + static char print_buf[1024] = { 0 }; + + va_list args; + va_start(args, format); + int r = vsnprintf(print_buf, sizeof(print_buf), format, args); + va_end(args); + + if (r > 0) { + printf(print_buf); + } +} + +__attribute__((weak)) void ei_printf_float(float f) { + ei_printf("%f", f); +} + +// we use alligned alloc instead of regular malloc +// due to https://github.com/espressif/esp-nn/issues/7 +__attribute__((weak)) void *ei_malloc(size_t size) { +#if defined(CONFIG_IDF_TARGET_ESP32S3) +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 2, 1) + return heap_caps_aligned_alloc(16, size, MALLOC_CAP_DEFAULT); +#else + return aligned_alloc(16, size); +#endif +#endif + return malloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { +#if defined(CONFIG_IDF_TARGET_ESP32S3) +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 2, 1) + return heap_caps_calloc(nitems, size, MALLOC_CAP_DEFAULT); +#else + void *p; + p = aligned_alloc(16, nitems * size); + if (p == nullptr) + return p; + + memset(p, '\0', nitems * size); + return p; +#endif +#endif + return calloc(nitems, size); +} + +__attribute__((weak)) void ei_free(void *ptr) { + free(ptr); +} + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif +__attribute__((weak)) void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_ESPRESSIF == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/CMakeLists.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/CMakeLists.txt new file mode 100644 index 0000000..d6e8030 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/CMakeLists.txt @@ -0,0 +1,96 @@ +# +# Copyright (c) 2019-2021 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +cmake_minimum_required(VERSION 3.15.6) + +project(ethosu_core_driver VERSION 0.0.1) + +# +# Build options +# + +option(DRIVER_PMU_AUTOINIT "Enable PMU boot auto-initialization" OFF) + +set(CMSIS_PATH "${CMAKE_CURRENT_SOURCE_DIR}/../cmsis" CACHE PATH "Path to CMSIS.") + +set(LOG_NAMES err warning info debug) +set(ETHOSU_LOG_SEVERITY "warning" CACHE STRING "Driver log severity level ${LOG_NAMES} (Defaults to 'warning')") +set(ETHOSU_TARGET_NPU_CONFIG "ethos-u55-128" CACHE STRING "Default NPU configuration") +set_property(CACHE ETHOSU_LOG_SEVERITY PROPERTY STRINGS ${LOG_NAMES}) + +# +# Global settings +# + +# Check that ETHOSU_LOG_SEVERITY has one of the supported levels +list(FIND LOG_NAMES ${ETHOSU_LOG_SEVERITY} LOG_SEVERITY) +if (${LOG_SEVERITY} EQUAL -1) + message(FATAL_ERROR "Unsupported log level ${ETHOSU_LOG_SEVERITY}") +endif() + +# Make include directories available for current- and sub projects +include_directories(include src) +include_directories(${CMSIS_PATH}/CMSIS/Core/Include) + +# +# Build libraries +# + +# Build driver library +add_library(ethosu_core_driver STATIC) +target_include_directories(ethosu_core_driver PUBLIC include) +target_sources(ethosu_core_driver PRIVATE src/ethosu_driver.c src/ethosu_pmu.c) + +string(TOLOWER ${ETHOSU_TARGET_NPU_CONFIG} ETHOSU_TARGET_NPU_CONFIG) +if(ETHOSU_TARGET_NPU_CONFIG MATCHES "^ethos-(u[0-9]+|uz)-([0-9]+$)") + set(ETHOSU_ARCH ${CMAKE_MATCH_1}) + set(ETHOSU_MACS ${CMAKE_MATCH_2}) +else() + message(FATAL_ERROR "Invalid Ethos-U target configuration '${ETHOSU_TARGET_NPU_CONFIG}") +endif() + +target_compile_definitions(ethosu_core_driver PRIVATE + ETHOSU_ARCH=${ETHOSU_ARCH} + ETHOS$) + +if (ETHOSU_ARCH STREQUAL "u55" OR ETHOSU_ARCH STREQUAL "u65") + target_sources(ethosu_core_driver PRIVATE src/ethosu_device_u55_u65.c) +else() + message(FATAL_ERROR "Invalid NPU configuration") +endif() + + +# Set the log level for the target +target_compile_definitions(ethosu_core_driver PRIVATE ETHOSU_LOG_SEVERITY=${LOG_SEVERITY}) + +# Install library and include files +install(TARGETS ethosu_core_driver LIBRARY DESTINATION "lib") +install(FILES include/ethosu_device.h include/ethosu_driver.h include/pmu_ethosu.h + DESTINATION "include") + +# +# Print build status +# + +message(STATUS "*******************************************************") +message(STATUS "PROJECT_NAME : ${PROJECT_NAME}") +message(STATUS "ETHOSU_TARGET_NPU_CONFIG : ${ETHOSU_TARGET_NPU_CONFIG}") +message(STATUS "CMAKE_SYSTEM_PROCESSOR : ${CMAKE_SYSTEM_PROCESSOR}") +message(STATUS "CMSIS_PATH : ${CMSIS_PATH}") +message(STATUS "ETHOSU_LOG_SEVERITY : ${ETHOSU_LOG_SEVERITY}") +message(STATUS "*******************************************************") \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/LICENSE.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/LICENSE.txt new file mode 100644 index 0000000..9c8f3ea --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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The driver is expected to +be cross compiled for any of the supported Arm Cortex(R)-M CPUs, which requires +the user to configure the build to match their system configuration. + + +One such requirement is to define the target CPU, normally by setting +`CMAKE_SYSTEM_PROCESSOR`. **Note** that when using the toolchain files provided +in [core_platform](https://git.mlplatform.org/ml/ethos-u/ethos-u-core-platform.git), +the variable `TARGET_CPU` must be used instead of `CMAKE_SYSTEM_PROCESSOR`. + +Target CPU is specified on the form "cortex-m", for example: +"cortex-m55+nodsp+nofp". + +Similarly the target NPU configuration is +controlled by setting `ETHOSU_TARGET_NPU_CONFIG`, for example "ethos-u55-128". + +The build configuration can be defined either in the toolchain file or +by passing options on the command line. + +```[bash] +$ cmake -B build \ + -DCMAKE_TOOLCHAIN_FILE= \ + -DCMAKE_SYSTEM_PROCESSOR=cortex-m \ + -DETHOSU_TARGET_NPU_CONFIG=ethos-u- +$ cmake --build build +``` + +or when using toolchain files from [core_platform](https://git.mlplatform.org/ml/ethos-u/ethos-u-core-platform.git) + +```[bash] +$ cmake -B build \ + -DCMAKE_TOOLCHAIN_FILE= \ + -DTARGET_CPU=cortex-m \ + -DETHOSU_TARGET_NPU_CONFIG=ethos-u- +$ cmake --build build +``` + +## Driver APIs + +The driver APIs are defined in `include/ethosu_driver.h` and the related types +in `include/ethosu_types.h`. Inferences can be invoked in two manners: +synchronously or asynchronously. The two types of invocation can be freely mixed +in a single application. + +### Synchronous invocation + +A typical usage of the driver can be the following: + +```[C] +// reserve a driver to be used (this call could block until a driver is available) +struct ethosu_driver *drv = ethosu_reserve_driver(); +... +// run one or more inferences +int result = ethosu_invoke(drv, + custom_data_ptr, + custom_data_size, + base_addr, + base_addr_size, + num_base_addr); +... +// release the driver for others to use +ethosu_release_driver(drv); +``` + +### Asynchronous invocation + +A typical usage of the driver can be the following: + +```[C] +// reserve a driver to be used (this call could block until a driver is available) +struct ethosu_driver *drv = ethosu_reserve_driver(); +... +// run one or more inferences +int result = ethosu_invoke_async(drv, + custom_data_ptr, + custom_data_size, + base_addr, + base_addr_size, + num_base_addr, + user_arg); +... +// do some other work +... +int ret; +do { + // true = blocking, false = non-blocking + // ret > 0 means inference not completed (only for non-blocking mode) + ret = ethosu_wait(drv, ); +} while(ret > 0); +... +// release the driver for others to use +ethosu_release_driver(drv); +``` + +Note that if `ethosu_wait` is invoked from a different thread and concurrently +with `ethosu_invoke_async`, the user is responsible to guarantee that +`ethosu_wait` is called after a successful completion of `ethosu_invoke_async`. +Otherwise `ethosu_wait` might fail and not actually wait for the inference +completion. + +### Driver initialization + +In order to use a driver it first needs to be initialized by calling the `init` +function, which will also register the handle in the list of available drivers. +A driver can be torn down by using the `deinit` function, which also removes the +driver from the list. + +The correct mapping is one driver per NPU device. Note that the NPUs must have +the same configuration, indeed the NPU configuration can be only one, which is +defined at compile time. + +## Implementation design + +The driver is structured in two main parts: the driver, which is responsible to +provide an unified API to the user; and the device part, which deals with the +details at the hardware level. + +In order to do its task the driver needs a device implementation. There could be +multiple device implementation for different hardware model and/or +configurations. Note that the driver can be compiled to target only one NPU +configuration by specializing the device part at compile time. + +## Data caching + +For running the driver on Arm CPUs which are configured with data cache, the +cache maintenance functions in the driver are exported with weakly linked +symbols that should be overridden. An example implementation using the CMSIS +primitives found in cachel1_armv7.h could be as below: + +```[C++] +extern "C" { +void ethosu_flush_dcache(uint32_t *p, size_t bytes) { + if (p) + SCB_CleanDCache_by_Addr(p, bytes); + else + SCB_CleanDCache(); +} + +void ethosu_invalidate_dcache(uint32_t *p, size_t bytes) { + if (p) + SCB_InvalidateDCache_by_Addr(p, bytes); + else + SCB_InvalidateDCache(); +} +} +``` + +## Mutex and semaphores + +To ensure the correct functionality of the driver mutexes and semaphores are +used internally. The default implementations of mutexes and semaphores are +designed for a single-threaded baremetal environment. Hence for integration in +environemnts where multi-threading is possible, e.g., RTOS, the user is +responsible to provide implementation for mutexes and semaphores to be used by +the driver. + +The mutex and semaphore APIs are defined as weak linked functions that can be +overridden by the user. The APIs are the usual ones and described below: + +```[C] +// create a mutex by returning back a handle +void *ethosu_mutex_create(void); +// lock the given mutex +void ethosu_mutex_lock(void *mutex); +// unlock the given mutex +void ethosu_mutex_unlock(void *mutex); + +// create a (binary) semaphore by returning back a handle +void *ethosu_semaphore_create(void); +// take from the given semaphore +void ethosu_semaphore_take(void *sem); +// give from the given semaphore +void ethosu_semaphore_give(void *sem); +``` + +## Begin/End inference callbacks + +The driver provide weak linked functions as hooks to receive callbacks whenever +an inference begins and ends. The user can override such functions when needed. +To avoid memory leaks, any allocations done in the ethosu_inference_begin() must +be balanced by a corresponding free of the memory in the ethosu_inference_end() +callback. + +```[C] +void ethosu_inference_begin(struct ethosu_driver *drv, void *user_arg); +void ethosu_inference_end(struct ethosu_driver *drv, void *user_arg); +``` + +Note that the `void *user_arg` pointer passed to invoke() function is the same +pointer passed to the begin() and end() callbacks. For example: + +```[C] +void my_function() { + ... + struct my_data data = {...}; + int result = int ethosu_invoke_v3(drv, + custom_data_ptr, + custom_data_size, + base_addr, + base_addr_size, + num_base_addr, + (void *)&data); + .... +} + +void ethosu_inference_begin(struct ethosu_driver *drv, void *user_arg) { + struct my_data *data = (struct my_data*) user_arg; + // use drv and data here +} + +void ethosu_inference_end(struct ethosu_driver *drv, void *user_arg) { + struct my_data *data = (struct my_data*) user_arg; + // use drv and data here +} +``` + +## License + +The Arm Ethos-U core driver is provided under an Apache-2.0 license. Please see +[LICENSE.txt](LICENSE.txt) for more information. + +## Contributions + +The Arm Ethos-U project welcomes contributions under the Apache-2.0 license. + +Before we can accept your contribution, you need to certify its origin and give +us your permission. For this process we use the Developer Certificate of Origin +(DCO) V1.1 (https://developercertificate.org). + +To indicate that you agree to the terms of the DCO, you "sign off" your +contribution by adding a line with your name and e-mail address to every git +commit message. You must use your real name, no pseudonyms or anonymous +contributions are accepted. If there are more than one contributor, everyone +adds their name and e-mail to the commit message. + +```[] +Author: John Doe \ +Date: Mon Feb 29 12:12:12 2016 +0000 + +Title of the commit + +Short description of the change. + +Signed-off-by: John Doe john.doe@example.org +Signed-off-by: Foo Bar foo.bar@example.org +``` + +The contributions will be code reviewed by Arm before they can be accepted into +the repository. + +In order to submit a contribution push your patch to +`ssh://@review.mlplatform.org:29418/ml/ethos-u/ethos-u-core-driver`. +To do this you will need to sign-in to +[review.mlplatform.org](https://review.mlplatform.org) using a GitHub account +and add your SSH key under your settings. If there is a problem adding the SSH +key make sure there is a valid email address in the Email Addresses field. + +## Security + +Please see [Security](SECURITY.md). + +## Trademark notice + +Arm, Cortex and Ethos are registered trademarks of Arm Limited (or its +subsidiaries) in the US and/or elsewhere. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/SECURITY.md b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/SECURITY.md new file mode 100644 index 0000000..29c6ce4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/SECURITY.md @@ -0,0 +1,85 @@ +# Security + +If you believe you have identified a security related issue or vulnerability, +then we encourage you to responsibly disclose it to us as soon as possible. + +## Reporting vulnerabilities + +Arm takes security issues seriously and welcomes feedback from researchers and +the security community in order to improve the security of its products and +services. We operate a coordinated disclosure policy for disclosing +vulnerabilities and other security issues. + +Security issues can be complex and one single timescale doesn't fit all +circumstances. We will make best endeavours to inform you when we expect +security notifications and fixes to be available and facilitate coordinated +disclosure when notifications and patches/mitigations are available. + +### Report + +For all security issues, contact Arm by email at +[arm-security@arm.com](mailto:arm-security@arm.com). In the body of the email +include as much information as possible about the issue or vulnerability and any +additional contact details. + +### Secure submission using PGP + +We support and encourage secure submission of vulnerability reports using PGP, +using the key below. If you would like replies to be encrypted, please provide +your own public key through a secure mechanism. + +~~~none +-----BEGIN PGP PUBLIC KEY BLOCK----- +mQINBFr7/RMBEACjHR5QZL/z1t2aLCRNXLE4KJiQmCo7edU5Be+7MTjIJDzZNu68 +lNEUYRoLexeayif8eC4T19bUsSbGpxHiYsFFjV8ewLXDyDJRRuaBGPfQ5rn/mE6X +Nvu+9Pputr+mB1R3CXcvrNkhmzPkK7zVM15oeyBMhogqPssuT4OeMduQdip8smfK +xTMk91RrJTLb+G3eE1tf+81kXBYvzp2e24Sn0/VeYe0IWnBobjVBZk3TmcYxDvz5 +Y47fU9V6cNj3Zq4VYrgxuLoFCA2VtetyiFQm5IYa3Bt3SWcAwihr8nbR2HoNdWyA +u8wJYYVzSq3hvT5l/IjTHxEcY+6RBq8poDSsftzvX386u9hmw7sJQFlTw6/pUjdr +gbsZ2ZzRBzKtU17ercpn4kU6VgVP3WRB5HiTFFkEpZuqAznOYaHbMq4dfd/g7Quq +C0VTbWiJnhku2i+g4BdHHRDtIF6U3aVQAfbrDb1LjVTa65p5ULOeY3HRAWtMNtu/ +Cj8cD98JDanzXtcnisds8vMQ8LZ6iMFChEnF8K4V0eLw9Ju6CMNiFYY7SEBndD/H +M4KcU4li7mROSbJcshgEbe1SYkxdMuI9eY4DNYxl3VjxoPUGzeqXo/ADFKE9bHsi +GTyEoij4ku0HspLVKnYHXn/LqHGwEcwjF8zphS+w5cn/e01akYwz5EVSQwARAQAB +tB1Bcm0gU3VwcG9ydCA8c3VwcG9ydEBhcm0uY29tPokCTgQTAQgAOBYhBN9zqDwZ +RL/vF0ihcdfNKdz4bBRiBQJa+/0TAhsDBQsJCAcCBhUKCQgLAgQWAgMBAh4BAheA +AAoJENfNKdz4bBRibK0P/jLlJR/QYypcjb+8BnHT9tCDgcV2KFYXS15VpbSNviN9 +Xs/UOnSadoGUMGCXDyb1PRNn98yUn7JlNR9rtsqPRmkpbo5cuw46ehgxjVlfcHnk +CttaE8Davx6zo0fyrBib2+oVVW8usi9+uRK4vhhPUicO3oXwzldsVFz+RbpubZxc +Bg/CZ+dQ2jMKOv1zDtInOG6OBnbQZRAeiWXgGhcIoPZ4zBQOi8nr0+bLcfvMeZi2 +uz6uKnylpXwZbl4ijcG8MKV/ei+7du+SzA9NY0WOT2g3FXDREWUhjKs8bmEZgIx4 +QgvDNpxAUThF+TqQ7zrsA8nT8POvDD0MhN/Z+A3QdPTdcaZFaXzIdxbDg+0FKmzu +OgtQBH4C01RWrkmZlhO5w7/Qjt0vLlhfyQIL9BW/HeEPtjnH2Hnq8xYnZhlVqJEh +FJU7F9sMvyiJiKviobFTd6AmpVkhxhcJ3k2L2C03imTsmUwAoejQCXwiYcOhyQ2t +Z9Nk8YIZTEw2urGFi4HSQPwPq2j/2j7ABJ4rlzJvO6vs5ppGkumvzIIP9JnpVXbp +wcbK6Ev6KdkX4s14Mzd6Hsd8LpL8t5nHhxUey6G0xKe2eSlHVm5Mlfhoete9UmIZ +dzIOZkgTgWXlYXRIxwGQ2Pss7pURtofykvLklq4jcobQuHxurl9cteodETfbWk/J +uQINBFr7/RMBEADWZG8eqt5D22g3T7ehnH/T3fuTX8LPUBnODMWGAEUY8uv64To8 +46odvrXFgWBgCf0sROEyJchc3SGLyR9S4lJsVJRde3QLN3WZkHlB4pSn4IQHFyQd +wsLQi+S9uggHMPlQ6MNvc5n0P3k5bT9fLUmtJWJ3QVjW7k963ZXpzf1zbQJqs30w +rlqGUZllfRoYQTfcYxFEaUFhwRJ//skNImWH8Vz+PTnqg2zRtFn3usrBV4GpNvsM +6jy+YEsSvUa7IY8k4wpPzEhIfqDjGbZxFSQ1H1G+mLUL+DD7oGffej/ZoC86TIdM +p6ew1rGhJdQBLh9nx+1ADOLWjNo2R0h60u7VR5q/K6V4fwWmeGFipPXZCD92I+nR +t/cjznwNyD/6J9YrBMF7mbGrS1TyfLaLt4tpdcBnsgqDTodd5OmG65mroXsg/lNO +7YZdecLZ34krfaLrWTtKkqULXbppB+uQvbVj8p8ONRImn6bZ+iAhnNaH9wJ06ico +b1F0imJ2SJWnFr6PzPRr0gPStLgu9wrRKheaORwF/H/HxSyPZxNVxFqu81q518A/ +plhub9INQLaxHf/TTjXpqZCcfdNTYUAW8rwbQfW9doSIT4lHY8bJXktb6BsVjkFj +PzDeYpXeOoTWetQqsEuTdg/F+qg041QBLtNj9Lr3Vy3StgMciRUIP8m0XwARAQAB +iQI2BBgBCAAgFiEE33OoPBlEv+8XSKFx180p3PhsFGIFAlr7/RMCGwwACgkQ180p +3PhsFGLWMA//V/XKrnI2YBh/SptUrgg7knPXva45bb7tGSH1fJg8f/wqycOSFFCY +ES45boA5jlQ3z8uw6BYCz5KeOucGhxAMw+x5EDdxZ33ksY5zqXB35WaMXzEwGYYb +E113/yhOsTbzu4bBKABSXbJO98MdAWvWpyCpp2MHIR3S9+ycM7/FMZ5xi3czZNRg +9+WZP+7W4qWhJptQ0kBh5C3N/tiltju5WQ2Y7XIn+5dMOJdtseFS7CNerxXZGAtH +nfRxaD/4ENdbWOwaVJiVW7+ioUJz09OWgy0gLYSDW+hciDnW1QAaJLpdAbniGZ0S +JsTmaZla8JnUKqZPgbFfA2OcnH9H+DWc0pHv17c5tJzTMP7rgirgGRX/U2LOzmFZ +1UxjQj5nn3Oa5frXbIAzb8xKiR0VDaquCM/3sti1AesYiS0Gw0Sqnw8qpFypgFXN +CKVgYXppIT+TmbDbNJDOB2UycxeI4vbiBwU8fI4qSpW12WsGdAJt/rx3UsyhZ+02 +4aSqDHzhJmtDPQ6lnaKe1fUkC90tgp8loVGmriWQx82jAQMqATVjIklTpE4vm00f +ocQIWOKEE90mKNEoV6rNbfl5QevmapTVdV/pmrRBzhbsa1uAUS4HZdH0Nf/OXEyv +yYCr2gCFPymkkRYhPr2w5EgbWyzLaBIwqjyIbXaveuB3DYi2Lhbf64I= +=EaN7 +-----END PGP PUBLIC KEY BLOCK----- +~~~ + +For more information visit + \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/ethosu_driver.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/ethosu_driver.h new file mode 100644 index 0000000..9c9f173 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/ethosu_driver.h @@ -0,0 +1,361 @@ +/* + * SPDX-FileCopyrightText: Copyright 2019-2023 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU_DRIVER_H +#define ETHOSU_DRIVER_H + +/****************************************************************************** + * Includes + ******************************************************************************/ + +#include "ethosu_types.h" + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * Defines + ******************************************************************************/ + +#define ETHOSU_DRIVER_VERSION_MAJOR 0 ///< Driver major version +#define ETHOSU_DRIVER_VERSION_MINOR 16 ///< Driver minor version +#define ETHOSU_DRIVER_VERSION_PATCH 0 ///< Driver patch version + +/****************************************************************************** + * Types + ******************************************************************************/ + +// Forward declare +struct ethosu_device; + +enum ethosu_job_state +{ + ETHOSU_JOB_IDLE = 0, + ETHOSU_JOB_RUNNING, + ETHOSU_JOB_DONE +}; + +struct ethosu_job +{ + volatile enum ethosu_job_state state; + const void *custom_data_ptr; + int custom_data_size; + const uint64_t *base_addr; + const size_t *base_addr_size; + int num_base_addr; + void *user_arg; +}; + +struct ethosu_driver +{ + struct ethosu_device *dev; + struct ethosu_driver *next; + struct ethosu_job job; + void *semaphore; + uint64_t fast_memory; + size_t fast_memory_size; + uint32_t power_request_counter; + bool status_error; + bool reserved; +}; + +struct ethosu_driver_version +{ + uint8_t major; + uint8_t minor; + uint8_t patch; +}; + +enum ethosu_request_clients +{ + ETHOSU_PMU_REQUEST = 0, + ETHOSU_INFERENCE_REQUEST = 1, +}; + +/****************************************************************************** + * Prototypes (weak functions in driver) + ******************************************************************************/ + +/** + * Interrupt handler to be called on IRQ from Ethos-U + * + * @param drv Pointer to driver handle + */ +void ethosu_irq_handler(struct ethosu_driver *drv); + +/** + * Flush/clean the data cache by address and size. Passing NULL as p argument + * expects the whole cache to be flushed. + * + * Addresses passed to this function must be 16 byte aligned. + * + * @param p 16 byte aligned address + * @param bytes Size of memory block in bytes + */ +void ethosu_flush_dcache(uint32_t *p, size_t bytes); + +/** + * Invalidate the data cache by address and size. Passing NULL as p argument + * expects the whole cache to be invalidated. + * + * Addresses passed to this function must be 16 byte aligned. + * + * @param p 16 byte aligned address + * @param bytes Size in bytes + */ +void ethosu_invalidate_dcache(uint32_t *p, size_t bytes); + +/** + * Minimal mutex implementation for baremetal applications. See + * ethosu_driver.c. + * + * @return Pointer to mutex handle + */ +void *ethosu_mutex_create(void); + +/** + * Minimal sempahore implementation for baremetal applications. See + * ethosu_driver.c. + * + * @return Pointer to semaphore handle + */ +void *ethosu_semaphore_create(void); + +/** + * Lock mutex. + * + * @param mutex Pointer to mutex handle + * @returns 0 on success, else negative error code + */ +int ethosu_mutex_lock(void *mutex); + +/** + * Unlock mutex. + * + * @param mutex Pointer to mutex handle + * @returns 0 on success, else negative error code + */ +int ethosu_mutex_unlock(void *mutex); + +/** + * Take semaphore. + * + * @param sem Pointer to semaphore handle + * @returns 0 on success, else negative error code + */ +int ethosu_semaphore_take(void *sem); + +/** + * Give semaphore. + * + * @param sem Pointer to semaphore handle + * @returns 0 on success, else negative error code + */ +int ethosu_semaphore_give(void *sem); + +/** + * Callback invoked just before the inference is started. + * + * @param drv Pointer to driver handle + * @param user_arg User argument provided to ethosu_invoke_*() + */ +void ethosu_inference_begin(struct ethosu_driver *drv, void *user_arg); + +/** + * Callback invoked just after the inference has completed. + * + * @param drv Pointer to driver handle + * @param user_arg User argument provided to ethosu_invoke_*() + */ +void ethosu_inference_end(struct ethosu_driver *drv, void *user_arg); + +/** + * Remapping command stream and base pointer addresses. + * + * @param address Address to be remapped. + * @param index -1 command stream, 0-n base address index + * + * @return Remapped address + */ +uint64_t ethosu_address_remap(uint64_t address, int index); + +/****************************************************************************** + * Prototypes + ******************************************************************************/ + +/** + * Initialize the Ethos-U driver. + * + * @param drv Pointer to driver handle + * @param base_address NPU register base address + * @param fast_memory Fast memory area, used for Ethos-U65 with spilling + * @param fast_memory_size Size in bytes of fast memory area + * @param secure_enable Configure NPU in secure- or non-secure mode + * @param privilege_enable Configure NPU in privileged- or non-privileged mode + * @return 0 on success, else negative error code + */ +int ethosu_init(struct ethosu_driver *drv, + void *const base_address, + const void *fast_memory, + const size_t fast_memory_size, + uint32_t secure_enable, + uint32_t privilege_enable); + +/** + * Deinitialize the Ethos-U driver. + * + * @param drv Pointer to driver handle + */ +void ethosu_deinit(struct ethosu_driver *drv); + +/** + * Soft resets the Ethos-U device. + * + * @param drv Pointer to driver handle + * @return 0 on success, else negative error code + */ +int ethosu_soft_reset(struct ethosu_driver *drv); + +/** + * Request to disable Q-channel power gating of the Ethos-U device. + * Power requests are ref.counted. Increases count. + * (Note: clock gating is made to follow power gating) + * + * @param drv Pointer to driver handle + * @return 0 on success, else negative error code + */ +int ethosu_request_power(struct ethosu_driver *drv); + +/** + * Release disable request for Q-channel power gating of the Ethos-U device. + * Power requests are ref.counted. Decreases count. + * + * @param drv Pointer to driver handle + */ +void ethosu_release_power(struct ethosu_driver *drv); + +/** + * Get Ethos-U driver version. + * + * @param ver Driver version struct + */ +void ethosu_get_driver_version(struct ethosu_driver_version *ver); + +/** + * Get Ethos-U hardware information. + * + * @param drv Pointer to driver handle + * @param hw Hardware information struct + */ +void ethosu_get_hw_info(struct ethosu_driver *drv, struct ethosu_hw_info *hw); + +/** + * Invoke command stream. + * + * @param drv Pointer to driver handle + * @param custom_data_ptr Custom data payload + * @param custom_data_size Size in bytes of custom data + * @param base_addr Array of base address pointers + * @param base_addr_size Size in bytes of each address in base_addr + * @param num_base_addr Number of elements in base_addr array + * @param user_arg User argument, will be passed to + * ethosu_inference_begin() and ethosu_inference_end() + * @return 0 on success, else negative error code + */ +int ethosu_invoke_v3(struct ethosu_driver *drv, + const void *custom_data_ptr, + const int custom_data_size, + uint64_t *const base_addr, + const size_t *base_addr_size, + const int num_base_addr, + void *user_arg); + +#define ethosu_invoke(drv, custom_data_ptr, custom_data_size, base_addr, base_addr_size, num_base_addr) \ + ethosu_invoke_v3(drv, custom_data_ptr, custom_data_size, base_addr, base_addr_size, num_base_addr, 0) + +/** + * Invoke command stream using async interface. + * Must be followed by call(s) to ethosu_wait() upon successful return. + * + * @see ethosu_invoke_v3 for documentation. + */ +int ethosu_invoke_async(struct ethosu_driver *drv, + const void *custom_data_ptr, + const int custom_data_size, + uint64_t *const base_addr, + const size_t *base_addr_size, + const int num_base_addr, + void *user_arg); + +/** + * Wait for inference to complete (block=true) + * Poll status or finish up if inference is complete (block=false) + * (This function is only intended to be used in conjuction with ethosu_invoke_async) + * + * @param drv Pointer to driver handle + * @param block If call should block if inference is running + * @return -2 on inference not invoked, -1 on inference error, 0 on success, 1 on inference running + */ +int ethosu_wait(struct ethosu_driver *drv, bool block); + +/** + * Reserves a driver to execute inference with. Call will block until a driver + * is available. + * + * @return Pointer to driver handle. + */ +struct ethosu_driver *ethosu_reserve_driver(void); + +/** + * Release driver that was previously reserved with @see ethosu_reserve_driver. + * + * @param drv Pointer to driver handle + */ +void ethosu_release_driver(struct ethosu_driver *drv); + +/** + * Static inline for backwards-compatibility. + * + * @see ethosu_invoke_v3 for documentation. + */ +static inline int ethosu_invoke_v2(const void *custom_data_ptr, + const int custom_data_size, + uint64_t *const base_addr, + const size_t *base_addr_size, + const int num_base_addr) +{ + struct ethosu_driver *drv = ethosu_reserve_driver(); + if (!drv) + { + return -1; + } + int result = ethosu_invoke_v3(drv, custom_data_ptr, custom_data_size, base_addr, base_addr_size, num_base_addr, 0); + ethosu_release_driver(drv); + return result; +} + +#ifdef __cplusplus +} +#endif + +#endif // ETHOSU_DRIVER_H diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/ethosu_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/ethosu_types.h new file mode 100644 index 0000000..a8062dd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/ethosu_types.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2019-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU_TYPES_H +#define ETHOSU_TYPES_H + +/****************************************************************************** + * Includes + ******************************************************************************/ + +#include + +/****************************************************************************** + * Types + ******************************************************************************/ + +enum ethosu_error_codes +{ + ETHOSU_SUCCESS = 0, ///< Success + ETHOSU_GENERIC_FAILURE = -1, ///< Generic failure + ETHOSU_INVALID_PARAM = -2 ///< Invalid parameter +}; + +enum ethosu_clock_q_request +{ + ETHOSU_CLOCK_Q_DISABLE = 0, ///< Disable NPU signal ready for clock off. + ETHOSU_CLOCK_Q_ENABLE = 1, ///< Enable NPU signal ready for clock off when stop+idle state reached. + ETHOSU_CLOCK_Q_UNCHANGED = 2 ///< Keep current clock q setting +}; + +enum ethosu_power_q_request +{ + ETHOSU_POWER_Q_DISABLE = 0, ///< Disable NPU signal ready for power off. + ETHOSU_POWER_Q_ENABLE = 1, ///< Enable NPU signal ready for power off when stop+idle state reached. + ETHOSU_POWER_Q_UNCHANGED = 2 ///< Keep current power q setting +}; + +struct ethosu_id +{ + uint32_t version_status; ///< Version status + uint32_t version_minor; ///< Version minor + uint32_t version_major; ///< Version major + uint32_t product_major; ///< Product major + uint32_t arch_patch_rev; ///< Architecture version patch + uint32_t arch_minor_rev; ///< Architecture version minor + uint32_t arch_major_rev; ///< Architecture version major +}; + +struct ethosu_config +{ + uint32_t macs_per_cc; ///< MACs per clock cycle + uint32_t cmd_stream_version; ///< NPU command stream version + uint32_t custom_dma; ///< Custom DMA enabled +}; + +struct ethosu_hw_info +{ + struct ethosu_id version; + struct ethosu_config cfg; +}; +#endif // ETHOSU_TYPES_H diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/pmu_ethosu.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/pmu_ethosu.h new file mode 100644 index 0000000..b717130 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/include/pmu_ethosu.h @@ -0,0 +1,326 @@ +/* + * SPDX-FileCopyrightText: Copyright 2019-2022 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PMU_ETHOSU_H +#define PMU_ETHOSU_H + +/***************************************************************************** + * Includes + *****************************************************************************/ + +#include + +#include "ethosu_driver.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************** + * Defines + *****************************************************************************/ + +#define ETHOSU_PMU_NCOUNTERS 4 + +#define ETHOSU_PMU_CNT1_Msk (1UL << 0) +#define ETHOSU_PMU_CNT2_Msk (1UL << 1) +#define ETHOSU_PMU_CNT3_Msk (1UL << 2) +#define ETHOSU_PMU_CNT4_Msk (1UL << 3) +#define ETHOSU_PMU_CCNT_Msk (1UL << 31) + +/***************************************************************************** + * Types + *****************************************************************************/ + +/** \brief HW Supported ETHOSU PMU Events + * + * Note: These values are symbolic. Actual HW-values may change. I.e. always use API + * to set/get actual event-type value. + * */ +enum ethosu_pmu_event_type +{ + ETHOSU_PMU_NO_EVENT = 0, + ETHOSU_PMU_CYCLE, + ETHOSU_PMU_NPU_IDLE, + ETHOSU_PMU_CC_STALLED_ON_BLOCKDEP, + ETHOSU_PMU_CC_STALLED_ON_SHRAM_RECONFIG, + ETHOSU_PMU_NPU_ACTIVE, + ETHOSU_PMU_MAC_ACTIVE, + ETHOSU_PMU_MAC_ACTIVE_8BIT, + ETHOSU_PMU_MAC_ACTIVE_16BIT, + ETHOSU_PMU_MAC_DPU_ACTIVE, + ETHOSU_PMU_MAC_STALLED_BY_WD_ACC, + ETHOSU_PMU_MAC_STALLED_BY_WD, + ETHOSU_PMU_MAC_STALLED_BY_ACC, + ETHOSU_PMU_MAC_STALLED_BY_IB, + ETHOSU_PMU_MAC_ACTIVE_32BIT, + ETHOSU_PMU_MAC_STALLED_BY_INT_W, + ETHOSU_PMU_MAC_STALLED_BY_INT_ACC, + ETHOSU_PMU_AO_ACTIVE, + ETHOSU_PMU_AO_ACTIVE_8BIT, + ETHOSU_PMU_AO_ACTIVE_16BIT, + ETHOSU_PMU_AO_STALLED_BY_OFMP_OB, + ETHOSU_PMU_AO_STALLED_BY_OFMP, + ETHOSU_PMU_AO_STALLED_BY_OB, + ETHOSU_PMU_AO_STALLED_BY_ACC_IB, + ETHOSU_PMU_AO_STALLED_BY_ACC, + ETHOSU_PMU_AO_STALLED_BY_IB, + ETHOSU_PMU_WD_ACTIVE, + ETHOSU_PMU_WD_STALLED, + ETHOSU_PMU_WD_STALLED_BY_WS, + ETHOSU_PMU_WD_STALLED_BY_WD_BUF, + ETHOSU_PMU_WD_PARSE_ACTIVE, + ETHOSU_PMU_WD_PARSE_STALLED, + ETHOSU_PMU_WD_PARSE_STALLED_IN, + ETHOSU_PMU_WD_PARSE_STALLED_OUT, + ETHOSU_PMU_WD_TRANS_WS, + ETHOSU_PMU_WD_TRANS_WB, + ETHOSU_PMU_WD_TRANS_DW0, + ETHOSU_PMU_WD_TRANS_DW1, + ETHOSU_PMU_AXI0_RD_TRANS_ACCEPTED, + ETHOSU_PMU_AXI0_RD_TRANS_COMPLETED, + ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_AXI0_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_AXI0_WR_TRANS_ACCEPTED, + ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_AXI0_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_AXI0_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_AXI0_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_AXI0_ENABLED_CYCLES, + ETHOSU_PMU_AXI0_RD_STALL_LIMIT, + ETHOSU_PMU_AXI0_WR_STALL_LIMIT, + ETHOSU_PMU_AXI_LATENCY_ANY, + ETHOSU_PMU_AXI_LATENCY_32, + ETHOSU_PMU_AXI_LATENCY_64, + ETHOSU_PMU_AXI_LATENCY_128, + ETHOSU_PMU_AXI_LATENCY_256, + ETHOSU_PMU_AXI_LATENCY_512, + ETHOSU_PMU_AXI_LATENCY_1024, + ETHOSU_PMU_ECC_DMA, + ETHOSU_PMU_ECC_SB0, + ETHOSU_PMU_AXI1_RD_TRANS_ACCEPTED, + ETHOSU_PMU_AXI1_RD_TRANS_COMPLETED, + ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED, + ETHOSU_PMU_AXI1_RD_TRAN_REQ_STALLED, + ETHOSU_PMU_AXI1_WR_TRANS_ACCEPTED, + ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_M, + ETHOSU_PMU_AXI1_WR_TRANS_COMPLETED_S, + ETHOSU_PMU_AXI1_WR_DATA_BEAT_WRITTEN, + ETHOSU_PMU_AXI1_WR_TRAN_REQ_STALLED, + ETHOSU_PMU_AXI1_WR_DATA_BEAT_STALLED, + ETHOSU_PMU_AXI1_ENABLED_CYCLES, + ETHOSU_PMU_AXI1_RD_STALL_LIMIT, + ETHOSU_PMU_AXI1_WR_STALL_LIMIT, + ETHOSU_PMU_ECC_SB1, + + ETHOSU_PMU_SENTINEL // End-marker (not event) +}; + +/***************************************************************************** + * Functions + *****************************************************************************/ + +/** + * \brief Enable the PMU + */ +void ETHOSU_PMU_Enable(struct ethosu_driver *drv); + +/** + * \brief Disable the PMU + */ +void ETHOSU_PMU_Disable(struct ethosu_driver *drv); + +/** + * \brief Set event to count for PMU eventer counter + * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure + * \param [in] type Event to count + */ +void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type); + +/** + * \brief Get number of PMU event counters + * \return Number of event counters + */ +uint32_t ETHOSU_PMU_Get_NumEventCounters(void); + +/** + * \brief Get event to count for PMU eventer counter + * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure + * \return type Event to count + */ +enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num); + +/** + * \brief Reset cycle counter + */ +void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv); + +/** + * \brief Reset all event counters + */ +void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv); + +/** + * \brief Enable counters + * \param [in] mask Counters to enable + * \note Enables one or more of the following: + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter (bit 31) + */ +void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask); + +/** + * \brief Disable counters + * \param [in] mask Counters to disable + * \note Disables one or more of the following: + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter (bit 31) + */ +void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask); + +/** + * \brief Determine counters activation + * + * \return Event count + * \param [in] mask Counters to enable + * \return a bitmask where bit-set means: + * - event counters activated (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter activate (bit 31) + * \note ETHOSU specific. Usage breaks CMSIS complience + */ +uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv); + +/** + * \brief Read cycle counter (64 bit) + * \return Cycle count + * \note Two HW 32-bit registers that can increment independently in-between reads. + * To work-around raciness yet still avoid turning + * off the event both are read as one value twice. If the latter read + * is not greater than the former, it means overflow of LSW without + * incrementing MSW has occurred, in which case the former value is used. + */ +uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv); + +/** + * \brief Set cycle counter (64 bit) + * \param [in] val Conter value + * \note Two HW 32-bit registers that can increment independently in-between reads. + * To work-around raciness, counter is temporary disabled if enabled. + * \note ETHOSU specific. Usage breaks CMSIS complience + */ +void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val); + +/** + * \brief Read event counter + * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) + * \return Event count + */ +uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num); + +/** + * \brief Set event counter value + * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) + * \param [in] val Conter value + * \note ETHOSU specific. Usage breaks CMSIS complience + */ +void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val); + +/** + * \brief Read counter overflow status + * \return Counter overflow status bits for the following: + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)) + * - cycle counter (bit 31) + */ +uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv); + +/** + * \brief Clear counter overflow status + * \param [in] mask Counter overflow status bits to clear + * \note Clears overflow status bits for one or more of the following: + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter (bit 31) + */ +void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask); + +/** + * \brief Enable counter overflow interrupt request + * \param [in] mask Counter overflow interrupt request bits to set + * \note Sets overflow interrupt request bits for one or more of the following: + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter (bit 31) + */ +void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask); + +/** + * \brief Disable counter overflow interrupt request + * \param [in] mask Counter overflow interrupt request bits to clear + * \note Clears overflow interrupt request bits for one or more of the following: + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter (bit 31) + */ +void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask); + +/** + * \brief Get counters overflow interrupt request stiinings + * \return mask Counter overflow interrupt request bits + * \note Sets overflow interrupt request bits for one or more of the following: + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter (bit 31) + * \note ETHOSU specific. Usage breaks CMSIS compliance + */ +uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv); + +/** + * \brief Software increment event counter + * \param [in] mask Counters to increment + * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) + * - cycle counter (bit 31) + * \note Software increment bits for one or more event counters. + */ +void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask); + +/** + * \brief Set start event number for the cycle counter + * \param [in] start_event Event to trigger start of the cycle counter + * \note Sets the event number that starts the cycle counter. + */ +void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event); + +/** + * \brief Set stop event number for the cycle counter + * \param [in] stop_event Event number + * \note Sets the event number that stops the cycle counter. + */ +void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event); + +/** + * \brief Read qread register + */ +uint32_t ETHOSU_PMU_Get_QREAD(struct ethosu_driver *drv); + +/** + * \brief Read status register + */ +uint32_t ETHOSU_PMU_Get_STATUS(struct ethosu_driver *drv); + +#ifdef __cplusplus +} +#endif + +#endif /* PMU_ETHOSU_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ehtosu_config_u65.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ehtosu_config_u65.h new file mode 100644 index 0000000..b115f43 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ehtosu_config_u65.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2019-2020,2022 Arm Limited. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU_CONFIG_H +#define ETHOSU_CONFIG_H + +/* Set default values if not manually overriden */ + +#ifndef NPU_QCONFIG +#define NPU_QCONFIG 2 +#endif + +#ifndef NPU_REGIONCFG_0 +#define NPU_REGIONCFG_0 3 +#endif + +#ifndef NPU_REGIONCFG_1 +#define NPU_REGIONCFG_1 2 +#endif + +#ifndef NPU_REGIONCFG_2 +#define NPU_REGIONCFG_2 1 +#endif + +#ifndef NPU_REGIONCFG_3 +#define NPU_REGIONCFG_3 1 +#endif + +#ifndef NPU_REGIONCFG_4 +#define NPU_REGIONCFG_4 1 +#endif + +#ifndef NPU_REGIONCFG_5 +#define NPU_REGIONCFG_5 1 +#endif + +#ifndef NPU_REGIONCFG_6 +#define NPU_REGIONCFG_6 1 +#endif + +#ifndef NPU_REGIONCFG_7 +#define NPU_REGIONCFG_7 1 +#endif + +#ifndef AXI_LIMIT0_MAX_BEATS_BYTES +#define AXI_LIMIT0_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT0_MEM_TYPE +#define AXI_LIMIT0_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT0_MAX_OUTSTANDING_READS +#define AXI_LIMIT0_MAX_OUTSTANDING_READS 64 +#endif + +#ifndef AXI_LIMIT0_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT0_MAX_OUTSTANDING_WRITES 32 +#endif + +#ifndef AXI_LIMIT1_MAX_BEATS_BYTES +#define AXI_LIMIT1_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT1_MEM_TYPE +#define AXI_LIMIT1_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT1_MAX_OUTSTANDING_READS +#define AXI_LIMIT1_MAX_OUTSTANDING_READS 64 +#endif + +#ifndef AXI_LIMIT1_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT1_MAX_OUTSTANDING_WRITES 32 +#endif + +#ifndef AXI_LIMIT2_MAX_BEATS_BYTES +#define AXI_LIMIT2_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT2_MEM_TYPE +#define AXI_LIMIT2_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT2_MAX_OUTSTANDING_READS +#define AXI_LIMIT2_MAX_OUTSTANDING_READS 64 +#endif + +#ifndef AXI_LIMIT2_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT2_MAX_OUTSTANDING_WRITES 32 +#endif + +#ifndef AXI_LIMIT3_MAX_BEATS_BYTES +#define AXI_LIMIT3_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT3_MEM_TYPE +#define AXI_LIMIT3_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT3_MAX_OUTSTANDING_READS +#define AXI_LIMIT3_MAX_OUTSTANDING_READS 64 +#endif + +#ifndef AXI_LIMIT3_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT3_MAX_OUTSTANDING_WRITES 32 +#endif + +#endif /* #ifndef ETHOSU_CONFIG_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu55_interface.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu55_interface.h new file mode 100644 index 0000000..9c0d230 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu55_interface.h @@ -0,0 +1,26198 @@ + +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU55_INTERFACE_H +#define ETHOSU55_INTERFACE_H + +#ifdef __KERNEL__ +#include +#else +#include +#endif + +#if !defined(__cplusplus) || __cplusplus < 201402L +#define CONSTEXPR +#else +#define CONSTEXPR constexpr +#endif + +#ifndef __cplusplus +#define STRUCT struct +#else +#define STRUCT +#endif + +#if defined(__cplusplus) && defined(NPU_DISASSEMBLE) +#include +#include +#include +#endif + +#if defined(__cplusplus) && !defined(NPU_NAMESPACE) +#define NPU_NAMESPACE npu +#endif + +#ifdef __cplusplus +#include +#include +#endif + +#ifdef __cplusplus +namespace NPU_NAMESPACE +{ +#endif +#define NNX_ARCH_VERSION_MAJOR 1 +#define NNX_ARCH_VERSION_MINOR 1 +#define NNX_ARCH_VERSION_PATCH 0 + +// Register offsets +// +// Register subpage BASE +// +#define NPU_REG_ID 0x0000 +#define NPU_REG_STATUS 0x0004 +#define NPU_REG_CMD 0x0008 +#define NPU_REG_RESET 0x000C +#define NPU_REG_QBASE 0x0010 +#define NPU_REG_QBASE_HI 0x0014 +#define NPU_REG_QREAD 0x0018 +#define NPU_REG_QCONFIG 0x001C +#define NPU_REG_QSIZE 0x0020 +#define NPU_REG_PROT 0x0024 +#define NPU_REG_CONFIG 0x0028 +#define NPU_REG_LOCK 0x002C +#define NPU_REG_REGIONCFG 0x003C +#define NPU_REG_AXI_LIMIT0 0x0040 +#define NPU_REG_AXI_LIMIT1 0x0044 +#define NPU_REG_AXI_LIMIT2 0x0048 +#define NPU_REG_AXI_LIMIT3 0x004C +#define BASE_REGISTERS_SIZE 0x0080 + +// +// Register subpage BASE_POINTERS +// +#define NPU_REG_BASEP_BASE 0x0080 +#define NPU_REG_BASEP_ARRLEN 0x0008 +#define BASE_POINTERS_REGISTERS_SIZE 0x0100 + +// +// Register subpage DEBUG +// +#define NPU_REG_WD_STATUS 0x0100 +#define NPU_REG_MAC_STATUS 0x0104 +#define NPU_REG_AO_STATUS 0x0108 +#define NPU_REG_DMA_STATUS0 0x0110 +#define NPU_REG_DMA_STATUS1 0x0114 +#define NPU_REG_CLKFORCE 0x0140 +#define NPU_REG_DEBUG_ADDRESS 0x0144 +#define NPU_REG_DEBUG_MISC 0x0148 +#define NPU_REG_DEBUG_BLOCK 0x0150 +#define DEBUG_REGISTERS_SIZE 0x0180 + +// +// Register subpage PMU +// +#define NPU_REG_PMCR 0x0180 +#define NPU_REG_PMCNTENSET 0x0184 +#define NPU_REG_PMCNTENCLR 0x0188 +#define NPU_REG_PMOVSSET 0x018C +#define NPU_REG_PMOVSCLR 0x0190 +#define NPU_REG_PMINTSET 0x0194 +#define NPU_REG_PMINTCLR 0x0198 +#define NPU_REG_PMCCNTR 0x01A0 +#define NPU_REG_PMCCNTR_HI 0x01A4 +#define NPU_REG_PMCCNTR_CFG 0x01A8 +#define NPU_REG_PMCAXI_CHAN 0x01AC +#define PMU_REGISTERS_SIZE 0x0200 + +// +// Register subpage TSU_DEBUG +// +#define NPU_REG_KERNEL_X 0x0200 +#define NPU_REG_KERNEL_Y 0x0204 +#define NPU_REG_KERNEL_W_M1 0x0208 +#define NPU_REG_KERNEL_H_M1 0x020C +#define NPU_REG_OFM_CBLK_WIDTH_M1 0x0210 +#define NPU_REG_OFM_CBLK_HEIGHT_M1 0x0214 +#define NPU_REG_OFM_CBLK_DEPTH_M1 0x0218 +#define NPU_REG_IFM_CBLK_DEPTH_M1 0x021C +#define NPU_REG_OFM_X 0x0220 +#define NPU_REG_OFM_Y 0x0224 +#define NPU_REG_OFM_Z 0x0228 +#define NPU_REG_IFM_Z 0x022C +#define NPU_REG_PAD_TOP 0x0230 +#define NPU_REG_PAD_LEFT 0x0234 +#define NPU_REG_IFM_CBLK_WIDTH 0x0238 +#define NPU_REG_IFM_CBLK_HEIGHT 0x023C +#define NPU_REG_DMA_IFM_SRC 0x0240 +#define NPU_REG_DMA_IFM_SRC_HI 0x0244 +#define NPU_REG_DMA_IFM_DST 0x0248 +#define NPU_REG_DMA_OFM_SRC 0x024C +#define NPU_REG_DMA_OFM_DST 0x0250 +#define NPU_REG_DMA_OFM_DST_HI 0x0254 +#define NPU_REG_DMA_WEIGHT_SRC 0x0258 +#define NPU_REG_DMA_WEIGHT_SRC_HI 0x025C +#define NPU_REG_DMA_CMD_SRC 0x0260 +#define NPU_REG_DMA_CMD_SRC_HI 0x0264 +#define NPU_REG_DMA_CMD_SIZE 0x0268 +#define NPU_REG_DMA_M2M_SRC 0x026C +#define NPU_REG_DMA_M2M_SRC_HI 0x0270 +#define NPU_REG_DMA_M2M_DST 0x0274 +#define NPU_REG_DMA_M2M_DST_HI 0x0278 +#define NPU_REG_CURRENT_QREAD 0x027C +#define NPU_REG_DMA_SCALE_SRC 0x0280 +#define NPU_REG_DMA_SCALE_SRC_HI 0x0284 +#define NPU_REG_CURRENT_BLOCK 0x02B4 +#define NPU_REG_CURRENT_OP 0x02B8 +#define NPU_REG_CURRENT_CMD 0x02BC +#define TSU_DEBUG_REGISTERS_SIZE 0x02C0 + +// +// Register subpage PMU_COUNTERS +// +#define NPU_REG_PMEVCNTR_BASE 0x0300 +#define NPU_REG_PMEVCNTR_ARRLEN 0x0004 +#define NPU_REG_PMEVTYPER_BASE 0x0380 +#define NPU_REG_PMEVTYPER_ARRLEN 0x0004 +#define PMU_COUNTERS_REGISTERS_SIZE 0x0400 + +// +// Register subpage SHARED_BUFFER +// +#define NPU_REG_SHARED_BUFFER_BASE 0x0400 +#define NPU_REG_SHARED_BUFFER_ARRLEN 0x0100 +#define SHARED_BUFFER_REGISTERS_SIZE 0x0800 + +// +// Register subpage TSU_IFM +// +#define NPU_REG_IFM_PAD_TOP 0x0800 +#define NPU_REG_IFM_PAD_LEFT 0x0804 +#define NPU_REG_IFM_PAD_RIGHT 0x0808 +#define NPU_REG_IFM_PAD_BOTTOM 0x080C +#define NPU_REG_IFM_DEPTH_M1 0x0810 +#define NPU_REG_IFM_PRECISION 0x0814 +#define NPU_REG_IFM_UPSCALE 0x081C +#define NPU_REG_IFM_ZERO_POINT 0x0824 +#define NPU_REG_IFM_WIDTH0_M1 0x0828 +#define NPU_REG_IFM_HEIGHT0_M1 0x082C +#define NPU_REG_IFM_HEIGHT1_M1 0x0830 +#define NPU_REG_IFM_IB_END 0x0834 +#define NPU_REG_IFM_REGION 0x083C +#define TSU_IFM_REGISTERS_SIZE 0x0840 + +// +// Register subpage TSU_OFM +// +#define NPU_REG_OFM_WIDTH_M1 0x0844 +#define NPU_REG_OFM_HEIGHT_M1 0x0848 +#define NPU_REG_OFM_DEPTH_M1 0x084C +#define NPU_REG_OFM_PRECISION 0x0850 +#define NPU_REG_OFM_BLK_WIDTH_M1 0x0854 +#define NPU_REG_OFM_BLK_HEIGHT_M1 0x0858 +#define NPU_REG_OFM_BLK_DEPTH_M1 0x085C +#define NPU_REG_OFM_ZERO_POINT 0x0860 +#define NPU_REG_OFM_WIDTH0_M1 0x0868 +#define NPU_REG_OFM_HEIGHT0_M1 0x086C +#define NPU_REG_OFM_HEIGHT1_M1 0x0870 +#define NPU_REG_OFM_REGION 0x087C +#define TSU_OFM_REGISTERS_SIZE 0x0880 + +// +// Register subpage TSU_KERNEL +// +#define NPU_REG_KERNEL_WIDTH_M1 0x0880 +#define NPU_REG_KERNEL_HEIGHT_M1 0x0884 +#define NPU_REG_KERNEL_STRIDE 0x0888 +#define NPU_REG_ACC_FORMAT 0x0890 +#define NPU_REG_ACTIVATION 0x0894 +#define NPU_REG_ACTIVATION_MIN 0x0898 +#define NPU_REG_ACTIVATION_MAX 0x089C +#define NPU_REG_WEIGHT_REGION 0x08A0 +#define NPU_REG_SCALE_REGION 0x08A4 +#define NPU_REG_AB_START 0x08B4 +#define NPU_REG_BLOCKDEP 0x08BC +#define TSU_KERNEL_REGISTERS_SIZE 0x08C0 + +// +// Register subpage TSU_DMA +// +#define NPU_REG_DMA0_SRC_REGION 0x08C0 +#define NPU_REG_DMA0_DST_REGION 0x08C4 +#define NPU_REG_DMA0_SIZE0 0x08C8 +#define NPU_REG_DMA0_SIZE1 0x08CC +#define TSU_DMA_REGISTERS_SIZE 0x0900 + +// +// Register subpage TSU_IFM2 +// +#define NPU_REG_IFM2_BROADCAST 0x0900 +#define NPU_REG_IFM2_SCALAR 0x0904 +#define NPU_REG_IFM2_PRECISION 0x0914 +#define NPU_REG_IFM2_ZERO_POINT 0x0924 +#define NPU_REG_IFM2_WIDTH0_M1 0x0928 +#define NPU_REG_IFM2_HEIGHT0_M1 0x092C +#define NPU_REG_IFM2_HEIGHT1_M1 0x0930 +#define NPU_REG_IFM2_IB_START 0x0934 +#define NPU_REG_IFM2_REGION 0x093C +#define TSU_IFM2_REGISTERS_SIZE 0x0940 + +// +// Register subpage TSU_IFM_BASE +// +#define NPU_REG_IFM_BASE0 0x0A00 +#define NPU_REG_IFM_BASE0_HI 0x0A04 +#define NPU_REG_IFM_BASE1 0x0A08 +#define NPU_REG_IFM_BASE1_HI 0x0A0C +#define NPU_REG_IFM_BASE2 0x0A10 +#define NPU_REG_IFM_BASE2_HI 0x0A14 +#define NPU_REG_IFM_BASE3 0x0A18 +#define NPU_REG_IFM_BASE3_HI 0x0A1C +#define NPU_REG_IFM_STRIDE_X 0x0A20 +#define NPU_REG_IFM_STRIDE_X_HI 0x0A24 +#define NPU_REG_IFM_STRIDE_Y 0x0A28 +#define NPU_REG_IFM_STRIDE_Y_HI 0x0A2C +#define NPU_REG_IFM_STRIDE_C 0x0A30 +#define NPU_REG_IFM_STRIDE_C_HI 0x0A34 +#define TSU_IFM_BASE_REGISTERS_SIZE 0x0A40 + +// +// Register subpage TSU_OFM_BASE +// +#define NPU_REG_OFM_BASE0 0x0A40 +#define NPU_REG_OFM_BASE0_HI 0x0A44 +#define NPU_REG_OFM_BASE1 0x0A48 +#define NPU_REG_OFM_BASE1_HI 0x0A4C +#define NPU_REG_OFM_BASE2 0x0A50 +#define NPU_REG_OFM_BASE2_HI 0x0A54 +#define NPU_REG_OFM_BASE3 0x0A58 +#define NPU_REG_OFM_BASE3_HI 0x0A5C +#define NPU_REG_OFM_STRIDE_X 0x0A60 +#define NPU_REG_OFM_STRIDE_X_HI 0x0A64 +#define NPU_REG_OFM_STRIDE_Y 0x0A68 +#define NPU_REG_OFM_STRIDE_Y_HI 0x0A6C +#define NPU_REG_OFM_STRIDE_C 0x0A70 +#define NPU_REG_OFM_STRIDE_C_HI 0x0A74 +#define TSU_OFM_BASE_REGISTERS_SIZE 0x0A80 + +// +// Register subpage TSU_WS_BASE +// +#define NPU_REG_WEIGHT_BASE 0x0A80 +#define NPU_REG_WEIGHT_BASE_HI 0x0A84 +#define NPU_REG_WEIGHT_LENGTH 0x0A88 +#define NPU_REG_WEIGHT_LENGTH_HI 0x0A8C +#define NPU_REG_SCALE_BASE 0x0A90 +#define NPU_REG_SCALE_BASE_HI 0x0A94 +#define NPU_REG_SCALE_LENGTH 0x0A98 +#define NPU_REG_SCALE_LENGTH_HI 0x0A9C +#define NPU_REG_OFM_SCALE 0x0AA0 +#define NPU_REG_OFM_SCALE_SHIFT 0x0AA4 +#define NPU_REG_OPA_SCALE 0x0AA8 +#define NPU_REG_OPA_SCALE_SHIFT 0x0AAC +#define NPU_REG_OPB_SCALE 0x0AB0 +#define TSU_WS_BASE_REGISTERS_SIZE 0x0AC0 + +// +// Register subpage TSU_DMA_BASE +// +#define NPU_REG_DMA0_SRC 0x0AC0 +#define NPU_REG_DMA0_SRC_HI 0x0AC4 +#define NPU_REG_DMA0_DST 0x0AC8 +#define NPU_REG_DMA0_DST_HI 0x0ACC +#define NPU_REG_DMA0_LEN 0x0AD0 +#define NPU_REG_DMA0_LEN_HI 0x0AD4 +#define TSU_DMA_BASE_REGISTERS_SIZE 0x0B00 + +// +// Register subpage TSU_IFM2_BASE +// +#define NPU_REG_IFM2_BASE0 0x0B00 +#define NPU_REG_IFM2_BASE0_HI 0x0B04 +#define NPU_REG_IFM2_BASE1 0x0B08 +#define NPU_REG_IFM2_BASE1_HI 0x0B0C +#define NPU_REG_IFM2_BASE2 0x0B10 +#define NPU_REG_IFM2_BASE2_HI 0x0B14 +#define NPU_REG_IFM2_BASE3 0x0B18 +#define NPU_REG_IFM2_BASE3_HI 0x0B1C +#define NPU_REG_IFM2_STRIDE_X 0x0B20 +#define NPU_REG_IFM2_STRIDE_X_HI 0x0B24 +#define NPU_REG_IFM2_STRIDE_Y 0x0B28 +#define NPU_REG_IFM2_STRIDE_Y_HI 0x0B2C +#define NPU_REG_IFM2_STRIDE_C 0x0B30 +#define NPU_REG_IFM2_STRIDE_C_HI 0x0B34 +#define TSU_IFM2_BASE_REGISTERS_SIZE 0x0B40 + +// +// Register subpage TSU_WS1_BASE +// +#define TSU_WS1_BASE_REGISTERS_SIZE 0x0B80 + +// +// Register subpage TSU_USER_BASE +// +#define NPU_REG_USER_DEFINED_BASE 0x0B80 +#define NPU_REG_USER_DEFINED_ARRLEN 0x0008 +#define TSU_USER_BASE_REGISTERS_SIZE 0x0BC0 + +// +// Register subpage TSU_DMA_EBASE +// +#define TSU_DMA_EBASE_REGISTERS_SIZE 0x0C00 + +// +// Register subpage ID +// +#define NPU_REG_REVISION 0x0FC0 +#define NPU_REG_PID4 0x0FD0 +#define NPU_REG_PID5 0x0FD4 +#define NPU_REG_PID6 0x0FD8 +#define NPU_REG_PID7 0x0FDC +#define NPU_REG_PID0 0x0FE0 +#define NPU_REG_PID1 0x0FE4 +#define NPU_REG_PID2 0x0FE8 +#define NPU_REG_PID3 0x0FEC +#define NPU_REG_CID0 0x0FF0 +#define NPU_REG_CID1 0x0FF4 +#define NPU_REG_CID2 0x0FF8 +#define NPU_REG_CID3 0x0FFC +#define ID_REGISTERS_SIZE 0x1000 + +#ifdef __cplusplus +// Enum types +enum class acc_format : uint8_t +{ + I32 = 0, + I40 = 1, + F16 = 2, +}; + +enum class activation_clip_range : uint8_t +{ + OFM_PRECISION = 0, + FORCE_UINT8 = 2, + FORCE_INT8 = 3, + FORCE_INT16 = 5, +}; + +enum class activation_format : uint8_t +{ + NHWC = 0, + NHCWB16 = 1, +}; + +enum class activation_function : uint8_t +{ + RELU = 0, + TANH = 3, + SIGMOID = 4, + TABLE_0 = 16, + TABLE_1 = 17, + TABLE_2 = 18, + TABLE_3 = 19, + TABLE_4 = 20, + TABLE_5 = 21, + TABLE_6 = 22, + TABLE_7 = 23, +}; + +enum class activation_precision : uint8_t +{ + B8 = 0, + B16 = 1, + B32 = 2, + B64 = 3, +}; + +enum class activation_type : uint8_t +{ + UNSIGNED = 0, + SIGNED = 1, +}; + +enum class axi_mem_encoding : uint8_t +{ + DEVICE_NON_BUFFERABLE = 0, + DEVICE_BUFFERABLE = 1, + NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2, + NORMAL_NON_CACHEABLE_BUFFERABLE = 3, + WRITE_THROUGH_NO_ALLOCATE = 4, + WRITE_THROUGH_READ_ALLOCATE = 5, + WRITE_THROUGH_WRITE_ALLOCATE = 6, + WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7, + WRITE_BACK_NO_ALLOCATE = 8, + WRITE_BACK_READ_ALLOCATE = 9, + WRITE_BACK_WRITE_ALLOCATE = 10, + WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11, +}; + +enum class broadcast_mode : uint8_t +{ + DISABLE = 0, + ENABLE = 1, +}; + +enum class cmd0_opcode : uint16_t +{ + NPU_OP_STOP = 0, + NPU_OP_IRQ = 1, + NPU_OP_CONV = 2, + NPU_OP_DEPTHWISE = 3, + NPU_OP_POOL = 5, + NPU_OP_ELEMENTWISE = 6, + NPU_OP_DMA_START = 16, + NPU_OP_DMA_WAIT = 17, + NPU_OP_KERNEL_WAIT = 18, + NPU_OP_PMU_MASK = 19, + NPU_SET_IFM_PAD_TOP = 256, + NPU_SET_IFM_PAD_LEFT = 257, + NPU_SET_IFM_PAD_RIGHT = 258, + NPU_SET_IFM_PAD_BOTTOM = 259, + NPU_SET_IFM_DEPTH_M1 = 260, + NPU_SET_IFM_PRECISION = 261, + NPU_SET_IFM_UPSCALE = 263, + NPU_SET_IFM_ZERO_POINT = 265, + NPU_SET_IFM_WIDTH0_M1 = 266, + NPU_SET_IFM_HEIGHT0_M1 = 267, + NPU_SET_IFM_HEIGHT1_M1 = 268, + NPU_SET_IFM_IB_END = 269, + NPU_SET_IFM_REGION = 271, + NPU_SET_OFM_WIDTH_M1 = 273, + NPU_SET_OFM_HEIGHT_M1 = 274, + NPU_SET_OFM_DEPTH_M1 = 275, + NPU_SET_OFM_PRECISION = 276, + NPU_SET_OFM_BLK_WIDTH_M1 = 277, + NPU_SET_OFM_BLK_HEIGHT_M1 = 278, + NPU_SET_OFM_BLK_DEPTH_M1 = 279, + NPU_SET_OFM_ZERO_POINT = 280, + NPU_SET_OFM_WIDTH0_M1 = 282, + NPU_SET_OFM_HEIGHT0_M1 = 283, + NPU_SET_OFM_HEIGHT1_M1 = 284, + NPU_SET_OFM_REGION = 287, + NPU_SET_KERNEL_WIDTH_M1 = 288, + NPU_SET_KERNEL_HEIGHT_M1 = 289, + NPU_SET_KERNEL_STRIDE = 290, + NPU_SET_ACC_FORMAT = 292, + NPU_SET_ACTIVATION = 293, + NPU_SET_ACTIVATION_MIN = 294, + NPU_SET_ACTIVATION_MAX = 295, + NPU_SET_WEIGHT_REGION = 296, + NPU_SET_SCALE_REGION = 297, + NPU_SET_AB_START = 301, + NPU_SET_BLOCKDEP = 303, + NPU_SET_DMA0_SRC_REGION = 304, + NPU_SET_DMA0_DST_REGION = 305, + NPU_SET_DMA0_SIZE0 = 306, + NPU_SET_DMA0_SIZE1 = 307, + NPU_SET_IFM2_BROADCAST = 384, + NPU_SET_IFM2_SCALAR = 385, + NPU_SET_IFM2_PRECISION = 389, + NPU_SET_IFM2_ZERO_POINT = 393, + NPU_SET_IFM2_WIDTH0_M1 = 394, + NPU_SET_IFM2_HEIGHT0_M1 = 395, + NPU_SET_IFM2_HEIGHT1_M1 = 396, + NPU_SET_IFM2_IB_START = 397, + NPU_SET_IFM2_REGION = 399, +}; + +enum class cmd1_opcode : uint16_t +{ + NPU_SET_IFM_BASE0 = 0, + NPU_SET_IFM_BASE1 = 1, + NPU_SET_IFM_BASE2 = 2, + NPU_SET_IFM_BASE3 = 3, + NPU_SET_IFM_STRIDE_X = 4, + NPU_SET_IFM_STRIDE_Y = 5, + NPU_SET_IFM_STRIDE_C = 6, + NPU_SET_OFM_BASE0 = 16, + NPU_SET_OFM_BASE1 = 17, + NPU_SET_OFM_BASE2 = 18, + NPU_SET_OFM_BASE3 = 19, + NPU_SET_OFM_STRIDE_X = 20, + NPU_SET_OFM_STRIDE_Y = 21, + NPU_SET_OFM_STRIDE_C = 22, + NPU_SET_WEIGHT_BASE = 32, + NPU_SET_WEIGHT_LENGTH = 33, + NPU_SET_SCALE_BASE = 34, + NPU_SET_SCALE_LENGTH = 35, + NPU_SET_OFM_SCALE = 36, + NPU_SET_OPA_SCALE = 37, + NPU_SET_OPB_SCALE = 38, + NPU_SET_DMA0_SRC = 48, + NPU_SET_DMA0_DST = 49, + NPU_SET_DMA0_LEN = 50, + NPU_SET_IFM2_BASE0 = 128, + NPU_SET_IFM2_BASE1 = 129, + NPU_SET_IFM2_BASE2 = 130, + NPU_SET_IFM2_BASE3 = 131, + NPU_SET_IFM2_STRIDE_X = 132, + NPU_SET_IFM2_STRIDE_Y = 133, + NPU_SET_IFM2_STRIDE_C = 134, + NPU_SET_USER_DEFINED0 = 160, + NPU_SET_USER_DEFINED1 = 161, + NPU_SET_USER_DEFINED2 = 162, + NPU_SET_USER_DEFINED3 = 163, + NPU_SET_USER_DEFINED4 = 164, + NPU_SET_USER_DEFINED5 = 165, + NPU_SET_USER_DEFINED6 = 166, + NPU_SET_USER_DEFINED7 = 167, +}; + +enum class cmd_ctrl : uint8_t +{ + CMD0_CTRL = 0, + CMD1_CTRL = 1, +}; + +enum class custom_dma_cs : uint8_t +{ + DISABLE = 0, + ENABLE = 1, +}; + +enum class custom_dma : uint8_t +{ + NOT_IMPLEMENTED = 0, + IMPLEMENTED = 1, +}; + +enum class dma_fault_src : uint8_t +{ + AXI_M0 = 0, + AXI_M1 = 1, +}; + +enum class dma_region_mode : uint8_t +{ + EXTERNAL = 0, + INTERNAL = 1, +}; + +enum class dma_stride_mode : uint8_t +{ + D1 = 0, +}; + +enum class elementwise_mode : uint8_t +{ + MUL = 0, + ADD = 1, + SUB = 2, + MIN = 3, + MAX = 4, + LRELU = 5, + ABS = 6, + CLZ = 7, + SHR = 8, + SHL = 9, +}; + +enum class functional_safety : uint8_t +{ + NOT_IMPLEMENTED = 0, + IMPLEMENTED = 1, +}; + +enum class ifm2_operand_order : uint8_t +{ + ORDER_B = 0, + ORDER_A = 1, +}; + +enum class ifm_scale_mode : uint8_t +{ + OPA_OPB_16 = 0, + OPA_32 = 1, + OPB_32 = 2, +}; + +enum class ifm_upscale_mode : uint8_t +{ + NONE = 0, + NEAREST = 1, + ZEROS = 2, +}; + +enum class kernel_decomposition : uint8_t +{ + D8X8 = 0, + D4X4 = 1, +}; + +enum class kernel_dilation : uint8_t +{ + NONE = 0, + X2 = 1, +}; + +enum class max_beats : uint8_t +{ + B64 = 0, + B128 = 1, + B256 = 2, +}; + +enum class mem_attr : uint8_t +{ + AXI0_OUTSTANDING_COUNTER0 = 0, + AXI0_OUTSTANDING_COUNTER1 = 1, + AXI1_OUTSTANDING_COUNTER2 = 2, + AXI1_OUTSTANDING_COUNTER3 = 3, +}; + +enum class ofm_scale_mode : uint8_t +{ + PER_CHANNEL = 0, + GLOBAL = 1, +}; + +enum class pmu_axi_channel : uint8_t +{ + RD_CMD = 0, + RD_IFM = 1, + RD_WEIGHTS = 2, + RD_SCALE_BIAS = 3, + RD_MEM2MEM = 4, + WR_OFM = 8, + WR_MEM2MEM = 9, +}; + +enum class pmu_event : uint16_t +{ + NO_EVENT = 0, + CYCLE = 17, + NPU_IDLE = 32, + CC_STALLED_ON_BLOCKDEP = 33, + CC_STALLED_ON_SHRAM_RECONFIG = 34, + NPU_ACTIVE = 35, + MAC_ACTIVE = 48, + MAC_ACTIVE_8BIT = 49, + MAC_ACTIVE_16BIT = 50, + MAC_DPU_ACTIVE = 51, + MAC_STALLED_BY_WD_ACC = 52, + MAC_STALLED_BY_WD = 53, + MAC_STALLED_BY_ACC = 54, + MAC_STALLED_BY_IB = 55, + MAC_ACTIVE_32BIT = 56, + MAC_STALLED_BY_INT_W = 57, + MAC_STALLED_BY_INT_ACC = 58, + AO_ACTIVE = 64, + AO_ACTIVE_8BIT = 65, + AO_ACTIVE_16BIT = 66, + AO_STALLED_BY_OFMP_OB = 67, + AO_STALLED_BY_OFMP = 68, + AO_STALLED_BY_OB = 69, + AO_STALLED_BY_ACC_IB = 70, + AO_STALLED_BY_ACC = 71, + AO_STALLED_BY_IB = 72, + WD_ACTIVE = 80, + WD_STALLED = 81, + WD_STALLED_BY_WS = 82, + WD_STALLED_BY_WD_BUF = 83, + WD_PARSE_ACTIVE = 84, + WD_PARSE_STALLED = 85, + WD_PARSE_STALLED_IN = 86, + WD_PARSE_STALLED_OUT = 87, + WD_TRANS_WS = 88, + WD_TRANS_WB = 89, + WD_TRANS_DW0 = 90, + WD_TRANS_DW1 = 91, + AXI0_RD_TRANS_ACCEPTED = 128, + AXI0_RD_TRANS_COMPLETED = 129, + AXI0_RD_DATA_BEAT_RECEIVED = 130, + AXI0_RD_TRAN_REQ_STALLED = 131, + AXI0_WR_TRANS_ACCEPTED = 132, + AXI0_WR_TRANS_COMPLETED_M = 133, + AXI0_WR_TRANS_COMPLETED_S = 134, + AXI0_WR_DATA_BEAT_WRITTEN = 135, + AXI0_WR_TRAN_REQ_STALLED = 136, + AXI0_WR_DATA_BEAT_STALLED = 137, + AXI0_ENABLED_CYCLES = 140, + AXI0_RD_STALL_LIMIT = 142, + AXI0_WR_STALL_LIMIT = 143, + AXI_LATENCY_ANY = 160, + AXI_LATENCY_32 = 161, + AXI_LATENCY_64 = 162, + AXI_LATENCY_128 = 163, + AXI_LATENCY_256 = 164, + AXI_LATENCY_512 = 165, + AXI_LATENCY_1024 = 166, + ECC_DMA = 176, + ECC_SB0 = 177, + AXI1_RD_TRANS_ACCEPTED = 384, + AXI1_RD_TRANS_COMPLETED = 385, + AXI1_RD_DATA_BEAT_RECEIVED = 386, + AXI1_RD_TRAN_REQ_STALLED = 387, + AXI1_WR_TRANS_ACCEPTED = 388, + AXI1_WR_TRANS_COMPLETED_M = 389, + AXI1_WR_TRANS_COMPLETED_S = 390, + AXI1_WR_DATA_BEAT_WRITTEN = 391, + AXI1_WR_TRAN_REQ_STALLED = 392, + AXI1_WR_DATA_BEAT_STALLED = 393, + AXI1_ENABLED_CYCLES = 396, + AXI1_RD_STALL_LIMIT = 398, + AXI1_WR_STALL_LIMIT = 399, + ECC_SB1 = 433, +}; + +enum class pooling_mode : uint8_t +{ + MAX = 0, + AVERAGE = 1, + REDUCE_SUM = 2, +}; + +enum class privilege_level : uint8_t +{ + USER = 0, + PRIVILEGED = 1, +}; + +enum class round_mode : uint8_t +{ + DBL = 0, + TRUNCATE = 1, + NATURAL = 2, +}; + +enum class security_level : uint8_t +{ + SECURE = 0, + NON_SECURE = 1, +}; + +enum class state : uint8_t +{ + STOPPED = 0, + RUNNING = 1, +}; + +enum class wd_core_slice_state : uint8_t +{ + HEADER = 0, + PALETTE = 1, + WEIGHTS = 2, +}; + +enum class wd_ctrl_state : uint8_t +{ + IDLE = 0, + DRAIN = 1, + OFD_INIT = 2, + OFD_RUN = 3, +}; + +enum class weight_order : uint8_t +{ + DEPTH_FIRST = 0, + PART_KERNEL_FIRST = 1, +}; + +#else + +enum acc_format +{ + ACC_FORMAT_I32 = 0, + ACC_FORMAT_I40 = 1, + ACC_FORMAT_F16 = 2, +}; + +enum activation_clip_range +{ + ACTIVATION_CLIP_RANGE_OFM_PRECISION = 0, + ACTIVATION_CLIP_RANGE_FORCE_UINT8 = 2, + ACTIVATION_CLIP_RANGE_FORCE_INT8 = 3, + ACTIVATION_CLIP_RANGE_FORCE_INT16 = 5, +}; + +enum activation_format +{ + ACTIVATION_FORMAT_NHWC = 0, + ACTIVATION_FORMAT_NHCWB16 = 1, +}; + +enum activation_function +{ + ACTIVATION_FUNCTION_RELU = 0, + ACTIVATION_FUNCTION_TANH = 3, + ACTIVATION_FUNCTION_SIGMOID = 4, + ACTIVATION_FUNCTION_TABLE_0 = 16, + ACTIVATION_FUNCTION_TABLE_1 = 17, + ACTIVATION_FUNCTION_TABLE_2 = 18, + ACTIVATION_FUNCTION_TABLE_3 = 19, + ACTIVATION_FUNCTION_TABLE_4 = 20, + ACTIVATION_FUNCTION_TABLE_5 = 21, + ACTIVATION_FUNCTION_TABLE_6 = 22, + ACTIVATION_FUNCTION_TABLE_7 = 23, +}; + +enum activation_precision +{ + ACTIVATION_PRECISION_B8 = 0, + ACTIVATION_PRECISION_B16 = 1, + ACTIVATION_PRECISION_B32 = 2, + ACTIVATION_PRECISION_B64 = 3, +}; + +enum activation_type +{ + ACTIVATION_TYPE_UNSIGNED = 0, + ACTIVATION_TYPE_SIGNED = 1, +}; + +enum axi_mem_encoding +{ + AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE = 0, + AXI_MEM_ENCODING_DEVICE_BUFFERABLE = 1, + AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2, + AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE = 3, + AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE = 4, + AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE = 5, + AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE = 6, + AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7, + AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE = 8, + AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE = 9, + AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE = 10, + AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11, +}; + +enum broadcast_mode +{ + BROADCAST_MODE_DISABLE = 0, + BROADCAST_MODE_ENABLE = 1, +}; + +enum cmd0_opcode +{ + CMD0_OPCODE_NPU_OP_STOP = 0, + CMD0_OPCODE_NPU_OP_IRQ = 1, + CMD0_OPCODE_NPU_OP_CONV = 2, + CMD0_OPCODE_NPU_OP_DEPTHWISE = 3, + CMD0_OPCODE_NPU_OP_POOL = 5, + CMD0_OPCODE_NPU_OP_ELEMENTWISE = 6, + CMD0_OPCODE_NPU_OP_DMA_START = 16, + CMD0_OPCODE_NPU_OP_DMA_WAIT = 17, + CMD0_OPCODE_NPU_OP_KERNEL_WAIT = 18, + CMD0_OPCODE_NPU_OP_PMU_MASK = 19, + CMD0_OPCODE_NPU_SET_IFM_PAD_TOP = 256, + CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT = 257, + CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT = 258, + CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM = 259, + CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1 = 260, + CMD0_OPCODE_NPU_SET_IFM_PRECISION = 261, + CMD0_OPCODE_NPU_SET_IFM_UPSCALE = 263, + CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT = 265, + CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1 = 266, + CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1 = 267, + CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1 = 268, + CMD0_OPCODE_NPU_SET_IFM_IB_END = 269, + CMD0_OPCODE_NPU_SET_IFM_REGION = 271, + CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1 = 273, + CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1 = 274, + CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1 = 275, + CMD0_OPCODE_NPU_SET_OFM_PRECISION = 276, + CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1 = 277, + CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1 = 278, + CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1 = 279, + CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT = 280, + CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1 = 282, + CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1 = 283, + CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1 = 284, + CMD0_OPCODE_NPU_SET_OFM_REGION = 287, + CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1 = 288, + CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1 = 289, + CMD0_OPCODE_NPU_SET_KERNEL_STRIDE = 290, + CMD0_OPCODE_NPU_SET_ACC_FORMAT = 292, + CMD0_OPCODE_NPU_SET_ACTIVATION = 293, + CMD0_OPCODE_NPU_SET_ACTIVATION_MIN = 294, + CMD0_OPCODE_NPU_SET_ACTIVATION_MAX = 295, + CMD0_OPCODE_NPU_SET_WEIGHT_REGION = 296, + CMD0_OPCODE_NPU_SET_SCALE_REGION = 297, + CMD0_OPCODE_NPU_SET_AB_START = 301, + CMD0_OPCODE_NPU_SET_BLOCKDEP = 303, + CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION = 304, + CMD0_OPCODE_NPU_SET_DMA0_DST_REGION = 305, + CMD0_OPCODE_NPU_SET_DMA0_SIZE0 = 306, + CMD0_OPCODE_NPU_SET_DMA0_SIZE1 = 307, + CMD0_OPCODE_NPU_SET_IFM2_BROADCAST = 384, + CMD0_OPCODE_NPU_SET_IFM2_SCALAR = 385, + CMD0_OPCODE_NPU_SET_IFM2_PRECISION = 389, + CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT = 393, + CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1 = 394, + CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1 = 395, + CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1 = 396, + CMD0_OPCODE_NPU_SET_IFM2_IB_START = 397, + CMD0_OPCODE_NPU_SET_IFM2_REGION = 399, +}; + +enum cmd1_opcode +{ + CMD1_OPCODE_NPU_SET_IFM_BASE0 = 0, + CMD1_OPCODE_NPU_SET_IFM_BASE1 = 1, + CMD1_OPCODE_NPU_SET_IFM_BASE2 = 2, + CMD1_OPCODE_NPU_SET_IFM_BASE3 = 3, + CMD1_OPCODE_NPU_SET_IFM_STRIDE_X = 4, + CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y = 5, + CMD1_OPCODE_NPU_SET_IFM_STRIDE_C = 6, + CMD1_OPCODE_NPU_SET_OFM_BASE0 = 16, + CMD1_OPCODE_NPU_SET_OFM_BASE1 = 17, + CMD1_OPCODE_NPU_SET_OFM_BASE2 = 18, + CMD1_OPCODE_NPU_SET_OFM_BASE3 = 19, + CMD1_OPCODE_NPU_SET_OFM_STRIDE_X = 20, + CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y = 21, + CMD1_OPCODE_NPU_SET_OFM_STRIDE_C = 22, + CMD1_OPCODE_NPU_SET_WEIGHT_BASE = 32, + CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH = 33, + CMD1_OPCODE_NPU_SET_SCALE_BASE = 34, + CMD1_OPCODE_NPU_SET_SCALE_LENGTH = 35, + CMD1_OPCODE_NPU_SET_OFM_SCALE = 36, + CMD1_OPCODE_NPU_SET_OPA_SCALE = 37, + CMD1_OPCODE_NPU_SET_OPB_SCALE = 38, + CMD1_OPCODE_NPU_SET_DMA0_SRC = 48, + CMD1_OPCODE_NPU_SET_DMA0_DST = 49, + CMD1_OPCODE_NPU_SET_DMA0_LEN = 50, + CMD1_OPCODE_NPU_SET_IFM2_BASE0 = 128, + CMD1_OPCODE_NPU_SET_IFM2_BASE1 = 129, + CMD1_OPCODE_NPU_SET_IFM2_BASE2 = 130, + CMD1_OPCODE_NPU_SET_IFM2_BASE3 = 131, + CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X = 132, + CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y = 133, + CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C = 134, + CMD1_OPCODE_NPU_SET_USER_DEFINED0 = 160, + CMD1_OPCODE_NPU_SET_USER_DEFINED1 = 161, + CMD1_OPCODE_NPU_SET_USER_DEFINED2 = 162, + CMD1_OPCODE_NPU_SET_USER_DEFINED3 = 163, + CMD1_OPCODE_NPU_SET_USER_DEFINED4 = 164, + CMD1_OPCODE_NPU_SET_USER_DEFINED5 = 165, + CMD1_OPCODE_NPU_SET_USER_DEFINED6 = 166, + CMD1_OPCODE_NPU_SET_USER_DEFINED7 = 167, +}; + +enum cmd_ctrl +{ + CMD_CTRL_CMD0_CTRL = 0, + CMD_CTRL_CMD1_CTRL = 1, +}; + +enum custom_dma_cs +{ + CUSTOM_DMA_CS_DISABLE = 0, + CUSTOM_DMA_CS_ENABLE = 1, +}; + +enum custom_dma +{ + CUSTOM_DMA_NOT_IMPLEMENTED = 0, + CUSTOM_DMA_IMPLEMENTED = 1, +}; + +enum dma_fault_src +{ + DMA_FAULT_SRC_AXI_M0 = 0, + DMA_FAULT_SRC_AXI_M1 = 1, +}; + +enum dma_region_mode +{ + DMA_REGION_MODE_EXTERNAL = 0, + DMA_REGION_MODE_INTERNAL = 1, +}; + +enum dma_stride_mode +{ + DMA_STRIDE_MODE_D1 = 0, +}; + +enum elementwise_mode +{ + ELEMENTWISE_MODE_MUL = 0, + ELEMENTWISE_MODE_ADD = 1, + ELEMENTWISE_MODE_SUB = 2, + ELEMENTWISE_MODE_MIN = 3, + ELEMENTWISE_MODE_MAX = 4, + ELEMENTWISE_MODE_LRELU = 5, + ELEMENTWISE_MODE_ABS = 6, + ELEMENTWISE_MODE_CLZ = 7, + ELEMENTWISE_MODE_SHR = 8, + ELEMENTWISE_MODE_SHL = 9, +}; + +enum functional_safety +{ + FUNCTIONAL_SAFETY_NOT_IMPLEMENTED = 0, + FUNCTIONAL_SAFETY_IMPLEMENTED = 1, +}; + +enum ifm2_operand_order +{ + IFM2_OPERAND_ORDER_ORDER_B = 0, + IFM2_OPERAND_ORDER_ORDER_A = 1, +}; + +enum ifm_scale_mode +{ + IFM_SCALE_MODE_OPA_OPB_16 = 0, + IFM_SCALE_MODE_OPA_32 = 1, + IFM_SCALE_MODE_OPB_32 = 2, +}; + +enum ifm_upscale_mode +{ + IFM_UPSCALE_MODE_NONE = 0, + IFM_UPSCALE_MODE_NEAREST = 1, + IFM_UPSCALE_MODE_ZEROS = 2, +}; + +enum kernel_decomposition +{ + KERNEL_DECOMPOSITION_D8X8 = 0, + KERNEL_DECOMPOSITION_D4X4 = 1, +}; + +enum kernel_dilation +{ + KERNEL_DILATION_NONE = 0, + KERNEL_DILATION_X2 = 1, +}; + +enum max_beats +{ + MAX_BEATS_B64 = 0, + MAX_BEATS_B128 = 1, + MAX_BEATS_B256 = 2, +}; + +enum mem_attr +{ + MEM_ATTR_AXI0_OUTSTANDING_COUNTER0 = 0, + MEM_ATTR_AXI0_OUTSTANDING_COUNTER1 = 1, + MEM_ATTR_AXI1_OUTSTANDING_COUNTER2 = 2, + MEM_ATTR_AXI1_OUTSTANDING_COUNTER3 = 3, +}; + +enum ofm_scale_mode +{ + OFM_SCALE_MODE_PER_CHANNEL = 0, + OFM_SCALE_MODE_GLOBAL = 1, +}; + +enum pmu_axi_channel +{ + PMU_AXI_CHANNEL_RD_CMD = 0, + PMU_AXI_CHANNEL_RD_IFM = 1, + PMU_AXI_CHANNEL_RD_WEIGHTS = 2, + PMU_AXI_CHANNEL_RD_SCALE_BIAS = 3, + PMU_AXI_CHANNEL_RD_MEM2MEM = 4, + PMU_AXI_CHANNEL_WR_OFM = 8, + PMU_AXI_CHANNEL_WR_MEM2MEM = 9, +}; + +enum pmu_event +{ + PMU_EVENT_NO_EVENT = 0, + PMU_EVENT_CYCLE = 17, + PMU_EVENT_NPU_IDLE = 32, + PMU_EVENT_CC_STALLED_ON_BLOCKDEP = 33, + PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG = 34, + PMU_EVENT_NPU_ACTIVE = 35, + PMU_EVENT_MAC_ACTIVE = 48, + PMU_EVENT_MAC_ACTIVE_8BIT = 49, + PMU_EVENT_MAC_ACTIVE_16BIT = 50, + PMU_EVENT_MAC_DPU_ACTIVE = 51, + PMU_EVENT_MAC_STALLED_BY_WD_ACC = 52, + PMU_EVENT_MAC_STALLED_BY_WD = 53, + PMU_EVENT_MAC_STALLED_BY_ACC = 54, + PMU_EVENT_MAC_STALLED_BY_IB = 55, + PMU_EVENT_MAC_ACTIVE_32BIT = 56, + PMU_EVENT_MAC_STALLED_BY_INT_W = 57, + PMU_EVENT_MAC_STALLED_BY_INT_ACC = 58, + PMU_EVENT_AO_ACTIVE = 64, + PMU_EVENT_AO_ACTIVE_8BIT = 65, + PMU_EVENT_AO_ACTIVE_16BIT = 66, + PMU_EVENT_AO_STALLED_BY_OFMP_OB = 67, + PMU_EVENT_AO_STALLED_BY_OFMP = 68, + PMU_EVENT_AO_STALLED_BY_OB = 69, + PMU_EVENT_AO_STALLED_BY_ACC_IB = 70, + PMU_EVENT_AO_STALLED_BY_ACC = 71, + PMU_EVENT_AO_STALLED_BY_IB = 72, + PMU_EVENT_WD_ACTIVE = 80, + PMU_EVENT_WD_STALLED = 81, + PMU_EVENT_WD_STALLED_BY_WS = 82, + PMU_EVENT_WD_STALLED_BY_WD_BUF = 83, + PMU_EVENT_WD_PARSE_ACTIVE = 84, + PMU_EVENT_WD_PARSE_STALLED = 85, + PMU_EVENT_WD_PARSE_STALLED_IN = 86, + PMU_EVENT_WD_PARSE_STALLED_OUT = 87, + PMU_EVENT_WD_TRANS_WS = 88, + PMU_EVENT_WD_TRANS_WB = 89, + PMU_EVENT_WD_TRANS_DW0 = 90, + PMU_EVENT_WD_TRANS_DW1 = 91, + PMU_EVENT_AXI0_RD_TRANS_ACCEPTED = 128, + PMU_EVENT_AXI0_RD_TRANS_COMPLETED = 129, + PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED = 130, + PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED = 131, + PMU_EVENT_AXI0_WR_TRANS_ACCEPTED = 132, + PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M = 133, + PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S = 134, + PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN = 135, + PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED = 136, + PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED = 137, + PMU_EVENT_AXI0_ENABLED_CYCLES = 140, + PMU_EVENT_AXI0_RD_STALL_LIMIT = 142, + PMU_EVENT_AXI0_WR_STALL_LIMIT = 143, + PMU_EVENT_AXI_LATENCY_ANY = 160, + PMU_EVENT_AXI_LATENCY_32 = 161, + PMU_EVENT_AXI_LATENCY_64 = 162, + PMU_EVENT_AXI_LATENCY_128 = 163, + PMU_EVENT_AXI_LATENCY_256 = 164, + PMU_EVENT_AXI_LATENCY_512 = 165, + PMU_EVENT_AXI_LATENCY_1024 = 166, + PMU_EVENT_ECC_DMA = 176, + PMU_EVENT_ECC_SB0 = 177, + PMU_EVENT_AXI1_RD_TRANS_ACCEPTED = 384, + PMU_EVENT_AXI1_RD_TRANS_COMPLETED = 385, + PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED = 386, + PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED = 387, + PMU_EVENT_AXI1_WR_TRANS_ACCEPTED = 388, + PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M = 389, + PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S = 390, + PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN = 391, + PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED = 392, + PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED = 393, + PMU_EVENT_AXI1_ENABLED_CYCLES = 396, + PMU_EVENT_AXI1_RD_STALL_LIMIT = 398, + PMU_EVENT_AXI1_WR_STALL_LIMIT = 399, + PMU_EVENT_ECC_SB1 = 433, +}; + +enum pooling_mode +{ + POOLING_MODE_MAX = 0, + POOLING_MODE_AVERAGE = 1, + POOLING_MODE_REDUCE_SUM = 2, +}; + +enum privilege_level +{ + PRIVILEGE_LEVEL_USER = 0, + PRIVILEGE_LEVEL_PRIVILEGED = 1, +}; + +enum round_mode +{ + ROUND_MODE_DBL = 0, + ROUND_MODE_TRUNCATE = 1, + ROUND_MODE_NATURAL = 2, +}; + +enum security_level +{ + SECURITY_LEVEL_SECURE = 0, + SECURITY_LEVEL_NON_SECURE = 1, +}; + +enum state +{ + STATE_STOPPED = 0, + STATE_RUNNING = 1, +}; + +enum wd_core_slice_state +{ + WD_CORE_SLICE_STATE_HEADER = 0, + WD_CORE_SLICE_STATE_PALETTE = 1, + WD_CORE_SLICE_STATE_WEIGHTS = 2, +}; + +enum wd_ctrl_state +{ + WD_CTRL_STATE_IDLE = 0, + WD_CTRL_STATE_DRAIN = 1, + WD_CTRL_STATE_OFD_INIT = 2, + WD_CTRL_STATE_OFD_RUN = 3, +}; + +enum weight_order +{ + WEIGHT_ORDER_DEPTH_FIRST = 0, + WEIGHT_ORDER_PART_KERNEL_FIRST = 1, +}; + +#endif + +#ifdef NPU_DISASSEMBLE + +static const char *acc_format_str[] = { + "ACC_FORMAT_I32", + "ACC_FORMAT_I40", + "ACC_FORMAT_F16", +}; + +static const char *activation_clip_range_str[] = { + "ACTIVATION_CLIP_RANGE_OFM_PRECISION", + "****", + "ACTIVATION_CLIP_RANGE_FORCE_UINT8", + "ACTIVATION_CLIP_RANGE_FORCE_INT8", + "****", + "ACTIVATION_CLIP_RANGE_FORCE_INT16", +}; + +static const char *activation_format_str[] = { + "ACTIVATION_FORMAT_NHWC", + "ACTIVATION_FORMAT_NHCWB16", +}; + +static const char *activation_function_str[] = { + "ACTIVATION_FUNCTION_RELU", + "****", + "****", + "ACTIVATION_FUNCTION_TANH", + "ACTIVATION_FUNCTION_SIGMOID", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "ACTIVATION_FUNCTION_TABLE_0", + "ACTIVATION_FUNCTION_TABLE_1", + "ACTIVATION_FUNCTION_TABLE_2", + "ACTIVATION_FUNCTION_TABLE_3", + "ACTIVATION_FUNCTION_TABLE_4", + "ACTIVATION_FUNCTION_TABLE_5", + "ACTIVATION_FUNCTION_TABLE_6", + "ACTIVATION_FUNCTION_TABLE_7", +}; + +static const char *activation_precision_str[] = { + "ACTIVATION_PRECISION_B8", + "ACTIVATION_PRECISION_B16", + "ACTIVATION_PRECISION_B32", + "ACTIVATION_PRECISION_B64", +}; + +static const char *activation_type_str[] = { + "ACTIVATION_TYPE_UNSIGNED", + "ACTIVATION_TYPE_SIGNED", +}; + +static const char *axi_mem_encoding_str[] = { + "AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE", + "AXI_MEM_ENCODING_DEVICE_BUFFERABLE", + "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE", + "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE", + "AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE", +}; + +static const char *broadcast_mode_str[] = { + "BROADCAST_MODE_DISABLE", + "BROADCAST_MODE_ENABLE", +}; + +static const char *cmd0_opcode_str[] = { + "CMD0_OPCODE_NPU_OP_STOP", + "CMD0_OPCODE_NPU_OP_IRQ", + "CMD0_OPCODE_NPU_OP_CONV", + "CMD0_OPCODE_NPU_OP_DEPTHWISE", + "****", + "CMD0_OPCODE_NPU_OP_POOL", + "CMD0_OPCODE_NPU_OP_ELEMENTWISE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_OP_DMA_START", + "CMD0_OPCODE_NPU_OP_DMA_WAIT", + "CMD0_OPCODE_NPU_OP_KERNEL_WAIT", + "CMD0_OPCODE_NPU_OP_PMU_MASK", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM_PAD_TOP", + "CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT", + "CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT", + "CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM", + "CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1", + "CMD0_OPCODE_NPU_SET_IFM_PRECISION", + "****", + "CMD0_OPCODE_NPU_SET_IFM_UPSCALE", + "****", + "CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT", + "CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1", + "CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1", + "CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1", + "CMD0_OPCODE_NPU_SET_IFM_IB_END", + "****", + "CMD0_OPCODE_NPU_SET_IFM_REGION", + "****", + "CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1", + "CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_PRECISION", + "CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1", + "CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT", + "****", + "CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1", + "CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1", + "CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1", + "****", + "****", + "CMD0_OPCODE_NPU_SET_OFM_REGION", + "CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1", + "CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1", + "CMD0_OPCODE_NPU_SET_KERNEL_STRIDE", + "****", + "CMD0_OPCODE_NPU_SET_ACC_FORMAT", + "CMD0_OPCODE_NPU_SET_ACTIVATION", + "CMD0_OPCODE_NPU_SET_ACTIVATION_MIN", + "CMD0_OPCODE_NPU_SET_ACTIVATION_MAX", + "CMD0_OPCODE_NPU_SET_WEIGHT_REGION", + "CMD0_OPCODE_NPU_SET_SCALE_REGION", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_AB_START", + "****", + "CMD0_OPCODE_NPU_SET_BLOCKDEP", + "CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION", + "CMD0_OPCODE_NPU_SET_DMA0_DST_REGION", + "CMD0_OPCODE_NPU_SET_DMA0_SIZE0", + "CMD0_OPCODE_NPU_SET_DMA0_SIZE1", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_BROADCAST", + "CMD0_OPCODE_NPU_SET_IFM2_SCALAR", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_PRECISION", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT", + "CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1", + "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1", + "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1", + "CMD0_OPCODE_NPU_SET_IFM2_IB_START", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_REGION", +}; + +static const char *cmd1_opcode_str[] = { + "CMD1_OPCODE_NPU_SET_IFM_BASE0", + "CMD1_OPCODE_NPU_SET_IFM_BASE1", + "CMD1_OPCODE_NPU_SET_IFM_BASE2", + "CMD1_OPCODE_NPU_SET_IFM_BASE3", + "CMD1_OPCODE_NPU_SET_IFM_STRIDE_X", + "CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y", + "CMD1_OPCODE_NPU_SET_IFM_STRIDE_C", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_OFM_BASE0", + "CMD1_OPCODE_NPU_SET_OFM_BASE1", + "CMD1_OPCODE_NPU_SET_OFM_BASE2", + "CMD1_OPCODE_NPU_SET_OFM_BASE3", + "CMD1_OPCODE_NPU_SET_OFM_STRIDE_X", + "CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y", + "CMD1_OPCODE_NPU_SET_OFM_STRIDE_C", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_WEIGHT_BASE", + "CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH", + "CMD1_OPCODE_NPU_SET_SCALE_BASE", + "CMD1_OPCODE_NPU_SET_SCALE_LENGTH", + "CMD1_OPCODE_NPU_SET_OFM_SCALE", + "CMD1_OPCODE_NPU_SET_OPA_SCALE", + "CMD1_OPCODE_NPU_SET_OPB_SCALE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_DMA0_SRC", + "CMD1_OPCODE_NPU_SET_DMA0_DST", + "CMD1_OPCODE_NPU_SET_DMA0_LEN", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_IFM2_BASE0", + "CMD1_OPCODE_NPU_SET_IFM2_BASE1", + "CMD1_OPCODE_NPU_SET_IFM2_BASE2", + "CMD1_OPCODE_NPU_SET_IFM2_BASE3", + "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X", + "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y", + "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_USER_DEFINED0", + "CMD1_OPCODE_NPU_SET_USER_DEFINED1", + "CMD1_OPCODE_NPU_SET_USER_DEFINED2", + "CMD1_OPCODE_NPU_SET_USER_DEFINED3", + "CMD1_OPCODE_NPU_SET_USER_DEFINED4", + "CMD1_OPCODE_NPU_SET_USER_DEFINED5", + "CMD1_OPCODE_NPU_SET_USER_DEFINED6", + "CMD1_OPCODE_NPU_SET_USER_DEFINED7", +}; + +static const char *cmd_ctrl_str[] = { + "CMD_CTRL_CMD0_CTRL", + "CMD_CTRL_CMD1_CTRL", +}; + +static const char *custom_dma_cs_str[] = { + "CUSTOM_DMA_CS_DISABLE", + "CUSTOM_DMA_CS_ENABLE", +}; + +static const char *custom_dma_str[] = { + "CUSTOM_DMA_NOT_IMPLEMENTED", + "CUSTOM_DMA_IMPLEMENTED", +}; + +static const char *dma_fault_src_str[] = { + "DMA_FAULT_SRC_AXI_M0", + "DMA_FAULT_SRC_AXI_M1", +}; + +static const char *dma_region_mode_str[] = { + "DMA_REGION_MODE_EXTERNAL", + "DMA_REGION_MODE_INTERNAL", +}; + +static const char *dma_stride_mode_str[] = { + "DMA_STRIDE_MODE_D1", +}; + +static const char *elementwise_mode_str[] = { + "ELEMENTWISE_MODE_MUL", + "ELEMENTWISE_MODE_ADD", + "ELEMENTWISE_MODE_SUB", + "ELEMENTWISE_MODE_MIN", + "ELEMENTWISE_MODE_MAX", + "ELEMENTWISE_MODE_LRELU", + "ELEMENTWISE_MODE_ABS", + "ELEMENTWISE_MODE_CLZ", + "ELEMENTWISE_MODE_SHR", + "ELEMENTWISE_MODE_SHL", +}; + +static const char *functional_safety_str[] = { + "FUNCTIONAL_SAFETY_NOT_IMPLEMENTED", + "FUNCTIONAL_SAFETY_IMPLEMENTED", +}; + +static const char *ifm2_operand_order_str[] = { + "IFM2_OPERAND_ORDER_ORDER_B", + "IFM2_OPERAND_ORDER_ORDER_A", +}; + +static const char *ifm_scale_mode_str[] = { + "IFM_SCALE_MODE_OPA_OPB_16", + "IFM_SCALE_MODE_OPA_32", + "IFM_SCALE_MODE_OPB_32", +}; + +static const char *ifm_upscale_mode_str[] = { + "IFM_UPSCALE_MODE_NONE", + "IFM_UPSCALE_MODE_NEAREST", + "IFM_UPSCALE_MODE_ZEROS", +}; + +static const char *kernel_decomposition_str[] = { + "KERNEL_DECOMPOSITION_D8X8", + "KERNEL_DECOMPOSITION_D4X4", +}; + +static const char *kernel_dilation_str[] = { + "KERNEL_DILATION_NONE", + "KERNEL_DILATION_X2", +}; + +static const char *max_beats_str[] = { + "MAX_BEATS_B64", + "MAX_BEATS_B128", + "MAX_BEATS_B256", +}; + +static const char *mem_attr_str[] = { + "MEM_ATTR_AXI0_OUTSTANDING_COUNTER0", + "MEM_ATTR_AXI0_OUTSTANDING_COUNTER1", + "MEM_ATTR_AXI1_OUTSTANDING_COUNTER2", + "MEM_ATTR_AXI1_OUTSTANDING_COUNTER3", +}; + +static const char *ofm_scale_mode_str[] = { + "OFM_SCALE_MODE_PER_CHANNEL", + "OFM_SCALE_MODE_GLOBAL", +}; + +static const char *pmu_axi_channel_str[] = { + "PMU_AXI_CHANNEL_RD_CMD", + "PMU_AXI_CHANNEL_RD_IFM", + "PMU_AXI_CHANNEL_RD_WEIGHTS", + "PMU_AXI_CHANNEL_RD_SCALE_BIAS", + "PMU_AXI_CHANNEL_RD_MEM2MEM", + "****", + "****", + "****", + "PMU_AXI_CHANNEL_WR_OFM", + "PMU_AXI_CHANNEL_WR_MEM2MEM", +}; + +static const char *pmu_event_str[] = { + "PMU_EVENT_NO_EVENT", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_CYCLE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_NPU_IDLE", + "PMU_EVENT_CC_STALLED_ON_BLOCKDEP", + "PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG", + "PMU_EVENT_NPU_ACTIVE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_MAC_ACTIVE", + "PMU_EVENT_MAC_ACTIVE_8BIT", + "PMU_EVENT_MAC_ACTIVE_16BIT", + "PMU_EVENT_MAC_DPU_ACTIVE", + "PMU_EVENT_MAC_STALLED_BY_WD_ACC", + "PMU_EVENT_MAC_STALLED_BY_WD", + "PMU_EVENT_MAC_STALLED_BY_ACC", + "PMU_EVENT_MAC_STALLED_BY_IB", + "PMU_EVENT_MAC_ACTIVE_32BIT", + "PMU_EVENT_MAC_STALLED_BY_INT_W", + "PMU_EVENT_MAC_STALLED_BY_INT_ACC", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AO_ACTIVE", + "PMU_EVENT_AO_ACTIVE_8BIT", + "PMU_EVENT_AO_ACTIVE_16BIT", + "PMU_EVENT_AO_STALLED_BY_OFMP_OB", + "PMU_EVENT_AO_STALLED_BY_OFMP", + "PMU_EVENT_AO_STALLED_BY_OB", + "PMU_EVENT_AO_STALLED_BY_ACC_IB", + "PMU_EVENT_AO_STALLED_BY_ACC", + "PMU_EVENT_AO_STALLED_BY_IB", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_WD_ACTIVE", + "PMU_EVENT_WD_STALLED", + "PMU_EVENT_WD_STALLED_BY_WS", + "PMU_EVENT_WD_STALLED_BY_WD_BUF", + "PMU_EVENT_WD_PARSE_ACTIVE", + "PMU_EVENT_WD_PARSE_STALLED", + "PMU_EVENT_WD_PARSE_STALLED_IN", + "PMU_EVENT_WD_PARSE_STALLED_OUT", + "PMU_EVENT_WD_TRANS_WS", + "PMU_EVENT_WD_TRANS_WB", + "PMU_EVENT_WD_TRANS_DW0", + "PMU_EVENT_WD_TRANS_DW1", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AXI0_RD_TRANS_ACCEPTED", + "PMU_EVENT_AXI0_RD_TRANS_COMPLETED", + "PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED", + "PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED", + "PMU_EVENT_AXI0_WR_TRANS_ACCEPTED", + "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M", + "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S", + "PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN", + "PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED", + "PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED", + "****", + "****", + "PMU_EVENT_AXI0_ENABLED_CYCLES", + "****", + "PMU_EVENT_AXI0_RD_STALL_LIMIT", + "PMU_EVENT_AXI0_WR_STALL_LIMIT", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AXI_LATENCY_ANY", + "PMU_EVENT_AXI_LATENCY_32", + "PMU_EVENT_AXI_LATENCY_64", + "PMU_EVENT_AXI_LATENCY_128", + "PMU_EVENT_AXI_LATENCY_256", + "PMU_EVENT_AXI_LATENCY_512", + "PMU_EVENT_AXI_LATENCY_1024", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_ECC_DMA", + "PMU_EVENT_ECC_SB0", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AXI1_RD_TRANS_ACCEPTED", + "PMU_EVENT_AXI1_RD_TRANS_COMPLETED", + "PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED", + "PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED", + "PMU_EVENT_AXI1_WR_TRANS_ACCEPTED", + "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M", + "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S", + "PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN", + "PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED", + "PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED", + "****", + "****", + "PMU_EVENT_AXI1_ENABLED_CYCLES", + "****", + "PMU_EVENT_AXI1_RD_STALL_LIMIT", + "PMU_EVENT_AXI1_WR_STALL_LIMIT", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_ECC_SB1", +}; + +static const char *pooling_mode_str[] = { + "POOLING_MODE_MAX", + "POOLING_MODE_AVERAGE", + "POOLING_MODE_REDUCE_SUM", +}; + +static const char *privilege_level_str[] = { + "PRIVILEGE_LEVEL_USER", + "PRIVILEGE_LEVEL_PRIVILEGED", +}; + +static const char *round_mode_str[] = { + "ROUND_MODE_DBL", + "ROUND_MODE_TRUNCATE", + "ROUND_MODE_NATURAL", +}; + +static const char *security_level_str[] = { + "SECURITY_LEVEL_SECURE", + "SECURITY_LEVEL_NON_SECURE", +}; + +static const char *state_str[] = { + "STATE_STOPPED", + "STATE_RUNNING", +}; + +static const char *wd_core_slice_state_str[] = { + "WD_CORE_SLICE_STATE_HEADER", + "WD_CORE_SLICE_STATE_PALETTE", + "WD_CORE_SLICE_STATE_WEIGHTS", +}; + +static const char *wd_ctrl_state_str[] = { + "WD_CTRL_STATE_IDLE", + "WD_CTRL_STATE_DRAIN", + "WD_CTRL_STATE_OFD_INIT", + "WD_CTRL_STATE_OFD_RUN", +}; + +static const char *weight_order_str[] = { + "WEIGHT_ORDER_DEPTH_FIRST", + "WEIGHT_ORDER_PART_KERNEL_FIRST", +}; + +#endif + +// Register type structs +// id_r - ID register +struct id_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t version_status : 4; // This is the version of the product + uint32_t version_minor : 4; // This is the n for the P part of an RnPn release number + uint32_t version_major : 4; // This is the n for the R part of an RnPn release number + uint32_t product_major : 4; // Product major ID number (unique per base product) + uint32_t arch_patch_rev : 4; // This is the patch number of the architecture version a.b + uint32_t + arch_minor_rev : 8; // This is the minor architecture version number, b in the architecture version a.b + uint32_t + arch_major_rev : 4; // This is the major architecture version number, a in the architecture version a.b + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR id_r() : word0(269500929) {} + CONSTEXPR id_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + id_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_version_status() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + uint32_t get_version_status() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR id_r &set_version_status(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + volatile id_r &set_version_status(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_version_minor() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + uint32_t get_version_minor() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR id_r &set_version_minor(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + volatile id_r &set_version_minor(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_version_major() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 8); + return value; + } + uint32_t get_version_major() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR id_r &set_version_major(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8); + return *this; + } + volatile id_r &set_version_major(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_product_major() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + uint32_t get_product_major() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR id_r &set_product_major(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + volatile id_r &set_product_major(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_arch_patch_rev() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 16); + return value; + } + uint32_t get_arch_patch_rev() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR id_r &set_arch_patch_rev(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16); + return *this; + } + volatile id_r &set_arch_patch_rev(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_arch_minor_rev() const + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 20); + return value; + } + uint32_t get_arch_minor_rev() const volatile + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 20); + return value; + } + CONSTEXPR id_r &set_arch_minor_rev(uint32_t value) + { + word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20); + return *this; + } + volatile id_r &set_arch_minor_rev(uint32_t value) volatile + { + word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20); + return *this; + } + CONSTEXPR uint32_t get_arch_major_rev() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + uint32_t get_arch_major_rev() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + CONSTEXPR id_r &set_arch_major_rev(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } + volatile id_r &set_arch_major_rev(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } +#endif +}; + +// status_r - Register describes the current operating status of the NPU +struct status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t state : 1; // NPU state, 0 = Stopped, 1 = Running + uint32_t irq_raised : 1; // Raw IRQ status, 0 = IRQ not raised, 1 = IRQ raised. IRQ is cleared using command + // register bit 1 + uint32_t + bus_status : 1; // 0=OK, 1=Bus abort detected and processing halted (NPU will reach IDLE state and not + // to start process any more commands/AXI transactions). Can only be cleared by a reset + uint32_t reset_status : 1; // Reset is ongoing and only this register can be read (other registers read as 0 + // and writes are ignored.) A value of 0 means NPU is not being reset and can be + // accessed as normal + uint32_t + cmd_parse_error : 1; // 0=No error 1=Command stream parsing error detected. Can only be cleared by reset + uint32_t cmd_end_reached : 1; // 0=Not reached, 1=Reached. Cleared by writing QBASE or QSIZE when NPU is in + // stopped state + uint32_t pmu_irq_raised : 1; // 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command register bit 1 + uint32_t wd_fault : 1; // Weight decoder state: 0=no fault 1=weight decoder decompression fault. Can only be + // cleared by reset + uint32_t ecc_fault : 1; // ECC state for internal RAMs: 0=no fault 1=ECC fault signalled. Can only be + // cleared by reset + uint32_t reserved0 : 2; + uint32_t faulting_interface : 1; // Faulting interface on bus abort + uint32_t faulting_channel : 4; // Faulting channel on a bus abort. Read: 0=Cmd 1=IFM 2=Weights 3=Scale+Bias + // 4=Mem2Mem; Write: 8=OFM 9=Mem2Mem + uint32_t irq_history_mask : 16; // IRQ History mask + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR status_r() : word0(8) {} + CONSTEXPR status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + status_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::state get_state() const + { + NPU_NAMESPACE::state value = static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::state get_state() const volatile + { + NPU_NAMESPACE::state value = static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR status_r &set_state(NPU_NAMESPACE::state value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + volatile status_r &set_state(NPU_NAMESPACE::state value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR uint32_t get_irq_raised() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_irq_raised() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR status_r &set_irq_raised(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile status_r &set_irq_raised(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_bus_status() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_bus_status() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR status_r &set_bus_status(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile status_r &set_bus_status(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_reset_status() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_reset_status() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR status_r &set_reset_status(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile status_r &set_reset_status(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_cmd_parse_error() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_cmd_parse_error() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR status_r &set_cmd_parse_error(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile status_r &set_cmd_parse_error(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_cmd_end_reached() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_cmd_end_reached() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR status_r &set_cmd_end_reached(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile status_r &set_cmd_end_reached(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_pmu_irq_raised() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_pmu_irq_raised() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR status_r &set_pmu_irq_raised(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile status_r &set_pmu_irq_raised(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_wd_fault() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_wd_fault() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR status_r &set_wd_fault(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile status_r &set_wd_fault(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_ecc_fault() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_ecc_fault() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR status_r &set_ecc_fault(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile status_r &set_ecc_fault(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_fault_src get_faulting_interface() const + { + NPU_NAMESPACE::dma_fault_src value = static_cast(((1U << 1) - 1) & (word0 >> 11)); + return value; + } + NPU_NAMESPACE::dma_fault_src get_faulting_interface() const volatile + { + NPU_NAMESPACE::dma_fault_src value = static_cast(((1U << 1) - 1) & (word0 >> 11)); + return value; + } + CONSTEXPR status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 11); + return *this; + } + volatile status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 11); + return *this; + } + CONSTEXPR uint32_t get_faulting_channel() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + uint32_t get_faulting_channel() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR status_r &set_faulting_channel(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + volatile status_r &set_faulting_channel(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_irq_history_mask() const + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + uint32_t get_irq_history_mask() const volatile + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR status_r &set_irq_history_mask(uint32_t value) + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } + volatile status_r &set_irq_history_mask(uint32_t value) volatile + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } +#endif +}; + +// cmd_r - Command register, reads as last written command +struct cmd_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t transition_to_running_state : 1; // Write 1 to transition the NPU to running state. Writing 0 has + // no effect + uint32_t clear_irq : 1; // Write 1 to clear the IRQ status in the STATUS register. Writing 0 has no effect + uint32_t clock_q_enable : 1; // Write 1 to this bit to enable clock off using clock q-interface and enable + // the requester clock gate + uint32_t power_q_enable : 1; // Write 1 to this bit to enable power off using power q-interface + uint32_t + stop_request : 1; // Write 1 to this bit to request STOP after completing any already-started commands + uint32_t reserved0 : 11; + uint32_t clear_irq_history : 16; // Clears the IRQ history mask + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cmd_r() : word0(12) {} + CONSTEXPR cmd_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cmd_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_transition_to_running_state() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_transition_to_running_state() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR cmd_r &set_transition_to_running_state(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile cmd_r &set_transition_to_running_state(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_clear_irq() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_clear_irq() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR cmd_r &set_clear_irq(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile cmd_r &set_clear_irq(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_clock_q_enable() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_clock_q_enable() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR cmd_r &set_clock_q_enable(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile cmd_r &set_clock_q_enable(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_power_q_enable() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_power_q_enable() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR cmd_r &set_power_q_enable(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile cmd_r &set_power_q_enable(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_stop_request() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_stop_request() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR cmd_r &set_stop_request(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile cmd_r &set_stop_request(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_clear_irq_history() const + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + uint32_t get_clear_irq_history() const volatile + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR cmd_r &set_clear_irq_history(uint32_t value) + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } + volatile cmd_r &set_clear_irq_history(uint32_t value) volatile + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } +#endif +}; + +// reset_r - Request Reset and new security mode +struct reset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t pending_CPL : 1; // Current privilege level 0=User 1=Privileged + uint32_t pending_CSL : 1; // Current security level 0=Secure 1=Non secure + uint32_t reserved0 : 30; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR reset_r() : word0(0) {} + CONSTEXPR reset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + reset_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::privilege_level get_pending_CPL() const + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::privilege_level get_pending_CPL() const volatile + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + volatile reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::security_level get_pending_CSL() const + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + NPU_NAMESPACE::security_level get_pending_CSL() const volatile + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + CONSTEXPR reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } + volatile reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } +#endif +}; + +// qbase_r - Base address of the command stream in bytes +struct qbase_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR qbase_r() : word0(0), word1(0) {} + CONSTEXPR qbase_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + qbase_r copy() volatile + { + return *this; + } +#endif +}; + +// qread_r - Read offset in the command stream in bytes. Multiple of 4 in the range 0 to 16 MB +struct qread_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t QREAD : 32; // The read offset of the current command under execution + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR qread_r() : word0(0) {} + CONSTEXPR qread_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + qread_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_QREAD() const + { + uint32_t value = word0; + return value; + } + uint32_t get_QREAD() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR qread_r &set_QREAD(uint32_t value) + { + word0 = value; + return *this; + } + volatile qread_r &set_QREAD(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// qconfig_r - AXI configuration for the command stream in the range 0-3. Same encoding as for REGIONCFG +struct qconfig_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cmd_region0 : 2; // Command region configuration + uint32_t reserved0 : 30; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR qconfig_r() : word0(0) {} + CONSTEXPR qconfig_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + qconfig_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_cmd_region0() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::mem_attr get_cmd_region0() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } +#endif +}; + +// qsize_r - Size of the command stream in bytes. Multiple of 4 in the range 0 to 16 MB +struct qsize_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t QSIZE : 32; // Size of the next command stream to be executed by the NPU + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR qsize_r() : word0(0) {} + CONSTEXPR qsize_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + qsize_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_QSIZE() const + { + uint32_t value = word0; + return value; + } + uint32_t get_QSIZE() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR qsize_r &set_QSIZE(uint32_t value) + { + word0 = value; + return *this; + } + volatile qsize_r &set_QSIZE(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// prot_r - Protection level configured for the NPU when acting as an AXI requester +struct prot_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t active_CPL : 1; // Current privilege level 0=User 1=Privileged + uint32_t active_CSL : 1; // Current security level 0=Secure 1=Non secure + uint32_t reserved0 : 30; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR prot_r() : word0(0) {} + CONSTEXPR prot_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + prot_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::privilege_level get_active_CPL() const + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::privilege_level get_active_CPL() const volatile + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + volatile prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::security_level get_active_CSL() const + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + NPU_NAMESPACE::security_level get_active_CSL() const volatile + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + CONSTEXPR prot_r &set_active_CSL(NPU_NAMESPACE::security_level value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } + volatile prot_r &set_active_CSL(NPU_NAMESPACE::security_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } +#endif +}; + +// config_r - RTL configuration +struct config_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t macs_per_cc : 4; // The log2(macs/clock cycle) + uint32_t cmd_stream_version : 4; // command stream version accepted by this NPU + uint32_t shram_size : 8; // Total size in KB of internal SHRAM + uint32_t reserved0 : 10; + uint32_t functional_safety : 1; // Functional safety configuration + uint32_t custom_dma : 1; // Custom DMA configuration + uint32_t product : 4; // Product configuration + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR config_r() : word0(0) {} + CONSTEXPR config_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + config_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_macs_per_cc() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + uint32_t get_macs_per_cc() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR config_r &set_macs_per_cc(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + volatile config_r &set_macs_per_cc(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_cmd_stream_version() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + uint32_t get_cmd_stream_version() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR config_r &set_cmd_stream_version(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + volatile config_r &set_cmd_stream_version(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_shram_size() const + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 8); + return value; + } + uint32_t get_shram_size() const volatile + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR config_r &set_shram_size(uint32_t value) + { + word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8); + return *this; + } + volatile config_r &set_shram_size(uint32_t value) volatile + { + word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8); + return *this; + } + CONSTEXPR NPU_NAMESPACE::functional_safety get_functional_safety() const + { + NPU_NAMESPACE::functional_safety value = + static_cast(((1U << 1) - 1) & (word0 >> 26)); + return value; + } + NPU_NAMESPACE::functional_safety get_functional_safety() const volatile + { + NPU_NAMESPACE::functional_safety value = + static_cast(((1U << 1) - 1) & (word0 >> 26)); + return value; + } + CONSTEXPR config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value) + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 26); + return *this; + } + volatile config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value) volatile + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 26); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma get_custom_dma() const + { + NPU_NAMESPACE::custom_dma value = static_cast(((1U << 1) - 1) & (word0 >> 27)); + return value; + } + NPU_NAMESPACE::custom_dma get_custom_dma() const volatile + { + NPU_NAMESPACE::custom_dma value = static_cast(((1U << 1) - 1) & (word0 >> 27)); + return value; + } + CONSTEXPR config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value) + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 27); + return *this; + } + volatile config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value) volatile + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 27); + return *this; + } + CONSTEXPR uint32_t get_product() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + uint32_t get_product() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + CONSTEXPR config_r &set_product(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } + volatile config_r &set_product(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } +#endif +}; + +// lock_r - Lock register. This register is designed for driver use and does not affect NPU functionality +struct lock_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t LOCK : 32; // 32 bit value for LOCK configuration + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR lock_r() : word0(0) {} + CONSTEXPR lock_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + lock_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_LOCK() const + { + uint32_t value = word0; + return value; + } + uint32_t get_LOCK() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR lock_r &set_LOCK(uint32_t value) + { + word0 = value; + return *this; + } + volatile lock_r &set_LOCK(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// regioncfg_r - Region memory type configuration. Bits[2*k+1:2*k] give the memory type for REGION[k] +struct regioncfg_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t region0 : 2; // Bits for Region0 Configuration + uint32_t region1 : 2; // Bits for Region1 Configuration + uint32_t region2 : 2; // Bits for Region2 Configuration + uint32_t region3 : 2; // Bits for Region3 Configuration + uint32_t region4 : 2; // Bits for Region4 Configuration + uint32_t region5 : 2; // Bits for Region5 Configuration + uint32_t region6 : 2; // Bits for Region6 Configuration + uint32_t region7 : 2; // Bits for Region7 Configuration + uint32_t reserved0 : 16; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR regioncfg_r() : word0(0) {} + CONSTEXPR regioncfg_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + regioncfg_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region0() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::mem_attr get_region0() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region1() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 2)); + return value; + } + NPU_NAMESPACE::mem_attr get_region1() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 2)); + return value; + } + CONSTEXPR regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 2); + return *this; + } + volatile regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 2); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region2() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::mem_attr get_region2() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 4); + return *this; + } + volatile regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region3() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 6)); + return value; + } + NPU_NAMESPACE::mem_attr get_region3() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 6)); + return value; + } + CONSTEXPR regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 6); + return *this; + } + volatile regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 6); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region4() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 8)); + return value; + } + NPU_NAMESPACE::mem_attr get_region4() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 8)); + return value; + } + CONSTEXPR regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 8); + return *this; + } + volatile regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 8); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region5() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 10)); + return value; + } + NPU_NAMESPACE::mem_attr get_region5() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 10)); + return value; + } + CONSTEXPR regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 10); + return *this; + } + volatile regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 10); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region6() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 12)); + return value; + } + NPU_NAMESPACE::mem_attr get_region6() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 12)); + return value; + } + CONSTEXPR regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 12); + return *this; + } + volatile regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 12); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region7() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 14)); + return value; + } + NPU_NAMESPACE::mem_attr get_region7() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 14)); + return value; + } + CONSTEXPR regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 14); + return *this; + } + volatile regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 14); + return *this; + } +#endif +}; + +// axi_limit0_r - AXI limits for port 0 counter 0 +struct axi_limit0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 5; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t reserved2 : 3; + uint32_t max_outstanding_write_m1 : 4; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 + uint32_t reserved3 : 4; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit0_r() : word0(0) {} + CONSTEXPR axi_limit0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit0_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + volatile axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } + volatile axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } +#endif +}; + +// axi_limit1_r - AXI limits for port 0 counter 1 +struct axi_limit1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 5; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t reserved2 : 3; + uint32_t max_outstanding_write_m1 : 4; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 + uint32_t reserved3 : 4; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit1_r() : word0(0) {} + CONSTEXPR axi_limit1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit1_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + volatile axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } + volatile axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } +#endif +}; + +// axi_limit2_r - AXI limits for port 1 counter 2 +struct axi_limit2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 5; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t reserved2 : 3; + uint32_t max_outstanding_write_m1 : 4; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 + uint32_t reserved3 : 4; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit2_r() : word0(0) {} + CONSTEXPR axi_limit2_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit2_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + volatile axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } + volatile axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } +#endif +}; + +// axi_limit3_r - AXI limits for port 1 counter 3 +struct axi_limit3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 5; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 31 + uint32_t reserved2 : 3; + uint32_t max_outstanding_write_m1 : 4; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 15 + uint32_t reserved3 : 4; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit3_r() : word0(0) {} + CONSTEXPR axi_limit3_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit3_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + volatile axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 16) & word0) | ((((1U << 5) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } + volatile axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 24) & word0) | ((((1U << 4) - 1) & value) << 24); + return *this; + } +#endif +}; + +// basep_r - The driver can use this address to relocate the command stream on region 0. If the region contains data +// requiring A-byte alignment then the base must be a multiple of A +struct basep_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR basep_r() : word0(0), word1(0) {} + CONSTEXPR basep_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + basep_r copy() volatile + { + return *this; + } +#endif +}; + +// wd_status_r - WD_STATUS +struct wd_status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t core_slice_state : 2; // WD core slice parser state + uint32_t core_idle : 1; // Core idle + uint32_t ctrl_state : 2; // WD control state + uint32_t ctrl_idle : 1; // All stripe jobs idle (all weights consumed) + uint32_t write_buf_index0 : 3; // current write index for next data from core + uint32_t write_buf_valid0 : 1; // write buf valid (full) + uint32_t write_buf_idle0 : 1; // write buf idle (empty) + uint32_t write_buf_index1 : 3; // current write index for next data from core + uint32_t write_buf_valid1 : 1; // write buf valid (full) + uint32_t write_buf_idle1 : 1; // write buf idle (empty) + uint32_t events : 12; // WD events mapped as appendix A + uint32_t reserved0 : 4; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR wd_status_r() : word0(0) {} + CONSTEXPR wd_status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + wd_status_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const + { + NPU_NAMESPACE::wd_core_slice_state value = + static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const volatile + { + NPU_NAMESPACE::wd_core_slice_state value = + static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR uint32_t get_core_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_core_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR wd_status_r &set_core_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile wd_status_r &set_core_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const + { + NPU_NAMESPACE::wd_ctrl_state value = static_cast(((1U << 2) - 1) & (word0 >> 3)); + return value; + } + NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const volatile + { + NPU_NAMESPACE::wd_ctrl_state value = static_cast(((1U << 2) - 1) & (word0 >> 3)); + return value; + } + CONSTEXPR wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value) + { + word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 3); + return *this; + } + volatile wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value) volatile + { + word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 3); + return *this; + } + CONSTEXPR uint32_t get_ctrl_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_ctrl_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR wd_status_r &set_ctrl_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile wd_status_r &set_ctrl_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_write_buf_index0() const + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 6); + return value; + } + uint32_t get_write_buf_index0() const volatile + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_index0(uint32_t value) + { + word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6); + return *this; + } + volatile wd_status_r &set_write_buf_index0(uint32_t value) volatile + { + word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_write_buf_valid0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_write_buf_valid0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_valid0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile wd_status_r &set_write_buf_valid0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_write_buf_idle0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_write_buf_idle0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_idle0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile wd_status_r &set_write_buf_idle0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_write_buf_index1() const + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 11); + return value; + } + uint32_t get_write_buf_index1() const volatile + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_index1(uint32_t value) + { + word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11); + return *this; + } + volatile wd_status_r &set_write_buf_index1(uint32_t value) volatile + { + word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_write_buf_valid1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_write_buf_valid1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_valid1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile wd_status_r &set_write_buf_valid1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_write_buf_idle1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + uint32_t get_write_buf_idle1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_idle1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + volatile wd_status_r &set_write_buf_idle1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = ((1U << 12) - 1) & (word0 >> 16); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = ((1U << 12) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR wd_status_r &set_events(uint32_t value) + { + word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16); + return *this; + } + volatile wd_status_r &set_events(uint32_t value) volatile + { + word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16); + return *this; + } +#endif +}; + +// mac_status_r - MAC_STATUS +struct mac_status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t block_cfg_valid : 1; // MAC has a valid block configuration + uint32_t trav_en : 1; // MAC is doing block traversal + uint32_t wait_for_ib : 1; // MAC is waiting for an Input Buffer to become available + uint32_t wait_for_acc_buf : 1; // MAC is waiting for an Accumulator Buffer to become available + uint32_t wait_for_weights : 1; // MAC is waiting for a Weight Block to become available + uint32_t stall_stripe : 1; // MAC is stalling between two stripes + uint32_t dw_sel : 1; // Currently used weight interface in MAC AI + uint32_t wait_for_dw0_ready : 1; // MAC AI is waiting for MAC DPU to send dw0_ready to WD + uint32_t wait_for_dw1_ready : 1; // MAC AI is waiting for MAC DPU to send dw1_ready to WD + uint32_t acc_buf_sel_ai : 1; // Currently used AccBuf interface in MAC AI + uint32_t wait_for_acc0_ready : 1; // MAC AI is waiting for acc0_ready from AO + uint32_t wait_for_acc1_ready : 1; // MAC AI is waiting for acc1_ready from AO + uint32_t acc_buf_sel_aa : 1; // Currently used AccBuf interface in MAC ADDER_ARRAY + uint32_t acc0_valid : 1; // MAC outgoing value of acc0_valid + uint32_t acc1_valid : 1; // MAC outgoing value of acc1_valid + uint32_t reserved0 : 1; + uint32_t events : 11; // Mapped to MAC events described in Appendix A + uint32_t reserved1 : 5; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR mac_status_r() : word0(0) {} + CONSTEXPR mac_status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + mac_status_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_block_cfg_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_block_cfg_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR mac_status_r &set_block_cfg_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile mac_status_r &set_block_cfg_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_trav_en() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_trav_en() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR mac_status_r &set_trav_en(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile mac_status_r &set_trav_en(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_wait_for_ib() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_wait_for_ib() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_ib(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile mac_status_r &set_wait_for_ib(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_wait_for_acc_buf() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_wait_for_acc_buf() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_acc_buf(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile mac_status_r &set_wait_for_acc_buf(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_wait_for_weights() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_wait_for_weights() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_weights(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile mac_status_r &set_wait_for_weights(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_stall_stripe() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_stall_stripe() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR mac_status_r &set_stall_stripe(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile mac_status_r &set_stall_stripe(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_dw_sel() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_dw_sel() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR mac_status_r &set_dw_sel(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile mac_status_r &set_dw_sel(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_wait_for_dw0_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_wait_for_dw0_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_dw0_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile mac_status_r &set_wait_for_dw0_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_wait_for_dw1_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_wait_for_dw1_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_dw1_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile mac_status_r &set_wait_for_dw1_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_acc_buf_sel_ai() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_acc_buf_sel_ai() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR mac_status_r &set_acc_buf_sel_ai(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile mac_status_r &set_acc_buf_sel_ai(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_wait_for_acc0_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_wait_for_acc0_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_acc0_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile mac_status_r &set_wait_for_acc0_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_wait_for_acc1_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + uint32_t get_wait_for_acc1_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_acc1_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + volatile mac_status_r &set_wait_for_acc1_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_acc_buf_sel_aa() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + uint32_t get_acc_buf_sel_aa() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR mac_status_r &set_acc_buf_sel_aa(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + volatile mac_status_r &set_acc_buf_sel_aa(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_acc0_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + uint32_t get_acc0_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + CONSTEXPR mac_status_r &set_acc0_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + volatile mac_status_r &set_acc0_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + CONSTEXPR uint32_t get_acc1_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_acc1_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR mac_status_r &set_acc1_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile mac_status_r &set_acc1_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = ((1U << 11) - 1) & (word0 >> 16); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = ((1U << 11) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR mac_status_r &set_events(uint32_t value) + { + word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16); + return *this; + } + volatile mac_status_r &set_events(uint32_t value) volatile + { + word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16); + return *this; + } +#endif +}; + +// ao_status_r - AO_STATUS +struct ao_status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cmd_sbw_valid : 1; // Block command to shared buffer write module is valid + uint32_t cmd_act_valid : 1; // Block command to activation function module is valid + uint32_t cmd_ctl_valid : 1; // Block command to control module is valid + uint32_t cmd_scl_valid : 1; // Block command to scale module is valid + uint32_t cmd_sbr_valid : 1; // Block command to shared buffer read module is valid + uint32_t cmd_ofm_valid : 1; // Block command to ofm parameter module is valid + uint32_t blk_cmd_ready : 1; // Ready to accept block command + uint32_t blk_cmd_valid : 1; // Block command from CC is valid + uint32_t reserved0 : 8; + uint32_t events : 8; // Mapped to AO events described in Appendix A + uint32_t reserved1 : 8; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ao_status_r() : word0(0) {} + CONSTEXPR ao_status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ao_status_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_cmd_sbw_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_cmd_sbw_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR ao_status_r &set_cmd_sbw_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile ao_status_r &set_cmd_sbw_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_cmd_act_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_cmd_act_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR ao_status_r &set_cmd_act_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile ao_status_r &set_cmd_act_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_cmd_ctl_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_cmd_ctl_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR ao_status_r &set_cmd_ctl_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile ao_status_r &set_cmd_ctl_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_cmd_scl_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_cmd_scl_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR ao_status_r &set_cmd_scl_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile ao_status_r &set_cmd_scl_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_cmd_sbr_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_cmd_sbr_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR ao_status_r &set_cmd_sbr_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile ao_status_r &set_cmd_sbr_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_cmd_ofm_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_cmd_ofm_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR ao_status_r &set_cmd_ofm_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile ao_status_r &set_cmd_ofm_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_blk_cmd_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_blk_cmd_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR ao_status_r &set_blk_cmd_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile ao_status_r &set_blk_cmd_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_blk_cmd_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_blk_cmd_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR ao_status_r &set_blk_cmd_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile ao_status_r &set_blk_cmd_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 16); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR ao_status_r &set_events(uint32_t value) + { + word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16); + return *this; + } + volatile ao_status_r &set_events(uint32_t value) volatile + { + word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16); + return *this; + } +#endif +}; + +// dma_status0_r - DMA_STATUS0 +struct dma_status0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cmd_idle : 1; // When this bit is high means that the CMD block is not busy in generating addresses + // for a CMD job + uint32_t ifm_idle : 1; // When this bit is high means that there are no ongoing IFM jobs + uint32_t wgt_idle_c0 : 1; // When this bit is high means that the WGT block is not busy in generating + // addresses for a WGT job + uint32_t bas_idle_c0 : 1; // When this bit is high means that the BAS block is not busy in generating + // addresses for a BAS job + uint32_t m2m_idle : 1; // When this bit is high means that there are no ongoing M2M jobs + uint32_t ofm_idle : 1; // When this bit is high means that there are no ongoing OFM jobs + uint32_t halt_req : 1; // CPM has requested to HALT AXI bus before soft reset + uint32_t halt_ack : 1; // DMA is in condition to halt the AXI bus since there are no pending transactions + uint32_t pause_req : 1; // CC has requested to pause the AXI + uint32_t pause_ack : 1; // DMA is in condition to pause the AXI bus since there are no pending transactions + uint32_t ib0_ai_valid_c0 : 1; // Data for AI to be read in IFM input buffer 0 - Core 0 + uint32_t ib0_ai_ready_c0 : 1; // Data consumed from AI in IFM input buffer 0 - Core 0 + uint32_t ib1_ai_valid_c0 : 1; // Data for AI to be read in IFM input buffer 1 - Core 0 + uint32_t ib1_ai_ready_c0 : 1; // Data consumed from AI in IFM input buffer 1 - Core 0 + uint32_t ib0_ao_valid_c0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 + uint32_t ib0_ao_ready_c0 : 1; // Data consumed from AO in IFM input buffer 0 - Core 0 + uint32_t ib1_ao_valid_c0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 + uint32_t ib1_ao_ready_c0 : 1; // Data consumed from AO in IFM input buffer 1 - Core 0 + uint32_t ob0_valid_c0 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 0 + uint32_t ob0_ready_c0 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 0 + uint32_t ob1_valid_c0 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 0 + uint32_t ob1_ready_c0 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 0 + uint32_t cmd_valid : 1; // New command word for CC to be consumed + uint32_t cmd_ready : 1; // command word consumed by CC + uint32_t wd_bitstream_valid_c0 : 1; // New weight word for WD to be consumed - Core 0 + uint32_t wd_bitstream_ready_c0 : 1; // Weight word consumed by WD - Core 0 + uint32_t bs_bitstream_valid_c0 : 1; // New BaS word for AO to be consumed - Core 0 + uint32_t bs_bitstream_ready_c0 : 1; // BaS word consumed by AO - Core 0 + uint32_t axi0_ar_stalled : 1; // Read transfer request stalled on arready low AXI0 (due to memory system) + uint32_t axi0_rd_limit_stall : 1; // Read stalled due to one AXI0 limit counter being reached + uint32_t axi0_aw_stalled : 1; // Write transfer request stalled on awready low AXI0 (due to memory system) + uint32_t axi0_w_stalled : 1; // Write transfer stalled on awready low AXI0 (due to memory system) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_status0_r() : word0(0) {} + CONSTEXPR dma_status0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_status0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_cmd_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_cmd_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR dma_status0_r &set_cmd_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile dma_status0_r &set_cmd_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_ifm_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_ifm_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR dma_status0_r &set_ifm_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile dma_status0_r &set_ifm_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_wgt_idle_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_wgt_idle_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR dma_status0_r &set_wgt_idle_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile dma_status0_r &set_wgt_idle_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_bas_idle_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_bas_idle_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR dma_status0_r &set_bas_idle_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile dma_status0_r &set_bas_idle_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_m2m_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_m2m_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR dma_status0_r &set_m2m_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile dma_status0_r &set_m2m_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_ofm_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_ofm_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR dma_status0_r &set_ofm_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile dma_status0_r &set_ofm_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_halt_req() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_halt_req() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR dma_status0_r &set_halt_req(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile dma_status0_r &set_halt_req(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_halt_ack() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_halt_ack() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR dma_status0_r &set_halt_ack(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile dma_status0_r &set_halt_ack(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_pause_req() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_pause_req() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR dma_status0_r &set_pause_req(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile dma_status0_r &set_pause_req(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_pause_ack() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_pause_ack() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR dma_status0_r &set_pause_ack(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile dma_status0_r &set_pause_ack(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_ib0_ai_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ai_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile dma_status0_r &set_ib0_ai_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + uint32_t get_ib0_ai_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ai_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + volatile dma_status0_r &set_ib0_ai_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + uint32_t get_ib1_ai_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ai_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + volatile dma_status0_r &set_ib1_ai_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + uint32_t get_ib1_ai_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ai_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + volatile dma_status0_r &set_ib1_ai_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_ib0_ao_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ao_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile dma_status0_r &set_ib0_ao_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + uint32_t get_ib0_ao_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ao_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + volatile dma_status0_r &set_ib0_ao_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + uint32_t get_ib1_ao_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ao_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + volatile dma_status0_r &set_ib1_ao_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + uint32_t get_ib1_ao_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ao_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + volatile dma_status0_r &set_ib1_ao_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + CONSTEXPR uint32_t get_ob0_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + uint32_t get_ob0_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + CONSTEXPR dma_status0_r &set_ob0_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + volatile dma_status0_r &set_ob0_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + CONSTEXPR uint32_t get_ob0_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + uint32_t get_ob0_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + CONSTEXPR dma_status0_r &set_ob0_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + volatile dma_status0_r &set_ob0_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + CONSTEXPR uint32_t get_ob1_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + uint32_t get_ob1_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + CONSTEXPR dma_status0_r &set_ob1_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + volatile dma_status0_r &set_ob1_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + CONSTEXPR uint32_t get_ob1_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + uint32_t get_ob1_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + CONSTEXPR dma_status0_r &set_ob1_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + volatile dma_status0_r &set_ob1_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + CONSTEXPR uint32_t get_cmd_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + uint32_t get_cmd_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + CONSTEXPR dma_status0_r &set_cmd_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + volatile dma_status0_r &set_cmd_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + CONSTEXPR uint32_t get_cmd_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + uint32_t get_cmd_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + CONSTEXPR dma_status0_r &set_cmd_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } + volatile dma_status0_r &set_cmd_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 24); + return value; + } + uint32_t get_wd_bitstream_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24); + return *this; + } + volatile dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 25); + return value; + } + uint32_t get_wd_bitstream_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 25); + return value; + } + CONSTEXPR dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25); + return *this; + } + volatile dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 26); + return value; + } + uint32_t get_bs_bitstream_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 26); + return value; + } + CONSTEXPR dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26); + return *this; + } + volatile dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 27); + return value; + } + uint32_t get_bs_bitstream_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 27); + return value; + } + CONSTEXPR dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27); + return *this; + } + volatile dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27); + return *this; + } + CONSTEXPR uint32_t get_axi0_ar_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 28); + return value; + } + uint32_t get_axi0_ar_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 28); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_ar_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28); + return *this; + } + volatile dma_status0_r &set_axi0_ar_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28); + return *this; + } + CONSTEXPR uint32_t get_axi0_rd_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 29); + return value; + } + uint32_t get_axi0_rd_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 29); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_rd_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29); + return *this; + } + volatile dma_status0_r &set_axi0_rd_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29); + return *this; + } + CONSTEXPR uint32_t get_axi0_aw_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 30); + return value; + } + uint32_t get_axi0_aw_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 30); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_aw_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30); + return *this; + } + volatile dma_status0_r &set_axi0_aw_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30); + return *this; + } + CONSTEXPR uint32_t get_axi0_w_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_axi0_w_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_w_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile dma_status0_r &set_axi0_w_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// dma_status1_r - DMA_STATUS1 +struct dma_status1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t axi0_wr_limit_stall : 1; // Write stalled due to one AXI0 limit counter being reached + uint32_t axi1_ar_stalled : 1; // Read transfer request stalled on arready low AXI1 (due to memory system) + uint32_t axi1_rd_limit_stall : 1; // Read stalled due to one AXI1 limit counter being reached + uint32_t axi1_wr_stalled : 1; // Write transfer request stalled on awready low AXI1 (due to memory system) + uint32_t axi1_w_stalled : 1; // Write transfer stalled on wready low AXI1 (due to memory system) + uint32_t axi1_wr_limit_stall : 1; // Write stalled due to one AXI1 limit counter being reached + uint32_t wgt_idle_c1 : 1; // When this bit is high means that the WGT block is not busy in generating + // addresses for a WGT job + uint32_t bas_idle_c1 : 1; // When this bit is high means that the BAS block is not busy in generating + // addresses for a BAS job + uint32_t ib0_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 0 - Core 1 + uint32_t ib0_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 0 - Core 1 + uint32_t ib1_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 1 - Core 1 + uint32_t ib1_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 1 - Core 1 + uint32_t ib0_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 + uint32_t ib0_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 0 - Core 1 + uint32_t ib1_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 + uint32_t ib1_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 1 - Core 1 + uint32_t ob0_valid_c1 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 1 + uint32_t ob0_ready_c1 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 1 + uint32_t ob1_valid_c1 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 1 + uint32_t ob1_ready_c1 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 1 + uint32_t wd_bitstream_valid_c1 : 1; // New weight word for WD to be consumed - Core 1 + uint32_t wd_bitstream_ready_c1 : 1; // Weight word consumed by WD - Core 1 + uint32_t bs_bitstream_valid_c1 : 1; // New BaS word for AO to be consumed - Core 1 + uint32_t bs_bitstream_ready_c1 : 1; // BaS word consumed by AO - Core 1 + uint32_t reserved0 : 8; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_status1_r() : word0(0) {} + CONSTEXPR dma_status1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_status1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_axi0_wr_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_axi0_wr_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR dma_status1_r &set_axi0_wr_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile dma_status1_r &set_axi0_wr_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_axi1_ar_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_axi1_ar_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_ar_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile dma_status1_r &set_axi1_ar_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_axi1_rd_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_axi1_rd_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_rd_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile dma_status1_r &set_axi1_rd_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_axi1_wr_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_axi1_wr_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_wr_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile dma_status1_r &set_axi1_wr_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_axi1_w_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_axi1_w_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_w_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile dma_status1_r &set_axi1_w_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_axi1_wr_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_axi1_wr_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_wr_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile dma_status1_r &set_axi1_wr_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_wgt_idle_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_wgt_idle_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR dma_status1_r &set_wgt_idle_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile dma_status1_r &set_wgt_idle_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_bas_idle_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_bas_idle_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR dma_status1_r &set_bas_idle_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile dma_status1_r &set_bas_idle_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_ib0_ai_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ai_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile dma_status1_r &set_ib0_ai_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_ib0_ai_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ai_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile dma_status1_r &set_ib0_ai_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_ib1_ai_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ai_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile dma_status1_r &set_ib1_ai_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + uint32_t get_ib1_ai_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ai_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + volatile dma_status1_r &set_ib1_ai_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + uint32_t get_ib0_ao_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ao_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + volatile dma_status1_r &set_ib0_ao_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + uint32_t get_ib0_ao_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ao_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + volatile dma_status1_r &set_ib0_ao_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_ib1_ao_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ao_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile dma_status1_r &set_ib1_ao_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + uint32_t get_ib1_ao_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ao_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + volatile dma_status1_r &set_ib1_ao_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + CONSTEXPR uint32_t get_ob0_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + uint32_t get_ob0_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR dma_status1_r &set_ob0_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + volatile dma_status1_r &set_ob0_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_ob0_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + uint32_t get_ob0_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + CONSTEXPR dma_status1_r &set_ob0_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + volatile dma_status1_r &set_ob0_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + CONSTEXPR uint32_t get_ob1_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + uint32_t get_ob1_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + CONSTEXPR dma_status1_r &set_ob1_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + volatile dma_status1_r &set_ob1_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + CONSTEXPR uint32_t get_ob1_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + uint32_t get_ob1_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + CONSTEXPR dma_status1_r &set_ob1_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + volatile dma_status1_r &set_ob1_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + uint32_t get_wd_bitstream_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + CONSTEXPR dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + volatile dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + uint32_t get_wd_bitstream_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + CONSTEXPR dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + volatile dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + uint32_t get_bs_bitstream_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + CONSTEXPR dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + volatile dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + uint32_t get_bs_bitstream_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + CONSTEXPR dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } + volatile dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } +#endif +}; + +// clkforce_r - Force clocks on for clock gating +struct clkforce_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t top_level_clk : 1; // set to 1 to force on TOP level clock + uint32_t cc_clk : 1; // set to 1 to force on CC clock + uint32_t dma_clk : 1; // set to 1 to force on DMA clock + uint32_t mac_clk : 1; // set to 1 to force on MAC clock + uint32_t ao_clk : 1; // set to 1 to force on AO clock + uint32_t wd_clk : 1; // set to 1 to force on WD clock + uint32_t reserved0 : 26; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR clkforce_r() : word0(0) {} + CONSTEXPR clkforce_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + clkforce_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_top_level_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_top_level_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR clkforce_r &set_top_level_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile clkforce_r &set_top_level_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_cc_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_cc_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR clkforce_r &set_cc_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile clkforce_r &set_cc_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_dma_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_dma_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR clkforce_r &set_dma_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile clkforce_r &set_dma_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_mac_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_mac_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR clkforce_r &set_mac_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile clkforce_r &set_mac_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_ao_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_ao_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR clkforce_r &set_ao_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile clkforce_r &set_ao_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_wd_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_wd_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR clkforce_r &set_wd_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile clkforce_r &set_wd_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } +#endif +}; + +// debug_address_r - Set debug address for register reads 0x400-0x7FF. The address must be 1KB aligned +struct debug_address_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t addr : 32; // Register address + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR debug_address_r() : word0(0) {} + CONSTEXPR debug_address_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + debug_address_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + uint32_t value = word0; + return value; + } + uint32_t get_addr() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR debug_address_r &set_addr(uint32_t value) + { + word0 = value; + return *this; + } + volatile debug_address_r &set_addr(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// debug_misc_r - 32-bit read/write register for driver debug use. This does not affect NPU function +struct debug_misc_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t misc : 32; // Debug misc + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR debug_misc_r() : word0(0) {} + CONSTEXPR debug_misc_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + debug_misc_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_misc() const + { + uint32_t value = word0; + return value; + } + uint32_t get_misc() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR debug_misc_r &set_misc(uint32_t value) + { + word0 = value; + return *this; + } + volatile debug_misc_r &set_misc(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// debug_block_r - Set from which of four block banks the TSU registers are read. 0 = read from the current bank 256+n = +// force to read from bank n where n is in the range 0 to 3 +struct debug_block_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t block : 32; // Debug block + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR debug_block_r() : word0(0) {} + CONSTEXPR debug_block_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + debug_block_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_block() const + { + uint32_t value = word0; + return value; + } + uint32_t get_block() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR debug_block_r &set_block(uint32_t value) + { + word0 = value; + return *this; + } + volatile debug_block_r &set_block(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pmcr_r - PMU Register control +struct pmcr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cnt_en : 1; // Enable counter + uint32_t event_cnt_rst : 1; // Reset event counter + uint32_t cycle_cnt_rst : 1; // Reset cycle counter + uint32_t mask_en : 1; // PMU can be enabled/disabled by command stream operation NPU_OP_PMU_MASK + uint32_t reserved0 : 7; + uint32_t num_event_cnt : 5; // Number of event counters + uint32_t reserved1 : 16; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcr_r() : word0(8192) {} + CONSTEXPR pmcr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_cnt_en() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_cnt_en() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmcr_r &set_cnt_en(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmcr_r &set_cnt_en(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_event_cnt_rst() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_event_cnt_rst() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmcr_r &set_event_cnt_rst(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmcr_r &set_event_cnt_rst(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_cycle_cnt_rst() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_cycle_cnt_rst() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmcr_r &set_cycle_cnt_rst(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmcr_r &set_cycle_cnt_rst(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_mask_en() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_mask_en() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmcr_r &set_mask_en(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmcr_r &set_mask_en(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_num_event_cnt() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 11); + return value; + } + uint32_t get_num_event_cnt() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR pmcr_r &set_num_event_cnt(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11); + return *this; + } + volatile pmcr_r &set_num_event_cnt(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11); + return *this; + } +#endif +}; + +// pmcntenset_r - Count enable set register +struct pmcntenset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0 : 1; // Event counter enable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1 : 1; // Event counter enable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2 : 1; // Event counter enable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3 : 1; // Event counter enable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT : 1; // PMCCNTR enable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcntenset_r() : word0(0) {} + CONSTEXPR pmcntenset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcntenset_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_2(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_2(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_3(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_3(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmcntenset_r &set_CYCLE_CNT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmcntenset_r &set_CYCLE_CNT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmcntenclr_r - Count enable clear register +struct pmcntenclr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0 : 1; // Event counter disable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1 : 1; // Event counter disable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2 : 1; // Event counter disable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3 : 1; // Event counter disable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT : 1; // PMCCNTR disable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcntenclr_r() : word0(0) {} + CONSTEXPR pmcntenclr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcntenclr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_2(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_2(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_3(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_3(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmcntenclr_r &set_CYCLE_CNT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmcntenclr_r &set_CYCLE_CNT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmovsset_r - Overflow flag status set register +struct pmovsset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow set bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow set bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow set bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow set bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow set bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmovsset_r() : word0(0) {} + CONSTEXPR pmovsset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmovsset_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmovsclr_r - Overflow flag status clear register +struct pmovsclr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow clear bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow clear bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow clear bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow clear bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow clear bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmovsclr_r() : word0(0) {} + CONSTEXPR pmovsclr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmovsclr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmintset_r - Interrupt enable set register +struct pmintset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request enable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmintset_r() : word0(0) {} + CONSTEXPR pmintset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmintset_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_0_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_0_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_1_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_1_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_2_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_2_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_3_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_3_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmintset_r &set_CYCLE_CNT_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmintset_r &set_CYCLE_CNT_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmintclr_r - Interrupt enable clear register +struct pmintclr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request disable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmintclr_r() : word0(0) {} + CONSTEXPR pmintclr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmintclr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmintclr_r &set_CYCLE_CNT_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmintclr_r &set_CYCLE_CNT_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmccntr_r - Performance monitor cycle count register +struct pmccntr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CYCLE_CNT_LO : 32; // Cycle count - LSB + uint32_t CYCLE_CNT_HI : 16; // Cycle count - MSB + uint32_t reserved0 : 16; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR pmccntr_r() : word0(0), word1(0) {} + CONSTEXPR pmccntr_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + pmccntr_r copy() volatile + { + return *this; + } +#endif +}; + +// pmccntr_cfg_r - Set start/stop event on the cycle counter +struct pmccntr_cfg_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CYCLE_CNT_CFG_START : 10; // Cycle counter start event + uint32_t reserved0 : 6; + uint32_t CYCLE_CNT_CFG_STOP : 10; // Cycle counter stop event + uint32_t reserved1 : 6; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmccntr_cfg_r() : word0(0) {} + CONSTEXPR pmccntr_cfg_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmccntr_cfg_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const volatile + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value) + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } + volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value) volatile + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 16)); + return value; + } + NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const volatile + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 16)); + return value; + } + CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value) + { + word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 16); + return *this; + } + volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value) volatile + { + word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 16); + return *this; + } +#endif +}; + +// pmcaxi_chan_r - Set which AXI channel to monitor for latency measurements in PMU +struct pmcaxi_chan_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CH_SEL : 4; // Channel select for latency measurements + uint32_t reserved0 : 4; + uint32_t AXI_CNT_SEL : 2; // AXI counter to monitor for latency measurements + uint32_t BW_CH_SEL_EN : 1; // Bandwidth channel selector + uint32_t reserved1 : 21; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcaxi_chan_r() : word0(0) {} + CONSTEXPR pmcaxi_chan_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcaxi_chan_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const + { + NPU_NAMESPACE::pmu_axi_channel value = + static_cast(((1U << 4) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const volatile + { + NPU_NAMESPACE::pmu_axi_channel value = + static_cast(((1U << 4) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value) + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 0); + return *this; + } + volatile pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value) volatile + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR uint32_t get_AXI_CNT_SEL() const + { + uint32_t value = ((1U << 2) - 1) & (word0 >> 8); + return value; + } + uint32_t get_AXI_CNT_SEL() const volatile + { + uint32_t value = ((1U << 2) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value) + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8); + return *this; + } + volatile pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value) volatile + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_BW_CH_SEL_EN() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_BW_CH_SEL_EN() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } +#endif +}; + +// kernel_x_r - Kernel X offset of in kernel decomposition +struct kernel_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_x_r() : word0(0) {} + CONSTEXPR kernel_x_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_x_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_x_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_x_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_y_r - Kernel Y offset of in kernel decomposition +struct kernel_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_y_r() : word0(0) {} + CONSTEXPR kernel_y_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_y_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_y_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_y_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_w_m1_r - Kernel (width-1) of current block +struct kernel_w_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_w_m1_r() : word0(0) {} + CONSTEXPR kernel_w_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_w_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_w_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_w_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_h_m1_r - Kernel (height-1) of current block +struct kernel_h_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_h_m1_r() : word0(0) {} + CONSTEXPR kernel_h_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_h_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_h_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_h_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_cblk_width_m1_r - OFM current block (width-1) +struct ofm_cblk_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_cblk_width_m1_r() : word0(0) {} + CONSTEXPR ofm_cblk_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_cblk_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_cblk_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_cblk_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_cblk_height_m1_r - OFM current block (height-1) +struct ofm_cblk_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_cblk_height_m1_r() : word0(0) {} + CONSTEXPR ofm_cblk_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_cblk_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_cblk_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_cblk_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_cblk_depth_m1_r - OFM current block (depth-1) +struct ofm_cblk_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_cblk_depth_m1_r() : word0(0) {} + CONSTEXPR ofm_cblk_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_cblk_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_cblk_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_cblk_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_cblk_depth_m1_r - IFM current block (depth-1) +struct ifm_cblk_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_cblk_depth_m1_r() : word0(0) {} + CONSTEXPR ifm_cblk_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_cblk_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_cblk_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_cblk_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_x_r - Block X coordinate in OFM +struct ofm_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_x_r() : word0(0) {} + CONSTEXPR ofm_x_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_x_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_x_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_x_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_y_r - Block Y coordinate in OFM +struct ofm_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_y_r() : word0(0) {} + CONSTEXPR ofm_y_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_y_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_y_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_y_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_z_r - Block Z (channel) coordinate in OFM +struct ofm_z_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_z_r() : word0(0) {} + CONSTEXPR ofm_z_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_z_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_z_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_z_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_z_r - Block Z (channel) coordinate in IFM +struct ifm_z_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_z_r() : word0(0) {} + CONSTEXPR ifm_z_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_z_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_z_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_z_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pad_top_r - Block top pad +struct pad_top_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pad_top_r() : word0(0) {} + CONSTEXPR pad_top_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pad_top_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pad_top_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile pad_top_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pad_left_r - Block left pad +struct pad_left_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pad_left_r() : word0(0) {} + CONSTEXPR pad_left_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pad_left_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pad_left_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile pad_left_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_cblk_width_r - IFM current block derived width +struct ifm_cblk_width_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_cblk_width_r() : word0(0) {} + CONSTEXPR ifm_cblk_width_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_cblk_width_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_cblk_width_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_cblk_width_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_cblk_height_r - IFM current block derived height +struct ifm_cblk_height_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_cblk_height_r() : word0(0) {} + CONSTEXPR ifm_cblk_height_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_cblk_height_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_cblk_height_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_cblk_height_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_ifm_src_r - DMA IFM channel source position on AXI +struct dma_ifm_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_ifm_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_ifm_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_ifm_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_ifm_dst_r - DMA IFM channel destination position in SHRAM +struct dma_ifm_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_ifm_dst_r() : word0(0) {} + CONSTEXPR dma_ifm_dst_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_ifm_dst_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma_ifm_dst_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma_ifm_dst_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_ofm_src_r - DMA OFM channel source position in SHRAM +struct dma_ofm_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_ofm_src_r() : word0(0) {} + CONSTEXPR dma_ofm_src_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_ofm_src_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma_ofm_src_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma_ofm_src_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_ofm_dst_r - DMA OFM channel destination position on AXI +struct dma_ofm_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_ofm_dst_r() : word0(0), word1(0) {} + CONSTEXPR dma_ofm_dst_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_ofm_dst_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_weight_src_r - DMA weight channel source position on AXI +struct dma_weight_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_weight_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_weight_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_weight_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_cmd_src_r - DMA command channel source position on AXI +struct dma_cmd_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_cmd_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_cmd_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_cmd_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_cmd_size_r - DMA command channel number of bytes buffered +struct dma_cmd_size_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_cmd_size_r() : word0(0) {} + CONSTEXPR dma_cmd_size_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_cmd_size_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma_cmd_size_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma_cmd_size_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_m2m_src_r - DMA memory to memory source position on AXI +struct dma_m2m_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_m2m_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_m2m_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_m2m_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_m2m_dst_r - DMA memory to memory destination position on AXI +struct dma_m2m_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_m2m_dst_r() : word0(0), word1(0) {} + CONSTEXPR dma_m2m_dst_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_m2m_dst_r copy() volatile + { + return *this; + } +#endif +}; + +// current_qread_r - QREAD position being issued (rather than completed) +struct current_qread_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_qread_r() : word0(0) {} + CONSTEXPR current_qread_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_qread_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_qread_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_qread_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_scale_src_r - DMA scale and bias channel source position on AXI +struct dma_scale_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset : 32; // Offset + uint32_t reserved0 : 32; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_scale_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_scale_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_scale_src_r copy() volatile + { + return *this; + } +#endif +}; + +// current_block_r - 0-3. Current block bank being executed by the TSU or last one executed if TSU is stopped +struct current_block_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_block_r() : word0(0) {} + CONSTEXPR current_block_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_block_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_block_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_block_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// current_op_r - Current NPU OP command being executed by the TSU +struct current_op_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_op_r() : word0(0) {} + CONSTEXPR current_op_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_op_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_op_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_op_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// current_cmd_r - Current 32-bit command being parsed by the command stream parser +struct current_cmd_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_cmd_r() : word0(0) {} + CONSTEXPR current_cmd_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_cmd_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_cmd_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_cmd_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pmevcntr_r - Performance monitor event 0 count register +struct pmevcntr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t count : 32; // Count word + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmevcntr_r() : word0(0) {} + CONSTEXPR pmevcntr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmevcntr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_count() const + { + uint32_t value = word0; + return value; + } + uint32_t get_count() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pmevcntr_r &set_count(uint32_t value) + { + word0 = value; + return *this; + } + volatile pmevcntr_r &set_count(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pmevtyper_r - Performance monitor event type register 0 +struct pmevtyper_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EV_TYPE : 10; // Event Type + uint32_t reserved0 : 22; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmevtyper_r() : word0(0) {} + CONSTEXPR pmevtyper_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmevtyper_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_event get_EV_TYPE() const + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::pmu_event get_EV_TYPE() const volatile + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value) + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } + volatile pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value) volatile + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } +#endif +}; + +// shared_buffer_r - Shared buffer debug access. Only valid in STOPPED state +struct shared_buffer_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t mem_word : 32; // Memory word + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR shared_buffer_r() : word0(0) {} + CONSTEXPR shared_buffer_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + shared_buffer_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_mem_word() const + { + uint32_t value = word0; + return value; + } + uint32_t get_mem_word() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR shared_buffer_r &set_mem_word(uint32_t value) + { + word0 = value; + return *this; + } + volatile shared_buffer_r &set_mem_word(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_top_r - None +struct ifm_pad_top_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_top_r() : word0(0) {} + CONSTEXPR ifm_pad_top_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_top_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_top_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_top_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_left_r - None +struct ifm_pad_left_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_left_r() : word0(0) {} + CONSTEXPR ifm_pad_left_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_left_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_left_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_left_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_right_r - None +struct ifm_pad_right_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_right_r() : word0(0) {} + CONSTEXPR ifm_pad_right_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_right_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_right_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_right_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_bottom_r - None +struct ifm_pad_bottom_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_bottom_r() : word0(0) {} + CONSTEXPR ifm_pad_bottom_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_bottom_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_bottom_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_bottom_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_depth_m1_r - None +struct ifm_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_depth_m1_r() : word0(0) {} + CONSTEXPR ifm_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_precision_r - None +struct ifm_precision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_precision_r() : word0(0) {} + CONSTEXPR ifm_precision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_precision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_precision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_precision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_upscale_r - None +struct ifm_upscale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_upscale_r() : word0(0) {} + CONSTEXPR ifm_upscale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_upscale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_upscale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_upscale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_zero_point_r - None +struct ifm_zero_point_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_zero_point_r() : word0(0) {} + CONSTEXPR ifm_zero_point_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_zero_point_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_zero_point_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_zero_point_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_width0_m1_r - None +struct ifm_width0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_width0_m1_r() : word0(0) {} + CONSTEXPR ifm_width0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_width0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_width0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_width0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_height0_m1_r - None +struct ifm_height0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_height0_m1_r() : word0(0) {} + CONSTEXPR ifm_height0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_height0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_height0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_height0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_height1_m1_r - None +struct ifm_height1_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_height1_m1_r() : word0(0) {} + CONSTEXPR ifm_height1_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_height1_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_height1_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_height1_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_ib_end_r - None +struct ifm_ib_end_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_ib_end_r() : word0(0) {} + CONSTEXPR ifm_ib_end_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_ib_end_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_ib_end_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_ib_end_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_region_r - None +struct ifm_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_region_r() : word0(0) {} + CONSTEXPR ifm_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_width_m1_r - None +struct ofm_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_width_m1_r() : word0(0) {} + CONSTEXPR ofm_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_height_m1_r - None +struct ofm_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_height_m1_r() : word0(0) {} + CONSTEXPR ofm_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_depth_m1_r - None +struct ofm_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_depth_m1_r() : word0(0) {} + CONSTEXPR ofm_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_precision_r - None +struct ofm_precision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_precision_r() : word0(0) {} + CONSTEXPR ofm_precision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_precision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_precision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_precision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_blk_width_m1_r - None +struct ofm_blk_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_blk_width_m1_r() : word0(0) {} + CONSTEXPR ofm_blk_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_blk_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_blk_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_blk_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_blk_height_m1_r - None +struct ofm_blk_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_blk_height_m1_r() : word0(0) {} + CONSTEXPR ofm_blk_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_blk_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_blk_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_blk_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_blk_depth_m1_r - None +struct ofm_blk_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_blk_depth_m1_r() : word0(0) {} + CONSTEXPR ofm_blk_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_blk_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_blk_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_blk_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_zero_point_r - None +struct ofm_zero_point_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_zero_point_r() : word0(0) {} + CONSTEXPR ofm_zero_point_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_zero_point_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_zero_point_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_zero_point_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_width0_m1_r - None +struct ofm_width0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_width0_m1_r() : word0(0) {} + CONSTEXPR ofm_width0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_width0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_width0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_width0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_height0_m1_r - None +struct ofm_height0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_height0_m1_r() : word0(0) {} + CONSTEXPR ofm_height0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_height0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_height0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_height0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_height1_m1_r - None +struct ofm_height1_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_height1_m1_r() : word0(0) {} + CONSTEXPR ofm_height1_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_height1_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_height1_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_height1_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_region_r - None +struct ofm_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_region_r() : word0(0) {} + CONSTEXPR ofm_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_width_m1_r - None +struct kernel_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_width_m1_r() : word0(0) {} + CONSTEXPR kernel_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_height_m1_r - None +struct kernel_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_height_m1_r() : word0(0) {} + CONSTEXPR kernel_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_stride_r - None +struct kernel_stride_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_stride_r() : word0(0) {} + CONSTEXPR kernel_stride_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_stride_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_stride_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_stride_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// acc_format_r - None +struct acc_format_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR acc_format_r() : word0(0) {} + CONSTEXPR acc_format_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + acc_format_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR acc_format_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile acc_format_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// activation_r - None +struct activation_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR activation_r() : word0(0) {} + CONSTEXPR activation_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + activation_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR activation_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile activation_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// activation_min_r - None +struct activation_min_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR activation_min_r() : word0(0) {} + CONSTEXPR activation_min_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + activation_min_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR activation_min_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile activation_min_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// activation_max_r - None +struct activation_max_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR activation_max_r() : word0(0) {} + CONSTEXPR activation_max_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + activation_max_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR activation_max_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile activation_max_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// weight_region_r - None +struct weight_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR weight_region_r() : word0(0) {} + CONSTEXPR weight_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + weight_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR weight_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile weight_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// scale_region_r - None +struct scale_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR scale_region_r() : word0(0) {} + CONSTEXPR scale_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + scale_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR scale_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile scale_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ab_start_r - None +struct ab_start_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ab_start_r() : word0(0) {} + CONSTEXPR ab_start_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ab_start_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ab_start_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ab_start_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// blockdep_r - None +struct blockdep_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR blockdep_r() : word0(0) {} + CONSTEXPR blockdep_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + blockdep_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR blockdep_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile blockdep_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_src_region_r - None +struct dma0_src_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_src_region_r() : word0(0) {} + CONSTEXPR dma0_src_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_src_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_src_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_src_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_dst_region_r - None +struct dma0_dst_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_dst_region_r() : word0(0) {} + CONSTEXPR dma0_dst_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_dst_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_dst_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_dst_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_size0_r - None +struct dma0_size0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_size0_r() : word0(0) {} + CONSTEXPR dma0_size0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_size0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_size0_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_size0_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_size1_r - None +struct dma0_size1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_size1_r() : word0(0) {} + CONSTEXPR dma0_size1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_size1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_size1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_size1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_broadcast_r - None +struct ifm2_broadcast_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_broadcast_r() : word0(0) {} + CONSTEXPR ifm2_broadcast_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_broadcast_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_broadcast_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_broadcast_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_scalar_r - None +struct ifm2_scalar_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_scalar_r() : word0(0) {} + CONSTEXPR ifm2_scalar_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_scalar_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_scalar_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_scalar_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_precision_r - None +struct ifm2_precision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_precision_r() : word0(0) {} + CONSTEXPR ifm2_precision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_precision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_precision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_precision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_zero_point_r - None +struct ifm2_zero_point_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_zero_point_r() : word0(0) {} + CONSTEXPR ifm2_zero_point_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_zero_point_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_zero_point_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_zero_point_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_width0_m1_r - None +struct ifm2_width0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_width0_m1_r() : word0(0) {} + CONSTEXPR ifm2_width0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_width0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_width0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_width0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_height0_m1_r - None +struct ifm2_height0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_height0_m1_r() : word0(0) {} + CONSTEXPR ifm2_height0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_height0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_height0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_height0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_height1_m1_r - None +struct ifm2_height1_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_height1_m1_r() : word0(0) {} + CONSTEXPR ifm2_height1_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_height1_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_height1_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_height1_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_ib_start_r - None +struct ifm2_ib_start_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_ib_start_r() : word0(0) {} + CONSTEXPR ifm2_ib_start_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_ib_start_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_ib_start_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_ib_start_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_region_r - None +struct ifm2_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_region_r() : word0(0) {} + CONSTEXPR ifm2_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_base0_r - None +struct ifm_base0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base0_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base0_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base0_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_base1_r - None +struct ifm_base1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base1_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base1_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base1_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_base2_r - None +struct ifm_base2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base2_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base2_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base2_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_base3_r - None +struct ifm_base3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base3_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base3_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base3_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_stride_x_r - None +struct ifm_stride_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_stride_x_r() : word0(0), word1(0) {} + CONSTEXPR ifm_stride_x_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_stride_x_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_stride_y_r - None +struct ifm_stride_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_stride_y_r() : word0(0), word1(0) {} + CONSTEXPR ifm_stride_y_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_stride_y_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_stride_c_r - None +struct ifm_stride_c_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_stride_c_r() : word0(0), word1(0) {} + CONSTEXPR ifm_stride_c_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_stride_c_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base0_r - None +struct ofm_base0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base0_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base0_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base0_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base1_r - None +struct ofm_base1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base1_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base1_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base1_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base2_r - None +struct ofm_base2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base2_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base2_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base2_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base3_r - None +struct ofm_base3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base3_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base3_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base3_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_stride_x_r - None +struct ofm_stride_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_stride_x_r() : word0(0), word1(0) {} + CONSTEXPR ofm_stride_x_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_stride_x_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_stride_y_r - None +struct ofm_stride_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_stride_y_r() : word0(0), word1(0) {} + CONSTEXPR ofm_stride_y_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_stride_y_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_stride_c_r - None +struct ofm_stride_c_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_stride_c_r() : word0(0), word1(0) {} + CONSTEXPR ofm_stride_c_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_stride_c_r copy() volatile + { + return *this; + } +#endif +}; + +// weight_base_r - None +struct weight_base_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR weight_base_r() : word0(0), word1(0) {} + CONSTEXPR weight_base_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + weight_base_r copy() volatile + { + return *this; + } +#endif +}; + +// weight_length_r - None +struct weight_length_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR weight_length_r() : word0(0), word1(0) {} + CONSTEXPR weight_length_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + weight_length_r copy() volatile + { + return *this; + } +#endif +}; + +// scale_base_r - None +struct scale_base_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR scale_base_r() : word0(0), word1(0) {} + CONSTEXPR scale_base_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + scale_base_r copy() volatile + { + return *this; + } +#endif +}; + +// scale_length_r - None +struct scale_length_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR scale_length_r() : word0(0), word1(0) {} + CONSTEXPR scale_length_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + scale_length_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_scale_r - None +struct ofm_scale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_scale_r() : word0(0) {} + CONSTEXPR ofm_scale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_scale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_scale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_scale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_scale_shift_r - None +struct ofm_scale_shift_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_scale_shift_r() : word0(0) {} + CONSTEXPR ofm_scale_shift_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_scale_shift_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_scale_shift_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_scale_shift_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// opa_scale_r - None +struct opa_scale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR opa_scale_r() : word0(0) {} + CONSTEXPR opa_scale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + opa_scale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR opa_scale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile opa_scale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// opa_scale_shift_r - None +struct opa_scale_shift_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR opa_scale_shift_r() : word0(0) {} + CONSTEXPR opa_scale_shift_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + opa_scale_shift_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR opa_scale_shift_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile opa_scale_shift_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// opb_scale_r - None +struct opb_scale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR opb_scale_r() : word0(0) {} + CONSTEXPR opb_scale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + opb_scale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR opb_scale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile opb_scale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_src_r - None +struct dma0_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_src_r() : word0(0), word1(0) {} + CONSTEXPR dma0_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma0_dst_r - None +struct dma0_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_dst_r() : word0(0), word1(0) {} + CONSTEXPR dma0_dst_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_dst_r copy() volatile + { + return *this; + } +#endif +}; + +// dma0_len_r - None +struct dma0_len_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_len_r() : word0(0), word1(0) {} + CONSTEXPR dma0_len_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_len_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base0_r - None +struct ifm2_base0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base0_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base0_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base0_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base1_r - None +struct ifm2_base1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base1_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base1_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base1_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base2_r - None +struct ifm2_base2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base2_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base2_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base2_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base3_r - None +struct ifm2_base3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base3_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base3_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base3_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_stride_x_r - None +struct ifm2_stride_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_stride_x_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_stride_x_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_stride_x_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_stride_y_r - None +struct ifm2_stride_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_stride_y_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_stride_y_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_stride_y_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_stride_c_r - None +struct ifm2_stride_c_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_stride_c_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_stride_c_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_stride_c_r copy() volatile + { + return *this; + } +#endif +}; + +// revision_r - Internal FPGA build revision: first 32-bits of the Ultan Git hash used for the build +struct revision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR revision_r() : word0(0) {} + CONSTEXPR revision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + revision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR revision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile revision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid4_r - Peripheral ID byte 4 (Arm=code 4) +struct pid4_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID4 : 32; // Byte 4 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid4_r() : word0(4) {} + CONSTEXPR pid4_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid4_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID4() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID4() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid4_r &set_PID4(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid4_r &set_PID4(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid5_r - Peripheral ID byte 5 (reserved) +struct pid5_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID5 : 32; // Byte 5 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid5_r() : word0(0) {} + CONSTEXPR pid5_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid5_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID5() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID5() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid5_r &set_PID5(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid5_r &set_PID5(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid6_r - Peripheral ID byte 6 (reserved) +struct pid6_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID6 : 32; // Byte 6 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid6_r() : word0(0) {} + CONSTEXPR pid6_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid6_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID6() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID6() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid6_r &set_PID6(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid6_r &set_PID6(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid7_r - Peripheral ID byte 7 (reserved) +struct pid7_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID7 : 32; // Byte 7 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid7_r() : word0(0) {} + CONSTEXPR pid7_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid7_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID7() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID7() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid7_r &set_PID7(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid7_r &set_PID7(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid0_r - Peripheral ID byte 0. This is bits[7:0] of the part number +struct pid0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID0 : 32; // Byte 0 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid0_r() : word0(128) {} + CONSTEXPR pid0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID0() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID0() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid0_r &set_PID0(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid0_r &set_PID0(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid1_r - Peripheral ID byte 1. This is bits[11:8] of the part number in bits[3:0], and bits[3:0] of the Arm ID in +// bits[7:4] +struct pid1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID1 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid1_r() : word0(181) {} + CONSTEXPR pid1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID1() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID1() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid1_r &set_PID1(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid1_r &set_PID1(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid2_r - Peripheral ID byte 2. This is bits[6:4] of the Arm ID in bits[2:0], and bit 3 indicates format B +struct pid2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID2 : 32; // Byte 2 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid2_r() : word0(11) {} + CONSTEXPR pid2_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid2_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID2() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID2() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid2_r &set_PID2(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid2_r &set_PID2(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid3_r - Peripheral ID byte 3 +struct pid3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID3 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid3_r() : word0(0) {} + CONSTEXPR pid3_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid3_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID3() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID3() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid3_r &set_PID3(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid3_r &set_PID3(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid0_r - Component ID byte 0 +struct cid0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID0 : 32; // Byte 0 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid0_r() : word0(13) {} + CONSTEXPR cid0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID0() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID0() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid0_r &set_CID0(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid0_r &set_CID0(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid1_r - Component ID byte 1 +struct cid1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID1 : 32; // Byte 1 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid1_r() : word0(240) {} + CONSTEXPR cid1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID1() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID1() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid1_r &set_CID1(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid1_r &set_CID1(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid2_r - Component ID byte 2 +struct cid2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID2 : 32; // Byte 2 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid2_r() : word0(5) {} + CONSTEXPR cid2_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid2_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID2() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID2() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid2_r &set_CID2(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid2_r &set_CID2(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid3_r - Component ID byte 3 +struct cid3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID3 : 32; // Byte 3 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid3_r() : word0(177) {} + CONSTEXPR cid3_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid3_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID3() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID3() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid3_r &set_CID3(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid3_r &set_CID3(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +struct NPU_REG +{ + STRUCT id_r ID; // 0x0000 + STRUCT status_r STATUS; // 0x0004 + STRUCT cmd_r CMD; // 0x0008 + STRUCT reset_r RESET; // 0x000C + STRUCT qbase_r QBASE; // 0x0010 + STRUCT qread_r QREAD; // 0x0018 + STRUCT qconfig_r QCONFIG; // 0x001C + STRUCT qsize_r QSIZE; // 0x0020 + STRUCT prot_r PROT; // 0x0024 + STRUCT config_r CONFIG; // 0x0028 + STRUCT lock_r LOCK; // 0x002C + uint32_t unused0[3]; + STRUCT regioncfg_r REGIONCFG; // 0x003C + STRUCT axi_limit0_r AXI_LIMIT0; // 0x0040 + STRUCT axi_limit1_r AXI_LIMIT1; // 0x0044 + STRUCT axi_limit2_r AXI_LIMIT2; // 0x0048 + STRUCT axi_limit3_r AXI_LIMIT3; // 0x004C + uint32_t unused1[12]; + STRUCT basep_r BASEP[8]; // 0x0080 + uint32_t unused2[16]; + STRUCT wd_status_r WD_STATUS; // 0x0100 + STRUCT mac_status_r MAC_STATUS; // 0x0104 + STRUCT ao_status_r AO_STATUS; // 0x0108 + uint32_t unused3[1]; + STRUCT dma_status0_r DMA_STATUS0; // 0x0110 + STRUCT dma_status1_r DMA_STATUS1; // 0x0114 + uint32_t unused4[10]; + STRUCT clkforce_r CLKFORCE; // 0x0140 + STRUCT debug_address_r DEBUG_ADDRESS; // 0x0144 + STRUCT debug_misc_r DEBUG_MISC; // 0x0148 + uint32_t unused5[1]; + STRUCT debug_block_r DEBUG_BLOCK; // 0x0150 + uint32_t unused6[11]; + STRUCT pmcr_r PMCR; // 0x0180 + STRUCT pmcntenset_r PMCNTENSET; // 0x0184 + STRUCT pmcntenclr_r PMCNTENCLR; // 0x0188 + STRUCT pmovsset_r PMOVSSET; // 0x018C + STRUCT pmovsclr_r PMOVSCLR; // 0x0190 + STRUCT pmintset_r PMINTSET; // 0x0194 + STRUCT pmintclr_r PMINTCLR; // 0x0198 + uint32_t unused7[1]; + STRUCT pmccntr_r PMCCNTR; // 0x01A0 + STRUCT pmccntr_cfg_r PMCCNTR_CFG; // 0x01A8 + STRUCT pmcaxi_chan_r PMCAXI_CHAN; // 0x01AC + uint32_t unused8[20]; + STRUCT kernel_x_r KERNEL_X; // 0x0200 + STRUCT kernel_y_r KERNEL_Y; // 0x0204 + STRUCT kernel_w_m1_r KERNEL_W_M1; // 0x0208 + STRUCT kernel_h_m1_r KERNEL_H_M1; // 0x020C + STRUCT ofm_cblk_width_m1_r OFM_CBLK_WIDTH_M1; // 0x0210 + STRUCT ofm_cblk_height_m1_r OFM_CBLK_HEIGHT_M1; // 0x0214 + STRUCT ofm_cblk_depth_m1_r OFM_CBLK_DEPTH_M1; // 0x0218 + STRUCT ifm_cblk_depth_m1_r IFM_CBLK_DEPTH_M1; // 0x021C + STRUCT ofm_x_r OFM_X; // 0x0220 + STRUCT ofm_y_r OFM_Y; // 0x0224 + STRUCT ofm_z_r OFM_Z; // 0x0228 + STRUCT ifm_z_r IFM_Z; // 0x022C + STRUCT pad_top_r PAD_TOP; // 0x0230 + STRUCT pad_left_r PAD_LEFT; // 0x0234 + STRUCT ifm_cblk_width_r IFM_CBLK_WIDTH; // 0x0238 + STRUCT ifm_cblk_height_r IFM_CBLK_HEIGHT; // 0x023C + STRUCT dma_ifm_src_r DMA_IFM_SRC; // 0x0240 + STRUCT dma_ifm_dst_r DMA_IFM_DST; // 0x0248 + STRUCT dma_ofm_src_r DMA_OFM_SRC; // 0x024C + STRUCT dma_ofm_dst_r DMA_OFM_DST; // 0x0250 + STRUCT dma_weight_src_r DMA_WEIGHT_SRC; // 0x0258 + STRUCT dma_cmd_src_r DMA_CMD_SRC; // 0x0260 + STRUCT dma_cmd_size_r DMA_CMD_SIZE; // 0x0268 + STRUCT dma_m2m_src_r DMA_M2M_SRC; // 0x026C + STRUCT dma_m2m_dst_r DMA_M2M_DST; // 0x0274 + STRUCT current_qread_r CURRENT_QREAD; // 0x027C + STRUCT dma_scale_src_r DMA_SCALE_SRC; // 0x0280 + uint32_t unused9[11]; + STRUCT current_block_r CURRENT_BLOCK; // 0x02B4 + STRUCT current_op_r CURRENT_OP; // 0x02B8 + STRUCT current_cmd_r CURRENT_CMD; // 0x02BC + uint32_t unused10[16]; + STRUCT pmevcntr_r PMEVCNTR[4]; // 0x0300 + uint32_t unused11[28]; + STRUCT pmevtyper_r PMEVTYPER[4]; // 0x0380 + uint32_t unused12[28]; + STRUCT shared_buffer_r SHARED_BUFFER[256]; // 0x0400 + STRUCT ifm_pad_top_r IFM_PAD_TOP; // 0x0800 + STRUCT ifm_pad_left_r IFM_PAD_LEFT; // 0x0804 + STRUCT ifm_pad_right_r IFM_PAD_RIGHT; // 0x0808 + STRUCT ifm_pad_bottom_r IFM_PAD_BOTTOM; // 0x080C + STRUCT ifm_depth_m1_r IFM_DEPTH_M1; // 0x0810 + STRUCT ifm_precision_r IFM_PRECISION; // 0x0814 + uint32_t unused13[1]; + STRUCT ifm_upscale_r IFM_UPSCALE; // 0x081C + uint32_t unused14[1]; + STRUCT ifm_zero_point_r IFM_ZERO_POINT; // 0x0824 + STRUCT ifm_width0_m1_r IFM_WIDTH0_M1; // 0x0828 + STRUCT ifm_height0_m1_r IFM_HEIGHT0_M1; // 0x082C + STRUCT ifm_height1_m1_r IFM_HEIGHT1_M1; // 0x0830 + STRUCT ifm_ib_end_r IFM_IB_END; // 0x0834 + uint32_t unused15[1]; + STRUCT ifm_region_r IFM_REGION; // 0x083C + uint32_t unused16[1]; + STRUCT ofm_width_m1_r OFM_WIDTH_M1; // 0x0844 + STRUCT ofm_height_m1_r OFM_HEIGHT_M1; // 0x0848 + STRUCT ofm_depth_m1_r OFM_DEPTH_M1; // 0x084C + STRUCT ofm_precision_r OFM_PRECISION; // 0x0850 + STRUCT ofm_blk_width_m1_r OFM_BLK_WIDTH_M1; // 0x0854 + STRUCT ofm_blk_height_m1_r OFM_BLK_HEIGHT_M1; // 0x0858 + STRUCT ofm_blk_depth_m1_r OFM_BLK_DEPTH_M1; // 0x085C + STRUCT ofm_zero_point_r OFM_ZERO_POINT; // 0x0860 + uint32_t unused17[1]; + STRUCT ofm_width0_m1_r OFM_WIDTH0_M1; // 0x0868 + STRUCT ofm_height0_m1_r OFM_HEIGHT0_M1; // 0x086C + STRUCT ofm_height1_m1_r OFM_HEIGHT1_M1; // 0x0870 + uint32_t unused18[2]; + STRUCT ofm_region_r OFM_REGION; // 0x087C + STRUCT kernel_width_m1_r KERNEL_WIDTH_M1; // 0x0880 + STRUCT kernel_height_m1_r KERNEL_HEIGHT_M1; // 0x0884 + STRUCT kernel_stride_r KERNEL_STRIDE; // 0x0888 + uint32_t unused19[1]; + STRUCT acc_format_r ACC_FORMAT; // 0x0890 + STRUCT activation_r ACTIVATION; // 0x0894 + STRUCT activation_min_r ACTIVATION_MIN; // 0x0898 + STRUCT activation_max_r ACTIVATION_MAX; // 0x089C + STRUCT weight_region_r WEIGHT_REGION; // 0x08A0 + STRUCT scale_region_r SCALE_REGION; // 0x08A4 + uint32_t unused20[3]; + STRUCT ab_start_r AB_START; // 0x08B4 + uint32_t unused21[1]; + STRUCT blockdep_r BLOCKDEP; // 0x08BC + STRUCT dma0_src_region_r DMA0_SRC_REGION; // 0x08C0 + STRUCT dma0_dst_region_r DMA0_DST_REGION; // 0x08C4 + STRUCT dma0_size0_r DMA0_SIZE0; // 0x08C8 + STRUCT dma0_size1_r DMA0_SIZE1; // 0x08CC + uint32_t unused22[12]; + STRUCT ifm2_broadcast_r IFM2_BROADCAST; // 0x0900 + STRUCT ifm2_scalar_r IFM2_SCALAR; // 0x0904 + uint32_t unused23[3]; + STRUCT ifm2_precision_r IFM2_PRECISION; // 0x0914 + uint32_t unused24[3]; + STRUCT ifm2_zero_point_r IFM2_ZERO_POINT; // 0x0924 + STRUCT ifm2_width0_m1_r IFM2_WIDTH0_M1; // 0x0928 + STRUCT ifm2_height0_m1_r IFM2_HEIGHT0_M1; // 0x092C + STRUCT ifm2_height1_m1_r IFM2_HEIGHT1_M1; // 0x0930 + STRUCT ifm2_ib_start_r IFM2_IB_START; // 0x0934 + uint32_t unused25[1]; + STRUCT ifm2_region_r IFM2_REGION; // 0x093C + uint32_t unused26[48]; + STRUCT ifm_base0_r IFM_BASE0; // 0x0A00 + STRUCT ifm_base1_r IFM_BASE1; // 0x0A08 + STRUCT ifm_base2_r IFM_BASE2; // 0x0A10 + STRUCT ifm_base3_r IFM_BASE3; // 0x0A18 + STRUCT ifm_stride_x_r IFM_STRIDE_X; // 0x0A20 + STRUCT ifm_stride_y_r IFM_STRIDE_Y; // 0x0A28 + STRUCT ifm_stride_c_r IFM_STRIDE_C; // 0x0A30 + uint32_t unused27[2]; + STRUCT ofm_base0_r OFM_BASE0; // 0x0A40 + STRUCT ofm_base1_r OFM_BASE1; // 0x0A48 + STRUCT ofm_base2_r OFM_BASE2; // 0x0A50 + STRUCT ofm_base3_r OFM_BASE3; // 0x0A58 + STRUCT ofm_stride_x_r OFM_STRIDE_X; // 0x0A60 + STRUCT ofm_stride_y_r OFM_STRIDE_Y; // 0x0A68 + STRUCT ofm_stride_c_r OFM_STRIDE_C; // 0x0A70 + uint32_t unused28[2]; + STRUCT weight_base_r WEIGHT_BASE; // 0x0A80 + STRUCT weight_length_r WEIGHT_LENGTH; // 0x0A88 + STRUCT scale_base_r SCALE_BASE; // 0x0A90 + STRUCT scale_length_r SCALE_LENGTH; // 0x0A98 + STRUCT ofm_scale_r OFM_SCALE; // 0x0AA0 + STRUCT ofm_scale_shift_r OFM_SCALE_SHIFT; // 0x0AA4 + STRUCT opa_scale_r OPA_SCALE; // 0x0AA8 + STRUCT opa_scale_shift_r OPA_SCALE_SHIFT; // 0x0AAC + STRUCT opb_scale_r OPB_SCALE; // 0x0AB0 + uint32_t unused29[3]; + STRUCT dma0_src_r DMA0_SRC; // 0x0AC0 + STRUCT dma0_dst_r DMA0_DST; // 0x0AC8 + STRUCT dma0_len_r DMA0_LEN; // 0x0AD0 + uint32_t unused30[10]; + STRUCT ifm2_base0_r IFM2_BASE0; // 0x0B00 + STRUCT ifm2_base1_r IFM2_BASE1; // 0x0B08 + STRUCT ifm2_base2_r IFM2_BASE2; // 0x0B10 + STRUCT ifm2_base3_r IFM2_BASE3; // 0x0B18 + STRUCT ifm2_stride_x_r IFM2_STRIDE_X; // 0x0B20 + STRUCT ifm2_stride_y_r IFM2_STRIDE_Y; // 0x0B28 + STRUCT ifm2_stride_c_r IFM2_STRIDE_C; // 0x0B30 + uint32_t unused31[18]; + uint32_t USER_DEFINED[16]; // 0x0B80 + uint32_t unused32[256]; + STRUCT revision_r REVISION; // 0x0FC0 + uint32_t unused33[3]; + STRUCT pid4_r PID4; // 0x0FD0 + STRUCT pid5_r PID5; // 0x0FD4 + STRUCT pid6_r PID6; // 0x0FD8 + STRUCT pid7_r PID7; // 0x0FDC + STRUCT pid0_r PID0; // 0x0FE0 + STRUCT pid1_r PID1; // 0x0FE4 + STRUCT pid2_r PID2; // 0x0FE8 + STRUCT pid3_r PID3; // 0x0FEC + STRUCT cid0_r CID0; // 0x0FF0 + STRUCT cid1_r CID1; // 0x0FF4 + STRUCT cid2_r CID2; // 0x0FF8 + STRUCT cid3_r CID3; // 0x0FFC + +#ifdef __cplusplus + enum class access_type_t : uint8_t + { + RW, + RO, + WO + }; + NPU_REG() + { + reset(); + } + void reset() + { + ID = 269500929; + STATUS = 8; + CMD = 12; + RESET = 0; + QBASE = 0; + QREAD = 0; + QCONFIG = 0; + QSIZE = 0; + PROT = 0; + CONFIG = 0; + LOCK = 0; + REGIONCFG = 0; + AXI_LIMIT0 = 0; + AXI_LIMIT1 = 0; + AXI_LIMIT2 = 0; + AXI_LIMIT3 = 0; + for (size_t i = 0; i < (sizeof(BASEP) / sizeof(BASEP[0])); ++i) + BASEP[i] = 0; + WD_STATUS = 0; + MAC_STATUS = 0; + AO_STATUS = 0; + DMA_STATUS0 = 0; + DMA_STATUS1 = 0; + CLKFORCE = 0; + DEBUG_ADDRESS = 0; + DEBUG_MISC = 0; + DEBUG_BLOCK = 0; + PMCR = 8192; + PMCNTENSET = 0; + PMCNTENCLR = 0; + PMOVSSET = 0; + PMOVSCLR = 0; + PMINTSET = 0; + PMINTCLR = 0; + PMCCNTR = 0; + PMCCNTR_CFG = 0; + PMCAXI_CHAN = 0; + KERNEL_X = 0; + KERNEL_Y = 0; + KERNEL_W_M1 = 0; + KERNEL_H_M1 = 0; + OFM_CBLK_WIDTH_M1 = 0; + OFM_CBLK_HEIGHT_M1 = 0; + OFM_CBLK_DEPTH_M1 = 0; + IFM_CBLK_DEPTH_M1 = 0; + OFM_X = 0; + OFM_Y = 0; + OFM_Z = 0; + IFM_Z = 0; + PAD_TOP = 0; + PAD_LEFT = 0; + IFM_CBLK_WIDTH = 0; + IFM_CBLK_HEIGHT = 0; + DMA_IFM_SRC = 0; + DMA_IFM_DST = 0; + DMA_OFM_SRC = 0; + DMA_OFM_DST = 0; + DMA_WEIGHT_SRC = 0; + DMA_CMD_SRC = 0; + DMA_CMD_SIZE = 0; + DMA_M2M_SRC = 0; + DMA_M2M_DST = 0; + CURRENT_QREAD = 0; + DMA_SCALE_SRC = 0; + CURRENT_BLOCK = 0; + CURRENT_OP = 0; + CURRENT_CMD = 0; + for (size_t i = 0; i < (sizeof(PMEVCNTR) / sizeof(PMEVCNTR[0])); ++i) + PMEVCNTR[i] = 0; + for (size_t i = 0; i < (sizeof(PMEVTYPER) / sizeof(PMEVTYPER[0])); ++i) + PMEVTYPER[i] = 0; + for (size_t i = 0; i < (sizeof(SHARED_BUFFER) / sizeof(SHARED_BUFFER[0])); ++i) + SHARED_BUFFER[i] = 0; + IFM_PAD_TOP = 0; + IFM_PAD_LEFT = 0; + IFM_PAD_RIGHT = 0; + IFM_PAD_BOTTOM = 0; + IFM_DEPTH_M1 = 0; + IFM_PRECISION = 0; + IFM_UPSCALE = 0; + IFM_ZERO_POINT = 0; + IFM_WIDTH0_M1 = 0; + IFM_HEIGHT0_M1 = 0; + IFM_HEIGHT1_M1 = 0; + IFM_IB_END = 0; + IFM_REGION = 0; + OFM_WIDTH_M1 = 0; + OFM_HEIGHT_M1 = 0; + OFM_DEPTH_M1 = 0; + OFM_PRECISION = 0; + OFM_BLK_WIDTH_M1 = 0; + OFM_BLK_HEIGHT_M1 = 0; + OFM_BLK_DEPTH_M1 = 0; + OFM_ZERO_POINT = 0; + OFM_WIDTH0_M1 = 0; + OFM_HEIGHT0_M1 = 0; + OFM_HEIGHT1_M1 = 0; + OFM_REGION = 0; + KERNEL_WIDTH_M1 = 0; + KERNEL_HEIGHT_M1 = 0; + KERNEL_STRIDE = 0; + ACC_FORMAT = 0; + ACTIVATION = 0; + ACTIVATION_MIN = 0; + ACTIVATION_MAX = 0; + WEIGHT_REGION = 0; + SCALE_REGION = 0; + AB_START = 0; + BLOCKDEP = 0; + DMA0_SRC_REGION = 0; + DMA0_DST_REGION = 0; + DMA0_SIZE0 = 0; + DMA0_SIZE1 = 0; + IFM2_BROADCAST = 0; + IFM2_SCALAR = 0; + IFM2_PRECISION = 0; + IFM2_ZERO_POINT = 0; + IFM2_WIDTH0_M1 = 0; + IFM2_HEIGHT0_M1 = 0; + IFM2_HEIGHT1_M1 = 0; + IFM2_IB_START = 0; + IFM2_REGION = 0; + IFM_BASE0 = 0; + IFM_BASE1 = 0; + IFM_BASE2 = 0; + IFM_BASE3 = 0; + IFM_STRIDE_X = 0; + IFM_STRIDE_Y = 0; + IFM_STRIDE_C = 0; + OFM_BASE0 = 0; + OFM_BASE1 = 0; + OFM_BASE2 = 0; + OFM_BASE3 = 0; + OFM_STRIDE_X = 0; + OFM_STRIDE_Y = 0; + OFM_STRIDE_C = 0; + WEIGHT_BASE = 0; + WEIGHT_LENGTH = 0; + SCALE_BASE = 0; + SCALE_LENGTH = 0; + OFM_SCALE = 0; + OFM_SCALE_SHIFT = 0; + OPA_SCALE = 0; + OPA_SCALE_SHIFT = 0; + OPB_SCALE = 0; + DMA0_SRC = 0; + DMA0_DST = 0; + DMA0_LEN = 0; + IFM2_BASE0 = 0; + IFM2_BASE1 = 0; + IFM2_BASE2 = 0; + IFM2_BASE3 = 0; + IFM2_STRIDE_X = 0; + IFM2_STRIDE_Y = 0; + IFM2_STRIDE_C = 0; + for (size_t i = 0; i < (sizeof(USER_DEFINED) / sizeof(USER_DEFINED[0])); ++i) + USER_DEFINED[i] = 0; + REVISION = 0; + PID4 = 4; + PID5 = 0; + PID6 = 0; + PID7 = 0; + PID0 = 128; + PID1 = 181; + PID2 = 11; + PID3 = 0; + CID0 = 13; + CID1 = 240; + CID2 = 5; + CID3 = 177; + } + uint32_t &operator[](const int addr_offset) + { + return reinterpret_cast(this)[addr_offset / 4]; + } + access_type_t get_access_type(uint32_t offset) + { + switch (offset) + { + case 0: + return access_type_t::RO; + case 4: + return access_type_t::RO; + case 8: + return access_type_t::RW; + case 12: + return access_type_t::RW; + case 16: + return access_type_t::RW; + case 24: + return access_type_t::RO; + case 28: + return access_type_t::RW; + case 32: + return access_type_t::RW; + case 36: + return access_type_t::RO; + case 40: + return access_type_t::RO; + case 44: + return access_type_t::RW; + case 60: + return access_type_t::RW; + case 64: + return access_type_t::RW; + case 68: + return access_type_t::RW; + case 72: + return access_type_t::RW; + case 76: + return access_type_t::RW; + case 128: + return access_type_t::RW; + case 136: + return access_type_t::RW; + case 144: + return access_type_t::RW; + case 152: + return access_type_t::RW; + case 160: + return access_type_t::RW; + case 168: + return access_type_t::RW; + case 176: + return access_type_t::RW; + case 184: + return access_type_t::RW; + case 256: + return access_type_t::RO; + case 260: + return access_type_t::RO; + case 264: + return access_type_t::RO; + case 272: + return access_type_t::RO; + case 276: + return access_type_t::RO; + case 320: + return access_type_t::RW; + case 324: + return access_type_t::RW; + case 328: + return access_type_t::RW; + case 336: + return access_type_t::RW; + case 384: + return access_type_t::RW; + case 388: + return access_type_t::RW; + case 392: + return access_type_t::RW; + case 396: + return access_type_t::RW; + case 400: + return access_type_t::RW; + case 404: + return access_type_t::RW; + case 408: + return access_type_t::RW; + case 416: + return access_type_t::RW; + case 424: + return access_type_t::RW; + case 428: + return access_type_t::RW; + case 512: + return access_type_t::RO; + case 516: + return access_type_t::RO; + case 520: + return access_type_t::RO; + case 524: + return access_type_t::RO; + case 528: + return access_type_t::RO; + case 532: + return access_type_t::RO; + case 536: + return access_type_t::RO; + case 540: + return access_type_t::RO; + case 544: + return access_type_t::RO; + case 548: + return access_type_t::RO; + case 552: + return access_type_t::RO; + case 556: + return access_type_t::RO; + case 560: + return access_type_t::RO; + case 564: + return access_type_t::RO; + case 568: + return access_type_t::RO; + case 572: + return access_type_t::RO; + case 576: + return access_type_t::RO; + case 584: + return access_type_t::RO; + case 588: + return access_type_t::RO; + case 592: + return access_type_t::RO; + case 600: + return access_type_t::RO; + case 608: + return access_type_t::RO; + case 616: + return access_type_t::RO; + case 620: + return access_type_t::RO; + case 628: + return access_type_t::RO; + case 636: + return access_type_t::RO; + case 640: + return access_type_t::RO; + case 692: + return access_type_t::RO; + case 696: + return access_type_t::RO; + case 700: + return access_type_t::RO; + case 768: + return access_type_t::RW; + case 772: + return access_type_t::RW; + case 776: + return access_type_t::RW; + case 780: + return access_type_t::RW; + case 896: + return access_type_t::RW; + case 900: + return access_type_t::RW; + case 904: + return access_type_t::RW; + case 908: + return access_type_t::RW; + case 1024: + return access_type_t::RW; + case 1028: + return access_type_t::RW; + case 1032: + return access_type_t::RW; + case 1036: + return access_type_t::RW; + case 1040: + return access_type_t::RW; + case 1044: + return access_type_t::RW; + case 1048: + return access_type_t::RW; + case 1052: + return access_type_t::RW; + case 1056: + return access_type_t::RW; + case 1060: + return access_type_t::RW; + case 1064: + return access_type_t::RW; + case 1068: + return access_type_t::RW; + case 1072: + return access_type_t::RW; + case 1076: + return access_type_t::RW; + case 1080: + return access_type_t::RW; + case 1084: + return access_type_t::RW; + case 1088: + return access_type_t::RW; + case 1092: + return access_type_t::RW; + case 1096: + return access_type_t::RW; + case 1100: + return access_type_t::RW; + case 1104: + return access_type_t::RW; + case 1108: + return access_type_t::RW; + case 1112: + return access_type_t::RW; + case 1116: + return access_type_t::RW; + case 1120: + return access_type_t::RW; + case 1124: + return access_type_t::RW; + case 1128: + return access_type_t::RW; + case 1132: + return access_type_t::RW; + case 1136: + return access_type_t::RW; + case 1140: + return access_type_t::RW; + case 1144: + return access_type_t::RW; + case 1148: + return access_type_t::RW; + case 1152: + return access_type_t::RW; + case 1156: + return access_type_t::RW; + case 1160: + return access_type_t::RW; + case 1164: + return access_type_t::RW; + case 1168: + return access_type_t::RW; + case 1172: + return access_type_t::RW; + case 1176: + return access_type_t::RW; + case 1180: + return access_type_t::RW; + case 1184: + return access_type_t::RW; + case 1188: + return access_type_t::RW; + case 1192: + return access_type_t::RW; + case 1196: + return access_type_t::RW; + case 1200: + return access_type_t::RW; + case 1204: + return access_type_t::RW; + case 1208: + return access_type_t::RW; + case 1212: + return access_type_t::RW; + case 1216: + return access_type_t::RW; + case 1220: + return access_type_t::RW; + case 1224: + return access_type_t::RW; + case 1228: + return access_type_t::RW; + case 1232: + return access_type_t::RW; + case 1236: + return access_type_t::RW; + case 1240: + return access_type_t::RW; + case 1244: + return access_type_t::RW; + case 1248: + return access_type_t::RW; + case 1252: + return access_type_t::RW; + case 1256: + return access_type_t::RW; + case 1260: + return access_type_t::RW; + case 1264: + return access_type_t::RW; + case 1268: + return access_type_t::RW; + case 1272: + return access_type_t::RW; + case 1276: + return access_type_t::RW; + case 1280: + return access_type_t::RW; + case 1284: + return access_type_t::RW; + case 1288: + return access_type_t::RW; + case 1292: + return access_type_t::RW; + case 1296: + return access_type_t::RW; + case 1300: + return access_type_t::RW; + case 1304: + return access_type_t::RW; + case 1308: + return access_type_t::RW; + case 1312: + return access_type_t::RW; + case 1316: + return access_type_t::RW; + case 1320: + return access_type_t::RW; + case 1324: + return access_type_t::RW; + case 1328: + return access_type_t::RW; + case 1332: + return access_type_t::RW; + case 1336: + return access_type_t::RW; + case 1340: + return access_type_t::RW; + case 1344: + return access_type_t::RW; + case 1348: + return access_type_t::RW; + case 1352: + return access_type_t::RW; + case 1356: + return access_type_t::RW; + case 1360: + return access_type_t::RW; + case 1364: + return access_type_t::RW; + case 1368: + return access_type_t::RW; + case 1372: + return access_type_t::RW; + case 1376: + return access_type_t::RW; + case 1380: + return access_type_t::RW; + case 1384: + return access_type_t::RW; + case 1388: + return access_type_t::RW; + case 1392: + return access_type_t::RW; + case 1396: + return access_type_t::RW; + case 1400: + return access_type_t::RW; + case 1404: + return access_type_t::RW; + case 1408: + return access_type_t::RW; + case 1412: + return access_type_t::RW; + case 1416: + return access_type_t::RW; + case 1420: + return access_type_t::RW; + case 1424: + return access_type_t::RW; + case 1428: + return access_type_t::RW; + case 1432: + return access_type_t::RW; + case 1436: + return access_type_t::RW; + case 1440: + return access_type_t::RW; + case 1444: + return access_type_t::RW; + case 1448: + return access_type_t::RW; + case 1452: + return access_type_t::RW; + case 1456: + return access_type_t::RW; + case 1460: + return access_type_t::RW; + case 1464: + return access_type_t::RW; + case 1468: + return access_type_t::RW; + case 1472: + return access_type_t::RW; + case 1476: + return access_type_t::RW; + case 1480: + return access_type_t::RW; + case 1484: + return access_type_t::RW; + case 1488: + return access_type_t::RW; + case 1492: + return access_type_t::RW; + case 1496: + return access_type_t::RW; + case 1500: + return access_type_t::RW; + case 1504: + return access_type_t::RW; + case 1508: + return access_type_t::RW; + case 1512: + return access_type_t::RW; + case 1516: + return access_type_t::RW; + case 1520: + return access_type_t::RW; + case 1524: + return access_type_t::RW; + case 1528: + return access_type_t::RW; + case 1532: + return access_type_t::RW; + case 1536: + return access_type_t::RW; + case 1540: + return access_type_t::RW; + case 1544: + return access_type_t::RW; + case 1548: + return access_type_t::RW; + case 1552: + return access_type_t::RW; + case 1556: + return access_type_t::RW; + case 1560: + return access_type_t::RW; + case 1564: + return access_type_t::RW; + case 1568: + return access_type_t::RW; + case 1572: + return access_type_t::RW; + case 1576: + return access_type_t::RW; + case 1580: + return access_type_t::RW; + case 1584: + return access_type_t::RW; + case 1588: + return access_type_t::RW; + case 1592: + return access_type_t::RW; + case 1596: + return access_type_t::RW; + case 1600: + return access_type_t::RW; + case 1604: + return access_type_t::RW; + case 1608: + return access_type_t::RW; + case 1612: + return access_type_t::RW; + case 1616: + return access_type_t::RW; + case 1620: + return access_type_t::RW; + case 1624: + return access_type_t::RW; + case 1628: + return access_type_t::RW; + case 1632: + return access_type_t::RW; + case 1636: + return access_type_t::RW; + case 1640: + return access_type_t::RW; + case 1644: + return access_type_t::RW; + case 1648: + return access_type_t::RW; + case 1652: + return access_type_t::RW; + case 1656: + return access_type_t::RW; + case 1660: + return access_type_t::RW; + case 1664: + return access_type_t::RW; + case 1668: + return access_type_t::RW; + case 1672: + return access_type_t::RW; + case 1676: + return access_type_t::RW; + case 1680: + return access_type_t::RW; + case 1684: + return access_type_t::RW; + case 1688: + return access_type_t::RW; + case 1692: + return access_type_t::RW; + case 1696: + return access_type_t::RW; + case 1700: + return access_type_t::RW; + case 1704: + return access_type_t::RW; + case 1708: + return access_type_t::RW; + case 1712: + return access_type_t::RW; + case 1716: + return access_type_t::RW; + case 1720: + return access_type_t::RW; + case 1724: + return access_type_t::RW; + case 1728: + return access_type_t::RW; + case 1732: + return access_type_t::RW; + case 1736: + return access_type_t::RW; + case 1740: + return access_type_t::RW; + case 1744: + return access_type_t::RW; + case 1748: + return access_type_t::RW; + case 1752: + return access_type_t::RW; + case 1756: + return access_type_t::RW; + case 1760: + return access_type_t::RW; + case 1764: + return access_type_t::RW; + case 1768: + return access_type_t::RW; + case 1772: + return access_type_t::RW; + case 1776: + return access_type_t::RW; + case 1780: + return access_type_t::RW; + case 1784: + return access_type_t::RW; + case 1788: + return access_type_t::RW; + case 1792: + return access_type_t::RW; + case 1796: + return access_type_t::RW; + case 1800: + return access_type_t::RW; + case 1804: + return access_type_t::RW; + case 1808: + return access_type_t::RW; + case 1812: + return access_type_t::RW; + case 1816: + return access_type_t::RW; + case 1820: + return access_type_t::RW; + case 1824: + return access_type_t::RW; + case 1828: + return access_type_t::RW; + case 1832: + return access_type_t::RW; + case 1836: + return access_type_t::RW; + case 1840: + return access_type_t::RW; + case 1844: + return access_type_t::RW; + case 1848: + return access_type_t::RW; + case 1852: + return access_type_t::RW; + case 1856: + return access_type_t::RW; + case 1860: + return access_type_t::RW; + case 1864: + return access_type_t::RW; + case 1868: + return access_type_t::RW; + case 1872: + return access_type_t::RW; + case 1876: + return access_type_t::RW; + case 1880: + return access_type_t::RW; + case 1884: + return access_type_t::RW; + case 1888: + return access_type_t::RW; + case 1892: + return access_type_t::RW; + case 1896: + return access_type_t::RW; + case 1900: + return access_type_t::RW; + case 1904: + return access_type_t::RW; + case 1908: + return access_type_t::RW; + case 1912: + return access_type_t::RW; + case 1916: + return access_type_t::RW; + case 1920: + return access_type_t::RW; + case 1924: + return access_type_t::RW; + case 1928: + return access_type_t::RW; + case 1932: + return access_type_t::RW; + case 1936: + return access_type_t::RW; + case 1940: + return access_type_t::RW; + case 1944: + return access_type_t::RW; + case 1948: + return access_type_t::RW; + case 1952: + return access_type_t::RW; + case 1956: + return access_type_t::RW; + case 1960: + return access_type_t::RW; + case 1964: + return access_type_t::RW; + case 1968: + return access_type_t::RW; + case 1972: + return access_type_t::RW; + case 1976: + return access_type_t::RW; + case 1980: + return access_type_t::RW; + case 1984: + return access_type_t::RW; + case 1988: + return access_type_t::RW; + case 1992: + return access_type_t::RW; + case 1996: + return access_type_t::RW; + case 2000: + return access_type_t::RW; + case 2004: + return access_type_t::RW; + case 2008: + return access_type_t::RW; + case 2012: + return access_type_t::RW; + case 2016: + return access_type_t::RW; + case 2020: + return access_type_t::RW; + case 2024: + return access_type_t::RW; + case 2028: + return access_type_t::RW; + case 2032: + return access_type_t::RW; + case 2036: + return access_type_t::RW; + case 2040: + return access_type_t::RW; + case 2044: + return access_type_t::RW; + case 2048: + return access_type_t::RW; + case 2052: + return access_type_t::RW; + case 2056: + return access_type_t::RW; + case 2060: + return access_type_t::RW; + case 2064: + return access_type_t::RW; + case 2068: + return access_type_t::RW; + case 2076: + return access_type_t::RW; + case 2084: + return access_type_t::RW; + case 2088: + return access_type_t::RW; + case 2092: + return access_type_t::RW; + case 2096: + return access_type_t::RW; + case 2100: + return access_type_t::RW; + case 2108: + return access_type_t::RW; + case 2116: + return access_type_t::RW; + case 2120: + return access_type_t::RW; + case 2124: + return access_type_t::RW; + case 2128: + return access_type_t::RW; + case 2132: + return access_type_t::RW; + case 2136: + return access_type_t::RW; + case 2140: + return access_type_t::RW; + case 2144: + return access_type_t::RW; + case 2152: + return access_type_t::RW; + case 2156: + return access_type_t::RW; + case 2160: + return access_type_t::RW; + case 2172: + return access_type_t::RW; + case 2176: + return access_type_t::RW; + case 2180: + return access_type_t::RW; + case 2184: + return access_type_t::RW; + case 2192: + return access_type_t::RW; + case 2196: + return access_type_t::RW; + case 2200: + return access_type_t::RW; + case 2204: + return access_type_t::RW; + case 2208: + return access_type_t::RW; + case 2212: + return access_type_t::RW; + case 2228: + return access_type_t::RW; + case 2236: + return access_type_t::RW; + case 2240: + return access_type_t::RW; + case 2244: + return access_type_t::RW; + case 2248: + return access_type_t::RW; + case 2252: + return access_type_t::RW; + case 2304: + return access_type_t::RW; + case 2308: + return access_type_t::RW; + case 2324: + return access_type_t::RW; + case 2340: + return access_type_t::RW; + case 2344: + return access_type_t::RW; + case 2348: + return access_type_t::RW; + case 2352: + return access_type_t::RW; + case 2356: + return access_type_t::RW; + case 2364: + return access_type_t::RW; + case 2560: + return access_type_t::RW; + case 2568: + return access_type_t::RW; + case 2576: + return access_type_t::RW; + case 2584: + return access_type_t::RW; + case 2592: + return access_type_t::RW; + case 2600: + return access_type_t::RW; + case 2608: + return access_type_t::RW; + case 2624: + return access_type_t::RW; + case 2632: + return access_type_t::RW; + case 2640: + return access_type_t::RW; + case 2648: + return access_type_t::RW; + case 2656: + return access_type_t::RW; + case 2664: + return access_type_t::RW; + case 2672: + return access_type_t::RW; + case 2688: + return access_type_t::RW; + case 2696: + return access_type_t::RW; + case 2704: + return access_type_t::RW; + case 2712: + return access_type_t::RW; + case 2720: + return access_type_t::RW; + case 2724: + return access_type_t::RW; + case 2728: + return access_type_t::RW; + case 2732: + return access_type_t::RW; + case 2736: + return access_type_t::RW; + case 2752: + return access_type_t::RW; + case 2760: + return access_type_t::RW; + case 2768: + return access_type_t::RW; + case 2816: + return access_type_t::RW; + case 2824: + return access_type_t::RW; + case 2832: + return access_type_t::RW; + case 2840: + return access_type_t::RW; + case 2848: + return access_type_t::RW; + case 2856: + return access_type_t::RW; + case 2864: + return access_type_t::RW; + case 2944: + return access_type_t::RW; + case 2952: + return access_type_t::RW; + case 2960: + return access_type_t::RW; + case 2968: + return access_type_t::RW; + case 2976: + return access_type_t::RW; + case 2984: + return access_type_t::RW; + case 2992: + return access_type_t::RW; + case 3000: + return access_type_t::RW; + case 4032: + return access_type_t::RO; + case 4048: + return access_type_t::RO; + case 4052: + return access_type_t::RO; + case 4056: + return access_type_t::RO; + case 4060: + return access_type_t::RO; + case 4064: + return access_type_t::RO; + case 4068: + return access_type_t::RO; + case 4072: + return access_type_t::RO; + case 4076: + return access_type_t::RO; + case 4080: + return access_type_t::RO; + case 4084: + return access_type_t::RO; + case 4088: + return access_type_t::RO; + case 4092: + return access_type_t::RO; + default: + return access_type_t::RO; + } + } +#endif +}; + +#ifdef __cplusplus +struct isa +{ +#ifdef NPU_DISASSEMBLE + static int disassemble(const uint32_t *in, + std::string &op, + std::vector> &fields) + { + switch (*in & 0xffff) + { + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP): + { + const npu_op_stop_t &v = *reinterpret_cast(in); + op = "NPU_OP_STOP"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ): + { + const npu_op_irq_t &v = *reinterpret_cast(in); + op = "NPU_OP_IRQ"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV): + { + const npu_op_conv_t &v = *reinterpret_cast(in); + op = "NPU_OP_CONV"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE): + { + const npu_op_depthwise_t &v = *reinterpret_cast(in); + op = "NPU_OP_DEPTHWISE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL): + { + const npu_op_pool_t &v = *reinterpret_cast(in); + op = "NPU_OP_POOL"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE): + { + const npu_op_elementwise_t &v = *reinterpret_cast(in); + op = "NPU_OP_ELEMENTWISE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START): + { + const npu_op_dma_start_t &v = *reinterpret_cast(in); + op = "NPU_OP_DMA_START"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT): + { + const npu_op_dma_wait_t &v = *reinterpret_cast(in); + op = "NPU_OP_DMA_WAIT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT): + { + const npu_op_kernel_wait_t &v = *reinterpret_cast(in); + op = "NPU_OP_KERNEL_WAIT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK): + { + const npu_op_pmu_mask_t &v = *reinterpret_cast(in); + op = "NPU_OP_PMU_MASK"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP): + { + const npu_set_ifm_pad_top_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_TOP"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT): + { + const npu_set_ifm_pad_left_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_LEFT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT): + { + const npu_set_ifm_pad_right_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_RIGHT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM): + { + const npu_set_ifm_pad_bottom_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_BOTTOM"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1): + { + const npu_set_ifm_depth_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_DEPTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION): + { + const npu_set_ifm_precision_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PRECISION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE): + { + const npu_set_ifm_upscale_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_UPSCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT): + { + const npu_set_ifm_zero_point_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_ZERO_POINT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1): + { + const npu_set_ifm_width0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_WIDTH0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1): + { + const npu_set_ifm_height0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_HEIGHT0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1): + { + const npu_set_ifm_height1_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_HEIGHT1_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END): + { + const npu_set_ifm_ib_end_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_IB_END"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION): + { + const npu_set_ifm_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1): + { + const npu_set_ofm_width_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_WIDTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1): + { + const npu_set_ofm_height_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_HEIGHT_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1): + { + const npu_set_ofm_depth_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_DEPTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION): + { + const npu_set_ofm_precision_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_PRECISION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1): + { + const npu_set_ofm_blk_width_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BLK_WIDTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1): + { + const npu_set_ofm_blk_height_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BLK_HEIGHT_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1): + { + const npu_set_ofm_blk_depth_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BLK_DEPTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT): + { + const npu_set_ofm_zero_point_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_ZERO_POINT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1): + { + const npu_set_ofm_width0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_WIDTH0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1): + { + const npu_set_ofm_height0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_HEIGHT0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1): + { + const npu_set_ofm_height1_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_HEIGHT1_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION): + { + const npu_set_ofm_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1): + { + const npu_set_kernel_width_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_KERNEL_WIDTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1): + { + const npu_set_kernel_height_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_KERNEL_HEIGHT_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE): + { + const npu_set_kernel_stride_t &v = *reinterpret_cast(in); + op = "NPU_SET_KERNEL_STRIDE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT): + { + const npu_set_acc_format_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACC_FORMAT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION): + { + const npu_set_activation_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACTIVATION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN): + { + const npu_set_activation_min_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACTIVATION_MIN"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX): + { + const npu_set_activation_max_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACTIVATION_MAX"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION): + { + const npu_set_weight_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION): + { + const npu_set_scale_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START): + { + const npu_set_ab_start_t &v = *reinterpret_cast(in); + op = "NPU_SET_AB_START"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP): + { + const npu_set_blockdep_t &v = *reinterpret_cast(in); + op = "NPU_SET_BLOCKDEP"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION): + { + const npu_set_dma0_src_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SRC_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION): + { + const npu_set_dma0_dst_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_DST_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0): + { + const npu_set_dma0_size0_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SIZE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1): + { + const npu_set_dma0_size1_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SIZE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST): + { + const npu_set_ifm2_broadcast_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BROADCAST"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR): + { + const npu_set_ifm2_scalar_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_SCALAR"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION): + { + const npu_set_ifm2_precision_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_PRECISION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT): + { + const npu_set_ifm2_zero_point_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_ZERO_POINT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1): + { + const npu_set_ifm2_width0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_WIDTH0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1): + { + const npu_set_ifm2_height0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_HEIGHT0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1): + { + const npu_set_ifm2_height1_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_HEIGHT1_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START): + { + const npu_set_ifm2_ib_start_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_IB_START"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION): + { + const npu_set_ifm2_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0): + { + const npu_set_ifm_base0_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1): + { + const npu_set_ifm_base1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2): + { + const npu_set_ifm_base2_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE2"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3): + { + const npu_set_ifm_base3_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE3"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X): + { + const npu_set_ifm_stride_x_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_STRIDE_X"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y): + { + const npu_set_ifm_stride_y_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_STRIDE_Y"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C): + { + const npu_set_ifm_stride_c_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_STRIDE_C"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0): + { + const npu_set_ofm_base0_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1): + { + const npu_set_ofm_base1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2): + { + const npu_set_ofm_base2_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE2"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3): + { + const npu_set_ofm_base3_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE3"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X): + { + const npu_set_ofm_stride_x_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_STRIDE_X"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y): + { + const npu_set_ofm_stride_y_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_STRIDE_Y"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C): + { + const npu_set_ofm_stride_c_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_STRIDE_C"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE): + { + const npu_set_weight_base_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT_BASE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH): + { + const npu_set_weight_length_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT_LENGTH"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE): + { + const npu_set_scale_base_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE_BASE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH): + { + const npu_set_scale_length_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE_LENGTH"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE): + { + const npu_set_ofm_scale_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_SCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE): + { + const npu_set_opa_scale_t &v = *reinterpret_cast(in); + op = "NPU_SET_OPA_SCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE): + { + const npu_set_opb_scale_t &v = *reinterpret_cast(in); + op = "NPU_SET_OPB_SCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC): + { + const npu_set_dma0_src_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SRC"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST): + { + const npu_set_dma0_dst_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_DST"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN): + { + const npu_set_dma0_len_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_LEN"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0): + { + const npu_set_ifm2_base0_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1): + { + const npu_set_ifm2_base1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2): + { + const npu_set_ifm2_base2_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE2"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3): + { + const npu_set_ifm2_base3_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE3"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X): + { + const npu_set_ifm2_stride_x_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_STRIDE_X"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y): + { + const npu_set_ifm2_stride_y_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_STRIDE_Y"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C): + { + const npu_set_ifm2_stride_c_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_STRIDE_C"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED0): + { + const npu_set_user_defined0_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED1): + { + const npu_set_user_defined1_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED2): + { + const npu_set_user_defined2_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED2"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED3): + { + const npu_set_user_defined3_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED3"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED4): + { + const npu_set_user_defined4_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED4"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED5): + { + const npu_set_user_defined5_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED5"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED6): + { + const npu_set_user_defined6_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED6"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED7): + { + const npu_set_user_defined7_t &v = *reinterpret_cast(in); + op = "NPU_SET_USER_DEFINED7"; + v.disassemble(fields); + break; + } + } + return (*in & (3 << 14)) != 0 ? 2 : 1; + } +#endif +#endif + // Signal the end of command stream + struct npu_op_stop_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t mask : 16; // Encoding for 16-bit mask value +#ifdef __cplusplus + public: + npu_op_stop_t(uint32_t _mask) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_op_stop_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_stop_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_stop_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_mask() const + { + return static_cast(mask); + } + CONSTEXPR npu_op_stop_t &set_mask(uint32_t value) + { + mask = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("mask", std::to_string(mask))); + } +#endif +#endif + }; + // Raises an IRQ to the host + struct npu_op_irq_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t mask : 16; // Encoding for 16-bit mask value +#ifdef __cplusplus + public: + npu_op_irq_t(uint32_t _mask) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_op_irq_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_irq_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_irq_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_mask() const + { + return static_cast(mask); + } + CONSTEXPR npu_op_irq_t &set_mask(uint32_t value) + { + mask = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("mask", std::to_string(mask))); + } +#endif +#endif + }; + // 2D convolution + struct npu_op_conv_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; +#ifdef __cplusplus + public: + CONSTEXPR npu_op_conv_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_conv_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_conv_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const {} +#endif +#endif + }; + // Depth-wise 2D convolution + struct npu_op_depthwise_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; +#ifdef __cplusplus + public: + CONSTEXPR npu_op_depthwise_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_depthwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_depthwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const {} +#endif +#endif + }; + // Pooling + struct npu_op_pool_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pooling_mode : 3; // Pooling mode + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_op_pool_t(NPU_NAMESPACE::pooling_mode _pooling_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + pooling_mode(static_cast(_pooling_mode) & ((1U << 3) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_pool_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pooling_mode(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_pool_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_pool_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::pooling_mode get_pooling_mode() const + { + return static_cast(pooling_mode); + } + CONSTEXPR npu_op_pool_t &set_pooling_mode(NPU_NAMESPACE::pooling_mode value) + { + pooling_mode = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "pooling_mode", + (pooling_mode < (sizeof(pooling_mode_str) / sizeof(pooling_mode_str[0])) ? + pooling_mode_str[pooling_mode] : + "****"))); + } +#endif +#endif + }; + // Elementwise operation + struct npu_op_elementwise_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t elementwise_mode : 6; // Elementwise mode + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_op_elementwise_t(NPU_NAMESPACE::elementwise_mode _elementwise_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + elementwise_mode(static_cast(_elementwise_mode) & ((1U << 6) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_elementwise_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), elementwise_mode(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_elementwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_elementwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::elementwise_mode get_elementwise_mode() const + { + return static_cast(elementwise_mode); + } + CONSTEXPR npu_op_elementwise_t &set_elementwise_mode(NPU_NAMESPACE::elementwise_mode value) + { + elementwise_mode = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "elementwise_mode", + (elementwise_mode < (sizeof(elementwise_mode_str) / sizeof(elementwise_mode_str[0])) ? + elementwise_mode_str[elementwise_mode] : + "****"))); + } +#endif +#endif + }; + // Queue new DMA for the given channel + struct npu_op_dma_start_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; +#ifdef __cplusplus + public: + CONSTEXPR npu_op_dma_start_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_dma_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_dma_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const {} +#endif +#endif + }; + // Wait for the DMA channel to have k or fewer active descriptors outstanding + struct npu_op_dma_wait_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t k : 4; // Number of outstanding descriptors + uint32_t reserved1 : 12; +#ifdef __cplusplus + public: + npu_op_dma_wait_t(uint32_t _k) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(_k & ((1U << 4) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_dma_wait_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_dma_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_dma_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_k() const + { + return static_cast(k); + } + CONSTEXPR npu_op_dma_wait_t &set_k(uint32_t value) + { + k = static_cast(value) & ((1U << 4) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("k", std::to_string(k))); + } +#endif +#endif + }; + // Wait for n or fewer kernel operations to be remaining + struct npu_op_kernel_wait_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t n : 2; // Number of kernel operations in range 0-3 + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_op_kernel_wait_t(uint32_t _n) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(_n & ((1U << 2) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_kernel_wait_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_kernel_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_kernel_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_n() const + { + return static_cast(n); + } + CONSTEXPR npu_op_kernel_wait_t &set_n(uint32_t value) + { + n = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("n", std::to_string(n))); + } +#endif +#endif + }; + // Enable or disable PMU counting (debug feature only) + struct npu_op_pmu_mask_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t enable : 1; // Enable or disable PMU mask + uint32_t reserved1 : 15; +#ifdef __cplusplus + public: + npu_op_pmu_mask_t(uint32_t _enable) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(_enable & ((1U << 1) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_op_pmu_mask_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_pmu_mask_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_pmu_mask_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_enable() const + { + return static_cast(enable); + } + CONSTEXPR npu_op_pmu_mask_t &set_enable(uint32_t value) + { + enable = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("enable", std::to_string(enable))); + } +#endif +#endif + }; + // IFM top pad + struct npu_set_ifm_pad_top_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 7; // IFM top pad + uint32_t reserved1 : 9; +#ifdef __cplusplus + public: + npu_set_ifm_pad_top_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_top_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_top_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_top_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_top_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 7) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // IFM left pad + struct npu_set_ifm_pad_left_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 7; // IFM left pad + uint32_t reserved1 : 9; +#ifdef __cplusplus + public: + npu_set_ifm_pad_left_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_left_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_left_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_left_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_left_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 7) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // IFM right pad + struct npu_set_ifm_pad_right_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 8; // IFM right pad. Max value is 128 + uint32_t reserved1 : 8; +#ifdef __cplusplus + public: + npu_set_ifm_pad_right_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_right_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_right_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_right_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_right_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 8) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // IFM bottom pad + struct npu_set_ifm_pad_bottom_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 8; // IFM bottom pad. Max value is 128 + uint32_t reserved1 : 8; +#ifdef __cplusplus + public: + npu_set_ifm_pad_bottom_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_bottom_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_bottom_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_bottom_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_bottom_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 8) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // Number of input channels for convolution + struct npu_set_ifm_depth_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t depth_m1 : 16; // Number of input channels for convolution +#ifdef __cplusplus + public: + npu_set_ifm_depth_m1_t(uint32_t _depth_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_depth_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_depth_m1() const + { + return static_cast(depth_m1); + } + CONSTEXPR npu_set_ifm_depth_m1_t &set_depth_m1(uint32_t value) + { + depth_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("depth_m1", std::to_string(depth_m1))); + } +#endif +#endif + }; + // IFM Precision + struct npu_set_ifm_precision_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_type : 1; // IFM type + uint32_t reserved1 : 1; + uint32_t activation_precision : 2; // IFM precision + uint32_t reserved2 : 2; + uint32_t activation_format : 2; // IFM format + uint32_t scale_mode : 2; // IFM scale mode + uint32_t reserved3 : 4; + uint32_t round_mode : 2; // IFM round mode +#ifdef __cplusplus + public: + npu_set_ifm_precision_t(NPU_NAMESPACE::activation_type _activation_type, + NPU_NAMESPACE::activation_precision _activation_precision, + NPU_NAMESPACE::activation_format _activation_format, + NPU_NAMESPACE::ifm_scale_mode _scale_mode, + NPU_NAMESPACE::round_mode _round_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_type(static_cast(_activation_type) & ((1U << 1) - 1)), reserved1(0), + activation_precision(static_cast(_activation_precision) & ((1U << 2) - 1)), reserved2(0), + activation_format(static_cast(_activation_format) & ((1U << 2) - 1)), + scale_mode(static_cast(_scale_mode) & ((1U << 2) - 1)), reserved3(0), + round_mode(static_cast(_round_mode) & ((1U << 2) - 1)) + { + } + CONSTEXPR npu_set_ifm_precision_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), reserved1(0), + activation_precision(0), reserved2(0), activation_format(0), scale_mode(0), reserved3(0), round_mode(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const + { + return static_cast(activation_type); + } + CONSTEXPR npu_set_ifm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value) + { + activation_type = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const + { + return static_cast(activation_precision); + } + CONSTEXPR npu_set_ifm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value) + { + activation_precision = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const + { + return static_cast(activation_format); + } + CONSTEXPR npu_set_ifm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value) + { + activation_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ifm_scale_mode get_scale_mode() const + { + return static_cast(scale_mode); + } + CONSTEXPR npu_set_ifm_precision_t &set_scale_mode(NPU_NAMESPACE::ifm_scale_mode value) + { + scale_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const + { + return static_cast(round_mode); + } + CONSTEXPR npu_set_ifm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value) + { + round_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_type", + (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ? + activation_type_str[activation_type] : + "****"))); + fields.push_back(std::make_pair( + "activation_precision", + (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ? + activation_precision_str[activation_precision] : + "****"))); + fields.push_back(std::make_pair( + "activation_format", + (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ? + activation_format_str[activation_format] : + "****"))); + fields.push_back(std::make_pair( + "scale_mode", + (scale_mode < (sizeof(ifm_scale_mode_str) / sizeof(ifm_scale_mode_str[0])) ? + ifm_scale_mode_str[scale_mode] : + "****"))); + fields.push_back(std::make_pair( + "round_mode", + (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] : + "****"))); + } +#endif +#endif + }; + // IFM upscale mode + struct npu_set_ifm_upscale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t mode : 2; // IFM upscale mode + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_set_ifm_upscale_t(NPU_NAMESPACE::ifm_upscale_mode _mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + mode(static_cast(_mode) & ((1U << 2) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_upscale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mode(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_upscale_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_upscale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ifm_upscale_mode get_mode() const + { + return static_cast(mode); + } + CONSTEXPR npu_set_ifm_upscale_t &set_mode(NPU_NAMESPACE::ifm_upscale_mode value) + { + mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "mode", + (mode < (sizeof(ifm_upscale_mode_str) / sizeof(ifm_upscale_mode_str[0])) ? ifm_upscale_mode_str[mode] : + "****"))); + } +#endif +#endif + }; + // IFM zero point + struct npu_set_ifm_zero_point_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t zero_point : 16; // Zero point offset +#ifdef __cplusplus + public: + npu_set_ifm_zero_point_t(uint32_t _zero_point) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + zero_point(_zero_point & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_zero_point_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_zero_point() const + { + return static_cast(zero_point); + } + CONSTEXPR npu_set_ifm_zero_point_t &set_zero_point(uint32_t value) + { + zero_point = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("zero_point", std::to_string(zero_point))); + } +#endif +#endif + }; + // IFM Tile 0 and tile 2 width + struct npu_set_ifm_width0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // IFM Tile 0 and tile 2 width +#ifdef __cplusplus + public: + npu_set_ifm_width0_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_width0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ifm_width0_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // IFM Tile 0 height + struct npu_set_ifm_height0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM Tile 0 height +#ifdef __cplusplus + public: + npu_set_ifm_height0_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_height0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm_height0_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // IFM Tile 1 height + struct npu_set_ifm_height1_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM Tile 1 height +#ifdef __cplusplus + public: + npu_set_ifm_height1_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_height1_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm_height1_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // End of IB0,IB1 buffers + struct npu_set_ifm_ib_end_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t ib_end : 6; // End of IB0,IB1 buffers in the SHRAM in KB units. Multiple of 2 + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ifm_ib_end_t(uint32_t _ib_end) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(_ib_end & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ifm_ib_end_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_ib_end_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_ib_end_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_ib_end() const + { + return static_cast(ib_end); + } + CONSTEXPR npu_set_ifm_ib_end_t &set_ib_end(uint32_t value) + { + ib_end = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("ib_end", std::to_string(ib_end))); + } +#endif +#endif + }; + // Index n for IFM access + struct npu_set_ifm_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Region number n + uint32_t reserved1 : 12; + uint32_t custom_dma_cs : 1; // Custom DMA select +#ifdef __cplusplus + public: + npu_set_ifm_region_t(uint32_t _region, NPU_NAMESPACE::custom_dma_cs _custom_dma_cs) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0), custom_dma_cs(static_cast(_custom_dma_cs) & ((1U << 1) - 1)) + { + } + CONSTEXPR npu_set_ifm_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), custom_dma_cs(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_ifm_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma_cs get_custom_dma_cs() const + { + return static_cast(custom_dma_cs); + } + CONSTEXPR npu_set_ifm_region_t &set_custom_dma_cs(NPU_NAMESPACE::custom_dma_cs value) + { + custom_dma_cs = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "custom_dma_cs", + (custom_dma_cs < (sizeof(custom_dma_cs_str) / sizeof(custom_dma_cs_str[0])) ? + custom_dma_cs_str[custom_dma_cs] : + "****"))); + } +#endif +#endif + }; + // Output feature map width + struct npu_set_ofm_width_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // Output feature map width +#ifdef __cplusplus + public: + npu_set_ofm_width_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_width_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ofm_width_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // Output feature map height + struct npu_set_ofm_height_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // Output feature map height +#ifdef __cplusplus + public: + npu_set_ofm_height_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_height_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_height_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Output feature map depth + struct npu_set_ofm_depth_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t depth_m1 : 16; // Output feature map depth +#ifdef __cplusplus + public: + npu_set_ofm_depth_m1_t(uint32_t _depth_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_depth_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_depth_m1() const + { + return static_cast(depth_m1); + } + CONSTEXPR npu_set_ofm_depth_m1_t &set_depth_m1(uint32_t value) + { + depth_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("depth_m1", std::to_string(depth_m1))); + } +#endif +#endif + }; + // OFM Precision + struct npu_set_ofm_precision_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_type : 1; // OFM type + uint32_t activation_precision : 2; // OFM precision + uint32_t reserved1 : 3; + uint32_t activation_format : 2; // OFM format + uint32_t scale_mode : 1; // OFM scale mode + uint32_t reserved2 : 5; + uint32_t round_mode : 2; // OFM round mode +#ifdef __cplusplus + public: + npu_set_ofm_precision_t(NPU_NAMESPACE::activation_type _activation_type, + NPU_NAMESPACE::activation_precision _activation_precision, + NPU_NAMESPACE::activation_format _activation_format, + NPU_NAMESPACE::ofm_scale_mode _scale_mode, + NPU_NAMESPACE::round_mode _round_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_type(static_cast(_activation_type) & ((1U << 1) - 1)), + activation_precision(static_cast(_activation_precision) & ((1U << 2) - 1)), reserved1(0), + activation_format(static_cast(_activation_format) & ((1U << 2) - 1)), + scale_mode(static_cast(_scale_mode) & ((1U << 1) - 1)), reserved2(0), + round_mode(static_cast(_round_mode) & ((1U << 2) - 1)) + { + } + CONSTEXPR npu_set_ofm_precision_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), + activation_precision(0), reserved1(0), activation_format(0), scale_mode(0), reserved2(0), round_mode(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const + { + return static_cast(activation_type); + } + CONSTEXPR npu_set_ofm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value) + { + activation_type = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const + { + return static_cast(activation_precision); + } + CONSTEXPR npu_set_ofm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value) + { + activation_precision = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const + { + return static_cast(activation_format); + } + CONSTEXPR npu_set_ofm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value) + { + activation_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ofm_scale_mode get_scale_mode() const + { + return static_cast(scale_mode); + } + CONSTEXPR npu_set_ofm_precision_t &set_scale_mode(NPU_NAMESPACE::ofm_scale_mode value) + { + scale_mode = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const + { + return static_cast(round_mode); + } + CONSTEXPR npu_set_ofm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value) + { + round_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_type", + (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ? + activation_type_str[activation_type] : + "****"))); + fields.push_back(std::make_pair( + "activation_precision", + (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ? + activation_precision_str[activation_precision] : + "****"))); + fields.push_back(std::make_pair( + "activation_format", + (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ? + activation_format_str[activation_format] : + "****"))); + fields.push_back(std::make_pair( + "scale_mode", + (scale_mode < (sizeof(ofm_scale_mode_str) / sizeof(ofm_scale_mode_str[0])) ? + ofm_scale_mode_str[scale_mode] : + "****"))); + fields.push_back(std::make_pair( + "round_mode", + (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] : + "****"))); + } +#endif +#endif + }; + // OFM block width + struct npu_set_ofm_blk_width_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 6; // OFM block width + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ofm_blk_width_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ofm_blk_width_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_blk_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_blk_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ofm_blk_width_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // OFM block height + struct npu_set_ofm_blk_height_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 5; // OFM block height + uint32_t reserved1 : 11; +#ifdef __cplusplus + public: + npu_set_ofm_blk_height_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 5) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ofm_blk_height_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_blk_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_blk_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_blk_height_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 5) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // OFM block depth + struct npu_set_ofm_blk_depth_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t depth_m1 : 7; // OFM block depth + uint32_t reserved1 : 9; +#ifdef __cplusplus + public: + npu_set_ofm_blk_depth_m1_t(uint32_t _depth_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 7) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_depth_m1() const + { + return static_cast(depth_m1); + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_depth_m1(uint32_t value) + { + depth_m1 = static_cast(value) & ((1U << 7) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("depth_m1", std::to_string(depth_m1))); + } +#endif +#endif + }; + // OFM zero point + struct npu_set_ofm_zero_point_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t zero_point : 16; // Zero point offset +#ifdef __cplusplus + public: + npu_set_ofm_zero_point_t(uint32_t _zero_point) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + zero_point(_zero_point & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_zero_point_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_zero_point() const + { + return static_cast(zero_point); + } + CONSTEXPR npu_set_ofm_zero_point_t &set_zero_point(uint32_t value) + { + zero_point = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("zero_point", std::to_string(zero_point))); + } +#endif +#endif + }; + // OFM Tile 0 and tile 2 width + struct npu_set_ofm_width0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // OFM Tile 0 and tile 2 width +#ifdef __cplusplus + public: + npu_set_ofm_width0_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_width0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ofm_width0_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // OFM Tile 0 height + struct npu_set_ofm_height0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // OFM Tile 0 height +#ifdef __cplusplus + public: + npu_set_ofm_height0_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_height0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_height0_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // OFM Tile 1 height + struct npu_set_ofm_height1_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // OFM Tile 1 height +#ifdef __cplusplus + public: + npu_set_ofm_height1_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_height1_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_height1_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Index n for OFM access + struct npu_set_ofm_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for OFM access + uint32_t reserved1 : 12; + uint32_t custom_dma_cs : 1; // Custom DMA select +#ifdef __cplusplus + public: + npu_set_ofm_region_t(uint32_t _region, NPU_NAMESPACE::custom_dma_cs _custom_dma_cs) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0), custom_dma_cs(static_cast(_custom_dma_cs) & ((1U << 1) - 1)) + { + } + CONSTEXPR npu_set_ofm_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), custom_dma_cs(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_ofm_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma_cs get_custom_dma_cs() const + { + return static_cast(custom_dma_cs); + } + CONSTEXPR npu_set_ofm_region_t &set_custom_dma_cs(NPU_NAMESPACE::custom_dma_cs value) + { + custom_dma_cs = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "custom_dma_cs", + (custom_dma_cs < (sizeof(custom_dma_cs_str) / sizeof(custom_dma_cs_str[0])) ? + custom_dma_cs_str[custom_dma_cs] : + "****"))); + } +#endif +#endif + }; + // Kernel width + struct npu_set_kernel_width_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // Kernel width +#ifdef __cplusplus + public: + npu_set_kernel_width_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_kernel_width_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_kernel_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_kernel_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_kernel_width_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // Kernel height + struct npu_set_kernel_height_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // Kernel height +#ifdef __cplusplus + public: + npu_set_kernel_height_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_kernel_height_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_kernel_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_kernel_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_kernel_height_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Kernel stride + struct npu_set_kernel_stride_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t stride_x_lsb : 1; // Stride x LSB. (kernel_x_stride - 1)[0] + uint32_t stride_y_lsb : 1; // Stride y LSB. (kernel_y_stride - 1)[0] + uint32_t weight_order : 1; // Weight ordering mode + uint32_t dilation_x : 1; // Kernel x dilation + uint32_t dilation_y : 1; // Kernel y dilation + uint32_t decomposition : 1; // Kernel decomposition + uint32_t stride_x_msb : 1; // Stride x MSB. (kernel_x_stride - 1) >> 1 + uint32_t reserved1 : 2; + uint32_t stride_y_msb : 1; // Stride y MSB. (kernel_y_stride - 1) >> 1 + uint32_t reserved2 : 6; +#ifdef __cplusplus + public: + npu_set_kernel_stride_t(uint32_t _stride_x_lsb, + uint32_t _stride_y_lsb, + NPU_NAMESPACE::weight_order _weight_order, + NPU_NAMESPACE::kernel_dilation _dilation_x, + NPU_NAMESPACE::kernel_dilation _dilation_y, + NPU_NAMESPACE::kernel_decomposition _decomposition, + uint32_t _stride_x_msb, + uint32_t _stride_y_msb) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + stride_x_lsb(_stride_x_lsb & ((1U << 1) - 1)), stride_y_lsb(_stride_y_lsb & ((1U << 1) - 1)), + weight_order(static_cast(_weight_order) & ((1U << 1) - 1)), + dilation_x(static_cast(_dilation_x) & ((1U << 1) - 1)), + dilation_y(static_cast(_dilation_y) & ((1U << 1) - 1)), + decomposition(static_cast(_decomposition) & ((1U << 1) - 1)), + stride_x_msb(_stride_x_msb & ((1U << 1) - 1)), reserved1(0), stride_y_msb(_stride_y_msb & ((1U << 1) - 1)), + reserved2(0) + { + } + CONSTEXPR npu_set_kernel_stride_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), stride_x_lsb(0), stride_y_lsb(0), + weight_order(0), dilation_x(0), dilation_y(0), decomposition(0), stride_x_msb(0), reserved1(0), + stride_y_msb(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_kernel_stride_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_kernel_stride_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_x_lsb() const + { + return static_cast(stride_x_lsb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_x_lsb(uint32_t value) + { + stride_x_lsb = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_y_lsb() const + { + return static_cast(stride_y_lsb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_y_lsb(uint32_t value) + { + stride_y_lsb = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::weight_order get_weight_order() const + { + return static_cast(weight_order); + } + CONSTEXPR npu_set_kernel_stride_t &set_weight_order(NPU_NAMESPACE::weight_order value) + { + weight_order = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_x() const + { + return static_cast(dilation_x); + } + CONSTEXPR npu_set_kernel_stride_t &set_dilation_x(NPU_NAMESPACE::kernel_dilation value) + { + dilation_x = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_y() const + { + return static_cast(dilation_y); + } + CONSTEXPR npu_set_kernel_stride_t &set_dilation_y(NPU_NAMESPACE::kernel_dilation value) + { + dilation_y = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::kernel_decomposition get_decomposition() const + { + return static_cast(decomposition); + } + CONSTEXPR npu_set_kernel_stride_t &set_decomposition(NPU_NAMESPACE::kernel_decomposition value) + { + decomposition = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_x_msb() const + { + return static_cast(stride_x_msb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_x_msb(uint32_t value) + { + stride_x_msb = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_y_msb() const + { + return static_cast(stride_y_msb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_y_msb(uint32_t value) + { + stride_y_msb = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("stride_x_lsb", std::to_string(stride_x_lsb))); + fields.push_back(std::make_pair("stride_y_lsb", std::to_string(stride_y_lsb))); + fields.push_back(std::make_pair( + "weight_order", + (weight_order < (sizeof(weight_order_str) / sizeof(weight_order_str[0])) ? + weight_order_str[weight_order] : + "****"))); + fields.push_back(std::make_pair( + "dilation_x", + (dilation_x < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ? + kernel_dilation_str[dilation_x] : + "****"))); + fields.push_back(std::make_pair( + "dilation_y", + (dilation_y < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ? + kernel_dilation_str[dilation_y] : + "****"))); + fields.push_back(std::make_pair( + "decomposition", + (decomposition < (sizeof(kernel_decomposition_str) / sizeof(kernel_decomposition_str[0])) ? + kernel_decomposition_str[decomposition] : + "****"))); + fields.push_back(std::make_pair("stride_x_msb", std::to_string(stride_x_msb))); + fields.push_back(std::make_pair("stride_y_msb", std::to_string(stride_y_msb))); + } +#endif +#endif + }; + // Accumulator format + struct npu_set_acc_format_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t acc_format : 2; // Accumulator format + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_set_acc_format_t(NPU_NAMESPACE::acc_format _acc_format) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + acc_format(static_cast(_acc_format) & ((1U << 2) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_acc_format_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), acc_format(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_acc_format_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_acc_format_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::acc_format get_acc_format() const + { + return static_cast(acc_format); + } + CONSTEXPR npu_set_acc_format_t &set_acc_format(NPU_NAMESPACE::acc_format value) + { + acc_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "acc_format", + (acc_format < (sizeof(acc_format_str) / sizeof(acc_format_str[0])) ? acc_format_str[acc_format] : + "****"))); + } +#endif +#endif + }; + // Activation function and clip range + struct npu_set_activation_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_function : 5; // Activation function (before table lookup) + uint32_t reserved1 : 7; + uint32_t activation_clip_range : 3; // Activation clip range. This must be set to 0 if table lookup is not used + uint32_t reserved2 : 1; +#ifdef __cplusplus + public: + npu_set_activation_t(NPU_NAMESPACE::activation_function _activation_function, + NPU_NAMESPACE::activation_clip_range _activation_clip_range) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_function(static_cast(_activation_function) & ((1U << 5) - 1)), reserved1(0), + activation_clip_range(static_cast(_activation_clip_range) & ((1U << 3) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_activation_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_function(0), reserved1(0), + activation_clip_range(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_activation_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_activation_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_function get_activation_function() const + { + return static_cast(activation_function); + } + CONSTEXPR npu_set_activation_t &set_activation_function(NPU_NAMESPACE::activation_function value) + { + activation_function = static_cast(value) & ((1U << 5) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_clip_range get_activation_clip_range() const + { + return static_cast(activation_clip_range); + } + CONSTEXPR npu_set_activation_t &set_activation_clip_range(NPU_NAMESPACE::activation_clip_range value) + { + activation_clip_range = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_function", + (activation_function < (sizeof(activation_function_str) / sizeof(activation_function_str[0])) ? + activation_function_str[activation_function] : + "****"))); + fields.push_back(std::make_pair( + "activation_clip_range", + (activation_clip_range < (sizeof(activation_clip_range_str) / sizeof(activation_clip_range_str[0])) ? + activation_clip_range_str[activation_clip_range] : + "****"))); + } +#endif +#endif + }; + // Lower bound clip + struct npu_set_activation_min_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t clip_boundary : 16; // Clip boundary for OFM activations +#ifdef __cplusplus + public: + npu_set_activation_min_t(uint32_t _clip_boundary) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + clip_boundary(_clip_boundary & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_activation_min_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_activation_min_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_activation_min_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_clip_boundary() const + { + return static_cast(clip_boundary); + } + CONSTEXPR npu_set_activation_min_t &set_clip_boundary(uint32_t value) + { + clip_boundary = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("clip_boundary", std::to_string(clip_boundary))); + } +#endif +#endif + }; + // Upper bound clip + struct npu_set_activation_max_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t clip_boundary : 16; // Clip boundary for OFM activations +#ifdef __cplusplus + public: + npu_set_activation_max_t(uint32_t _clip_boundary) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + clip_boundary(_clip_boundary & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_activation_max_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_activation_max_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_activation_max_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_clip_boundary() const + { + return static_cast(clip_boundary); + } + CONSTEXPR npu_set_activation_max_t &set_clip_boundary(uint32_t value) + { + clip_boundary = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("clip_boundary", std::to_string(clip_boundary))); + } +#endif +#endif + }; + // Index n for weight stream access + struct npu_set_weight_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for weight stream access + uint32_t reserved1 : 12; + uint32_t custom_dma_cs : 1; // Custom DMA select +#ifdef __cplusplus + public: + npu_set_weight_region_t(uint32_t _region, NPU_NAMESPACE::custom_dma_cs _custom_dma_cs) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0), custom_dma_cs(static_cast(_custom_dma_cs) & ((1U << 1) - 1)) + { + } + CONSTEXPR npu_set_weight_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), custom_dma_cs(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_weight_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_weight_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_weight_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma_cs get_custom_dma_cs() const + { + return static_cast(custom_dma_cs); + } + CONSTEXPR npu_set_weight_region_t &set_custom_dma_cs(NPU_NAMESPACE::custom_dma_cs value) + { + custom_dma_cs = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "custom_dma_cs", + (custom_dma_cs < (sizeof(custom_dma_cs_str) / sizeof(custom_dma_cs_str[0])) ? + custom_dma_cs_str[custom_dma_cs] : + "****"))); + } +#endif +#endif + }; + // Index n for scale stream access + struct npu_set_scale_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for scale stream access + uint32_t reserved1 : 12; + uint32_t custom_dma_cs : 1; // Custom DMA select +#ifdef __cplusplus + public: + npu_set_scale_region_t(uint32_t _region, NPU_NAMESPACE::custom_dma_cs _custom_dma_cs) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0), custom_dma_cs(static_cast(_custom_dma_cs) & ((1U << 1) - 1)) + { + } + CONSTEXPR npu_set_scale_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), custom_dma_cs(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_scale_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_scale_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_scale_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma_cs get_custom_dma_cs() const + { + return static_cast(custom_dma_cs); + } + CONSTEXPR npu_set_scale_region_t &set_custom_dma_cs(NPU_NAMESPACE::custom_dma_cs value) + { + custom_dma_cs = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "custom_dma_cs", + (custom_dma_cs < (sizeof(custom_dma_cs_str) / sizeof(custom_dma_cs_str[0])) ? + custom_dma_cs_str[custom_dma_cs] : + "****"))); + } +#endif +#endif + }; + // Start of ACC0,ACC1 buffers + struct npu_set_ab_start_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t ab_start : 6; // Start of ACC0,ACC1 buffers in the SHRAM in KB units. Multiple of 2 + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ab_start_t(uint32_t _ab_start) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(_ab_start & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ab_start_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ab_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ab_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_ab_start() const + { + return static_cast(ab_start); + } + CONSTEXPR npu_set_ab_start_t &set_ab_start(uint32_t value) + { + ab_start = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("ab_start", std::to_string(ab_start))); + } +#endif +#endif + }; + // Block number of blocks dependency + struct npu_set_blockdep_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t blockdep : 2; // Block number of blocks dependency between kernel operations + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_set_blockdep_t(uint32_t _blockdep) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(_blockdep & ((1U << 2) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_blockdep_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_blockdep_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_blockdep_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_blockdep() const + { + return static_cast(blockdep); + } + CONSTEXPR npu_set_blockdep_t &set_blockdep(uint32_t value) + { + blockdep = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("blockdep", std::to_string(blockdep))); + } +#endif +#endif + }; + // DMA0 source region + struct npu_set_dma0_src_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Region number + uint32_t reserved1 : 5; + uint32_t region_mode : 1; // Region mode + uint32_t stride_mode : 2; // Stride mode + uint32_t reserved2 : 4; + uint32_t custom_dma_cs : 1; // Custom DMA select +#ifdef __cplusplus + public: + npu_set_dma0_src_region_t(uint32_t _region, + NPU_NAMESPACE::dma_region_mode _region_mode, + NPU_NAMESPACE::dma_stride_mode _stride_mode, + NPU_NAMESPACE::custom_dma_cs _custom_dma_cs) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + region(_region & ((1U << 3) - 1)), reserved1(0), + region_mode(static_cast(_region_mode) & ((1U << 1) - 1)), + stride_mode(static_cast(_stride_mode) & ((1U << 2) - 1)), reserved2(0), + custom_dma_cs(static_cast(_custom_dma_cs) & ((1U << 1) - 1)) + { + } + CONSTEXPR npu_set_dma0_src_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0), + stride_mode(0), reserved2(0), custom_dma_cs(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_src_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_src_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_dma0_src_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode() const + { + return static_cast(region_mode); + } + CONSTEXPR npu_set_dma0_src_region_t &set_region_mode(NPU_NAMESPACE::dma_region_mode value) + { + region_mode = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode() const + { + return static_cast(stride_mode); + } + CONSTEXPR npu_set_dma0_src_region_t &set_stride_mode(NPU_NAMESPACE::dma_stride_mode value) + { + stride_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma_cs get_custom_dma_cs() const + { + return static_cast(custom_dma_cs); + } + CONSTEXPR npu_set_dma0_src_region_t &set_custom_dma_cs(NPU_NAMESPACE::custom_dma_cs value) + { + custom_dma_cs = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "region_mode", + (region_mode < (sizeof(dma_region_mode_str) / sizeof(dma_region_mode_str[0])) ? + dma_region_mode_str[region_mode] : + "****"))); + fields.push_back(std::make_pair( + "stride_mode", + (stride_mode < (sizeof(dma_stride_mode_str) / sizeof(dma_stride_mode_str[0])) ? + dma_stride_mode_str[stride_mode] : + "****"))); + fields.push_back(std::make_pair( + "custom_dma_cs", + (custom_dma_cs < (sizeof(custom_dma_cs_str) / sizeof(custom_dma_cs_str[0])) ? + custom_dma_cs_str[custom_dma_cs] : + "****"))); + } +#endif +#endif + }; + // DMA0 destination region + struct npu_set_dma0_dst_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Region number if region_mode is region_mode_external. Else core mask to write to (bit k + // set for core k=0,1) + uint32_t reserved1 : 5; + uint32_t region_mode : 1; // Region mode + uint32_t stride_mode : 2; // Stride mode + uint32_t reserved2 : 4; + uint32_t custom_dma_cs : 1; // Custom DMA select +#ifdef __cplusplus + public: + npu_set_dma0_dst_region_t(uint32_t _region, + NPU_NAMESPACE::dma_region_mode _region_mode, + NPU_NAMESPACE::dma_stride_mode _stride_mode, + NPU_NAMESPACE::custom_dma_cs _custom_dma_cs) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + region(_region & ((1U << 3) - 1)), reserved1(0), + region_mode(static_cast(_region_mode) & ((1U << 1) - 1)), + stride_mode(static_cast(_stride_mode) & ((1U << 2) - 1)), reserved2(0), + custom_dma_cs(static_cast(_custom_dma_cs) & ((1U << 1) - 1)) + { + } + CONSTEXPR npu_set_dma0_dst_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0), + stride_mode(0), reserved2(0), custom_dma_cs(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode() const + { + return static_cast(region_mode); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_region_mode(NPU_NAMESPACE::dma_region_mode value) + { + region_mode = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode() const + { + return static_cast(stride_mode); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_stride_mode(NPU_NAMESPACE::dma_stride_mode value) + { + stride_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma_cs get_custom_dma_cs() const + { + return static_cast(custom_dma_cs); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_custom_dma_cs(NPU_NAMESPACE::custom_dma_cs value) + { + custom_dma_cs = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "region_mode", + (region_mode < (sizeof(dma_region_mode_str) / sizeof(dma_region_mode_str[0])) ? + dma_region_mode_str[region_mode] : + "****"))); + fields.push_back(std::make_pair( + "stride_mode", + (stride_mode < (sizeof(dma_stride_mode_str) / sizeof(dma_stride_mode_str[0])) ? + dma_stride_mode_str[stride_mode] : + "****"))); + fields.push_back(std::make_pair( + "custom_dma_cs", + (custom_dma_cs < (sizeof(custom_dma_cs_str) / sizeof(custom_dma_cs_str[0])) ? + custom_dma_cs_str[custom_dma_cs] : + "****"))); + } +#endif +#endif + }; + // Size of second dimension for 2D/3D transfers + struct npu_set_dma0_size0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t size : 16; // Size of second dimension for 2D/3D transfers +#ifdef __cplusplus + public: + npu_set_dma0_size0_t(uint32_t _size) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(_size & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_dma0_size0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_size0_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_size0_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_size() const + { + return static_cast(size); + } + CONSTEXPR npu_set_dma0_size0_t &set_size(uint32_t value) + { + size = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("size", std::to_string(size))); + } +#endif +#endif + }; + // Size of third dimension for 3D transfers + struct npu_set_dma0_size1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t size : 16; // Size of third dimension for 3D transfers +#ifdef __cplusplus + public: + npu_set_dma0_size1_t(uint32_t _size) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(_size & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_dma0_size1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_size1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_size1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_size() const + { + return static_cast(size); + } + CONSTEXPR npu_set_dma0_size1_t &set_size(uint32_t value) + { + size = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("size", std::to_string(size))); + } +#endif +#endif + }; + // IFM2 broadcast configuration + struct npu_set_ifm2_broadcast_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t + broadcast_h : 1; // Broadcast H dimension (if set then any accesses to IFM2 sets y=0 and IFM2 height=1) + uint32_t broadcast_w : 1; // Broadcast W dimension (if set then any accesses to IFM2 sets x=0 and IFM2 width=1) + uint32_t broadcast_c : 1; // Broadcast C dimension (if set then any accesses to IFM2 sets c=0 and IFM2 depth=1) + uint32_t reserved1 : 3; + uint32_t operand_order : 1; // Operand order + uint32_t broadcast_constant : 1; // Broadcast constant given by NPU_SET_IFM2_SCALAR and so ignore BH, BW and BC + uint32_t reserved2 : 8; +#ifdef __cplusplus + public: + npu_set_ifm2_broadcast_t(NPU_NAMESPACE::broadcast_mode _broadcast_h, + NPU_NAMESPACE::broadcast_mode _broadcast_w, + NPU_NAMESPACE::broadcast_mode _broadcast_c, + NPU_NAMESPACE::ifm2_operand_order _operand_order, + NPU_NAMESPACE::broadcast_mode _broadcast_constant) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + broadcast_h(static_cast(_broadcast_h) & ((1U << 1) - 1)), + broadcast_w(static_cast(_broadcast_w) & ((1U << 1) - 1)), + broadcast_c(static_cast(_broadcast_c) & ((1U << 1) - 1)), reserved1(0), + operand_order(static_cast(_operand_order) & ((1U << 1) - 1)), + broadcast_constant(static_cast(_broadcast_constant) & ((1U << 1) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_ifm2_broadcast_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), broadcast_h(0), broadcast_w(0), + broadcast_c(0), reserved1(0), operand_order(0), broadcast_constant(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_h() const + { + return static_cast(broadcast_h); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_h(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_h = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_w() const + { + return static_cast(broadcast_w); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_w(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_w = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_c() const + { + return static_cast(broadcast_c); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_c(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_c = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ifm2_operand_order get_operand_order() const + { + return static_cast(operand_order); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_operand_order(NPU_NAMESPACE::ifm2_operand_order value) + { + operand_order = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_constant() const + { + return static_cast(broadcast_constant); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_constant(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_constant = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "broadcast_h", + (broadcast_h < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_h] : + "****"))); + fields.push_back(std::make_pair( + "broadcast_w", + (broadcast_w < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_w] : + "****"))); + fields.push_back(std::make_pair( + "broadcast_c", + (broadcast_c < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_c] : + "****"))); + fields.push_back(std::make_pair( + "operand_order", + (operand_order < (sizeof(ifm2_operand_order_str) / sizeof(ifm2_operand_order_str[0])) ? + ifm2_operand_order_str[operand_order] : + "****"))); + fields.push_back(std::make_pair( + "broadcast_constant", + (broadcast_constant < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_constant] : + "****"))); + } +#endif +#endif + }; + // IFM2 scalar value + struct npu_set_ifm2_scalar_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t scalar : 16; // int16 or uint16 depending on ifm2_precision.type +#ifdef __cplusplus + public: + npu_set_ifm2_scalar_t(uint32_t _scalar) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), scalar(_scalar & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_scalar_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), scalar(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_scalar_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_scalar_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_scalar() const + { + return static_cast(scalar); + } + CONSTEXPR npu_set_ifm2_scalar_t &set_scalar(uint32_t value) + { + scalar = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("scalar", std::to_string(scalar))); + } +#endif +#endif + }; + // IFM2 Precision + struct npu_set_ifm2_precision_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_type : 1; // IFM type - MUST MATCH IFM + uint32_t reserved1 : 1; + uint32_t activation_precision : 2; // IFM precision - MUST MATCH IFM + uint32_t reserved2 : 2; + uint32_t activation_format : 2; // IFM format + uint32_t reserved3 : 8; +#ifdef __cplusplus + public: + npu_set_ifm2_precision_t(NPU_NAMESPACE::activation_type _activation_type, + NPU_NAMESPACE::activation_precision _activation_precision, + NPU_NAMESPACE::activation_format _activation_format) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_type(static_cast(_activation_type) & ((1U << 1) - 1)), reserved1(0), + activation_precision(static_cast(_activation_precision) & ((1U << 2) - 1)), reserved2(0), + activation_format(static_cast(_activation_format) & ((1U << 2) - 1)), reserved3(0) + { + } + CONSTEXPR npu_set_ifm2_precision_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), reserved1(0), + activation_precision(0), reserved2(0), activation_format(0), reserved3(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const + { + return static_cast(activation_type); + } + CONSTEXPR npu_set_ifm2_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value) + { + activation_type = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const + { + return static_cast(activation_precision); + } + CONSTEXPR npu_set_ifm2_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value) + { + activation_precision = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const + { + return static_cast(activation_format); + } + CONSTEXPR npu_set_ifm2_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value) + { + activation_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_type", + (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ? + activation_type_str[activation_type] : + "****"))); + fields.push_back(std::make_pair( + "activation_precision", + (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ? + activation_precision_str[activation_precision] : + "****"))); + fields.push_back(std::make_pair( + "activation_format", + (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ? + activation_format_str[activation_format] : + "****"))); + } +#endif +#endif + }; + // IFM2 zero point + struct npu_set_ifm2_zero_point_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t zero_point : 16; // Zero point offset +#ifdef __cplusplus + public: + npu_set_ifm2_zero_point_t(uint32_t _zero_point) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + zero_point(_zero_point & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_zero_point_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_zero_point() const + { + return static_cast(zero_point); + } + CONSTEXPR npu_set_ifm2_zero_point_t &set_zero_point(uint32_t value) + { + zero_point = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("zero_point", std::to_string(zero_point))); + } +#endif +#endif + }; + // IFM2 Tile 0 and tile 2 width + struct npu_set_ifm2_width0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // IFM2 Tile 0 and tile 2 width +#ifdef __cplusplus + public: + npu_set_ifm2_width0_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_width0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ifm2_width0_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // IFM2 Tile 0 height + struct npu_set_ifm2_height0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM2 Tile 0 height +#ifdef __cplusplus + public: + npu_set_ifm2_height0_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_height0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm2_height0_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // IFM2 Tile 1 height + struct npu_set_ifm2_height1_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM2 Tile 1 height +#ifdef __cplusplus + public: + npu_set_ifm2_height1_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_height1_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm2_height1_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Start of IB0,IB1 buffers for IFM2 + struct npu_set_ifm2_ib_start_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t ib_start : 6; // Start of IB0,IB1 buffers for IFM2 in the SHRAM in KB units. Multiple of 2 + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ifm2_ib_start_t(uint32_t _ib_start) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_start(_ib_start & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ifm2_ib_start_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_start(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_ib_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_ib_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_ib_start() const + { + return static_cast(ib_start); + } + CONSTEXPR npu_set_ifm2_ib_start_t &set_ib_start(uint32_t value) + { + ib_start = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("ib_start", std::to_string(ib_start))); + } +#endif +#endif + }; + // Index n for IFM2 access + struct npu_set_ifm2_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for IFM2 access + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_set_ifm2_region_t(uint32_t _region) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ifm2_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_ifm2_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + } +#endif +#endif + }; + // IFM Tile 0 address + struct npu_set_ifm_base0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base0_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm_base0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_base0_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_base0_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm_base0_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM Tile 1 address + struct npu_set_ifm_base1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base1_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm_base1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_base1_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_base1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm_base1_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM Tile 2 address + struct npu_set_ifm_base2_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base2_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm_base2_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_base2_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_base2_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm_base2_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM Tile 3 address + struct npu_set_ifm_base3_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base3_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm_base3_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_base3_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_base3_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm_base3_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM byte stride between horizontal values + struct npu_set_ifm_stride_x_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_stride_x_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm_stride_x_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_stride_x_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_stride_x_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm_stride_x_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM byte stride between vertical values + struct npu_set_ifm_stride_y_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_stride_y_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm_stride_y_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_stride_y_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_stride_y_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm_stride_y_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM byte stride between channel blocks (of 16 bytes each block) + struct npu_set_ifm_stride_c_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_stride_c_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm_stride_c_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_stride_c_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_stride_c_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm_stride_c_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 0 address + struct npu_set_ofm_base0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base0_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ofm_base0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_base0_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_base0_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ofm_base0_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 1 address + struct npu_set_ofm_base1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base1_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ofm_base1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_base1_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_base1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ofm_base1_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 2 address + struct npu_set_ofm_base2_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base2_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ofm_base2_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_base2_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_base2_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ofm_base2_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 3 address + struct npu_set_ofm_base3_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base3_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ofm_base3_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_base3_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_base3_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ofm_base3_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM byte stride between horizontal values + struct npu_set_ofm_stride_x_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_stride_x_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ofm_stride_x_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_stride_x_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_stride_x_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ofm_stride_x_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM byte stride between vertical values + struct npu_set_ofm_stride_y_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_stride_y_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ofm_stride_y_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_stride_y_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_stride_y_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ofm_stride_y_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM byte stride between channel blocks (of 16 bytes each block) + struct npu_set_ofm_stride_c_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_stride_c_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ofm_stride_c_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_stride_c_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_stride_c_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ofm_stride_c_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Weight stream byte offset in WEIGHT_REGION + struct npu_set_weight_base_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_weight_base_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_weight_base_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_weight_base_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_weight_base_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_weight_base_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Weight stream byte length + struct npu_set_weight_length_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t length : 32; // Weight stream byte length +#ifdef __cplusplus + public: + npu_set_weight_length_t(uint32_t _length) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(_length) + { + } + CONSTEXPR npu_set_weight_length_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_weight_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_weight_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_length() const + { + return static_cast(length); + } + CONSTEXPR npu_set_weight_length_t &set_length(uint32_t value) + { + length = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("length", std::to_string(length))); + } +#endif +#endif + }; + // Scale and bias stream input byte offset from SCALE_REGION + struct npu_set_scale_base_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_scale_base_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_scale_base_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_scale_base_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_scale_base_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_scale_base_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Scale and bias stream input byte length + struct npu_set_scale_length_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t length : 20; // Scale and bias stream byte length + uint32_t reserved2 : 12; +#ifdef __cplusplus + public: + npu_set_scale_length_t(uint32_t _length) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), + length(_length & ((1U << 20) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_scale_length_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_scale_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_scale_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_length() const + { + return static_cast(length); + } + CONSTEXPR npu_set_scale_length_t &set_length(uint32_t value) + { + length = value & ((1U << 20) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("length", std::to_string(length))); + } +#endif +#endif + }; + // OFM scale + struct npu_set_ofm_scale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t shift : 6; // Shift + uint32_t reserved1 : 10; + uint32_t scale : 32; // Scale. Not applied for 32-bit operations +#ifdef __cplusplus + public: + npu_set_ofm_scale_t(uint32_t _shift, uint32_t _scale) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(_shift & ((1U << 6) - 1)), + reserved1(0), scale(_scale) + { + } + CONSTEXPR npu_set_ofm_scale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(0), reserved1(0), scale(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_shift() const + { + return static_cast(shift); + } + CONSTEXPR npu_set_ofm_scale_t &set_shift(uint32_t value) + { + shift = static_cast(value) & ((1U << 6) - 1); + return *this; + } + CONSTEXPR uint32_t get_scale() const + { + return static_cast(scale); + } + CONSTEXPR npu_set_ofm_scale_t &set_scale(uint32_t value) + { + scale = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("shift", std::to_string(shift))); + fields.push_back(std::make_pair("scale", std::to_string(scale))); + } +#endif +#endif + }; + // Input operand A scale + struct npu_set_opa_scale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t shift : 6; // Shift. Ignored if IFM scale mode is 0 + uint32_t reserved1 : 10; + uint32_t scale : 32; // Scale. 16-bit if IFM scale mode is 0 +#ifdef __cplusplus + public: + npu_set_opa_scale_t(uint32_t _shift, uint32_t _scale) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(_shift & ((1U << 6) - 1)), + reserved1(0), scale(_scale) + { + } + CONSTEXPR npu_set_opa_scale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(0), reserved1(0), scale(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_opa_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_opa_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_shift() const + { + return static_cast(shift); + } + CONSTEXPR npu_set_opa_scale_t &set_shift(uint32_t value) + { + shift = static_cast(value) & ((1U << 6) - 1); + return *this; + } + CONSTEXPR uint32_t get_scale() const + { + return static_cast(scale); + } + CONSTEXPR npu_set_opa_scale_t &set_scale(uint32_t value) + { + scale = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("shift", std::to_string(shift))); + fields.push_back(std::make_pair("scale", std::to_string(scale))); + } +#endif +#endif + }; + // Input operand B scale + struct npu_set_opb_scale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t scale : 16; // Scale. Not used if IFM scale mode is 1 or 2 + uint32_t reserved2 : 16; +#ifdef __cplusplus + public: + npu_set_opb_scale_t(uint32_t _scale) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), + scale(_scale & ((1U << 16) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_opb_scale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), scale(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_opb_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_opb_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_scale() const + { + return static_cast(scale); + } + CONSTEXPR npu_set_opb_scale_t &set_scale(uint32_t value) + { + scale = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("scale", std::to_string(scale))); + } +#endif +#endif + }; + // DMA user channel 0 source byte offset from DMA0_SRC_REGION + struct npu_set_dma0_src_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_src_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_dma0_src_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_src_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_src_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_dma0_src_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // DMA user channel 0 destination byte offset from DMA0_DST_REGION + struct npu_set_dma0_dst_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_dst_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_dma0_dst_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_dst_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_dst_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_dma0_dst_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // DMA user channel 0 transfer length in bytes for each 1D transfer + struct npu_set_dma0_len_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_len_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_dma0_len_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_len_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_len_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_dma0_len_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 0 address + struct npu_set_ifm2_base0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base0_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm2_base0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_base0_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_base0_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm2_base0_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 1 address + struct npu_set_ifm2_base1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base1_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm2_base1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_base1_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_base1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm2_base1_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 2 address + struct npu_set_ifm2_base2_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base2_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm2_base2_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_base2_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_base2_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm2_base2_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 3 address + struct npu_set_ifm2_base3_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base3_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm2_base3_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_base3_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_base3_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm2_base3_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 byte stride between horizontal values + struct npu_set_ifm2_stride_x_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_stride_x_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm2_stride_x_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_stride_x_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_stride_x_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm2_stride_x_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 byte stride between vertical values + struct npu_set_ifm2_stride_y_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_stride_y_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm2_stride_y_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_stride_y_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_stride_y_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm2_stride_y_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 byte stride between channel blocks (of 16 bytes each block) + struct npu_set_ifm2_stride_c_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t addr : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_stride_c_t(uint32_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(_addr) + { + } + CONSTEXPR npu_set_ifm2_stride_c_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), addr(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_stride_c_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_stride_c_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + return static_cast(addr); + } + CONSTEXPR npu_set_ifm2_stride_c_t &set_addr(uint32_t value) + { + addr = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // User defined register 0 + struct npu_set_user_defined0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined0_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined0_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined0_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined0_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; + // User defined register 1 + struct npu_set_user_defined1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined1_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined1_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined1_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; + // User defined register 2 + struct npu_set_user_defined2_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined2_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined2_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED2) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED2); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined2_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined2_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined2_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; + // User defined register 3 + struct npu_set_user_defined3_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined3_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined3_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED3) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED3); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined3_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined3_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined3_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; + // User defined register 4 + struct npu_set_user_defined4_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined4_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED4)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined4_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED4)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED4) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED4); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined4_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined4_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined4_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; + // User defined register 5 + struct npu_set_user_defined5_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined5_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED5)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined5_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED5)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED5) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED5); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined5_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined5_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined5_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; + // User defined register 6 + struct npu_set_user_defined6_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined6_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED6)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined6_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED6)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED6) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED6); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined6_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined6_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined6_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; + // User defined register 7 + struct npu_set_user_defined7_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t user_reg : 32; // User defined register +#ifdef __cplusplus + public: + npu_set_user_defined7_t(uint32_t _user_reg) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED7)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(_user_reg) + { + } + CONSTEXPR npu_set_user_defined7_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED7)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), user_reg(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED7) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_USER_DEFINED7); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_user_defined7_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_user_defined7_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_user_reg() const + { + return static_cast(user_reg); + } + CONSTEXPR npu_set_user_defined7_t &set_user_reg(uint32_t value) + { + user_reg = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("user_reg", std::to_string(user_reg))); + } +#endif +#endif + }; +#ifdef __cplusplus +}; +#endif +#define NPU_OP_STRUCTS \ + NPU_OP_(stop) \ + NPU_OP_(irq) \ + NPU_OP_(conv) \ + NPU_OP_(depthwise) \ + NPU_OP_(pool) \ + NPU_OP_(elementwise) \ + NPU_OP_(dma_start) \ + NPU_OP_(dma_wait) \ + NPU_OP_(kernel_wait) \ + NPU_OP_(pmu_mask) + +#define NPU_SET_STRUCTS \ + NPU_SET_(ifm_pad_top) \ + NPU_SET_(ifm_pad_left) \ + NPU_SET_(ifm_pad_right) \ + NPU_SET_(ifm_pad_bottom) \ + NPU_SET_(ifm_depth_m1) \ + NPU_SET_(ifm_precision) \ + NPU_SET_(ifm_upscale) \ + NPU_SET_(ifm_zero_point) \ + NPU_SET_(ifm_width0_m1) \ + NPU_SET_(ifm_height0_m1) \ + NPU_SET_(ifm_height1_m1) \ + NPU_SET_(ifm_ib_end) \ + NPU_SET_(ifm_region) \ + NPU_SET_(ofm_width_m1) \ + NPU_SET_(ofm_height_m1) \ + NPU_SET_(ofm_depth_m1) \ + NPU_SET_(ofm_precision) \ + NPU_SET_(ofm_blk_width_m1) \ + NPU_SET_(ofm_blk_height_m1) \ + NPU_SET_(ofm_blk_depth_m1) \ + NPU_SET_(ofm_zero_point) \ + NPU_SET_(ofm_width0_m1) \ + NPU_SET_(ofm_height0_m1) \ + NPU_SET_(ofm_height1_m1) \ + NPU_SET_(ofm_region) \ + NPU_SET_(kernel_width_m1) \ + NPU_SET_(kernel_height_m1) \ + NPU_SET_(kernel_stride) \ + NPU_SET_(acc_format) \ + NPU_SET_(activation) \ + NPU_SET_(activation_min) \ + NPU_SET_(activation_max) \ + NPU_SET_(weight_region) \ + NPU_SET_(scale_region) \ + NPU_SET_(ab_start) \ + NPU_SET_(blockdep) \ + NPU_SET_(dma0_src_region) \ + NPU_SET_(dma0_dst_region) \ + NPU_SET_(dma0_size0) \ + NPU_SET_(dma0_size1) \ + NPU_SET_(ifm2_broadcast) \ + NPU_SET_(ifm2_scalar) \ + NPU_SET_(ifm2_precision) \ + NPU_SET_(ifm2_zero_point) \ + NPU_SET_(ifm2_width0_m1) \ + NPU_SET_(ifm2_height0_m1) \ + NPU_SET_(ifm2_height1_m1) \ + NPU_SET_(ifm2_ib_start) \ + NPU_SET_(ifm2_region) \ + NPU_SET_(ifm_base0) \ + NPU_SET_(ifm_base1) \ + NPU_SET_(ifm_base2) \ + NPU_SET_(ifm_base3) \ + NPU_SET_(ifm_stride_x) \ + NPU_SET_(ifm_stride_y) \ + NPU_SET_(ifm_stride_c) \ + NPU_SET_(ofm_base0) \ + NPU_SET_(ofm_base1) \ + NPU_SET_(ofm_base2) \ + NPU_SET_(ofm_base3) \ + NPU_SET_(ofm_stride_x) \ + NPU_SET_(ofm_stride_y) \ + NPU_SET_(ofm_stride_c) \ + NPU_SET_(weight_base) \ + NPU_SET_(weight_length) \ + NPU_SET_(scale_base) \ + NPU_SET_(scale_length) \ + NPU_SET_(ofm_scale) \ + NPU_SET_(opa_scale) \ + NPU_SET_(opb_scale) \ + NPU_SET_(dma0_src) \ + NPU_SET_(dma0_dst) \ + NPU_SET_(dma0_len) \ + NPU_SET_(ifm2_base0) \ + NPU_SET_(ifm2_base1) \ + NPU_SET_(ifm2_base2) \ + NPU_SET_(ifm2_base3) \ + NPU_SET_(ifm2_stride_x) \ + NPU_SET_(ifm2_stride_y) \ + NPU_SET_(ifm2_stride_c) \ + NPU_SET_(user_defined0) \ + NPU_SET_(user_defined1) \ + NPU_SET_(user_defined2) \ + NPU_SET_(user_defined3) \ + NPU_SET_(user_defined4) \ + NPU_SET_(user_defined5) \ + NPU_SET_(user_defined6) \ + NPU_SET_(user_defined7) + +#define EXPAND_ACC_FORMAT(FUNC, SEP) FUNC(acc_format, I32) SEP FUNC(acc_format, I40) SEP FUNC(acc_format, F16) + +#define EXPAND_ACTIVATION_CLIP_RANGE(FUNC, SEP) \ + FUNC(activation_clip_range, OFM_PRECISION) \ + SEP FUNC(activation_clip_range, FORCE_UINT8) SEP FUNC(activation_clip_range, FORCE_INT8) \ + SEP FUNC(activation_clip_range, FORCE_INT16) + +#define EXPAND_ACTIVATION_FORMAT(FUNC, SEP) FUNC(activation_format, NHWC) SEP FUNC(activation_format, NHCWB16) + +#define EXPAND_ACTIVATION_FUNCTION(FUNC, SEP) \ + FUNC(activation_function, RELU) \ + SEP FUNC(activation_function, TANH) SEP FUNC(activation_function, SIGMOID) SEP FUNC(activation_function, TABLE_0) \ + SEP FUNC(activation_function, TABLE_1) SEP FUNC(activation_function, TABLE_2) \ + SEP FUNC(activation_function, TABLE_3) SEP FUNC(activation_function, TABLE_4) \ + SEP FUNC(activation_function, TABLE_5) SEP FUNC(activation_function, TABLE_6) \ + SEP FUNC(activation_function, TABLE_7) + +#define EXPAND_ACTIVATION_PRECISION(FUNC, SEP) \ + FUNC(activation_precision, B8) \ + SEP FUNC(activation_precision, B16) SEP FUNC(activation_precision, B32) SEP FUNC(activation_precision, B64) + +#define EXPAND_ACTIVATION_TYPE(FUNC, SEP) FUNC(activation_type, UNSIGNED) SEP FUNC(activation_type, SIGNED) + +#define EXPAND_AXI_MEM_ENCODING(FUNC, SEP) \ + FUNC(axi_mem_encoding, DEVICE_NON_BUFFERABLE) \ + SEP FUNC(axi_mem_encoding, DEVICE_BUFFERABLE) SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_NON_BUFFERABLE) \ + SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_BUFFERABLE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_NO_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_WRITE_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_AND_WRITE_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_NO_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_WRITE_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_AND_WRITE_ALLOCATE) + +#define EXPAND_BROADCAST_MODE(FUNC, SEP) FUNC(broadcast_mode, DISABLE) SEP FUNC(broadcast_mode, ENABLE) + +#define EXPAND_CMD0_OPCODE(FUNC, SEP) \ + FUNC(cmd0_opcode, NPU_OP_STOP) \ + SEP FUNC(cmd0_opcode, NPU_OP_IRQ) SEP FUNC(cmd0_opcode, NPU_OP_CONV) SEP FUNC( \ + cmd0_opcode, NPU_OP_DEPTHWISE) SEP FUNC(cmd0_opcode, NPU_OP_POOL) SEP FUNC(cmd0_opcode, NPU_OP_ELEMENTWISE) \ + SEP FUNC(cmd0_opcode, NPU_OP_DMA_START) SEP FUNC(cmd0_opcode, NPU_OP_DMA_WAIT) SEP FUNC( \ + cmd0_opcode, NPU_OP_KERNEL_WAIT) SEP FUNC(cmd0_opcode, NPU_OP_PMU_MASK) SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM_PAD_TOP) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_LEFT) SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_RIGHT) SEP FUNC( \ + cmd0_opcode, NPU_SET_IFM_PAD_BOTTOM) SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM_DEPTH_M1) SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM_PRECISION) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM_UPSCALE) SEP FUNC(cmd0_opcode, NPU_SET_IFM_ZERO_POINT) SEP FUNC( \ + cmd0_opcode, NPU_SET_IFM_WIDTH0_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT0_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_IB_END) SEP FUNC( \ + cmd0_opcode, NPU_SET_IFM_REGION) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_DEPTH_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_PRECISION) SEP FUNC( \ + cmd0_opcode, NPU_SET_OFM_BLK_WIDTH_M1) SEP FUNC(cmd0_opcode, \ + NPU_SET_OFM_BLK_HEIGHT_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_BLK_DEPTH_M1) SEP FUNC( \ + cmd0_opcode, NPU_SET_OFM_ZERO_POINT) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH0_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT0_M1) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_OFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_REGION) \ + SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_WIDTH_M1) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_KERNEL_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_STRIDE) \ + SEP FUNC(cmd0_opcode, NPU_SET_ACC_FORMAT) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_ACTIVATION) SEP FUNC(cmd0_opcode, NPU_SET_ACTIVATION_MIN) \ + SEP FUNC(cmd0_opcode, NPU_SET_ACTIVATION_MAX) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_WEIGHT_REGION) SEP FUNC(cmd0_opcode, NPU_SET_SCALE_REGION) \ + SEP FUNC(cmd0_opcode, \ + NPU_SET_AB_START) SEP FUNC(cmd0_opcode, NPU_SET_BLOCKDEP) \ + SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SRC_REGION) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_DMA0_DST_REGION) SEP FUNC(cmd0_opcode, \ + NPU_SET_DMA0_SIZE0) \ + SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SIZE1) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_IFM2_BROADCAST) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM2_SCALAR) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_IFM2_PRECISION) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM2_ZERO_POINT) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM2_WIDTH0_M1) \ + SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM2_HEIGHT0_M1) \ + SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM2_HEIGHT1_M1) \ + SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM2_IB_START) \ + SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM2_REGION) + +#define EXPAND_CMD1_OPCODE(FUNC, SEP) \ + FUNC(cmd1_opcode, NPU_SET_IFM_BASE0) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE1) SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE2) SEP FUNC( \ + cmd1_opcode, NPU_SET_IFM_BASE3) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_X) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_Y) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_C) SEP FUNC( \ + cmd1_opcode, NPU_SET_OFM_BASE0) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE1) \ + SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE2) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE3) SEP FUNC( \ + cmd1_opcode, NPU_SET_OFM_STRIDE_X) SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_Y) \ + SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_C) SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT_BASE) SEP FUNC( \ + cmd1_opcode, NPU_SET_WEIGHT_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_SCALE_BASE) \ + SEP FUNC(cmd1_opcode, NPU_SET_SCALE_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_OFM_SCALE) SEP FUNC( \ + cmd1_opcode, NPU_SET_OPA_SCALE) SEP FUNC(cmd1_opcode, NPU_SET_OPB_SCALE) \ + SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SRC) SEP FUNC(cmd1_opcode, NPU_SET_DMA0_DST) SEP FUNC( \ + cmd1_opcode, NPU_SET_DMA0_LEN) SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE0) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE1) SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE2) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE3) SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_X) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_Y) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_C) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED0) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED1) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED2) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED3) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED4) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED5) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED6) \ + SEP FUNC(cmd1_opcode, NPU_SET_USER_DEFINED7) + +#define EXPAND_CMD_CTRL(FUNC, SEP) FUNC(cmd_ctrl, CMD0_CTRL) SEP FUNC(cmd_ctrl, CMD1_CTRL) + +#define EXPAND_CUSTOM_DMA_CS(FUNC, SEP) FUNC(custom_dma_cs, DISABLE) SEP FUNC(custom_dma_cs, ENABLE) + +#define EXPAND_CUSTOM_DMA(FUNC, SEP) FUNC(custom_dma, NOT_IMPLEMENTED) SEP FUNC(custom_dma, IMPLEMENTED) + +#define EXPAND_DMA_FAULT_SRC(FUNC, SEP) FUNC(dma_fault_src, AXI_M0) SEP FUNC(dma_fault_src, AXI_M1) + +#define EXPAND_DMA_REGION_MODE(FUNC, SEP) FUNC(dma_region_mode, EXTERNAL) SEP FUNC(dma_region_mode, INTERNAL) + +#define EXPAND_DMA_STRIDE_MODE(FUNC, SEP) FUNC(dma_stride_mode, D1) + +#define EXPAND_ELEMENTWISE_MODE(FUNC, SEP) \ + FUNC(elementwise_mode, MUL) \ + SEP FUNC(elementwise_mode, ADD) SEP FUNC(elementwise_mode, SUB) SEP FUNC(elementwise_mode, MIN) \ + SEP FUNC(elementwise_mode, MAX) SEP FUNC(elementwise_mode, LRELU) SEP FUNC(elementwise_mode, ABS) \ + SEP FUNC(elementwise_mode, CLZ) SEP FUNC(elementwise_mode, SHR) SEP FUNC(elementwise_mode, SHL) + +#define EXPAND_FUNCTIONAL_SAFETY(FUNC, SEP) \ + FUNC(functional_safety, NOT_IMPLEMENTED) SEP FUNC(functional_safety, IMPLEMENTED) + +#define EXPAND_IFM2_OPERAND_ORDER(FUNC, SEP) FUNC(ifm2_operand_order, ORDER_B) SEP FUNC(ifm2_operand_order, ORDER_A) + +#define EXPAND_IFM_SCALE_MODE(FUNC, SEP) \ + FUNC(ifm_scale_mode, OPA_OPB_16) SEP FUNC(ifm_scale_mode, OPA_32) SEP FUNC(ifm_scale_mode, OPB_32) + +#define EXPAND_IFM_UPSCALE_MODE(FUNC, SEP) \ + FUNC(ifm_upscale_mode, NONE) SEP FUNC(ifm_upscale_mode, NEAREST) SEP FUNC(ifm_upscale_mode, ZEROS) + +#define EXPAND_KERNEL_DECOMPOSITION(FUNC, SEP) FUNC(kernel_decomposition, D8X8) SEP FUNC(kernel_decomposition, D4X4) + +#define EXPAND_KERNEL_DILATION(FUNC, SEP) FUNC(kernel_dilation, NONE) SEP FUNC(kernel_dilation, X2) + +#define EXPAND_MAX_BEATS(FUNC, SEP) FUNC(max_beats, B64) SEP FUNC(max_beats, B128) SEP FUNC(max_beats, B256) + +#define EXPAND_MEM_ATTR(FUNC, SEP) \ + FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER0) \ + SEP FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER1) SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER2) \ + SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER3) + +#define EXPAND_OFM_SCALE_MODE(FUNC, SEP) FUNC(ofm_scale_mode, PER_CHANNEL) SEP FUNC(ofm_scale_mode, GLOBAL) + +#define EXPAND_PMU_AXI_CHANNEL(FUNC, SEP) \ + FUNC(pmu_axi_channel, RD_CMD) \ + SEP FUNC(pmu_axi_channel, RD_IFM) SEP FUNC(pmu_axi_channel, RD_WEIGHTS) SEP FUNC(pmu_axi_channel, RD_SCALE_BIAS) \ + SEP FUNC(pmu_axi_channel, RD_MEM2MEM) SEP FUNC(pmu_axi_channel, WR_OFM) SEP FUNC(pmu_axi_channel, WR_MEM2MEM) + +#define EXPAND_PMU_EVENT(FUNC, SEP) \ + FUNC(pmu_event, NO_EVENT) \ + SEP FUNC(pmu_event, CYCLE) SEP FUNC(pmu_event, NPU_IDLE) SEP FUNC(pmu_event, CC_STALLED_ON_BLOCKDEP) SEP FUNC( \ + pmu_event, CC_STALLED_ON_SHRAM_RECONFIG) SEP FUNC(pmu_event, NPU_ACTIVE) SEP FUNC(pmu_event, MAC_ACTIVE) \ + SEP FUNC(pmu_event, MAC_ACTIVE_8BIT) SEP FUNC(pmu_event, MAC_ACTIVE_16BIT) SEP FUNC( \ + pmu_event, MAC_DPU_ACTIVE) SEP FUNC(pmu_event, MAC_STALLED_BY_WD_ACC) SEP FUNC(pmu_event, \ + MAC_STALLED_BY_WD) \ + SEP FUNC(pmu_event, MAC_STALLED_BY_ACC) SEP FUNC(pmu_event, MAC_STALLED_BY_IB) SEP FUNC( \ + pmu_event, \ + MAC_ACTIVE_32BIT) SEP FUNC(pmu_event, \ + MAC_STALLED_BY_INT_W) SEP FUNC(pmu_event, \ + MAC_STALLED_BY_INT_ACC) SEP FUNC(pmu_event, \ + AO_ACTIVE) \ + SEP FUNC(pmu_event, AO_ACTIVE_8BIT) SEP FUNC(pmu_event, AO_ACTIVE_16BIT) SEP FUNC( \ + pmu_event, AO_STALLED_BY_OFMP_OB) SEP FUNC(pmu_event, AO_STALLED_BY_OFMP) SEP \ + FUNC(pmu_event, AO_STALLED_BY_OB) SEP FUNC(pmu_event, AO_STALLED_BY_ACC_IB) SEP FUNC( \ + pmu_event, AO_STALLED_BY_ACC) SEP FUNC(pmu_event, AO_STALLED_BY_IB) SEP \ + FUNC(pmu_event, WD_ACTIVE) SEP FUNC(pmu_event, WD_STALLED) SEP FUNC(pmu_event, WD_STALLED_BY_WS) SEP FUNC( \ + pmu_event, WD_STALLED_BY_WD_BUF) SEP FUNC(pmu_event, \ + WD_PARSE_ACTIVE) SEP \ + FUNC(pmu_event, WD_PARSE_STALLED) SEP FUNC(pmu_event, WD_PARSE_STALLED_IN) SEP FUNC( \ + pmu_event, WD_PARSE_STALLED_OUT) SEP FUNC(pmu_event, \ + WD_TRANS_WS) SEP \ + FUNC(pmu_event, WD_TRANS_WB) SEP FUNC(pmu_event, WD_TRANS_DW0) SEP FUNC( \ + pmu_event, WD_TRANS_DW1) SEP FUNC(pmu_event, \ + AXI0_RD_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI0_RD_TRANS_COMPLETED) SEP FUNC(pmu_event, AXI0_RD_DATA_BEAT_RECEIVED) SEP FUNC( \ + pmu_event, AXI0_RD_TRAN_REQ_STALLED) SEP FUNC(pmu_event, \ + AXI0_WR_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI0_WR_TRANS_COMPLETED_M) SEP FUNC( \ + pmu_event, AXI0_WR_TRANS_COMPLETED_S) SEP \ + FUNC(pmu_event, AXI0_WR_DATA_BEAT_WRITTEN) SEP FUNC( \ + pmu_event, AXI0_WR_TRAN_REQ_STALLED) SEP \ + FUNC(pmu_event, AXI0_WR_DATA_BEAT_STALLED) SEP FUNC( \ + pmu_event, \ + AXI0_ENABLED_CYCLES) SEP FUNC(pmu_event, \ + AXI0_RD_STALL_LIMIT) SEP \ + FUNC(pmu_event, AXI0_WR_STALL_LIMIT) SEP FUNC( \ + pmu_event, \ + AXI_LATENCY_ANY) SEP FUNC(pmu_event, \ + AXI_LATENCY_32) SEP \ + FUNC(pmu_event, \ + AXI_LATENCY_64) SEP FUNC(pmu_event, \ + AXI_LATENCY_128) SEP \ + FUNC(pmu_event, AXI_LATENCY_256) SEP FUNC( \ + pmu_event, \ + AXI_LATENCY_512) SEP FUNC(pmu_event, \ + AXI_LATENCY_1024) SEP \ + FUNC(pmu_event, ECC_DMA) SEP FUNC( \ + pmu_event, \ + ECC_SB0) SEP FUNC(pmu_event, \ + AXI1_RD_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI1_RD_TRANS_COMPLETED) SEP FUNC( \ + pmu_event, AXI1_RD_DATA_BEAT_RECEIVED) SEP \ + FUNC(pmu_event, AXI1_RD_TRAN_REQ_STALLED) SEP FUNC( \ + pmu_event, AXI1_WR_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI1_WR_TRANS_COMPLETED_M) SEP FUNC( \ + pmu_event, \ + AXI1_WR_TRANS_COMPLETED_S) SEP \ + FUNC(pmu_event, \ + AXI1_WR_DATA_BEAT_WRITTEN) SEP \ + FUNC(pmu_event, \ + AXI1_WR_TRAN_REQ_STALLED) SEP \ + FUNC( \ + pmu_event, \ + AXI1_WR_DATA_BEAT_STALLED) SEP \ + FUNC( \ + pmu_event, \ + AXI1_ENABLED_CYCLES) SEP \ + FUNC( \ + pmu_event, \ + AXI1_RD_STALL_LIMIT) SEP \ + FUNC( \ + pmu_event, \ + AXI1_WR_STALL_LIMIT) \ + SEP FUNC( \ + pmu_event, \ + ECC_SB1) + +#define EXPAND_POOLING_MODE(FUNC, SEP) \ + FUNC(pooling_mode, MAX) SEP FUNC(pooling_mode, AVERAGE) SEP FUNC(pooling_mode, REDUCE_SUM) + +#define EXPAND_PRIVILEGE_LEVEL(FUNC, SEP) FUNC(privilege_level, USER) SEP FUNC(privilege_level, PRIVILEGED) + +#define EXPAND_ROUND_MODE(FUNC, SEP) FUNC(round_mode, DBL) SEP FUNC(round_mode, TRUNCATE) SEP FUNC(round_mode, NATURAL) + +#define EXPAND_SECURITY_LEVEL(FUNC, SEP) FUNC(security_level, SECURE) SEP FUNC(security_level, NON_SECURE) + +#define EXPAND_STATE(FUNC, SEP) FUNC(state, STOPPED) SEP FUNC(state, RUNNING) + +#define EXPAND_WD_CORE_SLICE_STATE(FUNC, SEP) \ + FUNC(wd_core_slice_state, HEADER) SEP FUNC(wd_core_slice_state, PALETTE) SEP FUNC(wd_core_slice_state, WEIGHTS) + +#define EXPAND_WD_CTRL_STATE(FUNC, SEP) \ + FUNC(wd_ctrl_state, IDLE) \ + SEP FUNC(wd_ctrl_state, DRAIN) SEP FUNC(wd_ctrl_state, OFD_INIT) SEP FUNC(wd_ctrl_state, OFD_RUN) + +#define EXPAND_WEIGHT_ORDER(FUNC, SEP) FUNC(weight_order, DEPTH_FIRST) SEP FUNC(weight_order, PART_KERNEL_FIRST) + +#ifdef __cplusplus +} +#endif +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu65_interface.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu65_interface.h new file mode 100644 index 0000000..c09cbf8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu65_interface.h @@ -0,0 +1,26061 @@ + +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU65_INTERFACE_H +#define ETHOSU65_INTERFACE_H + +#ifdef __KERNEL__ +#include +#else +#include +#endif + +#if !defined(__cplusplus) || __cplusplus < 201402L +#define CONSTEXPR +#else +#define CONSTEXPR constexpr +#endif + +#ifndef __cplusplus +#define STRUCT struct +#else +#define STRUCT +#endif + +#if defined(__cplusplus) && defined(NPU_DISASSEMBLE) +#include +#include +#include +#endif + +#if defined(__cplusplus) && !defined(NPU_NAMESPACE) +#define NPU_NAMESPACE npu +#endif + +#ifdef __cplusplus +#include +#include +#endif + +#ifdef __cplusplus +namespace NPU_NAMESPACE +{ +#endif +#define NNX_ARCH_VERSION_MAJOR 1 +#define NNX_ARCH_VERSION_MINOR 0 +#define NNX_ARCH_VERSION_PATCH 6 + +// Register offsets +// +// Register subpage BASE +// +#define NPU_REG_ID 0x0000 +#define NPU_REG_STATUS 0x0004 +#define NPU_REG_CMD 0x0008 +#define NPU_REG_RESET 0x000C +#define NPU_REG_QBASE 0x0010 +#define NPU_REG_QBASE_HI 0x0014 +#define NPU_REG_QREAD 0x0018 +#define NPU_REG_QCONFIG 0x001C +#define NPU_REG_QSIZE 0x0020 +#define NPU_REG_PROT 0x0024 +#define NPU_REG_CONFIG 0x0028 +#define NPU_REG_LOCK 0x002C +#define NPU_REG_REGIONCFG 0x003C +#define NPU_REG_AXI_LIMIT0 0x0040 +#define NPU_REG_AXI_LIMIT1 0x0044 +#define NPU_REG_AXI_LIMIT2 0x0048 +#define NPU_REG_AXI_LIMIT3 0x004C +#define BASE_REGISTERS_SIZE 0x0080 + +// +// Register subpage BASE_POINTERS +// +#define NPU_REG_BASEP_BASE 0x0080 +#define NPU_REG_BASEP_ARRLEN 0x0008 +#define BASE_POINTERS_REGISTERS_SIZE 0x0100 + +// +// Register subpage DEBUG +// +#define NPU_REG_WD_STATUS 0x0100 +#define NPU_REG_MAC_STATUS 0x0104 +#define NPU_REG_AO_STATUS 0x0108 +#define NPU_REG_DMA_STATUS0 0x0110 +#define NPU_REG_DMA_STATUS1 0x0114 +#define NPU_REG_CLKFORCE 0x0140 +#define NPU_REG_DEBUG_ADDRESS 0x0144 +#define NPU_REG_DEBUG_MISC 0x0148 +#define NPU_REG_DEBUGCORE 0x014C +#define NPU_REG_DEBUG_BLOCK 0x0150 +#define DEBUG_REGISTERS_SIZE 0x0180 + +// +// Register subpage PMU +// +#define NPU_REG_PMCR 0x0180 +#define NPU_REG_PMCNTENSET 0x0184 +#define NPU_REG_PMCNTENCLR 0x0188 +#define NPU_REG_PMOVSSET 0x018C +#define NPU_REG_PMOVSCLR 0x0190 +#define NPU_REG_PMINTSET 0x0194 +#define NPU_REG_PMINTCLR 0x0198 +#define NPU_REG_PMCCNTR 0x01A0 +#define NPU_REG_PMCCNTR_HI 0x01A4 +#define NPU_REG_PMCCNTR_CFG 0x01A8 +#define NPU_REG_PMCAXI_CHAN 0x01AC +#define PMU_REGISTERS_SIZE 0x0200 + +// +// Register subpage TSU_DEBUG +// +#define NPU_REG_KERNEL_X 0x0200 +#define NPU_REG_KERNEL_Y 0x0204 +#define NPU_REG_KERNEL_W_M1 0x0208 +#define NPU_REG_KERNEL_H_M1 0x020C +#define NPU_REG_OFM_CBLK_WIDTH_M1 0x0210 +#define NPU_REG_OFM_CBLK_HEIGHT_M1 0x0214 +#define NPU_REG_OFM_CBLK_DEPTH_M1 0x0218 +#define NPU_REG_IFM_CBLK_DEPTH_M1 0x021C +#define NPU_REG_OFM_X 0x0220 +#define NPU_REG_OFM_Y 0x0224 +#define NPU_REG_OFM_Z 0x0228 +#define NPU_REG_IFM_Z 0x022C +#define NPU_REG_PAD_TOP 0x0230 +#define NPU_REG_PAD_LEFT 0x0234 +#define NPU_REG_IFM_CBLK_WIDTH 0x0238 +#define NPU_REG_IFM_CBLK_HEIGHT 0x023C +#define NPU_REG_DMA_IFM_SRC 0x0240 +#define NPU_REG_DMA_IFM_SRC_HI 0x0244 +#define NPU_REG_DMA_IFM_DST 0x0248 +#define NPU_REG_DMA_OFM_SRC 0x024C +#define NPU_REG_DMA_OFM_DST 0x0250 +#define NPU_REG_DMA_OFM_DST_HI 0x0254 +#define NPU_REG_DMA_WEIGHT_SRC 0x0258 +#define NPU_REG_DMA_WEIGHT_SRC_HI 0x025C +#define NPU_REG_DMA_CMD_SRC 0x0260 +#define NPU_REG_DMA_CMD_SRC_HI 0x0264 +#define NPU_REG_DMA_CMD_SIZE 0x0268 +#define NPU_REG_DMA_M2M_SRC 0x026C +#define NPU_REG_DMA_M2M_SRC_HI 0x0270 +#define NPU_REG_DMA_M2M_DST 0x0274 +#define NPU_REG_DMA_M2M_DST_HI 0x0278 +#define NPU_REG_CURRENT_QREAD 0x027C +#define NPU_REG_DMA_SCALE_SRC 0x0280 +#define NPU_REG_DMA_SCALE_SRC_HI 0x0284 +#define NPU_REG_CURRENT_BLOCK 0x02B4 +#define NPU_REG_CURRENT_OP 0x02B8 +#define NPU_REG_CURRENT_CMD 0x02BC +#define TSU_DEBUG_REGISTERS_SIZE 0x02C0 + +// +// Register subpage PMU_COUNTERS +// +#define NPU_REG_PMEVCNTR_BASE 0x0300 +#define NPU_REG_PMEVCNTR_ARRLEN 0x0004 +#define NPU_REG_PMEVTYPER_BASE 0x0380 +#define NPU_REG_PMEVTYPER_ARRLEN 0x0004 +#define PMU_COUNTERS_REGISTERS_SIZE 0x0400 + +// +// Register subpage SHARED_BUFFER +// +#define NPU_REG_SHARED_BUFFER_BASE 0x0400 +#define NPU_REG_SHARED_BUFFER_ARRLEN 0x0100 +#define SHARED_BUFFER_REGISTERS_SIZE 0x0800 + +// +// Register subpage TSU_IFM +// +#define NPU_REG_IFM_PAD_TOP 0x0800 +#define NPU_REG_IFM_PAD_LEFT 0x0804 +#define NPU_REG_IFM_PAD_RIGHT 0x0808 +#define NPU_REG_IFM_PAD_BOTTOM 0x080C +#define NPU_REG_IFM_DEPTH_M1 0x0810 +#define NPU_REG_IFM_PRECISION 0x0814 +#define NPU_REG_IFM_UPSCALE 0x081C +#define NPU_REG_IFM_ZERO_POINT 0x0824 +#define NPU_REG_IFM_WIDTH0_M1 0x0828 +#define NPU_REG_IFM_HEIGHT0_M1 0x082C +#define NPU_REG_IFM_HEIGHT1_M1 0x0830 +#define NPU_REG_IFM_IB_END 0x0834 +#define NPU_REG_IFM_REGION 0x083C +#define TSU_IFM_REGISTERS_SIZE 0x0840 + +// +// Register subpage TSU_OFM +// +#define NPU_REG_OFM_WIDTH_M1 0x0844 +#define NPU_REG_OFM_HEIGHT_M1 0x0848 +#define NPU_REG_OFM_DEPTH_M1 0x084C +#define NPU_REG_OFM_PRECISION 0x0850 +#define NPU_REG_OFM_BLK_WIDTH_M1 0x0854 +#define NPU_REG_OFM_BLK_HEIGHT_M1 0x0858 +#define NPU_REG_OFM_BLK_DEPTH_M1 0x085C +#define NPU_REG_OFM_ZERO_POINT 0x0860 +#define NPU_REG_OFM_WIDTH0_M1 0x0868 +#define NPU_REG_OFM_HEIGHT0_M1 0x086C +#define NPU_REG_OFM_HEIGHT1_M1 0x0870 +#define NPU_REG_OFM_REGION 0x087C +#define TSU_OFM_REGISTERS_SIZE 0x0880 + +// +// Register subpage TSU_KERNEL +// +#define NPU_REG_KERNEL_WIDTH_M1 0x0880 +#define NPU_REG_KERNEL_HEIGHT_M1 0x0884 +#define NPU_REG_KERNEL_STRIDE 0x0888 +#define NPU_REG_PARALLEL_MODE 0x088C +#define NPU_REG_ACC_FORMAT 0x0890 +#define NPU_REG_ACTIVATION 0x0894 +#define NPU_REG_ACTIVATION_MIN 0x0898 +#define NPU_REG_ACTIVATION_MAX 0x089C +#define NPU_REG_WEIGHT_REGION 0x08A0 +#define NPU_REG_SCALE_REGION 0x08A4 +#define NPU_REG_AB_START 0x08B4 +#define NPU_REG_BLOCKDEP 0x08BC +#define TSU_KERNEL_REGISTERS_SIZE 0x08C0 + +// +// Register subpage TSU_DMA +// +#define NPU_REG_DMA0_SRC_REGION 0x08C0 +#define NPU_REG_DMA0_DST_REGION 0x08C4 +#define NPU_REG_DMA0_SIZE0 0x08C8 +#define NPU_REG_DMA0_SIZE1 0x08CC +#define TSU_DMA_REGISTERS_SIZE 0x0900 + +// +// Register subpage TSU_IFM2 +// +#define NPU_REG_IFM2_BROADCAST 0x0900 +#define NPU_REG_IFM2_SCALAR 0x0904 +#define NPU_REG_IFM2_PRECISION 0x0914 +#define NPU_REG_IFM2_ZERO_POINT 0x0924 +#define NPU_REG_IFM2_WIDTH0_M1 0x0928 +#define NPU_REG_IFM2_HEIGHT0_M1 0x092C +#define NPU_REG_IFM2_HEIGHT1_M1 0x0930 +#define NPU_REG_IFM2_IB_START 0x0934 +#define NPU_REG_IFM2_REGION 0x093C +#define TSU_IFM2_REGISTERS_SIZE 0x0940 + +// +// Register subpage TSU_IFM_BASE +// +#define NPU_REG_IFM_BASE0 0x0A00 +#define NPU_REG_IFM_BASE0_HI 0x0A04 +#define NPU_REG_IFM_BASE1 0x0A08 +#define NPU_REG_IFM_BASE1_HI 0x0A0C +#define NPU_REG_IFM_BASE2 0x0A10 +#define NPU_REG_IFM_BASE2_HI 0x0A14 +#define NPU_REG_IFM_BASE3 0x0A18 +#define NPU_REG_IFM_BASE3_HI 0x0A1C +#define NPU_REG_IFM_STRIDE_X 0x0A20 +#define NPU_REG_IFM_STRIDE_X_HI 0x0A24 +#define NPU_REG_IFM_STRIDE_Y 0x0A28 +#define NPU_REG_IFM_STRIDE_Y_HI 0x0A2C +#define NPU_REG_IFM_STRIDE_C 0x0A30 +#define NPU_REG_IFM_STRIDE_C_HI 0x0A34 +#define TSU_IFM_BASE_REGISTERS_SIZE 0x0A40 + +// +// Register subpage TSU_OFM_BASE +// +#define NPU_REG_OFM_BASE0 0x0A40 +#define NPU_REG_OFM_BASE0_HI 0x0A44 +#define NPU_REG_OFM_BASE1 0x0A48 +#define NPU_REG_OFM_BASE1_HI 0x0A4C +#define NPU_REG_OFM_BASE2 0x0A50 +#define NPU_REG_OFM_BASE2_HI 0x0A54 +#define NPU_REG_OFM_BASE3 0x0A58 +#define NPU_REG_OFM_BASE3_HI 0x0A5C +#define NPU_REG_OFM_STRIDE_X 0x0A60 +#define NPU_REG_OFM_STRIDE_X_HI 0x0A64 +#define NPU_REG_OFM_STRIDE_Y 0x0A68 +#define NPU_REG_OFM_STRIDE_Y_HI 0x0A6C +#define NPU_REG_OFM_STRIDE_C 0x0A70 +#define NPU_REG_OFM_STRIDE_C_HI 0x0A74 +#define TSU_OFM_BASE_REGISTERS_SIZE 0x0A80 + +// +// Register subpage TSU_WS_BASE +// +#define NPU_REG_WEIGHT_BASE 0x0A80 +#define NPU_REG_WEIGHT_BASE_HI 0x0A84 +#define NPU_REG_WEIGHT_LENGTH 0x0A88 +#define NPU_REG_WEIGHT_LENGTH_HI 0x0A8C +#define NPU_REG_SCALE_BASE 0x0A90 +#define NPU_REG_SCALE_BASE_HI 0x0A94 +#define NPU_REG_SCALE_LENGTH 0x0A98 +#define NPU_REG_SCALE_LENGTH_HI 0x0A9C +#define NPU_REG_OFM_SCALE 0x0AA0 +#define NPU_REG_OFM_SCALE_SHIFT 0x0AA4 +#define NPU_REG_OPA_SCALE 0x0AA8 +#define NPU_REG_OPA_SCALE_SHIFT 0x0AAC +#define NPU_REG_OPB_SCALE 0x0AB0 +#define TSU_WS_BASE_REGISTERS_SIZE 0x0AC0 + +// +// Register subpage TSU_DMA_BASE +// +#define NPU_REG_DMA0_SRC 0x0AC0 +#define NPU_REG_DMA0_SRC_HI 0x0AC4 +#define NPU_REG_DMA0_DST 0x0AC8 +#define NPU_REG_DMA0_DST_HI 0x0ACC +#define NPU_REG_DMA0_LEN 0x0AD0 +#define NPU_REG_DMA0_LEN_HI 0x0AD4 +#define NPU_REG_DMA0_SKIP0 0x0AD8 +#define NPU_REG_DMA0_SKIP0_HI 0x0ADC +#define NPU_REG_DMA0_SKIP1 0x0AE0 +#define NPU_REG_DMA0_SKIP1_HI 0x0AE4 +#define TSU_DMA_BASE_REGISTERS_SIZE 0x0B00 + +// +// Register subpage TSU_IFM2_BASE +// +#define NPU_REG_IFM2_BASE0 0x0B00 +#define NPU_REG_IFM2_BASE0_HI 0x0B04 +#define NPU_REG_IFM2_BASE1 0x0B08 +#define NPU_REG_IFM2_BASE1_HI 0x0B0C +#define NPU_REG_IFM2_BASE2 0x0B10 +#define NPU_REG_IFM2_BASE2_HI 0x0B14 +#define NPU_REG_IFM2_BASE3 0x0B18 +#define NPU_REG_IFM2_BASE3_HI 0x0B1C +#define NPU_REG_IFM2_STRIDE_X 0x0B20 +#define NPU_REG_IFM2_STRIDE_X_HI 0x0B24 +#define NPU_REG_IFM2_STRIDE_Y 0x0B28 +#define NPU_REG_IFM2_STRIDE_Y_HI 0x0B2C +#define NPU_REG_IFM2_STRIDE_C 0x0B30 +#define NPU_REG_IFM2_STRIDE_C_HI 0x0B34 +#define TSU_IFM2_BASE_REGISTERS_SIZE 0x0B40 + +// +// Register subpage TSU_WS1_BASE +// +#define NPU_REG_WEIGHT1_BASE 0x0B40 +#define NPU_REG_WEIGHT1_BASE_HI 0x0B44 +#define NPU_REG_WEIGHT1_LENGTH 0x0B48 +#define NPU_REG_WEIGHT1_LENGTH_HI 0x0B4C +#define NPU_REG_SCALE1_BASE 0x0B50 +#define NPU_REG_SCALE1_BASE_HI 0x0B54 +#define NPU_REG_SCALE1_LENGTH 0x0B58 +#define NPU_REG_SCALE1_LENGTH_HI 0x0B5C +#define TSU_WS1_BASE_REGISTERS_SIZE 0x0B80 + +// +// Register subpage TSU_USER_BASE +// +#define TSU_USER_BASE_REGISTERS_SIZE 0x0BC0 + +// +// Register subpage TSU_DMA_EBASE +// +#define TSU_DMA_EBASE_REGISTERS_SIZE 0x0C00 + +// +// Register subpage ID +// +#define NPU_REG_REVISION 0x0FC0 +#define NPU_REG_PID4 0x0FD0 +#define NPU_REG_PID5 0x0FD4 +#define NPU_REG_PID6 0x0FD8 +#define NPU_REG_PID7 0x0FDC +#define NPU_REG_PID0 0x0FE0 +#define NPU_REG_PID1 0x0FE4 +#define NPU_REG_PID2 0x0FE8 +#define NPU_REG_PID3 0x0FEC +#define NPU_REG_CID0 0x0FF0 +#define NPU_REG_CID1 0x0FF4 +#define NPU_REG_CID2 0x0FF8 +#define NPU_REG_CID3 0x0FFC +#define ID_REGISTERS_SIZE 0x1000 + +#ifdef __cplusplus +// Enum types +enum class acc_format : uint8_t +{ + I32 = 0, + I40 = 1, + F16 = 2, +}; + +enum class activation_clip_range : uint8_t +{ + OFM_PRECISION = 0, + FORCE_UINT8 = 2, + FORCE_INT8 = 3, + FORCE_INT16 = 5, +}; + +enum class activation_format : uint8_t +{ + NHWC = 0, + NHCWB16 = 1, +}; + +enum class activation_function : uint8_t +{ + RELU = 0, + TANH = 3, + SIGMOID = 4, + TABLE_0 = 16, + TABLE_1 = 17, + TABLE_2 = 18, + TABLE_3 = 19, + TABLE_4 = 20, + TABLE_5 = 21, + TABLE_6 = 22, + TABLE_7 = 23, +}; + +enum class activation_precision : uint8_t +{ + B8 = 0, + B16 = 1, + B32 = 2, + B64 = 3, +}; + +enum class activation_type : uint8_t +{ + UNSIGNED = 0, + SIGNED = 1, +}; + +enum class axi_mem_encoding : uint8_t +{ + DEVICE_NON_BUFFERABLE = 0, + DEVICE_BUFFERABLE = 1, + NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2, + NORMAL_NON_CACHEABLE_BUFFERABLE = 3, + WRITE_THROUGH_NO_ALLOCATE = 4, + WRITE_THROUGH_READ_ALLOCATE = 5, + WRITE_THROUGH_WRITE_ALLOCATE = 6, + WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7, + WRITE_BACK_NO_ALLOCATE = 8, + WRITE_BACK_READ_ALLOCATE = 9, + WRITE_BACK_WRITE_ALLOCATE = 10, + WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11, +}; + +enum class broadcast_mode : uint8_t +{ + DISABLE = 0, + ENABLE = 1, +}; + +enum class cmd0_opcode : uint16_t +{ + NPU_OP_STOP = 0, + NPU_OP_IRQ = 1, + NPU_OP_CONV = 2, + NPU_OP_DEPTHWISE = 3, + NPU_OP_POOL = 5, + NPU_OP_ELEMENTWISE = 6, + NPU_OP_DMA_START = 16, + NPU_OP_DMA_WAIT = 17, + NPU_OP_KERNEL_WAIT = 18, + NPU_OP_PMU_MASK = 19, + NPU_SET_IFM_PAD_TOP = 256, + NPU_SET_IFM_PAD_LEFT = 257, + NPU_SET_IFM_PAD_RIGHT = 258, + NPU_SET_IFM_PAD_BOTTOM = 259, + NPU_SET_IFM_DEPTH_M1 = 260, + NPU_SET_IFM_PRECISION = 261, + NPU_SET_IFM_UPSCALE = 263, + NPU_SET_IFM_ZERO_POINT = 265, + NPU_SET_IFM_WIDTH0_M1 = 266, + NPU_SET_IFM_HEIGHT0_M1 = 267, + NPU_SET_IFM_HEIGHT1_M1 = 268, + NPU_SET_IFM_IB_END = 269, + NPU_SET_IFM_REGION = 271, + NPU_SET_OFM_WIDTH_M1 = 273, + NPU_SET_OFM_HEIGHT_M1 = 274, + NPU_SET_OFM_DEPTH_M1 = 275, + NPU_SET_OFM_PRECISION = 276, + NPU_SET_OFM_BLK_WIDTH_M1 = 277, + NPU_SET_OFM_BLK_HEIGHT_M1 = 278, + NPU_SET_OFM_BLK_DEPTH_M1 = 279, + NPU_SET_OFM_ZERO_POINT = 280, + NPU_SET_OFM_WIDTH0_M1 = 282, + NPU_SET_OFM_HEIGHT0_M1 = 283, + NPU_SET_OFM_HEIGHT1_M1 = 284, + NPU_SET_OFM_REGION = 287, + NPU_SET_KERNEL_WIDTH_M1 = 288, + NPU_SET_KERNEL_HEIGHT_M1 = 289, + NPU_SET_KERNEL_STRIDE = 290, + NPU_SET_PARALLEL_MODE = 291, + NPU_SET_ACC_FORMAT = 292, + NPU_SET_ACTIVATION = 293, + NPU_SET_ACTIVATION_MIN = 294, + NPU_SET_ACTIVATION_MAX = 295, + NPU_SET_WEIGHT_REGION = 296, + NPU_SET_SCALE_REGION = 297, + NPU_SET_AB_START = 301, + NPU_SET_BLOCKDEP = 303, + NPU_SET_DMA0_SRC_REGION = 304, + NPU_SET_DMA0_DST_REGION = 305, + NPU_SET_DMA0_SIZE0 = 306, + NPU_SET_DMA0_SIZE1 = 307, + NPU_SET_IFM2_BROADCAST = 384, + NPU_SET_IFM2_SCALAR = 385, + NPU_SET_IFM2_PRECISION = 389, + NPU_SET_IFM2_ZERO_POINT = 393, + NPU_SET_IFM2_WIDTH0_M1 = 394, + NPU_SET_IFM2_HEIGHT0_M1 = 395, + NPU_SET_IFM2_HEIGHT1_M1 = 396, + NPU_SET_IFM2_IB_START = 397, + NPU_SET_IFM2_REGION = 399, +}; + +enum class cmd1_opcode : uint16_t +{ + NPU_SET_IFM_BASE0 = 0, + NPU_SET_IFM_BASE1 = 1, + NPU_SET_IFM_BASE2 = 2, + NPU_SET_IFM_BASE3 = 3, + NPU_SET_IFM_STRIDE_X = 4, + NPU_SET_IFM_STRIDE_Y = 5, + NPU_SET_IFM_STRIDE_C = 6, + NPU_SET_OFM_BASE0 = 16, + NPU_SET_OFM_BASE1 = 17, + NPU_SET_OFM_BASE2 = 18, + NPU_SET_OFM_BASE3 = 19, + NPU_SET_OFM_STRIDE_X = 20, + NPU_SET_OFM_STRIDE_Y = 21, + NPU_SET_OFM_STRIDE_C = 22, + NPU_SET_WEIGHT_BASE = 32, + NPU_SET_WEIGHT_LENGTH = 33, + NPU_SET_SCALE_BASE = 34, + NPU_SET_SCALE_LENGTH = 35, + NPU_SET_OFM_SCALE = 36, + NPU_SET_OPA_SCALE = 37, + NPU_SET_OPB_SCALE = 38, + NPU_SET_DMA0_SRC = 48, + NPU_SET_DMA0_DST = 49, + NPU_SET_DMA0_LEN = 50, + NPU_SET_DMA0_SKIP0 = 51, + NPU_SET_DMA0_SKIP1 = 52, + NPU_SET_IFM2_BASE0 = 128, + NPU_SET_IFM2_BASE1 = 129, + NPU_SET_IFM2_BASE2 = 130, + NPU_SET_IFM2_BASE3 = 131, + NPU_SET_IFM2_STRIDE_X = 132, + NPU_SET_IFM2_STRIDE_Y = 133, + NPU_SET_IFM2_STRIDE_C = 134, + NPU_SET_WEIGHT1_BASE = 144, + NPU_SET_WEIGHT1_LENGTH = 145, + NPU_SET_SCALE1_BASE = 146, + NPU_SET_SCALE1_LENGTH = 147, +}; + +enum class cmd_ctrl : uint8_t +{ + CMD0_CTRL = 0, + CMD1_CTRL = 1, +}; + +enum class custom_dma : uint8_t +{ + NOT_IMPLEMENTED = 0, + IMPLEMENTED = 1, +}; + +enum class dma_fault_src : uint8_t +{ + AXI_M0 = 0, + AXI_M1 = 1, +}; + +enum class dma_region_mode : uint8_t +{ + EXTERNAL = 0, + INTERNAL = 1, +}; + +enum class dma_stride_mode : uint8_t +{ + D1 = 0, + D2 = 1, + D3 = 2, +}; + +enum class elementwise_mode : uint8_t +{ + MUL = 0, + ADD = 1, + SUB = 2, + MIN = 3, + MAX = 4, + LRELU = 5, + ABS = 6, + CLZ = 7, + SHR = 8, + SHL = 9, +}; + +enum class functional_safety : uint8_t +{ + NOT_IMPLEMENTED = 0, + IMPLEMENTED = 1, +}; + +enum class ifm2_operand_order : uint8_t +{ + ORDER_B = 0, + ORDER_A = 1, +}; + +enum class ifm_scale_mode : uint8_t +{ + OPA_OPB_16 = 0, + OPA_32 = 1, + OPB_32 = 2, +}; + +enum class ifm_upscale_mode : uint8_t +{ + NONE = 0, + NEAREST = 1, + ZEROS = 2, +}; + +enum class kernel_decomposition : uint8_t +{ + D8X8 = 0, + D4X4 = 1, +}; + +enum class kernel_dilation : uint8_t +{ + NONE = 0, + X2 = 1, +}; + +enum class max_beats : uint8_t +{ + B64 = 0, + B128 = 1, + B256 = 2, +}; + +enum class mem_attr : uint8_t +{ + AXI0_OUTSTANDING_COUNTER0 = 0, + AXI0_OUTSTANDING_COUNTER1 = 1, + AXI1_OUTSTANDING_COUNTER2 = 2, + AXI1_OUTSTANDING_COUNTER3 = 3, +}; + +enum class ofm_scale_mode : uint8_t +{ + PER_CHANNEL = 0, + GLOBAL = 1, +}; + +enum class parallel_mode : uint8_t +{ + SINGLE_CORE = 0, + DUAL_CORE_DEPTH = 1, +}; + +enum class pmu_axi_channel : uint8_t +{ + RD_CMD = 0, + RD_IFM = 1, + RD_WEIGHTS = 2, + RD_SCALE_BIAS = 3, + RD_MEM2MEM = 4, + WR_OFM = 8, + WR_MEM2MEM = 9, +}; + +enum class pmu_event : uint16_t +{ + NO_EVENT = 0, + CYCLE = 17, + NPU_IDLE = 32, + CC_STALLED_ON_BLOCKDEP = 33, + CC_STALLED_ON_SHRAM_RECONFIG = 34, + NPU_ACTIVE = 35, + MAC_ACTIVE = 48, + MAC_ACTIVE_8BIT = 49, + MAC_ACTIVE_16BIT = 50, + MAC_DPU_ACTIVE = 51, + MAC_STALLED_BY_WD_ACC = 52, + MAC_STALLED_BY_WD = 53, + MAC_STALLED_BY_ACC = 54, + MAC_STALLED_BY_IB = 55, + MAC_ACTIVE_32BIT = 56, + MAC_STALLED_BY_INT_W = 57, + MAC_STALLED_BY_INT_ACC = 58, + AO_ACTIVE = 64, + AO_ACTIVE_8BIT = 65, + AO_ACTIVE_16BIT = 66, + AO_STALLED_BY_OFMP_OB = 67, + AO_STALLED_BY_OFMP = 68, + AO_STALLED_BY_OB = 69, + AO_STALLED_BY_ACC_IB = 70, + AO_STALLED_BY_ACC = 71, + AO_STALLED_BY_IB = 72, + WD_ACTIVE = 80, + WD_STALLED = 81, + WD_STALLED_BY_WS = 82, + WD_STALLED_BY_WD_BUF = 83, + WD_PARSE_ACTIVE = 84, + WD_PARSE_STALLED = 85, + WD_PARSE_STALLED_IN = 86, + WD_PARSE_STALLED_OUT = 87, + WD_TRANS_WS = 88, + WD_TRANS_WB = 89, + WD_TRANS_DW0 = 90, + WD_TRANS_DW1 = 91, + AXI0_RD_TRANS_ACCEPTED = 128, + AXI0_RD_TRANS_COMPLETED = 129, + AXI0_RD_DATA_BEAT_RECEIVED = 130, + AXI0_RD_TRAN_REQ_STALLED = 131, + AXI0_WR_TRANS_ACCEPTED = 132, + AXI0_WR_TRANS_COMPLETED_M = 133, + AXI0_WR_TRANS_COMPLETED_S = 134, + AXI0_WR_DATA_BEAT_WRITTEN = 135, + AXI0_WR_TRAN_REQ_STALLED = 136, + AXI0_WR_DATA_BEAT_STALLED = 137, + AXI0_ENABLED_CYCLES = 140, + AXI0_RD_STALL_LIMIT = 142, + AXI0_WR_STALL_LIMIT = 143, + AXI_LATENCY_ANY = 160, + AXI_LATENCY_32 = 161, + AXI_LATENCY_64 = 162, + AXI_LATENCY_128 = 163, + AXI_LATENCY_256 = 164, + AXI_LATENCY_512 = 165, + AXI_LATENCY_1024 = 166, + ECC_DMA = 176, + ECC_SB0 = 177, + AXI1_RD_TRANS_ACCEPTED = 384, + AXI1_RD_TRANS_COMPLETED = 385, + AXI1_RD_DATA_BEAT_RECEIVED = 386, + AXI1_RD_TRAN_REQ_STALLED = 387, + AXI1_WR_TRANS_ACCEPTED = 388, + AXI1_WR_TRANS_COMPLETED_M = 389, + AXI1_WR_TRANS_COMPLETED_S = 390, + AXI1_WR_DATA_BEAT_WRITTEN = 391, + AXI1_WR_TRAN_REQ_STALLED = 392, + AXI1_WR_DATA_BEAT_STALLED = 393, + AXI1_ENABLED_CYCLES = 396, + AXI1_RD_STALL_LIMIT = 398, + AXI1_WR_STALL_LIMIT = 399, + ECC_SB1 = 433, +}; + +enum class pooling_mode : uint8_t +{ + MAX = 0, + AVERAGE = 1, + REDUCE_SUM = 2, +}; + +enum class privilege_level : uint8_t +{ + USER = 0, + PRIVILEGED = 1, +}; + +enum class round_mode : uint8_t +{ + DBL = 0, + TRUNCATE = 1, + NATURAL = 2, +}; + +enum class security_level : uint8_t +{ + SECURE = 0, + NON_SECURE = 1, +}; + +enum class state : uint8_t +{ + STOPPED = 0, + RUNNING = 1, +}; + +enum class wd_core_slice_state : uint8_t +{ + HEADER = 0, + PALETTE = 1, + WEIGHTS = 2, +}; + +enum class wd_ctrl_state : uint8_t +{ + IDLE = 0, + DRAIN = 1, + OFD_INIT = 2, + OFD_RUN = 3, +}; + +enum class weight_order : uint8_t +{ + DEPTH_FIRST = 0, + PART_KERNEL_FIRST = 1, +}; + +#else + +enum acc_format +{ + ACC_FORMAT_I32 = 0, + ACC_FORMAT_I40 = 1, + ACC_FORMAT_F16 = 2, +}; + +enum activation_clip_range +{ + ACTIVATION_CLIP_RANGE_OFM_PRECISION = 0, + ACTIVATION_CLIP_RANGE_FORCE_UINT8 = 2, + ACTIVATION_CLIP_RANGE_FORCE_INT8 = 3, + ACTIVATION_CLIP_RANGE_FORCE_INT16 = 5, +}; + +enum activation_format +{ + ACTIVATION_FORMAT_NHWC = 0, + ACTIVATION_FORMAT_NHCWB16 = 1, +}; + +enum activation_function +{ + ACTIVATION_FUNCTION_RELU = 0, + ACTIVATION_FUNCTION_TANH = 3, + ACTIVATION_FUNCTION_SIGMOID = 4, + ACTIVATION_FUNCTION_TABLE_0 = 16, + ACTIVATION_FUNCTION_TABLE_1 = 17, + ACTIVATION_FUNCTION_TABLE_2 = 18, + ACTIVATION_FUNCTION_TABLE_3 = 19, + ACTIVATION_FUNCTION_TABLE_4 = 20, + ACTIVATION_FUNCTION_TABLE_5 = 21, + ACTIVATION_FUNCTION_TABLE_6 = 22, + ACTIVATION_FUNCTION_TABLE_7 = 23, +}; + +enum activation_precision +{ + ACTIVATION_PRECISION_B8 = 0, + ACTIVATION_PRECISION_B16 = 1, + ACTIVATION_PRECISION_B32 = 2, + ACTIVATION_PRECISION_B64 = 3, +}; + +enum activation_type +{ + ACTIVATION_TYPE_UNSIGNED = 0, + ACTIVATION_TYPE_SIGNED = 1, +}; + +enum axi_mem_encoding +{ + AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE = 0, + AXI_MEM_ENCODING_DEVICE_BUFFERABLE = 1, + AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2, + AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE = 3, + AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE = 4, + AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE = 5, + AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE = 6, + AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7, + AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE = 8, + AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE = 9, + AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE = 10, + AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11, +}; + +enum broadcast_mode +{ + BROADCAST_MODE_DISABLE = 0, + BROADCAST_MODE_ENABLE = 1, +}; + +enum cmd0_opcode +{ + CMD0_OPCODE_NPU_OP_STOP = 0, + CMD0_OPCODE_NPU_OP_IRQ = 1, + CMD0_OPCODE_NPU_OP_CONV = 2, + CMD0_OPCODE_NPU_OP_DEPTHWISE = 3, + CMD0_OPCODE_NPU_OP_POOL = 5, + CMD0_OPCODE_NPU_OP_ELEMENTWISE = 6, + CMD0_OPCODE_NPU_OP_DMA_START = 16, + CMD0_OPCODE_NPU_OP_DMA_WAIT = 17, + CMD0_OPCODE_NPU_OP_KERNEL_WAIT = 18, + CMD0_OPCODE_NPU_OP_PMU_MASK = 19, + CMD0_OPCODE_NPU_SET_IFM_PAD_TOP = 256, + CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT = 257, + CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT = 258, + CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM = 259, + CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1 = 260, + CMD0_OPCODE_NPU_SET_IFM_PRECISION = 261, + CMD0_OPCODE_NPU_SET_IFM_UPSCALE = 263, + CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT = 265, + CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1 = 266, + CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1 = 267, + CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1 = 268, + CMD0_OPCODE_NPU_SET_IFM_IB_END = 269, + CMD0_OPCODE_NPU_SET_IFM_REGION = 271, + CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1 = 273, + CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1 = 274, + CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1 = 275, + CMD0_OPCODE_NPU_SET_OFM_PRECISION = 276, + CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1 = 277, + CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1 = 278, + CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1 = 279, + CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT = 280, + CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1 = 282, + CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1 = 283, + CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1 = 284, + CMD0_OPCODE_NPU_SET_OFM_REGION = 287, + CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1 = 288, + CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1 = 289, + CMD0_OPCODE_NPU_SET_KERNEL_STRIDE = 290, + CMD0_OPCODE_NPU_SET_PARALLEL_MODE = 291, + CMD0_OPCODE_NPU_SET_ACC_FORMAT = 292, + CMD0_OPCODE_NPU_SET_ACTIVATION = 293, + CMD0_OPCODE_NPU_SET_ACTIVATION_MIN = 294, + CMD0_OPCODE_NPU_SET_ACTIVATION_MAX = 295, + CMD0_OPCODE_NPU_SET_WEIGHT_REGION = 296, + CMD0_OPCODE_NPU_SET_SCALE_REGION = 297, + CMD0_OPCODE_NPU_SET_AB_START = 301, + CMD0_OPCODE_NPU_SET_BLOCKDEP = 303, + CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION = 304, + CMD0_OPCODE_NPU_SET_DMA0_DST_REGION = 305, + CMD0_OPCODE_NPU_SET_DMA0_SIZE0 = 306, + CMD0_OPCODE_NPU_SET_DMA0_SIZE1 = 307, + CMD0_OPCODE_NPU_SET_IFM2_BROADCAST = 384, + CMD0_OPCODE_NPU_SET_IFM2_SCALAR = 385, + CMD0_OPCODE_NPU_SET_IFM2_PRECISION = 389, + CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT = 393, + CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1 = 394, + CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1 = 395, + CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1 = 396, + CMD0_OPCODE_NPU_SET_IFM2_IB_START = 397, + CMD0_OPCODE_NPU_SET_IFM2_REGION = 399, +}; + +enum cmd1_opcode +{ + CMD1_OPCODE_NPU_SET_IFM_BASE0 = 0, + CMD1_OPCODE_NPU_SET_IFM_BASE1 = 1, + CMD1_OPCODE_NPU_SET_IFM_BASE2 = 2, + CMD1_OPCODE_NPU_SET_IFM_BASE3 = 3, + CMD1_OPCODE_NPU_SET_IFM_STRIDE_X = 4, + CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y = 5, + CMD1_OPCODE_NPU_SET_IFM_STRIDE_C = 6, + CMD1_OPCODE_NPU_SET_OFM_BASE0 = 16, + CMD1_OPCODE_NPU_SET_OFM_BASE1 = 17, + CMD1_OPCODE_NPU_SET_OFM_BASE2 = 18, + CMD1_OPCODE_NPU_SET_OFM_BASE3 = 19, + CMD1_OPCODE_NPU_SET_OFM_STRIDE_X = 20, + CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y = 21, + CMD1_OPCODE_NPU_SET_OFM_STRIDE_C = 22, + CMD1_OPCODE_NPU_SET_WEIGHT_BASE = 32, + CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH = 33, + CMD1_OPCODE_NPU_SET_SCALE_BASE = 34, + CMD1_OPCODE_NPU_SET_SCALE_LENGTH = 35, + CMD1_OPCODE_NPU_SET_OFM_SCALE = 36, + CMD1_OPCODE_NPU_SET_OPA_SCALE = 37, + CMD1_OPCODE_NPU_SET_OPB_SCALE = 38, + CMD1_OPCODE_NPU_SET_DMA0_SRC = 48, + CMD1_OPCODE_NPU_SET_DMA0_DST = 49, + CMD1_OPCODE_NPU_SET_DMA0_LEN = 50, + CMD1_OPCODE_NPU_SET_DMA0_SKIP0 = 51, + CMD1_OPCODE_NPU_SET_DMA0_SKIP1 = 52, + CMD1_OPCODE_NPU_SET_IFM2_BASE0 = 128, + CMD1_OPCODE_NPU_SET_IFM2_BASE1 = 129, + CMD1_OPCODE_NPU_SET_IFM2_BASE2 = 130, + CMD1_OPCODE_NPU_SET_IFM2_BASE3 = 131, + CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X = 132, + CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y = 133, + CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C = 134, + CMD1_OPCODE_NPU_SET_WEIGHT1_BASE = 144, + CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH = 145, + CMD1_OPCODE_NPU_SET_SCALE1_BASE = 146, + CMD1_OPCODE_NPU_SET_SCALE1_LENGTH = 147, +}; + +enum cmd_ctrl +{ + CMD_CTRL_CMD0_CTRL = 0, + CMD_CTRL_CMD1_CTRL = 1, +}; + +enum custom_dma +{ + CUSTOM_DMA_NOT_IMPLEMENTED = 0, + CUSTOM_DMA_IMPLEMENTED = 1, +}; + +enum dma_fault_src +{ + DMA_FAULT_SRC_AXI_M0 = 0, + DMA_FAULT_SRC_AXI_M1 = 1, +}; + +enum dma_region_mode +{ + DMA_REGION_MODE_EXTERNAL = 0, + DMA_REGION_MODE_INTERNAL = 1, +}; + +enum dma_stride_mode +{ + DMA_STRIDE_MODE_D1 = 0, + DMA_STRIDE_MODE_D2 = 1, + DMA_STRIDE_MODE_D3 = 2, +}; + +enum elementwise_mode +{ + ELEMENTWISE_MODE_MUL = 0, + ELEMENTWISE_MODE_ADD = 1, + ELEMENTWISE_MODE_SUB = 2, + ELEMENTWISE_MODE_MIN = 3, + ELEMENTWISE_MODE_MAX = 4, + ELEMENTWISE_MODE_LRELU = 5, + ELEMENTWISE_MODE_ABS = 6, + ELEMENTWISE_MODE_CLZ = 7, + ELEMENTWISE_MODE_SHR = 8, + ELEMENTWISE_MODE_SHL = 9, +}; + +enum functional_safety +{ + FUNCTIONAL_SAFETY_NOT_IMPLEMENTED = 0, + FUNCTIONAL_SAFETY_IMPLEMENTED = 1, +}; + +enum ifm2_operand_order +{ + IFM2_OPERAND_ORDER_ORDER_B = 0, + IFM2_OPERAND_ORDER_ORDER_A = 1, +}; + +enum ifm_scale_mode +{ + IFM_SCALE_MODE_OPA_OPB_16 = 0, + IFM_SCALE_MODE_OPA_32 = 1, + IFM_SCALE_MODE_OPB_32 = 2, +}; + +enum ifm_upscale_mode +{ + IFM_UPSCALE_MODE_NONE = 0, + IFM_UPSCALE_MODE_NEAREST = 1, + IFM_UPSCALE_MODE_ZEROS = 2, +}; + +enum kernel_decomposition +{ + KERNEL_DECOMPOSITION_D8X8 = 0, + KERNEL_DECOMPOSITION_D4X4 = 1, +}; + +enum kernel_dilation +{ + KERNEL_DILATION_NONE = 0, + KERNEL_DILATION_X2 = 1, +}; + +enum max_beats +{ + MAX_BEATS_B64 = 0, + MAX_BEATS_B128 = 1, + MAX_BEATS_B256 = 2, +}; + +enum mem_attr +{ + MEM_ATTR_AXI0_OUTSTANDING_COUNTER0 = 0, + MEM_ATTR_AXI0_OUTSTANDING_COUNTER1 = 1, + MEM_ATTR_AXI1_OUTSTANDING_COUNTER2 = 2, + MEM_ATTR_AXI1_OUTSTANDING_COUNTER3 = 3, +}; + +enum ofm_scale_mode +{ + OFM_SCALE_MODE_PER_CHANNEL = 0, + OFM_SCALE_MODE_GLOBAL = 1, +}; + +enum parallel_mode +{ + PARALLEL_MODE_SINGLE_CORE = 0, + PARALLEL_MODE_DUAL_CORE_DEPTH = 1, +}; + +enum pmu_axi_channel +{ + PMU_AXI_CHANNEL_RD_CMD = 0, + PMU_AXI_CHANNEL_RD_IFM = 1, + PMU_AXI_CHANNEL_RD_WEIGHTS = 2, + PMU_AXI_CHANNEL_RD_SCALE_BIAS = 3, + PMU_AXI_CHANNEL_RD_MEM2MEM = 4, + PMU_AXI_CHANNEL_WR_OFM = 8, + PMU_AXI_CHANNEL_WR_MEM2MEM = 9, +}; + +enum pmu_event +{ + PMU_EVENT_NO_EVENT = 0, + PMU_EVENT_CYCLE = 17, + PMU_EVENT_NPU_IDLE = 32, + PMU_EVENT_CC_STALLED_ON_BLOCKDEP = 33, + PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG = 34, + PMU_EVENT_NPU_ACTIVE = 35, + PMU_EVENT_MAC_ACTIVE = 48, + PMU_EVENT_MAC_ACTIVE_8BIT = 49, + PMU_EVENT_MAC_ACTIVE_16BIT = 50, + PMU_EVENT_MAC_DPU_ACTIVE = 51, + PMU_EVENT_MAC_STALLED_BY_WD_ACC = 52, + PMU_EVENT_MAC_STALLED_BY_WD = 53, + PMU_EVENT_MAC_STALLED_BY_ACC = 54, + PMU_EVENT_MAC_STALLED_BY_IB = 55, + PMU_EVENT_MAC_ACTIVE_32BIT = 56, + PMU_EVENT_MAC_STALLED_BY_INT_W = 57, + PMU_EVENT_MAC_STALLED_BY_INT_ACC = 58, + PMU_EVENT_AO_ACTIVE = 64, + PMU_EVENT_AO_ACTIVE_8BIT = 65, + PMU_EVENT_AO_ACTIVE_16BIT = 66, + PMU_EVENT_AO_STALLED_BY_OFMP_OB = 67, + PMU_EVENT_AO_STALLED_BY_OFMP = 68, + PMU_EVENT_AO_STALLED_BY_OB = 69, + PMU_EVENT_AO_STALLED_BY_ACC_IB = 70, + PMU_EVENT_AO_STALLED_BY_ACC = 71, + PMU_EVENT_AO_STALLED_BY_IB = 72, + PMU_EVENT_WD_ACTIVE = 80, + PMU_EVENT_WD_STALLED = 81, + PMU_EVENT_WD_STALLED_BY_WS = 82, + PMU_EVENT_WD_STALLED_BY_WD_BUF = 83, + PMU_EVENT_WD_PARSE_ACTIVE = 84, + PMU_EVENT_WD_PARSE_STALLED = 85, + PMU_EVENT_WD_PARSE_STALLED_IN = 86, + PMU_EVENT_WD_PARSE_STALLED_OUT = 87, + PMU_EVENT_WD_TRANS_WS = 88, + PMU_EVENT_WD_TRANS_WB = 89, + PMU_EVENT_WD_TRANS_DW0 = 90, + PMU_EVENT_WD_TRANS_DW1 = 91, + PMU_EVENT_AXI0_RD_TRANS_ACCEPTED = 128, + PMU_EVENT_AXI0_RD_TRANS_COMPLETED = 129, + PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED = 130, + PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED = 131, + PMU_EVENT_AXI0_WR_TRANS_ACCEPTED = 132, + PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M = 133, + PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S = 134, + PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN = 135, + PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED = 136, + PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED = 137, + PMU_EVENT_AXI0_ENABLED_CYCLES = 140, + PMU_EVENT_AXI0_RD_STALL_LIMIT = 142, + PMU_EVENT_AXI0_WR_STALL_LIMIT = 143, + PMU_EVENT_AXI_LATENCY_ANY = 160, + PMU_EVENT_AXI_LATENCY_32 = 161, + PMU_EVENT_AXI_LATENCY_64 = 162, + PMU_EVENT_AXI_LATENCY_128 = 163, + PMU_EVENT_AXI_LATENCY_256 = 164, + PMU_EVENT_AXI_LATENCY_512 = 165, + PMU_EVENT_AXI_LATENCY_1024 = 166, + PMU_EVENT_ECC_DMA = 176, + PMU_EVENT_ECC_SB0 = 177, + PMU_EVENT_AXI1_RD_TRANS_ACCEPTED = 384, + PMU_EVENT_AXI1_RD_TRANS_COMPLETED = 385, + PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED = 386, + PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED = 387, + PMU_EVENT_AXI1_WR_TRANS_ACCEPTED = 388, + PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M = 389, + PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S = 390, + PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN = 391, + PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED = 392, + PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED = 393, + PMU_EVENT_AXI1_ENABLED_CYCLES = 396, + PMU_EVENT_AXI1_RD_STALL_LIMIT = 398, + PMU_EVENT_AXI1_WR_STALL_LIMIT = 399, + PMU_EVENT_ECC_SB1 = 433, +}; + +enum pooling_mode +{ + POOLING_MODE_MAX = 0, + POOLING_MODE_AVERAGE = 1, + POOLING_MODE_REDUCE_SUM = 2, +}; + +enum privilege_level +{ + PRIVILEGE_LEVEL_USER = 0, + PRIVILEGE_LEVEL_PRIVILEGED = 1, +}; + +enum round_mode +{ + ROUND_MODE_DBL = 0, + ROUND_MODE_TRUNCATE = 1, + ROUND_MODE_NATURAL = 2, +}; + +enum security_level +{ + SECURITY_LEVEL_SECURE = 0, + SECURITY_LEVEL_NON_SECURE = 1, +}; + +enum state +{ + STATE_STOPPED = 0, + STATE_RUNNING = 1, +}; + +enum wd_core_slice_state +{ + WD_CORE_SLICE_STATE_HEADER = 0, + WD_CORE_SLICE_STATE_PALETTE = 1, + WD_CORE_SLICE_STATE_WEIGHTS = 2, +}; + +enum wd_ctrl_state +{ + WD_CTRL_STATE_IDLE = 0, + WD_CTRL_STATE_DRAIN = 1, + WD_CTRL_STATE_OFD_INIT = 2, + WD_CTRL_STATE_OFD_RUN = 3, +}; + +enum weight_order +{ + WEIGHT_ORDER_DEPTH_FIRST = 0, + WEIGHT_ORDER_PART_KERNEL_FIRST = 1, +}; + +#endif + +#ifdef NPU_DISASSEMBLE + +static const char *acc_format_str[] = { + "ACC_FORMAT_I32", + "ACC_FORMAT_I40", + "ACC_FORMAT_F16", +}; + +static const char *activation_clip_range_str[] = { + "ACTIVATION_CLIP_RANGE_OFM_PRECISION", + "****", + "ACTIVATION_CLIP_RANGE_FORCE_UINT8", + "ACTIVATION_CLIP_RANGE_FORCE_INT8", + "****", + "ACTIVATION_CLIP_RANGE_FORCE_INT16", +}; + +static const char *activation_format_str[] = { + "ACTIVATION_FORMAT_NHWC", + "ACTIVATION_FORMAT_NHCWB16", +}; + +static const char *activation_function_str[] = { + "ACTIVATION_FUNCTION_RELU", + "****", + "****", + "ACTIVATION_FUNCTION_TANH", + "ACTIVATION_FUNCTION_SIGMOID", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "ACTIVATION_FUNCTION_TABLE_0", + "ACTIVATION_FUNCTION_TABLE_1", + "ACTIVATION_FUNCTION_TABLE_2", + "ACTIVATION_FUNCTION_TABLE_3", + "ACTIVATION_FUNCTION_TABLE_4", + "ACTIVATION_FUNCTION_TABLE_5", + "ACTIVATION_FUNCTION_TABLE_6", + "ACTIVATION_FUNCTION_TABLE_7", +}; + +static const char *activation_precision_str[] = { + "ACTIVATION_PRECISION_B8", + "ACTIVATION_PRECISION_B16", + "ACTIVATION_PRECISION_B32", + "ACTIVATION_PRECISION_B64", +}; + +static const char *activation_type_str[] = { + "ACTIVATION_TYPE_UNSIGNED", + "ACTIVATION_TYPE_SIGNED", +}; + +static const char *axi_mem_encoding_str[] = { + "AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE", + "AXI_MEM_ENCODING_DEVICE_BUFFERABLE", + "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE", + "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE", + "AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE", + "AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE", +}; + +static const char *broadcast_mode_str[] = { + "BROADCAST_MODE_DISABLE", + "BROADCAST_MODE_ENABLE", +}; + +static const char *cmd0_opcode_str[] = { + "CMD0_OPCODE_NPU_OP_STOP", + "CMD0_OPCODE_NPU_OP_IRQ", + "CMD0_OPCODE_NPU_OP_CONV", + "CMD0_OPCODE_NPU_OP_DEPTHWISE", + "****", + "CMD0_OPCODE_NPU_OP_POOL", + "CMD0_OPCODE_NPU_OP_ELEMENTWISE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_OP_DMA_START", + "CMD0_OPCODE_NPU_OP_DMA_WAIT", + "CMD0_OPCODE_NPU_OP_KERNEL_WAIT", + "CMD0_OPCODE_NPU_OP_PMU_MASK", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM_PAD_TOP", + "CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT", + "CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT", + "CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM", + "CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1", + "CMD0_OPCODE_NPU_SET_IFM_PRECISION", + "****", + "CMD0_OPCODE_NPU_SET_IFM_UPSCALE", + "****", + "CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT", + "CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1", + "CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1", + "CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1", + "CMD0_OPCODE_NPU_SET_IFM_IB_END", + "****", + "CMD0_OPCODE_NPU_SET_IFM_REGION", + "****", + "CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1", + "CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_PRECISION", + "CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1", + "CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1", + "CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT", + "****", + "CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1", + "CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1", + "CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1", + "****", + "****", + "CMD0_OPCODE_NPU_SET_OFM_REGION", + "CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1", + "CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1", + "CMD0_OPCODE_NPU_SET_KERNEL_STRIDE", + "CMD0_OPCODE_NPU_SET_PARALLEL_MODE", + "CMD0_OPCODE_NPU_SET_ACC_FORMAT", + "CMD0_OPCODE_NPU_SET_ACTIVATION", + "CMD0_OPCODE_NPU_SET_ACTIVATION_MIN", + "CMD0_OPCODE_NPU_SET_ACTIVATION_MAX", + "CMD0_OPCODE_NPU_SET_WEIGHT_REGION", + "CMD0_OPCODE_NPU_SET_SCALE_REGION", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_AB_START", + "****", + "CMD0_OPCODE_NPU_SET_BLOCKDEP", + "CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION", + "CMD0_OPCODE_NPU_SET_DMA0_DST_REGION", + "CMD0_OPCODE_NPU_SET_DMA0_SIZE0", + "CMD0_OPCODE_NPU_SET_DMA0_SIZE1", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_BROADCAST", + "CMD0_OPCODE_NPU_SET_IFM2_SCALAR", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_PRECISION", + "****", + "****", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT", + "CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1", + "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1", + "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1", + "CMD0_OPCODE_NPU_SET_IFM2_IB_START", + "****", + "CMD0_OPCODE_NPU_SET_IFM2_REGION", +}; + +static const char *cmd1_opcode_str[] = { + "CMD1_OPCODE_NPU_SET_IFM_BASE0", + "CMD1_OPCODE_NPU_SET_IFM_BASE1", + "CMD1_OPCODE_NPU_SET_IFM_BASE2", + "CMD1_OPCODE_NPU_SET_IFM_BASE3", + "CMD1_OPCODE_NPU_SET_IFM_STRIDE_X", + "CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y", + "CMD1_OPCODE_NPU_SET_IFM_STRIDE_C", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_OFM_BASE0", + "CMD1_OPCODE_NPU_SET_OFM_BASE1", + "CMD1_OPCODE_NPU_SET_OFM_BASE2", + "CMD1_OPCODE_NPU_SET_OFM_BASE3", + "CMD1_OPCODE_NPU_SET_OFM_STRIDE_X", + "CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y", + "CMD1_OPCODE_NPU_SET_OFM_STRIDE_C", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_WEIGHT_BASE", + "CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH", + "CMD1_OPCODE_NPU_SET_SCALE_BASE", + "CMD1_OPCODE_NPU_SET_SCALE_LENGTH", + "CMD1_OPCODE_NPU_SET_OFM_SCALE", + "CMD1_OPCODE_NPU_SET_OPA_SCALE", + "CMD1_OPCODE_NPU_SET_OPB_SCALE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_DMA0_SRC", + "CMD1_OPCODE_NPU_SET_DMA0_DST", + "CMD1_OPCODE_NPU_SET_DMA0_LEN", + "CMD1_OPCODE_NPU_SET_DMA0_SKIP0", + "CMD1_OPCODE_NPU_SET_DMA0_SKIP1", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_IFM2_BASE0", + "CMD1_OPCODE_NPU_SET_IFM2_BASE1", + "CMD1_OPCODE_NPU_SET_IFM2_BASE2", + "CMD1_OPCODE_NPU_SET_IFM2_BASE3", + "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X", + "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y", + "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "CMD1_OPCODE_NPU_SET_WEIGHT1_BASE", + "CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH", + "CMD1_OPCODE_NPU_SET_SCALE1_BASE", + "CMD1_OPCODE_NPU_SET_SCALE1_LENGTH", +}; + +static const char *cmd_ctrl_str[] = { + "CMD_CTRL_CMD0_CTRL", + "CMD_CTRL_CMD1_CTRL", +}; + +static const char *custom_dma_str[] = { + "CUSTOM_DMA_NOT_IMPLEMENTED", + "CUSTOM_DMA_IMPLEMENTED", +}; + +static const char *dma_fault_src_str[] = { + "DMA_FAULT_SRC_AXI_M0", + "DMA_FAULT_SRC_AXI_M1", +}; + +static const char *dma_region_mode_str[] = { + "DMA_REGION_MODE_EXTERNAL", + "DMA_REGION_MODE_INTERNAL", +}; + +static const char *dma_stride_mode_str[] = { + "DMA_STRIDE_MODE_D1", + "DMA_STRIDE_MODE_D2", + "DMA_STRIDE_MODE_D3", +}; + +static const char *elementwise_mode_str[] = { + "ELEMENTWISE_MODE_MUL", + "ELEMENTWISE_MODE_ADD", + "ELEMENTWISE_MODE_SUB", + "ELEMENTWISE_MODE_MIN", + "ELEMENTWISE_MODE_MAX", + "ELEMENTWISE_MODE_LRELU", + "ELEMENTWISE_MODE_ABS", + "ELEMENTWISE_MODE_CLZ", + "ELEMENTWISE_MODE_SHR", + "ELEMENTWISE_MODE_SHL", +}; + +static const char *functional_safety_str[] = { + "FUNCTIONAL_SAFETY_NOT_IMPLEMENTED", + "FUNCTIONAL_SAFETY_IMPLEMENTED", +}; + +static const char *ifm2_operand_order_str[] = { + "IFM2_OPERAND_ORDER_ORDER_B", + "IFM2_OPERAND_ORDER_ORDER_A", +}; + +static const char *ifm_scale_mode_str[] = { + "IFM_SCALE_MODE_OPA_OPB_16", + "IFM_SCALE_MODE_OPA_32", + "IFM_SCALE_MODE_OPB_32", +}; + +static const char *ifm_upscale_mode_str[] = { + "IFM_UPSCALE_MODE_NONE", + "IFM_UPSCALE_MODE_NEAREST", + "IFM_UPSCALE_MODE_ZEROS", +}; + +static const char *kernel_decomposition_str[] = { + "KERNEL_DECOMPOSITION_D8X8", + "KERNEL_DECOMPOSITION_D4X4", +}; + +static const char *kernel_dilation_str[] = { + "KERNEL_DILATION_NONE", + "KERNEL_DILATION_X2", +}; + +static const char *max_beats_str[] = { + "MAX_BEATS_B64", + "MAX_BEATS_B128", + "MAX_BEATS_B256", +}; + +static const char *mem_attr_str[] = { + "MEM_ATTR_AXI0_OUTSTANDING_COUNTER0", + "MEM_ATTR_AXI0_OUTSTANDING_COUNTER1", + "MEM_ATTR_AXI1_OUTSTANDING_COUNTER2", + "MEM_ATTR_AXI1_OUTSTANDING_COUNTER3", +}; + +static const char *ofm_scale_mode_str[] = { + "OFM_SCALE_MODE_PER_CHANNEL", + "OFM_SCALE_MODE_GLOBAL", +}; + +static const char *parallel_mode_str[] = { + "PARALLEL_MODE_SINGLE_CORE", + "PARALLEL_MODE_DUAL_CORE_DEPTH", +}; + +static const char *pmu_axi_channel_str[] = { + "PMU_AXI_CHANNEL_RD_CMD", + "PMU_AXI_CHANNEL_RD_IFM", + "PMU_AXI_CHANNEL_RD_WEIGHTS", + "PMU_AXI_CHANNEL_RD_SCALE_BIAS", + "PMU_AXI_CHANNEL_RD_MEM2MEM", + "****", + "****", + "****", + "PMU_AXI_CHANNEL_WR_OFM", + "PMU_AXI_CHANNEL_WR_MEM2MEM", +}; + +static const char *pmu_event_str[] = { + "PMU_EVENT_NO_EVENT", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_CYCLE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_NPU_IDLE", + "PMU_EVENT_CC_STALLED_ON_BLOCKDEP", + "PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG", + "PMU_EVENT_NPU_ACTIVE", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_MAC_ACTIVE", + "PMU_EVENT_MAC_ACTIVE_8BIT", + "PMU_EVENT_MAC_ACTIVE_16BIT", + "PMU_EVENT_MAC_DPU_ACTIVE", + "PMU_EVENT_MAC_STALLED_BY_WD_ACC", + "PMU_EVENT_MAC_STALLED_BY_WD", + "PMU_EVENT_MAC_STALLED_BY_ACC", + "PMU_EVENT_MAC_STALLED_BY_IB", + "PMU_EVENT_MAC_ACTIVE_32BIT", + "PMU_EVENT_MAC_STALLED_BY_INT_W", + "PMU_EVENT_MAC_STALLED_BY_INT_ACC", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AO_ACTIVE", + "PMU_EVENT_AO_ACTIVE_8BIT", + "PMU_EVENT_AO_ACTIVE_16BIT", + "PMU_EVENT_AO_STALLED_BY_OFMP_OB", + "PMU_EVENT_AO_STALLED_BY_OFMP", + "PMU_EVENT_AO_STALLED_BY_OB", + "PMU_EVENT_AO_STALLED_BY_ACC_IB", + "PMU_EVENT_AO_STALLED_BY_ACC", + "PMU_EVENT_AO_STALLED_BY_IB", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_WD_ACTIVE", + "PMU_EVENT_WD_STALLED", + "PMU_EVENT_WD_STALLED_BY_WS", + "PMU_EVENT_WD_STALLED_BY_WD_BUF", + "PMU_EVENT_WD_PARSE_ACTIVE", + "PMU_EVENT_WD_PARSE_STALLED", + "PMU_EVENT_WD_PARSE_STALLED_IN", + "PMU_EVENT_WD_PARSE_STALLED_OUT", + "PMU_EVENT_WD_TRANS_WS", + "PMU_EVENT_WD_TRANS_WB", + "PMU_EVENT_WD_TRANS_DW0", + "PMU_EVENT_WD_TRANS_DW1", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AXI0_RD_TRANS_ACCEPTED", + "PMU_EVENT_AXI0_RD_TRANS_COMPLETED", + "PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED", + "PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED", + "PMU_EVENT_AXI0_WR_TRANS_ACCEPTED", + "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M", + "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S", + "PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN", + "PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED", + "PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED", + "****", + "****", + "PMU_EVENT_AXI0_ENABLED_CYCLES", + "****", + "PMU_EVENT_AXI0_RD_STALL_LIMIT", + "PMU_EVENT_AXI0_WR_STALL_LIMIT", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AXI_LATENCY_ANY", + "PMU_EVENT_AXI_LATENCY_32", + "PMU_EVENT_AXI_LATENCY_64", + "PMU_EVENT_AXI_LATENCY_128", + "PMU_EVENT_AXI_LATENCY_256", + "PMU_EVENT_AXI_LATENCY_512", + "PMU_EVENT_AXI_LATENCY_1024", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_ECC_DMA", + "PMU_EVENT_ECC_SB0", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_AXI1_RD_TRANS_ACCEPTED", + "PMU_EVENT_AXI1_RD_TRANS_COMPLETED", + "PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED", + "PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED", + "PMU_EVENT_AXI1_WR_TRANS_ACCEPTED", + "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M", + "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S", + "PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN", + "PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED", + "PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED", + "****", + "****", + "PMU_EVENT_AXI1_ENABLED_CYCLES", + "****", + "PMU_EVENT_AXI1_RD_STALL_LIMIT", + "PMU_EVENT_AXI1_WR_STALL_LIMIT", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "****", + "PMU_EVENT_ECC_SB1", +}; + +static const char *pooling_mode_str[] = { + "POOLING_MODE_MAX", + "POOLING_MODE_AVERAGE", + "POOLING_MODE_REDUCE_SUM", +}; + +static const char *privilege_level_str[] = { + "PRIVILEGE_LEVEL_USER", + "PRIVILEGE_LEVEL_PRIVILEGED", +}; + +static const char *round_mode_str[] = { + "ROUND_MODE_DBL", + "ROUND_MODE_TRUNCATE", + "ROUND_MODE_NATURAL", +}; + +static const char *security_level_str[] = { + "SECURITY_LEVEL_SECURE", + "SECURITY_LEVEL_NON_SECURE", +}; + +static const char *state_str[] = { + "STATE_STOPPED", + "STATE_RUNNING", +}; + +static const char *wd_core_slice_state_str[] = { + "WD_CORE_SLICE_STATE_HEADER", + "WD_CORE_SLICE_STATE_PALETTE", + "WD_CORE_SLICE_STATE_WEIGHTS", +}; + +static const char *wd_ctrl_state_str[] = { + "WD_CTRL_STATE_IDLE", + "WD_CTRL_STATE_DRAIN", + "WD_CTRL_STATE_OFD_INIT", + "WD_CTRL_STATE_OFD_RUN", +}; + +static const char *weight_order_str[] = { + "WEIGHT_ORDER_DEPTH_FIRST", + "WEIGHT_ORDER_PART_KERNEL_FIRST", +}; + +#endif + +// Register type structs +// id_r - ID register +struct id_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t version_status : 4; // This is the version of the product + uint32_t version_minor : 4; // This is the n for the P part of an RnPn release number + uint32_t version_major : 4; // This is the n for the R part of an RnPn release number + uint32_t product_major : 4; // Product major ID number (unique per base product) + uint32_t arch_patch_rev : 4; // This is the patch number of the architecture version a.b + uint32_t + arch_minor_rev : 8; // This is the minor architecture version number, b in the architecture version a.b + uint32_t + arch_major_rev : 4; // This is the major architecture version number, a in the architecture version a.b + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR id_r() : word0(268853249) {} + CONSTEXPR id_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + id_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_version_status() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + uint32_t get_version_status() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR id_r &set_version_status(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + volatile id_r &set_version_status(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_version_minor() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + uint32_t get_version_minor() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR id_r &set_version_minor(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + volatile id_r &set_version_minor(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_version_major() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 8); + return value; + } + uint32_t get_version_major() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR id_r &set_version_major(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8); + return *this; + } + volatile id_r &set_version_major(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_product_major() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + uint32_t get_product_major() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR id_r &set_product_major(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + volatile id_r &set_product_major(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_arch_patch_rev() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 16); + return value; + } + uint32_t get_arch_patch_rev() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR id_r &set_arch_patch_rev(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16); + return *this; + } + volatile id_r &set_arch_patch_rev(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_arch_minor_rev() const + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 20); + return value; + } + uint32_t get_arch_minor_rev() const volatile + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 20); + return value; + } + CONSTEXPR id_r &set_arch_minor_rev(uint32_t value) + { + word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20); + return *this; + } + volatile id_r &set_arch_minor_rev(uint32_t value) volatile + { + word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20); + return *this; + } + CONSTEXPR uint32_t get_arch_major_rev() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + uint32_t get_arch_major_rev() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + CONSTEXPR id_r &set_arch_major_rev(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } + volatile id_r &set_arch_major_rev(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } +#endif +}; + +// status_r - Register describes the current operating status of the NPU +struct status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t state : 1; // NPU state, 0 = Stopped, 1 = Running + uint32_t irq_raised : 1; // Raw IRQ status, 0 = IRQ not raised, 1 = IRQ raised. IRQ is cleared using command + // register bit 1 + uint32_t + bus_status : 1; // 0=OK, 1=Bus abort detected and processing halted (NPU will reach IDLE state and not + // to start process any more commands/AXI transactions). Can only be cleared by a reset + uint32_t reset_status : 1; // Reset is ongoing and only this register can be read (other registers read as 0 + // and writes are ignored.) A value of 0 means NPU is not being reset and can be + // accessed as normal + uint32_t + cmd_parse_error : 1; // 0=No error 1=Command stream parsing error detected. Can only be cleared by reset + uint32_t cmd_end_reached : 1; // 0=Not reached, 1=Reached. Cleared by writing QBASE or QSIZE when NPU is in + // stopped state + uint32_t pmu_irq_raised : 1; // 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command register bit 1 + uint32_t wd_fault : 1; // Weight decoder state: 0=no fault 1=weight decoder decompression fault. Can only be + // cleared by reset + uint32_t ecc_fault : 1; // ECC state for internal RAMs: 0=no fault 1=ECC fault signalled. Can only be + // cleared by reset + uint32_t reserved0 : 2; + uint32_t faulting_interface : 1; // Faulting interface on bus abort + uint32_t faulting_channel : 4; // Faulting channel on a bus abort. Read: 0=Cmd 1=IFM 2=Weights 3=Scale+Bias + // 4=Mem2Mem; Write: 8=OFM 9=Mem2Mem + uint32_t irq_history_mask : 16; // IRQ History mask + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR status_r() : word0(8) {} + CONSTEXPR status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + status_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::state get_state() const + { + NPU_NAMESPACE::state value = static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::state get_state() const volatile + { + NPU_NAMESPACE::state value = static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR status_r &set_state(NPU_NAMESPACE::state value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + volatile status_r &set_state(NPU_NAMESPACE::state value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR uint32_t get_irq_raised() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_irq_raised() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR status_r &set_irq_raised(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile status_r &set_irq_raised(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_bus_status() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_bus_status() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR status_r &set_bus_status(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile status_r &set_bus_status(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_reset_status() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_reset_status() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR status_r &set_reset_status(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile status_r &set_reset_status(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_cmd_parse_error() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_cmd_parse_error() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR status_r &set_cmd_parse_error(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile status_r &set_cmd_parse_error(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_cmd_end_reached() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_cmd_end_reached() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR status_r &set_cmd_end_reached(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile status_r &set_cmd_end_reached(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_pmu_irq_raised() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_pmu_irq_raised() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR status_r &set_pmu_irq_raised(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile status_r &set_pmu_irq_raised(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_wd_fault() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_wd_fault() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR status_r &set_wd_fault(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile status_r &set_wd_fault(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_ecc_fault() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_ecc_fault() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR status_r &set_ecc_fault(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile status_r &set_ecc_fault(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_fault_src get_faulting_interface() const + { + NPU_NAMESPACE::dma_fault_src value = static_cast(((1U << 1) - 1) & (word0 >> 11)); + return value; + } + NPU_NAMESPACE::dma_fault_src get_faulting_interface() const volatile + { + NPU_NAMESPACE::dma_fault_src value = static_cast(((1U << 1) - 1) & (word0 >> 11)); + return value; + } + CONSTEXPR status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 11); + return *this; + } + volatile status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 11); + return *this; + } + CONSTEXPR uint32_t get_faulting_channel() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + uint32_t get_faulting_channel() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR status_r &set_faulting_channel(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + volatile status_r &set_faulting_channel(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_irq_history_mask() const + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + uint32_t get_irq_history_mask() const volatile + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR status_r &set_irq_history_mask(uint32_t value) + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } + volatile status_r &set_irq_history_mask(uint32_t value) volatile + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } +#endif +}; + +// cmd_r - Command register, reads as last written command +struct cmd_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t transition_to_running_state : 1; // Write 1 to transition the NPU to running state. Writing 0 has + // no effect + uint32_t clear_irq : 1; // Write 1 to clear the IRQ status in the STATUS register. Writing 0 has no effect + uint32_t clock_q_enable : 1; // Write 1 to this bit to enable clock off using clock q-interface and enable + // the requester clock gate + uint32_t power_q_enable : 1; // Write 1 to this bit to enable power off using power q-interface + uint32_t + stop_request : 1; // Write 1 to this bit to request STOP after completing any already-started commands + uint32_t reserved0 : 11; + uint32_t clear_irq_history : 16; // Clears the IRQ history mask + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cmd_r() : word0(12) {} + CONSTEXPR cmd_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cmd_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_transition_to_running_state() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_transition_to_running_state() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR cmd_r &set_transition_to_running_state(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile cmd_r &set_transition_to_running_state(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_clear_irq() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_clear_irq() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR cmd_r &set_clear_irq(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile cmd_r &set_clear_irq(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_clock_q_enable() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_clock_q_enable() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR cmd_r &set_clock_q_enable(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile cmd_r &set_clock_q_enable(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_power_q_enable() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_power_q_enable() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR cmd_r &set_power_q_enable(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile cmd_r &set_power_q_enable(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_stop_request() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_stop_request() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR cmd_r &set_stop_request(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile cmd_r &set_stop_request(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_clear_irq_history() const + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + uint32_t get_clear_irq_history() const volatile + { + uint32_t value = ((1U << 16) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR cmd_r &set_clear_irq_history(uint32_t value) + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } + volatile cmd_r &set_clear_irq_history(uint32_t value) volatile + { + word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16); + return *this; + } +#endif +}; + +// reset_r - Request Reset and new security mode +struct reset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t pending_CPL : 1; // Current privilege level 0=User 1=Privileged + uint32_t pending_CSL : 1; // Current security level 0=Secure 1=Non secure + uint32_t reserved0 : 30; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR reset_r() : word0(0) {} + CONSTEXPR reset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + reset_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::privilege_level get_pending_CPL() const + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::privilege_level get_pending_CPL() const volatile + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + volatile reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::security_level get_pending_CSL() const + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + NPU_NAMESPACE::security_level get_pending_CSL() const volatile + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + CONSTEXPR reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } + volatile reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } +#endif +}; + +// qbase_r - Base address of the command stream in bytes +struct qbase_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR qbase_r() : word0(0), word1(0) {} + CONSTEXPR qbase_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + qbase_r copy() volatile + { + return *this; + } +#endif +}; + +// qread_r - Read offset in the command stream in bytes. Multiple of 4 in the range 0 to 16 MB +struct qread_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t QREAD : 32; // The read offset of the current command under execution + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR qread_r() : word0(0) {} + CONSTEXPR qread_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + qread_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_QREAD() const + { + uint32_t value = word0; + return value; + } + uint32_t get_QREAD() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR qread_r &set_QREAD(uint32_t value) + { + word0 = value; + return *this; + } + volatile qread_r &set_QREAD(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// qconfig_r - AXI configuration for the command stream in the range 0-3. Same encoding as for REGIONCFG +struct qconfig_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cmd_region0 : 2; // Command region configuration + uint32_t reserved0 : 30; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR qconfig_r() : word0(0) {} + CONSTEXPR qconfig_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + qconfig_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_cmd_region0() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::mem_attr get_cmd_region0() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } +#endif +}; + +// qsize_r - Size of the command stream in bytes. Multiple of 4 in the range 0 to 16 MB +struct qsize_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t QSIZE : 32; // Size of the next command stream to be executed by the NPU + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR qsize_r() : word0(0) {} + CONSTEXPR qsize_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + qsize_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_QSIZE() const + { + uint32_t value = word0; + return value; + } + uint32_t get_QSIZE() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR qsize_r &set_QSIZE(uint32_t value) + { + word0 = value; + return *this; + } + volatile qsize_r &set_QSIZE(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// prot_r - Protection level configured for the NPU when acting as an AXI requester +struct prot_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t active_CPL : 1; // Current privilege level 0=User 1=Privileged + uint32_t active_CSL : 1; // Current security level 0=Secure 1=Non secure + uint32_t reserved0 : 30; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR prot_r() : word0(0) {} + CONSTEXPR prot_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + prot_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::privilege_level get_active_CPL() const + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::privilege_level get_active_CPL() const volatile + { + NPU_NAMESPACE::privilege_level value = + static_cast(((1U << 1) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + volatile prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::security_level get_active_CSL() const + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + NPU_NAMESPACE::security_level get_active_CSL() const volatile + { + NPU_NAMESPACE::security_level value = + static_cast(((1U << 1) - 1) & (word0 >> 1)); + return value; + } + CONSTEXPR prot_r &set_active_CSL(NPU_NAMESPACE::security_level value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } + volatile prot_r &set_active_CSL(NPU_NAMESPACE::security_level value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 1); + return *this; + } +#endif +}; + +// config_r - RTL configuration +struct config_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t macs_per_cc : 4; // The log2(macs/clock cycle) + uint32_t cmd_stream_version : 4; // command stream version accepted by this NPU + uint32_t shram_size : 8; // Total size in KB of internal SHRAM + uint32_t reserved0 : 10; + uint32_t functional_safety : 1; // Functional safety configuration + uint32_t custom_dma : 1; // Custom DMA configuration + uint32_t product : 4; // Product configuration + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR config_r() : word0(268435456) {} + CONSTEXPR config_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + config_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_macs_per_cc() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + uint32_t get_macs_per_cc() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR config_r &set_macs_per_cc(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + volatile config_r &set_macs_per_cc(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_cmd_stream_version() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + uint32_t get_cmd_stream_version() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR config_r &set_cmd_stream_version(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + volatile config_r &set_cmd_stream_version(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_shram_size() const + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 8); + return value; + } + uint32_t get_shram_size() const volatile + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR config_r &set_shram_size(uint32_t value) + { + word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8); + return *this; + } + volatile config_r &set_shram_size(uint32_t value) volatile + { + word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8); + return *this; + } + CONSTEXPR NPU_NAMESPACE::functional_safety get_functional_safety() const + { + NPU_NAMESPACE::functional_safety value = + static_cast(((1U << 1) - 1) & (word0 >> 26)); + return value; + } + NPU_NAMESPACE::functional_safety get_functional_safety() const volatile + { + NPU_NAMESPACE::functional_safety value = + static_cast(((1U << 1) - 1) & (word0 >> 26)); + return value; + } + CONSTEXPR config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value) + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 26); + return *this; + } + volatile config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value) volatile + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 26); + return *this; + } + CONSTEXPR NPU_NAMESPACE::custom_dma get_custom_dma() const + { + NPU_NAMESPACE::custom_dma value = static_cast(((1U << 1) - 1) & (word0 >> 27)); + return value; + } + NPU_NAMESPACE::custom_dma get_custom_dma() const volatile + { + NPU_NAMESPACE::custom_dma value = static_cast(((1U << 1) - 1) & (word0 >> 27)); + return value; + } + CONSTEXPR config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value) + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 27); + return *this; + } + volatile config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value) volatile + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast(value)) << 27); + return *this; + } + CONSTEXPR uint32_t get_product() const + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + uint32_t get_product() const volatile + { + uint32_t value = ((1U << 4) - 1) & (word0 >> 28); + return value; + } + CONSTEXPR config_r &set_product(uint32_t value) + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } + volatile config_r &set_product(uint32_t value) volatile + { + word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28); + return *this; + } +#endif +}; + +// lock_r - Lock register. This register is designed for driver use and does not affect NPU functionality +struct lock_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t LOCK : 32; // 32 bit value for LOCK configuration + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR lock_r() : word0(0) {} + CONSTEXPR lock_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + lock_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_LOCK() const + { + uint32_t value = word0; + return value; + } + uint32_t get_LOCK() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR lock_r &set_LOCK(uint32_t value) + { + word0 = value; + return *this; + } + volatile lock_r &set_LOCK(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// regioncfg_r - Region memory type configuration. Bits[2*k+1:2*k] give the memory type for REGION[k] +struct regioncfg_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t region0 : 2; // Bits for Region0 Configuration + uint32_t region1 : 2; // Bits for Region1 Configuration + uint32_t region2 : 2; // Bits for Region2 Configuration + uint32_t region3 : 2; // Bits for Region3 Configuration + uint32_t region4 : 2; // Bits for Region4 Configuration + uint32_t region5 : 2; // Bits for Region5 Configuration + uint32_t region6 : 2; // Bits for Region6 Configuration + uint32_t region7 : 2; // Bits for Region7 Configuration + uint32_t reserved0 : 16; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR regioncfg_r() : word0(0) {} + CONSTEXPR regioncfg_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + regioncfg_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region0() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::mem_attr get_region0() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region1() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 2)); + return value; + } + NPU_NAMESPACE::mem_attr get_region1() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 2)); + return value; + } + CONSTEXPR regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 2); + return *this; + } + volatile regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 2); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region2() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::mem_attr get_region2() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 4); + return *this; + } + volatile regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region3() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 6)); + return value; + } + NPU_NAMESPACE::mem_attr get_region3() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 6)); + return value; + } + CONSTEXPR regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 6); + return *this; + } + volatile regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 6); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region4() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 8)); + return value; + } + NPU_NAMESPACE::mem_attr get_region4() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 8)); + return value; + } + CONSTEXPR regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 8); + return *this; + } + volatile regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 8); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region5() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 10)); + return value; + } + NPU_NAMESPACE::mem_attr get_region5() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 10)); + return value; + } + CONSTEXPR regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 10); + return *this; + } + volatile regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 10); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region6() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 12)); + return value; + } + NPU_NAMESPACE::mem_attr get_region6() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 12)); + return value; + } + CONSTEXPR regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 12); + return *this; + } + volatile regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 12); + return *this; + } + CONSTEXPR NPU_NAMESPACE::mem_attr get_region7() const + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 14)); + return value; + } + NPU_NAMESPACE::mem_attr get_region7() const volatile + { + NPU_NAMESPACE::mem_attr value = static_cast(((1U << 2) - 1) & (word0 >> 14)); + return value; + } + CONSTEXPR regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value) + { + word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 14); + return *this; + } + volatile regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value) volatile + { + word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 14); + return *this; + } +#endif +}; + +// axi_limit0_r - AXI limits for port 0 counter 0 +struct axi_limit0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63 + uint32_t reserved2 : 2; + uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 31 + uint32_t reserved3 : 3; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit0_r() : word0(0) {} + CONSTEXPR axi_limit0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit0_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + volatile axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } + volatile axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } +#endif +}; + +// axi_limit1_r - AXI limits for port 0 counter 1 +struct axi_limit1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63 + uint32_t reserved2 : 2; + uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 31 + uint32_t reserved3 : 3; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit1_r() : word0(0) {} + CONSTEXPR axi_limit1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit1_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + volatile axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } + volatile axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } +#endif +}; + +// axi_limit2_r - AXI limits for port 1 counter 2 +struct axi_limit2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63 + uint32_t reserved2 : 2; + uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 31 + uint32_t reserved3 : 3; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit2_r() : word0(0) {} + CONSTEXPR axi_limit2_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit2_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + volatile axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } + volatile axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } +#endif +}; + +// axi_limit3_r - AXI limits for port 1 counter 3 +struct axi_limit3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t max_beats : 2; // Burst split alignment + uint32_t reserved0 : 2; + uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals + uint32_t reserved1 : 8; + uint32_t + max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63 + uint32_t reserved2 : 2; + uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range + // 0 to 31 + uint32_t reserved3 : 3; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR axi_limit3_r() : word0(0) {} + CONSTEXPR axi_limit3_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + axi_limit3_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::max_beats get_max_beats() const volatile + { + NPU_NAMESPACE::max_beats value = static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile + { + NPU_NAMESPACE::axi_mem_encoding value = + static_cast(((1U << 4) - 1) & (word0 >> 4)); + return value; + } + CONSTEXPR axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + volatile axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile + { + word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 4); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_read_m1() const + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + uint32_t get_max_outstanding_read_m1() const volatile + { + uint32_t value = ((1U << 6) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + volatile axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) volatile + { + word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_max_outstanding_write_m1() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + uint32_t get_max_outstanding_write_m1() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } + volatile axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24); + return *this; + } +#endif +}; + +// basep_r - The driver can use this address to relocate the command stream on region 0. If the region contains data +// requiring A-byte alignment then the base must be a multiple of A +struct basep_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR basep_r() : word0(0), word1(0) {} + CONSTEXPR basep_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + basep_r copy() volatile + { + return *this; + } +#endif +}; + +// wd_status_r - WD_STATUS +struct wd_status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t core_slice_state : 2; // WD core slice parser state + uint32_t core_idle : 1; // Core idle + uint32_t ctrl_state : 2; // WD control state + uint32_t ctrl_idle : 1; // All stripe jobs idle (all weights consumed) + uint32_t write_buf_index0 : 3; // current write index for next data from core + uint32_t write_buf_valid0 : 1; // write buf valid (full) + uint32_t write_buf_idle0 : 1; // write buf idle (empty) + uint32_t write_buf_index1 : 3; // current write index for next data from core + uint32_t write_buf_valid1 : 1; // write buf valid (full) + uint32_t write_buf_idle1 : 1; // write buf idle (empty) + uint32_t events : 12; // WD events mapped as appendix A + uint32_t reserved0 : 4; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR wd_status_r() : word0(0) {} + CONSTEXPR wd_status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + wd_status_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const + { + NPU_NAMESPACE::wd_core_slice_state value = + static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const volatile + { + NPU_NAMESPACE::wd_core_slice_state value = + static_cast(((1U << 2) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value) + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + volatile wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value) volatile + { + word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR uint32_t get_core_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_core_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR wd_status_r &set_core_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile wd_status_r &set_core_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const + { + NPU_NAMESPACE::wd_ctrl_state value = static_cast(((1U << 2) - 1) & (word0 >> 3)); + return value; + } + NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const volatile + { + NPU_NAMESPACE::wd_ctrl_state value = static_cast(((1U << 2) - 1) & (word0 >> 3)); + return value; + } + CONSTEXPR wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value) + { + word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 3); + return *this; + } + volatile wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value) volatile + { + word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast(value)) << 3); + return *this; + } + CONSTEXPR uint32_t get_ctrl_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_ctrl_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR wd_status_r &set_ctrl_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile wd_status_r &set_ctrl_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_write_buf_index0() const + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 6); + return value; + } + uint32_t get_write_buf_index0() const volatile + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_index0(uint32_t value) + { + word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6); + return *this; + } + volatile wd_status_r &set_write_buf_index0(uint32_t value) volatile + { + word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_write_buf_valid0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_write_buf_valid0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_valid0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile wd_status_r &set_write_buf_valid0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_write_buf_idle0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_write_buf_idle0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_idle0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile wd_status_r &set_write_buf_idle0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_write_buf_index1() const + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 11); + return value; + } + uint32_t get_write_buf_index1() const volatile + { + uint32_t value = ((1U << 3) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_index1(uint32_t value) + { + word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11); + return *this; + } + volatile wd_status_r &set_write_buf_index1(uint32_t value) volatile + { + word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_write_buf_valid1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_write_buf_valid1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_valid1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile wd_status_r &set_write_buf_valid1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_write_buf_idle1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + uint32_t get_write_buf_idle1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + CONSTEXPR wd_status_r &set_write_buf_idle1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + volatile wd_status_r &set_write_buf_idle1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = ((1U << 12) - 1) & (word0 >> 16); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = ((1U << 12) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR wd_status_r &set_events(uint32_t value) + { + word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16); + return *this; + } + volatile wd_status_r &set_events(uint32_t value) volatile + { + word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16); + return *this; + } +#endif +}; + +// mac_status_r - MAC_STATUS +struct mac_status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t block_cfg_valid : 1; // MAC has a valid block configuration + uint32_t trav_en : 1; // MAC is doing block traversal + uint32_t wait_for_ib : 1; // MAC is waiting for an Input Buffer to become available + uint32_t wait_for_acc_buf : 1; // MAC is waiting for an Accumulator Buffer to become available + uint32_t wait_for_weights : 1; // MAC is waiting for a Weight Block to become available + uint32_t stall_stripe : 1; // MAC is stalling between two stripes + uint32_t dw_sel : 1; // Currently used weight interface in MAC AI + uint32_t wait_for_dw0_ready : 1; // MAC AI is waiting for MAC DPU to send dw0_ready to WD + uint32_t wait_for_dw1_ready : 1; // MAC AI is waiting for MAC DPU to send dw1_ready to WD + uint32_t acc_buf_sel_ai : 1; // Currently used AccBuf interface in MAC AI + uint32_t wait_for_acc0_ready : 1; // MAC AI is waiting for acc0_ready from AO + uint32_t wait_for_acc1_ready : 1; // MAC AI is waiting for acc1_ready from AO + uint32_t acc_buf_sel_aa : 1; // Currently used AccBuf interface in MAC ADDER_ARRAY + uint32_t acc0_valid : 1; // MAC outgoing value of acc0_valid + uint32_t acc1_valid : 1; // MAC outgoing value of acc1_valid + uint32_t reserved0 : 1; + uint32_t events : 11; // Mapped to MAC events described in Appendix A + uint32_t reserved1 : 5; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR mac_status_r() : word0(0) {} + CONSTEXPR mac_status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + mac_status_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_block_cfg_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_block_cfg_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR mac_status_r &set_block_cfg_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile mac_status_r &set_block_cfg_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_trav_en() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_trav_en() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR mac_status_r &set_trav_en(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile mac_status_r &set_trav_en(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_wait_for_ib() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_wait_for_ib() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_ib(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile mac_status_r &set_wait_for_ib(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_wait_for_acc_buf() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_wait_for_acc_buf() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_acc_buf(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile mac_status_r &set_wait_for_acc_buf(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_wait_for_weights() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_wait_for_weights() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_weights(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile mac_status_r &set_wait_for_weights(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_stall_stripe() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_stall_stripe() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR mac_status_r &set_stall_stripe(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile mac_status_r &set_stall_stripe(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_dw_sel() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_dw_sel() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR mac_status_r &set_dw_sel(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile mac_status_r &set_dw_sel(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_wait_for_dw0_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_wait_for_dw0_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_dw0_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile mac_status_r &set_wait_for_dw0_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_wait_for_dw1_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_wait_for_dw1_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_dw1_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile mac_status_r &set_wait_for_dw1_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_acc_buf_sel_ai() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_acc_buf_sel_ai() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR mac_status_r &set_acc_buf_sel_ai(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile mac_status_r &set_acc_buf_sel_ai(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_wait_for_acc0_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_wait_for_acc0_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_acc0_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile mac_status_r &set_wait_for_acc0_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_wait_for_acc1_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + uint32_t get_wait_for_acc1_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR mac_status_r &set_wait_for_acc1_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + volatile mac_status_r &set_wait_for_acc1_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_acc_buf_sel_aa() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + uint32_t get_acc_buf_sel_aa() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR mac_status_r &set_acc_buf_sel_aa(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + volatile mac_status_r &set_acc_buf_sel_aa(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_acc0_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + uint32_t get_acc0_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + CONSTEXPR mac_status_r &set_acc0_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + volatile mac_status_r &set_acc0_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + CONSTEXPR uint32_t get_acc1_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_acc1_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR mac_status_r &set_acc1_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile mac_status_r &set_acc1_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = ((1U << 11) - 1) & (word0 >> 16); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = ((1U << 11) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR mac_status_r &set_events(uint32_t value) + { + word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16); + return *this; + } + volatile mac_status_r &set_events(uint32_t value) volatile + { + word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16); + return *this; + } +#endif +}; + +// ao_status_r - AO_STATUS +struct ao_status_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cmd_sbw_valid : 1; // Block command to shared buffer write module is valid + uint32_t cmd_act_valid : 1; // Block command to activation function module is valid + uint32_t cmd_ctl_valid : 1; // Block command to control module is valid + uint32_t cmd_scl_valid : 1; // Block command to scale module is valid + uint32_t cmd_sbr_valid : 1; // Block command to shared buffer read module is valid + uint32_t cmd_ofm_valid : 1; // Block command to ofm parameter module is valid + uint32_t blk_cmd_ready : 1; // Ready to accept block command + uint32_t blk_cmd_valid : 1; // Block command from CC is valid + uint32_t reserved0 : 8; + uint32_t events : 8; // Mapped to AO events described in Appendix A + uint32_t reserved1 : 8; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ao_status_r() : word0(0) {} + CONSTEXPR ao_status_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ao_status_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_cmd_sbw_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_cmd_sbw_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR ao_status_r &set_cmd_sbw_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile ao_status_r &set_cmd_sbw_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_cmd_act_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_cmd_act_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR ao_status_r &set_cmd_act_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile ao_status_r &set_cmd_act_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_cmd_ctl_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_cmd_ctl_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR ao_status_r &set_cmd_ctl_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile ao_status_r &set_cmd_ctl_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_cmd_scl_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_cmd_scl_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR ao_status_r &set_cmd_scl_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile ao_status_r &set_cmd_scl_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_cmd_sbr_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_cmd_sbr_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR ao_status_r &set_cmd_sbr_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile ao_status_r &set_cmd_sbr_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_cmd_ofm_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_cmd_ofm_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR ao_status_r &set_cmd_ofm_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile ao_status_r &set_cmd_ofm_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_blk_cmd_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_blk_cmd_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR ao_status_r &set_blk_cmd_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile ao_status_r &set_blk_cmd_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_blk_cmd_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_blk_cmd_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR ao_status_r &set_blk_cmd_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile ao_status_r &set_blk_cmd_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_events() const + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 16); + return value; + } + uint32_t get_events() const volatile + { + uint32_t value = ((1U << 8) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR ao_status_r &set_events(uint32_t value) + { + word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16); + return *this; + } + volatile ao_status_r &set_events(uint32_t value) volatile + { + word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16); + return *this; + } +#endif +}; + +// dma_status0_r - DMA_STATUS0 +struct dma_status0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cmd_idle : 1; // When this bit is high means that the CMD block is not busy in generating addresses + // for a CMD job + uint32_t ifm_idle : 1; // When this bit is high means that there are no ongoing IFM jobs + uint32_t wgt_idle_c0 : 1; // When this bit is high means that the WGT block is not busy in generating + // addresses for a WGT job + uint32_t bas_idle_c0 : 1; // When this bit is high means that the BAS block is not busy in generating + // addresses for a BAS job + uint32_t m2m_idle : 1; // When this bit is high means that there are no ongoing M2M jobs + uint32_t ofm_idle : 1; // When this bit is high means that there are no ongoing OFM jobs + uint32_t halt_req : 1; // CPM has requested to HALT AXI bus before soft reset + uint32_t halt_ack : 1; // DMA is in condition to halt the AXI bus since there are no pending transactions + uint32_t pause_req : 1; // CC has requested to pause the AXI + uint32_t pause_ack : 1; // DMA is in condition to pause the AXI bus since there are no pending transactions + uint32_t ib0_ai_valid_c0 : 1; // Data for AI to be read in IFM input buffer 0 - Core 0 + uint32_t ib0_ai_ready_c0 : 1; // Data consumed from AI in IFM input buffer 0 - Core 0 + uint32_t ib1_ai_valid_c0 : 1; // Data for AI to be read in IFM input buffer 1 - Core 0 + uint32_t ib1_ai_ready_c0 : 1; // Data consumed from AI in IFM input buffer 1 - Core 0 + uint32_t ib0_ao_valid_c0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 + uint32_t ib0_ao_ready_c0 : 1; // Data consumed from AO in IFM input buffer 0 - Core 0 + uint32_t ib1_ao_valid_c0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0 + uint32_t ib1_ao_ready_c0 : 1; // Data consumed from AO in IFM input buffer 1 - Core 0 + uint32_t ob0_valid_c0 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 0 + uint32_t ob0_ready_c0 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 0 + uint32_t ob1_valid_c0 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 0 + uint32_t ob1_ready_c0 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 0 + uint32_t cmd_valid : 1; // New command word for CC to be consumed + uint32_t cmd_ready : 1; // command word consumed by CC + uint32_t wd_bitstream_valid_c0 : 1; // New weight word for WD to be consumed - Core 0 + uint32_t wd_bitstream_ready_c0 : 1; // Weight word consumed by WD - Core 0 + uint32_t bs_bitstream_valid_c0 : 1; // New BaS word for AO to be consumed - Core 0 + uint32_t bs_bitstream_ready_c0 : 1; // BaS word consumed by AO - Core 0 + uint32_t axi0_ar_stalled : 1; // Read transfer request stalled on arready low AXI0 (due to memory system) + uint32_t axi0_rd_limit_stall : 1; // Read stalled due to one AXI0 limit counter being reached + uint32_t axi0_aw_stalled : 1; // Write transfer request stalled on awready low AXI0 (due to memory system) + uint32_t axi0_w_stalled : 1; // Write transfer stalled on awready low AXI0 (due to memory system) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_status0_r() : word0(0) {} + CONSTEXPR dma_status0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_status0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_cmd_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_cmd_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR dma_status0_r &set_cmd_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile dma_status0_r &set_cmd_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_ifm_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_ifm_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR dma_status0_r &set_ifm_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile dma_status0_r &set_ifm_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_wgt_idle_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_wgt_idle_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR dma_status0_r &set_wgt_idle_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile dma_status0_r &set_wgt_idle_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_bas_idle_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_bas_idle_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR dma_status0_r &set_bas_idle_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile dma_status0_r &set_bas_idle_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_m2m_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_m2m_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR dma_status0_r &set_m2m_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile dma_status0_r &set_m2m_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_ofm_idle() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_ofm_idle() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR dma_status0_r &set_ofm_idle(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile dma_status0_r &set_ofm_idle(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_halt_req() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_halt_req() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR dma_status0_r &set_halt_req(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile dma_status0_r &set_halt_req(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_halt_ack() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_halt_ack() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR dma_status0_r &set_halt_ack(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile dma_status0_r &set_halt_ack(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_pause_req() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_pause_req() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR dma_status0_r &set_pause_req(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile dma_status0_r &set_pause_req(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_pause_ack() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_pause_ack() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR dma_status0_r &set_pause_ack(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile dma_status0_r &set_pause_ack(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_ib0_ai_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ai_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile dma_status0_r &set_ib0_ai_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + uint32_t get_ib0_ai_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ai_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + volatile dma_status0_r &set_ib0_ai_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + uint32_t get_ib1_ai_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ai_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + volatile dma_status0_r &set_ib1_ai_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + uint32_t get_ib1_ai_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ai_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + volatile dma_status0_r &set_ib1_ai_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_ib0_ao_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ao_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile dma_status0_r &set_ib0_ao_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + uint32_t get_ib0_ao_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + CONSTEXPR dma_status0_r &set_ib0_ao_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + volatile dma_status0_r &set_ib0_ao_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + uint32_t get_ib1_ao_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ao_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + volatile dma_status0_r &set_ib1_ao_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + uint32_t get_ib1_ao_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + CONSTEXPR dma_status0_r &set_ib1_ao_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + volatile dma_status0_r &set_ib1_ao_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + CONSTEXPR uint32_t get_ob0_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + uint32_t get_ob0_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + CONSTEXPR dma_status0_r &set_ob0_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + volatile dma_status0_r &set_ob0_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + CONSTEXPR uint32_t get_ob0_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + uint32_t get_ob0_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + CONSTEXPR dma_status0_r &set_ob0_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + volatile dma_status0_r &set_ob0_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + CONSTEXPR uint32_t get_ob1_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + uint32_t get_ob1_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + CONSTEXPR dma_status0_r &set_ob1_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + volatile dma_status0_r &set_ob1_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + CONSTEXPR uint32_t get_ob1_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + uint32_t get_ob1_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + CONSTEXPR dma_status0_r &set_ob1_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + volatile dma_status0_r &set_ob1_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + CONSTEXPR uint32_t get_cmd_valid() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + uint32_t get_cmd_valid() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + CONSTEXPR dma_status0_r &set_cmd_valid(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + volatile dma_status0_r &set_cmd_valid(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + CONSTEXPR uint32_t get_cmd_ready() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + uint32_t get_cmd_ready() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + CONSTEXPR dma_status0_r &set_cmd_ready(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } + volatile dma_status0_r &set_cmd_ready(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 24); + return value; + } + uint32_t get_wd_bitstream_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 24); + return value; + } + CONSTEXPR dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24); + return *this; + } + volatile dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 25); + return value; + } + uint32_t get_wd_bitstream_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 25); + return value; + } + CONSTEXPR dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25); + return *this; + } + volatile dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_valid_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 26); + return value; + } + uint32_t get_bs_bitstream_valid_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 26); + return value; + } + CONSTEXPR dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26); + return *this; + } + volatile dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_ready_c0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 27); + return value; + } + uint32_t get_bs_bitstream_ready_c0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 27); + return value; + } + CONSTEXPR dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27); + return *this; + } + volatile dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27); + return *this; + } + CONSTEXPR uint32_t get_axi0_ar_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 28); + return value; + } + uint32_t get_axi0_ar_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 28); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_ar_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28); + return *this; + } + volatile dma_status0_r &set_axi0_ar_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28); + return *this; + } + CONSTEXPR uint32_t get_axi0_rd_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 29); + return value; + } + uint32_t get_axi0_rd_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 29); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_rd_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29); + return *this; + } + volatile dma_status0_r &set_axi0_rd_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29); + return *this; + } + CONSTEXPR uint32_t get_axi0_aw_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 30); + return value; + } + uint32_t get_axi0_aw_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 30); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_aw_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30); + return *this; + } + volatile dma_status0_r &set_axi0_aw_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30); + return *this; + } + CONSTEXPR uint32_t get_axi0_w_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_axi0_w_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR dma_status0_r &set_axi0_w_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile dma_status0_r &set_axi0_w_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// dma_status1_r - DMA_STATUS1 +struct dma_status1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t axi0_wr_limit_stall : 1; // Write stalled due to one AXI0 limit counter being reached + uint32_t axi1_ar_stalled : 1; // Read transfer request stalled on arready low AXI1 (due to memory system) + uint32_t axi1_rd_limit_stall : 1; // Read stalled due to one AXI1 limit counter being reached + uint32_t axi1_wr_stalled : 1; // Write transfer request stalled on awready low AXI1 (due to memory system) + uint32_t axi1_w_stalled : 1; // Write transfer stalled on wready low AXI1 (due to memory system) + uint32_t axi1_wr_limit_stall : 1; // Write stalled due to one AXI1 limit counter being reached + uint32_t wgt_idle_c1 : 1; // When this bit is high means that the WGT block is not busy in generating + // addresses for a WGT job + uint32_t bas_idle_c1 : 1; // When this bit is high means that the BAS block is not busy in generating + // addresses for a BAS job + uint32_t ib0_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 0 - Core 1 + uint32_t ib0_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 0 - Core 1 + uint32_t ib1_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 1 - Core 1 + uint32_t ib1_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 1 - Core 1 + uint32_t ib0_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 + uint32_t ib0_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 0 - Core 1 + uint32_t ib1_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1 + uint32_t ib1_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 1 - Core 1 + uint32_t ob0_valid_c1 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 1 + uint32_t ob0_ready_c1 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 1 + uint32_t ob1_valid_c1 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 1 + uint32_t ob1_ready_c1 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 1 + uint32_t wd_bitstream_valid_c1 : 1; // New weight word for WD to be consumed - Core 1 + uint32_t wd_bitstream_ready_c1 : 1; // Weight word consumed by WD - Core 1 + uint32_t bs_bitstream_valid_c1 : 1; // New BaS word for AO to be consumed - Core 1 + uint32_t bs_bitstream_ready_c1 : 1; // BaS word consumed by AO - Core 1 + uint32_t reserved0 : 8; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_status1_r() : word0(0) {} + CONSTEXPR dma_status1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_status1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_axi0_wr_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_axi0_wr_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR dma_status1_r &set_axi0_wr_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile dma_status1_r &set_axi0_wr_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_axi1_ar_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_axi1_ar_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_ar_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile dma_status1_r &set_axi1_ar_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_axi1_rd_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_axi1_rd_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_rd_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile dma_status1_r &set_axi1_rd_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_axi1_wr_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_axi1_wr_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_wr_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile dma_status1_r &set_axi1_wr_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_axi1_w_stalled() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_axi1_w_stalled() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_w_stalled(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile dma_status1_r &set_axi1_w_stalled(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_axi1_wr_limit_stall() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_axi1_wr_limit_stall() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR dma_status1_r &set_axi1_wr_limit_stall(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile dma_status1_r &set_axi1_wr_limit_stall(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + CONSTEXPR uint32_t get_wgt_idle_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + uint32_t get_wgt_idle_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 6); + return value; + } + CONSTEXPR dma_status1_r &set_wgt_idle_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + volatile dma_status1_r &set_wgt_idle_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6); + return *this; + } + CONSTEXPR uint32_t get_bas_idle_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + uint32_t get_bas_idle_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 7); + return value; + } + CONSTEXPR dma_status1_r &set_bas_idle_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + volatile dma_status1_r &set_bas_idle_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + uint32_t get_ib0_ai_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ai_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + volatile dma_status1_r &set_ib0_ai_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_ib0_ai_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + uint32_t get_ib0_ai_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 9); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ai_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + volatile dma_status1_r &set_ib0_ai_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_ib1_ai_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ai_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile dma_status1_r &set_ib1_ai_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + CONSTEXPR uint32_t get_ib1_ai_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + uint32_t get_ib1_ai_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ai_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + volatile dma_status1_r &set_ib1_ai_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + uint32_t get_ib0_ao_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 12); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ao_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + volatile dma_status1_r &set_ib0_ao_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12); + return *this; + } + CONSTEXPR uint32_t get_ib0_ao_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + uint32_t get_ib0_ao_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 13); + return value; + } + CONSTEXPR dma_status1_r &set_ib0_ao_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + volatile dma_status1_r &set_ib0_ao_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + uint32_t get_ib1_ao_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 14); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ao_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + volatile dma_status1_r &set_ib1_ao_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14); + return *this; + } + CONSTEXPR uint32_t get_ib1_ao_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + uint32_t get_ib1_ao_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 15); + return value; + } + CONSTEXPR dma_status1_r &set_ib1_ao_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + volatile dma_status1_r &set_ib1_ao_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15); + return *this; + } + CONSTEXPR uint32_t get_ob0_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + uint32_t get_ob0_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 16); + return value; + } + CONSTEXPR dma_status1_r &set_ob0_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + volatile dma_status1_r &set_ob0_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16); + return *this; + } + CONSTEXPR uint32_t get_ob0_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + uint32_t get_ob0_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 17); + return value; + } + CONSTEXPR dma_status1_r &set_ob0_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + volatile dma_status1_r &set_ob0_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17); + return *this; + } + CONSTEXPR uint32_t get_ob1_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + uint32_t get_ob1_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 18); + return value; + } + CONSTEXPR dma_status1_r &set_ob1_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + volatile dma_status1_r &set_ob1_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18); + return *this; + } + CONSTEXPR uint32_t get_ob1_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + uint32_t get_ob1_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 19); + return value; + } + CONSTEXPR dma_status1_r &set_ob1_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + volatile dma_status1_r &set_ob1_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + uint32_t get_wd_bitstream_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 20); + return value; + } + CONSTEXPR dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + volatile dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20); + return *this; + } + CONSTEXPR uint32_t get_wd_bitstream_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + uint32_t get_wd_bitstream_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 21); + return value; + } + CONSTEXPR dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + volatile dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_valid_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + uint32_t get_bs_bitstream_valid_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 22); + return value; + } + CONSTEXPR dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + volatile dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22); + return *this; + } + CONSTEXPR uint32_t get_bs_bitstream_ready_c1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + uint32_t get_bs_bitstream_ready_c1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 23); + return value; + } + CONSTEXPR dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } + volatile dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23); + return *this; + } +#endif +}; + +// clkforce_r - Force clocks on for clock gating +struct clkforce_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t top_level_clk : 1; // set to 1 to force on TOP level clock + uint32_t cc_clk : 1; // set to 1 to force on CC clock + uint32_t dma_clk : 1; // set to 1 to force on DMA clock + uint32_t mac_clk : 1; // set to 1 to force on MAC clock + uint32_t ao_clk : 1; // set to 1 to force on AO clock + uint32_t wd_clk : 1; // set to 1 to force on WD clock + uint32_t reserved0 : 26; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR clkforce_r() : word0(0) {} + CONSTEXPR clkforce_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + clkforce_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_top_level_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_top_level_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR clkforce_r &set_top_level_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile clkforce_r &set_top_level_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_cc_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_cc_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR clkforce_r &set_cc_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile clkforce_r &set_cc_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_dma_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_dma_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR clkforce_r &set_dma_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile clkforce_r &set_dma_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_mac_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_mac_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR clkforce_r &set_mac_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile clkforce_r &set_mac_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_ao_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + uint32_t get_ao_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 4); + return value; + } + CONSTEXPR clkforce_r &set_ao_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + volatile clkforce_r &set_ao_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4); + return *this; + } + CONSTEXPR uint32_t get_wd_clk() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + uint32_t get_wd_clk() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 5); + return value; + } + CONSTEXPR clkforce_r &set_wd_clk(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } + volatile clkforce_r &set_wd_clk(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5); + return *this; + } +#endif +}; + +// debug_address_r - Set debug address for register reads 0x400-0x7FF. The address must be 1KB aligned +struct debug_address_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t addr : 32; // Register address + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR debug_address_r() : word0(0) {} + CONSTEXPR debug_address_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + debug_address_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_addr() const + { + uint32_t value = word0; + return value; + } + uint32_t get_addr() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR debug_address_r &set_addr(uint32_t value) + { + word0 = value; + return *this; + } + volatile debug_address_r &set_addr(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// debug_misc_r - 32-bit read/write register for driver debug use. This does not affect NPU function +struct debug_misc_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t misc : 32; // Debug misc + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR debug_misc_r() : word0(0) {} + CONSTEXPR debug_misc_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + debug_misc_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_misc() const + { + uint32_t value = word0; + return value; + } + uint32_t get_misc() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR debug_misc_r &set_misc(uint32_t value) + { + word0 = value; + return *this; + } + volatile debug_misc_r &set_misc(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// debugcore_r - Select core number for debug registers (0x200-0x2FF) and RAM reads (0x400-0x7FF). Value is 0 or 1 +struct debugcore_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t core : 32; // Debug core + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR debugcore_r() : word0(0) {} + CONSTEXPR debugcore_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + debugcore_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_core() const + { + uint32_t value = word0; + return value; + } + uint32_t get_core() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR debugcore_r &set_core(uint32_t value) + { + word0 = value; + return *this; + } + volatile debugcore_r &set_core(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// debug_block_r - Set from which of four block banks the TSU registers are read. 0 = read from the current bank 256+n = +// force to read from bank n where n is in the range 0 to 3 +struct debug_block_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t block : 32; // Debug block + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR debug_block_r() : word0(0) {} + CONSTEXPR debug_block_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + debug_block_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_block() const + { + uint32_t value = word0; + return value; + } + uint32_t get_block() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR debug_block_r &set_block(uint32_t value) + { + word0 = value; + return *this; + } + volatile debug_block_r &set_block(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pmcr_r - PMU Register control +struct pmcr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t cnt_en : 1; // Enable counter + uint32_t event_cnt_rst : 1; // Reset event counter + uint32_t cycle_cnt_rst : 1; // Reset cycle counter + uint32_t mask_en : 1; // PMU can be enabled/disabled by command stream operation NPU_OP_PMU_MASK + uint32_t reserved0 : 7; + uint32_t num_event_cnt : 5; // Number of event counters + uint32_t reserved1 : 16; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcr_r() : word0(8192) {} + CONSTEXPR pmcr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_cnt_en() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_cnt_en() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmcr_r &set_cnt_en(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmcr_r &set_cnt_en(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_event_cnt_rst() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_event_cnt_rst() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmcr_r &set_event_cnt_rst(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmcr_r &set_event_cnt_rst(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_cycle_cnt_rst() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_cycle_cnt_rst() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmcr_r &set_cycle_cnt_rst(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmcr_r &set_cycle_cnt_rst(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_mask_en() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_mask_en() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmcr_r &set_mask_en(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmcr_r &set_mask_en(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_num_event_cnt() const + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 11); + return value; + } + uint32_t get_num_event_cnt() const volatile + { + uint32_t value = ((1U << 5) - 1) & (word0 >> 11); + return value; + } + CONSTEXPR pmcr_r &set_num_event_cnt(uint32_t value) + { + word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11); + return *this; + } + volatile pmcr_r &set_num_event_cnt(uint32_t value) volatile + { + word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11); + return *this; + } +#endif +}; + +// pmcntenset_r - Count enable set register +struct pmcntenset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0 : 1; // Event counter enable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1 : 1; // Event counter enable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2 : 1; // Event counter enable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3 : 1; // Event counter enable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT : 1; // PMCCNTR enable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcntenset_r() : word0(0) {} + CONSTEXPR pmcntenset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcntenset_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_2(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_2(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmcntenset_r &set_EVENT_CNT_3(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmcntenset_r &set_EVENT_CNT_3(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmcntenset_r &set_CYCLE_CNT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmcntenset_r &set_CYCLE_CNT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmcntenclr_r - Count enable clear register +struct pmcntenclr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0 : 1; // Event counter disable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1 : 1; // Event counter disable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2 : 1; // Event counter disable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3 : 1; // Event counter disable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT : 1; // PMCCNTR disable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcntenclr_r() : word0(0) {} + CONSTEXPR pmcntenclr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcntenclr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_0(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_0(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_1(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_1(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_2(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_2(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmcntenclr_r &set_EVENT_CNT_3(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmcntenclr_r &set_EVENT_CNT_3(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmcntenclr_r &set_CYCLE_CNT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmcntenclr_r &set_CYCLE_CNT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmovsset_r - Overflow flag status set register +struct pmovsset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow set bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow set bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow set bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow set bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow set bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmovsset_r() : word0(0) {} + CONSTEXPR pmovsset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmovsset_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmovsclr_r - Overflow flag status clear register +struct pmovsclr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow clear bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow clear bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow clear bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow clear bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow clear bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmovsclr_r() : word0(0) {} + CONSTEXPR pmovsclr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmovsclr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_OVF() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmintset_r - Interrupt enable set register +struct pmintset_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request enable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmintset_r() : word0(0) {} + CONSTEXPR pmintset_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmintset_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_0_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_0_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_1_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_1_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_2_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_2_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmintset_r &set_EVENT_CNT_3_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmintset_r &set_EVENT_CNT_3_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmintset_r &set_CYCLE_CNT_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmintset_r &set_CYCLE_CNT_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmintclr_r - Interrupt enable clear register +struct pmintclr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR0 + uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR1 + uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR2 + uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR3 + uint32_t reserved0 : 27; + uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request disable bit + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmintclr_r() : word0(0) {} + CONSTEXPR pmintclr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmintclr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + uint32_t get_EVENT_CNT_0_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 0); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + uint32_t get_EVENT_CNT_1_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 1); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + uint32_t get_EVENT_CNT_2_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 2); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2); + return *this; + } + CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + uint32_t get_EVENT_CNT_3_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 3); + return value; + } + CONSTEXPR pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + volatile pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3); + return *this; + } + CONSTEXPR uint32_t get_CYCLE_CNT_INT() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + uint32_t get_CYCLE_CNT_INT() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 31); + return value; + } + CONSTEXPR pmintclr_r &set_CYCLE_CNT_INT(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } + volatile pmintclr_r &set_CYCLE_CNT_INT(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31); + return *this; + } +#endif +}; + +// pmccntr_r - Performance monitor cycle count register +struct pmccntr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CYCLE_CNT_LO : 32; // Cycle count - LSB + uint32_t CYCLE_CNT_HI : 16; // Cycle count - MSB + uint32_t reserved0 : 16; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR pmccntr_r() : word0(0), word1(0) {} + CONSTEXPR pmccntr_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + pmccntr_r copy() volatile + { + return *this; + } +#endif +}; + +// pmccntr_cfg_r - Set start/stop event on the cycle counter +struct pmccntr_cfg_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CYCLE_CNT_CFG_START : 10; // Cycle counter start event + uint32_t reserved0 : 6; + uint32_t CYCLE_CNT_CFG_STOP : 10; // Cycle counter stop event + uint32_t reserved1 : 6; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmccntr_cfg_r() : word0(0) {} + CONSTEXPR pmccntr_cfg_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmccntr_cfg_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const volatile + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value) + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } + volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value) volatile + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 16)); + return value; + } + NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const volatile + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 16)); + return value; + } + CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value) + { + word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 16); + return *this; + } + volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value) volatile + { + word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 16); + return *this; + } +#endif +}; + +// pmcaxi_chan_r - Set which AXI channel to monitor for latency measurements in PMU +struct pmcaxi_chan_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CH_SEL : 4; // Channel select for latency measurements + uint32_t reserved0 : 4; + uint32_t AXI_CNT_SEL : 2; // AXI counter to monitor for latency measurements + uint32_t BW_CH_SEL_EN : 1; // Bandwidth channel selector + uint32_t reserved1 : 21; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmcaxi_chan_r() : word0(0) {} + CONSTEXPR pmcaxi_chan_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmcaxi_chan_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const + { + NPU_NAMESPACE::pmu_axi_channel value = + static_cast(((1U << 4) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const volatile + { + NPU_NAMESPACE::pmu_axi_channel value = + static_cast(((1U << 4) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value) + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 0); + return *this; + } + volatile pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value) volatile + { + word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast(value)) << 0); + return *this; + } + CONSTEXPR uint32_t get_AXI_CNT_SEL() const + { + uint32_t value = ((1U << 2) - 1) & (word0 >> 8); + return value; + } + uint32_t get_AXI_CNT_SEL() const volatile + { + uint32_t value = ((1U << 2) - 1) & (word0 >> 8); + return value; + } + CONSTEXPR pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value) + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8); + return *this; + } + volatile pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value) volatile + { + word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8); + return *this; + } + CONSTEXPR uint32_t get_BW_CH_SEL_EN() const + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + uint32_t get_BW_CH_SEL_EN() const volatile + { + uint32_t value = ((1U << 1) - 1) & (word0 >> 10); + return value; + } + CONSTEXPR pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value) + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } + volatile pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value) volatile + { + word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10); + return *this; + } +#endif +}; + +// kernel_x_r - Kernel X offset of in kernel decomposition +struct kernel_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_x_r() : word0(0) {} + CONSTEXPR kernel_x_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_x_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_x_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_x_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_y_r - Kernel Y offset of in kernel decomposition +struct kernel_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_y_r() : word0(0) {} + CONSTEXPR kernel_y_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_y_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_y_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_y_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_w_m1_r - Kernel (width-1) of current block +struct kernel_w_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_w_m1_r() : word0(0) {} + CONSTEXPR kernel_w_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_w_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_w_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_w_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_h_m1_r - Kernel (height-1) of current block +struct kernel_h_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_h_m1_r() : word0(0) {} + CONSTEXPR kernel_h_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_h_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_h_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_h_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_cblk_width_m1_r - OFM current block (width-1) +struct ofm_cblk_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_cblk_width_m1_r() : word0(0) {} + CONSTEXPR ofm_cblk_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_cblk_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_cblk_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_cblk_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_cblk_height_m1_r - OFM current block (height-1) +struct ofm_cblk_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_cblk_height_m1_r() : word0(0) {} + CONSTEXPR ofm_cblk_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_cblk_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_cblk_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_cblk_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_cblk_depth_m1_r - OFM current block (depth-1) +struct ofm_cblk_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_cblk_depth_m1_r() : word0(0) {} + CONSTEXPR ofm_cblk_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_cblk_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_cblk_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_cblk_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_cblk_depth_m1_r - IFM current block (depth-1) +struct ifm_cblk_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_cblk_depth_m1_r() : word0(0) {} + CONSTEXPR ifm_cblk_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_cblk_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_cblk_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_cblk_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_x_r - Block X coordinate in OFM +struct ofm_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_x_r() : word0(0) {} + CONSTEXPR ofm_x_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_x_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_x_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_x_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_y_r - Block Y coordinate in OFM +struct ofm_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_y_r() : word0(0) {} + CONSTEXPR ofm_y_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_y_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_y_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_y_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_z_r - Block Z (channel) coordinate in OFM +struct ofm_z_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_z_r() : word0(0) {} + CONSTEXPR ofm_z_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_z_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_z_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_z_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_z_r - Block Z (channel) coordinate in IFM +struct ifm_z_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_z_r() : word0(0) {} + CONSTEXPR ifm_z_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_z_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_z_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_z_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pad_top_r - Block top pad +struct pad_top_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pad_top_r() : word0(0) {} + CONSTEXPR pad_top_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pad_top_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pad_top_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile pad_top_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pad_left_r - Block left pad +struct pad_left_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pad_left_r() : word0(0) {} + CONSTEXPR pad_left_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pad_left_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pad_left_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile pad_left_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_cblk_width_r - IFM current block derived width +struct ifm_cblk_width_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_cblk_width_r() : word0(0) {} + CONSTEXPR ifm_cblk_width_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_cblk_width_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_cblk_width_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_cblk_width_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_cblk_height_r - IFM current block derived height +struct ifm_cblk_height_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_cblk_height_r() : word0(0) {} + CONSTEXPR ifm_cblk_height_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_cblk_height_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_cblk_height_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_cblk_height_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_ifm_src_r - DMA IFM channel source position on AXI +struct dma_ifm_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_ifm_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_ifm_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_ifm_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_ifm_dst_r - DMA IFM channel destination position in SHRAM +struct dma_ifm_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_ifm_dst_r() : word0(0) {} + CONSTEXPR dma_ifm_dst_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_ifm_dst_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma_ifm_dst_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma_ifm_dst_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_ofm_src_r - DMA OFM channel source position in SHRAM +struct dma_ofm_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_ofm_src_r() : word0(0) {} + CONSTEXPR dma_ofm_src_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_ofm_src_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma_ofm_src_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma_ofm_src_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_ofm_dst_r - DMA OFM channel destination position on AXI +struct dma_ofm_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_ofm_dst_r() : word0(0), word1(0) {} + CONSTEXPR dma_ofm_dst_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_ofm_dst_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_weight_src_r - DMA weight channel source position on AXI +struct dma_weight_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_weight_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_weight_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_weight_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_cmd_src_r - DMA command channel source position on AXI +struct dma_cmd_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_cmd_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_cmd_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_cmd_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_cmd_size_r - DMA command channel number of bytes buffered +struct dma_cmd_size_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma_cmd_size_r() : word0(0) {} + CONSTEXPR dma_cmd_size_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma_cmd_size_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma_cmd_size_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma_cmd_size_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_m2m_src_r - DMA memory to memory source position on AXI +struct dma_m2m_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_m2m_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_m2m_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_m2m_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma_m2m_dst_r - DMA memory to memory destination position on AXI +struct dma_m2m_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_m2m_dst_r() : word0(0), word1(0) {} + CONSTEXPR dma_m2m_dst_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_m2m_dst_r copy() volatile + { + return *this; + } +#endif +}; + +// current_qread_r - QREAD position being issued (rather than completed) +struct current_qread_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_qread_r() : word0(0) {} + CONSTEXPR current_qread_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_qread_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_qread_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_qread_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma_scale_src_r - DMA scale and bias channel source position on AXI +struct dma_scale_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t offset_LO : 32; // Offset - LSB + uint32_t offset_HI : 8; // Offset - MSB + uint32_t reserved0 : 24; + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma_scale_src_r() : word0(0), word1(0) {} + CONSTEXPR dma_scale_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma_scale_src_r copy() volatile + { + return *this; + } +#endif +}; + +// current_block_r - 0-3. Current block bank being executed by the TSU or last one executed if TSU is stopped +struct current_block_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_block_r() : word0(0) {} + CONSTEXPR current_block_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_block_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_block_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_block_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// current_op_r - Current NPU OP command being executed by the TSU +struct current_op_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_op_r() : word0(0) {} + CONSTEXPR current_op_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_op_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_op_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_op_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// current_cmd_r - Current 32-bit command being parsed by the command stream parser +struct current_cmd_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR current_cmd_r() : word0(0) {} + CONSTEXPR current_cmd_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + current_cmd_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR current_cmd_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile current_cmd_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pmevcntr_r - Performance monitor event 0 count register +struct pmevcntr_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t count : 32; // Count word + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmevcntr_r() : word0(0) {} + CONSTEXPR pmevcntr_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmevcntr_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_count() const + { + uint32_t value = word0; + return value; + } + uint32_t get_count() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pmevcntr_r &set_count(uint32_t value) + { + word0 = value; + return *this; + } + volatile pmevcntr_r &set_count(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pmevtyper_r - Performance monitor event type register 0 +struct pmevtyper_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t EV_TYPE : 10; // Event Type + uint32_t reserved0 : 22; + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pmevtyper_r() : word0(0) {} + CONSTEXPR pmevtyper_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pmevtyper_r copy() volatile + { + return *this; + } + CONSTEXPR NPU_NAMESPACE::pmu_event get_EV_TYPE() const + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + NPU_NAMESPACE::pmu_event get_EV_TYPE() const volatile + { + NPU_NAMESPACE::pmu_event value = static_cast(((1U << 10) - 1) & (word0 >> 0)); + return value; + } + CONSTEXPR pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value) + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } + volatile pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value) volatile + { + word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast(value)) << 0); + return *this; + } +#endif +}; + +// shared_buffer_r - Shared buffer debug access. Only valid in STOPPED state +struct shared_buffer_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t mem_word : 32; // Memory word + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR shared_buffer_r() : word0(0) {} + CONSTEXPR shared_buffer_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + shared_buffer_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_mem_word() const + { + uint32_t value = word0; + return value; + } + uint32_t get_mem_word() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR shared_buffer_r &set_mem_word(uint32_t value) + { + word0 = value; + return *this; + } + volatile shared_buffer_r &set_mem_word(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_top_r - None +struct ifm_pad_top_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_top_r() : word0(0) {} + CONSTEXPR ifm_pad_top_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_top_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_top_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_top_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_left_r - None +struct ifm_pad_left_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_left_r() : word0(0) {} + CONSTEXPR ifm_pad_left_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_left_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_left_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_left_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_right_r - None +struct ifm_pad_right_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_right_r() : word0(0) {} + CONSTEXPR ifm_pad_right_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_right_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_right_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_right_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_pad_bottom_r - None +struct ifm_pad_bottom_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_pad_bottom_r() : word0(0) {} + CONSTEXPR ifm_pad_bottom_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_pad_bottom_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_pad_bottom_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_pad_bottom_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_depth_m1_r - None +struct ifm_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_depth_m1_r() : word0(0) {} + CONSTEXPR ifm_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_precision_r - None +struct ifm_precision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_precision_r() : word0(0) {} + CONSTEXPR ifm_precision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_precision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_precision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_precision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_upscale_r - None +struct ifm_upscale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_upscale_r() : word0(0) {} + CONSTEXPR ifm_upscale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_upscale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_upscale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_upscale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_zero_point_r - None +struct ifm_zero_point_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_zero_point_r() : word0(0) {} + CONSTEXPR ifm_zero_point_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_zero_point_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_zero_point_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_zero_point_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_width0_m1_r - None +struct ifm_width0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_width0_m1_r() : word0(0) {} + CONSTEXPR ifm_width0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_width0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_width0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_width0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_height0_m1_r - None +struct ifm_height0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_height0_m1_r() : word0(0) {} + CONSTEXPR ifm_height0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_height0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_height0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_height0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_height1_m1_r - None +struct ifm_height1_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_height1_m1_r() : word0(0) {} + CONSTEXPR ifm_height1_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_height1_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_height1_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_height1_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_ib_end_r - None +struct ifm_ib_end_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_ib_end_r() : word0(0) {} + CONSTEXPR ifm_ib_end_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_ib_end_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_ib_end_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_ib_end_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_region_r - None +struct ifm_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm_region_r() : word0(0) {} + CONSTEXPR ifm_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_width_m1_r - None +struct ofm_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_width_m1_r() : word0(0) {} + CONSTEXPR ofm_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_height_m1_r - None +struct ofm_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_height_m1_r() : word0(0) {} + CONSTEXPR ofm_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_depth_m1_r - None +struct ofm_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_depth_m1_r() : word0(0) {} + CONSTEXPR ofm_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_precision_r - None +struct ofm_precision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_precision_r() : word0(0) {} + CONSTEXPR ofm_precision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_precision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_precision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_precision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_blk_width_m1_r - None +struct ofm_blk_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_blk_width_m1_r() : word0(0) {} + CONSTEXPR ofm_blk_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_blk_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_blk_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_blk_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_blk_height_m1_r - None +struct ofm_blk_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_blk_height_m1_r() : word0(0) {} + CONSTEXPR ofm_blk_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_blk_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_blk_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_blk_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_blk_depth_m1_r - None +struct ofm_blk_depth_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_blk_depth_m1_r() : word0(0) {} + CONSTEXPR ofm_blk_depth_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_blk_depth_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_blk_depth_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_blk_depth_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_zero_point_r - None +struct ofm_zero_point_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_zero_point_r() : word0(0) {} + CONSTEXPR ofm_zero_point_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_zero_point_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_zero_point_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_zero_point_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_width0_m1_r - None +struct ofm_width0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_width0_m1_r() : word0(0) {} + CONSTEXPR ofm_width0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_width0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_width0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_width0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_height0_m1_r - None +struct ofm_height0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_height0_m1_r() : word0(0) {} + CONSTEXPR ofm_height0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_height0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_height0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_height0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_height1_m1_r - None +struct ofm_height1_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_height1_m1_r() : word0(0) {} + CONSTEXPR ofm_height1_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_height1_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_height1_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_height1_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_region_r - None +struct ofm_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_region_r() : word0(0) {} + CONSTEXPR ofm_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_width_m1_r - None +struct kernel_width_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_width_m1_r() : word0(0) {} + CONSTEXPR kernel_width_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_width_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_width_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_width_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_height_m1_r - None +struct kernel_height_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_height_m1_r() : word0(0) {} + CONSTEXPR kernel_height_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_height_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_height_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_height_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// kernel_stride_r - None +struct kernel_stride_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR kernel_stride_r() : word0(0) {} + CONSTEXPR kernel_stride_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + kernel_stride_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR kernel_stride_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile kernel_stride_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// parallel_mode_r - None +struct parallel_mode_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR parallel_mode_r() : word0(0) {} + CONSTEXPR parallel_mode_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + parallel_mode_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR parallel_mode_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile parallel_mode_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// acc_format_r - None +struct acc_format_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR acc_format_r() : word0(0) {} + CONSTEXPR acc_format_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + acc_format_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR acc_format_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile acc_format_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// activation_r - None +struct activation_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR activation_r() : word0(0) {} + CONSTEXPR activation_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + activation_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR activation_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile activation_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// activation_min_r - None +struct activation_min_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR activation_min_r() : word0(0) {} + CONSTEXPR activation_min_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + activation_min_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR activation_min_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile activation_min_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// activation_max_r - None +struct activation_max_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR activation_max_r() : word0(0) {} + CONSTEXPR activation_max_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + activation_max_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR activation_max_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile activation_max_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// weight_region_r - None +struct weight_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR weight_region_r() : word0(0) {} + CONSTEXPR weight_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + weight_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR weight_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile weight_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// scale_region_r - None +struct scale_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR scale_region_r() : word0(0) {} + CONSTEXPR scale_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + scale_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR scale_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile scale_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ab_start_r - None +struct ab_start_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ab_start_r() : word0(0) {} + CONSTEXPR ab_start_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ab_start_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ab_start_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ab_start_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// blockdep_r - None +struct blockdep_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR blockdep_r() : word0(0) {} + CONSTEXPR blockdep_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + blockdep_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR blockdep_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile blockdep_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_src_region_r - None +struct dma0_src_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_src_region_r() : word0(0) {} + CONSTEXPR dma0_src_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_src_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_src_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_src_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_dst_region_r - None +struct dma0_dst_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_dst_region_r() : word0(0) {} + CONSTEXPR dma0_dst_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_dst_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_dst_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_dst_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_size0_r - None +struct dma0_size0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_size0_r() : word0(0) {} + CONSTEXPR dma0_size0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_size0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_size0_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_size0_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_size1_r - None +struct dma0_size1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR dma0_size1_r() : word0(0) {} + CONSTEXPR dma0_size1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + dma0_size1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR dma0_size1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile dma0_size1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_broadcast_r - None +struct ifm2_broadcast_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_broadcast_r() : word0(0) {} + CONSTEXPR ifm2_broadcast_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_broadcast_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_broadcast_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_broadcast_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_scalar_r - None +struct ifm2_scalar_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_scalar_r() : word0(0) {} + CONSTEXPR ifm2_scalar_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_scalar_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_scalar_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_scalar_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_precision_r - None +struct ifm2_precision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_precision_r() : word0(0) {} + CONSTEXPR ifm2_precision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_precision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_precision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_precision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_zero_point_r - None +struct ifm2_zero_point_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_zero_point_r() : word0(0) {} + CONSTEXPR ifm2_zero_point_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_zero_point_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_zero_point_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_zero_point_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_width0_m1_r - None +struct ifm2_width0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_width0_m1_r() : word0(0) {} + CONSTEXPR ifm2_width0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_width0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_width0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_width0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_height0_m1_r - None +struct ifm2_height0_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_height0_m1_r() : word0(0) {} + CONSTEXPR ifm2_height0_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_height0_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_height0_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_height0_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_height1_m1_r - None +struct ifm2_height1_m1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_height1_m1_r() : word0(0) {} + CONSTEXPR ifm2_height1_m1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_height1_m1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_height1_m1_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_height1_m1_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_ib_start_r - None +struct ifm2_ib_start_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_ib_start_r() : word0(0) {} + CONSTEXPR ifm2_ib_start_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_ib_start_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_ib_start_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_ib_start_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm2_region_r - None +struct ifm2_region_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ifm2_region_r() : word0(0) {} + CONSTEXPR ifm2_region_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ifm2_region_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ifm2_region_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ifm2_region_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ifm_base0_r - None +struct ifm_base0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base0_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base0_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base0_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_base1_r - None +struct ifm_base1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base1_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base1_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base1_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_base2_r - None +struct ifm_base2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base2_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base2_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base2_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_base3_r - None +struct ifm_base3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_base3_r() : word0(0), word1(0) {} + CONSTEXPR ifm_base3_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_base3_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_stride_x_r - None +struct ifm_stride_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_stride_x_r() : word0(0), word1(0) {} + CONSTEXPR ifm_stride_x_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_stride_x_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_stride_y_r - None +struct ifm_stride_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_stride_y_r() : word0(0), word1(0) {} + CONSTEXPR ifm_stride_y_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_stride_y_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm_stride_c_r - None +struct ifm_stride_c_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm_stride_c_r() : word0(0), word1(0) {} + CONSTEXPR ifm_stride_c_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm_stride_c_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base0_r - None +struct ofm_base0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base0_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base0_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base0_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base1_r - None +struct ofm_base1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base1_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base1_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base1_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base2_r - None +struct ofm_base2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base2_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base2_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base2_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_base3_r - None +struct ofm_base3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_base3_r() : word0(0), word1(0) {} + CONSTEXPR ofm_base3_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_base3_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_stride_x_r - None +struct ofm_stride_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_stride_x_r() : word0(0), word1(0) {} + CONSTEXPR ofm_stride_x_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_stride_x_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_stride_y_r - None +struct ofm_stride_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_stride_y_r() : word0(0), word1(0) {} + CONSTEXPR ofm_stride_y_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_stride_y_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_stride_c_r - None +struct ofm_stride_c_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ofm_stride_c_r() : word0(0), word1(0) {} + CONSTEXPR ofm_stride_c_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ofm_stride_c_r copy() volatile + { + return *this; + } +#endif +}; + +// weight_base_r - None +struct weight_base_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR weight_base_r() : word0(0), word1(0) {} + CONSTEXPR weight_base_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + weight_base_r copy() volatile + { + return *this; + } +#endif +}; + +// weight_length_r - None +struct weight_length_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR weight_length_r() : word0(0), word1(0) {} + CONSTEXPR weight_length_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + weight_length_r copy() volatile + { + return *this; + } +#endif +}; + +// scale_base_r - None +struct scale_base_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR scale_base_r() : word0(0), word1(0) {} + CONSTEXPR scale_base_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + scale_base_r copy() volatile + { + return *this; + } +#endif +}; + +// scale_length_r - None +struct scale_length_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR scale_length_r() : word0(0), word1(0) {} + CONSTEXPR scale_length_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + scale_length_r copy() volatile + { + return *this; + } +#endif +}; + +// ofm_scale_r - None +struct ofm_scale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_scale_r() : word0(0) {} + CONSTEXPR ofm_scale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_scale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_scale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_scale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// ofm_scale_shift_r - None +struct ofm_scale_shift_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR ofm_scale_shift_r() : word0(0) {} + CONSTEXPR ofm_scale_shift_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + ofm_scale_shift_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR ofm_scale_shift_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile ofm_scale_shift_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// opa_scale_r - None +struct opa_scale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR opa_scale_r() : word0(0) {} + CONSTEXPR opa_scale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + opa_scale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR opa_scale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile opa_scale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// opa_scale_shift_r - None +struct opa_scale_shift_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR opa_scale_shift_r() : word0(0) {} + CONSTEXPR opa_scale_shift_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + opa_scale_shift_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR opa_scale_shift_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile opa_scale_shift_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// opb_scale_r - None +struct opb_scale_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR opb_scale_r() : word0(0) {} + CONSTEXPR opb_scale_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + opb_scale_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR opb_scale_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile opb_scale_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// dma0_src_r - None +struct dma0_src_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_src_r() : word0(0), word1(0) {} + CONSTEXPR dma0_src_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_src_r copy() volatile + { + return *this; + } +#endif +}; + +// dma0_dst_r - None +struct dma0_dst_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_dst_r() : word0(0), word1(0) {} + CONSTEXPR dma0_dst_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_dst_r copy() volatile + { + return *this; + } +#endif +}; + +// dma0_len_r - None +struct dma0_len_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_len_r() : word0(0), word1(0) {} + CONSTEXPR dma0_len_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_len_r copy() volatile + { + return *this; + } +#endif +}; + +// dma0_skip0_r - None +struct dma0_skip0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_skip0_r() : word0(0), word1(0) {} + CONSTEXPR dma0_skip0_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_skip0_r copy() volatile + { + return *this; + } +#endif +}; + +// dma0_skip1_r - None +struct dma0_skip1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR dma0_skip1_r() : word0(0), word1(0) {} + CONSTEXPR dma0_skip1_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + dma0_skip1_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base0_r - None +struct ifm2_base0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base0_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base0_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base0_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base1_r - None +struct ifm2_base1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base1_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base1_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base1_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base2_r - None +struct ifm2_base2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base2_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base2_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base2_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_base3_r - None +struct ifm2_base3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_base3_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_base3_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_base3_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_stride_x_r - None +struct ifm2_stride_x_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_stride_x_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_stride_x_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_stride_x_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_stride_y_r - None +struct ifm2_stride_y_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_stride_y_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_stride_y_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_stride_y_r copy() volatile + { + return *this; + } +#endif +}; + +// ifm2_stride_c_r - None +struct ifm2_stride_c_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR ifm2_stride_c_r() : word0(0), word1(0) {} + CONSTEXPR ifm2_stride_c_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + ifm2_stride_c_r copy() volatile + { + return *this; + } +#endif +}; + +// weight1_base_r - None +struct weight1_base_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR weight1_base_r() : word0(0), word1(0) {} + CONSTEXPR weight1_base_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + weight1_base_r copy() volatile + { + return *this; + } +#endif +}; + +// weight1_length_r - None +struct weight1_length_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR weight1_length_r() : word0(0), word1(0) {} + CONSTEXPR weight1_length_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + weight1_length_r copy() volatile + { + return *this; + } +#endif +}; + +// scale1_base_r - None +struct scale1_base_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR scale1_base_r() : word0(0), word1(0) {} + CONSTEXPR scale1_base_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + scale1_base_r copy() volatile + { + return *this; + } +#endif +}; + +// scale1_length_r - None +struct scale1_length_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value_LO : 32; // 64-bit register value - LSB + uint32_t value_HI : 32; // 64-bit register value - MSB + }; + uint32_t word[2]; + }; +#else + private: + uint32_t word0; + uint32_t word1; + + public: + CONSTEXPR scale1_length_r() : word0(0), word1(0) {} + CONSTEXPR scale1_length_r(uint64_t init) : + word0(static_cast((init)&std::numeric_limits::max())), + word1(static_cast((init >> 32) & std::numeric_limits::max())) + { + } + CONSTEXPR void operator=(uint64_t value) + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + void operator=(uint64_t value) volatile + { + word0 = static_cast((value)&std::numeric_limits::max()); + word1 = static_cast((value >> 32) & std::numeric_limits::max()); + } + CONSTEXPR operator uint64_t() + { + return (static_cast(word1) << 32) | word0; + } + operator uint64_t() volatile + { + return (static_cast(word1) << 32) | word0; + } + scale1_length_r copy() volatile + { + return *this; + } +#endif +}; + +// revision_r - Internal FPGA build revision: first 32-bits of the Ultan Git hash used for the build +struct revision_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t value : 32; // 32-bit register value + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR revision_r() : word0(0) {} + CONSTEXPR revision_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + revision_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_value() const + { + uint32_t value = word0; + return value; + } + uint32_t get_value() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR revision_r &set_value(uint32_t value) + { + word0 = value; + return *this; + } + volatile revision_r &set_value(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid4_r - Peripheral ID byte 4 (Arm=code 4) +struct pid4_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID4 : 32; // Byte 4 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid4_r() : word0(4) {} + CONSTEXPR pid4_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid4_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID4() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID4() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid4_r &set_PID4(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid4_r &set_PID4(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid5_r - Peripheral ID byte 5 (reserved) +struct pid5_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID5 : 32; // Byte 5 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid5_r() : word0(0) {} + CONSTEXPR pid5_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid5_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID5() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID5() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid5_r &set_PID5(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid5_r &set_PID5(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid6_r - Peripheral ID byte 6 (reserved) +struct pid6_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID6 : 32; // Byte 6 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid6_r() : word0(0) {} + CONSTEXPR pid6_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid6_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID6() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID6() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid6_r &set_PID6(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid6_r &set_PID6(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid7_r - Peripheral ID byte 7 (reserved) +struct pid7_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID7 : 32; // Byte 7 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid7_r() : word0(0) {} + CONSTEXPR pid7_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid7_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID7() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID7() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid7_r &set_PID7(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid7_r &set_PID7(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid0_r - Peripheral ID byte 0. This is bits[7:0] of the part number +struct pid0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID0 : 32; // Byte 0 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid0_r() : word0(129) {} + CONSTEXPR pid0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID0() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID0() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid0_r &set_PID0(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid0_r &set_PID0(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid1_r - Peripheral ID byte 1. This is bits[11:8] of the part number in bits[3:0], and bits[3:0] of the Arm ID in +// bits[7:4] +struct pid1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID1 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid1_r() : word0(181) {} + CONSTEXPR pid1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID1() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID1() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid1_r &set_PID1(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid1_r &set_PID1(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid2_r - Peripheral ID byte 2. This is bits[6:4] of the Arm ID in bits[2:0], and bit 3 indicates format B +struct pid2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID2 : 32; // Byte 2 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid2_r() : word0(11) {} + CONSTEXPR pid2_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid2_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID2() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID2() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid2_r &set_PID2(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid2_r &set_PID2(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// pid3_r - Peripheral ID byte 3 +struct pid3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t PID3 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR pid3_r() : word0(0) {} + CONSTEXPR pid3_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + pid3_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_PID3() const + { + uint32_t value = word0; + return value; + } + uint32_t get_PID3() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR pid3_r &set_PID3(uint32_t value) + { + word0 = value; + return *this; + } + volatile pid3_r &set_PID3(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid0_r - Component ID byte 0 +struct cid0_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID0 : 32; // Byte 0 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid0_r() : word0(13) {} + CONSTEXPR cid0_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid0_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID0() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID0() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid0_r &set_CID0(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid0_r &set_CID0(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid1_r - Component ID byte 1 +struct cid1_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID1 : 32; // Byte 1 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid1_r() : word0(240) {} + CONSTEXPR cid1_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid1_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID1() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID1() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid1_r &set_CID1(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid1_r &set_CID1(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid2_r - Component ID byte 2 +struct cid2_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID2 : 32; // Byte 2 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid2_r() : word0(5) {} + CONSTEXPR cid2_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid2_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID2() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID2() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid2_r &set_CID2(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid2_r &set_CID2(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +// cid3_r - Component ID byte 3 +struct cid3_r +{ +#ifndef __cplusplus + union + { + struct + { + uint32_t CID3 : 32; // Byte 3 of Component ID (Lower 8 bits valid) + }; + uint32_t word; + }; +#else + private: + uint32_t word0; + + public: + CONSTEXPR cid3_r() : word0(177) {} + CONSTEXPR cid3_r(uint32_t init) : word0(init) {} + CONSTEXPR void operator=(uint32_t value) + { + word0 = value; + } + void operator=(uint32_t value) volatile + { + word0 = value; + } + CONSTEXPR operator uint32_t() + { + return word0; + } + operator uint32_t() volatile + { + return word0; + } + cid3_r copy() volatile + { + return *this; + } + CONSTEXPR uint32_t get_CID3() const + { + uint32_t value = word0; + return value; + } + uint32_t get_CID3() const volatile + { + uint32_t value = word0; + return value; + } + CONSTEXPR cid3_r &set_CID3(uint32_t value) + { + word0 = value; + return *this; + } + volatile cid3_r &set_CID3(uint32_t value) volatile + { + word0 = value; + return *this; + } +#endif +}; + +struct NPU_REG +{ + STRUCT id_r ID; // 0x0000 + STRUCT status_r STATUS; // 0x0004 + STRUCT cmd_r CMD; // 0x0008 + STRUCT reset_r RESET; // 0x000C + STRUCT qbase_r QBASE; // 0x0010 + STRUCT qread_r QREAD; // 0x0018 + STRUCT qconfig_r QCONFIG; // 0x001C + STRUCT qsize_r QSIZE; // 0x0020 + STRUCT prot_r PROT; // 0x0024 + STRUCT config_r CONFIG; // 0x0028 + STRUCT lock_r LOCK; // 0x002C + uint32_t unused0[3]; + STRUCT regioncfg_r REGIONCFG; // 0x003C + STRUCT axi_limit0_r AXI_LIMIT0; // 0x0040 + STRUCT axi_limit1_r AXI_LIMIT1; // 0x0044 + STRUCT axi_limit2_r AXI_LIMIT2; // 0x0048 + STRUCT axi_limit3_r AXI_LIMIT3; // 0x004C + uint32_t unused1[12]; + STRUCT basep_r BASEP[8]; // 0x0080 + uint32_t unused2[16]; + STRUCT wd_status_r WD_STATUS; // 0x0100 + STRUCT mac_status_r MAC_STATUS; // 0x0104 + STRUCT ao_status_r AO_STATUS; // 0x0108 + uint32_t unused3[1]; + STRUCT dma_status0_r DMA_STATUS0; // 0x0110 + STRUCT dma_status1_r DMA_STATUS1; // 0x0114 + uint32_t unused4[10]; + STRUCT clkforce_r CLKFORCE; // 0x0140 + STRUCT debug_address_r DEBUG_ADDRESS; // 0x0144 + STRUCT debug_misc_r DEBUG_MISC; // 0x0148 + STRUCT debugcore_r DEBUGCORE; // 0x014C + STRUCT debug_block_r DEBUG_BLOCK; // 0x0150 + uint32_t unused5[11]; + STRUCT pmcr_r PMCR; // 0x0180 + STRUCT pmcntenset_r PMCNTENSET; // 0x0184 + STRUCT pmcntenclr_r PMCNTENCLR; // 0x0188 + STRUCT pmovsset_r PMOVSSET; // 0x018C + STRUCT pmovsclr_r PMOVSCLR; // 0x0190 + STRUCT pmintset_r PMINTSET; // 0x0194 + STRUCT pmintclr_r PMINTCLR; // 0x0198 + uint32_t unused6[1]; + STRUCT pmccntr_r PMCCNTR; // 0x01A0 + STRUCT pmccntr_cfg_r PMCCNTR_CFG; // 0x01A8 + STRUCT pmcaxi_chan_r PMCAXI_CHAN; // 0x01AC + uint32_t unused7[20]; + STRUCT kernel_x_r KERNEL_X; // 0x0200 + STRUCT kernel_y_r KERNEL_Y; // 0x0204 + STRUCT kernel_w_m1_r KERNEL_W_M1; // 0x0208 + STRUCT kernel_h_m1_r KERNEL_H_M1; // 0x020C + STRUCT ofm_cblk_width_m1_r OFM_CBLK_WIDTH_M1; // 0x0210 + STRUCT ofm_cblk_height_m1_r OFM_CBLK_HEIGHT_M1; // 0x0214 + STRUCT ofm_cblk_depth_m1_r OFM_CBLK_DEPTH_M1; // 0x0218 + STRUCT ifm_cblk_depth_m1_r IFM_CBLK_DEPTH_M1; // 0x021C + STRUCT ofm_x_r OFM_X; // 0x0220 + STRUCT ofm_y_r OFM_Y; // 0x0224 + STRUCT ofm_z_r OFM_Z; // 0x0228 + STRUCT ifm_z_r IFM_Z; // 0x022C + STRUCT pad_top_r PAD_TOP; // 0x0230 + STRUCT pad_left_r PAD_LEFT; // 0x0234 + STRUCT ifm_cblk_width_r IFM_CBLK_WIDTH; // 0x0238 + STRUCT ifm_cblk_height_r IFM_CBLK_HEIGHT; // 0x023C + STRUCT dma_ifm_src_r DMA_IFM_SRC; // 0x0240 + STRUCT dma_ifm_dst_r DMA_IFM_DST; // 0x0248 + STRUCT dma_ofm_src_r DMA_OFM_SRC; // 0x024C + STRUCT dma_ofm_dst_r DMA_OFM_DST; // 0x0250 + STRUCT dma_weight_src_r DMA_WEIGHT_SRC; // 0x0258 + STRUCT dma_cmd_src_r DMA_CMD_SRC; // 0x0260 + STRUCT dma_cmd_size_r DMA_CMD_SIZE; // 0x0268 + STRUCT dma_m2m_src_r DMA_M2M_SRC; // 0x026C + STRUCT dma_m2m_dst_r DMA_M2M_DST; // 0x0274 + STRUCT current_qread_r CURRENT_QREAD; // 0x027C + STRUCT dma_scale_src_r DMA_SCALE_SRC; // 0x0280 + uint32_t unused8[11]; + STRUCT current_block_r CURRENT_BLOCK; // 0x02B4 + STRUCT current_op_r CURRENT_OP; // 0x02B8 + STRUCT current_cmd_r CURRENT_CMD; // 0x02BC + uint32_t unused9[16]; + STRUCT pmevcntr_r PMEVCNTR[4]; // 0x0300 + uint32_t unused10[28]; + STRUCT pmevtyper_r PMEVTYPER[4]; // 0x0380 + uint32_t unused11[28]; + STRUCT shared_buffer_r SHARED_BUFFER[256]; // 0x0400 + STRUCT ifm_pad_top_r IFM_PAD_TOP; // 0x0800 + STRUCT ifm_pad_left_r IFM_PAD_LEFT; // 0x0804 + STRUCT ifm_pad_right_r IFM_PAD_RIGHT; // 0x0808 + STRUCT ifm_pad_bottom_r IFM_PAD_BOTTOM; // 0x080C + STRUCT ifm_depth_m1_r IFM_DEPTH_M1; // 0x0810 + STRUCT ifm_precision_r IFM_PRECISION; // 0x0814 + uint32_t unused12[1]; + STRUCT ifm_upscale_r IFM_UPSCALE; // 0x081C + uint32_t unused13[1]; + STRUCT ifm_zero_point_r IFM_ZERO_POINT; // 0x0824 + STRUCT ifm_width0_m1_r IFM_WIDTH0_M1; // 0x0828 + STRUCT ifm_height0_m1_r IFM_HEIGHT0_M1; // 0x082C + STRUCT ifm_height1_m1_r IFM_HEIGHT1_M1; // 0x0830 + STRUCT ifm_ib_end_r IFM_IB_END; // 0x0834 + uint32_t unused14[1]; + STRUCT ifm_region_r IFM_REGION; // 0x083C + uint32_t unused15[1]; + STRUCT ofm_width_m1_r OFM_WIDTH_M1; // 0x0844 + STRUCT ofm_height_m1_r OFM_HEIGHT_M1; // 0x0848 + STRUCT ofm_depth_m1_r OFM_DEPTH_M1; // 0x084C + STRUCT ofm_precision_r OFM_PRECISION; // 0x0850 + STRUCT ofm_blk_width_m1_r OFM_BLK_WIDTH_M1; // 0x0854 + STRUCT ofm_blk_height_m1_r OFM_BLK_HEIGHT_M1; // 0x0858 + STRUCT ofm_blk_depth_m1_r OFM_BLK_DEPTH_M1; // 0x085C + STRUCT ofm_zero_point_r OFM_ZERO_POINT; // 0x0860 + uint32_t unused16[1]; + STRUCT ofm_width0_m1_r OFM_WIDTH0_M1; // 0x0868 + STRUCT ofm_height0_m1_r OFM_HEIGHT0_M1; // 0x086C + STRUCT ofm_height1_m1_r OFM_HEIGHT1_M1; // 0x0870 + uint32_t unused17[2]; + STRUCT ofm_region_r OFM_REGION; // 0x087C + STRUCT kernel_width_m1_r KERNEL_WIDTH_M1; // 0x0880 + STRUCT kernel_height_m1_r KERNEL_HEIGHT_M1; // 0x0884 + STRUCT kernel_stride_r KERNEL_STRIDE; // 0x0888 + STRUCT parallel_mode_r PARALLEL_MODE; // 0x088C + STRUCT acc_format_r ACC_FORMAT; // 0x0890 + STRUCT activation_r ACTIVATION; // 0x0894 + STRUCT activation_min_r ACTIVATION_MIN; // 0x0898 + STRUCT activation_max_r ACTIVATION_MAX; // 0x089C + STRUCT weight_region_r WEIGHT_REGION; // 0x08A0 + STRUCT scale_region_r SCALE_REGION; // 0x08A4 + uint32_t unused18[3]; + STRUCT ab_start_r AB_START; // 0x08B4 + uint32_t unused19[1]; + STRUCT blockdep_r BLOCKDEP; // 0x08BC + STRUCT dma0_src_region_r DMA0_SRC_REGION; // 0x08C0 + STRUCT dma0_dst_region_r DMA0_DST_REGION; // 0x08C4 + STRUCT dma0_size0_r DMA0_SIZE0; // 0x08C8 + STRUCT dma0_size1_r DMA0_SIZE1; // 0x08CC + uint32_t unused20[12]; + STRUCT ifm2_broadcast_r IFM2_BROADCAST; // 0x0900 + STRUCT ifm2_scalar_r IFM2_SCALAR; // 0x0904 + uint32_t unused21[3]; + STRUCT ifm2_precision_r IFM2_PRECISION; // 0x0914 + uint32_t unused22[3]; + STRUCT ifm2_zero_point_r IFM2_ZERO_POINT; // 0x0924 + STRUCT ifm2_width0_m1_r IFM2_WIDTH0_M1; // 0x0928 + STRUCT ifm2_height0_m1_r IFM2_HEIGHT0_M1; // 0x092C + STRUCT ifm2_height1_m1_r IFM2_HEIGHT1_M1; // 0x0930 + STRUCT ifm2_ib_start_r IFM2_IB_START; // 0x0934 + uint32_t unused23[1]; + STRUCT ifm2_region_r IFM2_REGION; // 0x093C + uint32_t unused24[48]; + STRUCT ifm_base0_r IFM_BASE0; // 0x0A00 + STRUCT ifm_base1_r IFM_BASE1; // 0x0A08 + STRUCT ifm_base2_r IFM_BASE2; // 0x0A10 + STRUCT ifm_base3_r IFM_BASE3; // 0x0A18 + STRUCT ifm_stride_x_r IFM_STRIDE_X; // 0x0A20 + STRUCT ifm_stride_y_r IFM_STRIDE_Y; // 0x0A28 + STRUCT ifm_stride_c_r IFM_STRIDE_C; // 0x0A30 + uint32_t unused25[2]; + STRUCT ofm_base0_r OFM_BASE0; // 0x0A40 + STRUCT ofm_base1_r OFM_BASE1; // 0x0A48 + STRUCT ofm_base2_r OFM_BASE2; // 0x0A50 + STRUCT ofm_base3_r OFM_BASE3; // 0x0A58 + STRUCT ofm_stride_x_r OFM_STRIDE_X; // 0x0A60 + STRUCT ofm_stride_y_r OFM_STRIDE_Y; // 0x0A68 + STRUCT ofm_stride_c_r OFM_STRIDE_C; // 0x0A70 + uint32_t unused26[2]; + STRUCT weight_base_r WEIGHT_BASE; // 0x0A80 + STRUCT weight_length_r WEIGHT_LENGTH; // 0x0A88 + STRUCT scale_base_r SCALE_BASE; // 0x0A90 + STRUCT scale_length_r SCALE_LENGTH; // 0x0A98 + STRUCT ofm_scale_r OFM_SCALE; // 0x0AA0 + STRUCT ofm_scale_shift_r OFM_SCALE_SHIFT; // 0x0AA4 + STRUCT opa_scale_r OPA_SCALE; // 0x0AA8 + STRUCT opa_scale_shift_r OPA_SCALE_SHIFT; // 0x0AAC + STRUCT opb_scale_r OPB_SCALE; // 0x0AB0 + uint32_t unused27[3]; + STRUCT dma0_src_r DMA0_SRC; // 0x0AC0 + STRUCT dma0_dst_r DMA0_DST; // 0x0AC8 + STRUCT dma0_len_r DMA0_LEN; // 0x0AD0 + STRUCT dma0_skip0_r DMA0_SKIP0; // 0x0AD8 + STRUCT dma0_skip1_r DMA0_SKIP1; // 0x0AE0 + uint32_t unused28[6]; + STRUCT ifm2_base0_r IFM2_BASE0; // 0x0B00 + STRUCT ifm2_base1_r IFM2_BASE1; // 0x0B08 + STRUCT ifm2_base2_r IFM2_BASE2; // 0x0B10 + STRUCT ifm2_base3_r IFM2_BASE3; // 0x0B18 + STRUCT ifm2_stride_x_r IFM2_STRIDE_X; // 0x0B20 + STRUCT ifm2_stride_y_r IFM2_STRIDE_Y; // 0x0B28 + STRUCT ifm2_stride_c_r IFM2_STRIDE_C; // 0x0B30 + uint32_t unused29[2]; + STRUCT weight1_base_r WEIGHT1_BASE; // 0x0B40 + STRUCT weight1_length_r WEIGHT1_LENGTH; // 0x0B48 + STRUCT scale1_base_r SCALE1_BASE; // 0x0B50 + STRUCT scale1_length_r SCALE1_LENGTH; // 0x0B58 + uint32_t unused30[280]; + STRUCT revision_r REVISION; // 0x0FC0 + uint32_t unused31[3]; + STRUCT pid4_r PID4; // 0x0FD0 + STRUCT pid5_r PID5; // 0x0FD4 + STRUCT pid6_r PID6; // 0x0FD8 + STRUCT pid7_r PID7; // 0x0FDC + STRUCT pid0_r PID0; // 0x0FE0 + STRUCT pid1_r PID1; // 0x0FE4 + STRUCT pid2_r PID2; // 0x0FE8 + STRUCT pid3_r PID3; // 0x0FEC + STRUCT cid0_r CID0; // 0x0FF0 + STRUCT cid1_r CID1; // 0x0FF4 + STRUCT cid2_r CID2; // 0x0FF8 + STRUCT cid3_r CID3; // 0x0FFC + +#ifdef __cplusplus + enum class access_type_t : uint8_t + { + RW, + RO, + WO + }; + NPU_REG() + { + reset(); + } + void reset() + { + ID = 268853249; + STATUS = 8; + CMD = 12; + RESET = 0; + QBASE = 0; + QREAD = 0; + QCONFIG = 0; + QSIZE = 0; + PROT = 0; + CONFIG = 268435456; + LOCK = 0; + REGIONCFG = 0; + AXI_LIMIT0 = 0; + AXI_LIMIT1 = 0; + AXI_LIMIT2 = 0; + AXI_LIMIT3 = 0; + for (size_t i = 0; i < (sizeof(BASEP) / sizeof(BASEP[0])); ++i) + BASEP[i] = 0; + WD_STATUS = 0; + MAC_STATUS = 0; + AO_STATUS = 0; + DMA_STATUS0 = 0; + DMA_STATUS1 = 0; + CLKFORCE = 0; + DEBUG_ADDRESS = 0; + DEBUG_MISC = 0; + DEBUGCORE = 0; + DEBUG_BLOCK = 0; + PMCR = 8192; + PMCNTENSET = 0; + PMCNTENCLR = 0; + PMOVSSET = 0; + PMOVSCLR = 0; + PMINTSET = 0; + PMINTCLR = 0; + PMCCNTR = 0; + PMCCNTR_CFG = 0; + PMCAXI_CHAN = 0; + KERNEL_X = 0; + KERNEL_Y = 0; + KERNEL_W_M1 = 0; + KERNEL_H_M1 = 0; + OFM_CBLK_WIDTH_M1 = 0; + OFM_CBLK_HEIGHT_M1 = 0; + OFM_CBLK_DEPTH_M1 = 0; + IFM_CBLK_DEPTH_M1 = 0; + OFM_X = 0; + OFM_Y = 0; + OFM_Z = 0; + IFM_Z = 0; + PAD_TOP = 0; + PAD_LEFT = 0; + IFM_CBLK_WIDTH = 0; + IFM_CBLK_HEIGHT = 0; + DMA_IFM_SRC = 0; + DMA_IFM_DST = 0; + DMA_OFM_SRC = 0; + DMA_OFM_DST = 0; + DMA_WEIGHT_SRC = 0; + DMA_CMD_SRC = 0; + DMA_CMD_SIZE = 0; + DMA_M2M_SRC = 0; + DMA_M2M_DST = 0; + CURRENT_QREAD = 0; + DMA_SCALE_SRC = 0; + CURRENT_BLOCK = 0; + CURRENT_OP = 0; + CURRENT_CMD = 0; + for (size_t i = 0; i < (sizeof(PMEVCNTR) / sizeof(PMEVCNTR[0])); ++i) + PMEVCNTR[i] = 0; + for (size_t i = 0; i < (sizeof(PMEVTYPER) / sizeof(PMEVTYPER[0])); ++i) + PMEVTYPER[i] = 0; + for (size_t i = 0; i < (sizeof(SHARED_BUFFER) / sizeof(SHARED_BUFFER[0])); ++i) + SHARED_BUFFER[i] = 0; + IFM_PAD_TOP = 0; + IFM_PAD_LEFT = 0; + IFM_PAD_RIGHT = 0; + IFM_PAD_BOTTOM = 0; + IFM_DEPTH_M1 = 0; + IFM_PRECISION = 0; + IFM_UPSCALE = 0; + IFM_ZERO_POINT = 0; + IFM_WIDTH0_M1 = 0; + IFM_HEIGHT0_M1 = 0; + IFM_HEIGHT1_M1 = 0; + IFM_IB_END = 0; + IFM_REGION = 0; + OFM_WIDTH_M1 = 0; + OFM_HEIGHT_M1 = 0; + OFM_DEPTH_M1 = 0; + OFM_PRECISION = 0; + OFM_BLK_WIDTH_M1 = 0; + OFM_BLK_HEIGHT_M1 = 0; + OFM_BLK_DEPTH_M1 = 0; + OFM_ZERO_POINT = 0; + OFM_WIDTH0_M1 = 0; + OFM_HEIGHT0_M1 = 0; + OFM_HEIGHT1_M1 = 0; + OFM_REGION = 0; + KERNEL_WIDTH_M1 = 0; + KERNEL_HEIGHT_M1 = 0; + KERNEL_STRIDE = 0; + PARALLEL_MODE = 0; + ACC_FORMAT = 0; + ACTIVATION = 0; + ACTIVATION_MIN = 0; + ACTIVATION_MAX = 0; + WEIGHT_REGION = 0; + SCALE_REGION = 0; + AB_START = 0; + BLOCKDEP = 0; + DMA0_SRC_REGION = 0; + DMA0_DST_REGION = 0; + DMA0_SIZE0 = 0; + DMA0_SIZE1 = 0; + IFM2_BROADCAST = 0; + IFM2_SCALAR = 0; + IFM2_PRECISION = 0; + IFM2_ZERO_POINT = 0; + IFM2_WIDTH0_M1 = 0; + IFM2_HEIGHT0_M1 = 0; + IFM2_HEIGHT1_M1 = 0; + IFM2_IB_START = 0; + IFM2_REGION = 0; + IFM_BASE0 = 0; + IFM_BASE1 = 0; + IFM_BASE2 = 0; + IFM_BASE3 = 0; + IFM_STRIDE_X = 0; + IFM_STRIDE_Y = 0; + IFM_STRIDE_C = 0; + OFM_BASE0 = 0; + OFM_BASE1 = 0; + OFM_BASE2 = 0; + OFM_BASE3 = 0; + OFM_STRIDE_X = 0; + OFM_STRIDE_Y = 0; + OFM_STRIDE_C = 0; + WEIGHT_BASE = 0; + WEIGHT_LENGTH = 0; + SCALE_BASE = 0; + SCALE_LENGTH = 0; + OFM_SCALE = 0; + OFM_SCALE_SHIFT = 0; + OPA_SCALE = 0; + OPA_SCALE_SHIFT = 0; + OPB_SCALE = 0; + DMA0_SRC = 0; + DMA0_DST = 0; + DMA0_LEN = 0; + DMA0_SKIP0 = 0; + DMA0_SKIP1 = 0; + IFM2_BASE0 = 0; + IFM2_BASE1 = 0; + IFM2_BASE2 = 0; + IFM2_BASE3 = 0; + IFM2_STRIDE_X = 0; + IFM2_STRIDE_Y = 0; + IFM2_STRIDE_C = 0; + WEIGHT1_BASE = 0; + WEIGHT1_LENGTH = 0; + SCALE1_BASE = 0; + SCALE1_LENGTH = 0; + REVISION = 0; + PID4 = 4; + PID5 = 0; + PID6 = 0; + PID7 = 0; + PID0 = 129; + PID1 = 181; + PID2 = 11; + PID3 = 0; + CID0 = 13; + CID1 = 240; + CID2 = 5; + CID3 = 177; + } + uint32_t &operator[](const int addr_offset) + { + return reinterpret_cast(this)[addr_offset / 4]; + } + access_type_t get_access_type(uint32_t offset) + { + switch (offset) + { + case 0: + return access_type_t::RO; + case 4: + return access_type_t::RO; + case 8: + return access_type_t::RW; + case 12: + return access_type_t::RW; + case 16: + return access_type_t::RW; + case 24: + return access_type_t::RO; + case 28: + return access_type_t::RW; + case 32: + return access_type_t::RW; + case 36: + return access_type_t::RO; + case 40: + return access_type_t::RO; + case 44: + return access_type_t::RW; + case 60: + return access_type_t::RW; + case 64: + return access_type_t::RW; + case 68: + return access_type_t::RW; + case 72: + return access_type_t::RW; + case 76: + return access_type_t::RW; + case 128: + return access_type_t::RW; + case 136: + return access_type_t::RW; + case 144: + return access_type_t::RW; + case 152: + return access_type_t::RW; + case 160: + return access_type_t::RW; + case 168: + return access_type_t::RW; + case 176: + return access_type_t::RW; + case 184: + return access_type_t::RW; + case 256: + return access_type_t::RO; + case 260: + return access_type_t::RO; + case 264: + return access_type_t::RO; + case 272: + return access_type_t::RO; + case 276: + return access_type_t::RO; + case 320: + return access_type_t::RW; + case 324: + return access_type_t::RW; + case 328: + return access_type_t::RW; + case 332: + return access_type_t::RW; + case 336: + return access_type_t::RW; + case 384: + return access_type_t::RW; + case 388: + return access_type_t::RW; + case 392: + return access_type_t::RW; + case 396: + return access_type_t::RW; + case 400: + return access_type_t::RW; + case 404: + return access_type_t::RW; + case 408: + return access_type_t::RW; + case 416: + return access_type_t::RW; + case 424: + return access_type_t::RW; + case 428: + return access_type_t::RW; + case 512: + return access_type_t::RO; + case 516: + return access_type_t::RO; + case 520: + return access_type_t::RO; + case 524: + return access_type_t::RO; + case 528: + return access_type_t::RO; + case 532: + return access_type_t::RO; + case 536: + return access_type_t::RO; + case 540: + return access_type_t::RO; + case 544: + return access_type_t::RO; + case 548: + return access_type_t::RO; + case 552: + return access_type_t::RO; + case 556: + return access_type_t::RO; + case 560: + return access_type_t::RO; + case 564: + return access_type_t::RO; + case 568: + return access_type_t::RO; + case 572: + return access_type_t::RO; + case 576: + return access_type_t::RO; + case 584: + return access_type_t::RO; + case 588: + return access_type_t::RO; + case 592: + return access_type_t::RO; + case 600: + return access_type_t::RO; + case 608: + return access_type_t::RO; + case 616: + return access_type_t::RO; + case 620: + return access_type_t::RO; + case 628: + return access_type_t::RO; + case 636: + return access_type_t::RO; + case 640: + return access_type_t::RO; + case 692: + return access_type_t::RO; + case 696: + return access_type_t::RO; + case 700: + return access_type_t::RO; + case 768: + return access_type_t::RW; + case 772: + return access_type_t::RW; + case 776: + return access_type_t::RW; + case 780: + return access_type_t::RW; + case 896: + return access_type_t::RW; + case 900: + return access_type_t::RW; + case 904: + return access_type_t::RW; + case 908: + return access_type_t::RW; + case 1024: + return access_type_t::RW; + case 1028: + return access_type_t::RW; + case 1032: + return access_type_t::RW; + case 1036: + return access_type_t::RW; + case 1040: + return access_type_t::RW; + case 1044: + return access_type_t::RW; + case 1048: + return access_type_t::RW; + case 1052: + return access_type_t::RW; + case 1056: + return access_type_t::RW; + case 1060: + return access_type_t::RW; + case 1064: + return access_type_t::RW; + case 1068: + return access_type_t::RW; + case 1072: + return access_type_t::RW; + case 1076: + return access_type_t::RW; + case 1080: + return access_type_t::RW; + case 1084: + return access_type_t::RW; + case 1088: + return access_type_t::RW; + case 1092: + return access_type_t::RW; + case 1096: + return access_type_t::RW; + case 1100: + return access_type_t::RW; + case 1104: + return access_type_t::RW; + case 1108: + return access_type_t::RW; + case 1112: + return access_type_t::RW; + case 1116: + return access_type_t::RW; + case 1120: + return access_type_t::RW; + case 1124: + return access_type_t::RW; + case 1128: + return access_type_t::RW; + case 1132: + return access_type_t::RW; + case 1136: + return access_type_t::RW; + case 1140: + return access_type_t::RW; + case 1144: + return access_type_t::RW; + case 1148: + return access_type_t::RW; + case 1152: + return access_type_t::RW; + case 1156: + return access_type_t::RW; + case 1160: + return access_type_t::RW; + case 1164: + return access_type_t::RW; + case 1168: + return access_type_t::RW; + case 1172: + return access_type_t::RW; + case 1176: + return access_type_t::RW; + case 1180: + return access_type_t::RW; + case 1184: + return access_type_t::RW; + case 1188: + return access_type_t::RW; + case 1192: + return access_type_t::RW; + case 1196: + return access_type_t::RW; + case 1200: + return access_type_t::RW; + case 1204: + return access_type_t::RW; + case 1208: + return access_type_t::RW; + case 1212: + return access_type_t::RW; + case 1216: + return access_type_t::RW; + case 1220: + return access_type_t::RW; + case 1224: + return access_type_t::RW; + case 1228: + return access_type_t::RW; + case 1232: + return access_type_t::RW; + case 1236: + return access_type_t::RW; + case 1240: + return access_type_t::RW; + case 1244: + return access_type_t::RW; + case 1248: + return access_type_t::RW; + case 1252: + return access_type_t::RW; + case 1256: + return access_type_t::RW; + case 1260: + return access_type_t::RW; + case 1264: + return access_type_t::RW; + case 1268: + return access_type_t::RW; + case 1272: + return access_type_t::RW; + case 1276: + return access_type_t::RW; + case 1280: + return access_type_t::RW; + case 1284: + return access_type_t::RW; + case 1288: + return access_type_t::RW; + case 1292: + return access_type_t::RW; + case 1296: + return access_type_t::RW; + case 1300: + return access_type_t::RW; + case 1304: + return access_type_t::RW; + case 1308: + return access_type_t::RW; + case 1312: + return access_type_t::RW; + case 1316: + return access_type_t::RW; + case 1320: + return access_type_t::RW; + case 1324: + return access_type_t::RW; + case 1328: + return access_type_t::RW; + case 1332: + return access_type_t::RW; + case 1336: + return access_type_t::RW; + case 1340: + return access_type_t::RW; + case 1344: + return access_type_t::RW; + case 1348: + return access_type_t::RW; + case 1352: + return access_type_t::RW; + case 1356: + return access_type_t::RW; + case 1360: + return access_type_t::RW; + case 1364: + return access_type_t::RW; + case 1368: + return access_type_t::RW; + case 1372: + return access_type_t::RW; + case 1376: + return access_type_t::RW; + case 1380: + return access_type_t::RW; + case 1384: + return access_type_t::RW; + case 1388: + return access_type_t::RW; + case 1392: + return access_type_t::RW; + case 1396: + return access_type_t::RW; + case 1400: + return access_type_t::RW; + case 1404: + return access_type_t::RW; + case 1408: + return access_type_t::RW; + case 1412: + return access_type_t::RW; + case 1416: + return access_type_t::RW; + case 1420: + return access_type_t::RW; + case 1424: + return access_type_t::RW; + case 1428: + return access_type_t::RW; + case 1432: + return access_type_t::RW; + case 1436: + return access_type_t::RW; + case 1440: + return access_type_t::RW; + case 1444: + return access_type_t::RW; + case 1448: + return access_type_t::RW; + case 1452: + return access_type_t::RW; + case 1456: + return access_type_t::RW; + case 1460: + return access_type_t::RW; + case 1464: + return access_type_t::RW; + case 1468: + return access_type_t::RW; + case 1472: + return access_type_t::RW; + case 1476: + return access_type_t::RW; + case 1480: + return access_type_t::RW; + case 1484: + return access_type_t::RW; + case 1488: + return access_type_t::RW; + case 1492: + return access_type_t::RW; + case 1496: + return access_type_t::RW; + case 1500: + return access_type_t::RW; + case 1504: + return access_type_t::RW; + case 1508: + return access_type_t::RW; + case 1512: + return access_type_t::RW; + case 1516: + return access_type_t::RW; + case 1520: + return access_type_t::RW; + case 1524: + return access_type_t::RW; + case 1528: + return access_type_t::RW; + case 1532: + return access_type_t::RW; + case 1536: + return access_type_t::RW; + case 1540: + return access_type_t::RW; + case 1544: + return access_type_t::RW; + case 1548: + return access_type_t::RW; + case 1552: + return access_type_t::RW; + case 1556: + return access_type_t::RW; + case 1560: + return access_type_t::RW; + case 1564: + return access_type_t::RW; + case 1568: + return access_type_t::RW; + case 1572: + return access_type_t::RW; + case 1576: + return access_type_t::RW; + case 1580: + return access_type_t::RW; + case 1584: + return access_type_t::RW; + case 1588: + return access_type_t::RW; + case 1592: + return access_type_t::RW; + case 1596: + return access_type_t::RW; + case 1600: + return access_type_t::RW; + case 1604: + return access_type_t::RW; + case 1608: + return access_type_t::RW; + case 1612: + return access_type_t::RW; + case 1616: + return access_type_t::RW; + case 1620: + return access_type_t::RW; + case 1624: + return access_type_t::RW; + case 1628: + return access_type_t::RW; + case 1632: + return access_type_t::RW; + case 1636: + return access_type_t::RW; + case 1640: + return access_type_t::RW; + case 1644: + return access_type_t::RW; + case 1648: + return access_type_t::RW; + case 1652: + return access_type_t::RW; + case 1656: + return access_type_t::RW; + case 1660: + return access_type_t::RW; + case 1664: + return access_type_t::RW; + case 1668: + return access_type_t::RW; + case 1672: + return access_type_t::RW; + case 1676: + return access_type_t::RW; + case 1680: + return access_type_t::RW; + case 1684: + return access_type_t::RW; + case 1688: + return access_type_t::RW; + case 1692: + return access_type_t::RW; + case 1696: + return access_type_t::RW; + case 1700: + return access_type_t::RW; + case 1704: + return access_type_t::RW; + case 1708: + return access_type_t::RW; + case 1712: + return access_type_t::RW; + case 1716: + return access_type_t::RW; + case 1720: + return access_type_t::RW; + case 1724: + return access_type_t::RW; + case 1728: + return access_type_t::RW; + case 1732: + return access_type_t::RW; + case 1736: + return access_type_t::RW; + case 1740: + return access_type_t::RW; + case 1744: + return access_type_t::RW; + case 1748: + return access_type_t::RW; + case 1752: + return access_type_t::RW; + case 1756: + return access_type_t::RW; + case 1760: + return access_type_t::RW; + case 1764: + return access_type_t::RW; + case 1768: + return access_type_t::RW; + case 1772: + return access_type_t::RW; + case 1776: + return access_type_t::RW; + case 1780: + return access_type_t::RW; + case 1784: + return access_type_t::RW; + case 1788: + return access_type_t::RW; + case 1792: + return access_type_t::RW; + case 1796: + return access_type_t::RW; + case 1800: + return access_type_t::RW; + case 1804: + return access_type_t::RW; + case 1808: + return access_type_t::RW; + case 1812: + return access_type_t::RW; + case 1816: + return access_type_t::RW; + case 1820: + return access_type_t::RW; + case 1824: + return access_type_t::RW; + case 1828: + return access_type_t::RW; + case 1832: + return access_type_t::RW; + case 1836: + return access_type_t::RW; + case 1840: + return access_type_t::RW; + case 1844: + return access_type_t::RW; + case 1848: + return access_type_t::RW; + case 1852: + return access_type_t::RW; + case 1856: + return access_type_t::RW; + case 1860: + return access_type_t::RW; + case 1864: + return access_type_t::RW; + case 1868: + return access_type_t::RW; + case 1872: + return access_type_t::RW; + case 1876: + return access_type_t::RW; + case 1880: + return access_type_t::RW; + case 1884: + return access_type_t::RW; + case 1888: + return access_type_t::RW; + case 1892: + return access_type_t::RW; + case 1896: + return access_type_t::RW; + case 1900: + return access_type_t::RW; + case 1904: + return access_type_t::RW; + case 1908: + return access_type_t::RW; + case 1912: + return access_type_t::RW; + case 1916: + return access_type_t::RW; + case 1920: + return access_type_t::RW; + case 1924: + return access_type_t::RW; + case 1928: + return access_type_t::RW; + case 1932: + return access_type_t::RW; + case 1936: + return access_type_t::RW; + case 1940: + return access_type_t::RW; + case 1944: + return access_type_t::RW; + case 1948: + return access_type_t::RW; + case 1952: + return access_type_t::RW; + case 1956: + return access_type_t::RW; + case 1960: + return access_type_t::RW; + case 1964: + return access_type_t::RW; + case 1968: + return access_type_t::RW; + case 1972: + return access_type_t::RW; + case 1976: + return access_type_t::RW; + case 1980: + return access_type_t::RW; + case 1984: + return access_type_t::RW; + case 1988: + return access_type_t::RW; + case 1992: + return access_type_t::RW; + case 1996: + return access_type_t::RW; + case 2000: + return access_type_t::RW; + case 2004: + return access_type_t::RW; + case 2008: + return access_type_t::RW; + case 2012: + return access_type_t::RW; + case 2016: + return access_type_t::RW; + case 2020: + return access_type_t::RW; + case 2024: + return access_type_t::RW; + case 2028: + return access_type_t::RW; + case 2032: + return access_type_t::RW; + case 2036: + return access_type_t::RW; + case 2040: + return access_type_t::RW; + case 2044: + return access_type_t::RW; + case 2048: + return access_type_t::RW; + case 2052: + return access_type_t::RW; + case 2056: + return access_type_t::RW; + case 2060: + return access_type_t::RW; + case 2064: + return access_type_t::RW; + case 2068: + return access_type_t::RW; + case 2076: + return access_type_t::RW; + case 2084: + return access_type_t::RW; + case 2088: + return access_type_t::RW; + case 2092: + return access_type_t::RW; + case 2096: + return access_type_t::RW; + case 2100: + return access_type_t::RW; + case 2108: + return access_type_t::RW; + case 2116: + return access_type_t::RW; + case 2120: + return access_type_t::RW; + case 2124: + return access_type_t::RW; + case 2128: + return access_type_t::RW; + case 2132: + return access_type_t::RW; + case 2136: + return access_type_t::RW; + case 2140: + return access_type_t::RW; + case 2144: + return access_type_t::RW; + case 2152: + return access_type_t::RW; + case 2156: + return access_type_t::RW; + case 2160: + return access_type_t::RW; + case 2172: + return access_type_t::RW; + case 2176: + return access_type_t::RW; + case 2180: + return access_type_t::RW; + case 2184: + return access_type_t::RW; + case 2188: + return access_type_t::RW; + case 2192: + return access_type_t::RW; + case 2196: + return access_type_t::RW; + case 2200: + return access_type_t::RW; + case 2204: + return access_type_t::RW; + case 2208: + return access_type_t::RW; + case 2212: + return access_type_t::RW; + case 2228: + return access_type_t::RW; + case 2236: + return access_type_t::RW; + case 2240: + return access_type_t::RW; + case 2244: + return access_type_t::RW; + case 2248: + return access_type_t::RW; + case 2252: + return access_type_t::RW; + case 2304: + return access_type_t::RW; + case 2308: + return access_type_t::RW; + case 2324: + return access_type_t::RW; + case 2340: + return access_type_t::RW; + case 2344: + return access_type_t::RW; + case 2348: + return access_type_t::RW; + case 2352: + return access_type_t::RW; + case 2356: + return access_type_t::RW; + case 2364: + return access_type_t::RW; + case 2560: + return access_type_t::RW; + case 2568: + return access_type_t::RW; + case 2576: + return access_type_t::RW; + case 2584: + return access_type_t::RW; + case 2592: + return access_type_t::RW; + case 2600: + return access_type_t::RW; + case 2608: + return access_type_t::RW; + case 2624: + return access_type_t::RW; + case 2632: + return access_type_t::RW; + case 2640: + return access_type_t::RW; + case 2648: + return access_type_t::RW; + case 2656: + return access_type_t::RW; + case 2664: + return access_type_t::RW; + case 2672: + return access_type_t::RW; + case 2688: + return access_type_t::RW; + case 2696: + return access_type_t::RW; + case 2704: + return access_type_t::RW; + case 2712: + return access_type_t::RW; + case 2720: + return access_type_t::RW; + case 2724: + return access_type_t::RW; + case 2728: + return access_type_t::RW; + case 2732: + return access_type_t::RW; + case 2736: + return access_type_t::RW; + case 2752: + return access_type_t::RW; + case 2760: + return access_type_t::RW; + case 2768: + return access_type_t::RW; + case 2776: + return access_type_t::RW; + case 2784: + return access_type_t::RW; + case 2816: + return access_type_t::RW; + case 2824: + return access_type_t::RW; + case 2832: + return access_type_t::RW; + case 2840: + return access_type_t::RW; + case 2848: + return access_type_t::RW; + case 2856: + return access_type_t::RW; + case 2864: + return access_type_t::RW; + case 2880: + return access_type_t::RW; + case 2888: + return access_type_t::RW; + case 2896: + return access_type_t::RW; + case 2904: + return access_type_t::RW; + case 4032: + return access_type_t::RO; + case 4048: + return access_type_t::RO; + case 4052: + return access_type_t::RO; + case 4056: + return access_type_t::RO; + case 4060: + return access_type_t::RO; + case 4064: + return access_type_t::RO; + case 4068: + return access_type_t::RO; + case 4072: + return access_type_t::RO; + case 4076: + return access_type_t::RO; + case 4080: + return access_type_t::RO; + case 4084: + return access_type_t::RO; + case 4088: + return access_type_t::RO; + case 4092: + return access_type_t::RO; + default: + return access_type_t::RO; + } + } +#endif +}; + +#ifdef __cplusplus +struct isa +{ +#ifdef NPU_DISASSEMBLE + static int disassemble(const uint32_t *in, + std::string &op, + std::vector> &fields) + { + switch (*in & 0xffff) + { + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP): + { + const npu_op_stop_t &v = *reinterpret_cast(in); + op = "NPU_OP_STOP"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ): + { + const npu_op_irq_t &v = *reinterpret_cast(in); + op = "NPU_OP_IRQ"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV): + { + const npu_op_conv_t &v = *reinterpret_cast(in); + op = "NPU_OP_CONV"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE): + { + const npu_op_depthwise_t &v = *reinterpret_cast(in); + op = "NPU_OP_DEPTHWISE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL): + { + const npu_op_pool_t &v = *reinterpret_cast(in); + op = "NPU_OP_POOL"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE): + { + const npu_op_elementwise_t &v = *reinterpret_cast(in); + op = "NPU_OP_ELEMENTWISE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START): + { + const npu_op_dma_start_t &v = *reinterpret_cast(in); + op = "NPU_OP_DMA_START"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT): + { + const npu_op_dma_wait_t &v = *reinterpret_cast(in); + op = "NPU_OP_DMA_WAIT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT): + { + const npu_op_kernel_wait_t &v = *reinterpret_cast(in); + op = "NPU_OP_KERNEL_WAIT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK): + { + const npu_op_pmu_mask_t &v = *reinterpret_cast(in); + op = "NPU_OP_PMU_MASK"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP): + { + const npu_set_ifm_pad_top_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_TOP"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT): + { + const npu_set_ifm_pad_left_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_LEFT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT): + { + const npu_set_ifm_pad_right_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_RIGHT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM): + { + const npu_set_ifm_pad_bottom_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PAD_BOTTOM"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1): + { + const npu_set_ifm_depth_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_DEPTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION): + { + const npu_set_ifm_precision_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_PRECISION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE): + { + const npu_set_ifm_upscale_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_UPSCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT): + { + const npu_set_ifm_zero_point_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_ZERO_POINT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1): + { + const npu_set_ifm_width0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_WIDTH0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1): + { + const npu_set_ifm_height0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_HEIGHT0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1): + { + const npu_set_ifm_height1_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_HEIGHT1_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END): + { + const npu_set_ifm_ib_end_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_IB_END"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION): + { + const npu_set_ifm_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1): + { + const npu_set_ofm_width_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_WIDTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1): + { + const npu_set_ofm_height_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_HEIGHT_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1): + { + const npu_set_ofm_depth_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_DEPTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION): + { + const npu_set_ofm_precision_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_PRECISION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1): + { + const npu_set_ofm_blk_width_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BLK_WIDTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1): + { + const npu_set_ofm_blk_height_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BLK_HEIGHT_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1): + { + const npu_set_ofm_blk_depth_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BLK_DEPTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT): + { + const npu_set_ofm_zero_point_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_ZERO_POINT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1): + { + const npu_set_ofm_width0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_WIDTH0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1): + { + const npu_set_ofm_height0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_HEIGHT0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1): + { + const npu_set_ofm_height1_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_HEIGHT1_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION): + { + const npu_set_ofm_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1): + { + const npu_set_kernel_width_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_KERNEL_WIDTH_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1): + { + const npu_set_kernel_height_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_KERNEL_HEIGHT_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE): + { + const npu_set_kernel_stride_t &v = *reinterpret_cast(in); + op = "NPU_SET_KERNEL_STRIDE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE): + { + const npu_set_parallel_mode_t &v = *reinterpret_cast(in); + op = "NPU_SET_PARALLEL_MODE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT): + { + const npu_set_acc_format_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACC_FORMAT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION): + { + const npu_set_activation_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACTIVATION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN): + { + const npu_set_activation_min_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACTIVATION_MIN"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX): + { + const npu_set_activation_max_t &v = *reinterpret_cast(in); + op = "NPU_SET_ACTIVATION_MAX"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION): + { + const npu_set_weight_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION): + { + const npu_set_scale_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START): + { + const npu_set_ab_start_t &v = *reinterpret_cast(in); + op = "NPU_SET_AB_START"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP): + { + const npu_set_blockdep_t &v = *reinterpret_cast(in); + op = "NPU_SET_BLOCKDEP"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION): + { + const npu_set_dma0_src_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SRC_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION): + { + const npu_set_dma0_dst_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_DST_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0): + { + const npu_set_dma0_size0_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SIZE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1): + { + const npu_set_dma0_size1_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SIZE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST): + { + const npu_set_ifm2_broadcast_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BROADCAST"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR): + { + const npu_set_ifm2_scalar_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_SCALAR"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION): + { + const npu_set_ifm2_precision_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_PRECISION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT): + { + const npu_set_ifm2_zero_point_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_ZERO_POINT"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1): + { + const npu_set_ifm2_width0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_WIDTH0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1): + { + const npu_set_ifm2_height0_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_HEIGHT0_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1): + { + const npu_set_ifm2_height1_m1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_HEIGHT1_M1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START): + { + const npu_set_ifm2_ib_start_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_IB_START"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION): + { + const npu_set_ifm2_region_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_REGION"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0): + { + const npu_set_ifm_base0_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1): + { + const npu_set_ifm_base1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2): + { + const npu_set_ifm_base2_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE2"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3): + { + const npu_set_ifm_base3_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_BASE3"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X): + { + const npu_set_ifm_stride_x_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_STRIDE_X"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y): + { + const npu_set_ifm_stride_y_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_STRIDE_Y"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C): + { + const npu_set_ifm_stride_c_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM_STRIDE_C"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0): + { + const npu_set_ofm_base0_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1): + { + const npu_set_ofm_base1_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2): + { + const npu_set_ofm_base2_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE2"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3): + { + const npu_set_ofm_base3_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_BASE3"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X): + { + const npu_set_ofm_stride_x_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_STRIDE_X"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y): + { + const npu_set_ofm_stride_y_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_STRIDE_Y"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C): + { + const npu_set_ofm_stride_c_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_STRIDE_C"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE): + { + const npu_set_weight_base_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT_BASE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH): + { + const npu_set_weight_length_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT_LENGTH"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE): + { + const npu_set_scale_base_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE_BASE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH): + { + const npu_set_scale_length_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE_LENGTH"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE): + { + const npu_set_ofm_scale_t &v = *reinterpret_cast(in); + op = "NPU_SET_OFM_SCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE): + { + const npu_set_opa_scale_t &v = *reinterpret_cast(in); + op = "NPU_SET_OPA_SCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE): + { + const npu_set_opb_scale_t &v = *reinterpret_cast(in); + op = "NPU_SET_OPB_SCALE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC): + { + const npu_set_dma0_src_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SRC"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST): + { + const npu_set_dma0_dst_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_DST"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN): + { + const npu_set_dma0_len_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_LEN"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0): + { + const npu_set_dma0_skip0_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SKIP0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1): + { + const npu_set_dma0_skip1_t &v = *reinterpret_cast(in); + op = "NPU_SET_DMA0_SKIP1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0): + { + const npu_set_ifm2_base0_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE0"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1): + { + const npu_set_ifm2_base1_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE1"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2): + { + const npu_set_ifm2_base2_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE2"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3): + { + const npu_set_ifm2_base3_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_BASE3"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X): + { + const npu_set_ifm2_stride_x_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_STRIDE_X"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y): + { + const npu_set_ifm2_stride_y_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_STRIDE_Y"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C): + { + const npu_set_ifm2_stride_c_t &v = *reinterpret_cast(in); + op = "NPU_SET_IFM2_STRIDE_C"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE): + { + const npu_set_weight1_base_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT1_BASE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH): + { + const npu_set_weight1_length_t &v = *reinterpret_cast(in); + op = "NPU_SET_WEIGHT1_LENGTH"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE): + { + const npu_set_scale1_base_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE1_BASE"; + v.disassemble(fields); + break; + } + case (static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) | + static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH): + { + const npu_set_scale1_length_t &v = *reinterpret_cast(in); + op = "NPU_SET_SCALE1_LENGTH"; + v.disassemble(fields); + break; + } + } + return (*in & (3 << 14)) != 0 ? 2 : 1; + } +#endif +#endif + // Signal the end of command stream + struct npu_op_stop_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t mask : 16; // Encoding for 16-bit mask value +#ifdef __cplusplus + public: + npu_op_stop_t(uint32_t _mask) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_op_stop_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_stop_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_stop_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_mask() const + { + return static_cast(mask); + } + CONSTEXPR npu_op_stop_t &set_mask(uint32_t value) + { + mask = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("mask", std::to_string(mask))); + } +#endif +#endif + }; + // Raises an IRQ to the host + struct npu_op_irq_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t mask : 16; // Encoding for 16-bit mask value +#ifdef __cplusplus + public: + npu_op_irq_t(uint32_t _mask) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_op_irq_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_irq_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_irq_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_mask() const + { + return static_cast(mask); + } + CONSTEXPR npu_op_irq_t &set_mask(uint32_t value) + { + mask = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("mask", std::to_string(mask))); + } +#endif +#endif + }; + // 2D convolution + struct npu_op_conv_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; +#ifdef __cplusplus + public: + CONSTEXPR npu_op_conv_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_conv_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_conv_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const {} +#endif +#endif + }; + // Depth-wise 2D convolution + struct npu_op_depthwise_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; +#ifdef __cplusplus + public: + CONSTEXPR npu_op_depthwise_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_depthwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_depthwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const {} +#endif +#endif + }; + // Pooling + struct npu_op_pool_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pooling_mode : 3; // Pooling mode + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_op_pool_t(NPU_NAMESPACE::pooling_mode _pooling_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + pooling_mode(static_cast(_pooling_mode) & ((1U << 3) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_pool_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pooling_mode(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_pool_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_pool_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::pooling_mode get_pooling_mode() const + { + return static_cast(pooling_mode); + } + CONSTEXPR npu_op_pool_t &set_pooling_mode(NPU_NAMESPACE::pooling_mode value) + { + pooling_mode = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "pooling_mode", + (pooling_mode < (sizeof(pooling_mode_str) / sizeof(pooling_mode_str[0])) ? + pooling_mode_str[pooling_mode] : + "****"))); + } +#endif +#endif + }; + // Elementwise operation + struct npu_op_elementwise_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t elementwise_mode : 6; // Elementwise mode + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_op_elementwise_t(NPU_NAMESPACE::elementwise_mode _elementwise_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + elementwise_mode(static_cast(_elementwise_mode) & ((1U << 6) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_elementwise_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), elementwise_mode(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_elementwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_elementwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::elementwise_mode get_elementwise_mode() const + { + return static_cast(elementwise_mode); + } + CONSTEXPR npu_op_elementwise_t &set_elementwise_mode(NPU_NAMESPACE::elementwise_mode value) + { + elementwise_mode = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "elementwise_mode", + (elementwise_mode < (sizeof(elementwise_mode_str) / sizeof(elementwise_mode_str[0])) ? + elementwise_mode_str[elementwise_mode] : + "****"))); + } +#endif +#endif + }; + // Queue new DMA for the given channel + struct npu_op_dma_start_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; +#ifdef __cplusplus + public: + CONSTEXPR npu_op_dma_start_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_dma_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_dma_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const {} +#endif +#endif + }; + // Wait for the DMA channel to have k or fewer active descriptors outstanding + struct npu_op_dma_wait_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t k : 4; // Number of outstanding descriptors + uint32_t reserved1 : 12; +#ifdef __cplusplus + public: + npu_op_dma_wait_t(uint32_t _k) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(_k & ((1U << 4) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_dma_wait_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_dma_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_dma_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_k() const + { + return static_cast(k); + } + CONSTEXPR npu_op_dma_wait_t &set_k(uint32_t value) + { + k = static_cast(value) & ((1U << 4) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("k", std::to_string(k))); + } +#endif +#endif + }; + // Wait for n or fewer kernel operations to be remaining + struct npu_op_kernel_wait_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t n : 2; // Number of kernel operations in range 0-3 + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_op_kernel_wait_t(uint32_t _n) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(_n & ((1U << 2) - 1)), reserved1(0) + { + } + CONSTEXPR npu_op_kernel_wait_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_kernel_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_kernel_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_n() const + { + return static_cast(n); + } + CONSTEXPR npu_op_kernel_wait_t &set_n(uint32_t value) + { + n = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("n", std::to_string(n))); + } +#endif +#endif + }; + // Enable or disable PMU counting (debug feature only) + struct npu_op_pmu_mask_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t enable : 1; // Enable or disable PMU mask + uint32_t reserved1 : 15; +#ifdef __cplusplus + public: + npu_op_pmu_mask_t(uint32_t _enable) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(_enable & ((1U << 1) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_op_pmu_mask_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_op_pmu_mask_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_op_pmu_mask_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_enable() const + { + return static_cast(enable); + } + CONSTEXPR npu_op_pmu_mask_t &set_enable(uint32_t value) + { + enable = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("enable", std::to_string(enable))); + } +#endif +#endif + }; + // IFM top pad + struct npu_set_ifm_pad_top_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 7; // IFM top pad + uint32_t reserved1 : 9; +#ifdef __cplusplus + public: + npu_set_ifm_pad_top_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_top_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_top_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_top_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_top_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 7) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // IFM left pad + struct npu_set_ifm_pad_left_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 7; // IFM left pad + uint32_t reserved1 : 9; +#ifdef __cplusplus + public: + npu_set_ifm_pad_left_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_left_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_left_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_left_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_left_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 7) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // IFM right pad + struct npu_set_ifm_pad_right_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 8; // IFM right pad. Max value is 128 + uint32_t reserved1 : 8; +#ifdef __cplusplus + public: + npu_set_ifm_pad_right_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_right_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_right_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_right_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_right_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 8) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // IFM bottom pad + struct npu_set_ifm_pad_bottom_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t pad : 8; // IFM bottom pad. Max value is 128 + uint32_t reserved1 : 8; +#ifdef __cplusplus + public: + npu_set_ifm_pad_bottom_t(uint32_t _pad) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_pad_bottom_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_pad_bottom_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_pad_bottom_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_pad() const + { + return static_cast(pad); + } + CONSTEXPR npu_set_ifm_pad_bottom_t &set_pad(uint32_t value) + { + pad = static_cast(value) & ((1U << 8) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("pad", std::to_string(pad))); + } +#endif +#endif + }; + // Number of input channels for convolution + struct npu_set_ifm_depth_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t depth_m1 : 16; // Number of input channels for convolution +#ifdef __cplusplus + public: + npu_set_ifm_depth_m1_t(uint32_t _depth_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_depth_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_depth_m1() const + { + return static_cast(depth_m1); + } + CONSTEXPR npu_set_ifm_depth_m1_t &set_depth_m1(uint32_t value) + { + depth_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("depth_m1", std::to_string(depth_m1))); + } +#endif +#endif + }; + // IFM Precision + struct npu_set_ifm_precision_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_type : 1; // IFM type + uint32_t reserved1 : 1; + uint32_t activation_precision : 2; // IFM precision + uint32_t reserved2 : 2; + uint32_t activation_format : 2; // IFM format + uint32_t scale_mode : 2; // IFM scale mode + uint32_t reserved3 : 4; + uint32_t round_mode : 2; // IFM round mode +#ifdef __cplusplus + public: + npu_set_ifm_precision_t(NPU_NAMESPACE::activation_type _activation_type, + NPU_NAMESPACE::activation_precision _activation_precision, + NPU_NAMESPACE::activation_format _activation_format, + NPU_NAMESPACE::ifm_scale_mode _scale_mode, + NPU_NAMESPACE::round_mode _round_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_type(static_cast(_activation_type) & ((1U << 1) - 1)), reserved1(0), + activation_precision(static_cast(_activation_precision) & ((1U << 2) - 1)), reserved2(0), + activation_format(static_cast(_activation_format) & ((1U << 2) - 1)), + scale_mode(static_cast(_scale_mode) & ((1U << 2) - 1)), reserved3(0), + round_mode(static_cast(_round_mode) & ((1U << 2) - 1)) + { + } + CONSTEXPR npu_set_ifm_precision_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), reserved1(0), + activation_precision(0), reserved2(0), activation_format(0), scale_mode(0), reserved3(0), round_mode(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const + { + return static_cast(activation_type); + } + CONSTEXPR npu_set_ifm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value) + { + activation_type = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const + { + return static_cast(activation_precision); + } + CONSTEXPR npu_set_ifm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value) + { + activation_precision = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const + { + return static_cast(activation_format); + } + CONSTEXPR npu_set_ifm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value) + { + activation_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ifm_scale_mode get_scale_mode() const + { + return static_cast(scale_mode); + } + CONSTEXPR npu_set_ifm_precision_t &set_scale_mode(NPU_NAMESPACE::ifm_scale_mode value) + { + scale_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const + { + return static_cast(round_mode); + } + CONSTEXPR npu_set_ifm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value) + { + round_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_type", + (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ? + activation_type_str[activation_type] : + "****"))); + fields.push_back(std::make_pair( + "activation_precision", + (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ? + activation_precision_str[activation_precision] : + "****"))); + fields.push_back(std::make_pair( + "activation_format", + (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ? + activation_format_str[activation_format] : + "****"))); + fields.push_back(std::make_pair( + "scale_mode", + (scale_mode < (sizeof(ifm_scale_mode_str) / sizeof(ifm_scale_mode_str[0])) ? + ifm_scale_mode_str[scale_mode] : + "****"))); + fields.push_back(std::make_pair( + "round_mode", + (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] : + "****"))); + } +#endif +#endif + }; + // IFM upscale mode + struct npu_set_ifm_upscale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t mode : 2; // IFM upscale mode + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_set_ifm_upscale_t(NPU_NAMESPACE::ifm_upscale_mode _mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + mode(static_cast(_mode) & ((1U << 2) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_ifm_upscale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mode(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_upscale_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_upscale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ifm_upscale_mode get_mode() const + { + return static_cast(mode); + } + CONSTEXPR npu_set_ifm_upscale_t &set_mode(NPU_NAMESPACE::ifm_upscale_mode value) + { + mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "mode", + (mode < (sizeof(ifm_upscale_mode_str) / sizeof(ifm_upscale_mode_str[0])) ? ifm_upscale_mode_str[mode] : + "****"))); + } +#endif +#endif + }; + // IFM zero point + struct npu_set_ifm_zero_point_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t zero_point : 16; // Zero point offset +#ifdef __cplusplus + public: + npu_set_ifm_zero_point_t(uint32_t _zero_point) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + zero_point(_zero_point & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_zero_point_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_zero_point() const + { + return static_cast(zero_point); + } + CONSTEXPR npu_set_ifm_zero_point_t &set_zero_point(uint32_t value) + { + zero_point = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("zero_point", std::to_string(zero_point))); + } +#endif +#endif + }; + // IFM Tile 0 and tile 2 width + struct npu_set_ifm_width0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // IFM Tile 0 and tile 2 width +#ifdef __cplusplus + public: + npu_set_ifm_width0_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_width0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ifm_width0_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // IFM Tile 0 height + struct npu_set_ifm_height0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM Tile 0 height +#ifdef __cplusplus + public: + npu_set_ifm_height0_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_height0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm_height0_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // IFM Tile 1 height + struct npu_set_ifm_height1_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM Tile 1 height +#ifdef __cplusplus + public: + npu_set_ifm_height1_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm_height1_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm_height1_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // End of IB0,IB1 buffers + struct npu_set_ifm_ib_end_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t ib_end : 6; // End of IB0,IB1 buffers in the SHRAM in KB units. Multiple of 2 + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ifm_ib_end_t(uint32_t _ib_end) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(_ib_end & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ifm_ib_end_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_ib_end_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_ib_end_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_ib_end() const + { + return static_cast(ib_end); + } + CONSTEXPR npu_set_ifm_ib_end_t &set_ib_end(uint32_t value) + { + ib_end = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("ib_end", std::to_string(ib_end))); + } +#endif +#endif + }; + // Index n for IFM access + struct npu_set_ifm_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Region number n + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_set_ifm_region_t(uint32_t _region) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ifm_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_ifm_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + } +#endif +#endif + }; + // Output feature map width + struct npu_set_ofm_width_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // Output feature map width +#ifdef __cplusplus + public: + npu_set_ofm_width_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_width_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ofm_width_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // Output feature map height + struct npu_set_ofm_height_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // Output feature map height +#ifdef __cplusplus + public: + npu_set_ofm_height_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_height_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_height_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Output feature map depth + struct npu_set_ofm_depth_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t depth_m1 : 16; // Output feature map depth +#ifdef __cplusplus + public: + npu_set_ofm_depth_m1_t(uint32_t _depth_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_depth_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_depth_m1() const + { + return static_cast(depth_m1); + } + CONSTEXPR npu_set_ofm_depth_m1_t &set_depth_m1(uint32_t value) + { + depth_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("depth_m1", std::to_string(depth_m1))); + } +#endif +#endif + }; + // OFM Precision + struct npu_set_ofm_precision_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_type : 1; // OFM type + uint32_t activation_precision : 2; // OFM precision + uint32_t reserved1 : 3; + uint32_t activation_format : 2; // OFM format + uint32_t scale_mode : 1; // OFM scale mode + uint32_t reserved2 : 5; + uint32_t round_mode : 2; // OFM round mode +#ifdef __cplusplus + public: + npu_set_ofm_precision_t(NPU_NAMESPACE::activation_type _activation_type, + NPU_NAMESPACE::activation_precision _activation_precision, + NPU_NAMESPACE::activation_format _activation_format, + NPU_NAMESPACE::ofm_scale_mode _scale_mode, + NPU_NAMESPACE::round_mode _round_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_type(static_cast(_activation_type) & ((1U << 1) - 1)), + activation_precision(static_cast(_activation_precision) & ((1U << 2) - 1)), reserved1(0), + activation_format(static_cast(_activation_format) & ((1U << 2) - 1)), + scale_mode(static_cast(_scale_mode) & ((1U << 1) - 1)), reserved2(0), + round_mode(static_cast(_round_mode) & ((1U << 2) - 1)) + { + } + CONSTEXPR npu_set_ofm_precision_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), + activation_precision(0), reserved1(0), activation_format(0), scale_mode(0), reserved2(0), round_mode(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const + { + return static_cast(activation_type); + } + CONSTEXPR npu_set_ofm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value) + { + activation_type = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const + { + return static_cast(activation_precision); + } + CONSTEXPR npu_set_ofm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value) + { + activation_precision = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const + { + return static_cast(activation_format); + } + CONSTEXPR npu_set_ofm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value) + { + activation_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ofm_scale_mode get_scale_mode() const + { + return static_cast(scale_mode); + } + CONSTEXPR npu_set_ofm_precision_t &set_scale_mode(NPU_NAMESPACE::ofm_scale_mode value) + { + scale_mode = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const + { + return static_cast(round_mode); + } + CONSTEXPR npu_set_ofm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value) + { + round_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_type", + (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ? + activation_type_str[activation_type] : + "****"))); + fields.push_back(std::make_pair( + "activation_precision", + (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ? + activation_precision_str[activation_precision] : + "****"))); + fields.push_back(std::make_pair( + "activation_format", + (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ? + activation_format_str[activation_format] : + "****"))); + fields.push_back(std::make_pair( + "scale_mode", + (scale_mode < (sizeof(ofm_scale_mode_str) / sizeof(ofm_scale_mode_str[0])) ? + ofm_scale_mode_str[scale_mode] : + "****"))); + fields.push_back(std::make_pair( + "round_mode", + (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] : + "****"))); + } +#endif +#endif + }; + // OFM block width + struct npu_set_ofm_blk_width_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 6; // OFM block width + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ofm_blk_width_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ofm_blk_width_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_blk_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_blk_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ofm_blk_width_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // OFM block height + struct npu_set_ofm_blk_height_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 5; // OFM block height + uint32_t reserved1 : 11; +#ifdef __cplusplus + public: + npu_set_ofm_blk_height_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 5) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ofm_blk_height_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_blk_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_blk_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_blk_height_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 5) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // OFM block depth + struct npu_set_ofm_blk_depth_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t depth_m1 : 7; // OFM block depth + uint32_t reserved1 : 9; +#ifdef __cplusplus + public: + npu_set_ofm_blk_depth_m1_t(uint32_t _depth_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 7) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_depth_m1() const + { + return static_cast(depth_m1); + } + CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_depth_m1(uint32_t value) + { + depth_m1 = static_cast(value) & ((1U << 7) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("depth_m1", std::to_string(depth_m1))); + } +#endif +#endif + }; + // OFM zero point + struct npu_set_ofm_zero_point_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t zero_point : 16; // Zero point offset +#ifdef __cplusplus + public: + npu_set_ofm_zero_point_t(uint32_t _zero_point) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + zero_point(_zero_point & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_zero_point_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_zero_point() const + { + return static_cast(zero_point); + } + CONSTEXPR npu_set_ofm_zero_point_t &set_zero_point(uint32_t value) + { + zero_point = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("zero_point", std::to_string(zero_point))); + } +#endif +#endif + }; + // OFM Tile 0 and tile 2 width + struct npu_set_ofm_width0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // OFM Tile 0 and tile 2 width +#ifdef __cplusplus + public: + npu_set_ofm_width0_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_width0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ofm_width0_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // OFM Tile 0 height + struct npu_set_ofm_height0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // OFM Tile 0 height +#ifdef __cplusplus + public: + npu_set_ofm_height0_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_height0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_height0_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // OFM Tile 1 height + struct npu_set_ofm_height1_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // OFM Tile 1 height +#ifdef __cplusplus + public: + npu_set_ofm_height1_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ofm_height1_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ofm_height1_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Index n for OFM access + struct npu_set_ofm_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for OFM access + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_set_ofm_region_t(uint32_t _region) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ofm_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_ofm_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + } +#endif +#endif + }; + // Kernel width + struct npu_set_kernel_width_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // Kernel width +#ifdef __cplusplus + public: + npu_set_kernel_width_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_kernel_width_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_kernel_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_kernel_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_kernel_width_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // Kernel height + struct npu_set_kernel_height_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // Kernel height +#ifdef __cplusplus + public: + npu_set_kernel_height_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_kernel_height_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_kernel_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_kernel_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_kernel_height_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Kernel stride + struct npu_set_kernel_stride_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t stride_x_lsb : 1; // Stride x LSB. (kernel_x_stride - 1)[0] + uint32_t stride_y_lsb : 1; // Stride y LSB. (kernel_y_stride - 1)[0] + uint32_t weight_order : 1; // Weight ordering mode + uint32_t dilation_x : 1; // Kernel x dilation + uint32_t dilation_y : 1; // Kernel y dilation + uint32_t decomposition : 1; // Kernel decomposition + uint32_t stride_x_msb : 1; // Stride x MSB. (kernel_x_stride - 1) >> 1 + uint32_t reserved1 : 2; + uint32_t stride_y_msb : 1; // Stride y MSB. (kernel_y_stride - 1) >> 1 + uint32_t reserved2 : 6; +#ifdef __cplusplus + public: + npu_set_kernel_stride_t(uint32_t _stride_x_lsb, + uint32_t _stride_y_lsb, + NPU_NAMESPACE::weight_order _weight_order, + NPU_NAMESPACE::kernel_dilation _dilation_x, + NPU_NAMESPACE::kernel_dilation _dilation_y, + NPU_NAMESPACE::kernel_decomposition _decomposition, + uint32_t _stride_x_msb, + uint32_t _stride_y_msb) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + stride_x_lsb(_stride_x_lsb & ((1U << 1) - 1)), stride_y_lsb(_stride_y_lsb & ((1U << 1) - 1)), + weight_order(static_cast(_weight_order) & ((1U << 1) - 1)), + dilation_x(static_cast(_dilation_x) & ((1U << 1) - 1)), + dilation_y(static_cast(_dilation_y) & ((1U << 1) - 1)), + decomposition(static_cast(_decomposition) & ((1U << 1) - 1)), + stride_x_msb(_stride_x_msb & ((1U << 1) - 1)), reserved1(0), stride_y_msb(_stride_y_msb & ((1U << 1) - 1)), + reserved2(0) + { + } + CONSTEXPR npu_set_kernel_stride_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), stride_x_lsb(0), stride_y_lsb(0), + weight_order(0), dilation_x(0), dilation_y(0), decomposition(0), stride_x_msb(0), reserved1(0), + stride_y_msb(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_kernel_stride_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_kernel_stride_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_x_lsb() const + { + return static_cast(stride_x_lsb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_x_lsb(uint32_t value) + { + stride_x_lsb = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_y_lsb() const + { + return static_cast(stride_y_lsb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_y_lsb(uint32_t value) + { + stride_y_lsb = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::weight_order get_weight_order() const + { + return static_cast(weight_order); + } + CONSTEXPR npu_set_kernel_stride_t &set_weight_order(NPU_NAMESPACE::weight_order value) + { + weight_order = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_x() const + { + return static_cast(dilation_x); + } + CONSTEXPR npu_set_kernel_stride_t &set_dilation_x(NPU_NAMESPACE::kernel_dilation value) + { + dilation_x = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_y() const + { + return static_cast(dilation_y); + } + CONSTEXPR npu_set_kernel_stride_t &set_dilation_y(NPU_NAMESPACE::kernel_dilation value) + { + dilation_y = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::kernel_decomposition get_decomposition() const + { + return static_cast(decomposition); + } + CONSTEXPR npu_set_kernel_stride_t &set_decomposition(NPU_NAMESPACE::kernel_decomposition value) + { + decomposition = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_x_msb() const + { + return static_cast(stride_x_msb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_x_msb(uint32_t value) + { + stride_x_msb = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR uint32_t get_stride_y_msb() const + { + return static_cast(stride_y_msb); + } + CONSTEXPR npu_set_kernel_stride_t &set_stride_y_msb(uint32_t value) + { + stride_y_msb = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("stride_x_lsb", std::to_string(stride_x_lsb))); + fields.push_back(std::make_pair("stride_y_lsb", std::to_string(stride_y_lsb))); + fields.push_back(std::make_pair( + "weight_order", + (weight_order < (sizeof(weight_order_str) / sizeof(weight_order_str[0])) ? + weight_order_str[weight_order] : + "****"))); + fields.push_back(std::make_pair( + "dilation_x", + (dilation_x < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ? + kernel_dilation_str[dilation_x] : + "****"))); + fields.push_back(std::make_pair( + "dilation_y", + (dilation_y < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ? + kernel_dilation_str[dilation_y] : + "****"))); + fields.push_back(std::make_pair( + "decomposition", + (decomposition < (sizeof(kernel_decomposition_str) / sizeof(kernel_decomposition_str[0])) ? + kernel_decomposition_str[decomposition] : + "****"))); + fields.push_back(std::make_pair("stride_x_msb", std::to_string(stride_x_msb))); + fields.push_back(std::make_pair("stride_y_msb", std::to_string(stride_y_msb))); + } +#endif +#endif + }; + // Multi-core parallel mode + struct npu_set_parallel_mode_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t parallel_mode : 1; // Multi-core parallel mode + uint32_t reserved1 : 15; +#ifdef __cplusplus + public: + npu_set_parallel_mode_t(NPU_NAMESPACE::parallel_mode _parallel_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + parallel_mode(static_cast(_parallel_mode) & ((1U << 1) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_parallel_mode_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), parallel_mode(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_parallel_mode_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_parallel_mode_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::parallel_mode get_parallel_mode() const + { + return static_cast(parallel_mode); + } + CONSTEXPR npu_set_parallel_mode_t &set_parallel_mode(NPU_NAMESPACE::parallel_mode value) + { + parallel_mode = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "parallel_mode", + (parallel_mode < (sizeof(parallel_mode_str) / sizeof(parallel_mode_str[0])) ? + parallel_mode_str[parallel_mode] : + "****"))); + } +#endif +#endif + }; + // Accumulator format + struct npu_set_acc_format_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t acc_format : 2; // Accumulator format + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_set_acc_format_t(NPU_NAMESPACE::acc_format _acc_format) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + acc_format(static_cast(_acc_format) & ((1U << 2) - 1)), reserved1(0) + { + } + CONSTEXPR npu_set_acc_format_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), acc_format(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_acc_format_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_acc_format_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::acc_format get_acc_format() const + { + return static_cast(acc_format); + } + CONSTEXPR npu_set_acc_format_t &set_acc_format(NPU_NAMESPACE::acc_format value) + { + acc_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "acc_format", + (acc_format < (sizeof(acc_format_str) / sizeof(acc_format_str[0])) ? acc_format_str[acc_format] : + "****"))); + } +#endif +#endif + }; + // Activation function and clip range + struct npu_set_activation_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_function : 5; // Activation function (before table lookup) + uint32_t reserved1 : 7; + uint32_t activation_clip_range : 3; // Activation clip range. This must be set to 0 if table lookup is not used + uint32_t reserved2 : 1; +#ifdef __cplusplus + public: + npu_set_activation_t(NPU_NAMESPACE::activation_function _activation_function, + NPU_NAMESPACE::activation_clip_range _activation_clip_range) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_function(static_cast(_activation_function) & ((1U << 5) - 1)), reserved1(0), + activation_clip_range(static_cast(_activation_clip_range) & ((1U << 3) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_activation_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_function(0), reserved1(0), + activation_clip_range(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_activation_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_activation_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_function get_activation_function() const + { + return static_cast(activation_function); + } + CONSTEXPR npu_set_activation_t &set_activation_function(NPU_NAMESPACE::activation_function value) + { + activation_function = static_cast(value) & ((1U << 5) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_clip_range get_activation_clip_range() const + { + return static_cast(activation_clip_range); + } + CONSTEXPR npu_set_activation_t &set_activation_clip_range(NPU_NAMESPACE::activation_clip_range value) + { + activation_clip_range = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_function", + (activation_function < (sizeof(activation_function_str) / sizeof(activation_function_str[0])) ? + activation_function_str[activation_function] : + "****"))); + fields.push_back(std::make_pair( + "activation_clip_range", + (activation_clip_range < (sizeof(activation_clip_range_str) / sizeof(activation_clip_range_str[0])) ? + activation_clip_range_str[activation_clip_range] : + "****"))); + } +#endif +#endif + }; + // Lower bound clip + struct npu_set_activation_min_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t clip_boundary : 16; // Clip boundary for OFM activations +#ifdef __cplusplus + public: + npu_set_activation_min_t(uint32_t _clip_boundary) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + clip_boundary(_clip_boundary & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_activation_min_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_activation_min_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_activation_min_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_clip_boundary() const + { + return static_cast(clip_boundary); + } + CONSTEXPR npu_set_activation_min_t &set_clip_boundary(uint32_t value) + { + clip_boundary = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("clip_boundary", std::to_string(clip_boundary))); + } +#endif +#endif + }; + // Upper bound clip + struct npu_set_activation_max_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t clip_boundary : 16; // Clip boundary for OFM activations +#ifdef __cplusplus + public: + npu_set_activation_max_t(uint32_t _clip_boundary) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + clip_boundary(_clip_boundary & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_activation_max_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_activation_max_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_activation_max_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_clip_boundary() const + { + return static_cast(clip_boundary); + } + CONSTEXPR npu_set_activation_max_t &set_clip_boundary(uint32_t value) + { + clip_boundary = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("clip_boundary", std::to_string(clip_boundary))); + } +#endif +#endif + }; + // Index n for weight stream access + struct npu_set_weight_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for weight stream access + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_set_weight_region_t(uint32_t _region) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_weight_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_weight_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_weight_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_weight_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + } +#endif +#endif + }; + // Index n for scale stream access + struct npu_set_scale_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for scale stream access + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_set_scale_region_t(uint32_t _region) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_scale_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_scale_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_scale_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_scale_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + } +#endif +#endif + }; + // Start of ACC0,ACC1 buffers + struct npu_set_ab_start_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t ab_start : 6; // Start of ACC0,ACC1 buffers in the SHRAM in KB units. Multiple of 2 + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ab_start_t(uint32_t _ab_start) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(_ab_start & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ab_start_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ab_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ab_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_ab_start() const + { + return static_cast(ab_start); + } + CONSTEXPR npu_set_ab_start_t &set_ab_start(uint32_t value) + { + ab_start = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("ab_start", std::to_string(ab_start))); + } +#endif +#endif + }; + // Block number of blocks dependency + struct npu_set_blockdep_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t blockdep : 2; // Block number of blocks dependency between kernel operations + uint32_t reserved1 : 14; +#ifdef __cplusplus + public: + npu_set_blockdep_t(uint32_t _blockdep) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(_blockdep & ((1U << 2) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_blockdep_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_blockdep_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_blockdep_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_blockdep() const + { + return static_cast(blockdep); + } + CONSTEXPR npu_set_blockdep_t &set_blockdep(uint32_t value) + { + blockdep = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("blockdep", std::to_string(blockdep))); + } +#endif +#endif + }; + // DMA0 source region + struct npu_set_dma0_src_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Region number + uint32_t reserved1 : 5; + uint32_t region_mode : 1; // Region mode + uint32_t stride_mode : 2; // Stride mode + uint32_t reserved2 : 5; +#ifdef __cplusplus + public: + npu_set_dma0_src_region_t(uint32_t _region, + NPU_NAMESPACE::dma_region_mode _region_mode, + NPU_NAMESPACE::dma_stride_mode _stride_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + region(_region & ((1U << 3) - 1)), reserved1(0), + region_mode(static_cast(_region_mode) & ((1U << 1) - 1)), + stride_mode(static_cast(_stride_mode) & ((1U << 2) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_dma0_src_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0), + stride_mode(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_src_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_src_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_dma0_src_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode() const + { + return static_cast(region_mode); + } + CONSTEXPR npu_set_dma0_src_region_t &set_region_mode(NPU_NAMESPACE::dma_region_mode value) + { + region_mode = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode() const + { + return static_cast(stride_mode); + } + CONSTEXPR npu_set_dma0_src_region_t &set_stride_mode(NPU_NAMESPACE::dma_stride_mode value) + { + stride_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "region_mode", + (region_mode < (sizeof(dma_region_mode_str) / sizeof(dma_region_mode_str[0])) ? + dma_region_mode_str[region_mode] : + "****"))); + fields.push_back(std::make_pair( + "stride_mode", + (stride_mode < (sizeof(dma_stride_mode_str) / sizeof(dma_stride_mode_str[0])) ? + dma_stride_mode_str[stride_mode] : + "****"))); + } +#endif +#endif + }; + // DMA0 destination region + struct npu_set_dma0_dst_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Region number if region_mode is region_mode_external. Else core mask to write to (bit k + // set for core k=0,1) + uint32_t reserved1 : 5; + uint32_t region_mode : 1; // Region mode + uint32_t stride_mode : 2; // Stride mode + uint32_t reserved2 : 5; +#ifdef __cplusplus + public: + npu_set_dma0_dst_region_t(uint32_t _region, + NPU_NAMESPACE::dma_region_mode _region_mode, + NPU_NAMESPACE::dma_stride_mode _stride_mode) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + region(_region & ((1U << 3) - 1)), reserved1(0), + region_mode(static_cast(_region_mode) & ((1U << 1) - 1)), + stride_mode(static_cast(_stride_mode) & ((1U << 2) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_dma0_dst_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0), + stride_mode(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode() const + { + return static_cast(region_mode); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_region_mode(NPU_NAMESPACE::dma_region_mode value) + { + region_mode = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode() const + { + return static_cast(stride_mode); + } + CONSTEXPR npu_set_dma0_dst_region_t &set_stride_mode(NPU_NAMESPACE::dma_stride_mode value) + { + stride_mode = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + fields.push_back(std::make_pair( + "region_mode", + (region_mode < (sizeof(dma_region_mode_str) / sizeof(dma_region_mode_str[0])) ? + dma_region_mode_str[region_mode] : + "****"))); + fields.push_back(std::make_pair( + "stride_mode", + (stride_mode < (sizeof(dma_stride_mode_str) / sizeof(dma_stride_mode_str[0])) ? + dma_stride_mode_str[stride_mode] : + "****"))); + } +#endif +#endif + }; + // Size of second dimension for 2D/3D transfers + struct npu_set_dma0_size0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t size : 16; // Size of second dimension for 2D/3D transfers +#ifdef __cplusplus + public: + npu_set_dma0_size0_t(uint32_t _size) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(_size & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_dma0_size0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_size0_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_size0_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_size() const + { + return static_cast(size); + } + CONSTEXPR npu_set_dma0_size0_t &set_size(uint32_t value) + { + size = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("size", std::to_string(size))); + } +#endif +#endif + }; + // Size of third dimension for 3D transfers + struct npu_set_dma0_size1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t size : 16; // Size of third dimension for 3D transfers +#ifdef __cplusplus + public: + npu_set_dma0_size1_t(uint32_t _size) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(_size & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_dma0_size1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_dma0_size1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_dma0_size1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_size() const + { + return static_cast(size); + } + CONSTEXPR npu_set_dma0_size1_t &set_size(uint32_t value) + { + size = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("size", std::to_string(size))); + } +#endif +#endif + }; + // IFM2 broadcast configuration + struct npu_set_ifm2_broadcast_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t + broadcast_h : 1; // Broadcast H dimension (if set then any accesses to IFM2 sets y=0 and IFM2 height=1) + uint32_t broadcast_w : 1; // Broadcast W dimension (if set then any accesses to IFM2 sets x=0 and IFM2 width=1) + uint32_t broadcast_c : 1; // Broadcast C dimension (if set then any accesses to IFM2 sets c=0 and IFM2 depth=1) + uint32_t reserved1 : 3; + uint32_t operand_order : 1; // Operand order + uint32_t broadcast_constant : 1; // Broadcast constant given by NPU_SET_IFM2_SCALAR and so ignore BH, BW and BC + uint32_t reserved2 : 8; +#ifdef __cplusplus + public: + npu_set_ifm2_broadcast_t(NPU_NAMESPACE::broadcast_mode _broadcast_h, + NPU_NAMESPACE::broadcast_mode _broadcast_w, + NPU_NAMESPACE::broadcast_mode _broadcast_c, + NPU_NAMESPACE::ifm2_operand_order _operand_order, + NPU_NAMESPACE::broadcast_mode _broadcast_constant) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + broadcast_h(static_cast(_broadcast_h) & ((1U << 1) - 1)), + broadcast_w(static_cast(_broadcast_w) & ((1U << 1) - 1)), + broadcast_c(static_cast(_broadcast_c) & ((1U << 1) - 1)), reserved1(0), + operand_order(static_cast(_operand_order) & ((1U << 1) - 1)), + broadcast_constant(static_cast(_broadcast_constant) & ((1U << 1) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_ifm2_broadcast_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), broadcast_h(0), broadcast_w(0), + broadcast_c(0), reserved1(0), operand_order(0), broadcast_constant(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_h() const + { + return static_cast(broadcast_h); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_h(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_h = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_w() const + { + return static_cast(broadcast_w); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_w(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_w = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_c() const + { + return static_cast(broadcast_c); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_c(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_c = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::ifm2_operand_order get_operand_order() const + { + return static_cast(operand_order); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_operand_order(NPU_NAMESPACE::ifm2_operand_order value) + { + operand_order = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_constant() const + { + return static_cast(broadcast_constant); + } + CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_constant(NPU_NAMESPACE::broadcast_mode value) + { + broadcast_constant = static_cast(value) & ((1U << 1) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "broadcast_h", + (broadcast_h < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_h] : + "****"))); + fields.push_back(std::make_pair( + "broadcast_w", + (broadcast_w < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_w] : + "****"))); + fields.push_back(std::make_pair( + "broadcast_c", + (broadcast_c < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_c] : + "****"))); + fields.push_back(std::make_pair( + "operand_order", + (operand_order < (sizeof(ifm2_operand_order_str) / sizeof(ifm2_operand_order_str[0])) ? + ifm2_operand_order_str[operand_order] : + "****"))); + fields.push_back(std::make_pair( + "broadcast_constant", + (broadcast_constant < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ? + broadcast_mode_str[broadcast_constant] : + "****"))); + } +#endif +#endif + }; + // IFM2 scalar value + struct npu_set_ifm2_scalar_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t scalar : 16; // int16 or uint16 depending on ifm2_precision.type +#ifdef __cplusplus + public: + npu_set_ifm2_scalar_t(uint32_t _scalar) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), scalar(_scalar & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_scalar_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), scalar(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_scalar_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_scalar_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_scalar() const + { + return static_cast(scalar); + } + CONSTEXPR npu_set_ifm2_scalar_t &set_scalar(uint32_t value) + { + scalar = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("scalar", std::to_string(scalar))); + } +#endif +#endif + }; + // IFM2 Precision + struct npu_set_ifm2_precision_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t activation_type : 1; // IFM type - MUST MATCH IFM + uint32_t reserved1 : 1; + uint32_t activation_precision : 2; // IFM precision - MUST MATCH IFM + uint32_t reserved2 : 2; + uint32_t activation_format : 2; // IFM format + uint32_t reserved3 : 8; +#ifdef __cplusplus + public: + npu_set_ifm2_precision_t(NPU_NAMESPACE::activation_type _activation_type, + NPU_NAMESPACE::activation_precision _activation_precision, + NPU_NAMESPACE::activation_format _activation_format) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION)), + reserved0(0), control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + activation_type(static_cast(_activation_type) & ((1U << 1) - 1)), reserved1(0), + activation_precision(static_cast(_activation_precision) & ((1U << 2) - 1)), reserved2(0), + activation_format(static_cast(_activation_format) & ((1U << 2) - 1)), reserved3(0) + { + } + CONSTEXPR npu_set_ifm2_precision_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), reserved1(0), + activation_precision(0), reserved2(0), activation_format(0), reserved3(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const + { + return static_cast(activation_type); + } + CONSTEXPR npu_set_ifm2_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value) + { + activation_type = static_cast(value) & ((1U << 1) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const + { + return static_cast(activation_precision); + } + CONSTEXPR npu_set_ifm2_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value) + { + activation_precision = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const + { + return static_cast(activation_format); + } + CONSTEXPR npu_set_ifm2_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value) + { + activation_format = static_cast(value) & ((1U << 2) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair( + "activation_type", + (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ? + activation_type_str[activation_type] : + "****"))); + fields.push_back(std::make_pair( + "activation_precision", + (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ? + activation_precision_str[activation_precision] : + "****"))); + fields.push_back(std::make_pair( + "activation_format", + (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ? + activation_format_str[activation_format] : + "****"))); + } +#endif +#endif + }; + // IFM2 zero point + struct npu_set_ifm2_zero_point_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t zero_point : 16; // Zero point offset +#ifdef __cplusplus + public: + npu_set_ifm2_zero_point_t(uint32_t _zero_point) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), + zero_point(_zero_point & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_zero_point_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_zero_point() const + { + return static_cast(zero_point); + } + CONSTEXPR npu_set_ifm2_zero_point_t &set_zero_point(uint32_t value) + { + zero_point = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("zero_point", std::to_string(zero_point))); + } +#endif +#endif + }; + // IFM2 Tile 0 and tile 2 width + struct npu_set_ifm2_width0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t width_m1 : 16; // IFM2 Tile 0 and tile 2 width +#ifdef __cplusplus + public: + npu_set_ifm2_width0_m1_t(uint32_t _width_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_width0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_width_m1() const + { + return static_cast(width_m1); + } + CONSTEXPR npu_set_ifm2_width0_m1_t &set_width_m1(uint32_t value) + { + width_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("width_m1", std::to_string(width_m1))); + } +#endif +#endif + }; + // IFM2 Tile 0 height + struct npu_set_ifm2_height0_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM2 Tile 0 height +#ifdef __cplusplus + public: + npu_set_ifm2_height0_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_height0_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm2_height0_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // IFM2 Tile 1 height + struct npu_set_ifm2_height1_m1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t height_m1 : 16; // IFM2 Tile 1 height +#ifdef __cplusplus + public: + npu_set_ifm2_height1_m1_t(uint32_t _height_m1) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1)) + { + } + CONSTEXPR npu_set_ifm2_height1_m1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_height_m1() const + { + return static_cast(height_m1); + } + CONSTEXPR npu_set_ifm2_height1_m1_t &set_height_m1(uint32_t value) + { + height_m1 = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("height_m1", std::to_string(height_m1))); + } +#endif +#endif + }; + // Start of IB0,IB1 buffers for IFM2 + struct npu_set_ifm2_ib_start_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t ib_start : 6; // Start of IB0,IB1 buffers for IFM2 in the SHRAM in KB units. Multiple of 2 + uint32_t reserved1 : 10; +#ifdef __cplusplus + public: + npu_set_ifm2_ib_start_t(uint32_t _ib_start) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_start(_ib_start & ((1U << 6) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ifm2_ib_start_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_start(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_ib_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_ib_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_ib_start() const + { + return static_cast(ib_start); + } + CONSTEXPR npu_set_ifm2_ib_start_t &set_ib_start(uint32_t value) + { + ib_start = static_cast(value) & ((1U << 6) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("ib_start", std::to_string(ib_start))); + } +#endif +#endif + }; + // Index n for IFM2 access + struct npu_set_ifm2_region_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t region : 3; // Index n for IFM2 access + uint32_t reserved1 : 13; +#ifdef __cplusplus + public: + npu_set_ifm2_region_t(uint32_t _region) : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)), + reserved1(0) + { + } + CONSTEXPR npu_set_ifm2_region_t() : + opcode(static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION) && + control == static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL); + } + operator uint32_t() + { + uint32_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ifm2_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ifm2_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_region() const + { + return static_cast(region); + } + CONSTEXPR npu_set_ifm2_region_t &set_region(uint32_t value) + { + region = static_cast(value) & ((1U << 3) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("region", std::to_string(region))); + } +#endif +#endif + }; + // IFM Tile 0 address + struct npu_set_ifm_base0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base0_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm_base0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm_base0_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM Tile 1 address + struct npu_set_ifm_base1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base1_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm_base1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm_base1_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM Tile 2 address + struct npu_set_ifm_base2_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base2_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm_base2_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm_base2_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM Tile 3 address + struct npu_set_ifm_base3_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_base3_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm_base3_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm_base3_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM byte stride between horizontal values + struct npu_set_ifm_stride_x_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_stride_x_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm_stride_x_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm_stride_x_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM byte stride between vertical values + struct npu_set_ifm_stride_y_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_stride_y_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm_stride_y_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm_stride_y_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM byte stride between channel blocks (of 16 bytes each block) + struct npu_set_ifm_stride_c_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm_stride_c_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm_stride_c_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm_stride_c_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 0 address + struct npu_set_ofm_base0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base0_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ofm_base0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ofm_base0_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 1 address + struct npu_set_ofm_base1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base1_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ofm_base1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ofm_base1_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 2 address + struct npu_set_ofm_base2_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base2_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ofm_base2_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ofm_base2_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM Tile 3 address + struct npu_set_ofm_base3_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_base3_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ofm_base3_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ofm_base3_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM byte stride between horizontal values + struct npu_set_ofm_stride_x_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_stride_x_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ofm_stride_x_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ofm_stride_x_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM byte stride between vertical values + struct npu_set_ofm_stride_y_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_stride_y_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ofm_stride_y_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ofm_stride_y_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // OFM byte stride between channel blocks (of 16 bytes each block) + struct npu_set_ofm_stride_c_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ofm_stride_c_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ofm_stride_c_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ofm_stride_c_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Weight stream byte offset in WEIGHT_REGION + struct npu_set_weight_base_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_weight_base_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_weight_base_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_weight_base_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Weight stream byte length + struct npu_set_weight_length_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t length : 32; // Weight stream byte length +#ifdef __cplusplus + public: + npu_set_weight_length_t(uint32_t _length) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(_length) + { + } + CONSTEXPR npu_set_weight_length_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_weight_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_weight_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_length() const + { + return static_cast(length); + } + CONSTEXPR npu_set_weight_length_t &set_length(uint32_t value) + { + length = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("length", std::to_string(length))); + } +#endif +#endif + }; + // Scale and bias stream input byte offset from SCALE_REGION + struct npu_set_scale_base_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_scale_base_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_scale_base_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_scale_base_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Scale and bias stream input byte length + struct npu_set_scale_length_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t length : 20; // Scale and bias stream byte length + uint32_t reserved2 : 12; +#ifdef __cplusplus + public: + npu_set_scale_length_t(uint32_t _length) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), + length(_length & ((1U << 20) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_scale_length_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_scale_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_scale_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_length() const + { + return static_cast(length); + } + CONSTEXPR npu_set_scale_length_t &set_length(uint32_t value) + { + length = value & ((1U << 20) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("length", std::to_string(length))); + } +#endif +#endif + }; + // OFM scale + struct npu_set_ofm_scale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t shift : 6; // Shift + uint32_t reserved1 : 10; + uint32_t scale : 32; // Scale. Not applied for 32-bit operations +#ifdef __cplusplus + public: + npu_set_ofm_scale_t(uint32_t _shift, uint32_t _scale) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(_shift & ((1U << 6) - 1)), + reserved1(0), scale(_scale) + { + } + CONSTEXPR npu_set_ofm_scale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(0), reserved1(0), scale(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_ofm_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_ofm_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_shift() const + { + return static_cast(shift); + } + CONSTEXPR npu_set_ofm_scale_t &set_shift(uint32_t value) + { + shift = static_cast(value) & ((1U << 6) - 1); + return *this; + } + CONSTEXPR uint32_t get_scale() const + { + return static_cast(scale); + } + CONSTEXPR npu_set_ofm_scale_t &set_scale(uint32_t value) + { + scale = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("shift", std::to_string(shift))); + fields.push_back(std::make_pair("scale", std::to_string(scale))); + } +#endif +#endif + }; + // Input operand A scale + struct npu_set_opa_scale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t shift : 6; // Shift. Ignored if IFM scale mode is 0 + uint32_t reserved1 : 10; + uint32_t scale : 32; // Scale. 16-bit if IFM scale mode is 0 +#ifdef __cplusplus + public: + npu_set_opa_scale_t(uint32_t _shift, uint32_t _scale) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(_shift & ((1U << 6) - 1)), + reserved1(0), scale(_scale) + { + } + CONSTEXPR npu_set_opa_scale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(0), reserved1(0), scale(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_opa_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_opa_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_shift() const + { + return static_cast(shift); + } + CONSTEXPR npu_set_opa_scale_t &set_shift(uint32_t value) + { + shift = static_cast(value) & ((1U << 6) - 1); + return *this; + } + CONSTEXPR uint32_t get_scale() const + { + return static_cast(scale); + } + CONSTEXPR npu_set_opa_scale_t &set_scale(uint32_t value) + { + scale = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("shift", std::to_string(shift))); + fields.push_back(std::make_pair("scale", std::to_string(scale))); + } +#endif +#endif + }; + // Input operand B scale + struct npu_set_opb_scale_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t scale : 16; // Scale. Not used if IFM scale mode is 1 or 2 + uint32_t reserved2 : 16; +#ifdef __cplusplus + public: + npu_set_opb_scale_t(uint32_t _scale) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), + scale(_scale & ((1U << 16) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_opb_scale_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), scale(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_opb_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_opb_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_scale() const + { + return static_cast(scale); + } + CONSTEXPR npu_set_opb_scale_t &set_scale(uint32_t value) + { + scale = static_cast(value) & ((1U << 16) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("scale", std::to_string(scale))); + } +#endif +#endif + }; + // DMA user channel 0 source byte offset from DMA0_SRC_REGION + struct npu_set_dma0_src_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_src_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_dma0_src_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_dma0_src_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // DMA user channel 0 destination byte offset from DMA0_DST_REGION + struct npu_set_dma0_dst_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_dst_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_dma0_dst_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_dma0_dst_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // DMA user channel 0 transfer length in bytes for each 1D transfer + struct npu_set_dma0_len_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_len_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_dma0_len_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_dma0_len_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // byte distance to skip after each inner (1D) transfer (2D/3D mode) (any alignment) + struct npu_set_dma0_skip0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_skip0_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_dma0_skip0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_dma0_skip0_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // byte distance to skip after each 2D transfer (3D mode) (any alignment) + struct npu_set_dma0_skip1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_dma0_skip1_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_dma0_skip1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_dma0_skip1_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 0 address + struct npu_set_ifm2_base0_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base0_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm2_base0_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm2_base0_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 1 address + struct npu_set_ifm2_base1_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base1_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm2_base1_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm2_base1_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 2 address + struct npu_set_ifm2_base2_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base2_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm2_base2_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm2_base2_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 Tile 3 address + struct npu_set_ifm2_base3_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_base3_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm2_base3_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm2_base3_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 byte stride between horizontal values + struct npu_set_ifm2_stride_x_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_stride_x_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm2_stride_x_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm2_stride_x_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 byte stride between vertical values + struct npu_set_ifm2_stride_y_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_stride_y_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm2_stride_y_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm2_stride_y_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // IFM2 byte stride between channel blocks (of 16 bytes each block) + struct npu_set_ifm2_stride_c_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_ifm2_stride_c_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_ifm2_stride_c_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_ifm2_stride_c_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Weight stream byte offset in WEIGHT_REGION for core 1 + struct npu_set_weight1_base_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_weight1_base_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_weight1_base_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_weight1_base_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Weight stream byte length for core 1 + struct npu_set_weight1_length_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t length : 32; // Weight stream byte length +#ifdef __cplusplus + public: + npu_set_weight1_length_t(uint32_t _length) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(_length) + { + } + CONSTEXPR npu_set_weight1_length_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH) && + control >= 1 && control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_weight1_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_weight1_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_length() const + { + return static_cast(length); + } + CONSTEXPR npu_set_weight1_length_t &set_length(uint32_t value) + { + length = value; + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("length", std::to_string(length))); + } +#endif +#endif + }; + // Scale and bias stream input byte offset from SCALE_REGION for core 1 + struct npu_set_scale1_base_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t addr_hi : 8; // address extension + uint32_t reserved1 : 8; + uint32_t addr_lo : 32; // address offset +#ifdef __cplusplus + public: + npu_set_scale1_base_t(uint64_t _addr) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), + addr_hi(static_cast((_addr >> 32) & std::numeric_limits::max())), reserved1(0), + addr_lo(static_cast((_addr)&std::numeric_limits::max())) + { + } + CONSTEXPR npu_set_scale1_base_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR uint64_t get_addr() const + { + return (static_cast(addr_hi) << 32) | addr_lo; + } + CONSTEXPR npu_set_scale1_base_t &set_addr(uint64_t value) + { + addr_lo = static_cast((value)&std::numeric_limits::max()); + addr_hi = static_cast((value >> 32) & std::numeric_limits::max()); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + std::stringstream saddr; + saddr << std::hex << "0x" << get_addr(); + fields.push_back(std::make_pair("addr", saddr.str())); + } +#endif +#endif + }; + // Scale and bias stream input byte length for core 1 + struct npu_set_scale1_length_t + { +#ifdef __cplusplus + private: +#endif + uint32_t opcode : 10; // opcode + uint32_t reserved0 : 4; + uint32_t control : 2; // control + uint32_t reserved1 : 16; + uint32_t length : 20; // Scale and bias stream byte length + uint32_t reserved2 : 12; +#ifdef __cplusplus + public: + npu_set_scale1_length_t(uint32_t _length) : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), + length(_length & ((1U << 20) - 1)), reserved2(0) + { + } + CONSTEXPR npu_set_scale1_length_t() : + opcode(static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH)), reserved0(0), + control(static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0), reserved2(0) + { + } + CONSTEXPR bool valid() const + { + return opcode == static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH) && control >= 1 && + control <= 2; + } + CONSTEXPR void init() + { + opcode = static_cast(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH); + control = static_cast(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL); + } + operator uint64_t() + { + uint64_t word; + std::memcpy(&word, this, sizeof(word)); + return word; + } + CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const + { + return static_cast(opcode); + } + CONSTEXPR npu_set_scale1_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value) + { + opcode = static_cast(value) & ((1U << 10) - 1); + return *this; + } + CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const + { + return static_cast(control); + } + CONSTEXPR npu_set_scale1_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value) + { + control = static_cast(value) & ((1U << 2) - 1); + return *this; + } + CONSTEXPR uint32_t get_length() const + { + return static_cast(length); + } + CONSTEXPR npu_set_scale1_length_t &set_length(uint32_t value) + { + length = value & ((1U << 20) - 1); + return *this; + } +#ifdef NPU_DISASSEMBLE + void disassemble(std::vector> &fields) const + { + fields.push_back(std::make_pair("length", std::to_string(length))); + } +#endif +#endif + }; +#ifdef __cplusplus +}; +#endif +#define NPU_OP_STRUCTS \ + NPU_OP_(stop) \ + NPU_OP_(irq) \ + NPU_OP_(conv) \ + NPU_OP_(depthwise) \ + NPU_OP_(pool) \ + NPU_OP_(elementwise) \ + NPU_OP_(dma_start) \ + NPU_OP_(dma_wait) \ + NPU_OP_(kernel_wait) \ + NPU_OP_(pmu_mask) + +#define NPU_SET_STRUCTS \ + NPU_SET_(ifm_pad_top) \ + NPU_SET_(ifm_pad_left) \ + NPU_SET_(ifm_pad_right) \ + NPU_SET_(ifm_pad_bottom) \ + NPU_SET_(ifm_depth_m1) \ + NPU_SET_(ifm_precision) \ + NPU_SET_(ifm_upscale) \ + NPU_SET_(ifm_zero_point) \ + NPU_SET_(ifm_width0_m1) \ + NPU_SET_(ifm_height0_m1) \ + NPU_SET_(ifm_height1_m1) \ + NPU_SET_(ifm_ib_end) \ + NPU_SET_(ifm_region) \ + NPU_SET_(ofm_width_m1) \ + NPU_SET_(ofm_height_m1) \ + NPU_SET_(ofm_depth_m1) \ + NPU_SET_(ofm_precision) \ + NPU_SET_(ofm_blk_width_m1) \ + NPU_SET_(ofm_blk_height_m1) \ + NPU_SET_(ofm_blk_depth_m1) \ + NPU_SET_(ofm_zero_point) \ + NPU_SET_(ofm_width0_m1) \ + NPU_SET_(ofm_height0_m1) \ + NPU_SET_(ofm_height1_m1) \ + NPU_SET_(ofm_region) \ + NPU_SET_(kernel_width_m1) \ + NPU_SET_(kernel_height_m1) \ + NPU_SET_(kernel_stride) \ + NPU_SET_(parallel_mode) \ + NPU_SET_(acc_format) \ + NPU_SET_(activation) \ + NPU_SET_(activation_min) \ + NPU_SET_(activation_max) \ + NPU_SET_(weight_region) \ + NPU_SET_(scale_region) \ + NPU_SET_(ab_start) \ + NPU_SET_(blockdep) \ + NPU_SET_(dma0_src_region) \ + NPU_SET_(dma0_dst_region) \ + NPU_SET_(dma0_size0) \ + NPU_SET_(dma0_size1) \ + NPU_SET_(ifm2_broadcast) \ + NPU_SET_(ifm2_scalar) \ + NPU_SET_(ifm2_precision) \ + NPU_SET_(ifm2_zero_point) \ + NPU_SET_(ifm2_width0_m1) \ + NPU_SET_(ifm2_height0_m1) \ + NPU_SET_(ifm2_height1_m1) \ + NPU_SET_(ifm2_ib_start) \ + NPU_SET_(ifm2_region) \ + NPU_SET_(ifm_base0) \ + NPU_SET_(ifm_base1) \ + NPU_SET_(ifm_base2) \ + NPU_SET_(ifm_base3) \ + NPU_SET_(ifm_stride_x) \ + NPU_SET_(ifm_stride_y) \ + NPU_SET_(ifm_stride_c) \ + NPU_SET_(ofm_base0) \ + NPU_SET_(ofm_base1) \ + NPU_SET_(ofm_base2) \ + NPU_SET_(ofm_base3) \ + NPU_SET_(ofm_stride_x) \ + NPU_SET_(ofm_stride_y) \ + NPU_SET_(ofm_stride_c) \ + NPU_SET_(weight_base) \ + NPU_SET_(weight_length) \ + NPU_SET_(scale_base) \ + NPU_SET_(scale_length) \ + NPU_SET_(ofm_scale) \ + NPU_SET_(opa_scale) \ + NPU_SET_(opb_scale) \ + NPU_SET_(dma0_src) \ + NPU_SET_(dma0_dst) \ + NPU_SET_(dma0_len) \ + NPU_SET_(dma0_skip0) \ + NPU_SET_(dma0_skip1) \ + NPU_SET_(ifm2_base0) \ + NPU_SET_(ifm2_base1) \ + NPU_SET_(ifm2_base2) \ + NPU_SET_(ifm2_base3) \ + NPU_SET_(ifm2_stride_x) \ + NPU_SET_(ifm2_stride_y) \ + NPU_SET_(ifm2_stride_c) \ + NPU_SET_(weight1_base) \ + NPU_SET_(weight1_length) \ + NPU_SET_(scale1_base) \ + NPU_SET_(scale1_length) + +#define EXPAND_ACC_FORMAT(FUNC, SEP) FUNC(acc_format, I32) SEP FUNC(acc_format, I40) SEP FUNC(acc_format, F16) + +#define EXPAND_ACTIVATION_CLIP_RANGE(FUNC, SEP) \ + FUNC(activation_clip_range, OFM_PRECISION) \ + SEP FUNC(activation_clip_range, FORCE_UINT8) SEP FUNC(activation_clip_range, FORCE_INT8) \ + SEP FUNC(activation_clip_range, FORCE_INT16) + +#define EXPAND_ACTIVATION_FORMAT(FUNC, SEP) FUNC(activation_format, NHWC) SEP FUNC(activation_format, NHCWB16) + +#define EXPAND_ACTIVATION_FUNCTION(FUNC, SEP) \ + FUNC(activation_function, RELU) \ + SEP FUNC(activation_function, TANH) SEP FUNC(activation_function, SIGMOID) SEP FUNC(activation_function, TABLE_0) \ + SEP FUNC(activation_function, TABLE_1) SEP FUNC(activation_function, TABLE_2) \ + SEP FUNC(activation_function, TABLE_3) SEP FUNC(activation_function, TABLE_4) \ + SEP FUNC(activation_function, TABLE_5) SEP FUNC(activation_function, TABLE_6) \ + SEP FUNC(activation_function, TABLE_7) + +#define EXPAND_ACTIVATION_PRECISION(FUNC, SEP) \ + FUNC(activation_precision, B8) \ + SEP FUNC(activation_precision, B16) SEP FUNC(activation_precision, B32) SEP FUNC(activation_precision, B64) + +#define EXPAND_ACTIVATION_TYPE(FUNC, SEP) FUNC(activation_type, UNSIGNED) SEP FUNC(activation_type, SIGNED) + +#define EXPAND_AXI_MEM_ENCODING(FUNC, SEP) \ + FUNC(axi_mem_encoding, DEVICE_NON_BUFFERABLE) \ + SEP FUNC(axi_mem_encoding, DEVICE_BUFFERABLE) SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_NON_BUFFERABLE) \ + SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_BUFFERABLE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_NO_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_WRITE_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_AND_WRITE_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_NO_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_WRITE_ALLOCATE) \ + SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_AND_WRITE_ALLOCATE) + +#define EXPAND_BROADCAST_MODE(FUNC, SEP) FUNC(broadcast_mode, DISABLE) SEP FUNC(broadcast_mode, ENABLE) + +#define EXPAND_CMD0_OPCODE(FUNC, SEP) \ + FUNC(cmd0_opcode, NPU_OP_STOP) \ + SEP FUNC(cmd0_opcode, NPU_OP_IRQ) SEP FUNC(cmd0_opcode, NPU_OP_CONV) SEP FUNC( \ + cmd0_opcode, NPU_OP_DEPTHWISE) SEP FUNC(cmd0_opcode, NPU_OP_POOL) SEP FUNC(cmd0_opcode, NPU_OP_ELEMENTWISE) \ + SEP FUNC(cmd0_opcode, NPU_OP_DMA_START) SEP FUNC(cmd0_opcode, NPU_OP_DMA_WAIT) SEP FUNC( \ + cmd0_opcode, NPU_OP_KERNEL_WAIT) SEP FUNC(cmd0_opcode, NPU_OP_PMU_MASK) SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM_PAD_TOP) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_LEFT) SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_RIGHT) SEP FUNC( \ + cmd0_opcode, NPU_SET_IFM_PAD_BOTTOM) SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM_DEPTH_M1) SEP FUNC(cmd0_opcode, \ + NPU_SET_IFM_PRECISION) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM_UPSCALE) SEP FUNC(cmd0_opcode, NPU_SET_IFM_ZERO_POINT) SEP FUNC( \ + cmd0_opcode, NPU_SET_IFM_WIDTH0_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT0_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_IB_END) SEP FUNC( \ + cmd0_opcode, NPU_SET_IFM_REGION) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_DEPTH_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_PRECISION) SEP FUNC( \ + cmd0_opcode, NPU_SET_OFM_BLK_WIDTH_M1) SEP FUNC(cmd0_opcode, \ + NPU_SET_OFM_BLK_HEIGHT_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_BLK_DEPTH_M1) SEP FUNC( \ + cmd0_opcode, NPU_SET_OFM_ZERO_POINT) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH0_M1) \ + SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT0_M1) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_OFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_REGION) \ + SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_WIDTH_M1) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_KERNEL_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_STRIDE) \ + SEP FUNC(cmd0_opcode, NPU_SET_PARALLEL_MODE) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_ACC_FORMAT) SEP FUNC(cmd0_opcode, NPU_SET_ACTIVATION) \ + SEP FUNC(cmd0_opcode, \ + NPU_SET_ACTIVATION_MIN) SEP FUNC(cmd0_opcode, \ + NPU_SET_ACTIVATION_MAX) \ + SEP FUNC(cmd0_opcode, NPU_SET_WEIGHT_REGION) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_SCALE_REGION) SEP FUNC(cmd0_opcode, NPU_SET_AB_START) \ + SEP FUNC(cmd0_opcode, NPU_SET_BLOCKDEP) \ + SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SRC_REGION) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_DMA0_DST_REGION) SEP FUNC(cmd0_opcode, \ + NPU_SET_DMA0_SIZE0) \ + SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SIZE1) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_IFM2_BROADCAST) SEP \ + FUNC(cmd0_opcode, NPU_SET_IFM2_SCALAR) SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_IFM2_PRECISION) SEP \ + FUNC(cmd0_opcode, NPU_SET_IFM2_ZERO_POINT) SEP \ + FUNC(cmd0_opcode, \ + NPU_SET_IFM2_WIDTH0_M1) SEP \ + FUNC(cmd0_opcode, \ + NPU_SET_IFM2_HEIGHT0_M1) SEP \ + FUNC(cmd0_opcode, \ + NPU_SET_IFM2_HEIGHT1_M1) \ + SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_IFM2_IB_START) \ + SEP FUNC( \ + cmd0_opcode, \ + NPU_SET_IFM2_REGION) + +#define EXPAND_CMD1_OPCODE(FUNC, SEP) \ + FUNC(cmd1_opcode, NPU_SET_IFM_BASE0) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE1) SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE2) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE3) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_X) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_Y) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_C) SEP FUNC( \ + cmd1_opcode, NPU_SET_OFM_BASE0) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE1) \ + SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE2) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE3) SEP FUNC( \ + cmd1_opcode, NPU_SET_OFM_STRIDE_X) SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_Y) \ + SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_C) SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT_BASE) SEP FUNC( \ + cmd1_opcode, NPU_SET_WEIGHT_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_SCALE_BASE) \ + SEP FUNC(cmd1_opcode, NPU_SET_SCALE_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_OFM_SCALE) \ + SEP FUNC(cmd1_opcode, NPU_SET_OPA_SCALE) SEP FUNC(cmd1_opcode, NPU_SET_OPB_SCALE) \ + SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SRC) SEP FUNC(cmd1_opcode, NPU_SET_DMA0_DST) \ + SEP FUNC(cmd1_opcode, NPU_SET_DMA0_LEN) SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SKIP0) \ + SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SKIP1) SEP FUNC( \ + cmd1_opcode, NPU_SET_IFM2_BASE0) SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE1) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE2) SEP FUNC(cmd1_opcode, \ + NPU_SET_IFM2_BASE3) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_X) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_Y) \ + SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_C) \ + SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT1_BASE) \ + SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT1_LENGTH) \ + SEP FUNC(cmd1_opcode, NPU_SET_SCALE1_BASE) \ + SEP FUNC(cmd1_opcode, NPU_SET_SCALE1_LENGTH) + +#define EXPAND_CMD_CTRL(FUNC, SEP) FUNC(cmd_ctrl, CMD0_CTRL) SEP FUNC(cmd_ctrl, CMD1_CTRL) + +#define EXPAND_CUSTOM_DMA(FUNC, SEP) FUNC(custom_dma, NOT_IMPLEMENTED) SEP FUNC(custom_dma, IMPLEMENTED) + +#define EXPAND_DMA_FAULT_SRC(FUNC, SEP) FUNC(dma_fault_src, AXI_M0) SEP FUNC(dma_fault_src, AXI_M1) + +#define EXPAND_DMA_REGION_MODE(FUNC, SEP) FUNC(dma_region_mode, EXTERNAL) SEP FUNC(dma_region_mode, INTERNAL) + +#define EXPAND_DMA_STRIDE_MODE(FUNC, SEP) \ + FUNC(dma_stride_mode, D1) SEP FUNC(dma_stride_mode, D2) SEP FUNC(dma_stride_mode, D3) + +#define EXPAND_ELEMENTWISE_MODE(FUNC, SEP) \ + FUNC(elementwise_mode, MUL) \ + SEP FUNC(elementwise_mode, ADD) SEP FUNC(elementwise_mode, SUB) SEP FUNC(elementwise_mode, MIN) \ + SEP FUNC(elementwise_mode, MAX) SEP FUNC(elementwise_mode, LRELU) SEP FUNC(elementwise_mode, ABS) \ + SEP FUNC(elementwise_mode, CLZ) SEP FUNC(elementwise_mode, SHR) SEP FUNC(elementwise_mode, SHL) + +#define EXPAND_FUNCTIONAL_SAFETY(FUNC, SEP) \ + FUNC(functional_safety, NOT_IMPLEMENTED) SEP FUNC(functional_safety, IMPLEMENTED) + +#define EXPAND_IFM2_OPERAND_ORDER(FUNC, SEP) FUNC(ifm2_operand_order, ORDER_B) SEP FUNC(ifm2_operand_order, ORDER_A) + +#define EXPAND_IFM_SCALE_MODE(FUNC, SEP) \ + FUNC(ifm_scale_mode, OPA_OPB_16) SEP FUNC(ifm_scale_mode, OPA_32) SEP FUNC(ifm_scale_mode, OPB_32) + +#define EXPAND_IFM_UPSCALE_MODE(FUNC, SEP) \ + FUNC(ifm_upscale_mode, NONE) SEP FUNC(ifm_upscale_mode, NEAREST) SEP FUNC(ifm_upscale_mode, ZEROS) + +#define EXPAND_KERNEL_DECOMPOSITION(FUNC, SEP) FUNC(kernel_decomposition, D8X8) SEP FUNC(kernel_decomposition, D4X4) + +#define EXPAND_KERNEL_DILATION(FUNC, SEP) FUNC(kernel_dilation, NONE) SEP FUNC(kernel_dilation, X2) + +#define EXPAND_MAX_BEATS(FUNC, SEP) FUNC(max_beats, B64) SEP FUNC(max_beats, B128) SEP FUNC(max_beats, B256) + +#define EXPAND_MEM_ATTR(FUNC, SEP) \ + FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER0) \ + SEP FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER1) SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER2) \ + SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER3) + +#define EXPAND_OFM_SCALE_MODE(FUNC, SEP) FUNC(ofm_scale_mode, PER_CHANNEL) SEP FUNC(ofm_scale_mode, GLOBAL) + +#define EXPAND_PARALLEL_MODE(FUNC, SEP) FUNC(parallel_mode, SINGLE_CORE) SEP FUNC(parallel_mode, DUAL_CORE_DEPTH) + +#define EXPAND_PMU_AXI_CHANNEL(FUNC, SEP) \ + FUNC(pmu_axi_channel, RD_CMD) \ + SEP FUNC(pmu_axi_channel, RD_IFM) SEP FUNC(pmu_axi_channel, RD_WEIGHTS) SEP FUNC(pmu_axi_channel, RD_SCALE_BIAS) \ + SEP FUNC(pmu_axi_channel, RD_MEM2MEM) SEP FUNC(pmu_axi_channel, WR_OFM) SEP FUNC(pmu_axi_channel, WR_MEM2MEM) + +#define EXPAND_PMU_EVENT(FUNC, SEP) \ + FUNC(pmu_event, NO_EVENT) \ + SEP FUNC(pmu_event, CYCLE) SEP FUNC(pmu_event, NPU_IDLE) SEP FUNC(pmu_event, CC_STALLED_ON_BLOCKDEP) SEP FUNC( \ + pmu_event, CC_STALLED_ON_SHRAM_RECONFIG) SEP FUNC(pmu_event, NPU_ACTIVE) SEP FUNC(pmu_event, MAC_ACTIVE) \ + SEP FUNC(pmu_event, MAC_ACTIVE_8BIT) SEP FUNC(pmu_event, MAC_ACTIVE_16BIT) SEP FUNC( \ + pmu_event, MAC_DPU_ACTIVE) SEP FUNC(pmu_event, MAC_STALLED_BY_WD_ACC) SEP FUNC(pmu_event, \ + MAC_STALLED_BY_WD) \ + SEP FUNC(pmu_event, MAC_STALLED_BY_ACC) SEP FUNC(pmu_event, MAC_STALLED_BY_IB) SEP FUNC( \ + pmu_event, \ + MAC_ACTIVE_32BIT) SEP FUNC(pmu_event, \ + MAC_STALLED_BY_INT_W) SEP FUNC(pmu_event, \ + MAC_STALLED_BY_INT_ACC) SEP FUNC(pmu_event, \ + AO_ACTIVE) \ + SEP FUNC(pmu_event, AO_ACTIVE_8BIT) SEP FUNC(pmu_event, AO_ACTIVE_16BIT) SEP FUNC( \ + pmu_event, AO_STALLED_BY_OFMP_OB) SEP FUNC(pmu_event, AO_STALLED_BY_OFMP) SEP \ + FUNC(pmu_event, AO_STALLED_BY_OB) SEP FUNC(pmu_event, AO_STALLED_BY_ACC_IB) SEP FUNC( \ + pmu_event, AO_STALLED_BY_ACC) SEP FUNC(pmu_event, AO_STALLED_BY_IB) SEP \ + FUNC(pmu_event, WD_ACTIVE) SEP FUNC(pmu_event, WD_STALLED) SEP FUNC(pmu_event, WD_STALLED_BY_WS) SEP FUNC( \ + pmu_event, WD_STALLED_BY_WD_BUF) SEP FUNC(pmu_event, \ + WD_PARSE_ACTIVE) SEP \ + FUNC(pmu_event, WD_PARSE_STALLED) SEP FUNC(pmu_event, WD_PARSE_STALLED_IN) SEP FUNC( \ + pmu_event, WD_PARSE_STALLED_OUT) SEP FUNC(pmu_event, \ + WD_TRANS_WS) SEP \ + FUNC(pmu_event, WD_TRANS_WB) SEP FUNC(pmu_event, WD_TRANS_DW0) SEP FUNC( \ + pmu_event, WD_TRANS_DW1) SEP FUNC(pmu_event, \ + AXI0_RD_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI0_RD_TRANS_COMPLETED) SEP FUNC(pmu_event, AXI0_RD_DATA_BEAT_RECEIVED) SEP FUNC( \ + pmu_event, AXI0_RD_TRAN_REQ_STALLED) SEP FUNC(pmu_event, \ + AXI0_WR_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI0_WR_TRANS_COMPLETED_M) SEP FUNC( \ + pmu_event, AXI0_WR_TRANS_COMPLETED_S) SEP \ + FUNC(pmu_event, AXI0_WR_DATA_BEAT_WRITTEN) SEP FUNC( \ + pmu_event, AXI0_WR_TRAN_REQ_STALLED) SEP \ + FUNC(pmu_event, AXI0_WR_DATA_BEAT_STALLED) SEP FUNC( \ + pmu_event, \ + AXI0_ENABLED_CYCLES) SEP FUNC(pmu_event, \ + AXI0_RD_STALL_LIMIT) SEP \ + FUNC(pmu_event, AXI0_WR_STALL_LIMIT) SEP FUNC( \ + pmu_event, \ + AXI_LATENCY_ANY) SEP FUNC(pmu_event, \ + AXI_LATENCY_32) SEP \ + FUNC(pmu_event, \ + AXI_LATENCY_64) SEP FUNC(pmu_event, \ + AXI_LATENCY_128) SEP \ + FUNC(pmu_event, AXI_LATENCY_256) SEP FUNC( \ + pmu_event, \ + AXI_LATENCY_512) SEP FUNC(pmu_event, \ + AXI_LATENCY_1024) SEP \ + FUNC(pmu_event, ECC_DMA) SEP FUNC( \ + pmu_event, \ + ECC_SB0) SEP FUNC(pmu_event, \ + AXI1_RD_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI1_RD_TRANS_COMPLETED) SEP FUNC( \ + pmu_event, AXI1_RD_DATA_BEAT_RECEIVED) SEP \ + FUNC(pmu_event, AXI1_RD_TRAN_REQ_STALLED) SEP FUNC( \ + pmu_event, AXI1_WR_TRANS_ACCEPTED) SEP \ + FUNC(pmu_event, AXI1_WR_TRANS_COMPLETED_M) SEP FUNC( \ + pmu_event, \ + AXI1_WR_TRANS_COMPLETED_S) SEP \ + FUNC(pmu_event, \ + AXI1_WR_DATA_BEAT_WRITTEN) SEP \ + FUNC(pmu_event, \ + AXI1_WR_TRAN_REQ_STALLED) SEP \ + FUNC( \ + pmu_event, \ + AXI1_WR_DATA_BEAT_STALLED) SEP \ + FUNC( \ + pmu_event, \ + AXI1_ENABLED_CYCLES) SEP \ + FUNC( \ + pmu_event, \ + AXI1_RD_STALL_LIMIT) SEP \ + FUNC( \ + pmu_event, \ + AXI1_WR_STALL_LIMIT) \ + SEP FUNC( \ + pmu_event, \ + ECC_SB1) + +#define EXPAND_POOLING_MODE(FUNC, SEP) \ + FUNC(pooling_mode, MAX) SEP FUNC(pooling_mode, AVERAGE) SEP FUNC(pooling_mode, REDUCE_SUM) + +#define EXPAND_PRIVILEGE_LEVEL(FUNC, SEP) FUNC(privilege_level, USER) SEP FUNC(privilege_level, PRIVILEGED) + +#define EXPAND_ROUND_MODE(FUNC, SEP) FUNC(round_mode, DBL) SEP FUNC(round_mode, TRUNCATE) SEP FUNC(round_mode, NATURAL) + +#define EXPAND_SECURITY_LEVEL(FUNC, SEP) FUNC(security_level, SECURE) SEP FUNC(security_level, NON_SECURE) + +#define EXPAND_STATE(FUNC, SEP) FUNC(state, STOPPED) SEP FUNC(state, RUNNING) + +#define EXPAND_WD_CORE_SLICE_STATE(FUNC, SEP) \ + FUNC(wd_core_slice_state, HEADER) SEP FUNC(wd_core_slice_state, PALETTE) SEP FUNC(wd_core_slice_state, WEIGHTS) + +#define EXPAND_WD_CTRL_STATE(FUNC, SEP) \ + FUNC(wd_ctrl_state, IDLE) \ + SEP FUNC(wd_ctrl_state, DRAIN) SEP FUNC(wd_ctrl_state, OFD_INIT) SEP FUNC(wd_ctrl_state, OFD_RUN) + +#define EXPAND_WEIGHT_ORDER(FUNC, SEP) FUNC(weight_order, DEPTH_FIRST) SEP FUNC(weight_order, PART_KERNEL_FIRST) + +#ifdef __cplusplus +} +#endif +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_config_u55.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_config_u55.h new file mode 100644 index 0000000..9330bb1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_config_u55.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2019-2020,2022 Arm Limited. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU_CONFIG_H +#define ETHOSU_CONFIG_H + +/* Set default values if not manually overriden */ + +#ifndef NPU_QCONFIG +#define NPU_QCONFIG 2 +#endif + +#ifndef NPU_REGIONCFG_0 +#define NPU_REGIONCFG_0 3 +#endif + +#ifndef NPU_REGIONCFG_1 +#define NPU_REGIONCFG_1 0 +#endif + +#ifndef NPU_REGIONCFG_2 +#define NPU_REGIONCFG_2 1 +#endif + +#ifndef NPU_REGIONCFG_3 +#define NPU_REGIONCFG_3 1 +#endif + +#ifndef NPU_REGIONCFG_4 +#define NPU_REGIONCFG_4 1 +#endif + +#ifndef NPU_REGIONCFG_5 +#define NPU_REGIONCFG_5 1 +#endif + +#ifndef NPU_REGIONCFG_6 +#define NPU_REGIONCFG_6 1 +#endif + +#ifndef NPU_REGIONCFG_7 +#define NPU_REGIONCFG_7 1 +#endif + +#ifndef AXI_LIMIT0_MAX_BEATS_BYTES +#define AXI_LIMIT0_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT0_MEM_TYPE +#define AXI_LIMIT0_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT0_MAX_OUTSTANDING_READS +#define AXI_LIMIT0_MAX_OUTSTANDING_READS 32 +#endif + +#ifndef AXI_LIMIT0_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT0_MAX_OUTSTANDING_WRITES 16 +#endif + +#ifndef AXI_LIMIT1_MAX_BEATS_BYTES +#define AXI_LIMIT1_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT1_MEM_TYPE +#define AXI_LIMIT1_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT1_MAX_OUTSTANDING_READS +#define AXI_LIMIT1_MAX_OUTSTANDING_READS 32 +#endif + +#ifndef AXI_LIMIT1_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT1_MAX_OUTSTANDING_WRITES 16 +#endif + +#ifndef AXI_LIMIT2_MAX_BEATS_BYTES +#define AXI_LIMIT2_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT2_MEM_TYPE +#define AXI_LIMIT2_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT2_MAX_OUTSTANDING_READS +#define AXI_LIMIT2_MAX_OUTSTANDING_READS 32 +#endif + +#ifndef AXI_LIMIT2_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT2_MAX_OUTSTANDING_WRITES 16 +#endif + +#ifndef AXI_LIMIT3_MAX_BEATS_BYTES +#define AXI_LIMIT3_MAX_BEATS_BYTES 0x0 +#endif + +#ifndef AXI_LIMIT3_MEM_TYPE +#define AXI_LIMIT3_MEM_TYPE 0x0 +#endif + +#ifndef AXI_LIMIT3_MAX_OUTSTANDING_READS +#define AXI_LIMIT3_MAX_OUTSTANDING_READS 32 +#endif + +#ifndef AXI_LIMIT3_MAX_OUTSTANDING_WRITES +#define AXI_LIMIT3_MAX_OUTSTANDING_WRITES 16 +#endif + +#endif /* #ifndef ETHOSU_CONFIG_H */ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_device.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_device.h new file mode 100644 index 0000000..02942b1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_device.h @@ -0,0 +1,142 @@ +/* + * SPDX-FileCopyrightText: Copyright 2019-2023 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU_DEVICE_H +#define ETHOSU_DEVICE_H + +/****************************************************************************** + * Includes + ******************************************************************************/ +#include "ethosu_types.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * Defines + ******************************************************************************/ + +// NOTE: Deprecated +#ifndef ETHOSU_PMU_NCOUNTERS +#define ETHOSU_PMU_NCOUNTERS 4 +#endif + +/****************************************************************************** + * Types + ******************************************************************************/ +struct NPU_REG; // Forward declare, to be implemented by each device + +struct ethosu_device +{ + volatile struct NPU_REG *reg; // Register map + uint32_t secure; + uint32_t privileged; +}; + +/****************************************************************************** + * Prototypes + ******************************************************************************/ + +/** + * Initialize the device. + */ +struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_enable, uint32_t privilege_enable); + +/** + * Deinitialize the device. + */ +void ethosu_dev_deinit(struct ethosu_device *dev); + +/** + * Initialize AXI settings for device. + */ +enum ethosu_error_codes ethosu_dev_axi_init(struct ethosu_device *dev); + +/** + * Execute a given command stream on NPU. + * \param[in] cmd_stream_ptr Pointer to the command stream + * \param[in] cms_length Command stream length + * \param[in] base_addr Pointer to array of base addresses + * - 0: weight tensor + * - 1: scratch tensor + * - All input tensors + * - All output tensors + * \param[in] num_base_addr Number of base addresses. + */ +void ethosu_dev_run_command_stream(struct ethosu_device *dev, + const uint8_t *cmd_stream_ptr, + uint32_t cms_length, + const uint64_t *base_addr, + int num_base_addr); + +/** + * Print information on NPU error status + */ +void ethosu_dev_print_err_status(struct ethosu_device *dev); + +/** + * Interrupt handler on device layer + * \return true if NPU status is OK, otherwise false + */ +bool ethosu_dev_handle_interrupt(struct ethosu_device *dev); + +/** + * Get hardware information from NPU + * \param[out] hwinfo Pointer to the hardware info struct to be filled in. + */ +void ethosu_dev_get_hw_info(struct ethosu_device *dev, struct ethosu_hw_info *hwinfo); + +/** + * Verify that requested security state and privilege mode are active + * \return 32 bit status value + */ +bool ethosu_dev_verify_access_state(struct ethosu_device *dev); + +/** + * Performs a NPU soft reset and waits for the NPU to become ready + * \return \ref ethosu_error_codes + */ +enum ethosu_error_codes ethosu_dev_soft_reset(struct ethosu_device *dev); + +/** + * Enable/disable clock and power using clock/power q interface. + * \param[in] clock_q Clock q ENABLE/DISABLE \ref clock_q_request. + * \param[in] power_q Power q ENABLE/DISABLE \ref power_q_request. + * \return \ref ethosu_error_codes + */ +enum ethosu_error_codes ethosu_dev_set_clock_and_power(struct ethosu_device *dev, + enum ethosu_clock_q_request clock_q, + enum ethosu_power_q_request power_q); + +/** + * Verifies that optimizer parameters from model are compatible with the hardware + * \param[in] cfg Config data from optimizer. + * \param[in] id Id data from optimizer. + * \return true if parameters match with hardware, false otherwise. + */ +bool ethosu_dev_verify_optimizer_config(struct ethosu_device *dev, uint32_t cfg_in, uint32_t id_in); + +#ifdef __cplusplus +} +#endif + +#endif // ETHOSU_DEVICE_H diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_device_u55_u65.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_device_u55_u65.c new file mode 100644 index 0000000..7de0daa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_device_u55_u65.c @@ -0,0 +1,392 @@ +/* + * SPDX-FileCopyrightText: Copyright 2019-2023 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * Includes + ******************************************************************************/ +#if EI_ETHOS + +#include "ethosu_interface.h" + +#include "ethosu_device.h" +#include "ethosu_log.h" + +#ifdef ETHOSU55 +#include "ethosu_config_u55.h" +#else +#include "ethosu_config_u65.h" +#endif + +#include +#include +#include +#include +#include +#include + +/****************************************************************************** + * Defines + ******************************************************************************/ + +#define ETHOSU_PRODUCT_U55 0 +#define ETHOSU_PRODUCT_U65 1 + +#define BASEP_OFFSET 4 + +#ifdef ETHOSU65 +#define ADDRESS_BITS 40 +#else +#define ADDRESS_BITS 32 +#endif + +#define ADDRESS_MASK ((1ull << ADDRESS_BITS) - 1) + +#define NPU_CMD_PWR_CLK_MASK (0xC) + +/****************************************************************************** + * Functions + ******************************************************************************/ + +uint64_t __attribute__((weak)) ethosu_address_remap(uint64_t address, int index) +{ + (void)(index); + return address; +} + +struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_enable, uint32_t privilege_enable) +{ + struct ethosu_device *dev = malloc(sizeof(struct ethosu_device)); + if (!dev) + { + LOG_ERR("Failed to allocate memory for Ethos-U device"); + return NULL; + } + + dev->reg = (volatile struct NPU_REG *)base_address; + dev->secure = secure_enable; + dev->privileged = privilege_enable; + +#ifdef ETHOSU55 + if (dev->reg->CONFIG.product != ETHOSU_PRODUCT_U55) +#else + if (dev->reg->CONFIG.product != ETHOSU_PRODUCT_U65) +#endif + { + LOG_ERR("Failed to initialize device. Driver has not been compiled for this product"); + goto err; + } + + // Make sure the NPU is in a known state + if (ethosu_dev_soft_reset(dev) != ETHOSU_SUCCESS) + { + goto err; + } + + return dev; + +err: + free(dev); + return NULL; +} + +void ethosu_dev_deinit(struct ethosu_device *dev) +{ + free(dev); +} + +enum ethosu_error_codes ethosu_dev_axi_init(struct ethosu_device *dev) +{ + struct regioncfg_r rcfg = {0}; + struct axi_limit0_r l0 = {0}; + struct axi_limit1_r l1 = {0}; + struct axi_limit2_r l2 = {0}; + struct axi_limit3_r l3 = {0}; + + dev->reg->QCONFIG.word = NPU_QCONFIG; + + rcfg.region0 = NPU_REGIONCFG_0; + rcfg.region1 = NPU_REGIONCFG_1; + rcfg.region2 = NPU_REGIONCFG_2; + rcfg.region3 = NPU_REGIONCFG_3; + rcfg.region4 = NPU_REGIONCFG_4; + rcfg.region5 = NPU_REGIONCFG_5; + rcfg.region6 = NPU_REGIONCFG_6; + rcfg.region7 = NPU_REGIONCFG_7; + dev->reg->REGIONCFG.word = rcfg.word; + + l0.max_beats = AXI_LIMIT0_MAX_BEATS_BYTES; + l0.memtype = AXI_LIMIT0_MEM_TYPE; + l0.max_outstanding_read_m1 = AXI_LIMIT0_MAX_OUTSTANDING_READS - 1; + l0.max_outstanding_write_m1 = AXI_LIMIT0_MAX_OUTSTANDING_WRITES - 1; + + l1.max_beats = AXI_LIMIT1_MAX_BEATS_BYTES; + l1.memtype = AXI_LIMIT1_MEM_TYPE; + l1.max_outstanding_read_m1 = AXI_LIMIT1_MAX_OUTSTANDING_READS - 1; + l1.max_outstanding_write_m1 = AXI_LIMIT1_MAX_OUTSTANDING_WRITES - 1; + + l2.max_beats = AXI_LIMIT2_MAX_BEATS_BYTES; + l2.memtype = AXI_LIMIT2_MEM_TYPE; + l2.max_outstanding_read_m1 = AXI_LIMIT2_MAX_OUTSTANDING_READS - 1; + l2.max_outstanding_write_m1 = AXI_LIMIT2_MAX_OUTSTANDING_WRITES - 1; + + l3.max_beats = AXI_LIMIT3_MAX_BEATS_BYTES; + l3.memtype = AXI_LIMIT3_MEM_TYPE; + l3.max_outstanding_read_m1 = AXI_LIMIT3_MAX_OUTSTANDING_READS - 1; + l3.max_outstanding_write_m1 = AXI_LIMIT3_MAX_OUTSTANDING_WRITES - 1; + + dev->reg->AXI_LIMIT0.word = l0.word; + dev->reg->AXI_LIMIT1.word = l1.word; + dev->reg->AXI_LIMIT2.word = l2.word; + dev->reg->AXI_LIMIT3.word = l3.word; + + return ETHOSU_SUCCESS; +} + +void ethosu_dev_run_command_stream(struct ethosu_device *dev, + const uint8_t *cmd_stream_ptr, + uint32_t cms_length, + const uint64_t *base_addr, + int num_base_addr) +{ + assert(num_base_addr <= NPU_REG_BASEP_ARRLEN); + + struct cmd_r cmd; + uint64_t qbase = ethosu_address_remap((uintptr_t)cmd_stream_ptr, -1); + assert(qbase <= ADDRESS_MASK); + LOG_DEBUG("QBASE=0x%016llx, QSIZE=%" PRIu32 ", cmd_stream_ptr=%p", qbase, cms_length, cmd_stream_ptr); + + dev->reg->QBASE.word[0] = qbase & 0xffffffff; +#ifdef ETHOSU65 + dev->reg->QBASE.word[1] = qbase >> 32; +#endif + dev->reg->QSIZE.word = cms_length; + + for (int i = 0; i < num_base_addr; i++) + { + uint64_t addr = ethosu_address_remap(base_addr[i], i); + assert(addr <= ADDRESS_MASK); + LOG_DEBUG("BASEP%d=0x%016llx", i, addr); + dev->reg->BASEP[i].word[0] = addr & 0xffffffff; +#ifdef ETHOSU65 + dev->reg->BASEP[i].word[1] = addr >> 32; +#endif + } + + cmd.word = dev->reg->CMD.word & NPU_CMD_PWR_CLK_MASK; + cmd.transition_to_running_state = 1; + + dev->reg->CMD.word = cmd.word; + LOG_DEBUG("CMD=0x%08" PRIx32, cmd.word); +} + +void ethosu_dev_print_err_status(struct ethosu_device *dev) +{ + LOG_ERR("NPU status=0x%08" PRIx32 ", qread=%" PRIu32 ", cmd_end_reached=%u", + dev->reg->STATUS.word, + dev->reg->QREAD.word, + dev->reg->STATUS.cmd_end_reached); +} + +bool ethosu_dev_handle_interrupt(struct ethosu_device *dev) +{ + struct cmd_r cmd; + + // Clear interrupt + cmd.word = dev->reg->CMD.word & NPU_CMD_PWR_CLK_MASK; + cmd.clear_irq = 1; + dev->reg->CMD.word = cmd.word; + + // If a fault has occured, the NPU needs to be reset + if (dev->reg->STATUS.bus_status || dev->reg->STATUS.cmd_parse_error || dev->reg->STATUS.wd_fault || + dev->reg->STATUS.ecc_fault || !dev->reg->STATUS.cmd_end_reached) + { + return false; + } + + return true; +} + +bool ethosu_dev_verify_access_state(struct ethosu_device *dev) +{ + if (dev->reg->PROT.active_CSL != (dev->secure ? SECURITY_LEVEL_SECURE : SECURITY_LEVEL_NON_SECURE) || + dev->reg->PROT.active_CPL != (dev->privileged ? PRIVILEGE_LEVEL_PRIVILEGED : PRIVILEGE_LEVEL_USER)) + { + return false; + } + return true; +} + +enum ethosu_error_codes ethosu_dev_soft_reset(struct ethosu_device *dev) +{ + // Note that after a soft-reset, the NPU is unconditionally + // powered until the next CMD gets written. + + struct reset_r reset; + + reset.word = 0; + reset.pending_CPL = dev->privileged ? PRIVILEGE_LEVEL_PRIVILEGED : PRIVILEGE_LEVEL_USER; + reset.pending_CSL = dev->secure ? SECURITY_LEVEL_SECURE : SECURITY_LEVEL_NON_SECURE; + + // Reset and set security level + LOG_INFO("Soft reset NPU"); + dev->reg->RESET.word = reset.word; + + // Wait until reset status indicates that reset has been completed + for (int i = 0; i < 100000 && dev->reg->STATUS.reset_status != 0; i++) + { + } + + if (dev->reg->STATUS.reset_status != 0) + { + LOG_ERR("Soft reset timed out"); + return ETHOSU_GENERIC_FAILURE; + } + + // Verify that NPU has switched security state and privilege level + if (ethosu_dev_verify_access_state(dev) != true) + { + LOG_ERR("Failed to switch security state and privilege level"); + return ETHOSU_GENERIC_FAILURE; + } + + // Reinitialize AXI settings + ethosu_dev_axi_init(dev); + + return ETHOSU_SUCCESS; +} + +void ethosu_dev_get_hw_info(struct ethosu_device *dev, struct ethosu_hw_info *hwinfo) +{ + struct config_r cfg; + struct id_r id; + + cfg.word = dev->reg->CONFIG.word; + id.word = dev->reg->ID.word; + + hwinfo->cfg.cmd_stream_version = cfg.cmd_stream_version; + hwinfo->cfg.custom_dma = cfg.custom_dma; + hwinfo->cfg.macs_per_cc = cfg.macs_per_cc; + + hwinfo->version.arch_major_rev = id.arch_major_rev; + hwinfo->version.arch_minor_rev = id.arch_minor_rev; + hwinfo->version.arch_patch_rev = id.arch_patch_rev; + hwinfo->version.product_major = id.product_major; + hwinfo->version.version_major = id.version_major; + hwinfo->version.version_minor = id.version_minor; + hwinfo->version.version_status = id.version_status; +} + +enum ethosu_error_codes ethosu_dev_set_clock_and_power(struct ethosu_device *dev, + enum ethosu_clock_q_request clock_q, + enum ethosu_power_q_request power_q) +{ + struct cmd_r cmd = {0}; + cmd.word = dev->reg->CMD.word & NPU_CMD_PWR_CLK_MASK; + + if (power_q != ETHOSU_POWER_Q_UNCHANGED) + { + cmd.power_q_enable = power_q == ETHOSU_POWER_Q_ENABLE ? 1 : 0; + } + if (clock_q != ETHOSU_CLOCK_Q_UNCHANGED) + { + cmd.clock_q_enable = clock_q == ETHOSU_CLOCK_Q_ENABLE ? 1 : 0; + } + + dev->reg->CMD.word = cmd.word; + LOG_DEBUG("CMD=0x%08" PRIx32, cmd.word); + + return ETHOSU_SUCCESS; +} + +bool ethosu_dev_verify_optimizer_config(struct ethosu_device *dev, uint32_t cfg_in, uint32_t id_in) +{ + struct config_r *opt_cfg = (struct config_r *)&cfg_in; + struct config_r hw_cfg; + struct id_r *opt_id = (struct id_r *)&id_in; + struct id_r hw_id; + bool ret = true; + + hw_cfg.word = dev->reg->CONFIG.word; + hw_id.word = dev->reg->ID.word; + + LOG_INFO("Optimizer config. product=%u, cmd_stream_version=%u, macs_per_cc=%u, shram_size=%u, custom_dma=%u", + opt_cfg->product, + opt_cfg->cmd_stream_version, + opt_cfg->macs_per_cc, + opt_cfg->shram_size, + opt_cfg->custom_dma); + LOG_INFO("Optimizer config. arch version: %u.%u.%u", + opt_id->arch_major_rev, + opt_id->arch_minor_rev, + opt_id->arch_patch_rev); + LOG_INFO("Ethos-U config. product=%u, cmd_stream_version=%u, macs_per_cc=%u, shram_size=%u, custom_dma=%u", + hw_cfg.product, + hw_cfg.cmd_stream_version, + hw_cfg.macs_per_cc, + hw_cfg.shram_size, + hw_cfg.custom_dma); + LOG_INFO("Ethos-U. arch version=%u.%u.%u", hw_id.arch_major_rev, hw_id.arch_minor_rev, hw_id.arch_patch_rev); + + if (opt_cfg->word != hw_cfg.word) + { + if (hw_cfg.product != opt_cfg->product) + { + LOG_ERR("NPU config mismatch. npu.product=%u, optimizer.product=%u", hw_cfg.product, opt_cfg->product); + ret = false; + } + + if (hw_cfg.macs_per_cc != opt_cfg->macs_per_cc) + { + LOG_ERR("NPU config mismatch. npu.macs_per_cc=%u, optimizer.macs_per_cc=%u", + hw_cfg.macs_per_cc, + opt_cfg->macs_per_cc); + ret = false; + } + + if (hw_cfg.cmd_stream_version != opt_cfg->cmd_stream_version) + { + LOG_ERR("NPU config mismatch. npu.cmd_stream_version=%u, optimizer.cmd_stream_version=%u", + hw_cfg.cmd_stream_version, + opt_cfg->cmd_stream_version); + ret = false; + } + + if (!hw_cfg.custom_dma && opt_cfg->custom_dma) + { + LOG_ERR("NPU config mismatch. npu.custom_dma=%u, optimizer.custom_dma=%u", + hw_cfg.custom_dma, + opt_cfg->custom_dma); + ret = false; + } + } + + if ((hw_id.arch_major_rev != opt_id->arch_major_rev) || (hw_id.arch_minor_rev < opt_id->arch_minor_rev)) + { + LOG_ERR("NPU arch mismatch. npu.arch=%u.%u.%u, optimizer.arch=%u.%u.%u", + hw_id.arch_major_rev, + hw_id.arch_minor_rev, + hw_id.arch_patch_rev, + opt_id->arch_major_rev, + opt_id->arch_minor_rev, + opt_id->arch_patch_rev); + ret = false; + } + + return ret; +} +#endif // EI_ETHOS diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_driver.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_driver.c new file mode 100644 index 0000000..ae038e3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_driver.c @@ -0,0 +1,765 @@ +/* + * SPDX-FileCopyrightText: Copyright 2019-2023 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** + * Includes + ******************************************************************************/ +#if EI_ETHOS + +#include "ethosu_driver.h" +#include "ethosu_device.h" +#include "ethosu_log.h" + +#ifdef ETHOSU55 +#include "ethosu_config_u55.h" +#else +#include "ethosu_config_u65.h" +#endif + +#include +#include +#include +#include +#include +#include +#include + +/****************************************************************************** + * Defines + ******************************************************************************/ + +#define UNUSED(x) ((void)x) + +#define BYTES_IN_32_BITS 4 +#define MASK_16_BYTE_ALIGN (0xF) +#define OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD 2 +#define DRIVER_ACTION_LENGTH_32_BIT_WORD 1 +#define ETHOSU_FOURCC ('1' << 24 | 'P' << 16 | 'O' << 8 | 'C') // "Custom Operator Payload 1" + +#define FAST_MEMORY_BASE_ADDR_INDEX 2 + +/****************************************************************************** + * Types + ******************************************************************************/ + +// Driver actions +enum DRIVER_ACTION_e +{ + RESERVED = 0, + OPTIMIZER_CONFIG = 1, + COMMAND_STREAM = 2, + NOP = 5, +}; + +// Custom operator payload data struct +struct cop_data_s +{ + union + { + // Driver action data + struct + { + uint8_t driver_action_command; // (valid values in DRIVER_ACTION_e) + uint8_t reserved; + + // Driver action data + union + { + // DA_CMD_OPT_CFG + struct + { + uint16_t rel_nbr : 4; + uint16_t patch_nbr : 4; + uint16_t opt_cfg_reserved : 8; + }; + + // DA_CMD_CMSTRM + struct + { + uint16_t length; + }; + + uint16_t driver_action_data; + }; + }; + + uint32_t word; + }; +}; + +// optimizer config struct +struct opt_cfg_s +{ + struct cop_data_s da_data; + uint32_t cfg; + uint32_t id; +}; + +/****************************************************************************** + * Variables + ******************************************************************************/ + +// Registered drivers linked list HEAD +static struct ethosu_driver *registered_drivers = NULL; + +/****************************************************************************** + * Weak functions - Cache + * + * Default NOP operations. Override if available on the targeted device. + ******************************************************************************/ + +/* + * Flush/clean the data cache by address and size. Passing NULL as p argument + * expects the whole cache to be flushed. + */ +void __attribute__((weak)) ethosu_flush_dcache(uint32_t *p, size_t bytes) +{ + UNUSED(p); + UNUSED(bytes); +} + +/* + * Invalidate the data cache by address and size. Passing NULL as p argument + * expects the whole cache to be invalidated. + */ +void __attribute__((weak)) ethosu_invalidate_dcache(uint32_t *p, size_t bytes) +{ + UNUSED(p); + UNUSED(bytes); +} + +/****************************************************************************** + * Weak functions - Semaphore/Mutex for multi NPU + * + * Following section handles the minimal sempahore and mutex implementation in + * case of baremetal applications. Weak symbols will be overridden by RTOS + * definitions and implement true thread-safety (in application layer). + ******************************************************************************/ + +struct ethosu_semaphore_t +{ + uint8_t count; +}; + +static void *ethosu_mutex; +static void *ethosu_semaphore; + +void *__attribute__((weak)) ethosu_mutex_create(void) +{ + return NULL; +} + +void __attribute__((weak)) ethosu_mutex_destroy(void *mutex) +{ + UNUSED(mutex); +} + +int __attribute__((weak)) ethosu_mutex_lock(void *mutex) +{ + UNUSED(mutex); + return 0; +} + +int __attribute__((weak)) ethosu_mutex_unlock(void *mutex) +{ + UNUSED(mutex); + return 0; +} + +// Baremetal implementation of creating a semaphore +void *__attribute__((weak)) ethosu_semaphore_create(void) +{ + struct ethosu_semaphore_t *sem = malloc(sizeof(*sem)); + if (sem != NULL) + { + sem->count = 0; + } + return sem; +} + +void __attribute__((weak)) ethosu_semaphore_destroy(void *sem) +{ + free((struct ethosu_semaphore_t *)sem); +} + +// Baremetal simulation of waiting/sleeping for and then taking a semaphore using intrisics +int __attribute__((weak)) ethosu_semaphore_take(void *sem) +{ + struct ethosu_semaphore_t *s = sem; + while (s->count == 0) + { + __WFE(); + } + s->count--; + return 0; +} + +// Baremetal simulation of giving a semaphore and waking up processes using intrinsics +int __attribute__((weak)) ethosu_semaphore_give(void *sem) +{ + struct ethosu_semaphore_t *s = sem; + s->count++; + __SEV(); + return 0; +} + +/****************************************************************************** + * Weak functions - Inference begin/end callbacks + ******************************************************************************/ + +void __attribute__((weak)) ethosu_inference_begin(struct ethosu_driver *drv, void *user_arg) +{ + UNUSED(user_arg); + UNUSED(drv); +} + +void __attribute__((weak)) ethosu_inference_end(struct ethosu_driver *drv, void *user_arg) +{ + UNUSED(user_arg); + UNUSED(drv); +} + +/****************************************************************************** + * Static functions + ******************************************************************************/ +static void ethosu_register_driver(struct ethosu_driver *drv) +{ + ethosu_mutex_lock(ethosu_mutex); + drv->next = registered_drivers; + registered_drivers = drv; + ethosu_mutex_unlock(ethosu_mutex); + + ethosu_semaphore_give(ethosu_semaphore); + + LOG_INFO("New NPU driver registered (handle: 0x%p, NPU: 0x%p)", drv, drv->dev->reg); +} + +static int ethosu_deregister_driver(struct ethosu_driver *drv) +{ + struct ethosu_driver *curr; + struct ethosu_driver **prev; + + ethosu_mutex_lock(ethosu_mutex); + curr = registered_drivers; + prev = ®istered_drivers; + + while (curr != NULL) + { + if (curr == drv) + { + *prev = curr->next; + LOG_INFO("NPU driver handle %p deregistered.", drv); + ethosu_semaphore_take(ethosu_semaphore); + break; + } + + prev = &curr->next; + curr = curr->next; + } + + ethosu_mutex_unlock(ethosu_mutex); + + if (curr == NULL) + { + LOG_ERR("No NPU driver handle registered at address %p.", drv); + return -1; + } + + return 0; +} + +static void ethosu_reset_job(struct ethosu_driver *drv) +{ + memset(&drv->job, 0, sizeof(struct ethosu_job)); +} + +static int handle_optimizer_config(struct ethosu_driver *drv, struct opt_cfg_s const *opt_cfg_p) +{ + LOG_INFO("Optimizer release nbr: %u patch: %u", opt_cfg_p->da_data.rel_nbr, opt_cfg_p->da_data.patch_nbr); + + if (ethosu_dev_verify_optimizer_config(drv->dev, opt_cfg_p->cfg, opt_cfg_p->id) != true) + { + return -1; + } + + return 0; +} + +static int handle_command_stream(struct ethosu_driver *drv, const uint8_t *cmd_stream, const int cms_length) +{ + uint32_t cms_bytes = cms_length * BYTES_IN_32_BITS; + ptrdiff_t cmd_stream_ptr = (ptrdiff_t)cmd_stream; + + LOG_INFO("handle_command_stream: cmd_stream=%p, cms_length %d", cmd_stream, cms_length); + + if (0 != ((ptrdiff_t)cmd_stream & MASK_16_BYTE_ALIGN)) + { + LOG_ERR("Command stream addr %p not aligned to 16 bytes", cmd_stream); + return -1; + } + + // Verify 16 byte alignment for base address' + for (int i = 0; i < drv->job.num_base_addr; i++) + { + if (0 != (drv->job.base_addr[i] & MASK_16_BYTE_ALIGN)) + { + LOG_ERR("Base addr %d: 0x%llx not aligned to 16 bytes", i, drv->job.base_addr[i]); + return -1; + } + } + + // Flush the cache if available on CPU. + // The upcasting to uin32_t* is ok since the pointer never is dereferenced. + // The base_addr_size is null if invoking from prior to invoke_V2, in that case + // the whole cache is being flushed. + + if (drv->job.base_addr_size != NULL) + { + ethosu_flush_dcache((uint32_t *)cmd_stream_ptr, cms_bytes); + for (int i = 0; i < drv->job.num_base_addr; i++) + { + ethosu_flush_dcache((uint32_t *)(uintptr_t)drv->job.base_addr[i], drv->job.base_addr_size[i]); + } + } + else + { + ethosu_flush_dcache(NULL, 0); + } + + // Request power gating disabled during inference run + if (ethosu_request_power(drv)) + { + LOG_ERR("Failed to request power"); + return -1; + } + + drv->job.state = ETHOSU_JOB_RUNNING; + + // Inference begin callback + ethosu_inference_begin(drv, drv->job.user_arg); + + // Execute the command stream + ethosu_dev_run_command_stream(drv->dev, cmd_stream, cms_bytes, drv->job.base_addr, drv->job.num_base_addr); + + return 0; +} + +/****************************************************************************** + * Weak functions - Interrupt handler + ******************************************************************************/ +void __attribute__((weak)) ethosu_irq_handler(struct ethosu_driver *drv) +{ + LOG_DEBUG("Got interrupt from Ethos-U"); + + drv->job.state = ETHOSU_JOB_DONE; + if (!ethosu_dev_handle_interrupt(drv->dev)) + { + drv->status_error = true; + } + ethosu_semaphore_give(drv->semaphore); +} + +/****************************************************************************** + * Functions API + ******************************************************************************/ + +int ethosu_init(struct ethosu_driver *drv, + void *const base_address, + const void *fast_memory, + const size_t fast_memory_size, + uint32_t secure_enable, + uint32_t privilege_enable) +{ + LOG_INFO("Initializing NPU: base_address=%p, fast_memory=%p, fast_memory_size=%zu, secure=%" PRIu32 + ", privileged=%" PRIu32, + base_address, + fast_memory, + fast_memory_size, + secure_enable, + privilege_enable); + + if (!ethosu_mutex) + { + ethosu_mutex = ethosu_mutex_create(); + } + + if (!ethosu_semaphore) + { + ethosu_semaphore = ethosu_semaphore_create(); + if (!ethosu_semaphore) + { + LOG_ERR("Failed to create global driver semaphore"); + return -1; + } + } + + drv->fast_memory = (uint32_t)fast_memory; + drv->fast_memory_size = fast_memory_size; + drv->power_request_counter = 0; + + // Initialize the device and set requested security state and privilege mode + drv->dev = ethosu_dev_init(base_address, secure_enable, privilege_enable); + + if (drv->dev == NULL) + { + LOG_ERR("Failed to initialize Ethos-U device"); + return -1; + } + + drv->semaphore = ethosu_semaphore_create(); + if (!drv->semaphore) + { + LOG_ERR("Failed to create driver semaphore"); + ethosu_dev_deinit(drv->dev); + drv->dev = NULL; + return -1; + } + + drv->status_error = false; + + ethosu_reset_job(drv); + ethosu_register_driver(drv); + + return 0; +} + +void ethosu_deinit(struct ethosu_driver *drv) +{ + ethosu_deregister_driver(drv); + ethosu_semaphore_destroy(drv->semaphore); + ethosu_dev_deinit(drv->dev); + drv->dev = NULL; +} + +int ethosu_soft_reset(struct ethosu_driver *drv) +{ + // Soft reset the NPU + if (ethosu_dev_soft_reset(drv->dev) != ETHOSU_SUCCESS) + { + LOG_ERR("Failed to soft-reset NPU"); + return -1; + } + + // Update power and clock gating after the soft reset + ethosu_dev_set_clock_and_power(drv->dev, + drv->power_request_counter > 0 ? ETHOSU_CLOCK_Q_DISABLE : ETHOSU_CLOCK_Q_ENABLE, + drv->power_request_counter > 0 ? ETHOSU_POWER_Q_DISABLE : ETHOSU_POWER_Q_ENABLE); + + return 0; +} + +int ethosu_request_power(struct ethosu_driver *drv) +{ + // Check if this is the first power request, increase counter + if (drv->power_request_counter++ == 0) + { + // Always reset to a known state. Changes to requested + // security state/privilege mode if necessary. + if (ethosu_soft_reset(drv)) + { + LOG_ERR("Failed to request power for Ethos-U"); + drv->power_request_counter--; + return -1; + } + } + return 0; +} + +void ethosu_release_power(struct ethosu_driver *drv) +{ + if (drv->power_request_counter == 0) + { + LOG_WARN("No power request left to release, reference counter is 0"); + } + else + { + // Decrement ref counter and enable power gating if no requests remain + if (--drv->power_request_counter == 0) + { + ethosu_dev_set_clock_and_power(drv->dev, ETHOSU_CLOCK_Q_ENABLE, ETHOSU_POWER_Q_ENABLE); + } + } +} + +void ethosu_get_driver_version(struct ethosu_driver_version *ver) +{ + assert(ver != NULL); + ver->major = ETHOSU_DRIVER_VERSION_MAJOR; + ver->minor = ETHOSU_DRIVER_VERSION_MINOR; + ver->patch = ETHOSU_DRIVER_VERSION_PATCH; +} + +void ethosu_get_hw_info(struct ethosu_driver *drv, struct ethosu_hw_info *hw) +{ + assert(hw != NULL); + ethosu_dev_get_hw_info(drv->dev, hw); +} + +int ethosu_wait(struct ethosu_driver *drv, bool block) +{ + int ret = 0; + + switch (drv->job.state) + { + case ETHOSU_JOB_IDLE: + LOG_ERR("Inference job not running..."); + ret = -2; + break; + case ETHOSU_JOB_RUNNING: + if (!block) + { + // Inference still running, do not block + ret = 1; + break; + } + // fall through + case ETHOSU_JOB_DONE: + // Wait for interrupt in blocking mode. In non-blocking mode + // the interrupt has already triggered + ethosu_semaphore_take(drv->semaphore); + + // Inference done callback + ethosu_inference_end(drv, drv->job.user_arg); + + // Relase power gating disabled requirement + ethosu_release_power(drv); + + // Check NPU and interrupt status + if (drv->status_error) + { + LOG_ERR("NPU error(s) occured during inference."); + ethosu_dev_print_err_status(drv->dev); + + // Reset the NPU + (void)ethosu_soft_reset(drv); + // NPU is no longer in error state + drv->status_error = false; + + ret = -1; + } + + if (ret == 0) + { + // Invalidate cache + if (drv->job.base_addr_size != NULL) + { + for (int i = 0; i < drv->job.num_base_addr; i++) + { + ethosu_invalidate_dcache((uint32_t *)(uintptr_t)drv->job.base_addr[i], drv->job.base_addr_size[i]); + } + } + else + { + ethosu_invalidate_dcache(NULL, 0); + } + + LOG_DEBUG("Inference finished successfully..."); + } + + // Reset internal job (state resets to IDLE) + ethosu_reset_job(drv); + break; + + default: + LOG_ERR("Unexpected job state"); + ethosu_reset_job(drv); + ret = -1; + break; + } + + // Return inference job status + return ret; +} + +int ethosu_invoke_async(struct ethosu_driver *drv, + const void *custom_data_ptr, + const int custom_data_size, + uint64_t *const base_addr, + const size_t *base_addr_size, + const int num_base_addr, + void *user_arg) +{ + + const struct cop_data_s *data_ptr = custom_data_ptr; + const struct cop_data_s *data_end = (struct cop_data_s *)((ptrdiff_t)custom_data_ptr + custom_data_size); + + // Make sure an inference is not already running + if (drv->job.state != ETHOSU_JOB_IDLE) + { + LOG_ERR("Inference already running, or waiting to be cleared..."); + return -1; + } + + drv->job.state = ETHOSU_JOB_IDLE; + drv->job.custom_data_ptr = custom_data_ptr; + drv->job.custom_data_size = custom_data_size; + drv->job.base_addr = base_addr; + drv->job.base_addr_size = base_addr_size; + drv->job.num_base_addr = num_base_addr; + drv->job.user_arg = user_arg; + + // First word in custom_data_ptr should contain "Custom Operator Payload 1" + if (data_ptr->word != ETHOSU_FOURCC) + { + LOG_ERR("Custom Operator Payload: %" PRIu32 " is not correct, expected %x", data_ptr->word, ETHOSU_FOURCC); + goto err; + } + + // Custom data length must be a multiple of 32 bits + if ((custom_data_size % BYTES_IN_32_BITS) != 0) + { + LOG_ERR("custom_data_size=0x%x not a multiple of 4", (unsigned)custom_data_size); + goto err; + } + + data_ptr++; + + // Adjust base address to fast memory area + if (drv->fast_memory != 0 && num_base_addr >= FAST_MEMORY_BASE_ADDR_INDEX) + { + + if (base_addr_size != NULL && base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX] > drv->fast_memory_size) + { + LOG_ERR("Fast memory area too small. fast_memory_size=%u, base_addr_size=%u", + drv->fast_memory_size, + base_addr_size[FAST_MEMORY_BASE_ADDR_INDEX]); + goto err; + } + + base_addr[FAST_MEMORY_BASE_ADDR_INDEX] = drv->fast_memory; + } + + drv->status_error = false; + + // Parse Custom Operator Payload data + while (data_ptr < data_end) + { + switch (data_ptr->driver_action_command) + { + case OPTIMIZER_CONFIG: + LOG_DEBUG("OPTIMIZER_CONFIG"); + struct opt_cfg_s const *opt_cfg_p = (const struct opt_cfg_s *)data_ptr; + + if (handle_optimizer_config(drv, opt_cfg_p) < 0) + { + goto err; + } + data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + OPTIMIZER_CONFIG_LENGTH_32_BIT_WORD; + break; + case COMMAND_STREAM: + // Vela only supports putting one COMMAND_STREAM per op + LOG_DEBUG("COMMAND_STREAM"); + const uint8_t *command_stream = (const uint8_t *)(data_ptr + 1); + int cms_length = (data_ptr->reserved << 16) | data_ptr->length; + + if (handle_command_stream(drv, command_stream, cms_length) < 0) + { + goto err; + } + data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD + cms_length; + break; + case NOP: + LOG_DEBUG("NOP"); + data_ptr += DRIVER_ACTION_LENGTH_32_BIT_WORD; + break; + default: + LOG_ERR("UNSUPPORTED driver_action_command: %u", data_ptr->driver_action_command); + goto err; + break; + } + } + + return 0; +err: + LOG_ERR("Failed to invoke inference."); + ethosu_reset_job(drv); + return -1; +} + +int ethosu_invoke_v3(struct ethosu_driver *drv, + const void *custom_data_ptr, + const int custom_data_size, + uint64_t *const base_addr, + const size_t *base_addr_size, + const int num_base_addr, + void *user_arg) +{ + if (ethosu_invoke_async( + drv, custom_data_ptr, custom_data_size, base_addr, base_addr_size, num_base_addr, user_arg) < 0) + { + return -1; + } + + return ethosu_wait(drv, true); +} + +struct ethosu_driver *ethosu_reserve_driver(void) +{ + struct ethosu_driver *drv = NULL; + + LOG_INFO("Acquiring NPU driver handle"); + ethosu_semaphore_take(ethosu_semaphore); // This is meant to block until available + + ethosu_mutex_lock(ethosu_mutex); + drv = registered_drivers; + + while (drv != NULL) + { + if (!drv->reserved) + { + drv->reserved = true; + LOG_DEBUG("NPU driver handle %p reserved", drv); + break; + } + drv = drv->next; + } + ethosu_mutex_unlock(ethosu_mutex); + + if (!drv) + { + LOG_ERR("No NPU driver handle available, but semaphore taken"); + } + + return drv; +} + +void ethosu_release_driver(struct ethosu_driver *drv) +{ + ethosu_mutex_lock(ethosu_mutex); + if (drv != NULL && drv->reserved) + { + if (drv->job.state == ETHOSU_JOB_RUNNING || drv->job.state == ETHOSU_JOB_DONE) + { + // Give the inference one shot to complete or force kill the job + if (ethosu_wait(drv, false) == 1) + { + // Still running, soft reset the NPU and reset driver + drv->power_request_counter = 0; + ethosu_soft_reset(drv); + ethosu_reset_job(drv); + drv->status_error = false; + } + } + + drv->reserved = false; + LOG_DEBUG("NPU driver handle %p released", drv); + ethosu_semaphore_give(ethosu_semaphore); + } + ethosu_mutex_unlock(ethosu_mutex); +} +#endif // EI_ETHOS \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_interface.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_interface.h new file mode 100644 index 0000000..2409cb4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_interface.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// clang-format off +#ifndef ETHOSU_INTERFACE_WRAPPER_ +#define ETHOSU_INTERFACE_WRAPPER_ + +#define xstr(a) str(a) +#define str(a) #a + +#define catm(a, b) catm_(a, b) +#define catm_(a, b) a##b + +#define ETHOSU_INTERFACE_FILE xstr(catm(ethos, ETHOSU_ARCH)_interface.h) + +#include ETHOSU_INTERFACE_FILE + +#endif // ETHOSU_INTERFACE_WRAPPER_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_log.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_log.h new file mode 100644 index 0000000..582b91d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_log.h @@ -0,0 +1,72 @@ +/* + * SPDX-FileCopyrightText: Copyright 2021-2023 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHOSU_LOG_H +#define ETHOSU_LOG_H + +/****************************************************************************** + * Includes + ******************************************************************************/ + +#include +#include + +/****************************************************************************** + * Defines + ******************************************************************************/ + +// Log severity levels +#define ETHOSU_LOG_ERR 0 +#define ETHOSU_LOG_WARN 1 +#define ETHOSU_LOG_INFO 2 +#define ETHOSU_LOG_DEBUG 3 + +// Define default log severity +#ifndef ETHOSU_LOG_SEVERITY +#define ETHOSU_LOG_SEVERITY ETHOSU_LOG_WARN +#endif + +// Log formatting +#define LOG(f, ...) (void)fprintf(stdout, f, ##__VA_ARGS__) + +#if ETHOSU_LOG_SEVERITY >= ETHOSU_LOG_ERR +#define LOG_ERR(f, ...) \ + (void)fprintf(stderr, "E: " f " (%s:%d)\n", ##__VA_ARGS__, strrchr("/" __FILE__, '/') + 1, __LINE__) +#else +#define LOG_ERR(f, ...) +#endif + +#if ETHOSU_LOG_SEVERITY >= ETHOSU_LOG_WARN +#define LOG_WARN(f, ...) (void)fprintf(stdout, "W: " f "\n", ##__VA_ARGS__) +#else +#define LOG_WARN(f, ...) +#endif + +#if ETHOSU_LOG_SEVERITY >= ETHOSU_LOG_INFO +#define LOG_INFO(f, ...) (void)fprintf(stdout, "I: " f "\n", ##__VA_ARGS__) +#else +#define LOG_INFO(f, ...) +#endif + +#if ETHOSU_LOG_SEVERITY >= ETHOSU_LOG_DEBUG +#define LOG_DEBUG(f, ...) (void)fprintf(stdout, "D: %s(): " f "\n", __FUNCTION__, ##__VA_ARGS__) +#else +#define LOG_DEBUG(f, ...) +#endif + +#endif \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_pmu.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_pmu.c new file mode 100644 index 0000000..6832005 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/src/ethosu_pmu.c @@ -0,0 +1,304 @@ +/* + * SPDX-FileCopyrightText: Copyright 2019-2023 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/***************************************************************************** + * Includes + *****************************************************************************/ +#if EI_ETHOS + +#include "ethosu_device.h" +#include "ethosu_driver.h" +#include "ethosu_interface.h" +#include "ethosu_log.h" +#include "pmu_ethosu.h" + +#include +#include +#include + +/***************************************************************************** + * Defines + *****************************************************************************/ + +#define MASK_0_31_BITS (0xFFFFFFFF) +#define MASK_32_47_BITS (0xFFFF00000000) + +#define COMMA , +#define SEMICOLON ; + +#define EVTYPE(A, name) \ + case PMU_EVENT_##name: \ + return ETHOSU_PMU_##name + +#define EVID(A, name) (PMU_EVENT_##name) + +/***************************************************************************** + * Variables + *****************************************************************************/ + +static const enum pmu_event eventbyid[] = {EXPAND_PMU_EVENT(EVID, COMMA)}; + +/***************************************************************************** + * Static functions + *****************************************************************************/ + +static enum ethosu_pmu_event_type pmu_event_type(uint32_t id) +{ + switch (id) + { + EXPAND_PMU_EVENT(EVTYPE, SEMICOLON); + default: + LOG_ERR("Unknown PMU event id: 0x%" PRIx32, id); + } + + return ETHOSU_PMU_SENTINEL; +} + +static uint32_t pmu_event_value(enum ethosu_pmu_event_type event) +{ + int a = event; + if ((a < ETHOSU_PMU_SENTINEL) && (a >= ETHOSU_PMU_NO_EVENT)) + { + return eventbyid[event]; + } + else + { + return (uint32_t)(-1); + } +} + +/***************************************************************************** + * Functions + *****************************************************************************/ + +void ETHOSU_PMU_Enable(struct ethosu_driver *drv) +{ + LOG_DEBUG("Enable PMU"); + struct pmcr_r pmcr = {0}; + pmcr.cnt_en = 1; + ethosu_request_power(drv); + drv->dev->reg->PMCR.word = pmcr.word; +} + +void ETHOSU_PMU_Disable(struct ethosu_driver *drv) +{ + LOG_DEBUG("Disable PMU"); + drv->dev->reg->PMCR.word = 0; + ethosu_release_power(drv); +} + +uint32_t ETHOSU_PMU_Get_NumEventCounters(void) +{ + return NPU_REG_PMEVCNTR_ARRLEN; +} + +void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type) +{ + assert(num < ETHOSU_PMU_NCOUNTERS); + uint32_t val = pmu_event_value(type); + LOG_DEBUG("num=%" PRIu32 ", type=%d, val=%" PRIu32, num, type, val); + drv->dev->reg->PMEVTYPER[num].word = val; +} + +enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num) +{ + assert(num < ETHOSU_PMU_NCOUNTERS); + uint32_t val = drv->dev->reg->PMEVTYPER[num].word; + enum ethosu_pmu_event_type type = pmu_event_type(val); + LOG_DEBUG("num=%" PRIu32 ", type=%d, val=%" PRIu32, num, type, val); + return type; +} + +void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv) +{ + LOG_DEBUG("Reset PMU cycle counter"); + struct pmcr_r pmcr; + pmcr.word = drv->dev->reg->PMCR.word; + pmcr.cycle_cnt_rst = 1; + drv->dev->reg->PMCR.word = pmcr.word; +} + +void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv) +{ + LOG_DEBUG("Reset all events"); + struct pmcr_r pmcr; + pmcr.word = drv->dev->reg->PMCR.word; + pmcr.event_cnt_rst = 1; + drv->dev->reg->PMCR.word = pmcr.word; +} + +void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask) +{ + LOG_DEBUG("mask=0x%08" PRIx32, mask); + drv->dev->reg->PMCNTENSET.word = mask; +} + +void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask) +{ + LOG_DEBUG("mask=0x%08" PRIx32, mask); + drv->dev->reg->PMCNTENCLR.word = mask; +} + +uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv) +{ + uint32_t pmcntenset = drv->dev->reg->PMCNTENSET.word; + LOG_DEBUG("mask=0x%08" PRIx32, pmcntenset); + return pmcntenset; +} + +uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv) +{ + uint32_t val_lo = drv->dev->reg->PMCCNTR.CYCLE_CNT_LO; + uint32_t val_hi = drv->dev->reg->PMCCNTR.CYCLE_CNT_HI; + uint64_t val = ((uint64_t)val_hi << 32) | val_lo; + + LOG_DEBUG("val=%" PRIu64, val); + return val; +} + +void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val) +{ + uint32_t active = ETHOSU_PMU_CNTR_Status(drv) & ETHOSU_PMU_CCNT_Msk; + + LOG_DEBUG("val=%llu", val); + + if (active) + { + ETHOSU_PMU_CNTR_Disable(drv, ETHOSU_PMU_CCNT_Msk); + } + + drv->dev->reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS; + drv->dev->reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32; + + if (active) + { + ETHOSU_PMU_CNTR_Enable(drv, ETHOSU_PMU_CCNT_Msk); + } +} + +uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num) +{ + assert(num < ETHOSU_PMU_NCOUNTERS); + uint32_t val = drv->dev->reg->PMEVCNTR[num].word; + LOG_DEBUG("num=%" PRIu32 ", val=%" PRIu32, num, val); + + return val; +} + +void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val) +{ + assert(num < ETHOSU_PMU_NCOUNTERS); + LOG_DEBUG("num=%" PRIu32 ", val=%" PRIu32, num, val); + drv->dev->reg->PMEVCNTR[num].word = val; +} + +uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv) +{ + LOG_DEBUG(""); + return drv->dev->reg->PMOVSSET.word; +} + +void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask) +{ + LOG_DEBUG(""); + drv->dev->reg->PMOVSCLR.word = mask; +} + +void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask) +{ + LOG_DEBUG("mask=0x%08" PRIx32, mask); + drv->dev->reg->PMINTSET.word = mask; +} + +void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask) +{ + LOG_DEBUG("mask=0x%08" PRIx32, mask); + drv->dev->reg->PMINTCLR.word = mask; +} + +uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv) +{ + uint32_t pmint = drv->dev->reg->PMINTSET.word; + LOG_DEBUG("mask=0x%08" PRIx32, pmint); + return pmint; +} + +void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask) +{ + LOG_DEBUG(""); + uint32_t cntrs_active = ETHOSU_PMU_CNTR_Status(drv); + + // Disable counters + ETHOSU_PMU_CNTR_Disable(drv, mask); + + // Increment cycle counter + if (mask & ETHOSU_PMU_CCNT_Msk) + { + uint64_t val = ETHOSU_PMU_Get_CCNTR(drv) + 1; + drv->dev->reg->PMCCNTR.CYCLE_CNT_LO = val & MASK_0_31_BITS; + drv->dev->reg->PMCCNTR.CYCLE_CNT_HI = (val & MASK_32_47_BITS) >> 32; + } + + for (int i = 0; i < ETHOSU_PMU_NCOUNTERS; i++) + { + if (mask & (1u << i)) + { + uint32_t val = ETHOSU_PMU_Get_EVCNTR(drv, i); + drv->dev->reg->PMEVCNTR[i].word = val + 1; + } + } + + // Reenable the active counters + ETHOSU_PMU_CNTR_Enable(drv, cntrs_active); +} + +void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event) +{ + LOG_DEBUG("start_event=%u", start_event); + uint32_t val = pmu_event_value(start_event); + struct pmccntr_cfg_r cfg; + cfg.word = drv->dev->reg->PMCCNTR_CFG.word; + cfg.CYCLE_CNT_CFG_START = val; + drv->dev->reg->PMCCNTR_CFG.word = cfg.word; +} + +void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event) +{ + LOG_DEBUG("stop_event=%u", stop_event); + uint32_t val = pmu_event_value(stop_event); + struct pmccntr_cfg_r cfg; + cfg.word = drv->dev->reg->PMCCNTR_CFG.word; + cfg.CYCLE_CNT_CFG_STOP = val; + drv->dev->reg->PMCCNTR_CFG.word = cfg.word; +} + +uint32_t ETHOSU_PMU_Get_QREAD(struct ethosu_driver *drv) +{ + uint32_t val = drv->dev->reg->QREAD.word; + LOG_DEBUG("qread=%" PRIu32, val); + return val; +} + +uint32_t ETHOSU_PMU_Get_STATUS(struct ethosu_driver *drv) +{ + uint32_t val = drv->dev->reg->STATUS.word; + LOG_DEBUG("status=0x%" PRIx32, val); + return val; +} + +#endif // EI_ETHOS \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/version.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/version.txt new file mode 100644 index 0000000..5656be6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/ethos-core-driver/version.txt @@ -0,0 +1 @@ +v1.23.2 \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/himax-we2/debug_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/himax-we2/debug_log.cpp new file mode 100644 index 0000000..3dd5d13 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/himax-we2/debug_log.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_HIMAX_WE2 == 1 + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include +#include + +// Redirect TFLite DebugLog to ei_printf +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 +void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_HIMAX_WE2 == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/himax-we2/ei_classifier_porting.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/himax-we2/ei_classifier_porting.cpp new file mode 100644 index 0000000..8c291d3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/himax-we2/ei_classifier_porting.cpp @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_HIMAX_WE2 == 1 + +/* Include ----------------------------------------------------------------- */ +#include +#include +#include +#include +#include "xprintf.h" +extern "C" { + #include "timer_interface.h" +}; + +__attribute__((weak)) EI_IMPULSE_ERROR ei_run_impulse_check_canceled() { + return EI_IMPULSE_OK; +} + +/** + * Cancelable sleep, can be triggered with signal from other thread + */ +__attribute__((weak)) EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + hx_drv_timer_cm55x_delay_ms(time_ms, TIMER_STATE_DC); + + return EI_IMPULSE_OK; +} + +// Should be called at least once every ~10.7 seconds +uint64_t ei_read_timer_ms() +{ + uint32_t tick, loop_cnt; + SystemGetTick(&tick, &loop_cnt); + + // tick is counting down, so we need to add elapsed ticks to the total tick count + uint64_t elapsed_ms = (uint64_t)loop_cnt * (uint64_t)(SysTick_LOAD_RELOAD_Msk+1) + (SysTick_LOAD_RELOAD_Msk + 1 - tick); + // convert ticks to ms knowing the CPU frequency + elapsed_ms = elapsed_ms / (SystemCoreClock / 1000); + + return elapsed_ms; +} + +uint64_t ei_read_timer_us() +{ + uint32_t tick, loop_cnt; + SystemGetTick(&tick, &loop_cnt); + + // tick is counting down, so we need to add elapsed ticks to the total tick count + uint64_t elapsed_us = (uint64_t)loop_cnt * (uint64_t)(SysTick_LOAD_RELOAD_Msk+1) + (SysTick_LOAD_RELOAD_Msk + 1 - tick); + // convert ticks to ms knowing the CPU frequency + elapsed_us = elapsed_us / (SystemCoreClock / 1000000); + + return elapsed_us; +} + +void ei_serial_set_baudrate(int baudrate) +{ + // hx_drv_uart_initial((HX_DRV_UART_BAUDRATE_E)baudrate); +} + +void ei_putchar(char c) +{ + /* Send char to serial output */ + xputc(c); +} + +__attribute__((weak)) void ei_printf(const char *format, ...) { + va_list args; + va_start(args, format); + xvprintf(format, args); + va_end(args); +} + +__attribute__((weak)) void ei_printf_float(float f) { + float n = f; + + static double PRECISION = 0.00001; + static int MAX_NUMBER_STRING_SIZE = 32; + + char s[MAX_NUMBER_STRING_SIZE]; + + if (n == 0.0) { + ei_printf("0.00000"); + } else { + int digit, m; //, m1; + char *c = s; + int neg = (n < 0); + if (neg) { + n = -n; + } + // calculate magnitude + m = log10(n); + if (neg) { + *(c++) = '-'; + } + if (m < 1.0) { + m = 0; + } + // convert the number + while (n > PRECISION || m >= 0) { + double weight = pow(10.0, m); + if (weight > 0 && !isinf(weight)) { + digit = floor(n / weight); + n -= (digit * weight); + *(c++) = '0' + digit; + } + if (m == 0 && n > 0) { + *(c++) = '.'; + } + m--; + } + *(c) = '\0'; + ei_printf("%s", s); + } +} + +__attribute__((weak)) void *ei_malloc(size_t size) { + return malloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + return calloc(nitems, size); +} + +__attribute__((weak)) void ei_free(void *ptr) { + free(ptr); +} + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif +__attribute__((weak)) void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // #if EI_PORTING_HIMAX_WE2 == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/iar/debug_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/iar/debug_log.cpp new file mode 100644 index 0000000..ae378e4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/iar/debug_log.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_IAR == 1 + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include +#include + +// Redirect TFLite DebugLog to ei_printf +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 +void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_IAR == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/iar/ei_classifier_porting.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/iar/ei_classifier_porting.cpp new file mode 100644 index 0000000..3d450f0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/iar/ei_classifier_porting.cpp @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_IAR == 1 + +#include +#include +#include + +#include "main.h" +#include "stm32f4xx_hal.h" + + +__attribute__((weak)) EI_IMPULSE_ERROR ei_run_impulse_check_canceled() { + return EI_IMPULSE_OK; +} + +/** + * Cancelable sleep, can be triggered with signal from other thread + */ +__attribute__((weak)) EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + + HAL_Delay(time_ms); + + return EI_IMPULSE_OK; +} + +uint64_t ei_read_timer_ms() { + + return HAL_GetTick(); +} + +uint64_t ei_read_timer_us() { + + return HAL_GetTick() * 1000; +} + +__attribute__((weak)) void ei_printf(const char *format, ...) { + + va_list myargs; + va_start(myargs, format); + vprintf(format, myargs); + va_end(myargs); +} + +__attribute__((weak)) void ei_printf_float(float f) { + ei_printf("%f", f); +} + +__attribute__((weak)) void ei_putchar(char data) +{ + putchar(data); +} + +__attribute__((weak)) void *ei_malloc(size_t size) { + return malloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + return calloc(nitems, size); +} + +__attribute__((weak)) void ei_free(void *ptr) { + free(ptr); +} + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif +__attribute__((weak)) void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_IAR == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/infineon-psoc62/debug_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/infineon-psoc62/debug_log.cpp new file mode 100644 index 0000000..47dfb2f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/infineon-psoc62/debug_log.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_INFINEONPSOC62 == 1 + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include +#include + +// Redirect TFLite DebugLog to ei_printf +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 +void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_INFINEONPSOC62 == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/infineon-psoc62/ei_classifier_porting.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/infineon-psoc62/ei_classifier_porting.cpp new file mode 100644 index 0000000..23e5b27 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/infineon-psoc62/ei_classifier_porting.cpp @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_INFINEONPSOC62 == 1 + +#include +#include +#include +#include "unistd.h" +#include "cyhal.h" +#ifdef FREERTOS_ENABLED +#include +#include +#include +#else /* bare-metal */ +#include "cyhal_lptimer.h" + +static bool timer_init = false; +static volatile uint64_t tick = 0; + +static void systick_isr(void) +{ + tick++; +} +#endif + +__attribute__((weak)) EI_IMPULSE_ERROR ei_run_impulse_check_canceled() { + return EI_IMPULSE_OK; +} + +#ifdef FREERTOS_ENABLED +__attribute__((weak)) EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + vTaskDelay(time_ms / portTICK_PERIOD_MS); + + return EI_IMPULSE_OK; +} + +__attribute__((weak)) uint64_t ei_read_timer_ms() { + + return xTaskGetTickCount(); +} + +__attribute__((weak)) uint64_t ei_read_timer_us() { + + return xTaskGetTickCount()*1000; +} +#else /* Bare-metal */ +__attribute__((weak)) EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + cyhal_system_delay_ms(time_ms); + return EI_IMPULSE_OK; +} + +uint64_t ei_read_timer_ms() { + if(timer_init == false) { + cyhal_clock_t clock; + uint32_t freq; + + // get IMO clock frequency + cyhal_clock_reserve(&clock, &CYHAL_CLOCK_IMO); + freq = cyhal_clock_get_frequency(&clock); + cyhal_clock_free(&clock); + + // set SysTick to 1 ms + Cy_SysTick_Init(CY_SYSTICK_CLOCK_SOURCE_CLK_IMO, (freq / 1000) - 1); + Cy_SysTick_SetCallback(0, systick_isr); + timer_init = true; + return 0; + } + return tick; +} + +uint64_t ei_read_timer_us() { + return ei_read_timer_ms() * 1000; +} +#endif /* FREERTOS_ENABLED */ + +void ei_putchar(char c) +{ + putchar(c); +} + +__attribute__((weak)) char ei_getchar(void) +{ + return getchar(); +} + +__attribute__((weak)) void ei_printf(const char *format, ...) { + + char buffer[256]; + va_list myargs; + va_start(myargs, format); + vsnprintf(buffer, 256, format, myargs); + va_end(myargs); + + printf("%s", buffer); +} + +__attribute__((weak)) void ei_printf_float(float f) { + ei_printf("%f", f); +} + +#ifdef FREERTOS_ENABLED +__attribute__((weak)) void *ei_malloc(size_t size) { + return pvPortMalloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + void *mem = NULL; + + /* Infineon port of FreeRTOS does not support pvPortCalloc */ + mem = pvPortMalloc(nitems * size); + if (mem) { + /* zero the memory */ + memset(mem, 0, nitems * size); + } + return mem; +} + +__attribute__((weak)) void ei_free(void *ptr) { + vPortFree(ptr); +} +#else +__attribute__((weak)) void *ei_malloc(size_t size) { + return malloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + return calloc(nitems, size); +} + +__attribute__((weak)) void ei_free(void *ptr) { + free(ptr); +} +#endif + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif +__attribute__((weak)) void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_INFINEONPSOC62 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/particle/debug_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/particle/debug_log.cpp new file mode 100644 index 0000000..58b697b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/particle/debug_log.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_PARTICLE == 1 + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include +#include + +// On mbed platforms, we set up a serial port and write to it for debug logging. +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 +void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_PARTICLE diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/particle/ei_classifier_porting.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/particle/ei_classifier_porting.cpp new file mode 100644 index 0000000..b280d33 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/particle/ei_classifier_porting.cpp @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2023 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_PARTICLE == 1 + +#include +#include +#include + +#define EI_WEAK_FN __attribute__((weak)) + +EI_WEAK_FN EI_IMPULSE_ERROR ei_run_impulse_check_canceled() { + return EI_IMPULSE_OK; +} + +EI_WEAK_FN EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + delay(time_ms); + return EI_IMPULSE_OK; +} + +uint64_t ei_read_timer_ms() { + return millis(); +} + +uint64_t ei_read_timer_us() { + return micros(); +} + +void ei_serial_set_baudrate(int baudrate) +{ + +} + +EI_WEAK_FN void ei_putchar(char c) +{ + Serial.write(c); +} + +EI_WEAK_FN char ei_getchar() +{ + char ch = 0; + if (Serial.available() > 0) { + ch = Serial.read(); + } + return ch; +} + +/** + * Printf function uses vsnprintf and output using Arduino Serial + */ +__attribute__((weak)) void ei_printf(const char *format, ...) { + static char print_buf[1024] = { 0 }; + + va_list args; + va_start(args, format); + int r = vsnprintf(print_buf, sizeof(print_buf), format, args); + va_end(args); + + if (r > 0) { + Serial.write(print_buf); + } +} + +__attribute__((weak)) void ei_printf_float(float f) { + Serial.print(f, 6); +} + +__attribute__((weak)) void *ei_malloc(size_t size) { + return malloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + return calloc(nitems, size); +} + +__attribute__((weak)) void ei_free(void *ptr) { + free(ptr); +} + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif +__attribute__((weak)) void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_PARTICLE == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/seeed-vision-ai/debug_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/seeed-vision-ai/debug_log.cpp new file mode 100644 index 0000000..9022698 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/seeed-vision-ai/debug_log.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_HIMAX == 1 + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include +#include + +// Redirect TFLite DebugLog to ei_printf +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 +void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // EI_PORTING_HIMAX == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/seeed-vision-ai/ei_classifier_porting.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/seeed-vision-ai/ei_classifier_porting.cpp new file mode 100644 index 0000000..39145da --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/porting/seeed-vision-ai/ei_classifier_porting.cpp @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an "AS + * IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either + * express or implied. See the License for the specific language + * governing permissions and limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../ei_classifier_porting.h" +#if EI_PORTING_SEEED_VISION_AI == 1 + +/* Include ----------------------------------------------------------------- */ +#include +#include +#include +// #include "hx_drv_tflm.h" +#include "hx_drv_timer.h" +#include + +#include "embARC_debug.h" + + +/* Constants ---------------------------------------------------------------- */ +#define HIMAX_TIMER_CLK_FREQ_HZ 400000000 +#define HIMAX_TIMER_TICK_1SEC (HIMAX_TIMER_CLK_FREQ_HZ/1) +#define HIMAX_TIMER_TICK_1MSEC (HIMAX_TIMER_TICK_1SEC/1000) + +/* Private variables -------------------------------------------------------- */ + +__attribute__((weak)) EI_IMPULSE_ERROR ei_run_impulse_check_canceled() { + return EI_IMPULSE_OK; +} + +/** + * Cancelable sleep, can be triggered with signal from other thread + */ +__attribute__((weak)) EI_IMPULSE_ERROR ei_sleep(int32_t time_ms) { + + board_delay_ms(time_ms); + + return EI_IMPULSE_OK; +} + +// Should be called at least once every ~10.7 seconds +uint64_t ei_read_timer_ms() +{ + static uint64_t system_time_ms = 0; + static uint64_t prev_tick_us = 0; + uint64_t tick_us; + int64_t diff_tick_us, elapsed_time_ms; + + tick_us = board_get_cur_us(); + diff_tick_us = tick_us - prev_tick_us; + elapsed_time_ms = diff_tick_us / 1000; + + // update system time and previous tick reference + if (elapsed_time_ms > 0) { + system_time_ms += elapsed_time_ms; + prev_tick_us = tick_us; + } + + return system_time_ms; +} + +uint64_t ei_read_timer_us() +{ + return board_get_cur_us(); +} + +void ei_serial_set_baudrate(int baudrate) +{ + // hx_drv_uart_initial((HX_DRV_UART_BAUDRATE_E)baudrate); +} + +void ei_putchar(char c) +{ + /* Send char to serial output */ + ei_printf("%c", c); +} + +__attribute__((weak)) void ei_printf(const char *format, ...) { + va_list args; + va_start(args, format); + // print_out(format, args); + xvprintf(format, args); + va_end(args); +} + +__attribute__((weak)) void ei_printf_float(float f) { + float n = f; + + static double PRECISION = 0.00001; + static int MAX_NUMBER_STRING_SIZE = 32; + + char s[MAX_NUMBER_STRING_SIZE]; + + if (n == 0.0) { + ei_printf("0.00000"); + } else { + int digit, m; //, m1; + char *c = s; + int neg = (n < 0); + if (neg) { + n = -n; + } + // calculate magnitude + m = log10(n); + if (neg) { + *(c++) = '-'; + } + if (m < 1.0) { + m = 0; + } + // convert the number + while (n > PRECISION || m >= 0) { + double weight = pow(10.0, m); + if (weight > 0 && !isinf(weight)) { + digit = floor(n / weight); + n -= (digit * weight); + *(c++) = '0' + digit; + } + if (m == 0 && n > 0) { + *(c++) = '.'; + } + m--; + } + *(c) = '\0'; + ei_printf("%s", s); + } +} + +__attribute__((weak)) void *ei_malloc(size_t size) { + return malloc(size); +} + +__attribute__((weak)) void *ei_calloc(size_t nitems, size_t size) { + return calloc(nitems, size); +} + +__attribute__((weak)) void ei_free(void *ptr) { + free(ptr); +} + +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" +#endif +__attribute__((weak)) void DebugLog(const char* s) { + ei_printf("%s", s); +} + +#endif // #if EI_PORTING_SEEED_VISION_AI == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/sources.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/sources.txt new file mode 100644 index 0000000..6e67469 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/sources.txt @@ -0,0 +1,7 @@ +tensorflow and third_party folders based on: https://github.com/tensorflow/tensorflow/#c903b4607821a03c36c17b0befa2535c7dd0e066 +TensorFlow source was prepared using `make -f tensorflow/lite/micro/tools/make/Makefile generate_projects` +The folders were taken from `tensorflow/lite/micro/tools/make/gen/osx_x86_64/prj/hello_world/make` +These files and directories were then deleted: + - `tensorflow/lite/micro/debug_log.cc` + - `tensorflow/lite/micro/examples/hello_world` +CMSIS-DSP based on: https://github.com/ARM-software/CMSIS_5/tree/4d378e81968c6bec5441a42885b24db7cf189bca diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/LICENSE b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/LICENSE new file mode 100644 index 0000000..d645695 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/builtin_op_data.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/builtin_op_data.h new file mode 100644 index 0000000..b512ba7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/builtin_op_data.h @@ -0,0 +1,22 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +// Compatibility shim for new location of interface definitions. + +#ifndef TENSORFLOW_LITE_BUILTIN_OP_DATA_H_ +#define TENSORFLOW_LITE_BUILTIN_OP_DATA_H_ + +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" + +#endif // TENSORFLOW_LITE_BUILTIN_OP_DATA_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/builtin_ops.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/builtin_ops.h new file mode 100644 index 0000000..3370730 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/builtin_ops.h @@ -0,0 +1,194 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_BUILTIN_OPS_H_ +#define TENSORFLOW_LITE_BUILTIN_OPS_H_ + +// DO NOT EDIT MANUALLY: This file is automatically generated by +// `schema/builtin_ops_header/generator.cc`. + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// The enum for builtin operators. +// Note: CUSTOM, DELEGATE, and PLACEHOLDER_FOR_GREATER_OP_CODES are 3 special +// ops which are not real built-in ops. +typedef enum { + kTfLiteBuiltinAdd = 0, + kTfLiteBuiltinAveragePool2d = 1, + kTfLiteBuiltinConcatenation = 2, + kTfLiteBuiltinConv2d = 3, + kTfLiteBuiltinDepthwiseConv2d = 4, + kTfLiteBuiltinDepthToSpace = 5, + kTfLiteBuiltinDequantize = 6, + kTfLiteBuiltinEmbeddingLookup = 7, + kTfLiteBuiltinFloor = 8, + kTfLiteBuiltinFullyConnected = 9, + kTfLiteBuiltinHashtableLookup = 10, + kTfLiteBuiltinL2Normalization = 11, + kTfLiteBuiltinL2Pool2d = 12, + kTfLiteBuiltinLocalResponseNormalization = 13, + kTfLiteBuiltinLogistic = 14, + kTfLiteBuiltinLshProjection = 15, + kTfLiteBuiltinLstm = 16, + kTfLiteBuiltinMaxPool2d = 17, + kTfLiteBuiltinMul = 18, + kTfLiteBuiltinRelu = 19, + kTfLiteBuiltinReluN1To1 = 20, + kTfLiteBuiltinRelu6 = 21, + kTfLiteBuiltinReshape = 22, + kTfLiteBuiltinResizeBilinear = 23, + kTfLiteBuiltinRnn = 24, + kTfLiteBuiltinSoftmax = 25, + kTfLiteBuiltinSpaceToDepth = 26, + kTfLiteBuiltinSvdf = 27, + kTfLiteBuiltinTanh = 28, + kTfLiteBuiltinConcatEmbeddings = 29, + kTfLiteBuiltinSkipGram = 30, + kTfLiteBuiltinCall = 31, + kTfLiteBuiltinCustom = 32, + kTfLiteBuiltinEmbeddingLookupSparse = 33, + kTfLiteBuiltinPad = 34, + kTfLiteBuiltinUnidirectionalSequenceRnn = 35, + kTfLiteBuiltinGather = 36, + kTfLiteBuiltinBatchToSpaceNd = 37, + kTfLiteBuiltinSpaceToBatchNd = 38, + kTfLiteBuiltinTranspose = 39, + kTfLiteBuiltinMean = 40, + kTfLiteBuiltinSub = 41, + kTfLiteBuiltinDiv = 42, + kTfLiteBuiltinSqueeze = 43, + kTfLiteBuiltinUnidirectionalSequenceLstm = 44, + kTfLiteBuiltinStridedSlice = 45, + kTfLiteBuiltinBidirectionalSequenceRnn = 46, + kTfLiteBuiltinExp = 47, + kTfLiteBuiltinTopkV2 = 48, + kTfLiteBuiltinSplit = 49, + kTfLiteBuiltinLogSoftmax = 50, + kTfLiteBuiltinDelegate = 51, + kTfLiteBuiltinBidirectionalSequenceLstm = 52, + kTfLiteBuiltinCast = 53, + kTfLiteBuiltinPrelu = 54, + kTfLiteBuiltinMaximum = 55, + kTfLiteBuiltinArgMax = 56, + kTfLiteBuiltinMinimum = 57, + kTfLiteBuiltinLess = 58, + kTfLiteBuiltinNeg = 59, + kTfLiteBuiltinPadv2 = 60, + kTfLiteBuiltinGreater = 61, + kTfLiteBuiltinGreaterEqual = 62, + kTfLiteBuiltinLessEqual = 63, + kTfLiteBuiltinSelect = 64, + kTfLiteBuiltinSlice = 65, + kTfLiteBuiltinSin = 66, + kTfLiteBuiltinTransposeConv = 67, + kTfLiteBuiltinSparseToDense = 68, + kTfLiteBuiltinTile = 69, + kTfLiteBuiltinExpandDims = 70, + kTfLiteBuiltinEqual = 71, + kTfLiteBuiltinNotEqual = 72, + kTfLiteBuiltinLog = 73, + kTfLiteBuiltinSum = 74, + kTfLiteBuiltinSqrt = 75, + kTfLiteBuiltinRsqrt = 76, + kTfLiteBuiltinShape = 77, + kTfLiteBuiltinPow = 78, + kTfLiteBuiltinArgMin = 79, + kTfLiteBuiltinFakeQuant = 80, + kTfLiteBuiltinReduceProd = 81, + kTfLiteBuiltinReduceMax = 82, + kTfLiteBuiltinPack = 83, + kTfLiteBuiltinLogicalOr = 84, + kTfLiteBuiltinOneHot = 85, + kTfLiteBuiltinLogicalAnd = 86, + kTfLiteBuiltinLogicalNot = 87, + kTfLiteBuiltinUnpack = 88, + kTfLiteBuiltinReduceMin = 89, + kTfLiteBuiltinFloorDiv = 90, + kTfLiteBuiltinReduceAny = 91, + kTfLiteBuiltinSquare = 92, + kTfLiteBuiltinZerosLike = 93, + kTfLiteBuiltinFill = 94, + kTfLiteBuiltinFloorMod = 95, + kTfLiteBuiltinRange = 96, + kTfLiteBuiltinResizeNearestNeighbor = 97, + kTfLiteBuiltinLeakyRelu = 98, + kTfLiteBuiltinSquaredDifference = 99, + kTfLiteBuiltinMirrorPad = 100, + kTfLiteBuiltinAbs = 101, + kTfLiteBuiltinSplitV = 102, + kTfLiteBuiltinUnique = 103, + kTfLiteBuiltinCeil = 104, + kTfLiteBuiltinReverseV2 = 105, + kTfLiteBuiltinAddN = 106, + kTfLiteBuiltinGatherNd = 107, + kTfLiteBuiltinCos = 108, + kTfLiteBuiltinWhere = 109, + kTfLiteBuiltinRank = 110, + kTfLiteBuiltinElu = 111, + kTfLiteBuiltinReverseSequence = 112, + kTfLiteBuiltinMatrixDiag = 113, + kTfLiteBuiltinQuantize = 114, + kTfLiteBuiltinMatrixSetDiag = 115, + kTfLiteBuiltinRound = 116, + kTfLiteBuiltinHardSwish = 117, + kTfLiteBuiltinIf = 118, + kTfLiteBuiltinWhile = 119, + kTfLiteBuiltinNonMaxSuppressionV4 = 120, + kTfLiteBuiltinNonMaxSuppressionV5 = 121, + kTfLiteBuiltinScatterNd = 122, + kTfLiteBuiltinSelectV2 = 123, + kTfLiteBuiltinDensify = 124, + kTfLiteBuiltinSegmentSum = 125, + kTfLiteBuiltinBatchMatmul = 126, + kTfLiteBuiltinPlaceholderForGreaterOpCodes = 127, + kTfLiteBuiltinCumsum = 128, + kTfLiteBuiltinCallOnce = 129, + kTfLiteBuiltinBroadcastTo = 130, + kTfLiteBuiltinRfft2d = 131, + kTfLiteBuiltinConv3d = 132, + kTfLiteBuiltinImag = 133, + kTfLiteBuiltinReal = 134, + kTfLiteBuiltinComplexAbs = 135, + kTfLiteBuiltinHashtable = 136, + kTfLiteBuiltinHashtableFind = 137, + kTfLiteBuiltinHashtableImport = 138, + kTfLiteBuiltinHashtableSize = 139, + kTfLiteBuiltinReduceAll = 140, + kTfLiteBuiltinConv3dTranspose = 141, + kTfLiteBuiltinVarHandle = 142, + kTfLiteBuiltinReadVariable = 143, + kTfLiteBuiltinAssignVariable = 144, + kTfLiteBuiltinBroadcastArgs = 145, + kTfLiteBuiltinRandomStandardNormal = 146, + kTfLiteBuiltinBucketize = 147, + kTfLiteBuiltinRandomUniform = 148, + kTfLiteBuiltinMultinomial = 149, + kTfLiteBuiltinGelu = 150, + kTfLiteBuiltinDynamicUpdateSlice = 151, + kTfLiteBuiltinRelu0To1 = 152, + kTfLiteBuiltinUnsortedSegmentProd = 153, + kTfLiteBuiltinUnsortedSegmentMax = 154, + kTfLiteBuiltinUnsortedSegmentSum = 155, + kTfLiteBuiltinAtan2 = 156, + kTfLiteBuiltinUnsortedSegmentMin = 157, + kTfLiteBuiltinSign = 158, +} TfLiteBuiltinOperator; + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus +#endif // TENSORFLOW_LITE_BUILTIN_OPS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h new file mode 100644 index 0000000..f1e511a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h @@ -0,0 +1,22 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_C_BUILTIN_OP_DATA_H_ +#define TENSORFLOW_LITE_C_BUILTIN_OP_DATA_H_ + +/// For documentation, see +/// third_party/tensorflow/lite/core/c/builtin_op_data.h. +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" // IWYU pragma: export + +#endif // TENSORFLOW_LITE_C_BUILTIN_OP_DATA_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/c_api_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/c_api_types.h new file mode 100644 index 0000000..4d3fab2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/c_api_types.h @@ -0,0 +1,26 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This file declares types used by the pure C inference API defined in c_api.h, +// some of which are also used in the C++ and C kernel and interpreter APIs. + +#ifndef TENSORFLOW_LITE_C_C_API_TYPES_H_ +#define TENSORFLOW_LITE_C_C_API_TYPES_H_ + +/// For documentation, see +/// third_party/tensorflow/lite/core/c/c_api_types.h. +#include "edge-impulse-sdk/tensorflow/lite/core/c/c_api_types.h" // IWYU pragma: export + +#endif // TENSORFLOW_LITE_C_C_API_TYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/common.c b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/common.c new file mode 100644 index 0000000..9efcd3a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/common.c @@ -0,0 +1,17 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +// Dummy file for backwards compatibility. +// See core/api/common.cc + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/common.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/common.h new file mode 100644 index 0000000..00c3768 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/c/common.h @@ -0,0 +1,43 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This file defines common C types and APIs for implementing operations, +// delegates and other constructs in TensorFlow Lite. The actual operations and +// delegates can be defined using C++, but the interface between the interpreter +// and the operations are C. +// +// Summary of abstractions +// TF_LITE_ENSURE - Self-sufficient error checking +// TfLiteStatus - Status reporting +// TfLiteIntArray - stores tensor shapes (dims), +// TfLiteContext - allows an op to access the tensors +// TfLiteTensor - tensor (a multidimensional array) +// TfLiteNode - a single node or operation +// TfLiteRegistration - the implementation of a conceptual operation. +// TfLiteDelegate - allows delegation of nodes to alternative backends. +// +// Some abstractions in this file are created and managed by Interpreter. +// +// NOTE: The order of values in these structs are "semi-ABI stable". New values +// should be added only to the end of structs and never reordered. + +#ifndef TENSORFLOW_LITE_C_COMMON_H_ +#define TENSORFLOW_LITE_C_COMMON_H_ + +/// For documentation, see +/// third_party/tensorflow/lite/core/c/common.h. +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" // IWYU pragma: export + +#endif // TENSORFLOW_LITE_C_COMMON_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/context_util.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/context_util.h new file mode 100644 index 0000000..8c97a8d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/context_util.h @@ -0,0 +1,54 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +/// \file +/// +/// This provides a few C++ helpers that are useful for manipulating C +/// structures in C++. +#ifndef TENSORFLOW_LITE_CONTEXT_UTIL_H_ +#define TENSORFLOW_LITE_CONTEXT_UTIL_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +namespace tflite { + +/// Provides a range iterable wrapper for TfLiteIntArray* (C lists) that TfLite +/// C api uses. +// Can't use the google array_view, since we can't depend on even +// absl for embedded device reasons. +class TfLiteIntArrayView { + public: + /// Construct a view of a TfLiteIntArray*. Note, `int_array` should be + /// non-null and this view does not take ownership of it. + explicit TfLiteIntArrayView(const TfLiteIntArray* int_array) + : int_array_(int_array) {} + + TfLiteIntArrayView(const TfLiteIntArrayView&) = default; + TfLiteIntArrayView& operator=(const TfLiteIntArrayView& rhs) = default; + + typedef const int* const_iterator; + const_iterator begin() const { return int_array_->data; } + const_iterator end() const { return &int_array_->data[int_array_->size]; } + size_t size() const { return end() - begin(); } + int operator[](size_t pos) const { return int_array_->data[pos]; } + + private: + const TfLiteIntArray* int_array_; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_CONTEXT_UTIL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/common.cpp new file mode 100644 index 0000000..67b8c6c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/common.cpp @@ -0,0 +1,354 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +#include "edge-impulse-sdk/tensorflow/lite/core/c/c_api_types.h" +#ifdef TF_LITE_TENSORFLOW_PROFILER +#include "edge-impulse-sdk/tensorflow/lite/tensorflow_profiler_logger.h" +#endif + +#ifndef TF_LITE_STATIC_MEMORY +#include +#include +#endif // TF_LITE_STATIC_MEMORY + +extern "C" { + +size_t TfLiteIntArrayGetSizeInBytes(int size) { + static TfLiteIntArray dummy; + + size_t computed_size = sizeof(dummy) + sizeof(dummy.data[0]) * size; +#if defined(_MSC_VER) + // Context for why this is needed is in http://b/189926408#comment21 + computed_size -= sizeof(dummy.data[0]); +#endif + return computed_size; +} + +int TfLiteIntArrayEqual(const TfLiteIntArray* a, const TfLiteIntArray* b) { + if (a == b) return 1; + if (a == nullptr || b == nullptr) return 0; + return TfLiteIntArrayEqualsArray(a, b->size, b->data); +} + +int TfLiteIntArrayEqualsArray(const TfLiteIntArray* a, int b_size, + const int b_data[]) { + if (a == nullptr) return (b_size == 0); + if (a->size != b_size) return 0; + int i = 0; + for (; i < a->size; i++) + if (a->data[i] != b_data[i]) return 0; + return 1; +} + +#ifndef TF_LITE_STATIC_MEMORY + +TfLiteIntArray* TfLiteIntArrayCreate(int size) { + size_t alloc_size = TfLiteIntArrayGetSizeInBytes(size); + if (alloc_size <= 0) return nullptr; + TfLiteIntArray* ret = (TfLiteIntArray*)malloc(alloc_size); + if (!ret) return ret; + ret->size = size; + return ret; +} + +TfLiteIntArray* TfLiteIntArrayCopy(const TfLiteIntArray* src) { + if (!src) return nullptr; + TfLiteIntArray* ret = TfLiteIntArrayCreate(src->size); + if (ret) { + memcpy(ret->data, src->data, src->size * sizeof(int)); + } + return ret; +} + +void TfLiteIntArrayFree(TfLiteIntArray* a) { free(a); } + +#endif // TF_LITE_STATIC_MEMORY + +int TfLiteFloatArrayGetSizeInBytes(int size) { + static TfLiteFloatArray dummy; + + int computed_size = sizeof(dummy) + sizeof(dummy.data[0]) * size; +#if defined(_MSC_VER) + // Context for why this is needed is in http://b/189926408#comment21 + computed_size -= sizeof(dummy.data[0]); +#endif + return computed_size; +} + +#ifndef TF_LITE_STATIC_MEMORY + +TfLiteFloatArray* TfLiteFloatArrayCreate(int size) { + TfLiteFloatArray* ret = + (TfLiteFloatArray*)malloc(TfLiteFloatArrayGetSizeInBytes(size)); + ret->size = size; + return ret; +} + +void TfLiteFloatArrayFree(TfLiteFloatArray* a) { free(a); } + +void TfLiteTensorDataFree(TfLiteTensor* t) { + if (t->allocation_type == kTfLiteDynamic || + t->allocation_type == kTfLitePersistentRo) { + if (t->data.raw) { +#ifdef TF_LITE_TENSORFLOW_PROFILER + tflite::PauseHeapMonitoring(/*pause=*/true); + tflite::OnTfLiteTensorDealloc(t); +#endif + free(t->data.raw); +#ifdef TF_LITE_TENSORFLOW_PROFILER + tflite::PauseHeapMonitoring(/*pause=*/false); +#endif + } + } + t->data.raw = nullptr; +} + +void TfLiteQuantizationFree(TfLiteQuantization* quantization) { + if (quantization->type == kTfLiteAffineQuantization) { + TfLiteAffineQuantization* q_params = + (TfLiteAffineQuantization*)(quantization->params); + if (q_params->scale) { + TfLiteFloatArrayFree(q_params->scale); + q_params->scale = nullptr; + } + if (q_params->zero_point) { + TfLiteIntArrayFree(q_params->zero_point); + q_params->zero_point = nullptr; + } + free(q_params); + } + quantization->params = nullptr; + quantization->type = kTfLiteNoQuantization; +} + +void TfLiteSparsityFree(TfLiteSparsity* sparsity) { + if (sparsity == nullptr) { + return; + } + + if (sparsity->traversal_order) { + TfLiteIntArrayFree(sparsity->traversal_order); + sparsity->traversal_order = nullptr; + } + + if (sparsity->block_map) { + TfLiteIntArrayFree(sparsity->block_map); + sparsity->block_map = nullptr; + } + + if (sparsity->dim_metadata) { + int i = 0; + for (; i < sparsity->dim_metadata_size; i++) { + TfLiteDimensionMetadata metadata = sparsity->dim_metadata[i]; + if (metadata.format == kTfLiteDimSparseCSR) { + TfLiteIntArrayFree(metadata.array_segments); + metadata.array_segments = nullptr; + TfLiteIntArrayFree(metadata.array_indices); + metadata.array_indices = nullptr; + } + } + free(sparsity->dim_metadata); + sparsity->dim_metadata = nullptr; + } + + free(sparsity); +} + +void TfLiteTensorFree(TfLiteTensor* t) { + TfLiteTensorDataFree(t); + if (t->dims) TfLiteIntArrayFree(t->dims); + t->dims = nullptr; + + if (t->dims_signature) { + TfLiteIntArrayFree((TfLiteIntArray*)t->dims_signature); + } + t->dims_signature = nullptr; + + TfLiteQuantizationFree(&t->quantization); + TfLiteSparsityFree(t->sparsity); + t->sparsity = nullptr; +} + +void TfLiteTensorReset(TfLiteType type, const char* name, TfLiteIntArray* dims, + TfLiteQuantizationParams quantization, char* buffer, + size_t size, TfLiteAllocationType allocation_type, + const void* allocation, bool is_variable, + TfLiteTensor* tensor) { + TfLiteTensorFree(tensor); + tensor->type = type; + tensor->name = name; + tensor->dims = dims; + tensor->params = quantization; + tensor->data.raw = buffer; + tensor->bytes = size; + tensor->allocation_type = allocation_type; + tensor->allocation = allocation; + tensor->is_variable = is_variable; + + tensor->quantization.type = kTfLiteNoQuantization; + tensor->quantization.params = nullptr; +} + +TfLiteStatus TfLiteTensorCopy(const TfLiteTensor* src, TfLiteTensor* dst) { + if (!src || !dst) return kTfLiteOk; + if (src->bytes != dst->bytes) return kTfLiteError; + if (src == dst) return kTfLiteOk; + + dst->type = src->type; + if (dst->dims) TfLiteIntArrayFree(dst->dims); + dst->dims = TfLiteIntArrayCopy(src->dims); + memcpy(dst->data.raw, src->data.raw, src->bytes); + dst->buffer_handle = src->buffer_handle; + dst->data_is_stale = src->data_is_stale; + dst->delegate = src->delegate; + + return kTfLiteOk; +} + +TfLiteStatus TfLiteTensorResizeMaybeCopy(size_t num_bytes, TfLiteTensor* tensor, + bool preserve_data) { + if (tensor->allocation_type != kTfLiteDynamic && + tensor->allocation_type != kTfLitePersistentRo) { + return kTfLiteOk; + } +#ifdef TF_LITE_TENSORFLOW_PROFILER + tflite::PauseHeapMonitoring(/*pause=*/true); +#endif + size_t alloc_bytes = num_bytes; + // TODO(b/145340303): Tensor data should be aligned. +#ifdef TFLITE_KERNEL_USE_XNNPACK + alloc_bytes += 16; // XNNPACK_EXTRA_BYTES = 16 +#endif + if (!tensor->data.data) { + tensor->data.data = (char*)malloc(alloc_bytes); +#ifdef TF_LITE_TENSORFLOW_PROFILER + tflite::OnTfLiteTensorAlloc(tensor, alloc_bytes); +#endif + } else if (num_bytes > tensor->bytes) { +#ifdef TF_LITE_TENSORFLOW_PROFILER + tflite::OnTfLiteTensorDealloc(tensor); +#endif + if (preserve_data) { + tensor->data.data = (char*)realloc(tensor->data.data, alloc_bytes); + } else { + // Calling free and malloc can be more efficient as it avoids needlessly + // copying the data when it is not required. + free(tensor->data.data); + tensor->data.data = (char*)malloc(alloc_bytes); + } +#ifdef TF_LITE_TENSORFLOW_PROFILER + tflite::OnTfLiteTensorAlloc(tensor, alloc_bytes); +#endif + } +#ifdef TF_LITE_TENSORFLOW_PROFILER + tflite::PauseHeapMonitoring(/*pause=*/false); +#endif + tensor->bytes = num_bytes; + if (tensor->data.data == nullptr && num_bytes != 0) { + // We are done allocating but tensor is pointing to null and a valid size + // was requested, so we error. + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus TfLiteTensorRealloc(size_t num_bytes, TfLiteTensor* tensor) { + return TfLiteTensorResizeMaybeCopy(num_bytes, tensor, true); +} +#endif // TF_LITE_STATIC_MEMORY + +const char* TfLiteTypeGetName(TfLiteType type) { + switch (type) { + case kTfLiteNoType: + return "NOTYPE"; + case kTfLiteFloat32: + return "FLOAT32"; + case kTfLiteUInt16: + return "UINT16"; + case kTfLiteInt16: + return "INT16"; + case kTfLiteInt32: + return "INT32"; + case kTfLiteUInt32: + return "UINT32"; + case kTfLiteUInt8: + return "UINT8"; + case kTfLiteInt8: + return "INT8"; + case kTfLiteInt64: + return "INT64"; + case kTfLiteUInt64: + return "UINT64"; + case kTfLiteBool: + return "BOOL"; + case kTfLiteComplex64: + return "COMPLEX64"; + case kTfLiteComplex128: + return "COMPLEX128"; + case kTfLiteString: + return "STRING"; + case kTfLiteFloat16: + return "FLOAT16"; + case kTfLiteFloat64: + return "FLOAT64"; + case kTfLiteResource: + return "RESOURCE"; + case kTfLiteVariant: + return "VARIANT"; + case kTfLiteInt4: + return "INT4"; + } + return "Unknown type"; +} + +TfLiteDelegate TfLiteDelegateCreate() { return TfLiteDelegate{}; } + +TfLiteOpaqueDelegate* TfLiteOpaqueDelegateCreate( + const TfLiteOpaqueDelegateBuilder* opaque_delegate_builder) { + if (!opaque_delegate_builder) return nullptr; + + TfLiteDelegate* result = new TfLiteDelegate{}; + result->opaque_delegate_builder = new TfLiteOpaqueDelegateBuilder{}; + *(result->opaque_delegate_builder) = *opaque_delegate_builder; + + return reinterpret_cast(result); +} + +void TfLiteOpaqueDelegateDelete(TfLiteOpaqueDelegate* opaque_delegate) { + if (!opaque_delegate) return; + + const TfLiteDelegate* tflite_delegate = + reinterpret_cast(opaque_delegate); + delete tflite_delegate->opaque_delegate_builder; + delete tflite_delegate; +} + +void* TfLiteOpaqueDelegateGetData(const TfLiteOpaqueDelegate* delegate) { + if (!delegate) return nullptr; + + // The following cast is safe only because this code is part of the + // TF Lite runtime implementation. Apps using TF Lite should not rely on + // 'TfLiteOpaqueDelegate' and 'TfLiteDelegate' being equivalent. + const auto* tflite_delegate = + reinterpret_cast(delegate); + + if (!tflite_delegate->opaque_delegate_builder) return tflite_delegate->data_; + + return tflite_delegate->opaque_delegate_builder->data; +} + +} // extern "C" diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.cpp new file mode 100644 index 0000000..e6b84a6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.cpp @@ -0,0 +1,38 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include + +namespace tflite { + +int ErrorReporter::Report(const char* format, ...) { + va_list args; + va_start(args, format); + int code = Report(format, args); + va_end(args); + return code; +} + +// TODO(aselle): Make the name of ReportError on context the same, so +// we can use the ensure functions w/o a context and w/ a reporter. +int ErrorReporter::ReportError(void*, const char* format, ...) { + va_list args; + va_start(args, format); + int code = Report(format, args); + va_end(args); + return code; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h new file mode 100644 index 0000000..99ab8cf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h @@ -0,0 +1,72 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_CORE_API_ERROR_REPORTER_H_ +#define TENSORFLOW_LITE_CORE_API_ERROR_REPORTER_H_ + +#include + +namespace tflite { + +/// A functor that reports error to supporting system. Invoked similar to +/// printf. +/// +/// Usage: +/// ErrorReporter foo; +/// foo.Report("test %d", 5); +/// or +/// va_list args; +/// foo.Report("test %d", args); // where args is va_list +/// +/// Subclass ErrorReporter to provide another reporting destination. +/// For example, if you have a GUI program, you might redirect to a buffer +/// that drives a GUI error log box. +class ErrorReporter { + public: + virtual ~ErrorReporter() = default; + /// Converts `args` to character equivalents according to `format` string, + /// constructs the error string and report it. + /// Returns number of characters written or zero on success, and negative + /// number on error. + virtual int Report(const char* format, va_list args) = 0; + + /// Converts arguments to character equivalents according to `format` string, + /// constructs the error string and report it. + /// Returns number of characters written or zero on success, and negative + /// number on error. + int Report(const char* format, ...); + + /// Equivalent to `Report` above. The additional `void*` parameter is unused. + /// This method is for compatibility with macros that takes `TfLiteContext`, + /// like TF_LITE_ENSURE and related macros. + int ReportError(void*, const char* format, ...); +}; + +} // namespace tflite + +// You should not make bare calls to the error reporter, instead use the +// TF_LITE_REPORT_ERROR macro, since this allows message strings to be +// stripped when the binary size has to be optimized. If you are looking to +// reduce binary size, define TF_LITE_STRIP_ERROR_STRINGS when compiling and +// every call will be stubbed out, taking no memory. +#ifndef TF_LITE_STRIP_ERROR_STRINGS +#define TF_LITE_REPORT_ERROR(reporter, ...) \ + do { \ + static_cast(reporter)->Report(__VA_ARGS__); \ + } while (false) +#else // TF_LITE_STRIP_ERROR_STRINGS +#define TF_LITE_REPORT_ERROR(reporter, ...) +#endif // TF_LITE_STRIP_ERROR_STRINGS + +#endif // TENSORFLOW_LITE_CORE_API_ERROR_REPORTER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.cpp new file mode 100644 index 0000000..31d4af9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.cpp @@ -0,0 +1,2518 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.h" + +#include +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h" + +namespace tflite { + +namespace { + +// Utility class for safely allocating POD data. This is useful for avoiding +// leaks in cases where op params are allocated but fail to propagate to the +// parsed op data (e.g., when model parameters are invalid). +class SafeBuiltinDataAllocator { + public: + class BuiltinDataDeleter { + public: + explicit BuiltinDataDeleter(BuiltinDataAllocator* allocator) + : allocator_(allocator) {} + + void operator()(void* data) { allocator_->Deallocate(data); } + + private: + BuiltinDataAllocator* allocator_; + }; + + template + using BuiltinDataPtr = std::unique_ptr; + + explicit SafeBuiltinDataAllocator(BuiltinDataAllocator* allocator) + : allocator_(allocator) {} + + template + BuiltinDataPtr Allocate() { + return BuiltinDataPtr(allocator_->AllocatePOD(), + BuiltinDataDeleter(allocator_)); + } + + private: + BuiltinDataAllocator* allocator_; +}; + +// All the Parse functions take some pointers as params and this function has +// the common DCHECKs to catch if any of those are nullptr. +void CheckParsePointerParams(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + TFLITE_DCHECK(op != nullptr); + TFLITE_DCHECK(error_reporter != nullptr); + TFLITE_DCHECK(allocator != nullptr); + TFLITE_DCHECK(builtin_data != nullptr); +} + +// Copies the contents from the flatbuffer int vector `flatbuffer` into the +// int array `buffer`. `flat_vector` and `buffer` represent the same +// configuration operation for a given operation. +TfLiteStatus FlatBufferIntVectorToArray( + int max_size_of_buffer, const flatbuffers::Vector* flat_vector, + int* buffer, ErrorReporter* error_reporter, const char* op_name) { + if (!flat_vector) { + TF_LITE_REPORT_ERROR(error_reporter, + "Input array not provided for operation '%s'.\n", + op_name); + return kTfLiteError; + } else { + size_t num_dimensions = flat_vector->size(); + if (num_dimensions > max_size_of_buffer / sizeof(int)) { + TF_LITE_REPORT_ERROR( + error_reporter, + "Found too many dimensions in the input array of operation '%s'.\n", + op_name); + return kTfLiteError; + } else { + for (size_t i = 0; i < num_dimensions; ++i) { + buffer[i] = flat_vector->Get(i); + } + } + } + return kTfLiteOk; +} + +// Converts the flatbuffer activation to what is used at runtime. +TfLiteFusedActivation ConvertActivation(ActivationFunctionType activation) { + switch (activation) { + case ActivationFunctionType_NONE: + return kTfLiteActNone; + case ActivationFunctionType_RELU: + return kTfLiteActRelu; + case ActivationFunctionType_RELU_N1_TO_1: + return kTfLiteActReluN1To1; + case ActivationFunctionType_RELU6: + return kTfLiteActRelu6; + case ActivationFunctionType_TANH: + return kTfLiteActTanh; + case ActivationFunctionType_SIGN_BIT: + return kTfLiteActSignBit; + } + return kTfLiteActNone; +} + +// Converts the flatbuffer padding enum to what is used at runtime. +TfLitePadding ConvertPadding(Padding padding) { + switch (padding) { + case Padding_SAME: + return kTfLitePaddingSame; + case Padding_VALID: + return kTfLitePaddingValid; + } + return kTfLitePaddingUnknown; +} + +// Converts the flatbuffer mirror padding enum to what is used at runtime. +TfLiteMirrorPaddingMode ConvertMirrorPadding(MirrorPadMode padding) { + switch (padding) { + case MirrorPadMode_REFLECT: + return kTfLiteMirrorPaddingReflect; + case MirrorPadMode_SYMMETRIC: + return kTfLiteMirrorPaddingSymmetric; + } + return kTfLiteMirrorPaddingUnknown; +} + +#ifndef TF_LITE_STATIC_MEMORY +TfLiteStatus ParseOpDataTfLite(const Operator* op, BuiltinOperator op_type, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + auto parseLSHProjectionType = [](LSHProjectionType type) { + switch (type) { + case LSHProjectionType_SPARSE: + return kTfLiteLshProjectionSparse; + case LSHProjectionType_DENSE: + return kTfLiteLshProjectionDense; + default: + return kTfLiteLshProjectionUnknown; + } + }; + auto parseCombinerType = [](CombinerType type) { + switch (type) { + case CombinerType_MEAN: + return kTfLiteCombinerTypeMean; + case CombinerType_SQRTN: + return kTfLiteCombinerTypeSqrtn; + case CombinerType_SUM: + default: + return kTfLiteCombinerTypeSum; + } + }; + + SafeBuiltinDataAllocator safe_allocator(allocator); + *builtin_data = nullptr; + switch (op_type) { + case BuiltinOperator_ABS: { + return ParseAbs(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_ADD: { + return ParseAdd(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_ADD_N: { + return ParseAddN(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_ARG_MAX: { + return ParseArgMax(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_ARG_MIN: { + return ParseArgMin(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_ASSIGN_VARIABLE: { + return ParseAssignVariable(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_AVERAGE_POOL_2D: { + return ParsePool(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_BATCH_MATMUL: { + return ParseBatchMatMul(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_BATCH_TO_SPACE_ND: { + return ParseBatchToSpaceNd(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_BROADCAST_ARGS: { + return ParseBroadcastArgs(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_BROADCAST_TO: { + return ParseBroadcastTo(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_CALL_ONCE: { + return ParseCallOnce(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_CEIL: { + return ParseCeil(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_CONCATENATION: { + return ParseConcatenation(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_CONV_2D: { + return ParseConv2D(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_CUMSUM: { + return ParseCumsum(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_DEPTH_TO_SPACE: { + return ParseDepthToSpace(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_DEPTHWISE_CONV_2D: { + return ParseDepthwiseConv2D(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_DEQUANTIZE: { + return ParseDequantize(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_DIV: { + return ParseDiv(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_ELU: { + return ParseElu(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_EXP: { + return ParseExp(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_EXPAND_DIMS: { + return ParseExpandDims(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_FILL: { + return ParseFill(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_FLOOR: { + return ParseFloor(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_FLOOR_DIV: { + return ParseFloorDiv(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_FLOOR_MOD: { + return ParseFloorMod(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_FULLY_CONNECTED: { + return ParseFullyConnected(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_GATHER_ND: { + return ParseGatherNd(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_GREATER: { + return ParseGreater(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_GREATER_EQUAL: { + return ParseGreaterEqual(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_HARD_SWISH: { + return ParseHardSwish(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_L2_NORMALIZATION: { + return ParseL2Normalization(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_L2_POOL_2D: { + return ParsePool(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LEAKY_RELU: { + return ParseLeakyRelu(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LESS: { + return ParseLess(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LESS_EQUAL: { + return ParseLessEqual(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LOG: { + return ParseLog(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LOGICAL_AND: { + return ParseLogicalAnd(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LOGICAL_NOT: { + return ParseLogicalNot(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LOGICAL_OR: { + return ParseLogicalOr(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LOGISTIC: { + return ParseLogistic(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LOG_SOFTMAX: { + return ParseLogSoftmax(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_LSTM: { + return ParseLSTM(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_MAXIMUM: { + return ParseMaximum(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_MAX_POOL_2D: { + return ParsePool(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_MIRROR_PAD: { + return ParseMirrorPad(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_MEAN: { + return ParseReducer(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_MINIMUM: { + return ParseMinimum(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_MUL: { + return ParseMul(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_NEG: { + return ParseNeg(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_NOT_EQUAL: { + return ParseNotEqual(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_PACK: { + return ParsePack(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_PAD: { + return ParsePad(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_PADV2: { + return ParsePadV2(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_POW: { + return ParsePow(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_PRELU: { + return ParsePrelu(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_QUANTIZE: { + return ParseQuantize(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_READ_VARIABLE: { + return ParseReadVariable(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_REDUCE_ANY: { + return ParseReducer(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_REDUCE_ALL: { + return ParseReducer(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_REDUCE_MAX: { + return ParseReducer(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_REDUCE_MIN: { + return ParseReducer(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_REDUCE_PROD: { + return ParseReducer(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_RELU: { + return ParseRelu(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_RELU6: { + return ParseRelu6(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_RESHAPE: { + return ParseReshape(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_RESIZE_BILINEAR: { + return ParseResizeBilinear(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_RESIZE_NEAREST_NEIGHBOR: { + return ParseResizeNearestNeighbor(op, error_reporter, allocator, + builtin_data); + } + + case BuiltinOperator_ROUND: { + return ParseRound(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_RSQRT: { + return ParseRsqrt(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SELECT_V2: { + return ParseSelectV2(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SHAPE: { + return ParseShape(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SIN: { + return ParseSin(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SOFTMAX: { + return ParseSoftmax(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SPACE_TO_BATCH_ND: { + return ParseSpaceToBatchNd(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SPACE_TO_DEPTH: { + return ParseSpaceToDepth(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SPLIT: { + return ParseSplit(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SPLIT_V: { + return ParseSplitV(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SQRT: { + return ParseSqrt(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SQUARE: { + return ParseSquare(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SQUARED_DIFFERENCE: { + return ParseSquaredDifference(op, error_reporter, allocator, + builtin_data); + } + + case BuiltinOperator_SQUEEZE: { + return ParseSqueeze(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_STRIDED_SLICE: { + return ParseStridedSlice(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SUB: { + return ParseSub(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SUM: { + return ParseReducer(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_SVDF: { + return ParseSvdf(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_TANH: { + return ParseTanh(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_TRANSPOSE_CONV: { + return ParseTransposeConv(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_UNPACK: { + return ParseUnpack(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_VAR_HANDLE: { + return ParseVarHandle(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_ZEROS_LIKE: { + return ParseZerosLike(op, error_reporter, allocator, builtin_data); + } + + case BuiltinOperator_CAST: { + return ParseCast(op, error_reporter, allocator, builtin_data); + } + case BuiltinOperator_LSH_PROJECTION: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* lshParams = + op->builtin_options_as_LSHProjectionOptions()) { + params->type = parseLSHProjectionType(lshParams->type()); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* sequence_rnn_params = + op->builtin_options_as_SequenceRNNOptions()) { + params->activation = + ConvertActivation(sequence_rnn_params->fused_activation_function()); + params->time_major = sequence_rnn_params->time_major(); + params->asymmetric_quantize_inputs = + sequence_rnn_params->asymmetric_quantize_inputs(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN: { + auto params = + safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* bidi_sequence_rnn_params = + op->builtin_options_as_BidirectionalSequenceRNNOptions()) { + params->activation = ConvertActivation( + bidi_sequence_rnn_params->fused_activation_function()); + params->time_major = bidi_sequence_rnn_params->time_major(); + params->merge_outputs = bidi_sequence_rnn_params->merge_outputs(); + params->asymmetric_quantize_inputs = + bidi_sequence_rnn_params->asymmetric_quantize_inputs(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_RNN: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* rnn_params = op->builtin_options_as_RNNOptions()) { + params->activation = + ConvertActivation(rnn_params->fused_activation_function()); + params->asymmetric_quantize_inputs = + rnn_params->asymmetric_quantize_inputs(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_EMBEDDING_LOOKUP_SPARSE: { + auto params = + safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* embedding_params = + op->builtin_options_as_EmbeddingLookupSparseOptions()) { + params->combiner = parseCombinerType(embedding_params->combiner()); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + + case BuiltinOperator_HASHTABLE_LOOKUP: + // no-op. + return kTfLiteOk; + + case BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* schema_params = + op->builtin_options_as_LocalResponseNormalizationOptions()) { + params->radius = schema_params->radius(); + params->bias = schema_params->bias(); + params->alpha = schema_params->alpha(); + params->beta = schema_params->beta(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM: { + return ParseUnidirectionalSequenceLSTM(op, error_reporter, allocator, + builtin_data); + } + case BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM: { + auto params = + safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* bidi_lstm_params = + op->builtin_options_as_BidirectionalSequenceLSTMOptions()) { + params->activation = + ConvertActivation(bidi_lstm_params->fused_activation_function()); + params->cell_clip = bidi_lstm_params->cell_clip(); + params->proj_clip = bidi_lstm_params->proj_clip(); + params->merge_outputs = bidi_lstm_params->merge_outputs(); + params->time_major = bidi_lstm_params->time_major(); + params->asymmetric_quantize_inputs = + bidi_lstm_params->asymmetric_quantize_inputs(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_SKIP_GRAM: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* skip_gram_params = + op->builtin_options_as_SkipGramOptions()) { + params->ngram_size = skip_gram_params->ngram_size(); + params->max_skip_size = skip_gram_params->max_skip_size(); + params->include_all_ngrams = skip_gram_params->include_all_ngrams(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + + case BuiltinOperator_GATHER: { + return ParseGather(op, error_reporter, allocator, builtin_data); + } + case BuiltinOperator_SPARSE_TO_DENSE: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* sparse_to_dense_params = + op->builtin_options_as_SparseToDenseOptions()) { + params->validate_indices = sparse_to_dense_params->validate_indices(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_DELEGATE: { + TF_LITE_REPORT_ERROR(error_reporter, + "DELEGATE op shouldn't exist in model."); + return kTfLiteError; + } + case BuiltinOperator_FAKE_QUANT: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* schema_params = + op->builtin_options_as_FakeQuantOptions()) { + params->min = schema_params->min(); + params->max = schema_params->max(); + params->num_bits = schema_params->num_bits(); + params->narrow_range = schema_params->narrow_range(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_ONE_HOT: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* schema_params = op->builtin_options_as_OneHotOptions()) { + params->axis = schema_params->axis(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_UNIQUE: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + const auto* unique_params = op->builtin_options_as_UniqueOptions(); + if (unique_params != nullptr) { + params->index_out_type = + unique_params->idx_out_type() == tflite::TensorType_INT64 + ? TfLiteType::kTfLiteInt64 + : TfLiteType::kTfLiteInt32; + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_REVERSE_SEQUENCE: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* reverse_seq_params = + op->builtin_options_as_ReverseSequenceOptions()) { + params->seq_dim = reverse_seq_params->seq_dim(); + params->batch_dim = reverse_seq_params->batch_dim(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_IF: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* if_params = op->builtin_options_as_IfOptions()) { + params->then_subgraph_index = if_params->then_subgraph_index(); + params->else_subgraph_index = if_params->else_subgraph_index(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_WHILE: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* while_params = op->builtin_options_as_WhileOptions()) { + params->cond_subgraph_index = while_params->cond_subgraph_index(); + params->body_subgraph_index = while_params->body_subgraph_index(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_CONV_3D: + case BuiltinOperator_CONV_3D_TRANSPOSE: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* conv3d_params = op->builtin_options_as_Conv3DOptions()) { + params->padding = ConvertPadding(conv3d_params->padding()); + params->activation = + ConvertActivation(conv3d_params->fused_activation_function()); + params->stride_depth = conv3d_params->stride_d(); + params->stride_height = conv3d_params->stride_h(); + params->stride_width = conv3d_params->stride_w(); + params->dilation_depth_factor = conv3d_params->dilation_d_factor(); + params->dilation_height_factor = conv3d_params->dilation_h_factor(); + params->dilation_width_factor = conv3d_params->dilation_w_factor(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_HASHTABLE: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* hashtable_params = + op->builtin_options_as_HashtableOptions()) { + params->table_id = hashtable_params->table_id(); + TF_LITE_ENSURE_STATUS(ConvertTensorType( + hashtable_params->key_dtype(), ¶ms->key_dtype, error_reporter)); + TF_LITE_ENSURE_STATUS(ConvertTensorType(hashtable_params->value_dtype(), + ¶ms->value_dtype, + error_reporter)); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_MULTINOMIAL: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* multinomial_params = + op->builtin_options_as_RandomOptions()) { + params->seed = multinomial_params->seed(); + params->seed2 = multinomial_params->seed2(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_RANDOM_STANDARD_NORMAL: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* random_std_normal_params = + op->builtin_options_as_RandomOptions()) { + params->seed = random_std_normal_params->seed(); + params->seed2 = random_std_normal_params->seed2(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_BUCKETIZE: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* bucketize_params = + op->builtin_options_as_BucketizeOptions()) { + const flatbuffers::Vector* boundaries = + bucketize_params->boundaries(); + if (boundaries == nullptr) { + TF_LITE_REPORT_ERROR( + error_reporter, + "boundaries array not provided for operation 'bucketize'.\n"); + return kTfLiteError; + } + params->num_boundaries = boundaries->size(); + if (boundaries->data() == nullptr) { + TF_LITE_REPORT_ERROR(error_reporter, + "boundaries.data() returned nullptr for " + "operation 'bucketize'.\n"); + return kTfLiteError; + } + params->boundaries = boundaries->data(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_RANDOM_UNIFORM: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* random_uniform_params = + op->builtin_options_as_RandomOptions()) { + params->seed = random_uniform_params->seed(); + params->seed2 = random_uniform_params->seed2(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + case BuiltinOperator_GELU: { + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* gelu_params = op->builtin_options_as_GeluOptions()) { + params->approximate = gelu_params->approximate(); + } + *builtin_data = params.release(); + return kTfLiteOk; + } + // Below are the ops with no builtin_data structure. + // TODO(aselle): Implement call in BuiltinOptions, but nullptrs are + // ok for now, since there is no call implementation either. + case BuiltinOperator_CALL: + case BuiltinOperator_COMPLEX_ABS: + case BuiltinOperator_CONCAT_EMBEDDINGS: + case BuiltinOperator_COS: + case BuiltinOperator_CUSTOM: + case BuiltinOperator_DENSIFY: + case BuiltinOperator_DYNAMIC_UPDATE_SLICE: + case BuiltinOperator_EMBEDDING_LOOKUP: + case BuiltinOperator_EQUAL: + case BuiltinOperator_HASHTABLE_FIND: + case BuiltinOperator_HASHTABLE_IMPORT: + case BuiltinOperator_HASHTABLE_SIZE: + case BuiltinOperator_IMAG: + case BuiltinOperator_MATRIX_DIAG: + case BuiltinOperator_MATRIX_SET_DIAG: + case BuiltinOperator_NON_MAX_SUPPRESSION_V4: + case BuiltinOperator_NON_MAX_SUPPRESSION_V5: + case BuiltinOperator_RELU_N1_TO_1: + case BuiltinOperator_RELU_0_TO_1: + case BuiltinOperator_SCATTER_ND: + case BuiltinOperator_SELECT: + case BuiltinOperator_SLICE: + case BuiltinOperator_TILE: + case BuiltinOperator_TOPK_V2: + case BuiltinOperator_TRANSPOSE: + case BuiltinOperator_RANGE: + case BuiltinOperator_RANK: + case BuiltinOperator_REAL: + case BuiltinOperator_RFFT2D: + case BuiltinOperator_SEGMENT_SUM: + case BuiltinOperator_REVERSE_V2: + case BuiltinOperator_UNSORTED_SEGMENT_MAX: + case BuiltinOperator_UNSORTED_SEGMENT_MIN: + case BuiltinOperator_UNSORTED_SEGMENT_PROD: + case BuiltinOperator_UNSORTED_SEGMENT_SUM: + case BuiltinOperator_ATAN2: + case BuiltinOperator_SIGN: + case BuiltinOperator_WHERE: + return kTfLiteOk; + case BuiltinOperator_PLACEHOLDER_FOR_GREATER_OP_CODES: + return kTfLiteError; + } + return kTfLiteError; +} // NOLINT[readability/fn_size] +#endif // !defined(TF_LITE_STATIC_MEMORY) +} // namespace + +TfLiteStatus ConvertTensorType(TensorType tensor_type, TfLiteType* type, + ErrorReporter* error_reporter) { + switch (tensor_type) { + case TensorType_FLOAT16: + *type = kTfLiteFloat16; + return kTfLiteOk; + case TensorType_FLOAT32: + *type = kTfLiteFloat32; + return kTfLiteOk; + case TensorType_FLOAT64: + *type = kTfLiteFloat64; + return kTfLiteOk; + case TensorType_INT16: + *type = kTfLiteInt16; + return kTfLiteOk; + case TensorType_UINT16: + *type = kTfLiteUInt16; + return kTfLiteOk; + case TensorType_INT32: + *type = kTfLiteInt32; + return kTfLiteOk; + case TensorType_UINT32: + *type = kTfLiteUInt32; + return kTfLiteOk; + case TensorType_UINT8: + *type = kTfLiteUInt8; + return kTfLiteOk; + case TensorType_INT8: + *type = kTfLiteInt8; + return kTfLiteOk; + case TensorType_INT64: + *type = kTfLiteInt64; + return kTfLiteOk; + case TensorType_UINT64: + *type = kTfLiteUInt64; + return kTfLiteOk; + case TensorType_STRING: + *type = kTfLiteString; + return kTfLiteOk; + case TensorType_BOOL: + *type = kTfLiteBool; + return kTfLiteOk; + case TensorType_COMPLEX64: + *type = kTfLiteComplex64; + return kTfLiteOk; + case TensorType_COMPLEX128: + *type = kTfLiteComplex128; + return kTfLiteOk; + case TensorType_RESOURCE: + *type = kTfLiteResource; + return kTfLiteOk; + case TensorType_VARIANT: + *type = kTfLiteVariant; + return kTfLiteOk; + case TensorType_INT4: + *type = kTfLiteInt4; + return kTfLiteOk; + default: + *type = kTfLiteNoType; + TF_LITE_REPORT_ERROR(error_reporter, + "Unsupported data type %d in tensor\n", tensor_type); + return kTfLiteError; + } +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseAbs(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseAdd(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const AddOptions* schema_params = op->builtin_options_as_AddOptions(); + + if (schema_params != nullptr) { + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + params->pot_scale_int16 = schema_params->pot_scale_int16(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseAddN(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + return kTfLiteOk; +} + +TfLiteStatus ParseArgMax(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ArgMaxOptions* schema_params = op->builtin_options_as_ArgMaxOptions(); + + if (schema_params != nullptr) { + TF_LITE_ENSURE_STATUS(ConvertTensorType( + schema_params->output_type(), ¶ms->output_type, error_reporter)); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseArgMin(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ArgMinOptions* schema_params = op->builtin_options_as_ArgMinOptions(); + + if (schema_params != nullptr) { + TF_LITE_ENSURE_STATUS(ConvertTensorType( + schema_params->output_type(), ¶ms->output_type, error_reporter)); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseAssignVariable(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseBatchMatMul(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* bmm_params = op->builtin_options_as_BatchMatMulOptions()) { + params->adj_x = bmm_params->adj_x(); + params->adj_y = bmm_params->adj_y(); + params->asymmetric_quantize_inputs = + bmm_params->asymmetric_quantize_inputs(); + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseBatchToSpaceNd(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseBroadcastArgs(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseBroadcastTo(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseCallOnce(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const CallOnceOptions* schema_params = + op->builtin_options_as_CallOnceOptions(); + + if (schema_params != nullptr) { + params->init_subgraph_index = schema_params->init_subgraph_index(); + + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseCast(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* schema_params = op->builtin_options_as_CastOptions()) { + TF_LITE_ENSURE_STATUS(ConvertTensorType( + schema_params->in_data_type(), ¶ms->in_data_type, error_reporter)); + TF_LITE_ENSURE_STATUS(ConvertTensorType(schema_params->out_data_type(), + ¶ms->out_data_type, + error_reporter)); + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseCeil(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseConcatenation(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ConcatenationOptions* schema_params = + op->builtin_options_as_ConcatenationOptions(); + + if (schema_params != nullptr) { + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + params->axis = schema_params->axis(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseComplexAbs(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseConv2D(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const Conv2DOptions* schema_params = op->builtin_options_as_Conv2DOptions(); + + if (schema_params != nullptr) { + params->padding = ConvertPadding(schema_params->padding()); + params->stride_width = schema_params->stride_w(); + params->stride_height = schema_params->stride_h(); + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + + params->dilation_width_factor = schema_params->dilation_w_factor(); + params->dilation_height_factor = schema_params->dilation_h_factor(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseCumsum(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* cumsum_params = op->builtin_options_as_CumsumOptions()) { + params->exclusive = cumsum_params->exclusive(); + params->reverse = cumsum_params->reverse(); + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseCos(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseDepthToSpace(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const auto* schema_params = op->builtin_options_as_DepthToSpaceOptions(); + if (schema_params != nullptr) { + params->block_size = schema_params->block_size(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseDepthwiseConv2D(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const DepthwiseConv2DOptions* schema_params = + op->builtin_options_as_DepthwiseConv2DOptions(); + + if (schema_params != nullptr) { + params->padding = ConvertPadding(schema_params->padding()); + params->stride_width = schema_params->stride_w(); + params->stride_height = schema_params->stride_h(); + params->depth_multiplier = schema_params->depth_multiplier(); + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + + params->dilation_width_factor = schema_params->dilation_w_factor(); + params->dilation_height_factor = schema_params->dilation_h_factor(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseDequantize(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseDiv(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* schema_params = op->builtin_options_as_DivOptions()) { + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseElu(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseEqual(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseExp(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseExpandDims(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseFill(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseFloor(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseFloorDiv(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseFloorMod(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseFullyConnected(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const FullyConnectedOptions* schema_params = + op->builtin_options_as_FullyConnectedOptions(); + + if (schema_params != nullptr) { + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + params->keep_num_dims = schema_params->keep_num_dims(); + params->asymmetric_quantize_inputs = + schema_params->asymmetric_quantize_inputs(); + + switch (schema_params->weights_format()) { + case FullyConnectedOptionsWeightsFormat_DEFAULT: + params->weights_format = kTfLiteFullyConnectedWeightsFormatDefault; + break; + case FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8: + params->weights_format = + kTfLiteFullyConnectedWeightsFormatShuffled4x16Int8; + break; + default: + TF_LITE_REPORT_ERROR(error_reporter, + "Unhandled fully-connected weights format."); + return kTfLiteError; + } + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseGather(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + params->axis = 0; + params->batch_dims = 0; + if (const auto* gather_params = op->builtin_options_as_GatherOptions()) { + params->axis = gather_params->axis(); + params->batch_dims = gather_params->batch_dims(); + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseGatherNd(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseGreater(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseGreaterEqual(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseHardSwish(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseImag(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseIf(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const IfOptions* schema_params = op->builtin_options_as_IfOptions(); + + if (schema_params != nullptr) { + params->then_subgraph_index = schema_params->then_subgraph_index(); + params->else_subgraph_index = schema_params->else_subgraph_index(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseL2Normalization(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const L2NormOptions* schema_params = op->builtin_options_as_L2NormOptions(); + + if (schema_params != nullptr) { + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseLeakyRelu(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* leaky_relu_params = + op->builtin_options_as_LeakyReluOptions()) { + params->alpha = leaky_relu_params->alpha(); + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLess(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLessEqual(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLog(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLogicalAnd(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLogicalNot(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLogicalOr(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLogistic(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseLogSoftmax(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseLSTM(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* lstm_params = op->builtin_options_as_LSTMOptions()) { + params->activation = + ConvertActivation(lstm_params->fused_activation_function()); + params->cell_clip = lstm_params->cell_clip(); + params->proj_clip = lstm_params->proj_clip(); + switch (lstm_params->kernel_type()) { + case LSTMKernelType_FULL: + params->kernel_type = kTfLiteLSTMFullKernel; + break; + case LSTMKernelType_BASIC: + params->kernel_type = kTfLiteLSTMBasicKernel; + break; + default: + TF_LITE_REPORT_ERROR(error_reporter, "Unhandled LSTM kernel type: %d", + lstm_params->kernel_type()); + return kTfLiteError; + } + params->asymmetric_quantize_inputs = + lstm_params->asymmetric_quantize_inputs(); + } else { + TF_LITE_REPORT_ERROR(error_reporter, "No valid LSTM builtin options exist"); + return kTfLiteError; + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseMaximum(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseMinimum(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseMirrorPad(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const MirrorPadOptions* schema_params = + op->builtin_options_as_MirrorPadOptions(); + + if (schema_params != nullptr) { + params->mode = ConvertMirrorPadding(schema_params->mode()); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseMul(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const MulOptions* schema_params = op->builtin_options_as_MulOptions(); + + if (schema_params != nullptr) { + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseNeg(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseNotEqual(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParsePack(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const PackOptions* schema_params = op->builtin_options_as_PackOptions(); + + if (schema_params != nullptr) { + params->values_count = schema_params->values_count(); + params->axis = schema_params->axis(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParsePad(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParsePadV2(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +TfLiteStatus ParsePool(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const Pool2DOptions* schema_params = op->builtin_options_as_Pool2DOptions(); + + if (schema_params != nullptr) { + params->padding = ConvertPadding(schema_params->padding()); + params->stride_width = schema_params->stride_w(); + params->stride_height = schema_params->stride_h(); + params->filter_width = schema_params->filter_width(); + params->filter_height = schema_params->filter_height(); + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParsePow(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParsePrelu(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseQuantize(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseReal(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseReadVariable(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseReducer(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ReducerOptions* schema_params = op->builtin_options_as_ReducerOptions(); + + if (schema_params != nullptr) { + params->keep_dims = schema_params->keep_dims(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseRelu(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseRelu6(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseReshape(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ReshapeOptions* schema_params = op->builtin_options_as_ReshapeOptions(); + + if (schema_params != nullptr) { + const flatbuffers::Vector* new_shape = schema_params->new_shape(); + if (new_shape != nullptr) { + TF_LITE_ENSURE_STATUS( + FlatBufferIntVectorToArray(sizeof(params->shape), new_shape, + params->shape, error_reporter, "reshape")); + params->num_dimensions = new_shape->size(); + } else { + // TODO(b/157480169) TODO(b/147203660): We should either return + // kTfLiteError or fill in some reasonable defaults in the params struct. + // We are not doing so until we better undertand the ramifications of + // changing the legacy behavior. + } + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseResizeBilinear(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ResizeBilinearOptions* schema_params = + op->builtin_options_as_ResizeBilinearOptions(); + + if (schema_params != nullptr) { + params->align_corners = schema_params->align_corners(); + params->half_pixel_centers = schema_params->half_pixel_centers(); + } else { + params->align_corners = false; + params->half_pixel_centers = false; + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseResizeNearestNeighbor(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ResizeNearestNeighborOptions* schema_params = + op->builtin_options_as_ResizeNearestNeighborOptions(); + + if (schema_params != nullptr) { + params->align_corners = schema_params->align_corners(); + params->half_pixel_centers = schema_params->half_pixel_centers(); + } else { + params->align_corners = false; + params->half_pixel_centers = false; + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseRfft2D(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseRound(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseRsqrt(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSelect(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSelectV2(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseShape(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const ShapeOptions* schema_params = op->builtin_options_as_ShapeOptions(); + + if (schema_params != nullptr) { + TF_LITE_ENSURE_STATUS(ConvertTensorType(schema_params->out_type(), + ¶ms->out_type, error_reporter)); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSin(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSlice(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseSoftmax(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const SoftmaxOptions* schema_params = op->builtin_options_as_SoftmaxOptions(); + + if (schema_params != nullptr) { + params->beta = schema_params->beta(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSpaceToBatchNd(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseSpaceToDepth(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const auto* schema_params = op->builtin_options_as_SpaceToDepthOptions(); + if (schema_params != nullptr) { + params->block_size = schema_params->block_size(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseSplit(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const SplitOptions* schema_params = op->builtin_options_as_SplitOptions(); + + if (schema_params != nullptr) { + params->num_splits = schema_params->num_splits(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseSplitV(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + SafeBuiltinDataAllocator safe_allocator(allocator); + + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const SplitVOptions* schema_params = op->builtin_options_as_SplitVOptions(); + + if (schema_params != nullptr) { + params->num_splits = schema_params->num_splits(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseUnidirectionalSequenceLSTM(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + SafeBuiltinDataAllocator safe_allocator(allocator); + auto params = + safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + if (const auto* seq_lstm_params = + op->builtin_options_as_UnidirectionalSequenceLSTMOptions()) { + params->activation = + ConvertActivation(seq_lstm_params->fused_activation_function()); + params->cell_clip = seq_lstm_params->cell_clip(); + params->proj_clip = seq_lstm_params->proj_clip(); + params->time_major = seq_lstm_params->time_major(); + params->asymmetric_quantize_inputs = + seq_lstm_params->asymmetric_quantize_inputs(); + params->diagonal_recurrent_tensors = + seq_lstm_params->diagonal_recurrent_tensors(); + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseSqueeze(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + SafeBuiltinDataAllocator safe_allocator(allocator); + + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const SqueezeOptions* schema_params = op->builtin_options_as_SqueezeOptions(); + + if (schema_params != nullptr) { + const auto* squeeze_dims = schema_params->squeeze_dims(); + if (squeeze_dims != nullptr) { + TF_LITE_ENSURE_STATUS(FlatBufferIntVectorToArray( + sizeof(params->squeeze_dims), squeeze_dims, params->squeeze_dims, + error_reporter, "squeeze")); + params->num_squeeze_dims = squeeze_dims->size(); + } else { + params->num_squeeze_dims = 0; + } + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSqrt(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSquare(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseSquaredDifference(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseStridedSlice(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const StridedSliceOptions* schema_params = + op->builtin_options_as_StridedSliceOptions(); + + if (schema_params != nullptr) { + params->begin_mask = schema_params->begin_mask(); + params->end_mask = schema_params->end_mask(); + params->ellipsis_mask = schema_params->ellipsis_mask(); + params->new_axis_mask = schema_params->new_axis_mask(); + params->shrink_axis_mask = schema_params->shrink_axis_mask(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseSub(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const SubOptions* schema_params = op->builtin_options_as_SubOptions(); + + if (schema_params != nullptr) { + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + params->pot_scale_int16 = schema_params->pot_scale_int16(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseSvdf(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const SVDFOptions* schema_params = op->builtin_options_as_SVDFOptions(); + if (schema_params != nullptr) { + params->rank = schema_params->rank(); + params->activation = + ConvertActivation(schema_params->fused_activation_function()); + params->asymmetric_quantize_inputs = + schema_params->asymmetric_quantize_inputs(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseTanh(const Operator*, ErrorReporter*, BuiltinDataAllocator*, + void**) { + return kTfLiteOk; +} +// +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseTranspose(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseTransposeConv(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + const TransposeConvOptions* transpose_conv_params = + op->builtin_options_as_TransposeConvOptions(); + if (transpose_conv_params != nullptr) { + params->padding = ConvertPadding(transpose_conv_params->padding()); + params->stride_width = transpose_conv_params->stride_w(); + params->stride_height = transpose_conv_params->stride_h(); + + params->activation = + ConvertActivation(transpose_conv_params->fused_activation_function()); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseUnpack(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const UnpackOptions* schema_params = op->builtin_options_as_UnpackOptions(); + + if (schema_params != nullptr) { + params->num = schema_params->num(); + params->axis = schema_params->axis(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseVarHandle(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const VarHandleOptions* schema_params = + op->builtin_options_as_VarHandleOptions(); + + if (schema_params != nullptr) { + if (schema_params->container()) { + params->container = schema_params->container()->c_str(); + } + if (schema_params->shared_name()) { + params->shared_name = schema_params->shared_name()->c_str(); + } + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +TfLiteStatus ParseWhile(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { + CheckParsePointerParams(op, error_reporter, allocator, builtin_data); + + SafeBuiltinDataAllocator safe_allocator(allocator); + std::unique_ptr + params = safe_allocator.Allocate(); + TF_LITE_ENSURE(error_reporter, params != nullptr); + + const WhileOptions* schema_params = op->builtin_options_as_WhileOptions(); + + if (schema_params != nullptr) { + params->cond_subgraph_index = schema_params->cond_subgraph_index(); + params->body_subgraph_index = schema_params->body_subgraph_index(); + } else { + // TODO(b/157480169): We should either return kTfLiteError or fill in some + // reasonable defaults in the params struct. We are not doing so until we + // better undertand the ramifications of changing the legacy behavior. + } + + *builtin_data = params.release(); + return kTfLiteOk; +} + +// We have this parse function instead of directly returning kTfLiteOk from the +// switch-case in ParseOpData because this function is used as part of the +// selective registration for the OpResolver implementation in micro. +TfLiteStatus ParseZerosLike(const Operator*, ErrorReporter*, + BuiltinDataAllocator*, void**) { + return kTfLiteOk; +} + +TfLiteStatus ParseOpData(const Operator* op, BuiltinOperator op_type, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data) { +// TODO(b/145762662): It would be preferable to have the build graph for TF Lite +// Micro not have the ParseOpData function at all. This would require splitting +// the current file into two separate files, one of which defines the +// ParseOpData function and the other that defines the operator specific parse +// functions (e.g. ParseAdd). +// +// Such a split was attempted but was not worth the effort at the time because +// of the following reasons: +// * We could either duplicate the functions and the SafeBuiltinDataAllocator +// class in the anonymous namespace of this file, or attempt to make a common +// library with these helper functions and class. +// * Making a common library with a separate build target was not feasible as +// it introduced circular dependencies due to the ErrorReporter and a common +// .cc and .h within the same api build target the also cause circular +// dependencies due to the BuiltinDataAllocator class. +// * If all the builtin operators were to have their own parse functions, or we +// were ok with some amount of code duplication, then this split of the .cc +// files would be a lot more feasible. +#ifdef TF_LITE_STATIC_MEMORY + TF_LITE_REPORT_ERROR( + error_reporter, + "ParseOpData is unsupported on TfLiteMicro, please use the operator " + "specific parse functions (e.g. ParseAdd etc.).\n"); + return kTfLiteError; +#else + return ParseOpDataTfLite(op, op_type, error_reporter, allocator, + builtin_data); +#endif +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.h new file mode 100644 index 0000000..b8e6019 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.h @@ -0,0 +1,427 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_CORE_API_FLATBUFFER_CONVERSIONS_H_ +#define TENSORFLOW_LITE_CORE_API_FLATBUFFER_CONVERSIONS_H_ + +// These functions transform codes and data structures that are defined in the +// flatbuffer serialization format into in-memory values that are used by the +// runtime API and interpreter. + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +// Interface class for builtin data allocations. +class BuiltinDataAllocator { + public: + virtual void* Allocate(size_t size, size_t alignment_hint) = 0; + virtual void Deallocate(void* data) = 0; + + // Allocate a structure, but make sure it is a POD structure that doesn't + // require constructors to run. The reason we do this, is that Interpreter's C + // extension part will take ownership so destructors will not be run during + // deallocation. + template + T* AllocatePOD() { + // TODO(b/154346074): Change this to is_trivially_destructible when all + // platform targets support that properly. + static_assert(std::is_pod::value, "Builtin data structure must be POD."); + void* allocated_memory = this->Allocate(sizeof(T), alignof(T)); + return new (allocated_memory) T(); + } + + virtual ~BuiltinDataAllocator() {} +}; + +// Parse the appropriate data out of the op. +// +// This handles builtin data explicitly as there are flatbuffer schemas. +// If it returns kTfLiteOk, it passes the data out with `builtin_data`. The +// calling function has to pass in an allocator object, and this allocator +// will be called to reserve space for the output data. If the calling +// function's allocator reserves memory on the heap, then it's the calling +// function's responsibility to free it. +// If it returns kTfLiteError, `builtin_data` will be `nullptr`. +TfLiteStatus ParseOpData(const Operator* op, BuiltinOperator op_type, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +// Converts the tensor data type used in the flat buffer to the representation +// used by the runtime. +TfLiteStatus ConvertTensorType(TensorType tensor_type, TfLiteType* type, + ErrorReporter* error_reporter); + +TfLiteStatus ParseAbs(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseAdd(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseAddN(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseArgMax(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseArgMin(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseAssignVariable(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseBatchMatMul(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseBatchToSpaceNd(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseBroadcastArgs(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseBroadcastTo(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseCallOnce(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseCeil(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseCast(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseComplexAbs(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseConcatenation(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseConv2D(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseCos(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseCumsum(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseDepthToSpace(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseDepthwiseConv2D(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseDequantize(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseDiv(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseElu(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseEqual(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseExp(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseExpandDims(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseFill(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseFloor(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseFloorDiv(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseFloorMod(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseFullyConnected(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseGather(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseGatherNd(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseGreater(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseGreaterEqual(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseHardSwish(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseImag(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseIf(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseL2Normalization(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLeakyRelu(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLess(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseLessEqual(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLog(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseLogicalAnd(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLogicalNot(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLogicalOr(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLogistic(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLogSoftmax(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseLSTM(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseMaximum(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseMinimum(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseMirrorPad(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseMul(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseNeg(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseNotEqual(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParsePack(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParsePad(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParsePadV2(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParsePool(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParsePow(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParsePrelu(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseQuantize(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseReal(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseReadVariable(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseReducer(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseRelu(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseRelu6(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseReshape(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseResizeBilinear(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseResizeNearestNeighbor(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseRfft2D(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseRound(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseRsqrt(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSelect(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSelectV2(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseShape(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSin(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSlice(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSoftmax(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSpaceToBatchNd(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseSpaceToDepth(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseSplit(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSplitV(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSqueeze(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSqrt(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSquare(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSquaredDifference(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseStridedSlice(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseSub(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseSvdf(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseTanh(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseTranspose(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseTransposeConv(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseUnpack(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseUnidirectionalSequenceLSTM(const Operator* op, + ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseVarHandle(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +TfLiteStatus ParseWhile(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +TfLiteStatus ParseZerosLike(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, + void** builtin_data); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_CORE_API_FLATBUFFER_CONVERSIONS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.cpp new file mode 100644 index 0000000..bb2e080 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.cpp @@ -0,0 +1,68 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.h" + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h" + +namespace tflite { + +TfLiteStatus GetRegistrationFromOpCode( + const OperatorCode* opcode, const OpResolver& op_resolver, + ErrorReporter* error_reporter, const TfLiteRegistration** registration) { + TfLiteStatus status = kTfLiteOk; + *registration = nullptr; + auto builtin_code = GetBuiltinCode(opcode); + int version = opcode->version(); + + if (builtin_code > BuiltinOperator_MAX) { + TF_LITE_REPORT_ERROR( + error_reporter, + "Op builtin_code out of range: %d. Are you using old TFLite binary " + "with newer model?", + builtin_code); + status = kTfLiteError; + } else if (builtin_code != BuiltinOperator_CUSTOM) { + *registration = op_resolver.FindOp(builtin_code, version); + if (*registration == nullptr) { + TF_LITE_REPORT_ERROR( + error_reporter, + "Didn't find op for builtin opcode '%s' version '%d'. " + "This model is not supported by EON Compiler of TensorFlow Lite Micro,", + "but is in full TFLite (e.g. on Linux).\n", + EnumNameBuiltinOperator(builtin_code), version); + status = kTfLiteError; + } + } else if (!opcode->custom_code()) { + TF_LITE_REPORT_ERROR( + error_reporter, + "Operator with CUSTOM builtin_code has no custom_code.\n"); + status = kTfLiteError; + } else { + const char* name = opcode->custom_code()->c_str(); + *registration = op_resolver.FindOp(name, version); + if (*registration == nullptr) { + // Do not report error for unresolved custom op, we do the final check + // while preparing ops. + status = kTfLiteError; + } + } + return status; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.h new file mode 100644 index 0000000..75fc5d0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.h @@ -0,0 +1,129 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_CORE_API_OP_RESOLVER_H_ +#define TENSORFLOW_LITE_CORE_API_OP_RESOLVER_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +/// Abstract interface that returns TfLiteRegistrations given op codes or custom +/// op names. This is the mechanism that ops being referenced in the flatbuffer +/// model are mapped to executable function pointers (TfLiteRegistrations). +class OpResolver { + public: + /// Finds the op registration for a builtin operator by enum code. + virtual const TfLiteRegistration* FindOp(tflite::BuiltinOperator op, + int version) const = 0; + /// Finds the op registration of a custom operator by op name. + virtual const TfLiteRegistration* FindOp(const char* op, + int version) const = 0; + + // Represents a sequence of delegates. + using TfLiteDelegatePtrVector = + std::vector>; + + // Returns optional delegates for resolving and handling ops in the flatbuffer + // model. This may be used in addition to the standard TfLiteRegistration + // lookup for graph resolution. + // WARNING: This API is deprecated, GetDelegateCreators is preferred. + virtual TfLiteDelegatePtrVector GetDelegates(int num_threads) const { + return {}; + } + + // Represents a function that creates a TfLite delegate instance. + using TfLiteDelegateCreator = + std::function( + TfLiteContext* /*context*/)>; + + // Represents a sequence of delegate creator functions. + using TfLiteDelegateCreators = std::vector; + + // Returns a vector of delegate creators to create optional delegates for + // resolving and handling ops in the flatbuffer model. This may be used in + // addition to the standard TfLiteRegistration lookup for graph resolution. + // + // Note that this method is not used (will not be called) if you are using + // TF Lite in Google Play Services; the GetOpaqueDelegateCreators method + // (see below) is used for that case. + virtual TfLiteDelegateCreators GetDelegateCreators() const { return {}; } + + // TODO(b/202712825): it would be nice if we could avoid the need for separate + // "opaque" types & methods for use only with TF Lite in Google Play Services. + + // Represents an opaque delegate instance. + // WARNING: Experimental interface, subject to change. + using TfLiteOpaqueDelegatePtr = + std::unique_ptr; + + // Represents a function that creates an opaque delegate instance. + // WARNING: Experimental interface, subject to change. + using TfLiteOpaqueDelegateCreator = + std::function; + + // Represents a sequence of opaque delegate creator functions. + // WARNING: Experimental interface, subject to change. + using TfLiteOpaqueDelegateCreators = std::vector; + + // Returns a vector of opaque delegate creators to create optional opaque + // delegates for resolving and handling ops in the flatbuffer model. This may + // be used in addition to the standard TfLiteRegistration lookup for graph + // resolution. + // + // Note that this method will be called only if you are using TF Lite in + // Google Play Services; if you are using regular TF Lite, GetDelegateCreators + // (see above) is used instead. + // + // WARNING: Experimental interface, subject to change. + virtual TfLiteOpaqueDelegateCreators GetOpaqueDelegateCreators() const { + return {}; + } + + virtual ~OpResolver() {} + + private: + /// Returns true if this OpResolver may contain any "user defined" ops. + /// By "user defined" ops, we mean any op definitions other than those + /// contained in tflite::ops::builtin::BuiltinOpResolver. + /// + /// If this method returns true, it doesn't necessarily mean that the + /// OpResolver contains a user-defined op, just that the absence of + /// user-defined ops can't be guaranteed. + /// + /// Note that "user-defined" ops are not the same as "custom" ops; + /// BuiltinOpResolver may support certain "custom" ops, in addition to + /// "builtin" ops, and may not support all of the "builtin" op enum values. + virtual bool MayContainUserDefinedOps() const { return true; } + + friend class OpResolverInternal; +}; + +// Handles the logic for converting between an OperatorCode structure extracted +// from a flatbuffer and information about a registered operator +// implementation. +TfLiteStatus GetRegistrationFromOpCode(const OperatorCode* opcode, + const OpResolver& op_resolver, + ErrorReporter* error_reporter, + const TfLiteRegistration** registration); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_CORE_API_OP_RESOLVER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/tensor_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/tensor_utils.cpp new file mode 100644 index 0000000..b62d50c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/tensor_utils.cpp @@ -0,0 +1,50 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/core/api/tensor_utils.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +namespace tflite { + +TfLiteStatus ResetVariableTensor(TfLiteTensor* tensor) { + if (!tensor->is_variable) { + return kTfLiteOk; + } + // TODO(b/115961645): Implement - If a variable tensor has a buffer, reset it + // to the value of the buffer. + int value = 0; + if (tensor->type == kTfLiteInt8) { + value = tensor->params.zero_point; + } + // TODO(b/139446230): Provide a platform header to better handle these + // specific scenarios. +#if __ANDROID__ || defined(__x86_64__) || defined(__i386__) || \ + defined(__i386) || defined(__x86__) || defined(__X86__) || \ + defined(_X86_) || defined(_M_IX86) || defined(_M_X64) + memset(tensor->data.raw, value, tensor->bytes); +#else + char* raw_ptr = tensor->data.raw; + for (size_t i = 0; i < tensor->bytes; ++i) { + *raw_ptr = value; + raw_ptr++; + } +#endif + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/tensor_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/tensor_utils.h new file mode 100644 index 0000000..608128a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/api/tensor_utils.h @@ -0,0 +1,28 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_CORE_API_TENSOR_UTILS_H_ +#define TENSORFLOW_LITE_CORE_API_TENSOR_UTILS_H_ + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +namespace tflite { + +// Resets a variable tensor to the default value. +TfLiteStatus ResetVariableTensor(TfLiteTensor* tensor); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_CORE_API_TENSOR_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h new file mode 100644 index 0000000..3a1ee0e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h @@ -0,0 +1,537 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +/// WARNING: Users of TensorFlow Lite should not include this file directly, +/// but should instead include +/// "third_party/tensorflow/lite/c/builtin_op_data.h". +/// Only the TensorFlow Lite implementation itself should include this +/// file directly. +#ifndef TENSORFLOW_LITE_CORE_C_BUILTIN_OP_DATA_H_ +#define TENSORFLOW_LITE_CORE_C_BUILTIN_OP_DATA_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// TfLiteReshapeParams can't have dynamic data so we fix the maximum possible +// number of dimensions. +#define TFLITE_RESHAPE_PARAMS_MAX_DIMENSION_COUNT 8 + +// TODO(aselle): Consider using "if this then that" for testing. + +// Useful placeholder to put in otherwise empty structs to avoid size warnings. +typedef struct { + char dummy; +} EmptyStructPlaceholder; + +// IMPORTANT: All new members of structs must be added at the end to ensure +// backwards compatibility. + +// Possible padding types (for convolutions) +typedef enum { + kTfLitePaddingUnknown = 0, + kTfLitePaddingSame, + kTfLitePaddingValid, +} TfLitePadding; + +typedef enum { + kTfLiteMirrorPaddingUnknown = 0, + kTfLiteMirrorPaddingReflect, + kTfLiteMirrorPaddingSymmetric, +} TfLiteMirrorPaddingMode; + +// TODO(b/130259536): We should move this out of builtin_op_data. +typedef struct { + int width; + int height; + int width_offset; + int height_offset; +} TfLitePaddingValues; + +typedef struct { + TfLiteMirrorPaddingMode mode; +} TfLiteMirrorPaddingParams; + +// Possible fused activation functions. +typedef enum { + kTfLiteActNone = 0, + kTfLiteActRelu, + kTfLiteActReluN1To1, // min(max(-1, x), 1) + kTfLiteActRelu6, // min(max(0, x), 6) + kTfLiteActTanh, + kTfLiteActSignBit, + kTfLiteActSigmoid, +} TfLiteFusedActivation; + +typedef struct { + // Parameters for CONV_2D version 1. + TfLitePadding padding; + int stride_width; + int stride_height; + TfLiteFusedActivation activation; + + // Parameters for CONV_2D version 2. + // Note: Version 2 supports dilation values not equal to 1. + int dilation_width_factor; + int dilation_height_factor; +} TfLiteConvParams; + +typedef struct { + TfLitePadding padding; + int stride_width; + int stride_height; + int stride_depth; + int dilation_width_factor; + int dilation_height_factor; + int dilation_depth_factor; + TfLiteFusedActivation activation; +} TfLiteConv3DParams; + +typedef TfLiteConv3DParams TfLiteConv3DTransposeParams; + +typedef struct { + TfLitePadding padding; + int stride_width; + int stride_height; + int filter_width; + int filter_height; + TfLiteFusedActivation activation; + struct { + TfLitePaddingValues padding; + } computed; +} TfLitePoolParams; + +typedef struct { + // Parameters for DepthwiseConv version 1 or above. + TfLitePadding padding; + int stride_width; + int stride_height; + // `depth_multiplier` is redundant. It's used by CPU kernels in + // TensorFlow 2.0 or below, but ignored in versions above. + // + // The information can be deduced from the shape of input and the shape of + // weights. Since the TFLiteConverter toolchain doesn't support partially + // specified shapes, relying on `depth_multiplier` stops us from supporting + // graphs with dynamic shape tensors. + // + // Note: Some of the delegates (e.g. NNAPI, GPU) are still relying on this + // field. + int depth_multiplier; + TfLiteFusedActivation activation; + // Parameters for DepthwiseConv version 2 or above. + int dilation_width_factor; + int dilation_height_factor; +} TfLiteDepthwiseConvParams; + +typedef struct { + int rank; + TfLiteFusedActivation activation; + + // Parameter for SVDF version 4. + bool asymmetric_quantize_inputs; +} TfLiteSVDFParams; + +typedef struct { + TfLiteFusedActivation activation; + + // Parameter for RNN version 3. + bool asymmetric_quantize_inputs; +} TfLiteRNNParams; + +typedef struct { + bool time_major; + TfLiteFusedActivation activation; + + // Parameter for Sequence RNN version 3. + bool asymmetric_quantize_inputs; +} TfLiteSequenceRNNParams; + +typedef struct { + bool time_major; + TfLiteFusedActivation activation; + bool merge_outputs; + + // Parameter for Bidirectional RNN verison 3. + bool asymmetric_quantize_inputs; +} TfLiteBidirectionalSequenceRNNParams; + +typedef enum { + kTfLiteFullyConnectedWeightsFormatDefault = 0, + kTfLiteFullyConnectedWeightsFormatShuffled4x16Int8 = 1, +} TfLiteFullyConnectedWeightsFormat; + +typedef struct { + // Parameters for FullyConnected version 1 or above. + TfLiteFusedActivation activation; + + // Parameters for FullyConnected version 2 or above. + TfLiteFullyConnectedWeightsFormat weights_format; + + // Parameters for FullyConnected version 5 or above. + // If set to true, then the number of dimensions in the input and the output + // tensors are the same. Furthermore, all but the last dimension of the input + // and output shapes will be equal. + bool keep_num_dims; + + // Parameters for FullyConnected version 7 or above. + // If set to true and the weights are quantized, then non constant inputs + // are quantized at evaluation time with asymmetric quantization. + bool asymmetric_quantize_inputs; +} TfLiteFullyConnectedParams; + +typedef enum { + kTfLiteLshProjectionUnknown = 0, + kTfLiteLshProjectionSparse = 1, + kTfLiteLshProjectionDense = 2, +} TfLiteLSHProjectionType; + +typedef struct { + TfLiteLSHProjectionType type; +} TfLiteLSHProjectionParams; + +typedef struct { + float beta; +} TfLiteSoftmaxParams; + +typedef struct { + int axis; + TfLiteFusedActivation activation; +} TfLiteConcatenationParams; + +typedef struct { + TfLiteFusedActivation activation; + // Parameter added for the version 4. + bool pot_scale_int16; +} TfLiteAddParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLiteSpaceToBatchNDParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLiteBatchToSpaceNDParams; + +typedef struct { + bool adj_x; + bool adj_y; + // Parameters for BatchMatMul version 4 or above. + // If set to true and the weights are quantized, then non constant inputs + // are quantized at evaluation time with asymmetric quantization. + bool asymmetric_quantize_inputs; +} TfLiteBatchMatMulParams; + +typedef struct { + TfLiteFusedActivation activation; +} TfLiteMulParams; + +typedef struct { + TfLiteFusedActivation activation; + // Parameter added for the version 5. + bool pot_scale_int16; +} TfLiteSubParams; + +typedef struct { + TfLiteFusedActivation activation; +} TfLiteDivParams; + +typedef struct { + TfLiteFusedActivation activation; +} TfLiteL2NormParams; + +typedef struct { + int radius; + float bias; + float alpha; + float beta; +} TfLiteLocalResponseNormParams; + +typedef enum { + kTfLiteLSTMFullKernel = 0, + kTfLiteLSTMBasicKernel +} TfLiteLSTMKernelType; + +typedef struct { + // Parameters for LSTM version 1. + TfLiteFusedActivation activation; + float cell_clip; + float proj_clip; + + // Parameters for LSTM version 2. + // kTfLiteLSTMBasicKernel is only supported in version 2 or above. + TfLiteLSTMKernelType kernel_type; + + // Parameters for LSTM version 4. + bool asymmetric_quantize_inputs; +} TfLiteLSTMParams; + +typedef struct { + // Parameters needed for the underlying LSTM. + TfLiteFusedActivation activation; + float cell_clip; + float proj_clip; + + // If set to true then the first dimension is time, otherwise batch. + bool time_major; + + // Parameter for unidirectional sequence RNN version 3. + bool asymmetric_quantize_inputs; + + // Parameter for unidirectional sequence RNN version 4. + bool diagonal_recurrent_tensors; +} TfLiteUnidirectionalSequenceLSTMParams; + +typedef struct { + // Parameters supported by version 1: + // Parameters inherited for the LSTM kernel. + TfLiteFusedActivation activation; + float cell_clip; + float proj_clip; + + // If true, store the outputs of both directions in the first output. + bool merge_outputs; + + // Parameters supported by version 2: + // If set to true then the first dimension is time, otherwise batch. + bool time_major; + + // Parameters supported by version 3: + // If set to true, then hybrid ops use asymmetric quantization for inputs. + bool asymmetric_quantize_inputs; +} TfLiteBidirectionalSequenceLSTMParams; + +typedef struct { + bool align_corners; + // half_pixel_centers assumes pixels are of half the actual dimensions, and + // yields more accurate resizes. Corresponds to the same argument for the + // original TensorFlow op in TF2.0. + bool half_pixel_centers; +} TfLiteResizeBilinearParams; + +typedef struct { + bool align_corners; + bool half_pixel_centers; +} TfLiteResizeNearestNeighborParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLitePadParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLitePadV2Params; + +typedef struct { + // These fields are only used in old models for backward compatibility. + // In the current implementation, we use the 2nd input of the op as the shape, + // and these fields are unused. + int shape[TFLITE_RESHAPE_PARAMS_MAX_DIMENSION_COUNT]; + int num_dimensions; +} TfLiteReshapeParams; + +typedef struct { + int ngram_size; + int max_skip_size; + bool include_all_ngrams; +} TfLiteSkipGramParams; + +typedef struct { + int block_size; +} TfLiteSpaceToDepthParams; + +typedef struct { + int block_size; +} TfLiteDepthToSpaceParams; + +typedef struct { + TfLiteType in_data_type; + TfLiteType out_data_type; +} TfLiteCastParams; + +typedef enum { + kTfLiteCombinerTypeSum = 0, + kTfLiteCombinerTypeMean = 1, + kTfLiteCombinerTypeSqrtn = 2, +} TfLiteCombinerType; + +typedef struct { + TfLiteCombinerType combiner; +} TfLiteEmbeddingLookupSparseParams; + +typedef struct { + int axis; + int batch_dims; +} TfLiteGatherParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLiteTransposeParams; + +typedef struct { + bool keep_dims; +} TfLiteReducerParams; + +typedef struct { + int num_splits; +} TfLiteSplitParams; + +typedef struct { + int num_splits; +} TfLiteSplitVParams; + +typedef struct { + // TODO(ahentz): We can't have dynamic data in this struct, at least not yet. + // For now we will fix the maximum possible number of dimensions. + int squeeze_dims[8]; + int num_squeeze_dims; +} TfLiteSqueezeParams; + +typedef struct { + int begin_mask; + int end_mask; + int ellipsis_mask; + int new_axis_mask; + int shrink_axis_mask; +} TfLiteStridedSliceParams; + +typedef struct { + TfLiteType output_type; +} TfLiteArgMaxParams; + +typedef struct { + TfLiteType output_type; +} TfLiteArgMinParams; + +typedef struct { + // Parameters supported by version 1: + TfLitePadding padding; + int stride_width; + int stride_height; + + // Parameters supported by version 4: + TfLiteFusedActivation activation; +} TfLiteTransposeConvParams; + +typedef struct { + bool validate_indices; +} TfLiteSparseToDenseParams; + +typedef struct { + TfLiteType out_type; +} TfLiteShapeParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLiteRankParams; + +typedef struct { + // Parameters supported by version 1: + float min; + float max; + int num_bits; + + // Parameters supported by version 2: + bool narrow_range; +} TfLiteFakeQuantParams; + +typedef struct { + int values_count; + int axis; +} TfLitePackParams; + +typedef struct { + int axis; +} TfLiteOneHotParams; + +typedef struct { + int num; + int axis; +} TfLiteUnpackParams; + +typedef struct { + float alpha; +} TfLiteLeakyReluParams; + +typedef struct { + TfLiteType index_out_type; +} TfLiteUniqueParams; + +typedef struct { + int seq_dim; + int batch_dim; +} TfLiteReverseSequenceParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLiteMatrixDiagParams; + +typedef struct { + EmptyStructPlaceholder placeholder; +} TfLiteMatrixSetDiagParams; + +typedef struct { + int then_subgraph_index; + int else_subgraph_index; +} TfLiteIfParams; + +typedef struct { + int cond_subgraph_index; + int body_subgraph_index; +} TfLiteWhileParams; + +typedef struct { + bool exclusive; + bool reverse; +} TfLiteCumsumParams; + +typedef struct { + int init_subgraph_index; +} TfLiteCallOnceParams; + +typedef struct { + int table_id; + TfLiteType key_dtype; + TfLiteType value_dtype; +} TfLiteHashtableParams; + +typedef struct { + const char* container; + const char* shared_name; +} TfLiteVarHandleParams; + +typedef struct { + int seed; + int seed2; +} TfLiteRandomParams; + +typedef struct { + int num_boundaries; + // This points to the memory stored in the model (flatbuffer), + // and is not owned. + const float* boundaries; +} TfLiteBucketizeParams; + +typedef struct { + bool approximate; +} TfLiteGeluParams; + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // TENSORFLOW_LITE_CORE_C_BUILTIN_OP_DATA_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/c_api_types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/c_api_types.h new file mode 100644 index 0000000..3aab43f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/c_api_types.h @@ -0,0 +1,168 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This file declares types used by the pure C inference API defined in c_api.h, +// some of which are also used in the C++ and C kernel and interpreter APIs. + +/// WARNING: Users of TensorFlow Lite should not include this file directly, +/// but should instead include +/// "third_party/tensorflow/lite/c/c_api_types.h". +/// Only the TensorFlow Lite implementation itself should include this +/// file directly. + +#ifndef TENSORFLOW_LITE_CORE_C_C_API_TYPES_H_ +#define TENSORFLOW_LITE_CORE_C_C_API_TYPES_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Define TFL_CAPI_EXPORT macro to export a function properly with a shared +// library. +#ifdef SWIG +#define TFL_CAPI_EXPORT +#elif defined(TFL_STATIC_LIBRARY_BUILD) +#define TFL_CAPI_EXPORT +#else // not definded TFL_STATIC_LIBRARY_BUILD +#if defined(_WIN32) +#ifdef TFL_COMPILE_LIBRARY +#define TFL_CAPI_EXPORT __declspec(dllexport) +#else +#define TFL_CAPI_EXPORT __declspec(dllimport) +#endif // TFL_COMPILE_LIBRARY +#else +#define TFL_CAPI_EXPORT __attribute__((visibility("default"))) +#endif // _WIN32 +#endif // SWIG + +// Note that new error status values may be added in future in order to +// indicate more fine-grained internal states, therefore, applications should +// not rely on status values being members of the enum. +typedef enum TfLiteStatus { + kTfLiteOk = 0, + + // Generally referring to an error in the runtime (i.e. interpreter) + kTfLiteError = 1, + + // Generally referring to an error from a TfLiteDelegate itself. + kTfLiteDelegateError = 2, + + // Generally referring to an error in applying a delegate due to + // incompatibility between runtime and delegate, e.g., this error is returned + // when trying to apply a TF Lite delegate onto a model graph that's already + // immutable. + kTfLiteApplicationError = 3, + + // Generally referring to serialized delegate data not being found. + // See tflite::delegates::Serialization. + kTfLiteDelegateDataNotFound = 4, + + // Generally referring to data-writing issues in delegate serialization. + // See tflite::delegates::Serialization. + kTfLiteDelegateDataWriteError = 5, + + // Generally referring to data-reading issues in delegate serialization. + // See tflite::delegates::Serialization. + kTfLiteDelegateDataReadError = 6, + + // Generally referring to issues when the TF Lite model has ops that cannot be + // resolved at runtime. This could happen when the specific op is not + // registered or built with the TF Lite framework. + kTfLiteUnresolvedOps = 7, + + // Generally referring to invocation cancelled by the user. + // See `interpreter::Cancel`. + // TODO(b/194915839): Implement `interpreter::Cancel`. + // TODO(b/250636993): Cancellation triggered by `SetCancellationFunction` + // should also return this status code. + kTfLiteCancelled = 8, +} TfLiteStatus; + +// Types supported by tensor +typedef enum { + kTfLiteNoType = 0, + kTfLiteFloat32 = 1, + kTfLiteInt32 = 2, + kTfLiteUInt8 = 3, + kTfLiteInt64 = 4, + kTfLiteString = 5, + kTfLiteBool = 6, + kTfLiteInt16 = 7, + kTfLiteComplex64 = 8, + kTfLiteInt8 = 9, + kTfLiteFloat16 = 10, + kTfLiteFloat64 = 11, + kTfLiteComplex128 = 12, + kTfLiteUInt64 = 13, + kTfLiteResource = 14, + kTfLiteVariant = 15, + kTfLiteUInt32 = 16, + kTfLiteUInt16 = 17, + kTfLiteInt4 = 18, +} TfLiteType; + +// Legacy. Will be deprecated in favor of TfLiteAffineQuantization. +// If per-layer quantization is specified this field will still be populated in +// addition to TfLiteAffineQuantization. +// Parameters for asymmetric quantization. Quantized values can be converted +// back to float using: +// real_value = scale * (quantized_value - zero_point) +typedef struct TfLiteQuantizationParams { + float scale; + int32_t zero_point; +} TfLiteQuantizationParams; + +// -------------------------------------------------------------------------- +// Opaque types used by c_api.h, c_api_opaque.h and common.h. + +// TfLiteOpaqueContext is an opaque version of TfLiteContext; +typedef struct TfLiteOpaqueContext TfLiteOpaqueContext; + +// TfLiteOpaqueNode is an opaque version of TfLiteNode; +typedef struct TfLiteOpaqueNode TfLiteOpaqueNode; + +// TfLiteOpaqueTensor is an opaque version of TfLiteTensor; +typedef struct TfLiteOpaqueTensor TfLiteOpaqueTensor; + +// TfLiteDelegate: allows delegation of nodes to alternative backends. +// Forward declaration of concrete type declared in common.h. +typedef struct TfLiteDelegate TfLiteDelegate; + +// TfLiteOpaqueDelegateStruct: unconditionally opaque version of +// TfLiteDelegate; allows delegation of nodes to alternative backends. +// +// This is an abstract type that is intended to have the same +// role as TfLiteDelegate, but without exposing the implementation +// details of how delegates are implemented. +// WARNING: This is an experimental type and subject to change. +typedef struct TfLiteOpaqueDelegateStruct TfLiteOpaqueDelegateStruct; + +// TfLiteOpaqueDelegate: conditionally opaque version of +// TfLiteDelegate; allows delegation of nodes to alternative backends. +// For TF Lite in Play Services, this is an opaque type, +// but for regular TF Lite, this is just a typedef for TfLiteDelegate. +// WARNING: This is an experimental type and subject to change. +#if TFLITE_WITH_STABLE_ABI || TFLITE_USE_OPAQUE_DELEGATE +typedef TfLiteOpaqueDelegateStruct TfLiteOpaqueDelegate; +#else +typedef TfLiteDelegate TfLiteOpaqueDelegate; +#endif + +#ifdef __cplusplus +} // extern C +#endif +#endif // TENSORFLOW_LITE_CORE_C_C_API_TYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/common.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/common.h new file mode 100644 index 0000000..83b4a31 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/core/c/common.h @@ -0,0 +1,1170 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This file defines common C types and APIs for implementing operations, +// delegates and other constructs in TensorFlow Lite. The actual operations and +// delegates can be defined using C++, but the interface between the interpreter +// and the operations are C. +// +// Summary of abstractions +// TF_LITE_ENSURE - Self-sufficient error checking +// TfLiteStatus - Status reporting +// TfLiteIntArray - stores tensor shapes (dims), +// TfLiteContext - allows an op to access the tensors +// TfLiteTensor - tensor (a multidimensional array) +// TfLiteNode - a single node or operation +// TfLiteRegistration - the implementation of a conceptual operation. +// TfLiteDelegate - allows delegation of nodes to alternative backends. +// +// Some abstractions in this file are created and managed by Interpreter. +// +// NOTE: The order of values in these structs are "semi-ABI stable". New values +// should be added only to the end of structs and never reordered. + +/// WARNING: Users of TensorFlow Lite should not include this file directly, +/// but should instead include +/// "third_party/tensorflow/lite/c/common.h". +/// Only the TensorFlow Lite implementation itself should include this +/// file directly. + +#ifndef TENSORFLOW_LITE_CORE_C_COMMON_H_ +#define TENSORFLOW_LITE_CORE_C_COMMON_H_ + +#include +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/c_api_types.h" // IWYU pragma: export + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// The list of external context types known to TF Lite. This list exists solely +// to avoid conflicts and to ensure ops can share the external contexts they +// need. Access to the external contexts is controlled by one of the +// corresponding support files. +typedef enum TfLiteExternalContextType { + kTfLiteEigenContext = 0, // include eigen_support.h to use. + kTfLiteGemmLowpContext = 1, // include gemm_support.h to use. + kTfLiteEdgeTpuContext = 2, // Placeholder for Edge TPU support. + kTfLiteCpuBackendContext = 3, // include cpu_backend_context.h to use. + kTfLiteMaxExternalContexts = 4 +} TfLiteExternalContextType; + +// Forward declare so dependent structs and methods can reference these types +// prior to the struct definitions. +struct TfLiteContext; +struct TfLiteDelegate; +struct TfLiteRegistration; +struct TfLiteOpaqueDelegateBuilder; + +// An external context is a collection of information unrelated to the TF Lite +// framework, but useful to a subset of the ops. TF Lite knows very little +// about the actual contexts, but it keeps a list of them, and is able to +// refresh them if configurations like the number of recommended threads +// change. +typedef struct TfLiteExternalContext { + TfLiteExternalContextType type; + TfLiteStatus (*Refresh)(struct TfLiteContext* context); +} TfLiteExternalContext; + +#define kTfLiteOptionalTensor (-1) + +// Fixed size list of integers. Used for dimensions and inputs/outputs tensor +// indices +typedef struct TfLiteIntArray { + int size; + +#if defined(_MSC_VER) + // Context for why this is needed is in http://b/189926408#comment21 + int data[1]; +#elif (!defined(__clang__) && defined(__GNUC__) && __GNUC__ == 6 && \ + __GNUC_MINOR__ >= 1) || \ + defined(HEXAGON) || \ + (defined(__clang__) && __clang_major__ == 7 && __clang_minor__ == 1) + // gcc 6.1+ have a bug where flexible members aren't properly handled + // https://github.com/google/re2/commit/b94b7cd42e9f02673cd748c1ac1d16db4052514c + int data[0]; +#else + int data[]; +#endif +} TfLiteIntArray; + +// Given the size (number of elements) in a TfLiteIntArray, calculate its size +// in bytes. +size_t TfLiteIntArrayGetSizeInBytes(int size); + +#ifndef TF_LITE_STATIC_MEMORY +// Create a array of a given `size` (uninitialized entries). +// This returns a pointer, that you must free using TfLiteIntArrayFree(). +TfLiteIntArray* TfLiteIntArrayCreate(int size); +#endif + +// Check if two intarrays are equal. Returns 1 if they are equal, 0 otherwise. +int TfLiteIntArrayEqual(const TfLiteIntArray* a, const TfLiteIntArray* b); + +// Check if an intarray equals an array. Returns 1 if equals, 0 otherwise. +int TfLiteIntArrayEqualsArray(const TfLiteIntArray* a, int b_size, + const int b_data[]); + +#ifndef TF_LITE_STATIC_MEMORY +// Create a copy of an array passed as `src`. +// You are expected to free memory with TfLiteIntArrayFree +TfLiteIntArray* TfLiteIntArrayCopy(const TfLiteIntArray* src); + +// Free memory of array `a`. +void TfLiteIntArrayFree(TfLiteIntArray* a); +#endif // TF_LITE_STATIC_MEMORY + +// Fixed size list of floats. Used for per-channel quantization. +typedef struct TfLiteFloatArray { + int size; +#if defined(_MSC_VER) + // Context for why this is needed is in http://b/189926408#comment21 + float data[1]; +#elif (!defined(__clang__) && defined(__GNUC__) && __GNUC__ == 6 && \ + __GNUC_MINOR__ >= 1) || \ + defined(HEXAGON) || \ + (defined(__clang__) && __clang_major__ == 7 && __clang_minor__ == 1) + // gcc 6.1+ have a bug where flexible members aren't properly handled + // https://github.com/google/re2/commit/b94b7cd42e9f02673cd748c1ac1d16db4052514c + float data[0]; +#else + float data[]; +#endif +} TfLiteFloatArray; + +// Given the size (number of elements) in a TfLiteFloatArray, calculate its size +// in bytes. +int TfLiteFloatArrayGetSizeInBytes(int size); + +#ifndef TF_LITE_STATIC_MEMORY +// Create a array of a given `size` (uninitialized entries). +// This returns a pointer, that you must free using TfLiteFloatArrayFree(). +TfLiteFloatArray* TfLiteFloatArrayCreate(int size); + +// Free memory of array `a`. +void TfLiteFloatArrayFree(TfLiteFloatArray* a); +#endif // TF_LITE_STATIC_MEMORY + +// Since we must not depend on any libraries, define a minimal subset of +// error macros while avoiding names that have pre-conceived meanings like +// assert and check. + +// Try to make all reporting calls through TF_LITE_KERNEL_LOG rather than +// calling the context->ReportError function directly, so that message strings +// can be stripped out if the binary size needs to be severely optimized. +#ifndef TF_LITE_STRIP_ERROR_STRINGS +#ifdef TF_LITE_LOG_FILE_NAME +#define TF_LITE_KERNEL_LOG(context, ...) \ + do { \ + (context)->ReportError((context), __FILE__ " " __VA_ARGS__); \ + } while (false) + +#define TF_LITE_MAYBE_KERNEL_LOG(context, ...) \ + do { \ + if ((context) != nullptr) { \ + (context)->ReportError((context), __FILE__ " " __VA_ARGS__); \ + } \ + } while (false) +#else // TF_LITE_LOG_FILE_NAME +#define TF_LITE_KERNEL_LOG(context, ...) \ + do { \ + (context)->ReportError((context), __VA_ARGS__); \ + } while (false) + +#define TF_LITE_MAYBE_KERNEL_LOG(context, ...) \ + do { \ + if ((context) != nullptr) { \ + (context)->ReportError((context), __VA_ARGS__); \ + } \ + } while (false) +#endif // TF_LITE_LOG_FILE_NAME +#else // TF_LITE_STRIP_ERROR_STRINGS +#define ARGS_UNUSED(...) (void)sizeof(#__VA_ARGS__) +#define TF_LITE_KERNEL_LOG(context, ...) ARGS_UNUSED(__VA_ARGS__) +#define TF_LITE_MAYBE_KERNEL_LOG(context, ...) ARGS_UNUSED(__VA_ARGS__) +#endif // TF_LITE_STRIP_ERROR_STRINGS + +// Check whether value is true, and if not return kTfLiteError from +// the current function (and report the error string msg). +#define TF_LITE_ENSURE_MSG(context, value, msg) \ + do { \ + if (!(value)) { \ + TF_LITE_KERNEL_LOG((context), __FILE__ " " msg); \ + return kTfLiteError; \ + } \ + } while (0) + +// Check whether the value `a` is true, and if not return kTfLiteError from +// the current function, while also reporting the location of the error. +#define TF_LITE_ENSURE(context, a) \ + do { \ + if (!(a)) { \ + TF_LITE_KERNEL_LOG((context), "%s:%d %s was not true.", __FILE__, \ + __LINE__, #a); \ + return kTfLiteError; \ + } \ + } while (0) + +#define TF_LITE_ENSURE_STATUS(a) \ + do { \ + const TfLiteStatus s = (a); \ + if (s != kTfLiteOk) { \ + return s; \ + } \ + } while (0) + +// Check whether the value `a == b` is true, and if not return kTfLiteError from +// the current function, while also reporting the location of the error. +// `a` and `b` may be evaluated more than once, so no side effects or +// extremely expensive computations should be done. +// NOTE: Use TF_LITE_ENSURE_TYPES_EQ if comparing TfLiteTypes. +#define TF_LITE_ENSURE_EQ(context, a, b) \ + do { \ + if ((a) != (b)) { \ + TF_LITE_KERNEL_LOG((context), "%s:%d %s != %s (%d != %d)", __FILE__, \ + __LINE__, #a, #b, (a), (b)); \ + return kTfLiteError; \ + } \ + } while (0) + +#define TF_LITE_ENSURE_TYPES_EQ(context, a, b) \ + do { \ + if ((a) != (b)) { \ + TF_LITE_KERNEL_LOG((context), "%s:%d %s != %s (%s != %s)", __FILE__, \ + __LINE__, #a, #b, TfLiteTypeGetName(a), \ + TfLiteTypeGetName(b)); \ + return kTfLiteError; \ + } \ + } while (0) + +#define TF_LITE_ENSURE_NEAR(context, a, b, epsilon) \ + do { \ + auto delta = ((a) > (b)) ? ((a) - (b)) : ((b) - (a)); \ + if (delta > epsilon) { \ + TF_LITE_KERNEL_LOG((context), "%s:%d %s not near %s (%f != %f)", \ + __FILE__, __LINE__, #a, #b, static_cast(a), \ + static_cast(b)); \ + return kTfLiteError; \ + } \ + } while (0) + +#define TF_LITE_ENSURE_OK(context, status) \ + do { \ + const TfLiteStatus s = (status); \ + if ((s) != kTfLiteOk) { \ + return s; \ + } \ + } while (0) + +// Single-precision complex data type compatible with the C99 definition. +typedef struct TfLiteComplex64 { + float re, im; // real and imaginary parts, respectively. +} TfLiteComplex64; + +// Double-precision complex data type compatible with the C99 definition. +typedef struct TfLiteComplex128 { + double re, im; // real and imaginary parts, respectively. +} TfLiteComplex128; + +// Half precision data type compatible with the C99 definition. +typedef struct TfLiteFloat16 { + uint16_t data; +} TfLiteFloat16; + +// Return the name of a given type, for error reporting purposes. +const char* TfLiteTypeGetName(TfLiteType type); + +// SupportedQuantizationTypes. +typedef enum TfLiteQuantizationType { + // No quantization. + kTfLiteNoQuantization = 0, + // Affine quantization (with support for per-channel quantization). + // Corresponds to TfLiteAffineQuantization. + kTfLiteAffineQuantization = 1, +} TfLiteQuantizationType; + +// Structure specifying the quantization used by the tensor, if-any. +typedef struct TfLiteQuantization { + // The type of quantization held by params. + TfLiteQuantizationType type; + // Holds an optional reference to a quantization param structure. The actual + // type depends on the value of the `type` field (see the comment there for + // the values and corresponding types). + void* params; +} TfLiteQuantization; + +// Parameters for asymmetric quantization across a dimension (i.e per output +// channel quantization). +// quantized_dimension specifies which dimension the scales and zero_points +// correspond to. +// For a particular value in quantized_dimension, quantized values can be +// converted back to float using: +// real_value = scale * (quantized_value - zero_point) +typedef struct TfLiteAffineQuantization { + TfLiteFloatArray* scale; + TfLiteIntArray* zero_point; + int32_t quantized_dimension; +} TfLiteAffineQuantization; + +/* A union of pointers that points to memory for a given tensor. */ +typedef union TfLitePtrUnion { + /* Do not access these members directly, if possible, use + * GetTensorData(tensor) instead, otherwise only access .data, as other + * members are deprecated. */ + int32_t* i32; + uint32_t* u32; + int64_t* i64; + uint64_t* u64; + float* f; + TfLiteFloat16* f16; + double* f64; + char* raw; + const char* raw_const; + uint8_t* uint8; + bool* b; + int16_t* i16; + uint16_t* ui16; + TfLiteComplex64* c64; + TfLiteComplex128* c128; + int8_t* int8; + /* Only use this member. */ + void* data; +} TfLitePtrUnion; + +// Memory allocation strategies. +// * kTfLiteMmapRo: Read-only memory-mapped data, or data externally allocated. +// * kTfLiteArenaRw: Arena allocated with no guarantees about persistence, +// and available during eval. +// * kTfLiteArenaRwPersistent: Arena allocated but persistent across eval, and +// only available during eval. +// * kTfLiteDynamic: Allocated during eval, or for string tensors. +// * kTfLitePersistentRo: Allocated and populated during prepare. This is +// useful for tensors that can be computed during prepare and treated +// as constant inputs for downstream ops (also in prepare). +// * kTfLiteCustom: Custom memory allocation provided by the user. See +// TfLiteCustomAllocation below. +typedef enum TfLiteAllocationType { + kTfLiteMemNone = 0, + kTfLiteMmapRo, + kTfLiteArenaRw, + kTfLiteArenaRwPersistent, + kTfLiteDynamic, + kTfLitePersistentRo, + kTfLiteCustom, +} TfLiteAllocationType; + +// The delegates should use zero or positive integers to represent handles. +// -1 is reserved from unallocated status. +typedef int TfLiteBufferHandle; +enum { + kTfLiteNullBufferHandle = -1, +}; + +// Storage format of each dimension in a sparse tensor. +typedef enum TfLiteDimensionType { + kTfLiteDimDense = 0, + kTfLiteDimSparseCSR, +} TfLiteDimensionType; + +// Metadata to encode each dimension in a sparse tensor. +typedef struct TfLiteDimensionMetadata { + TfLiteDimensionType format; + int dense_size; + TfLiteIntArray* array_segments; + TfLiteIntArray* array_indices; +} TfLiteDimensionMetadata; + +// Parameters used to encode a sparse tensor. For detailed explanation of each +// field please refer to lite/schema/schema.fbs. +typedef struct TfLiteSparsity { + TfLiteIntArray* traversal_order; + TfLiteIntArray* block_map; + TfLiteDimensionMetadata* dim_metadata; + int dim_metadata_size; +} TfLiteSparsity; + +// Defines a custom memory allocation not owned by the runtime. +// `data` should be aligned to kDefaultTensorAlignment defined in +// lite/util.h. (Currently 64 bytes) +// NOTE: See Interpreter.SetCustomAllocationForTensor for details on usage. +typedef struct TfLiteCustomAllocation { + void* data; + size_t bytes; +} TfLiteCustomAllocation; + +// The flags used in `Interpreter::SetCustomAllocationForTensor`. +// Note that this is a bitmask, so the values should be 1, 2, 4, 8, ...etc. +typedef enum TfLiteCustomAllocationFlags { + kTfLiteCustomAllocationFlagsNone = 0, + // Skips checking whether allocation.data points to an aligned buffer as + // expected by the TFLite runtime. + // NOTE: Setting this flag can cause crashes when calling Invoke(). + // Use with caution. + kTfLiteCustomAllocationFlagsSkipAlignCheck = 1, +} TfLiteCustomAllocationFlags; + +// A tensor in the interpreter system which is a wrapper around a buffer of +// data including a dimensionality (or NULL if not currently defined). +#ifndef TF_LITE_STATIC_MEMORY +typedef struct TfLiteTensor { + // The data type specification for data stored in `data`. This affects + // what member of `data` union should be used. + TfLiteType type; + // A union of data pointers. The appropriate type should be used for a typed + // tensor based on `type`. + TfLitePtrUnion data; + // A pointer to a structure representing the dimensionality interpretation + // that the buffer should have. NOTE: the product of elements of `dims` + // and the element datatype size should be equal to `bytes` below. + TfLiteIntArray* dims; + // Quantization information. + TfLiteQuantizationParams params; + // How memory is mapped + // kTfLiteMmapRo: Memory mapped read only. + // i.e. weights + // kTfLiteArenaRw: Arena allocated read write memory + // (i.e. temporaries, outputs). + TfLiteAllocationType allocation_type; + // The number of bytes required to store the data of this Tensor. I.e. + // (bytes of each element) * dims[0] * ... * dims[n-1]. For example, if + // type is kTfLiteFloat32 and dims = {3, 2} then + // bytes = sizeof(float) * 3 * 2 = 4 * 3 * 2 = 24. + size_t bytes; + + // An opaque pointer to a tflite::MMapAllocation + const void* allocation; + + // Null-terminated name of this tensor. + const char* name; + + // The delegate which knows how to handle `buffer_handle`. + // WARNING: This is an experimental interface that is subject to change. + struct TfLiteDelegate* delegate; + + // An integer buffer handle that can be handled by `delegate`. + // The value is valid only when delegate is not null. + // WARNING: This is an experimental interface that is subject to change. + TfLiteBufferHandle buffer_handle; + + // If the delegate uses its own buffer (e.g. GPU memory), the delegate is + // responsible to set data_is_stale to true. + // `delegate->CopyFromBufferHandle` can be called to copy the data from + // delegate buffer. + // WARNING: This is an // experimental interface that is subject to change. + bool data_is_stale; + + // True if the tensor is a variable. + bool is_variable; + + // Quantization information. Replaces params field above. + TfLiteQuantization quantization; + + // Parameters used to encode a sparse tensor. + // This is optional. The field is NULL if a tensor is dense. + // WARNING: This is an experimental interface that is subject to change. + TfLiteSparsity* sparsity; + + // Optional. Encodes shapes with unknown dimensions with -1. This field is + // only populated when unknown dimensions exist in a read-write tensor (i.e. + // an input or output tensor). (e.g. `dims` contains [1, 1, 1, 3] and + // `dims_signature` contains [1, -1, -1, 3]). If no unknown dimensions exist + // then `dims_signature` is either null, or set to an empty array. Note that + // this field only exists when TF_LITE_STATIC_MEMORY is not defined. + const TfLiteIntArray* dims_signature; +} TfLiteTensor; + +// A structure representing an instance of a node. +// This structure only exhibits the inputs, outputs, user defined data and some +// node properties (like statefulness), not other features like the type. +typedef struct TfLiteNode { + // Inputs to this node expressed as indices into the simulator's tensors. + TfLiteIntArray* inputs; + + // Outputs to this node expressed as indices into the simulator's tensors. + TfLiteIntArray* outputs; + + // intermediate tensors to this node expressed as indices into the simulator's + // tensors. + TfLiteIntArray* intermediates; + + // Temporary tensors uses during the computations. This usually contains no + // tensors, but ops are allowed to change that if they need scratch space of + // any sort. + TfLiteIntArray* temporaries; + + // Opaque data provided by the node implementer through `Registration.init`. + void* user_data; + + // Opaque data provided to the node if the node is a builtin. This is usually + // a structure defined in builtin_op_data.h + void* builtin_data; + + // Custom initial data. This is the opaque data provided in the flatbuffer. + // WARNING: This is an experimental interface that is subject to change. + const void* custom_initial_data; + int custom_initial_data_size; + + // The pointer to the delegate. This is non-null only when the node is + // created by calling `interpreter.ModifyGraphWithDelegate`. + // WARNING: This is an experimental interface that is subject to change. + struct TfLiteDelegate* delegate; + + // Whether this op might have side effect (e.g. stateful op). + bool might_have_side_effect; +} TfLiteNode; +#else // defined(TF_LITE_STATIC_MEMORY)? +// NOTE: This flag is opt-in only at compile time. +// +// Specific reduced TfLiteTensor struct for TF Micro runtime. This struct +// contains only the minimum fields required to initialize and prepare a micro +// inference graph. The fields in this struct have been ordered from +// largest-to-smallest for optimal struct sizeof. +// +// This struct does not use: +// - allocation +// - buffer_handle +// - data_is_stale +// - delegate +// - dims_signature +// - name +// - sparsity +typedef struct TfLiteTensor { + // TODO(b/155784997): Consider consolidating these quantization fields: + // Quantization information. Replaces params field above. + TfLiteQuantization quantization; + + // Quantization information. + TfLiteQuantizationParams params; + + // A union of data pointers. The appropriate type should be used for a typed + // tensor based on `type`. + TfLitePtrUnion data; + + // A pointer to a structure representing the dimensionality interpretation + // that the buffer should have. NOTE: the product of elements of `dims` + // and the element datatype size should be equal to `bytes` below. + TfLiteIntArray* dims; + + // The number of bytes required to store the data of this Tensor. I.e. + // (bytes of each element) * dims[0] * ... * dims[n-1]. For example, if + // type is kTfLiteFloat32 and dims = {3, 2} then + // bytes = sizeof(float) * 3 * 2 = 4 * 3 * 2 = 24. + size_t bytes; + + // The data type specification for data stored in `data`. This affects + // what member of `data` union should be used. + TfLiteType type; + + // How memory is mapped + // kTfLiteMmapRo: Memory mapped read only. + // i.e. weights + // kTfLiteArenaRw: Arena allocated read write memory + // (i.e. temporaries, outputs). + TfLiteAllocationType allocation_type; + + // True if the tensor is a variable. + bool is_variable; +} TfLiteTensor; + +// Specific reduced TfLiteNode struct for TF Micro runtime. This struct contains +// only the minimum fields required to represent a node. +// +// This struct does not use: +// - delegate +// - intermediates +// - temporaries +typedef struct TfLiteNode { + // Inputs to this node expressed as indices into the simulator's tensors. + TfLiteIntArray* inputs; + + // Outputs to this node expressed as indices into the simulator's tensors. + TfLiteIntArray* outputs; + + // intermediate tensors to this node expressed as indices into the simulator's + // tensors. + TfLiteIntArray* intermediates; + + // Opaque data provided by the node implementer through `Registration.init`. + void* user_data; + + // Opaque data provided to the node if the node is a builtin. This is usually + // a structure defined in builtin_op_data.h + void* builtin_data; + + // Custom initial data. This is the opaque data provided in the flatbuffer. + // WARNING: This is an experimental interface that is subject to change. + const void* custom_initial_data; + int custom_initial_data_size; +} TfLiteNode; +#endif // TF_LITE_STATIC_MEMORY + +// Light-weight tensor struct for TF Micro runtime. Provides the minimal amount +// of information required for a kernel to run during TfLiteRegistration::Eval. +// TODO(b/160955687): Move this field into TF_LITE_STATIC_MEMORY when TFLM +// builds with this flag by default internally. +typedef struct TfLiteEvalTensor { + // A union of data pointers. The appropriate type should be used for a typed + // tensor based on `type`. + TfLitePtrUnion data; + + // A pointer to a structure representing the dimensionality interpretation + // that the buffer should have. + TfLiteIntArray* dims; + + // The data type specification for data stored in `data`. This affects + // what member of `data` union should be used. + TfLiteType type; +} TfLiteEvalTensor; + +#ifndef TF_LITE_STATIC_MEMORY +// Free data memory of tensor `t`. +void TfLiteTensorDataFree(TfLiteTensor* t); + +// Free quantization data. +void TfLiteQuantizationFree(TfLiteQuantization* quantization); + +// Free sparsity parameters. +void TfLiteSparsityFree(TfLiteSparsity* sparsity); + +// Free memory of tensor `t`. +void TfLiteTensorFree(TfLiteTensor* t); + +// Set all of a tensor's fields (and free any previously allocated data). +void TfLiteTensorReset(TfLiteType type, const char* name, TfLiteIntArray* dims, + TfLiteQuantizationParams quantization, char* buffer, + size_t size, TfLiteAllocationType allocation_type, + const void* allocation, bool is_variable, + TfLiteTensor* tensor); + +// Copies the contents of 'src' in 'dst'. +// Function does nothing if either 'src' or 'dst' is passed as nullptr and +// return kTfLiteOk. +// Returns kTfLiteError if 'src' and 'dst' doesn't have matching data size. +// Note function copies contents, so it won't create new data pointer +// or change allocation type. +// All Tensor related properties will be copied from 'src' to 'dst' like +// quantization, sparsity, ... +TfLiteStatus TfLiteTensorCopy(const TfLiteTensor* src, TfLiteTensor* dst); + +// Change the size of the memory block owned by `tensor` to `num_bytes`. +// Tensors with allocation types other than `kTfLiteDynamic` will be ignored and +// a kTfLiteOk will be returned. +// `tensor`'s internal data buffer will be assigned a pointer +// which can safely be passed to free or realloc if `num_bytes` is zero. +// If `preserve_data` is true, tensor data will be unchanged in the range from +// the start of the region up to the minimum of the old and new sizes. In the +// case of NULL tensor, or an error allocating new memory, returns +// `kTfLiteError`. +TfLiteStatus TfLiteTensorResizeMaybeCopy(size_t num_bytes, TfLiteTensor* tensor, + bool preserve_data); + +// Change the size of the memory block owned by `tensor` to `num_bytes`. +// Tensors with allocation types other than kTfLiteDynamic will be ignored and +// a kTfLiteOk will be returned. +// `tensor`'s internal data buffer will be assigned a pointer +// which can safely be passed to free or realloc if `num_bytes` is zero. +// Tensor data will be unchanged in the range from the start of the region up to +// the minimum of the old and new sizes. In the case +// of NULL tensor, or an error allocating new memory, returns `kTfLiteError`. +TfLiteStatus TfLiteTensorRealloc(size_t num_bytes, TfLiteTensor* tensor); +#endif // TF_LITE_STATIC_MEMORY + +// WARNING: This is an experimental interface that is subject to change. +// +// Currently, TfLiteDelegateParams has to be allocated in a way that it's +// trivially destructable. It will be stored as `builtin_data` field in +// `TfLiteNode` of the delegate node. +// +// See also the `CreateDelegateParams` function in `interpreter.cc` details. +typedef struct TfLiteDelegateParams { + struct TfLiteDelegate* delegate; + TfLiteIntArray* nodes_to_replace; + TfLiteIntArray* input_tensors; + TfLiteIntArray* output_tensors; +} TfLiteDelegateParams; + +// WARNING: This is an experimental interface that is subject to change. +// +// Currently, TfLiteOpaqueDelegateParams has to be allocated in a way that it's +// trivially destructable. It will be stored as `builtin_data` field in +// `TfLiteNode` of the delegate node. +// +// See also the `CreateOpaqueDelegateParams` function in `subgraph.cc` +// details. +typedef struct TfLiteOpaqueDelegateParams { + TfLiteOpaqueDelegate* delegate; + void* delegate_data; + TfLiteIntArray* nodes_to_replace; + TfLiteIntArray* input_tensors; + TfLiteIntArray* output_tensors; +} TfLiteOpaqueDelegateParams; + +typedef struct TfLiteContext { + // Number of tensors in the context. + size_t tensors_size; + + // The execution plan contains a list of the node indices in execution + // order. execution_plan->size is the current number of nodes. And, + // execution_plan->data[0] is the first node that needs to be run. + // TfLiteDelegates can traverse the current execution plan by iterating + // through each member of this array and using GetNodeAndRegistration() to + // access details about a node. i.e. + // + // TfLiteIntArray* execution_plan; + // TF_LITE_ENSURE_STATUS(context->GetExecutionPlan(context, &execution_plan)); + // for (int exec_index = 0; exec_index < execution_plan->size; exec_index++) { + // int node_index = execution_plan->data[exec_index]; + // TfLiteNode* node; + // TfLiteRegistration* reg; + // context->GetNodeAndRegistration(context, node_index, &node, ®); + // } + // Note: the memory pointed by '`*execution_plan` is OWNED by TfLite runtime. + // Future calls to GetExecutionPlan invalidates earlier outputs. The following + // code snippet shows the issue of such an invocation pattern. After calling + // CheckNode, subsequent access to `plan_1st` is undefined. + // + // void CheckNode(const TfLiteNode* node) { + // ... + // TfLiteIntArray* plan_2nd; + // TF_LITE_ENSURE_STATUS(context->GetExecutionPlan(context, &plan_2nd)); + // ... + // } + // + // TfLiteIntArray* plan_1st; + // TF_LITE_ENSURE_STATUS(context->GetExecutionPlan(context, &plan_1st)); + // for (int exec_index = 0; exec_index < plan_1st->size; exec_index++) { + // int node_index = plan_1st->data[exec_index]; + // TfLiteNode* node; + // TfLiteRegistration* reg; + // context->GetNodeAndRegistration(context, node_index, &node, ®); + // CheckNode(node); + // } + // + // WARNING: This is an experimental interface that is subject to change. + TfLiteStatus (*GetExecutionPlan)(struct TfLiteContext* context, + TfLiteIntArray** execution_plan); + + // opaque full context ptr (an opaque c++ data structure) + void* impl_; + + // Request memory pointer be resized. Updates dimensions on the tensor. + // NOTE: ResizeTensor takes ownership of newSize. + TfLiteStatus (*ResizeTensor)(struct TfLiteContext*, TfLiteTensor* tensor, + TfLiteIntArray* new_size); + // Request that an error be reported with format string msg. + void (*ReportError)(struct TfLiteContext*, const char* msg, ...); + + // Add `tensors_to_add` tensors, preserving pre-existing Tensor entries. If + // non-null, the value pointed to by `first_new_tensor_index` will be set to + // the index of the first new tensor. + TfLiteStatus (*AddTensors)(struct TfLiteContext*, int tensors_to_add, + int* first_new_tensor_index); + + // Get a Tensor node by node_index. + // WARNING: This is an experimental interface that is subject to change. + TfLiteStatus (*GetNodeAndRegistration)( + struct TfLiteContext*, int node_index, TfLiteNode** node, + struct TfLiteRegistration** registration); + + // Replace ops with one or more stub delegate operations. This function + // does not take ownership of `nodes_to_replace`. + TfLiteStatus (*ReplaceNodeSubsetsWithDelegateKernels)( + struct TfLiteContext*, struct TfLiteRegistration registration, + const TfLiteIntArray* nodes_to_replace, struct TfLiteDelegate* delegate); + + // Number of threads that are recommended to subsystems like gemmlowp and + // eigen. + int recommended_num_threads; + + // Access external contexts by type. + // WARNING: This is an experimental interface that is subject to change. + TfLiteExternalContext* (*GetExternalContext)(struct TfLiteContext*, + TfLiteExternalContextType); + // Set the value of a external context. Does not take ownership of the + // pointer. + // WARNING: This is an experimental interface that is subject to change. + void (*SetExternalContext)(struct TfLiteContext*, TfLiteExternalContextType, + TfLiteExternalContext*); + + // Flag for allowing float16 precision for FP32 calculation. + // default: false. + // WARNING: This is an experimental API and subject to change. + bool allow_fp32_relax_to_fp16; + + // Pointer to the op-level profiler, if set; nullptr otherwise. + void* profiler; + + // Allocate persistent buffer which has the same life time as the interpreter. + // Returns nullptr on failure. + // The memory is allocated from heap for TFL, and from tail in TFLM. + // This method is only available in Init or Prepare stage. + // WARNING: This is an experimental interface that is subject to change. + void* (*AllocatePersistentBuffer)(struct TfLiteContext* ctx, size_t bytes); + + // Allocate a buffer which will be deallocated right after invoke phase. + // The memory is allocated from heap in TFL, and from volatile arena in TFLM. + // This method is only available in invoke stage. + // NOTE: If possible use RequestScratchBufferInArena method to avoid memory + // allocation during inference time. + // WARNING: This is an experimental interface that is subject to change. + TfLiteStatus (*AllocateBufferForEval)(struct TfLiteContext* ctx, size_t bytes, + void** ptr); + + // Request a scratch buffer in the arena through static memory planning. + // This method is only available in Prepare stage and the buffer is allocated + // by the interpreter between Prepare and Eval stage. In Eval stage, + // GetScratchBuffer API can be used to fetch the address. + // WARNING: This is an experimental interface that is subject to change. + TfLiteStatus (*RequestScratchBufferInArena)(struct TfLiteContext* ctx, + size_t bytes, int* buffer_idx); + + // Get the scratch buffer pointer. + // This method is only available in Eval stage. + // WARNING: This is an experimental interface that is subject to change. + void* (*GetScratchBuffer)(struct TfLiteContext* ctx, int buffer_idx); + + // Resize the memory pointer of the `tensor`. This method behaves the same as + // `ResizeTensor`, except that it makes a copy of the shape array internally + // so the shape array could be deallocated right afterwards. + // WARNING: This is an experimental interface that is subject to change. + TfLiteStatus (*ResizeTensorExplicit)(struct TfLiteContext* ctx, + TfLiteTensor* tensor, int dims, + const int* shape); + + // This method provides a preview of post-delegation partitioning. Each + // TfLiteDelegateParams in the referenced array corresponds to one instance of + // the delegate kernel. + // Example usage: + // + // TfLiteIntArray* nodes_to_replace = ...; + // TfLiteDelegateParams* params_array; + // int num_partitions = 0; + // TF_LITE_ENSURE_STATUS(context->PreviewDelegatePartitioning( + // context, delegate, nodes_to_replace, ¶ms_array, &num_partitions)); + // for (int idx = 0; idx < num_partitions; idx++) { + // const auto& partition_params = params_array[idx]; + // ... + // } + // + // NOTE: The context owns the memory referenced by partition_params_array. It + // will be cleared with another call to PreviewDelegateParitioning, or after + // TfLiteDelegateParams::Prepare returns. + // + // WARNING: This is an experimental interface that is subject to change. + TfLiteStatus (*PreviewDelegatePartitioning)( + struct TfLiteContext* context, const TfLiteIntArray* nodes_to_replace, + TfLiteDelegateParams** partition_params_array, int* num_partitions); + + // Returns a TfLiteTensor struct for a given index. + // WARNING: This is an experimental interface that is subject to change. + // WARNING: This method may not be available on all platforms. + TfLiteTensor* (*GetTensor)(const struct TfLiteContext* context, + int tensor_idx); + + // Returns a TfLiteEvalTensor struct for a given index. + // WARNING: This is an experimental interface that is subject to change. + // WARNING: This method may not be available on all platforms. + TfLiteEvalTensor* (*GetEvalTensor)(const struct TfLiteContext* context, + int tensor_idx); + + // Retrieves named metadata buffer from the TFLite model. + // Returns kTfLiteOk if metadata is successfully obtained from the flatbuffer + // Model: that is, there exists a `metadata` entry with given `name` string. + // (see TFLite's schema.fbs). + // The corresponding `buffer` information is populated in `ptr` & `bytes`. + // The data from `ptr` is valid for the lifetime of the Interpreter. + // + // WARNING: This is an experimental interface that is subject to change. + TfLiteStatus (*GetModelMetadata)(const struct TfLiteContext* context, + const char* name, const char** ptr, + size_t* bytes); +} TfLiteContext; + +// `TfLiteRegistrationExternal` is an external version of `TfLiteRegistration` +// for C API which doesn't use internal types (such as `TfLiteContext`) but only +// uses stable API types (such as `TfLiteOpaqueContext`). The purpose of each +// field is the exactly the same as with `TfLiteRegistration`. +typedef struct TfLiteRegistrationExternal TfLiteRegistrationExternal; + +typedef struct TfLiteRegistration { + // Initializes the op from serialized data. + // Called only *once* for the lifetime of the op, so any one-time allocations + // should be made here (unless they depend on tensor sizes). + // + // If a built-in op: + // `buffer` is the op's params data (TfLiteLSTMParams*). + // `length` is zero. + // If custom op: + // `buffer` is the op's `custom_options`. + // `length` is the size of the buffer. + // + // Returns a type-punned (i.e. void*) opaque data (e.g. a primitive pointer + // or an instance of a struct). + // + // The returned pointer will be stored with the node in the `user_data` field, + // accessible within prepare and invoke functions below. + // NOTE: if the data is already in the desired format, simply implement this + // function to return `nullptr` and implement the free function to be a no-op. + void* (*init)(TfLiteContext* context, const char* buffer, size_t length); + + // The pointer `buffer` is the data previously returned by an init invocation. + void (*free)(TfLiteContext* context, void* buffer); + + // prepare is called when the inputs this node depends on have been resized. + // context->ResizeTensor() can be called to request output tensors to be + // resized. + // Can be called multiple times for the lifetime of the op. + // + // Returns kTfLiteOk on success. + TfLiteStatus (*prepare)(TfLiteContext* context, TfLiteNode* node); + + // Execute the node (should read node->inputs and output to node->outputs). + // Returns kTfLiteOk on success. + TfLiteStatus (*invoke)(TfLiteContext* context, TfLiteNode* node); + + // profiling_string is called during summarization of profiling information + // in order to group executions together. Providing a value here will cause a + // given op to appear multiple times is the profiling report. This is + // particularly useful for custom ops that can perform significantly + // different calculations depending on their `user-data`. + const char* (*profiling_string)(const TfLiteContext* context, + const TfLiteNode* node); + + // Builtin codes. If this kernel refers to a builtin this is the code + // of the builtin. This is so we can do marshaling to other frameworks like + // NN API. + // Note: It is the responsibility of the registration binder to set this + // properly. + int32_t builtin_code; + + // Custom op name. If the op is a builtin, this will be null. + // Note: It is the responsibility of the registration binder to set this + // properly. + // WARNING: This is an experimental interface that is subject to change. + const char* custom_name; + + // The version of the op. + // Note: It is the responsibility of the registration binder to set this + // properly. + int version; + + // The external version of `TfLiteRegistration`. Since we can't use internal + // types (such as `TfLiteContext`) for C API to maintain ABI stability. + // C API user will provide `TfLiteRegistrationExternal` to implement custom + // ops. We keep it inside of `TfLiteRegistration` and use it to route + // callbacks properly. + TfLiteRegistrationExternal* registration_external; +} TfLiteRegistration; + +// Old version of `TfLiteRegistration` to maintain binary backward +// compatibility. +// WARNING: This structure is deprecated / not an official part of the API. +// It should be only used for binary backward compatibility. +typedef struct TfLiteRegistration_V1 { + void* (*init)(TfLiteContext* context, const char* buffer, size_t length); + void (*free)(TfLiteContext* context, void* buffer); + TfLiteStatus (*prepare)(TfLiteContext* context, TfLiteNode* node); + TfLiteStatus (*invoke)(TfLiteContext* context, TfLiteNode* node); + const char* (*profiling_string)(const TfLiteContext* context, + const TfLiteNode* node); + int32_t builtin_code; + const char* custom_name; + int version; +} TfLiteRegistration_V1; + +// The flags used in `TfLiteDelegate`. Note that this is a bitmask, so the +// values should be 1, 2, 4, 8, ...etc. +typedef enum TfLiteDelegateFlags { + kTfLiteDelegateFlagsNone = 0, + // The flag is set if the delegate can handle dynamic sized tensors. + // For example, the output shape of a `Resize` op with non-constant shape + // can only be inferred when the op is invoked. + // In this case, the Delegate is responsible for calling + // `SetTensorToDynamic` to mark the tensor as a dynamic tensor, and calling + // `ResizeTensor` when invoking the op. + // + // If the delegate isn't capable to handle dynamic tensors, this flag need + // to be set to false. + kTfLiteDelegateFlagsAllowDynamicTensors = 1, + + // This flag can be used by delegates (that allow dynamic tensors) to ensure + // applicable tensor shapes are automatically propagated in the case of tensor + // resizing. + // This means that non-dynamic (allocation_type != kTfLiteDynamic) I/O tensors + // of a delegate kernel will have correct shapes before its Prepare() method + // is called. The runtime leverages TFLite builtin ops in the original + // execution plan to propagate shapes. + // + // A few points to note: + // 1. This requires kTfLiteDelegateFlagsAllowDynamicTensors. If that flag is + // false, this one is redundant since the delegate kernels are re-initialized + // every time tensors are resized. + // 2. Enabling this flag adds some overhead to AllocateTensors(), since extra + // work is required to prepare the original execution plan. + // 3. This flag requires that the original execution plan only have ops with + // valid registrations (and not 'dummy' custom ops like with Flex). + // WARNING: This feature is experimental and subject to change. + kTfLiteDelegateFlagsRequirePropagatedShapes = 2, + + // This flag can be used by delegates to request per-operator profiling. If a + // node is a delegate node, this flag will be checked before profiling. If + // set, then the node will not be profiled. The delegate will then add per + // operator information using Profiler::EventType::OPERATOR_INVOKE_EVENT and + // the results will appear in the operator-wise Profiling section and not in + // the Delegate internal section. + kTfLiteDelegateFlagsPerOperatorProfiling = 4 +} TfLiteDelegateFlags; + +// WARNING: This is an experimental interface that is subject to change. +typedef struct TfLiteDelegate { + // Data that delegate needs to identify itself. This data is owned by the + // delegate. The delegate is owned in the user code, so the delegate is + // responsible for deallocating this when it is destroyed. + void* data_; + + // Invoked by ModifyGraphWithDelegate. This prepare is called, giving the + // delegate a view of the current graph through TfLiteContext*. It typically + // will look at the nodes and call ReplaceNodeSubsetsWithDelegateKernels() + // to ask the TensorFlow lite runtime to create macro-nodes to represent + // delegated subgraphs of the original graph. + TfLiteStatus (*Prepare)(TfLiteContext* context, + struct TfLiteDelegate* delegate); + + // Copy the data from delegate buffer handle into raw memory of the given + // 'tensor'. Note that the delegate is allowed to allocate the raw bytes as + // long as it follows the rules for kTfLiteDynamic tensors, in which case this + // cannot be null. + TfLiteStatus (*CopyFromBufferHandle)(TfLiteContext* context, + struct TfLiteDelegate* delegate, + TfLiteBufferHandle buffer_handle, + TfLiteTensor* tensor); + + // Copy the data from raw memory of the given 'tensor' to delegate buffer + // handle. This can be null if the delegate doesn't use its own buffer. + TfLiteStatus (*CopyToBufferHandle)(TfLiteContext* context, + struct TfLiteDelegate* delegate, + TfLiteBufferHandle buffer_handle, + TfLiteTensor* tensor); + + // Free the Delegate Buffer Handle. Note: This only frees the handle, but + // this doesn't release the underlying resource (e.g. textures). The + // resources are either owned by application layer or the delegate. + // This can be null if the delegate doesn't use its own buffer. + void (*FreeBufferHandle)(TfLiteContext* context, + struct TfLiteDelegate* delegate, + TfLiteBufferHandle* handle); + + // Bitmask flags. See the comments in `TfLiteDelegateFlags`. + int64_t flags; + + // The opaque delegate builder associated with this object. If set then the + // TF Lite runtime will give precedence to this field. E.g. instead of + // invoking 'Prepare' via the function pointer inside the 'TfLiteDelegate' + // object, the runtime will first check if the corresponding function + // pointer inside 'opaque_delegate_builder' is set and if so invoke that. + // + // If this field is non-null, then the 'Prepare' field (of the + // 'TfLiteDelegate') should be null. + struct TfLiteOpaqueDelegateBuilder* opaque_delegate_builder; +} TfLiteDelegate; + +// Build a 'null' delegate, with all the fields properly set to their default +// values. +TfLiteDelegate TfLiteDelegateCreate(void); + +// `TfLiteOpaqueDelegateBuilder` is used for constructing +// `TfLiteOpaqueDelegate`, see `TfLiteOpaqueDelegateCreate` below. Note: +// This struct is not ABI stable. +// +// For forward source compatibility `TfLiteOpaqueDelegateBuilder` objects should +// be brace-initialized, so that all fields (including any that might be added +// in the future) get zero-initialized. The purpose of each field is exactly +// the same as with `TfLiteDelegate`. +// +// WARNING: This is an experimental interface that is subject to change. +typedef struct TfLiteOpaqueDelegateBuilder { + // Data that delegate needs to identify itself. This data is owned by the + // delegate. The delegate is owned in the user code, so the delegate is + // responsible for deallocating this when it is destroyed. + void* data; + // Invoked by ModifyGraphWithDelegate. This prepare is called, giving the + // delegate a view of the current graph through TfLiteContext*. It typically + // will look at the nodes and call ReplaceNodeSubsetsWithDelegateKernels() + // to ask the TensorFlow lite runtime to create macro-nodes to represent + // delegated subgraphs of the original graph. + TfLiteStatus (*Prepare)(TfLiteOpaqueContext* context, // NOLINT + TfLiteOpaqueDelegate* delegate, void* data); + // Copies the data from delegate buffer handle into raw memory of the given + // 'tensor'. Note that the delegate is allowed to allocate the raw bytes as + // long as it follows the rules for kTfLiteDynamic tensors, in which case this + // cannot be null. + TfLiteStatus (*CopyFromBufferHandle)( // NOLINT + TfLiteOpaqueContext* context, TfLiteOpaqueDelegate* delegate, void* data, + TfLiteBufferHandle buffer_handle, TfLiteOpaqueTensor* tensor); + // Copies the data from raw memory of the given 'tensor' to delegate buffer + // handle. This can be null if the delegate doesn't use its own buffer. + TfLiteStatus (*CopyToBufferHandle)( // NOLINT + TfLiteOpaqueContext* context, TfLiteOpaqueDelegate* delegate, void* data, + TfLiteBufferHandle buffer_handle, TfLiteOpaqueTensor* tensor); + // Frees the Delegate Buffer Handle. Note: This only frees the handle, but + // this doesn't release the underlying resource (e.g. textures). The + // resources are either owned by application layer or the delegate. + // This can be null if the delegate doesn't use its own buffer. + void (*FreeBufferHandle)(TfLiteOpaqueContext* context, // NOLINT + TfLiteOpaqueDelegate* delegate, void* data, + TfLiteBufferHandle* handle); + // Bitmask flags. See the comments in `TfLiteDelegateFlags`. + int64_t flags; +} TfLiteOpaqueDelegateBuilder; + +// Creates an opaque delegate and returns its address. The opaque delegate will +// behave according to the provided 'opaque_delegate_builder'. The lifetime of +// the objects pointed to by any of the fields within the +// 'opaque_delegate_builder' must outlive the returned +// 'TfLiteOpaqueDelegate' and any 'TfLiteInterpreter', +// 'TfLiteInterpreterOptions', 'tflite::Interpreter', or +// 'tflite::InterpreterBuilder' that the delegate is added to. The returned +// address should be passed to 'TfLiteOpaqueDelegateDelete' for deletion. If +// 'opaque_delegate_builder' is a null pointer, then a null pointer will be +// returned. +TfLiteOpaqueDelegate* TfLiteOpaqueDelegateCreate( + const TfLiteOpaqueDelegateBuilder* opaque_delegate_builder); + +// Deletes the provided opaque 'delegate'. This function has no effect if the +// 'delegate' is a null pointer. +void TfLiteOpaqueDelegateDelete(TfLiteOpaqueDelegate* delegate); + +// Returns a pointer to the data associated with the provided opaque 'delegate'. +// +// A null pointer will be returned when: +// - The 'delegate' is null. +// - The 'data' field of the 'TfLiteOpaqueDelegateBuilder' used to construct the +// 'delegate' was null. +// - Or in case of any other error. +// - The 'delegate' has been constructed via a 'TfLiteOpaqueDelegateBuilder', +// but the 'data' field of the 'TfLiteOpaqueDelegateBuilder' is null. +// +// The data_ field of 'delegate' will be returned if the +// 'opaque_delegate_builder' field is null. +void* TfLiteOpaqueDelegateGetData(const TfLiteOpaqueDelegate* delegate); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus +#endif // TENSORFLOW_LITE_CORE_C_COMMON_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.cpp new file mode 100644 index 0000000..dd733f4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.cpp @@ -0,0 +1,192 @@ +/* Copyright 2023 Edge Impulse Inc. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#define FLATBUFFERS_LOCALE_INDEPENDENT 0 +#include +#include +#include + +#include +#include +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" + +#define FEATURE_TYPE float + +namespace tflite { +namespace ops { +namespace custom { +namespace tree_ensemble_classifier { + +struct OpDataTree { + uint32_t num_leaf_nodes; + uint32_t num_internal_nodes; + uint32_t num_trees; + const uint16_t* nodes_modes; + const uint16_t* nodes_featureids; + const float* nodes_values; + const uint16_t* nodes_truenodeids; + const uint16_t* nodes_falsenodeids; + const float* nodes_weights; + const uint8_t* nodes_classids; + const uint16_t* tree_root_ids; + const uint8_t* buffer_t; + size_t buffer_length; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + + const uint8_t* buffer_t = reinterpret_cast(buffer); + const flexbuffers::Map& m = flexbuffers::GetRoot(buffer_t, length).AsMap(); + + auto* data = new OpDataTree; + + data->buffer_t = buffer_t; + data->buffer_length = length; + + data->num_leaf_nodes = m["num_leaf_nodes"].AsUInt32(); + data->num_internal_nodes = m["num_internal_nodes"].AsUInt32(); + data->num_trees = m["num_trees"].AsUInt32(); + + data->nodes_modes = (uint16_t*)(m["nodes_modes"].AsBlob().data()); + data->nodes_featureids = (uint16_t*)(m["nodes_featureids"].AsBlob().data()); + data->nodes_values = (float*)(m["nodes_values"].AsBlob().data()); + data->nodes_truenodeids = (uint16_t*)(m["nodes_truenodeids"].AsBlob().data()); + data->nodes_falsenodeids = (uint16_t*)(m["nodes_falsenodeids"].AsBlob().data()); + data->nodes_weights = (float*)(m["nodes_weights"].AsBlob().data()); + data->nodes_classids = (uint8_t*)(m["nodes_classids"].AsBlob().data()); + data->tree_root_ids = (uint16_t*)(m["tree_root_ids"].AsBlob().data()); + + return data; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + + const OpDataTree* data = static_cast(node->user_data); + const flexbuffers::Map& m = flexbuffers::GetRoot(data->buffer_t, data->buffer_length).AsMap(); + + // The OOB checks below are very important to prevent vulnerabilities where an adversary sends + // us a malicious TFLite model, similar to: https://nvd.nist.gov/vuln/detail/CVE-2022-23560 + + int num_nodes = data->num_leaf_nodes + data->num_internal_nodes; + + // Check that the tree root ids are valid. + for (uint32_t i = 0; i < data->num_trees; i++) { + TF_LITE_ENSURE_EQ(context, data->tree_root_ids[i] < num_nodes, true); + TF_LITE_ENSURE_EQ(context, data->tree_root_ids[i] >= 0, true); + } + + // Check that all node indices are valid + for (uint32_t i = 0; i < data->num_internal_nodes; i++) { + TF_LITE_ENSURE_EQ(context, data->nodes_truenodeids[i] < num_nodes, true); + TF_LITE_ENSURE_EQ(context, data->nodes_truenodeids[i] >= 0, true); + TF_LITE_ENSURE_EQ(context, data->nodes_falsenodeids[i] < num_nodes, true); + TF_LITE_ENSURE_EQ(context, data->nodes_falsenodeids[i] >= 0, true); + } + + // Check all node arrays have the same length + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_featureids"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_values"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_truenodeids"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_falsenodeids"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_leaf_nodes, m["nodes_weights"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_leaf_nodes, m["nodes_classids"].AsBlob().size()); + + // Check data types are supported. Currently we only support one combination. + TF_LITE_ENSURE_EQ(context, strncmp(m["tree_index_type"].AsString().c_str(), "uint16", 6), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["node_value_type"].AsString().c_str(), "float32", 7), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["class_index_type"].AsString().c_str(), "uint8", 5), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["class_weight_type"].AsString().c_str(), "float32", 7), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["equality_operator"].AsString().c_str(), "leq", 3), 0); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + const TfLiteTensor* input = GetInput(context, node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, NumDimensions(input) == 2); + TfLiteTensor* output = GetOutput(context, node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + int input_width = SizeOfDimension(input, 1); + int output_width = SizeOfDimension(output, 1); + + // Check that all indices into the input/output tensor are valid + for (uint32_t i = 0; i < data->num_internal_nodes; i++) { + TF_LITE_ENSURE(context, data->nodes_featureids[i] < input_width); + TF_LITE_ENSURE(context, data->nodes_featureids[i] >= 0); + if (data->nodes_modes[i] == 0) { + TF_LITE_ENSURE(context, data->nodes_classids[i] < output_width); + TF_LITE_ENSURE(context, data->nodes_classids[i] >= 0); + } + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + + const OpDataTree* data = static_cast(node->user_data); + const TfLiteTensor* input; + TF_LITE_ENSURE_OK(context, GetInputSafe(context, node, 0, &input)); + TfLiteTensor* output; + TF_LITE_ENSURE_OK(context, GetOutputSafe(context, node, 0, &output)); + + float* output_data = GetTensorData(output); + memset(output_data, 0, GetTensorShape(output).FlatSize() * sizeof(float)); + + for (uint32_t i = 0; i < data->num_trees; i++) { + uint16_t ix = data->tree_root_ids[i]; + while (ix < data->num_internal_nodes) { + if (input->data.f[data->nodes_featureids[ix]] <= data->nodes_values[ix]) { + ix = data->nodes_truenodeids[ix]; + } else { + ix = data->nodes_falsenodeids[ix]; + } + } + ix -= data->num_internal_nodes; + output->data.f[data->nodes_classids[ix]] += data->nodes_weights[ix]; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration* Register_TREE_ENSEMBLE_CLASSIFIER() { + static TfLiteRegistration r = { + tree_ensemble_classifier::Init, + nullptr, + tree_ensemble_classifier::Prepare, + tree_ensemble_classifier::Eval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; + return &r; +} + +TfLiteRegistration* Register_TFLITE_TREE_ENSEMBLE_CLASSIFIER() { + return Register_TREE_ENSEMBLE_CLASSIFIER(); +} + +} // namespace custom +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.h new file mode 100644 index 0000000..fcdc98a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/custom/tree_ensemble_classifier.h @@ -0,0 +1,31 @@ +/* Copyright 2023 Edge Impulse Inc. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_TREE_ENSEMBLE_CLASSIFIER_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_TREE_ENSEMBLE_CLASSIFIER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { +namespace ops { +namespace custom { + +TfLiteRegistration* Register_TREE_ENSEMBLE_CLASSIFIER(); + +} +} +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_TREE_ENSEMBLE_CLASSIFIER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h new file mode 100644 index 0000000..05af6fd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h @@ -0,0 +1,1272 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_COMMON_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_COMMON_H_ + +#include +#ifndef ALLOW_SLOW_GENERIC_DEPTHWISECONV_FALLBACK +#ifdef GEMMLOWP_ALLOW_SLOW_SCALAR_FALLBACK +#define ALLOW_SLOW_GENERIC_DEPTHWISECONV_FALLBACK +#endif +#endif + +#include +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/optimized/neon_check.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +constexpr int kReverseShift = -1; + +inline void GetActivationMinMax(FusedActivationFunctionType ac, + float* output_activation_min, + float* output_activation_max) { + switch (ac) { + case FusedActivationFunctionType::kNone: + *output_activation_min = std::numeric_limits::lowest(); + *output_activation_max = std::numeric_limits::max(); + break; + case FusedActivationFunctionType::kRelu: + *output_activation_min = 0.f; + *output_activation_max = std::numeric_limits::max(); + break; + case FusedActivationFunctionType::kRelu1: + *output_activation_min = -1.f; + *output_activation_max = 1.f; + break; + case FusedActivationFunctionType::kRelu6: + *output_activation_min = 0.f; + *output_activation_max = 6.f; + break; + } +} + +template +inline T ActivationFunctionWithMinMax(T x, T output_activation_min, + T output_activation_max) { + using std::max; + using std::min; + return min(max(x, output_activation_min), output_activation_max); +} + +// Legacy function, left for compatibility only. +template +float ActivationFunction(float x) { + float output_activation_min, output_activation_max; + GetActivationMinMax(Ac, &output_activation_min, &output_activation_max); + return ActivationFunctionWithMinMax(x, output_activation_min, + output_activation_max); +} + +inline void BiasAndClamp(float clamp_min, float clamp_max, int bias_size, + const float* bias_data, int array_size, + float* array_data) { + if (bias_size == 0) return; + // Note: see b/132215220: in May 2019 we thought it would be OK to replace + // this with the Eigen one-liner: + // return (array.colwise() + bias).cwiseMin(clamp_max).cwiseMin(clamp_max). + // This turned out to severely regress performance: +4ms (i.e. 8%) on + // MobileNet v2 / 1.0 / 224. So we keep custom NEON code for now. + TFLITE_DCHECK_EQ((array_size % bias_size), 0); +#ifdef USE_NEON + float* array_ptr = array_data; + float* array_end_ptr = array_ptr + array_size; + const auto clamp_min_vec = vdupq_n_f32(clamp_min); + const auto clamp_max_vec = vdupq_n_f32(clamp_max); + for (; array_ptr != array_end_ptr; array_ptr += bias_size) { + int i = 0; + for (; i <= bias_size - 16; i += 16) { + auto b0 = vld1q_f32(bias_data + i); + auto b1 = vld1q_f32(bias_data + i + 4); + auto b2 = vld1q_f32(bias_data + i + 8); + auto b3 = vld1q_f32(bias_data + i + 12); + auto a0 = vld1q_f32(array_ptr + i); + auto a1 = vld1q_f32(array_ptr + i + 4); + auto a2 = vld1q_f32(array_ptr + i + 8); + auto a3 = vld1q_f32(array_ptr + i + 12); + auto x0 = vaddq_f32(a0, b0); + auto x1 = vaddq_f32(a1, b1); + auto x2 = vaddq_f32(a2, b2); + auto x3 = vaddq_f32(a3, b3); + x0 = vmaxq_f32(clamp_min_vec, x0); + x1 = vmaxq_f32(clamp_min_vec, x1); + x2 = vmaxq_f32(clamp_min_vec, x2); + x3 = vmaxq_f32(clamp_min_vec, x3); + x0 = vminq_f32(clamp_max_vec, x0); + x1 = vminq_f32(clamp_max_vec, x1); + x2 = vminq_f32(clamp_max_vec, x2); + x3 = vminq_f32(clamp_max_vec, x3); + vst1q_f32(array_ptr + i, x0); + vst1q_f32(array_ptr + i + 4, x1); + vst1q_f32(array_ptr + i + 8, x2); + vst1q_f32(array_ptr + i + 12, x3); + } + for (; i <= bias_size - 4; i += 4) { + auto b = vld1q_f32(bias_data + i); + auto a = vld1q_f32(array_ptr + i); + auto x = vaddq_f32(a, b); + x = vmaxq_f32(clamp_min_vec, x); + x = vminq_f32(clamp_max_vec, x); + vst1q_f32(array_ptr + i, x); + } + for (; i < bias_size; i++) { + array_ptr[i] = ActivationFunctionWithMinMax(array_ptr[i] + bias_data[i], + clamp_min, clamp_max); + } + } +#else // not NEON + for (int array_offset = 0; array_offset < array_size; + array_offset += bias_size) { + for (int i = 0; i < bias_size; i++) { + array_data[array_offset + i] = ActivationFunctionWithMinMax( + array_data[array_offset + i] + bias_data[i], clamp_min, clamp_max); + } + } +#endif +} + +// Single-rounding MultiplyByQuantizedMultiplier +#if TFLITE_SINGLE_ROUNDING +inline int32_t MultiplyByQuantizedMultiplier(int32_t x, + int32_t quantized_multiplier, + int shift) { + TFLITE_DCHECK(quantized_multiplier >= 0); + TFLITE_DCHECK(shift >= -31 && shift <= 30); + + const int64_t total_shift = 31 - shift; + const int64_t round = static_cast(1) << (total_shift - 1); + int64_t result = x * static_cast(quantized_multiplier) + round; + result = result >> total_shift; + + TFLITE_DCHECK(result >= std::numeric_limits::min() && + result <= std::numeric_limits::max()); + return static_cast(result); +} + +inline int32_t MultiplyByQuantizedMultiplierSmallerThanOneExp( + int32_t x, int32_t quantized_multiplier, int shift) { + TFLITE_DCHECK_LE(shift, 0); + return MultiplyByQuantizedMultiplier(x, quantized_multiplier, shift); +} + +inline int32_t MultiplyByQuantizedMultiplierGreaterThanOne( + int32_t x, int32_t quantized_multiplier, int shift) { + TFLITE_DCHECK_GE(shift, 0); + return MultiplyByQuantizedMultiplier(x, quantized_multiplier, shift); +} + +inline int32_t MultiplyByQuantizedMultiplier(int64_t x, + int32_t quantized_multiplier, + int shift) { + // Inputs: + // - quantized_multiplier has fixed point at bit 31 + // - shift is -31 to +7 (negative for right shift) + // + // Assumptions: The following input ranges are assumed + // - quantize_scale>=0 (the usual range is (1<<30) to (1>>31)-1) + // - scaling is chosen so final scaled result fits in int32_t + // - input x is in the range -(1<<47) <= x < (1<<47) + TFLITE_DCHECK(quantized_multiplier >= 0); + TFLITE_DCHECK(shift >= -31 && shift < 8); + TFLITE_DCHECK(x >= -(static_cast(1) << 47) && + x < (static_cast(1) << 47)); + + const int32_t reduced_multiplier = + (quantized_multiplier < 0x7FFF0000) + ? ((quantized_multiplier + (1 << 15)) >> 16) + : 0x7FFF; + const int64_t total_shift = 15 - shift; + const int64_t round = static_cast(1) << (total_shift - 1); + int64_t result = x * static_cast(reduced_multiplier) + round; + result = result >> total_shift; + + TFLITE_DCHECK(result >= std::numeric_limits::min() && + result <= std::numeric_limits::max()); + return static_cast(result); +} + +#ifdef USE_NEON +inline int32x4x4_t MultiplyByQuantizedMultiplier4Rows( + int32x4x4_t input_val, int32_t quantized_multiplier, int shift) { + TFLITE_DCHECK(quantized_multiplier >= 0); + + const int right_shift = std::min(-1, shift); + const int left_shift = shift - right_shift; + + const int32x4_t multiplier_dup = vdupq_n_s32(quantized_multiplier); + const int32x4_t left_shift_dup = vdupq_n_s32(left_shift); + const int32x4_t right_shift_dup = vdupq_n_s32(right_shift); + + int32x4x4_t result; + result.val[0] = vrshlq_s32( + vqdmulhq_s32(vshlq_s32(input_val.val[0], left_shift_dup), multiplier_dup), + right_shift_dup); + + result.val[1] = vrshlq_s32( + vqdmulhq_s32(vshlq_s32(input_val.val[1], left_shift_dup), multiplier_dup), + right_shift_dup); + + result.val[2] = vrshlq_s32( + vqdmulhq_s32(vshlq_s32(input_val.val[2], left_shift_dup), multiplier_dup), + right_shift_dup); + + result.val[3] = vrshlq_s32( + vqdmulhq_s32(vshlq_s32(input_val.val[3], left_shift_dup), multiplier_dup), + right_shift_dup); + + return result; +} +#endif // USE_NEON +// Double-rounding MultiplyByQuantizedMultiplier +#else +inline int32_t MultiplyByQuantizedMultiplierSmallerThanOneExp( + int32_t x, int32_t quantized_multiplier, int left_shift) { + using gemmlowp::RoundingDivideByPOT; + using gemmlowp::SaturatingRoundingDoublingHighMul; + return RoundingDivideByPOT( + SaturatingRoundingDoublingHighMul(x, quantized_multiplier), -left_shift); +} + +inline int32_t MultiplyByQuantizedMultiplierGreaterThanOne( + int32_t x, int32_t quantized_multiplier, int left_shift) { + using gemmlowp::SaturatingRoundingDoublingHighMul; + return SaturatingRoundingDoublingHighMul(x * (1 << left_shift), + quantized_multiplier); +} + +inline int32_t MultiplyByQuantizedMultiplier(int32_t x, + int32_t quantized_multiplier, + int shift) { + using gemmlowp::RoundingDivideByPOT; + using gemmlowp::SaturatingRoundingDoublingHighMul; + int left_shift = shift > 0 ? shift : 0; + int right_shift = shift > 0 ? 0 : -shift; + return RoundingDivideByPOT(SaturatingRoundingDoublingHighMul( + x * (1 << left_shift), quantized_multiplier), + right_shift); +} + +inline int32_t MultiplyByQuantizedMultiplier(int64_t x, + int32_t quantized_multiplier, + int shift) { + // Inputs: + // - quantized_multiplier has fixed point at bit 31 + // - shift is -31 to +7 (negative for right shift) + // + // Assumptions: The following input ranges are assumed + // - quantize_scale>=0 (the usual range is (1<<30) to (1>>31)-1) + // - scaling is chosen so final scaled result fits in int32_t + // - input x is in the range -(1<<47) <= x < (1<<47) + assert(quantized_multiplier >= 0); + assert(shift >= -31 && shift < 8); + assert(x >= -(static_cast(1) << 47) && + x < (static_cast(1) << 47)); + + int32_t reduced_multiplier = (quantized_multiplier < 0x7FFF0000) + ? ((quantized_multiplier + (1 << 15)) >> 16) + : 0x7FFF; + int total_shift = 15 - shift; + x = (x * (int64_t)reduced_multiplier) + ((int64_t)1 << (total_shift - 1)); + int32_t result = x >> total_shift; + return result; +} + +#ifdef USE_NEON +// Round uses ARM's rounding shift right. +inline int32x4x4_t MultiplyByQuantizedMultiplier4Rows( + int32x4x4_t input_val, int32_t quantized_multiplier, int shift) { + const int left_shift = std::max(shift, 0); + const int right_shift = std::min(shift, 0); + int32x4x4_t result; + + int32x4_t multiplier_dup = vdupq_n_s32(quantized_multiplier); + int32x4_t left_shift_dup = vdupq_n_s32(left_shift); + int32x4_t right_shift_dup = vdupq_n_s32(right_shift); + + result.val[0] = + vrshlq_s32(vqrdmulhq_s32(vshlq_s32(input_val.val[0], left_shift_dup), + multiplier_dup), + right_shift_dup); + + result.val[1] = + vrshlq_s32(vqrdmulhq_s32(vshlq_s32(input_val.val[1], left_shift_dup), + multiplier_dup), + right_shift_dup); + + result.val[2] = + vrshlq_s32(vqrdmulhq_s32(vshlq_s32(input_val.val[2], left_shift_dup), + multiplier_dup), + right_shift_dup); + + result.val[3] = + vrshlq_s32(vqrdmulhq_s32(vshlq_s32(input_val.val[3], left_shift_dup), + multiplier_dup), + right_shift_dup); + + return result; +} +#endif // USE_NEON +#endif // TFLITE_SINGLE_ROUNDING + +template +int CountLeadingZeros(T integer_input) { + static_assert(std::is_unsigned::value, + "Only unsigned integer types handled."); +#if defined(__GNUC__) + return integer_input ? __builtin_clz(integer_input) + : std::numeric_limits::digits; +#else + if (integer_input == 0) { + return std::numeric_limits::digits; + } + + const T one_in_leading_positive = static_cast(1) + << (std::numeric_limits::digits - 1); + int leading_zeros = 0; + while (integer_input < one_in_leading_positive) { + integer_input <<= 1; + ++leading_zeros; + } + return leading_zeros; +#endif +} + +template +inline int CountLeadingSignBits(T integer_input) { + static_assert(std::is_signed::value, "Only signed integer types handled."); +#if defined(__GNUC__) && !defined(__clang__) + return integer_input ? __builtin_clrsb(integer_input) + : std::numeric_limits::digits; +#else + using U = typename std::make_unsigned::type; + return integer_input >= 0 + ? CountLeadingZeros(static_cast(integer_input)) - 1 + : integer_input != std::numeric_limits::min() + ? CountLeadingZeros(2 * static_cast(-integer_input) - 1) + : 0; +#endif +} + +// Use "count leading zeros" helper functions to do a fast Floor(log_2(x)). +template +inline Integer FloorLog2(Integer n) { + static_assert(std::is_integral::value, ""); + static_assert(std::is_signed::value, ""); + static_assert(sizeof(Integer) == 4 || sizeof(Integer) == 8, ""); + TFLITE_CHECK_GT(n, 0); + if (sizeof(Integer) == 4) { + return 30 - CountLeadingSignBits(n); + } else { + return 62 - CountLeadingSignBits(n); + } +} + +namespace detail { + +// LUTPopulate takes an optional type-erased transform_params to allow passing +// extra parameters to the transform function pointer. const void* is used +// instead of std::function to be compatible with TFLite Micro +template +inline typename std::enable_if::value, + FloatT>::type +LUTTransform(Func transform, const void* /*transform_params*/, FloatT value) { + static_assert(std::is_floating_point::value, + "FloatT must be a floating-point type."); + return transform(value); +} + +template +inline typename std::enable_if< + std::is_same::value, FloatT>::type +LUTTransform(Func transform, const void* transform_params, FloatT value) { + static_assert(std::is_floating_point::value, + "FloatT must be a floating-point type."); + return transform(value, transform_params); +} + +// Use the same LUT generation code for both uint8_t and int8_t. Int8_t indexes +// will be directly casted to uint8_t, the int8 LUT will thus be ordered as [0, +// 1, ..., 127, -128, ..., -2, -1] instead of [-128, -127, ..., -1, 0, 1, ..., +// 126, 127]. +template +inline void LUTPopulateInt8(float input_scale, int32_t input_zero_point, + float output_scale, int32_t output_zero_point, + Func transform, const void* transform_params, + T* lut) { + static_assert( + std::is_same::value || std::is_same::value, + "T must be an uint8 or int8 type."); + uint8_t* lut_uint8 = reinterpret_cast(lut); + const float inverse_scale = 1 / output_scale; + int32_t maxval = std::numeric_limits::max(); + int32_t minval = std::numeric_limits::min(); + for (int32_t val = minval; val <= maxval; ++val) { + const float dequantized = input_scale * (val - input_zero_point); + const float transformed = + LUTTransform(transform, transform_params, dequantized); + const float rescaled = TfLiteRound(transformed * inverse_scale); + const int32_t quantized = + static_cast(rescaled + output_zero_point); + lut_uint8[static_cast(static_cast(val))] = static_cast( + static_cast(std::max(std::min(maxval, quantized), minval))); + } +} + +// Keep floating-point type configurable for backward compatibility. float +// should be used for FloatT by default. +template +inline void LUTPopulateInt16(FloatT input_scale, int32_t input_zero_point, + FloatT output_scale, int32_t output_zero_point, + Func transform, const void* transform_params, + int16_t* lut) { + static_assert(std::is_floating_point::value, + "FloatT must be a floating-point type."); + const FloatT input_min = + input_scale * (std::numeric_limits::min() - input_zero_point); + const FloatT input_max = + input_scale * (std::numeric_limits::max() - input_zero_point); + const FloatT output_min = + output_scale * (std::numeric_limits::min() - output_zero_point); + const FloatT output_max = + output_scale * (std::numeric_limits::max() - output_zero_point); + + const int nb_steps = 512; + const FloatT step = (input_max - input_min) / nb_steps; + const FloatT half_step = step / 2; + const FloatT output_scaling_inv = + static_cast(std::numeric_limits::max() - + std::numeric_limits::min() + 1) / + (output_max - output_min); + const FloatT table_min = + static_cast(std::numeric_limits::min()); + const FloatT table_max = + static_cast(std::numeric_limits::max()); + + for (int i = 0; i < nb_steps; i++) { + const FloatT val = + LUTTransform(transform, transform_params, input_min + i * step); + const FloatT val_midpoint = LUTTransform( + transform, transform_params, input_min + i * step + half_step); + const FloatT val_next = LUTTransform(transform, transform_params, + input_min + (i + 1) * step); + + const FloatT sample_val = TfLiteRound(val * output_scaling_inv); + const FloatT midpoint_interp_val = + TfLiteRound((val_next * output_scaling_inv + + TfLiteRound(val * output_scaling_inv)) / + 2); + const FloatT midpoint_val = TfLiteRound(val_midpoint * output_scaling_inv); + const FloatT midpoint_err = midpoint_interp_val - midpoint_val; + const FloatT bias = TfLiteRound(midpoint_err / 2); + + lut[i] = static_cast(std::min( + std::max(sample_val - bias, table_min), table_max)); + } + + lut[nb_steps] = static_cast(std::min( + std::max(TfLiteRound(LUTTransform( + transform, transform_params, input_max) * + output_scaling_inv), + table_min), + table_max)); +} + +} // namespace detail + +template +inline typename std::enable_if::value || + std::is_same::value, + void>::type +LUTPopulate(float input_scale, int32_t input_zero_point, float output_scale, + int32_t output_zero_point, float (*transform)(float), T* lut) { + detail::LUTPopulateInt8(input_scale, input_zero_point, output_scale, + output_zero_point, transform, nullptr, lut); +} + +template +inline typename std::enable_if::value || + std::is_same::value, + void>::type +LUTPopulate(float input_scale, int32_t input_zero_point, float output_scale, + int32_t output_zero_point, float (*transform)(float, const void*), + const void* transform_params, T* lut) { + detail::LUTPopulateInt8(input_scale, input_zero_point, output_scale, + output_zero_point, transform, transform_params, lut); +} + +template +inline typename std::enable_if::value, void>::type +LUTPopulate(float input_scale, int32_t input_zero_point, float output_scale, + int32_t output_zero_point, float (*transform)(float), T* lut) { + detail::LUTPopulateInt16(input_scale, input_zero_point, output_scale, + output_zero_point, transform, nullptr, lut); +} + +template +inline typename std::enable_if::value, void>::type +LUTPopulate(float input_scale, int32_t input_zero_point, float output_scale, + int32_t output_zero_point, float (*transform)(float, const void*), + const void* transform_params, T* lut) { + detail::LUTPopulateInt16(input_scale, input_zero_point, output_scale, + output_zero_point, transform, + transform_params, lut); +} + +// Deprecated, avoid usage and prefer the float version. Kept for +// backward-compatiblity. +template +inline typename std::enable_if::value, void>::type +LUTPopulate(double input_scale, int32_t input_zero_point, double output_scale, + int32_t output_zero_point, double (*transform)(double), T* lut) { + detail::LUTPopulateInt16(input_scale, input_zero_point, output_scale, + output_zero_point, transform, nullptr, lut); +} + +// The size of the LUT depends on the type of input. For uint8 and int8 inputs a +// simple 256 entries LUT is used. For int16 inputs the high 9 bits are used for +// indexing and the 7 remaining bits are used for interpolation. We thus use a +// 513-entries LUT for int16 cases, 512 for the 9-bit indexing and 1 extra entry +// to interpolate the last value. +template +constexpr int LUTSize() { + static_assert(std::is_same::value || + std::is_same::value || + std::is_same::value, + "Only LUTs with uint8, int8 or int16 inputs are supported."); + // As per c++11: constexpr methods cannot have more than one return statement. + return (std::is_same::value || std::is_same::value) + ? 256 + : 513; +} + +// int16_t -> int16_t table lookup with interpolation +// LUT must have 513 values +inline int16_t LUTLookup(int16_t value, const int16_t* lut) { + // 512 base values, lut[513] is only used to calculate the slope + const uint16_t index = static_cast(256 + (value >> 7)); + assert(index < 512 && "LUT index out of range."); + const int16_t offset = value & 0x7f; + + // Base and slope are Q0.x + const int16_t base = lut[index]; + const int16_t slope = lut[index + 1] - lut[index]; + + // Q0.x * Q0.7 = Q0.(x + 7) + // Round and convert from Q0.(x + 7) to Q0.x + const int delta = (slope * offset + 64) >> 7; + + // Q0.15 + Q0.15 + return static_cast(base + delta); +} + +// int8_t -> int8_t table lookup without interpolation +// LUT must have 256 values +// LUTPopulate has ordered the LUT so that indexing it with an +// int8_t is just done by casting it to an uint8_t. +inline int8_t LUTLookup(int8_t value, const int8_t* lut) { + return lut[static_cast(value)]; +} + +// uint8_t -> uint8_t table lookup without interpolation +// LUT must have 256 values +inline uint8_t LUTLookup(uint8_t value, const uint8_t* lut) { + return lut[value]; +} + +// Table of sigmoid(i/24) at 0.16 format - 256 elements. + +// We use combined sigmoid and tanh look-up table, since +// tanh(x) = 2*sigmoid(2*x) -1. +// Both functions are symmetric, so the LUT table is only needed +// for the absolute value of the input. +static const uint16_t sigmoid_table_uint16[256] = { + 32768, 33451, 34133, 34813, 35493, 36169, 36843, 37513, 38180, 38841, 39498, + 40149, 40794, 41432, 42064, 42688, 43304, 43912, 44511, 45102, 45683, 46255, + 46817, 47369, 47911, 48443, 48964, 49475, 49975, 50464, 50942, 51409, 51865, + 52311, 52745, 53169, 53581, 53983, 54374, 54755, 55125, 55485, 55834, 56174, + 56503, 56823, 57133, 57433, 57724, 58007, 58280, 58544, 58800, 59048, 59288, + 59519, 59743, 59959, 60168, 60370, 60565, 60753, 60935, 61110, 61279, 61441, + 61599, 61750, 61896, 62036, 62172, 62302, 62428, 62549, 62666, 62778, 62886, + 62990, 63090, 63186, 63279, 63368, 63454, 63536, 63615, 63691, 63765, 63835, + 63903, 63968, 64030, 64090, 64148, 64204, 64257, 64308, 64357, 64405, 64450, + 64494, 64536, 64576, 64614, 64652, 64687, 64721, 64754, 64786, 64816, 64845, + 64873, 64900, 64926, 64950, 64974, 64997, 65019, 65039, 65060, 65079, 65097, + 65115, 65132, 65149, 65164, 65179, 65194, 65208, 65221, 65234, 65246, 65258, + 65269, 65280, 65291, 65301, 65310, 65319, 65328, 65337, 65345, 65352, 65360, + 65367, 65374, 65381, 65387, 65393, 65399, 65404, 65410, 65415, 65420, 65425, + 65429, 65433, 65438, 65442, 65445, 65449, 65453, 65456, 65459, 65462, 65465, + 65468, 65471, 65474, 65476, 65479, 65481, 65483, 65485, 65488, 65489, 65491, + 65493, 65495, 65497, 65498, 65500, 65501, 65503, 65504, 65505, 65507, 65508, + 65509, 65510, 65511, 65512, 65513, 65514, 65515, 65516, 65517, 65517, 65518, + 65519, 65520, 65520, 65521, 65522, 65522, 65523, 65523, 65524, 65524, 65525, + 65525, 65526, 65526, 65526, 65527, 65527, 65528, 65528, 65528, 65529, 65529, + 65529, 65529, 65530, 65530, 65530, 65530, 65531, 65531, 65531, 65531, 65531, + 65532, 65532, 65532, 65532, 65532, 65532, 65533, 65533, 65533, 65533, 65533, + 65533, 65533, 65533, 65534, 65534, 65534, 65534, 65534, 65534, 65534, 65534, + 65534, 65534, 65535}; + +// TODO(b/77858996): Add these to gemmlowp. +template +IntegerType SaturatingAddNonGemmlowp(IntegerType a, IntegerType b) { + static_assert(std::is_same::value, "unimplemented"); + return a; +} + +template <> +inline std::int32_t SaturatingAddNonGemmlowp(std::int32_t a, std::int32_t b) { + std::int64_t a64 = a; + std::int64_t b64 = b; + std::int64_t sum = a64 + b64; + return static_cast(std::min( + static_cast(std::numeric_limits::max()), + std::max( + static_cast(std::numeric_limits::min()), + sum))); +} + +template +gemmlowp::FixedPoint SaturatingAddNonGemmlowp( + gemmlowp::FixedPoint a, + gemmlowp::FixedPoint b) { + return gemmlowp::FixedPoint::FromRaw( + SaturatingAddNonGemmlowp(a.raw(), b.raw())); +} + +template +IntegerType SaturatingSub(IntegerType a, IntegerType b) { + static_assert(std::is_same::value, "unimplemented"); + return a; +} + +template <> +inline std::int16_t SaturatingSub(std::int16_t a, std::int16_t b) { + std::int32_t a32 = a; + std::int32_t b32 = b; + std::int32_t diff = a32 - b32; + return static_cast( + std::min(static_cast(32767), + std::max(static_cast(-32768), diff))); +} + +template <> +inline std::int32_t SaturatingSub(std::int32_t a, std::int32_t b) { + std::int64_t a64 = a; + std::int64_t b64 = b; + std::int64_t diff = a64 - b64; + return static_cast(std::min( + static_cast(std::numeric_limits::max()), + std::max( + static_cast(std::numeric_limits::min()), + diff))); +} + +template +gemmlowp::FixedPoint SaturatingSub( + gemmlowp::FixedPoint a, + gemmlowp::FixedPoint b) { + return gemmlowp::FixedPoint::FromRaw( + SaturatingSub(a.raw(), b.raw())); +} +// End section to be moved to gemmlowp. + +template +IntegerType SaturatingRoundingMultiplyByPOTParam(IntegerType x, int exponent) { + if (exponent == 0) { + return x; + } + using ScalarIntegerType = + typename gemmlowp::FixedPointRawTypeTraits::ScalarRawType; + const IntegerType min = + gemmlowp::Dup(std::numeric_limits::min()); + const IntegerType max = + gemmlowp::Dup(std::numeric_limits::max()); + const int ScalarIntegerTypeBits = 8 * sizeof(ScalarIntegerType); + + const std::int32_t threshold = + ((1 << (ScalarIntegerTypeBits - 1 - exponent)) - 1); + const IntegerType positive_mask = + gemmlowp::MaskIfGreaterThan(x, gemmlowp::Dup(threshold)); + const IntegerType negative_mask = + gemmlowp::MaskIfLessThan(x, gemmlowp::Dup(-threshold)); + + IntegerType result = gemmlowp::ShiftLeft(x, exponent); + result = gemmlowp::SelectUsingMask(positive_mask, max, result); + result = gemmlowp::SelectUsingMask(negative_mask, min, result); + return result; +} + +// If we want to leave IntegerBits fixed, then multiplication +// by a power of two has to be saturating/rounding, not exact anymore. +template +gemmlowp::FixedPoint +SaturatingRoundingMultiplyByPOTParam( + gemmlowp::FixedPoint a, int exponent) { + return gemmlowp::FixedPoint::FromRaw( + SaturatingRoundingMultiplyByPOTParam(a.raw(), exponent)); +} + +// Convert int32_t multiplier to int16_t with rounding. +inline void DownScaleInt32ToInt16Multiplier(int32_t multiplier_int32_t, + int16_t* multiplier_int16_t) { + TFLITE_DCHECK_GE(multiplier_int32_t, 0); + static constexpr int32_t kRoundingOffset = 1 << 15; + if (multiplier_int32_t >= + std::numeric_limits::max() - kRoundingOffset) { + *multiplier_int16_t = std::numeric_limits::max(); + return; + } + const int32_t result = (multiplier_int32_t + kRoundingOffset) >> 16; + TFLITE_DCHECK_LE(result << 16, multiplier_int32_t + kRoundingOffset); + TFLITE_DCHECK_GT(result << 16, multiplier_int32_t - kRoundingOffset); + *multiplier_int16_t = result; + TFLITE_DCHECK_EQ(*multiplier_int16_t, result); +} + +// Minimum output bits to accommodate log of maximum input range. It actually +// does not matter if one considers, say, [-64,64] or [-64,64). +// +// For example, run this through Octave: +// [0:127; ... +// ceil(log(abs( log(2.^(0:127))+1 ))/log(2)); ... +// ceil(log(abs( log(2.^(0:127))+1 ))/log(2))] +constexpr int min_log_x_output_bits(int input_bits) { + return input_bits > 90 ? 7 + : input_bits > 44 ? 6 + : input_bits > 21 ? 5 + : input_bits > 10 ? 4 + : input_bits > 4 ? 3 + : input_bits > 1 ? 2 + : 1; +} + +// Although currently the name of this function says that it cannot handle +// values less than 1, in practice it can handle as low as 1/x_max, where +// x_max is the largest representable input. In other words, the output range +// is symmetric. +template +inline gemmlowp::FixedPoint +log_x_for_x_greater_than_or_equal_to_1_impl( + gemmlowp::FixedPoint input_val) { + // assert(__builtin_clz(0u) >= std::numeric_limits::digits - 1); + // assert(__builtin_clz(0u) <= std::numeric_limits::digits); + using FixedPoint0 = gemmlowp::FixedPoint; + // The reason for accumulating the result with an extra bit of headroom is + // that z_pow_2_adj * log_2 might be saturated, and adding num_scaled * + // recip_denom will otherwise introduce an error. + static constexpr int kAccumIntegerBits = OutputIntegerBits + 1; + using FixedPointAccum = gemmlowp::FixedPoint; + + const FixedPoint0 log_2 = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( + FixedPoint0, 1488522236, std::log(2.0)); + const FixedPoint0 sqrt_sqrt_half = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( + FixedPoint0, 1805811301, std::sqrt(std::sqrt(0.5))); + const FixedPoint0 sqrt_half = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( + FixedPoint0, 1518500250, std::sqrt(0.5)); + const FixedPoint0 one_quarter = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(FixedPoint0, 536870912, 1.0 / 4.0); + + const FixedPoint0 alpha_n = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( + FixedPoint0, 117049297, 11.0 / 240.0 * std::sqrt(std::sqrt(2.0))); + const FixedPoint0 alpha_d = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( + FixedPoint0, 127690142, 1.0 / 20.0 * std::sqrt(std::sqrt(2.0))); + const FixedPoint0 alpha_i = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( + FixedPoint0, 1057819769, + 2.0 / std::sqrt(std::sqrt(2.0)) - std::sqrt(std::sqrt(2.0))); + const FixedPoint0 alpha_f = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( + FixedPoint0, 638450708, 1.0 / 4.0 * std::sqrt(std::sqrt(2.0))); + + const FixedPointAccum shifted_quarter = + gemmlowp::Rescale(one_quarter); + + // Reinterpret the input value as Q0.31, because we will figure out the + // required shift "ourselves" instead of using, say, Rescale. + FixedPoint0 z_a = FixedPoint0::FromRaw(input_val.raw()); + // z_a_pow_2 = input_integer_bits - z_a_headroom; + int z_a_headroom_plus_1 = CountLeadingZeros(static_cast(z_a.raw())); + FixedPoint0 r_a_tmp = + SaturatingRoundingMultiplyByPOTParam(z_a, (z_a_headroom_plus_1 - 1)); + const int32_t r_a_raw = + SaturatingRoundingMultiplyByPOTParam((r_a_tmp * sqrt_half).raw(), 1); + // z_pow_2_adj = max(z_pow_2_a - 0.75, z_pow_2_b - 0.25); + // z_pow_2_adj = max(InputIntegerBits - z_a_headroom_plus_1 + 0.25, + // InputIntegerBits - z_b_headroom - 0.25); + const FixedPointAccum z_a_pow_2_adj = SaturatingAddNonGemmlowp( + FixedPointAccum::FromRaw(SaturatingRoundingMultiplyByPOTParam( + static_cast(InputIntegerBits - z_a_headroom_plus_1), + 31 - kAccumIntegerBits)), + shifted_quarter); + + // z_b is treated like z_a, but premultiplying by sqrt(0.5). + FixedPoint0 z_b = z_a * sqrt_half; + int z_b_headroom = CountLeadingZeros(static_cast(z_b.raw())) - 1; + const int32_t r_b_raw = + SaturatingRoundingMultiplyByPOTParam(z_a.raw(), z_b_headroom); + const FixedPointAccum z_b_pow_2_adj = SaturatingSub( + FixedPointAccum::FromRaw(SaturatingRoundingMultiplyByPOTParam( + static_cast(InputIntegerBits - z_b_headroom), + 31 - kAccumIntegerBits)), + shifted_quarter); + + const FixedPoint0 r = FixedPoint0::FromRaw(std::min(r_a_raw, r_b_raw)); + const FixedPointAccum z_pow_2_adj = FixedPointAccum::FromRaw( + std::max(z_a_pow_2_adj.raw(), z_b_pow_2_adj.raw())); + + const FixedPoint0 p = gemmlowp::RoundingHalfSum(r, sqrt_sqrt_half); + FixedPoint0 q = r - sqrt_sqrt_half; + q = q + q; + + const FixedPoint0 common_sq = q * q; + const FixedPoint0 num = q * r + q * common_sq * alpha_n; + const FixedPoint0 denom_minus_one_0 = + p * (alpha_i + q + alpha_d * common_sq) + alpha_f * q; + const FixedPoint0 recip_denom = + one_over_one_plus_x_for_x_in_0_1(denom_minus_one_0); + + const FixedPointAccum num_scaled = gemmlowp::Rescale(num); + return gemmlowp::Rescale(z_pow_2_adj * log_2 + + num_scaled * recip_denom); +} + +template +inline gemmlowp::FixedPoint +log_x_for_x_greater_than_or_equal_to_1( + gemmlowp::FixedPoint input_val) { + static_assert( + OutputIntegerBits >= min_log_x_output_bits(InputIntegerBits), + "Output integer bits must be sufficient to accommodate logs of inputs."); + return log_x_for_x_greater_than_or_equal_to_1_impl( + input_val); +} + +inline int32_t GetReciprocal(int32_t x, int x_integer_digits, + int* num_bits_over_unit) { + int headroom_plus_one = CountLeadingZeros(static_cast(x)); + // This is the number of bits to the left of the binary point above 1.0. + // Consider x=1.25. In that case shifted_scale=0.8 and + // no later adjustment will be needed. + *num_bits_over_unit = x_integer_digits - headroom_plus_one; + const int32_t shifted_sum_minus_one = + static_cast((static_cast(x) << headroom_plus_one) - + (static_cast(1) << 31)); + + gemmlowp::FixedPoint shifted_scale = + gemmlowp::one_over_one_plus_x_for_x_in_0_1( + gemmlowp::FixedPoint::FromRaw(shifted_sum_minus_one)); + return shifted_scale.raw(); +} + +inline void GetInvSqrtQuantizedMultiplierExp(int32_t input, int reverse_shift, + int32_t* output_inv_sqrt, + int* output_shift) { + TFLITE_DCHECK_GE(input, 0); + if (input <= 1) { + // Handle the input value 1 separately to avoid overflow in that case + // in the general computation below (b/143972021). Also handle 0 as if it + // were a 1. 0 is an invalid input here (divide by zero) and 1 is a valid + // but rare/unrealistic input value. We can expect both to occur in some + // incompletely trained models, but probably not in fully trained models. + *output_inv_sqrt = std::numeric_limits::max(); + *output_shift = 0; + return; + } + TFLITE_DCHECK_GT(input, 1); + *output_shift = 11; + while (input >= (1 << 29)) { + input /= 4; + ++*output_shift; + } + const unsigned max_left_shift_bits = + CountLeadingZeros(static_cast(input)) - 1; + const unsigned max_left_shift_bit_pairs = max_left_shift_bits / 2; + const unsigned left_shift_bit_pairs = max_left_shift_bit_pairs - 1; + *output_shift -= left_shift_bit_pairs; + input <<= 2 * left_shift_bit_pairs; + TFLITE_DCHECK_GE(input, (1 << 27)); + TFLITE_DCHECK_LT(input, (1 << 29)); + using gemmlowp::FixedPoint; + using gemmlowp::Rescale; + using gemmlowp::SaturatingRoundingMultiplyByPOT; + // Using 3 integer bits gives us enough room for the internal arithmetic in + // this Newton-Raphson iteration. + using F3 = FixedPoint; + using F0 = FixedPoint; + const F3 fixedpoint_input = F3::FromRaw(input >> 1); + const F3 fixedpoint_half_input = + SaturatingRoundingMultiplyByPOT<-1>(fixedpoint_input); + const F3 fixedpoint_half_three = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F3, (1 << 28) + (1 << 27), 1.5); + // Newton-Raphson iteration + // Naive unoptimized starting guess: x = 1 + F3 x = F3::One(); + // Naive unoptimized number of iterations: 5 + for (int i = 0; i < 5; i++) { + const F3 x3 = Rescale<3>(x * x * x); + x = Rescale<3>(fixedpoint_half_three * x - fixedpoint_half_input * x3); + } + const F0 fixedpoint_half_sqrt_2 = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F0, 1518500250, std::sqrt(2.) / 2.); + x = x * fixedpoint_half_sqrt_2; + *output_inv_sqrt = x.raw(); + if (*output_shift < 0) { + *output_inv_sqrt <<= -*output_shift; + *output_shift = 0; + } + // Convert right shift (right is positive) to left shift. + *output_shift *= reverse_shift; +} + +// DO NOT USE THIS STRUCT FOR NEW FUNCTIONALITY BEYOND IMPLEMENTING +// BROADCASTING. +// +// NdArrayDesc describes the shape and memory layout of an N-dimensional +// rectangular array of numbers. +// +// NdArrayDesc is basically identical to Dims defined in types.h. +// However, as Dims is to be deprecated, this class exists as an adaptor +// to enable simple unoptimized implementations of element-wise broadcasting +// operations. +template +struct NdArrayDesc { + // The "extent" of each dimension. Indices along dimension d must be in the + // half-open interval [0, extents[d]). + int extents[N]; + + // The number of *elements* (not bytes) between consecutive indices of each + // dimension. + int strides[N]; +}; + +// DO NOT USE THIS FUNCTION FOR NEW FUNCTIONALITY BEYOND IMPLEMENTING +// BROADCASTING. +// +// Same as Offset(), except takes as NdArrayDesc instead of Dims. +inline int SubscriptToIndex(const NdArrayDesc<4>& desc, int i0, int i1, int i2, + int i3) { + TFLITE_DCHECK(i0 >= 0 && i0 < desc.extents[0]); + TFLITE_DCHECK(i1 >= 0 && i1 < desc.extents[1]); + TFLITE_DCHECK(i2 >= 0 && i2 < desc.extents[2]); + TFLITE_DCHECK(i3 >= 0 && i3 < desc.extents[3]); + return i0 * desc.strides[0] + i1 * desc.strides[1] + i2 * desc.strides[2] + + i3 * desc.strides[3]; +} + +inline int SubscriptToIndex(const NdArrayDesc<5>& desc, int indexes[5]) { + return indexes[0] * desc.strides[0] + indexes[1] * desc.strides[1] + + indexes[2] * desc.strides[2] + indexes[3] * desc.strides[3] + + indexes[4] * desc.strides[4]; +} + +inline int SubscriptToIndex(const NdArrayDesc<8>& desc, int indexes[8]) { + return indexes[0] * desc.strides[0] + indexes[1] * desc.strides[1] + + indexes[2] * desc.strides[2] + indexes[3] * desc.strides[3] + + indexes[4] * desc.strides[4] + indexes[5] * desc.strides[5] + + indexes[6] * desc.strides[6] + indexes[7] * desc.strides[7]; +} + +// Given the dimensions of the operands for an element-wise binary broadcast, +// adjusts them so that they can be directly iterated over with simple loops. +// Returns the adjusted dims as instances of NdArrayDesc in 'desc0_out' and +// 'desc1_out'. 'desc0_out' and 'desc1_out' cannot be nullptr. +// +// This function assumes that the two input shapes are compatible up to +// broadcasting and the shorter one has already been prepended with 1s to be the +// same length. E.g., if shape0 is (1, 16, 16, 64) and shape1 is (1, 64), +// shape1 must already have been prepended to be (1, 1, 1, 64). Recall that +// Dims refer to shapes in reverse order. In this case, input0_dims will be +// (64, 16, 16, 1) and input1_dims will be (64, 1, 1, 1). +// +// When two shapes are compatible up to broadcasting, for each dimension d, +// the input extents are either equal, or one of them is 1. +// +// This function performs the following for each dimension d: +// - If the extents are equal, then do nothing since the loop that walks over +// both of the input arrays is correct. +// - Otherwise, one (and only one) of the extents must be 1. Say extent0 is 1 +// and extent1 is e1. Then set extent0 to e1 and stride0 *to 0*. This allows +// array0 to be referenced *at any index* in dimension d and still access the +// same slice. +template +inline void NdArrayDescsForElementwiseBroadcast(const Dims& input0_dims, + const Dims& input1_dims, + NdArrayDesc* desc0_out, + NdArrayDesc* desc1_out) { + TFLITE_DCHECK(desc0_out != nullptr); + TFLITE_DCHECK(desc1_out != nullptr); + + // Copy dims to desc. + for (int i = 0; i < N; ++i) { + desc0_out->extents[i] = input0_dims.sizes[i]; + desc0_out->strides[i] = input0_dims.strides[i]; + desc1_out->extents[i] = input1_dims.sizes[i]; + desc1_out->strides[i] = input1_dims.strides[i]; + } + + // Walk over each dimension. If the extents are equal do nothing. + // Otherwise, set the desc with extent 1 to have extent equal to the other and + // stride 0. + for (int i = 0; i < N; ++i) { + const int extent0 = ArraySize(input0_dims, i); + const int extent1 = ArraySize(input1_dims, i); + if (extent0 != extent1) { + if (extent0 == 1) { + desc0_out->strides[i] = 0; + desc0_out->extents[i] = extent1; + } else { + TFLITE_DCHECK_EQ(extent1, 1); + desc1_out->strides[i] = 0; + desc1_out->extents[i] = extent0; + } + } + } +} + +// Copies dims to desc, calculating strides. +template +inline void CopyDimsToDesc(const RuntimeShape& input_shape, + NdArrayDesc* desc_out) { + int desc_stride = 1; + for (int i = N - 1; i >= 0; --i) { + desc_out->extents[i] = input_shape.Dims(i); + desc_out->strides[i] = desc_stride; + desc_stride *= input_shape.Dims(i); + } +} + +template +inline void NdArrayDescsForElementwiseBroadcast( + const RuntimeShape& input0_shape, const RuntimeShape& input1_shape, + NdArrayDesc* desc0_out, NdArrayDesc* desc1_out) { + TFLITE_DCHECK(desc0_out != nullptr); + TFLITE_DCHECK(desc1_out != nullptr); + + auto extended_input0_shape = RuntimeShape::ExtendedShape(N, input0_shape); + auto extended_input1_shape = RuntimeShape::ExtendedShape(N, input1_shape); + + // Copy dims to desc, calculating strides. + CopyDimsToDesc(extended_input0_shape, desc0_out); + CopyDimsToDesc(extended_input1_shape, desc1_out); + + // Walk over each dimension. If the extents are equal do nothing. + // Otherwise, set the desc with extent 1 to have extent equal to the other and + // stride 0. + for (int i = 0; i < N; ++i) { + const int extent0 = extended_input0_shape.Dims(i); + const int extent1 = extended_input1_shape.Dims(i); + if (extent0 != extent1) { + if (extent0 == 1) { + desc0_out->strides[i] = 0; + desc0_out->extents[i] = extent1; + } else { + TFLITE_DCHECK_EQ(extent1, 1); + desc1_out->strides[i] = 0; + desc1_out->extents[i] = extent0; + } + } + } +} + +template +inline void NdArrayDescsForElementwiseBroadcast( + const RuntimeShape& input0_shape, const RuntimeShape& input1_shape, + const RuntimeShape& input2_shape, NdArrayDesc* desc0_out, + NdArrayDesc* desc1_out, NdArrayDesc* desc2_out) { + TFLITE_DCHECK(desc0_out != nullptr); + TFLITE_DCHECK(desc1_out != nullptr); + TFLITE_DCHECK(desc2_out != nullptr); + + auto extended_input0_shape = RuntimeShape::ExtendedShape(N, input0_shape); + auto extended_input1_shape = RuntimeShape::ExtendedShape(N, input1_shape); + auto extended_input2_shape = RuntimeShape::ExtendedShape(N, input2_shape); + + // Copy dims to desc, calculating strides. + CopyDimsToDesc(extended_input0_shape, desc0_out); + CopyDimsToDesc(extended_input1_shape, desc1_out); + CopyDimsToDesc(extended_input2_shape, desc2_out); + + // Walk over each dimension. If the extents are equal do nothing. + // Otherwise, set the desc with extent 1 to have extent equal to the other and + // stride 0. + for (int i = 0; i < N; ++i) { + const int extent0 = extended_input0_shape.Dims(i); + const int extent1 = extended_input1_shape.Dims(i); + const int extent2 = extended_input2_shape.Dims(i); + + int extent = extent0; + if (extent1 != 1) extent = extent1; + if (extent2 != 1) extent = extent2; + + TFLITE_DCHECK(extent0 == 1 || extent0 == extent); + TFLITE_DCHECK(extent1 == 1 || extent1 == extent); + TFLITE_DCHECK(extent2 == 1 || extent2 == extent); + + if (!(extent0 == extent1 && extent1 == extent2)) { + if (extent0 == 1) { + desc0_out->strides[i] = 0; + desc0_out->extents[i] = extent; + } + if (extent1 == 1) { + desc1_out->strides[i] = 0; + desc1_out->extents[i] = extent; + } + if (extent2 == 1) { + desc2_out->strides[i] = 0; + desc2_out->extents[i] = extent; + } + } + } +} + +// Detailed implementation of NDOpsHelper, the indexes must be a zero array. +// This implementation is equivalent to N nested loops. Ex, if N=4, it can be +// re-writen as: +// for (int b = 0; b < output.extents[0]; ++b) { +// for (int y = 0; y < output.extents[1]; ++y) { +// for (int x = 0; x < output.extents[2]; ++x) { +// for (int c = 0; c < output.extents[3]; ++c) { +// calc({b,y,x,c}); +// } +// } +// } +// } +template +typename std::enable_if::type NDOpsHelperImpl( + const NdArrayDesc& output, const Calc& calc, int indexes[N]) { + for (indexes[DIM] = 0; indexes[DIM] < output.extents[DIM]; ++indexes[DIM]) { + NDOpsHelperImpl(output, calc, indexes); + } +} + +template +typename std::enable_if::type NDOpsHelperImpl( + const NdArrayDesc& output, const Calc& calc, int indexes[N]) { + for (indexes[DIM] = 0; indexes[DIM] < output.extents[DIM]; ++indexes[DIM]) { + calc(indexes); + } +} + +// Execute the calc function in the innermost iteration based on the shape of +// the output. The calc function should take a single argument of type int[N]. +template +inline void NDOpsHelper(const NdArrayDesc& output, const Calc& calc) { + int indexes[N] = {0}; + NDOpsHelperImpl(output, calc, indexes); +} +// Copied from gemmlowp::RoundDown when we dropped direct dependency on +// gemmlowp. +// +// Returns the runtime argument rounded down to the nearest multiple of +// the fixed Modulus. +template +Integer RoundDown(Integer i) { + return i - (i % Modulus); +} + +// Copied from gemmlowp::RoundUp when we dropped direct dependency on +// gemmlowp. +// +// Returns the runtime argument rounded up to the nearest multiple of +// the fixed Modulus. +template +Integer RoundUp(Integer i) { + return RoundDown(i + Modulus - 1); +} + +// Copied from gemmlowp::CeilQuotient when we dropped direct dependency on +// gemmlowp. +// +// Returns the quotient a / b rounded up ('ceil') to the nearest integer. +template +Integer CeilQuotient(Integer a, Integer b) { + return (a + b - 1) / b; +} + +// This function is a copy of gemmlowp::HowManyThreads, copied when we dropped +// the direct dependency of internal/optimized/ on gemmlowp. +// +// It computes a reasonable number of threads to use for a GEMM of shape +// (rows, cols, depth). +// +// TODO(b/131910176): get rid of this function by switching each call site +// to its own more sensible logic for its own workload. +template +inline int LegacyHowManyThreads(int max_num_threads, int rows, int cols, + int depth) { + // Early-exit in the default case where multi-threading is disabled. + if (max_num_threads == 1) { + return 1; + } + + // Ensure that each thread has KernelRows rows to process, if at all possible. + int thread_count = std::min(max_num_threads, rows / KernelRows); + + // Limit the number of threads according to the overall size of the problem. + if (thread_count > 1) { + // Empirically determined value. + static constexpr std::uint64_t min_cubic_size_per_thread = 64 * 1024; + + // We can only multiply two out of three sizes without risking overflow + const std::uint64_t cubic_size = + std::uint64_t(rows) * std::uint64_t(cols) * std::uint64_t(depth); + + thread_count = std::min( + thread_count, static_cast(cubic_size / min_cubic_size_per_thread)); + } + + if (thread_count < 1) { + thread_count = 1; + } + + assert(thread_count > 0 && thread_count <= max_num_threads); + return thread_count; +} + +template +void optimized_ops_preload_l1_stream(const T* ptr) { +#ifdef __GNUC__ + // builtin offered by GCC-compatible compilers including clang + __builtin_prefetch(ptr, /* 0 means read */ 0, /* 0 means no locality */ 0); +#else + (void)ptr; +#endif +} + +template +void optimized_ops_preload_l1_keep(const T* ptr) { +#ifdef __GNUC__ + // builtin offered by GCC-compatible compilers including clang + __builtin_prefetch(ptr, /* 0 means read */ 0, /* 3 means high locality */ 3); +#else + (void)ptr; +#endif +} + +template +void optimized_ops_prefetch_write_l1_keep(const T* ptr) { +#ifdef __GNUC__ + // builtin offered by GCC-compatible compilers including clang + __builtin_prefetch(ptr, /* 1 means write */ 1, /* 3 means high locality */ 3); +#else + (void)ptr; +#endif +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_COMMON_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h new file mode 100644 index 0000000..1fafbf0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h @@ -0,0 +1,123 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_COMPATIBILITY_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_COMPATIBILITY_H_ + +#include +#include "edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h" + +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" + +#ifndef TFLITE_DCHECK +#define TFLITE_DCHECK(condition) (condition) ? (void)0 : TFLITE_ASSERT_FALSE +#endif + +#ifndef TFLITE_DCHECK_EQ +#define TFLITE_DCHECK_EQ(x, y) ((x) == (y)) ? (void)0 : TFLITE_ASSERT_FALSE +#endif + +#ifndef TFLITE_DCHECK_NE +#define TFLITE_DCHECK_NE(x, y) ((x) != (y)) ? (void)0 : TFLITE_ASSERT_FALSE +#endif + +#ifndef TFLITE_DCHECK_GE +#define TFLITE_DCHECK_GE(x, y) ((x) >= (y)) ? (void)0 : TFLITE_ASSERT_FALSE +#endif + +#ifndef TFLITE_DCHECK_GT +#define TFLITE_DCHECK_GT(x, y) ((x) > (y)) ? (void)0 : TFLITE_ASSERT_FALSE +#endif + +#ifndef TFLITE_DCHECK_LE +#define TFLITE_DCHECK_LE(x, y) ((x) <= (y)) ? (void)0 : TFLITE_ASSERT_FALSE +#endif + +#ifndef TFLITE_DCHECK_LT +#define TFLITE_DCHECK_LT(x, y) ((x) < (y)) ? (void)0 : TFLITE_ASSERT_FALSE +#endif + +// TODO(ahentz): Clean up: We should stick to the DCHECK versions. +#ifndef TFLITE_CHECK +#define TFLITE_CHECK(condition) (condition) ? (void)0 : TFLITE_ABORT +#endif + +#ifndef TFLITE_CHECK_EQ +#define TFLITE_CHECK_EQ(x, y) ((x) == (y)) ? (void)0 : TFLITE_ABORT +#endif + +#ifndef TFLITE_CHECK_NE +#define TFLITE_CHECK_NE(x, y) ((x) != (y)) ? (void)0 : TFLITE_ABORT +#endif + +#ifndef TFLITE_CHECK_GE +#define TFLITE_CHECK_GE(x, y) ((x) >= (y)) ? (void)0 : TFLITE_ABORT +#endif + +#ifndef TFLITE_CHECK_GT +#define TFLITE_CHECK_GT(x, y) ((x) > (y)) ? (void)0 : TFLITE_ABORT +#endif + +#ifndef TFLITE_CHECK_LE +#define TFLITE_CHECK_LE(x, y) ((x) <= (y)) ? (void)0 : TFLITE_ABORT +#endif + +#ifndef TFLITE_CHECK_LT +#define TFLITE_CHECK_LT(x, y) ((x) < (y)) ? (void)0 : TFLITE_ABORT +#endif + +#ifndef TF_LITE_STATIC_MEMORY +// TODO(b/162019032): Consider removing these type-aliases. +using int8 = std::int8_t; +using uint8 = std::uint8_t; +using int16 = std::int16_t; +using uint16 = std::uint16_t; +using int32 = std::int32_t; +using uint32 = std::uint32_t; +#endif // !defined(TF_LITE_STATIC_MEMORY) + +// Allow for cross-compiler usage of function signatures - currently used for +// specifying named RUY profiler regions in templated methods. +#if defined(_MSC_VER) +#define TFLITE_PRETTY_FUNCTION __FUNCSIG__ +#elif defined(__GNUC__) +#define TFLITE_PRETTY_FUNCTION __PRETTY_FUNCTION__ +#else +#define TFLITE_PRETTY_FUNCTION __func__ +#endif + +// TFLITE_DEPRECATED() +// +// Duplicated from absl/base/macros.h to avoid pulling in that library. +// Marks a deprecated class, struct, enum, function, method and variable +// declarations. The macro argument is used as a custom diagnostic message (e.g. +// suggestion of a better alternative). +// +// Example: +// +// class TFLITE_DEPRECATED("Use Bar instead") Foo {...}; +// TFLITE_DEPRECATED("Use Baz instead") void Bar() {...} +// +// Every usage of a deprecated entity will trigger a warning when compiled with +// clang's `-Wdeprecated-declarations` option. This option is turned off by +// default, but the warnings will be reported by clang-tidy. +#if defined(__clang__) && __cplusplus >= 201103L +#define TFLITE_DEPRECATED(message) __attribute__((deprecated(message))) +#endif + +#ifndef TFLITE_DEPRECATED +#define TFLITE_DEPRECATED(message) +#endif + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_COMPATIBILITY_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h new file mode 100644 index 0000000..c97cc31 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h @@ -0,0 +1,40 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_CPPMATH_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_CPPMATH_H_ + +#include + +namespace tflite { + +#if defined(TF_LITE_USE_GLOBAL_CMATH_FUNCTIONS) || \ + (defined(__ANDROID__) && !defined(__NDK_MAJOR__)) || defined(__ZEPHYR__) +#define TF_LITE_GLOBAL_STD_PREFIX +#else +#define TF_LITE_GLOBAL_STD_PREFIX std +#endif + +#define DECLARE_STD_GLOBAL_SWITCH1(tf_name, std_name) \ + template \ + inline T tf_name(const T x) { \ + return TF_LITE_GLOBAL_STD_PREFIX::std_name(x); \ + } + +DECLARE_STD_GLOBAL_SWITCH1(TfLiteRound, round); +DECLARE_STD_GLOBAL_SWITCH1(TfLiteExpm1, expm1); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_CPPMATH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/max.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/max.h new file mode 100644 index 0000000..d636564 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/max.h @@ -0,0 +1,30 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_MAX_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_MAX_H_ + +#include + +namespace tflite { + +// Patched by Edge Impulse, remove std::fmax +template +inline T TfLiteMax(const T& x, const T& y) { + return std::max(x, y); +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_MAX_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/min.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/min.h new file mode 100644 index 0000000..68049b4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/min.h @@ -0,0 +1,30 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_MIN_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_MIN_H_ + +#include + +namespace tflite { + +// Patched by Edge Impulse, remove std::fmin +template +inline T TfLiteMin(const T& x, const T& y) { + return std::min(x, y); +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_MIN_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/optimized/neon_check.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/optimized/neon_check.h new file mode 100644 index 0000000..7df1129 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/optimized/neon_check.h @@ -0,0 +1,20 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_OPTIMIZED_NEON_CHECK_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_OPTIMIZED_NEON_CHECK_H_ + +// TFLM does not need to utilize any Neon optimizations. + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_OPTIMIZED_NEON_CHECK_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h new file mode 100644 index 0000000..a03e502 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h @@ -0,0 +1,122 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_PORTABLE_TENSOR_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_PORTABLE_TENSOR_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +inline RuntimeShape GetTensorShape(std::vector data) { + return RuntimeShape(data.size(), data.data()); +} + +// A list of tensors in a format that can be used by kernels like split and +// concatenation. +template +class VectorOfTensors { + public: + // Build with the tensors in 'tensor_list'. + VectorOfTensors(const TfLiteContext& context, + const TfLiteIntArray& tensor_list) { + int num_tensors = tensor_list.size; + + all_data_.reserve(num_tensors); + all_shape_.reserve(num_tensors); + all_shape_ptr_.reserve(num_tensors); + + for (int i = 0; i < num_tensors; ++i) { + TfLiteTensor* t = context.GetTensor(&context, tensor_list.data[i]); + all_data_.push_back(GetTensorData(t)); + all_shape_.push_back(GetTensorShape(t)); + } + + // Taking the pointer from inside a std::vector is only OK if the vector is + // never modified, so we populate all_shape in the previous loop and then we + // are free to grab iterators here. + for (int i = 0; i < num_tensors; ++i) { + all_shape_ptr_.push_back(&all_shape_[i]); + } + } + // Return a pointer to the data pointers of all tensors in the list. For + // example: + // float* const* f = v.data(); + // f[0][1] is the second element of the first tensor. + T* const* data() const { return all_data_.data(); } + + // Return a pointer the shape pointers of all tensors in the list. For + // example: + // const RuntimeShape* const* d = v.dims(); + // dims[1] are the dimensions of the second tensor in the list. + const RuntimeShape* const* shapes() const { return all_shape_ptr_.data(); } + + private: + std::vector all_data_; + std::vector all_shape_; + std::vector all_shape_ptr_; +}; + +// A list of quantized tensors in a format that can be used by kernels like +// split and concatenation. +class VectorOfQuantizedTensors : public VectorOfTensors { + public: + // Build with the tensors in 'tensor_list'. + VectorOfQuantizedTensors(const TfLiteContext& context, + const TfLiteIntArray& tensor_list) + : VectorOfTensors(context, tensor_list) { + for (int i = 0; i < tensor_list.size; ++i) { + TfLiteTensor* t = context.GetTensor(&context, tensor_list.data[i]); + zero_point_.push_back(t->params.zero_point); + scale_.push_back(t->params.scale); + } + } + + const float* scale() const { return scale_.data(); } + const int32_t* zero_point() const { return zero_point_.data(); } + + private: + std::vector zero_point_; + std::vector scale_; +}; + +// Writes randomly accessed values from `input` sequentially into `output`. +template +class SequentialTensorWriter { + public: + SequentialTensorWriter(const TfLiteTensor* input, TfLiteTensor* output) { + input_data_ = GetTensorData(input); + output_ptr_ = GetTensorData(output); + } + SequentialTensorWriter(const T* input_data, T* output_data) + : input_data_(input_data), output_ptr_(output_data) {} + + void Write(int position) { *output_ptr_++ = input_data_[position]; } + void WriteN(int position, int len) { + memcpy(output_ptr_, &input_data_[position], sizeof(T) * len); + output_ptr_ += len; + } + + private: + const T* input_data_; + T* output_ptr_; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_PORTABLE_TENSOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.cpp new file mode 100644 index 0000000..ec7ad76 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.cpp @@ -0,0 +1,86 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_TENSOR_UTILS_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_TENSOR_UTILS_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" + +#if defined(_MSC_VER) +#define __restrict__ __restrict +#endif + +namespace tflite { + +// Not all backends support CpuBackendContext usage, so forward declare to avoid +// pulling in its implementation. Use of CpuBackendContext in method +// implementations is purely optional. +class CpuBackendContext; + +namespace tensor_utils { + +// Apply Rectified Linear to elements of a vector. +void ApplyReluToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result) { + for (int v = 0; v < v_size; v++) { + result[v] = std::max(0.0f, vector[v]); + } +} + +// Apply Rectified Linear 1 (cap to [-1;1]) to elements of a vector +void ApplyRelu1ToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result) { + for (int v = 0; v < v_size; v++) { + result[v] = std::max(-1.0f, std::min(vector[v], 1.0f)); + } +} + +// Apply Rectified Linear 6 (cap to [0;6]) to elements of a vector +void ApplyRelu6ToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result) { + for (int v = 0; v < v_size; v++) { + result[v] = std::max(0.0f, std::min(vector[v], 6.0f)); + } +} + +// Apply signbit to elements of a vector +void ApplySignbitToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result) { + for (int v = 0; v < v_size; v++) { + result[v] = std::signbit(vector[v]); + } +} + +void UnpackDenseInt4IntoInt8(const int8_t* src_buffer, int num_elements, + int8_t* dst_buffer) { + for (int i = 0; i < num_elements; i += 2) { + // Shift left first so that sign is properly extended when shifted right + dst_buffer[i] = static_cast(src_buffer[i / 2] << 4) >> 4; + // Break early if the tensor has odd length and the higher nibble should be + // ignored. + if (i + 1 == num_elements) break; + dst_buffer[i + 1] = static_cast(src_buffer[i / 2]) >> 4; + } +} + +} // namespace tensor_utils +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_TENSOR_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h new file mode 100644 index 0000000..5674e2e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h @@ -0,0 +1,623 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_PORTABLE_TENSOR_UTILS_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_PORTABLE_TENSOR_UTILS_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +#if defined(_MSC_VER) +#define __restrict__ __restrict +#endif + +namespace tflite { + +// Not all backends support CpuBackendContext usage, so forward declare to avoid +// pulling in its implementation. Use of CpuBackendContext in method +// implementations is purely optional. +class CpuBackendContext; + +namespace tensor_utils { + +// Multiplies a matrix with a scalar and reduce the result on each row to a +// scalar. +// Parameters: +// - matrix: matrix of size n_row * n_col +// - scalar: the scalar that is multiplied to each element in the matrix +// - n_row: the row count of the matrix +// - n_col: the column count of the matrix +// - output: the 32bit output +// Note: We do not need saturation because the int8 * int8 is safe from overflow +// in (2^31-1) / (2^14) = 131072, which is bigger than the n_row. Non-zero +// initial output value is not exceptionally large. +void MatrixScalarMultiplyAccumulate(const int8_t* matrix, int32_t scalar, + int32_t n_row, int32_t n_col, + int32_t* output); + +// Add another vector for each batch in the batch vector. +template +void VectorBatchVectorAdd(const T* vector, int v_size, int n_batch, + T* batch_vector) { + for (int b = 0; b < n_batch; b++) { + for (int i = 0; i < v_size; ++i) { + batch_vector[i] += vector[i]; + } + batch_vector += v_size; + } +} + +// Cwise product of two vectors. +template +inline void VectorVectorCwiseProduct(const T* vector1, const T* vector2, + int v_size, T* result) { + for (int v = 0; v < v_size; v++) { + *result++ = *vector1++ * *vector2++; + } +} + +// Cwise product of a vector and a batch-vector. +template +inline void VectorBatchVectorCwiseProduct(const T* vector, int v_size, + const T* batch_vector, int n_batch, + T* result) { + for (int b = 0; b < n_batch; b++) { + VectorVectorCwiseProduct(vector, batch_vector, v_size, result); + // Update the pointers. + result += v_size; + batch_vector += v_size; + } +} + +// Cwise product and accumulate of two vectors. Since it's a MAC operation, the +// assumption here is that result array is initialized to valid values. +template +inline void VectorVectorCwiseProductAccumulate(const T* __restrict__ vector1, + const T* __restrict__ vector2, + int v_size, + T* __restrict__ result) { + for (int v = 0; v < v_size; v++) { + *result++ += *vector1++ * *vector2++; + } +} + +// Cwise product and accumulate of a vector and a batch-vector. Since it's a MAC +// operation, the assumption here is that result array is initialized to valid +// values. +template +inline void VectorBatchVectorCwiseProductAccumulate(const T* vector, int v_size, + const T* batch_vector, + int n_batch, T* result) { + for (int b = 0; b < n_batch; b++) { + VectorVectorCwiseProductAccumulate(vector, batch_vector, v_size, result); + // Update the pointers. + result += v_size; + batch_vector += v_size; + } +} + +// Batch vector initialization with another vector. +template +void VectorBatchVectorAssign(const T* vector, int v_size, int n_batch, + T* batch_vector) { + for (int b = 0; b < n_batch; b++) { + std::copy_n(vector, v_size, batch_vector + b * v_size); + } +} + +// Checks if all entries of vector are zero for float. +bool IsZeroVector(const float* vector, int v_size); + +// Checks if all entries of vector are zero for int8. +bool IsZeroVector(const int8_t* vector, int v_size); + +// Quantizes a buffer of floating point values using a symmetric quantization +// (i.e. linear quantization without an offset) to 8-bit signed integers. +// It also outputs the range (min, max) of the floating point buffer, and the +// scaling factor used to quantize the values. +void SymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float* min_value, + float* max_value, float* scaling_factor); + +// Quantizes a buffer of floating point values using a symmetric quantization +// (i.e. linear quantization without an offset) to 8-bit signed integers. +// It uses the range (min, max) provided to the function to calculate the +// appropriate scaling factor to quantize the values. +void SymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float min_value, + float max_value, float* scaling_factor); + +void AsymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float* scaling_factor, + int32_t* offset); + +// Helper function to quantize floats. +// float_data_ptr input float vectors +// n_batch number of input vectors +// n_data size of a single input vector +// quantized_data_ptr (out) vector with quantized data +// scaling_factors (out) scaling factors (one per vector) +// zero_points (out) zero points (one per vector) +// do_asymmetric controls if the quantization should be asymmetric. +inline void BatchQuantizeFloats(const float* float_data_ptr, int n_batch, + int n_data, int8_t* quantized_data_ptr, + float* scaling_factors, int32_t* zero_points, + bool do_asymmetric) { + for (int b = 0; b < n_batch; ++b) { + const int offset = b * n_data; + if (do_asymmetric) { + tensor_utils::AsymmetricQuantizeFloats( + float_data_ptr + offset, n_data, quantized_data_ptr + offset, + &scaling_factors[b], &zero_points[b]); + } else { + float unused_min, unused_max; + tensor_utils::SymmetricQuantizeFloats( + float_data_ptr + offset, n_data, quantized_data_ptr + offset, + &unused_min, &unused_max, &scaling_factors[b]); + } + } +} + +// Multiplies a matrix by a "batched" vector (i.e. a matrix with a batch +// dimension composed by input vectors independent from each other). The result +// of the multiplication is accumulated to the passed result buffer. +// More specifically, for a matrix M of shape [n, i] and a batched-vector +// of shape [i, batch] it will first compute the product of shape [n, batch]. +// This product will be accumulated to the result buffer. +void MatrixBatchVectorMultiplyAccumulate(const float* matrix, int m_rows, + int m_cols, const float* vector, + int n_batch, float* result); + +// Same as the function above, but the matrix is a sparse tensor with block +// pattern 1x4. +// This function assumes that m_cols is a multiple of the block size (4 in this +// case) so that there's no incomplete block. +void SparseMatrixBatchVectorMultiplyAccumulate1x4( + const float* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const float* __restrict__ vector, int n_batch, float* __restrict__ result); + +// Same as the function above, but the matrix is stored in block compressed +// sparse row format with block pattern 1x16 which consists of two arrays: +// 1. A matrix array stores non-zero blocks of the matrix in row major. +// 2. A ledger array stores nrows groups, one group per row. Each group starts +// with an integer representing the number of non-zero blocks for the +// corresponding row and follows with column indexes of the first element +// of each non-zero block. +// This function assumes that +// 1. m_cols is a multiple of 16 so that all blocks are full blocks. +// 2. m_cols < 254 * 16 so that block index can be represented by uint8. +void SparseMatrixBatchVectorMultiplyAccumulate( + const float* __restrict__ matrix, const uint8_t* __restrict__ ledger, + int m_rows, int m_cols, const float* __restrict__ vector, int n_batch, + float* __restrict__ result); + +// Same as the function above, but for values quantized using symmetric +// quantization (e.g. by calling SymmetricQuantizeFloats). +// The passed scaling factors is a buffer of the quantization scaling factors +// that will be used to dequentize the products into the final result buffer. +// These scaling factors are the multiplication of the matrix scaling factor +// by the vector's scaling factor, one per batch (i.e. this allows quantizing +// each batch in the batch-vector matrix independently). +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, + const float* __restrict__ scaling_factors, int n_batch, + float* __restrict__ result); + +// Same as the function above except that vector values +// are quantized with asymmetric quantization per-batch and the matrix +// is quantized per row. +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, + const float* __restrict__ scaling_factors, int n_batch, + float* __restrict__ result, const float* __restrict__ per_channel_scale, + const int32_t* __restrict__ input_offset); + +// Same as the function above, but the matrix is a sparse tensor with block +// pattern 1x16. +// This function assumes that m_cols is a multiple of the block size (16 in this +// case) so that there's no incomplete block. Also, it assumes all offsets of +// input, output and filter are zero. +void SparseMatrixBatchVectorMultiplyAccumulate1x16( + const int8_t* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const int8_t* __restrict__ vector, const int32_t* __restrict__ bias_vector, + int n_batch, const int32_t input_offset, const int32_t output_multiplier, + const int32_t output_shift, const int32_t output_offset, + const int32_t output_activation_min, const int32_t output_activation_max, + int8_t* __restrict__ result); + +// Same as the function above, but the matrix is stored in block compressed +// sparse row format with block pattern 1x16 which consists of two arrays: +// 1. A matrix array stores non-zero blocks of the matrix in row major. +// 2. A ledger array stores nrows groups, one group per row. Each group starts +// with an integer representing the number of non-zero blocks for the +// corresponding row followed by column index of the first element of +// each non-zero block. +// This function assumes that +// 1. m_cols is a multiple of 16 so that all blocks are full blocks. +// 2. m_cols < 254 * 16 so that block index can be represented by uint8. +void SparseMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const uint8_t* __restrict__ ledger, + const int m_rows, const int m_cols, const int8_t* __restrict__ vectors, + const float* __restrict__ scaling_factors, int n_batch, + float* __restrict__ result); + +// Same as the above 8, 8, 8 integer matmul except for the presence of zero +// point and non-accumulative. +// TODO(b/148688698): remove this function by folding zero point calculation in +// prepare() function. +void MatrixBatchVectorMultiply(const int8_t* input, int32_t input_zeropoint, + const int8_t* input_to_gate_weights, + int32_t input_to_gate_effective_scale_a, + int32_t input_to_gate_effective_scale_b, + int32_t n_batch, int32_t n_input, int32_t n_cell, + int8_t* gate_output, int8_t gate_output_zp); + +// Same as above but has 16 bit and 8 bit input and 8 bit output. +// Used in projection when hidden is 16bit. +void MatrixBatchVectorMultiply(const int16_t* hidden, + const int8_t* hidden_to_output_weights, + int32_t proj_effective_scale_a, + int32_t proj_effective_scale_b, + const int32_t* gate_bias, int32_t n_batch, + int32_t n_hidden, int32_t n_output, + int32_t output_zp, int8_t* proj_output); + +// Apply Layer Normalization (https://arxiv.org/abs/1607.06450) to a Quantized +// vector. +// Parameters: +// - input: batch vector of size n_batch * n_input; 16 bit. +// - layer_norm_weights: the quantized layer normalization weights. +// - bias: the bias for the layer normalization. +// - layer_norm_scale_a: multiplier for scale factor. +// - layer_norm_scale_b: shift for scale factor. +// - variance_limit: the guard to make sure the inverse does not overflow. +// - n_batch: the number of batches. +// - n_input: the size for input and output. +// - output: the 16 bit output +void ApplyLayerNorm(const int16_t* input, const int16_t* layer_norm_weights, + const int32_t* bias, int32_t layer_norm_scale_a, + int32_t layer_norm_scale_b, int32_t variance_limit, + int n_batch, int n_input, int16_t* output); + +// Same as above but the internal calculation is done in float. +void ApplyLayerNormFloat(const int16_t* input, + const int16_t* layer_norm_weights, + int32_t layer_norm_scale_a, int32_t layer_norm_scale_b, + const int32_t* bias, int n_batch, int n_input, + int16_t* output); + +// Apply Sigmoid to a quantized vector. +// Parameters: +// - input: batch vector of size n_batch * n_input; 16 bit. +// - n_batch: the number of batches. +// - n_input: the size for input and output. +// - output: the 16 bit output +// The input is in Q3.12 format and the output is in Q0.15 format. +void ApplySigmoid(const int16_t* input, int32_t n_batch, int32_t n_input, + int16_t* output); + +// Same as above but the internal calcualtion is float. +void ApplySigmoidFloat(const int16_t* input, int32_t n_batch, int32_t n_input, + int16_t* output); + +// Apply Tanh to a quantized vector. +// Parameters: +// - integer_bits: the integer bits of the input. +// Currently supports 0, 1, 2, 3, 4, 5, 6. +// - input: batch vector of size n_batch * n_input; 16 bit. +// - n_batch: the number of batches. +// - n_input: the size for input and output. +// - output: the 16 bit output +// The input is in Qm.15-m format and the output is in Q0.15 format. +void ApplyTanh(int32_t intger_bits, const int16_t* input, int32_t n_batch, + int32_t n_input, int16_t* output); + +// Apply Tanh to a quantized vector. Tbe internal calculation is in float. +// - Input has 2^(integer_bits) as scale. +// - Output has Q0.15 as scale. +void ApplyTanhFloat(const int16_t* input, int32_t n_batch, int32_t n_input, + int32_t integer_bits, int16_t* output); + +// Element-wise multiplication of two quantized vectors. +// Parameters: +// - input_1: batch vector of size n_batch * n_input; 16 bit. +// - input_2: batch vector of size n_batch * n_input; 16 bit. +// - n_batch: the number of batches. +// - n_input: the size for input and output. +// - shift: the shift needed to produce the output. +// - output: the 16 bit output of size n_batch * n_input. +// Output does not need to be initialized. +void CwiseMul(const int16_t* input_1, const int16_t* input_2, int n_batch, + int n_input, int shift, int16_t* output); + +// Element-wise multiplication of two quantized vectors. +// Parameters: +// - input_1: batch vector of size n_batch * n_input; 16 bit. +// - input_2: batch vector of size n_batch * n_input; 16 bit. +// - n_batch: the number of batches. +// - n_input: the size for input and output. +// - shift: the shift needed to produce the output. +// - output: the 8 bit output of size n_batch * n_input. +// Output does not need to be initialized. +void CwiseMul(const int16_t* input_1, const int16_t* input_2, int n_batch, + int n_input, int shift, int8_t* output); + +// Element-wise multiplication of two quantized vectors with rescaling. +// Parameters: +// - input_1: batch vector of size n_batch * n_input; 16 bit. +// - input_2: batch vector of size n_batch * n_input; 16 bit. +// - multiplier: the multiplier part of scale. +// - shift: the shift part of scale. +// - n_batch: the number of batches. +// - n_input: the size for input and output. +// - output: the 8 bit output of size n_batch * n_input. +// - output_zp: the zero point of output. +// Output does not need to be initialized. +// Multiplier ("m") and shift ("s") are connected to scale ("s") with s = m * +// 2^(s - 31). +void CwiseMul(const int16_t* input_1, const int16_t* input_2, + int32_t multiplier, int32_t shift, int32_t n_batch, + int32_t n_input, int32_t output_zp, int8_t* output); + +// Element-wise saturating addition of two quantized vectors without rescaling. +// Parameters: +// - input_1: batch vector of size n_batch * n_input; 16 bit. +// - input_2: batch vector of size n_batch * n_input; 16 bit. +// - n_batch: the number of batches. +// - n_input: the size for input and output. +// - output: the 8 bit output of size n_batch * n_input. +// Output does not need to be initialized. +void CwiseAdd(const int16_t* input_1, const int16_t* input_2, int n_batch, + int n_input, int16_t* output); + +// Element-wise in-place clipping of a vector. Overloaded for float, int16_t, +// int8_t. Parameters: +// - vector: vector of size v_size. +// - v_size: the size of the vector. +// - clipping_value: the value used for clipping. +void CwiseClipping(float* vector, const int v_size, const float clipping_value); +void CwiseClipping(int16_t* vector, const int v_size, + const int16_t clipping_value); +void CwiseClipping(int8_t* vector, const int v_size, + const int8_t clipping_value); + +// Dot product of two vectors. +float VectorVectorDotProduct(const float* vector1, const float* vector2, + int v_size); + +// Dot product of two batch vectors of size n_batch * v_size: +// vector1 = [x_1_1, x_1_2, ..., x_1_vsize, +// x_2_1, x_2_2, ..., x_2_vsize, +// ... +// x_nbatch_1,..., x_nbatch_vsize] +// vector2 = [y_1_1, y_1_2, ..., y_1_vsize, +// y_2_1, y_2_2, ..., y_2_vsize, +// ... +// y_nbatch_1,..., y_nbatch_vsize] +// Then result will be a vector of n_batch size starting from 'result': +// [x_1_1 * y_1_1 + x_1_2 * y_1_2 + ... + x_1_vsize * y_1_vsize, +// x_2_1 * y_2_1 + x_2_2 * y_2_2 + ... + x_2_vsize * y_2_vsize, +// ... +// x_nbatch_1 * y_nbatch_1 + ... + x_nbatch_vsize * y_nbatch_vsize] +template +inline void BatchVectorBatchVectorDotProduct(const T* vector1, const T* vector2, + int v_size, int n_batch, + T* result) { + for (int b = 0; b < n_batch; b++) { + result[b] = VectorVectorDotProduct(vector1, vector2, v_size); + vector1 += v_size; + vector2 += v_size; + } +} + +// Same as above but input is 16bit and output is 32bit. +void BatchVectorBatchVectorDotProduct(const int16_t* vector1, + const int16_t* vector2, int v_size, + int n_batch, int32_t* result); + +// Same as above, but inputs are 16bit integer and output is 16bit integer. +void VectorBatchVectorCwiseProductAccumulate(const int16_t* vector, int v_size, + const int16_t* batch_vector, + int n_batch, int32_t multiplier, + int shift, int16_t* result); + +// Compute "1.0f - elements of vector" (used in CIFG). +void Sub1Vector(const float* vector, int v_size, float* result); + +// Compute "1.0f - elements of vector" (used in CIFG) for int16 input. +// "vector" has range [0, 32767] because it is the output of sigmoid function. +void Sub1Vector(const int16_t* vector, int v_size, int16_t* result); + +// Reduce-sum on a float input vector: +// input_vector: float pointer to input vector. +// output_vector: float pointer to vector. +// output_size: output vector size. +// reduction_size: number of consecutive elements from input vector which are +// added to get one element of output. +void ReductionSumVector(const float* input_vector, float* output_vector, + int output_size, int reduction_size); + +// Same as above but input/output is 32 bit integer. +void ReductionSumVector(const int32_t* input_vector, int32_t* output_vector, + int output_size, int reduction_size); + +// Same as above but input is 8 bit integer. +void ReductionSumVector(const int8_t* input_vector, int32_t* output_vector, + int output_size, int reduction_size); + +// Multiply all elements of vector with a scalar. +void VectorScalarMultiply(const int8_t* vector, int v_size, float scale, + float* result); + +// Layer norm for each batch. +void MeanStddevNormalization(const float* input_vector, float* output_vector, + int v_size, int n_batch); + +// Saturate Add with rescale on both inputs. +void TwoGateSaturatingAdd(const int8_t* input, int8_t input_zp, + const int8_t* recurrent, int8_t recurrent_zp, + int32_t input_effective_scale_a, + int32_t input_effective_scale_b, + int32_t recurrent_effective_scale_a, + int32_t recurrent_effective_scale_b, int32_t n_batch, + int32_t n_cell, int16_t* output); + +// Same as the function above, but provide a scratch buffer for the +// int8 x int8 -> int32 and a CpuBackendContext for the accumulator +// computation. +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, + const float* __restrict__ scaling_factors, int n_batch, + int32_t* __restrict__ scratch, float* __restrict__ result, + CpuBackendContext* __restrict__ context); + +// Same as the function above except that can make use of cached row sums. +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, const float* scaling_factors, + int n_batch, float* __restrict__ result, const float* per_channel_scale, + const int32_t* input_offset, int32_t* scratch, int32_t* row_sums, + bool* compute_row_sums, CpuBackendContext* context); + +// Same as the function above, but provides separate scaling factor for the +// matrix and the vectors. The scaling factors are multiplied in the +// scaling_factor_scratch buffer. +inline void MatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, const float matrix_scaling_factor, + const float* vector_scaling_factors, int n_batch, + float* __restrict__ result, const float* per_channel_scale, + const int32_t* input_offset, int32_t* scratch, int32_t* row_sums, + bool* compute_row_sums, float* scaling_factor_scratch, + CpuBackendContext* context) { + for (int b = 0; b < n_batch; ++b) { + scaling_factor_scratch[b] = + vector_scaling_factors[b] * matrix_scaling_factor; + } + MatrixBatchVectorMultiplyAccumulate(matrix, m_rows, m_cols, vectors, + scaling_factor_scratch, n_batch, result, + per_channel_scale, input_offset, scratch, + row_sums, compute_row_sums, context); +} + +// Multiplies a matrix by a "batched" vector (i.e. a matrix with a batch +// dimension composed by input vectors independent from each other). The result +// of the multiplication is accumulated to the passed result buffer. +// More specifically, for a matrix M of shape [n, i] and a batched-vector +// of shape [i, batch] it will first compute the product of shape [n, batch]. +// This product will be accumulated to the result buffer, +// Parameters: +// - input: batch vector of size n_batch * n_input +// - bias: vector of size b_input +// - input_to_gate_weights: matrix of size n_input * n_output +// - multiplier: scalar +// - shift: scalar +// - n_batch: the batch size +// - n_input: the input size +// - n_output: the output size +// - output_zp: the zero point of the output. +// - scratch: batch vector of size n_batch * n_output +// - output: the 16 bit output +// Notes: +// - this is used for gate matmul: for non-cifg it is for input, forget, +// cell, output gates; for cifg, it is for forget, cell, output gates. +// - multiplier and shift combined gives the scale. +// - assumes input zero point is 0. +// - scratch is created for optimization purpose only. +// TODO(b/152066492): this can be removed if some future optimization +// work makes it unnecessary. +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int16_t* output, CpuBackendContext* context); + +// Multiplies a matrix by a "batched" vector (i.e. a matrix with a batch +// dimension composed by input vectors independent from each other). The result +// of the multiplication is accumulated to the passed result buffer. +// More specifically, for a matrix M of shape [n, i] and a batched-vector +// of shape [i, batch] it will first compute the product of shape [n, batch]. +// This product will be accumulated to the result buffer, +// Parameters: +// - input: batch vector of size n_batch * n_input +// - bias: vector of size b_input +// - input_to_gate_weights: matrix of size n_input * n_output +// - multiplier: scalar +// - shift: scalar +// - n_batch: the batch size +// - n_input: the input size +// - n_output: the output size +// - output_zp: the zero point of the output. +// - scratch: batch vector of size n_batch * n_output +// - output: the 8 bit output +// Notes: +// - this is used for projection matmul. +// - multiplier and shift combined gives the scale. +// - assumes input zero point is 0. +// - scratch is created for optimization purpose only. +// TODO(b/152066492): this can be removed if some future optimization +// work makes it unnecessary. +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int8_t* output, CpuBackendContext* context); + +// Apply Rectified Linear to elements of a vector. +void ApplyReluToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result); + +// Apply Rectified Linear 1 (cap to [-1;1]) to elements of a vector +void ApplyRelu1ToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result); + +// Apply Rectified Linear 6 (cap to [0;6]) to elements of a vector +void ApplyRelu6ToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result); + +// Apply signbit to elements of a vector +void ApplySignbitToVector(const float* __restrict__ vector, int v_size, + float* __restrict__ result); + +// Unpack or inflate `src_buffer` by taking each element and splitting it as +// two elements into `dst_buffer`. +// Parameters: +// src_buffer : Densely packed buffer containing int4 values +// num_elements : Number of elements stored in the buffer. Note that this can +// be smaller than the size of `src_buffer` by 1 if it's odd, +// in which case the last nibble in `src_buffer` is ignored. +// This should be equal to the size of `dst_buffer`. +// dst_buffer : Buffer to unpack into. Should be allocated by the caller. +// Size should be at least `num_elements`. +// Notes: +// For example, given `src_buffer = {0x12, 0x34};`, calling this function +// will return `dst_buffer = {0x02, 0x01, 0x04, 0x03}`. +void UnpackDenseInt4IntoInt8(const int8_t* src_buffer, int num_elements, + int8_t* dst_buffer); + +} // namespace tensor_utils + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_PORTABLE_TENSOR_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.cpp new file mode 100644 index 0000000..efd57db --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.cpp @@ -0,0 +1,416 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" + +namespace tflite { + +namespace { +// These constants are used to manipulate the binary representation of doubles. +// Double-precision binary64 floating point format is: +// Bit | 63 | 62-52 | 51-0 | +// | Sign | Exponent | Fraction | +// To avoid 64-bit integers as much as possible, I break this into high and +// low 32-bit chunks. High is: +// Bit | 31 | 30-20 | 19-0 | +// | Sign | Exponent | High Fraction | +// Low is: +// Bit | 31-0 | +// | Low Fraction | +// We then access the components through logical bit-wise operations to +// extract the parts needed, with the positions and masks derived from the +// layout shown above. +constexpr uint64_t kSignMask = 0x8000000000000000LL; +constexpr uint64_t kExponentMask = 0x7ff0000000000000LL; +constexpr int32_t kExponentShift = 52; +constexpr int32_t kExponentBias = 1023; +constexpr uint32_t kExponentIsBadNum = 0x7ff; +constexpr uint64_t kFractionMask = 0x000fffffffc00000LL; +constexpr uint32_t kFractionShift = 22; +constexpr uint32_t kFractionRoundingMask = 0x003fffff; +constexpr uint32_t kFractionRoundingThreshold = 0x00200000; +} // namespace + +void QuantizeMultiplier(double double_multiplier, int32_t* quantized_multiplier, + int* shift) { +#if TFLITE_SINGLE_ROUNDING + // Single-rounding MultiplyByQuantizedMultiplier only supports positive + // multipliers. + // TFLITE_DCHECK(double_multiplier >= 0); +#endif + if (double_multiplier == 0.) { + *quantized_multiplier = 0; + *shift = 0; + return; + } +#ifdef TFLITE_EMULATE_FLOAT + // If we're trying to avoid the use of floating-point instructions (for + // example on microcontrollers) then use an alternative implementation + // that only requires integer and bitwise operations. To enable this, you + // need to set the define during the build process for your platform. + int64_t q_fixed = IntegerFrExp(double_multiplier, shift); +#else // TFLITE_EMULATE_FLOAT + const double q = std::frexp(double_multiplier, shift); + auto q_fixed = static_cast(TfLiteRound(q * (1LL << 31))); +#endif // TFLITE_EMULATE_FLOAT + TFLITE_CHECK(q_fixed <= (1LL << 31)); + if (q_fixed == (1LL << 31)) { + q_fixed /= 2; + ++*shift; + } + TFLITE_CHECK_LE(q_fixed, std::numeric_limits::max()); + // A shift amount smaller than -31 would cause all bits to be shifted out + // and thus all results would be zero. We implement that instead with + // q_fixed==0, so as to avoid hitting issues with right-shift + // operations with shift amounts greater than 31. Note that this happens + // roughly when abs(double_multiplier) < 2^-31 and the present handling means + // that we're effectively flushing tiny double_multiplier's to zero. + // We could conceivably handle values in the range (roughly) [32, 63] + // as 'denormals' i.e. (shift==0, q_fixed < 2^30). In that point of view + // the present handling is just doing 'flush denormals to zero'. We could + // reconsider and actually generate nonzero denormals if a need arises. + if (*shift < -31) { + *shift = 0; + q_fixed = 0; + } +#if TFLITE_SINGLE_ROUNDING + // Single-rounding MultiplyByQuantizedMultiplier doesn't support a shift > 30, + // saturate it. + if (*shift > 30) { + *shift = 30; + q_fixed = (1LL << 31) - 1; + } +#endif + *quantized_multiplier = static_cast(q_fixed); +} + +void QuantizeMultiplierGreaterThanOne(double double_multiplier, + int32_t* quantized_multiplier, + int* left_shift) { + TFLITE_CHECK_GT(double_multiplier, 1.); + QuantizeMultiplier(double_multiplier, quantized_multiplier, left_shift); + TFLITE_CHECK_GE(*left_shift, 0); +} + +void QuantizeMultiplierSmallerThanOneExp(double double_multiplier, + int32_t* quantized_multiplier, + int* left_shift) { + TFLITE_CHECK_LT(double_multiplier, 1.); + TFLITE_CHECK_GT(double_multiplier, 0.); + int shift; + QuantizeMultiplier(double_multiplier, quantized_multiplier, &shift); + TFLITE_CHECK_LE(shift, 0); + *left_shift = shift; +} + +int64_t IntegerFrExp(double input, int* shift) { + // Make sure our assumptions about the double layout hold. + TFLITE_CHECK_EQ(8, sizeof(double)); + + // We want to access the bits of the input double value directly, which is + // tricky to do safely, so use a union to handle the casting. + union { + double double_value; + uint64_t double_as_uint; + } cast_union; + cast_union.double_value = input; + const uint64_t u = cast_union.double_as_uint; + + // If the bitfield is all zeros apart from the sign bit, this is a normalized + // zero value, so return standard values for this special case. + if ((u & ~kSignMask) == 0) { + *shift = 0; + return 0; + } + + // Deal with NaNs and Infs, which are always indicated with a fixed pattern in + // the exponent, and distinguished by whether the fractions are zero or + // non-zero. + const uint32_t exponent_part = ((u & kExponentMask) >> kExponentShift); + if (exponent_part == kExponentIsBadNum) { + *shift = std::numeric_limits::max(); + if (u & kFractionMask) { + // NaN, so just return zero (with the exponent set to INT_MAX). + return 0; + } else { + // Infinity, so return +/- INT_MAX. + if (u & kSignMask) { + return std::numeric_limits::min(); + } else { + return std::numeric_limits::max(); + } + } + } + + // The shift is fairly easy to extract from the high bits of the double value, + // just by masking it out and applying a bias. The std::frexp() implementation + // always returns values between 0.5 and 1.0 though, whereas the exponent + // assumes 1.0 to 2.0 is the standard range, so I add on one to match that + // interface. + *shift = (exponent_part - kExponentBias) + 1; + + // There's an implicit high bit in the double format definition, so make sure + // we include that at the top, and then reconstruct the rest of the fractional + // value from the remaining fragments. + int64_t fraction = 0x40000000 + ((u & kFractionMask) >> kFractionShift); + + // We're cutting off some bits at the bottom, so to exactly match the standard + // frexp implementation here we'll apply rounding by adding one to the least + // significant bit of the result if the discarded portion is over half of the + // maximum. + if ((u & kFractionRoundingMask) > kFractionRoundingThreshold) { + fraction += 1; + } + // Negate the fraction if the sign bit was set. + if (u & kSignMask) { + fraction *= -1; + } + + return fraction; +} + +double DoubleFromFractionAndShift(int64_t fraction, int shift) { + union { + double double_value; + uint64_t double_as_uint; + } result; + + // Detect NaNs and infinities. + if (shift == std::numeric_limits::max()) { + if (fraction == 0) { + return std::numeric_limits::quiet_NaN(); + } else if (fraction > 0) { + return std::numeric_limits::infinity(); + } else { + return -std::numeric_limits::infinity(); + } + } + + // Return a normalized zero for a zero fraction. + if (fraction == 0) { + result.double_as_uint = 0; + return result.double_value; + } + + bool is_negative = (fraction < 0); + int64_t encoded_fraction = is_negative ? -fraction : fraction; + int64_t encoded_shift = (shift - 1); + while (encoded_fraction < 0x40000000) { + encoded_fraction *= 2; + encoded_shift -= 1; + } + while (encoded_fraction > 0x80000000) { + encoded_fraction /= 2; + encoded_shift += 1; + } + encoded_fraction -= 0x40000000; + if (encoded_shift < -1022) { + encoded_shift = -1023; + } else if (encoded_shift > 1022) { + encoded_shift = 1023; + } + encoded_shift += kExponentBias; + uint64_t encoded_sign = is_negative ? kSignMask : 0; + result.double_as_uint = encoded_sign | (encoded_shift << kExponentShift) | + (encoded_fraction << kFractionShift); + return result.double_value; +} + +double IntegerDoubleMultiply(double a, double b) { + int a_shift; + const int64_t a_fraction = IntegerFrExp(a, &a_shift); + int b_shift; + const int64_t b_fraction = IntegerFrExp(b, &b_shift); + // Detect NaNs and infinities. + if (a_shift == std::numeric_limits::max() || + (b_shift == std::numeric_limits::max())) { + return std::numeric_limits::quiet_NaN(); + } + const int result_shift = a_shift + b_shift + 1; + const int64_t result_fraction = (a_fraction * b_fraction) >> 32; + return DoubleFromFractionAndShift(result_fraction, result_shift); +} + +int IntegerDoubleCompare(double a, double b) { + int a_shift; + const int64_t a_fraction = IntegerFrExp(a, &a_shift); + int b_shift; + const int64_t b_fraction = IntegerFrExp(b, &b_shift); + + // Detect NaNs and infinities. + if (a_shift == std::numeric_limits::max() || + (b_shift == std::numeric_limits::max())) { + return 1; + } + + if ((a_fraction == 0) && (b_fraction < 0)) { + return 1; + } else if ((a_fraction < 0) && (b_fraction == 0)) { + return -1; + } else if (a_shift < b_shift) { + return -1; + } else if (a_shift > b_shift) { + return 1; + } else if (a_fraction < b_fraction) { + return -1; + } else if (a_fraction > b_fraction) { + return 1; + } else { + return 0; + } +} + +void PreprocessSoftmaxScaling(double beta, double input_scale, + int input_integer_bits, + int32_t* quantized_multiplier, int* left_shift) { + // If the overall multiplier (input and beta) is large, then exp() of an + // input difference of 1 scaled by this will be large. In other words, we + // can cap the multiplier and know that, when it is used, the output will be + // (round to) zero wherever the input is not at the maximum value. + + // If the overall scale is less than one, and input_integer_bits=0, then the + // result is double equivalent of Q0.31 (actually with more precision). Thus + // this generates a Q(input_integer_bits).(31-input_integer_bits) + // representation. +#if TFLITE_SINGLE_ROUNDING + const double max_real_multiplier = (1LL << 30) - 1.0; +#else + const double max_real_multiplier = (1LL << 31) - 1.0; +#endif + +#ifdef TFLITE_EMULATE_FLOAT + const double input_beta = IntegerDoubleMultiply(beta, input_scale); + int shift; + int64_t fraction = IntegerFrExp(input_beta, &shift); + shift += (31 - input_integer_bits); + double input_beta_real_multiplier = + DoubleFromFractionAndShift(fraction, shift); + if (IntegerDoubleCompare(input_beta_real_multiplier, max_real_multiplier) > + 0) { + input_beta_real_multiplier = max_real_multiplier; + } +#else // TFLITE_EMULATE_FLOAT + const double input_beta_real_multiplier = + std::min(beta * input_scale * (1 << (31 - input_integer_bits)), + max_real_multiplier); +#endif // TFLITE_EMULATE_FLOAT + + QuantizeMultiplierGreaterThanOne(input_beta_real_multiplier, + quantized_multiplier, left_shift); +} + +void PreprocessLogSoftmaxScalingExp(double beta, double input_scale, + int input_integer_bits, + int32_t* quantized_multiplier, + int* left_shift, + int32_t* reverse_scaling_divisor, + int* reverse_scaling_left_shift) { + PreprocessSoftmaxScaling(beta, input_scale, input_integer_bits, + quantized_multiplier, left_shift); + + // Also calculate what amounts to the inverse scaling factor for the input. + const double real_reverse_scaling_divisor = + (1 << (31 - *left_shift)) / static_cast(*quantized_multiplier); + tflite::QuantizeMultiplierSmallerThanOneExp(real_reverse_scaling_divisor, + reverse_scaling_divisor, + reverse_scaling_left_shift); +} + +int CalculateInputRadius(int input_integer_bits, int input_left_shift, + int total_signed_bits) { +#ifdef TFLITE_EMULATE_FLOAT + int64_t result = (1 << input_integer_bits) - 1; + result <<= (total_signed_bits - input_integer_bits); + result >>= input_left_shift; + return result; +#else // TFLITE_EMULATE_FLOAT + const double max_input_rescaled = + 1.0 * ((1 << input_integer_bits) - 1) * + (1LL << (total_signed_bits - input_integer_bits)) / + (1LL << input_left_shift); + // Tighten bound using floor. Suppose that we could use the exact value. + // After scaling the difference, the result would be at the maximum. Thus we + // must ensure that our value has lower magnitude. + return static_cast(std::floor(max_input_rescaled)); +#endif // TFLITE_EMULATE_FLOAT +} + +void NudgeQuantizationRange(const float min, const float max, + const int quant_min, const int quant_max, + float* nudged_min, float* nudged_max, + float* nudged_scale) { + // This code originates from tensorflow/core/kernels/fake_quant_ops_functor.h. + const float quant_min_float = static_cast(quant_min); + const float quant_max_float = static_cast(quant_max); + *nudged_scale = (max - min) / (quant_max_float - quant_min_float); + const float zero_point_from_min = quant_min_float - min / *nudged_scale; + uint16_t nudged_zero_point; + if (zero_point_from_min < quant_min_float) { + nudged_zero_point = static_cast(quant_min); + } else if (zero_point_from_min > quant_max_float) { + nudged_zero_point = static_cast(quant_max); + } else { + nudged_zero_point = static_cast(TfLiteRound(zero_point_from_min)); + } + *nudged_min = (quant_min_float - nudged_zero_point) * (*nudged_scale); + *nudged_max = (quant_max_float - nudged_zero_point) * (*nudged_scale); +} + +void FakeQuantizeArray(const float nudged_scale, const float nudged_min, + const float nudged_max, const float* input_data, + float* output_data, const float size) { + // This code originates from tensorflow/core/kernels/fake_quant_ops_functor.h. + const float inv_nudged_scale = 1.0f / nudged_scale; + + for (int i = 0; i < size; i++) { + const float src_val = input_data[i]; + const float clamped = std::min(nudged_max, std::max(nudged_min, src_val)); + const float clamped_shifted = clamped - nudged_min; + const float dst_val = + TfLiteRound(clamped_shifted * inv_nudged_scale) * nudged_scale + + nudged_min; + output_data[i] = dst_val; + } +} + +bool CheckedLog2(const float x, int* log2_result) { + // Using TfLiteRound instead of std::round and std::log instead of + // std::log2 to work around these functions being missing in a toolchain + // used in some TensorFlow tests as of May 2018. + const float x_log2 = std::log(x) * (1.0f / std::log(2.0f)); + const float x_log2_rounded = TfLiteRound(x_log2); + const float x_log2_fracpart = x_log2 - x_log2_rounded; + + *log2_result = static_cast(x_log2_rounded); + return std::abs(x_log2_fracpart) < 1e-3f; +} + +void QuantizeMultiplierArray(const double* effective_scales, size_t size, + int32_t* effective_scale_significand, + int* effective_shift) { + for (size_t i = 0; i < size; ++i) { + QuantizeMultiplier(effective_scales[i], &effective_scale_significand[i], + &effective_shift[i]); + } +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h new file mode 100644 index 0000000..9571d1f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h @@ -0,0 +1,292 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_QUANTIZATION_UTIL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_QUANTIZATION_UTIL_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +// Given the min and max values of a float array, return +// reasonable quantization parameters to use for this array. +template +QuantizationParams ChooseQuantizationParams(double rmin, double rmax, + bool narrow_range) { + const T qmin = std::numeric_limits::min() + (narrow_range ? 1 : 0); + const T qmax = std::numeric_limits::max(); + const double qmin_double = qmin; + const double qmax_double = qmax; + // 0 should always be a representable value. Let's assume that the initial + // min,max range contains 0. + TFLITE_CHECK_LE(rmin, 0.); + TFLITE_CHECK_GE(rmax, 0.); + if (rmin == rmax) { + // Special case where the min,max range is a point. Should be {0}. + TFLITE_CHECK_EQ(rmin, 0.); + TFLITE_CHECK_EQ(rmax, 0.); + QuantizationParams quantization_params; + quantization_params.zero_point = 0; + quantization_params.scale = 0.; + return quantization_params; + } + + // General case. + // + // First determine the scale. + const double scale = (rmax - rmin) / (qmax_double - qmin_double); + + // Zero-point computation. + // First the initial floating-point computation. The zero-point can be + // determined from solving an affine equation for any known pair + // (real value, corresponding quantized value). + // We know two such pairs: (rmin, qmin) and (rmax, qmax). + // The arithmetic error on the zero point computed from either pair + // will be roughly machine_epsilon * (sum of absolute values of terms) + // so we want to use the variant that adds the smaller terms. + const double zero_point_from_min = qmin_double - rmin / scale; + const double zero_point_from_max = qmax_double - rmax / scale; + const double zero_point_from_min_error = + std::abs(qmin_double) + std::abs(rmin / scale); + const double zero_point_from_max_error = + std::abs(qmax_double) + std::abs(rmax / scale); + + const double zero_point_double = + zero_point_from_min_error < zero_point_from_max_error + ? zero_point_from_min + : zero_point_from_max; + + // Now we need to nudge the zero point to be an integer + // (our zero points are integer, and this is motivated by the requirement + // to be able to represent the real value "0" exactly as a quantized value, + // which is required in multiple places, for example in Im2col with SAME + // padding). + T nudged_zero_point = 0; + if (zero_point_double < qmin_double) { + nudged_zero_point = qmin; + } else if (zero_point_double > qmax_double) { + nudged_zero_point = qmax; + } else { + nudged_zero_point = static_cast(round(zero_point_double)); + } + // The zero point should always be in the range of quantized value, + // [qmin, qmax]. + TFLITE_CHECK_GE(nudged_zero_point, qmin); + TFLITE_CHECK_LE(nudged_zero_point, qmax); + + // Finally, store the result nudged quantization params. + QuantizationParams quantization_params; + quantization_params.zero_point = nudged_zero_point; + quantization_params.scale = scale; + return quantization_params; +} + +template +QuantizationParams ChooseQuantizationParams(double rmin, double rmax) { + return ChooseQuantizationParams(rmin, rmax, false); +} + +// Converts a floating-point number to an integer. For all inputs x where +// static_cast(x) is legal according to the C++ standard, the result +// is identical to that cast (i.e. the result is x with its fractional part +// truncated whenever that is representable as IntOut). +// +// static_cast would cause undefined behavior for the following cases, which +// have well-defined behavior for this function: +// +// 1. If x is NaN, the result is zero. +// +// 2. If the truncated form of x is above the representable range of IntOut, +// the result is std::numeric_limits::max(). +// +// 3. If the truncated form of x is below the representable range of IntOut, +// the result is std::numeric_limits::min(). +// +// Note that cases #2 and #3 cover infinities as well as finite numbers. +// +// The range of FloatIn must include the range of IntOut, otherwise +// the results are undefined. +// TODO(sfeuz): Replace by absl::SafeCast once available. +template +IntOut SafeCast(FloatIn x) { + static_assert(!std::numeric_limits::is_integer, + "FloatIn is integer"); + static_assert(std::numeric_limits::is_integer, + "IntOut is not integer"); + static_assert(std::numeric_limits::radix == 2, "IntOut is base 2"); + + // Special case NaN, for which the logic below doesn't work. + if (std::isnan(x)) { + return 0; + } + + // Negative values all clip to zero for unsigned results. + if (!std::numeric_limits::is_signed && x < 0) { + return 0; + } + + // Handle infinities. + if (std::isinf(x)) { + return x < 0 ? std::numeric_limits::min() + : std::numeric_limits::max(); + } + + // Set exp such that x == f * 2^exp for some f with |f| in [0.5, 1.0), + // unless x is zero in which case exp == 0. Note that this implies that the + // magnitude of x is strictly less than 2^exp. + int exp = 0; + std::frexp(x, &exp); + + // Let N be the number of non-sign bits in the representation of IntOut. If + // the magnitude of x is strictly less than 2^N, the truncated version of x + // is representable as IntOut. The only representable integer for which this + // is not the case is kMin for signed types (i.e. -2^N), but that is covered + // by the fall-through below. + if (exp <= std::numeric_limits::digits) { + return x; + } + + // Handle numbers with magnitude >= 2^N. + return x < 0 ? std::numeric_limits::min() + : std::numeric_limits::max(); +} + +// Decompose a double multiplier into a Q0.31 int32 representation of its +// significand, and shift representation of NEGATIVE its exponent --- +// this is intended as a RIGHT-shift. +// +// Restricted to the case where the multiplier < 1 (and non-negative). +void QuantizeMultiplierSmallerThanOneExp(double double_multiplier, + int32_t* quantized_multiplier, + int* left_shift); + +// Decompose a double multiplier into a Q0.31 int32 representation of its +// significand, and shift representation of its exponent. +// +// Restricted to the case where the multiplier > 1. +void QuantizeMultiplierGreaterThanOne(double double_multiplier, + int32_t* quantized_multiplier, + int* left_shift); + +// Decompose a double multiplier into a Q0.31 int32 representation of its +// significand, and shift representation of its exponent. +// +// Handles an arbitrary positive multiplier. The 'shift' output-value is +// basically the 'floating-point exponent' of the multiplier: +// Negative for a right-shift (when the multiplier is <1), positive for a +// left-shift (when the multiplier is >1) +void QuantizeMultiplier(double double_multiplier, int32_t* quantized_multiplier, + int* shift); + +// Splits a double input value into a returned fraction, and a shift value from +// the exponent, using only bitwise and integer operations to support +// microcontrollers and other environments without floating-point support. +// +// This is designed to be a replacement for how std::frexp() is used within the +// QuantizeMultiplier() function, and so has a different signature than the +// standard version, returning a 64-bit integer rather than a double. This +// result has a maximum value of 1<<31, with the fraction expressed as a +// proportion of that maximum. +// +// std::frexp() returns NaNs and infinities unmodified, but since we're +// returning integers that can't represent those values, instead we return +// a shift of std::numeric_limits::max() for all bad numbers, with an int64 +// result of 0 for NaNs, std:numeric_limits::max() for +INFINITY, and +// std::numeric_limits::min() for -INFINITY. Denormalized inputs will +// result in return values that end up truncating some bits at the end, +// reflecting the loss of precision inherent in denormalization. +int64_t IntegerFrExp(double input, int* shift); + +// Converts an integer fraction in the format produced by IntegerFrExp (where +// 0x40000000 is 1.0) and an exponent shift (between -1022 and +1022) into an +// IEEE binary64 double format result. The implementation uses only integer and +// bitwise operators, so no floating point hardware support or emulation is +// needed. This is here so quantized operations can run non-time-critical +// preparation calculations on microcontrollers and other platforms without +// float support. +double DoubleFromFractionAndShift(int64_t fraction, int shift); + +// Performs a multiplication of two numbers in double format, using only integer +// and bitwise instructions. This is aimed at supporting housekeeping functions +// for quantized operations on microcontrollers without floating-point hardware. +double IntegerDoubleMultiply(double a, double b); + +// Returns -1 if a is less than b, 0 if a and b are equal, and +1 if a is +// greater than b. It is implemented using only integer and logical instructions +// so that it can be easily run on microcontrollers for quantized operations. +int IntegerDoubleCompare(double a, double b); + +// This first creates a multiplier in a double equivalent of +// Q(input_integer_bits).(31-input_integer_bits) representation, with extra +// precision in the double's fractional bits. It then splits the result into +// significand and exponent. +void PreprocessSoftmaxScaling(double beta, double input_scale, + int input_integer_bits, + int32_t* quantized_multiplier, int* left_shift); +// Like PreprocessSoftmaxScaling, but inverse scaling factors also calculated. +void PreprocessLogSoftmaxScalingExp(double beta, double input_scale, + int input_integer_bits, + int32_t* quantized_multiplier, + int* left_shift, + int32_t* reverse_scaling_divisor, + int* reverse_scaling_left_shift); +// Calculate the largest input that will result in a within-bounds intermediate +// result within MultiplyByQuantizedMultiplierGreaterThanOne. In other words, +// it must not overflow before we reduce the value by multiplication by the +// input multiplier. The negative radius is used as the minimum difference in +// Softmax. +int CalculateInputRadius(int input_integer_bits, int input_left_shift, + int total_signed_bits = 31); + +// Nudges a min/max quantization range to ensure zero is zero. +// Gymnastics with nudged zero point is to ensure that real zero maps to +// an integer, which is required for e.g. zero-padding in convolutional layers. +// Outputs nudged_min, nudged_max, nudged_scale. +void NudgeQuantizationRange(const float min, const float max, + const int quant_min, const int quant_max, + float* nudged_min, float* nudged_max, + float* nudged_scale); + +// Fake quantizes (quantizes and dequantizes) input_data using the scale, +// nudged_min, and nudged_max from NudgeQuantizationRange. This matches the code +// in TensorFlow's FakeQuantizeWithMinMaxVarsFunctor. +void FakeQuantizeArray(const float nudged_scale, const float nudged_min, + const float nudged_max, const float* input_data, + float* output_data, const float size); + +// If x is approximately a power of two (with any positive or negative +// exponent), stores that exponent (i.e. log2(x)) in *log2_result, otherwise +// returns false. +bool CheckedLog2(const float x, int* log2_result); + +// Decomposes an array of double multipliers into a Q0.31 int32 representation +// of its significand, and shift representation of its exponent. +// +// Handles an arbitrary multiplier. The 'shift' output-value is +// basically the 'floating-point exponent' of the multiplier: +// Negative for a right-shift (when the multiplier is <1), positive for a +// left-shift (when the multiplier is >1) +void QuantizeMultiplierArray(const double* effective_scales, size_t size, + int32_t* effective_scale_significand, + int* effective_shift); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_QUANTIZATION_UTIL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h new file mode 100644 index 0000000..ada6696 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h @@ -0,0 +1,400 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ADD_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ADD_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { + +namespace reference_ops { + +template +inline void Add(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + T activation_min, activation_max; + GetActivationParams(params, &activation_min, &activation_max); + + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = ActivationFunctionWithMinMax( + input1_data[i] + input2_data[i], activation_min, activation_max); + } +} + +// Element-wise add that can often be used for inner loop of broadcast add as +// well as the non-broadcast add. + +// This function is used for 8-bit as well as for 16-bit, but the accumulator +// is 32-bit for both cases. The overflow does not happen due to the +// choice of the shift (20 or 15, accordingly - see add.cc for more comments). +template +inline void AddElementwise(int size, const ArithmeticParams& params, + const T* input1_data, const T* input2_data, + T* output_data) { + TFLITE_DCHECK_GT(params.input1_offset, -std::numeric_limits::max()); + TFLITE_DCHECK_GT(params.input2_offset, -std::numeric_limits::max()); + TFLITE_DCHECK_LT(params.input1_offset, std::numeric_limits::max()); + TFLITE_DCHECK_LT(params.input2_offset, std::numeric_limits::max()); + + for (int i = 0; i < size; ++i) { + const int32_t input1_val = params.input1_offset + input1_data[i]; + const int32_t input2_val = params.input2_offset + input2_data[i]; + const int32_t shifted_input1_val = input1_val * (1 << params.left_shift); + const int32_t shifted_input2_val = input2_val * (1 << params.left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, params.input1_multiplier, params.input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, params.input2_multiplier, params.input2_shift); + const int32_t raw_sum = scaled_input1_val + scaled_input2_val; + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + raw_sum, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[i] = static_cast(clamped_output); + } +} + +// Scalar-broadcast add that can be used for inner loop of more general +// broadcast add, so that, for example, scalar-broadcast with batch will still +// be fast. +inline void AddScalarBroadcast(int size, const ArithmeticParams& params, + uint8_t input1_data, const uint8_t* input2_data, + uint8_t* output_data) { + TFLITE_DCHECK_GT(params.input1_offset, -256); + TFLITE_DCHECK_GT(params.input2_offset, -256); + TFLITE_DCHECK_LT(params.input1_offset, 256); + TFLITE_DCHECK_LT(params.input2_offset, 256); + + const int32_t input1_val = params.input1_offset + input1_data; + const int32_t shifted_input1_val = input1_val * (1 << params.left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, params.input1_multiplier, params.input1_shift); + for (int i = 0; i < size; ++i) { + const int32_t input2_val = params.input2_offset + input2_data[i]; + const int32_t shifted_input2_val = input2_val * (1 << params.left_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, params.input2_multiplier, params.input2_shift); + const int32_t raw_sum = scaled_input1_val + scaled_input2_val; + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + raw_sum, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[i] = static_cast(clamped_output); + } +} + +inline void Add(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const uint8_t* input1_data, + const RuntimeShape& input2_shape, const uint8_t* input2_data, + const RuntimeShape& output_shape, uint8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + TFLITE_DCHECK_GT(params.input1_offset, -256); + TFLITE_DCHECK_GT(params.input2_offset, -256); + TFLITE_DCHECK_LT(params.input1_offset, 256); + TFLITE_DCHECK_LT(params.input2_offset, 256); + AddElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +inline void AddGeneralParamScale(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const int16_t* input1_data, + const RuntimeShape& input2_shape, + const int16_t* input2_data, + const RuntimeShape& output_shape, + int16_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + int max_value = std::numeric_limits::max(); + + TFLITE_DCHECK_GT(params.input1_offset, -max_value); + TFLITE_DCHECK_GT(params.input2_offset, -max_value); + TFLITE_DCHECK_LT(params.input1_offset, max_value); + TFLITE_DCHECK_LT(params.input2_offset, max_value); + AddElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +inline void Add(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const int16_t* input1_data, + const RuntimeShape& input2_shape, const int16_t* input2_data, + const RuntimeShape& output_shape, int16_t* output_data, + bool pot_scale = true) { + if (!pot_scale) { + AddGeneralParamScale(params, input1_shape, input1_data, input2_shape, + input2_data, output_shape, output_data); + return; + } + + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + + const int input1_shift = params.input1_shift; + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + const int16_t output_activation_min = params.quantized_activation_min; + const int16_t output_activation_max = params.quantized_activation_max; + + TFLITE_DCHECK(input1_shift == 0 || params.input2_shift == 0); + TFLITE_DCHECK_LE(input1_shift, 0); + TFLITE_DCHECK_LE(params.input2_shift, 0); + const int16_t* not_shift_input = + input1_shift == 0 ? input1_data : input2_data; + const int16_t* shift_input = input1_shift == 0 ? input2_data : input1_data; + const int input_right_shift = + input1_shift == 0 ? -params.input2_shift : -input1_shift; + + for (int i = 0; i < flat_size; i++) { + // F0 uses 0 integer bits, range [-1, 1]. + using F0 = gemmlowp::FixedPoint; + + F0 input_ready_scaled = F0::FromRaw(not_shift_input[i]); + F0 scaled_input = F0::FromRaw( + gemmlowp::RoundingDivideByPOT(shift_input[i], input_right_shift)); + F0 result = gemmlowp::SaturatingAdd(scaled_input, input_ready_scaled); + const int16_t raw_output = result.raw(); + const int16_t clamped_output = std::min( + output_activation_max, std::max(output_activation_min, raw_output)); + output_data[i] = clamped_output; + } +} + +template +inline typename std::enable_if::value, void>::type +BroadcastAdd4DSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(4, output_shape); + + T activation_min, activation_max; + GetActivationParams(params, &activation_min, &activation_max); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + for (int b = 0; b < extended_output_shape.Dims(0); ++b) { + for (int y = 0; y < extended_output_shape.Dims(1); ++y) { + for (int x = 0; x < extended_output_shape.Dims(2); ++x) { + for (int c = 0; c < extended_output_shape.Dims(3); ++c) { + output_data[Offset(extended_output_shape, b, y, x, c)] = + ActivationFunctionWithMinMax( + input1_data[SubscriptToIndex(desc1, b, y, x, c)] + + input2_data[SubscriptToIndex(desc2, b, y, x, c)], + activation_min, activation_max); + } + } + } + } +} + +// This function is used for 8-bit as well as for 16-bit, but the accumulator +// is 32-bit for both cases. The overflow does not happen due to the +// choice of the shift (20 or 15, accordingly - see add.cc for more comments). +template +inline typename std::enable_if::value, void>::type +BroadcastAdd4DSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(4, output_shape); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + for (int b = 0; b < extended_output_shape.Dims(0); ++b) { + for (int y = 0; y < extended_output_shape.Dims(1); ++y) { + for (int x = 0; x < extended_output_shape.Dims(2); ++x) { + for (int c = 0; c < extended_output_shape.Dims(3); ++c) { + const int32_t input1_val = + params.input1_offset + + input1_data[SubscriptToIndex(desc1, b, y, x, c)]; + const int32_t input2_val = + params.input2_offset + + input2_data[SubscriptToIndex(desc2, b, y, x, c)]; + const int32_t shifted_input1_val = + input1_val * (1 << params.left_shift); + const int32_t shifted_input2_val = + input2_val * (1 << params.left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, params.input1_multiplier, + params.input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, params.input2_multiplier, + params.input2_shift); + const int32_t raw_sum = scaled_input1_val + scaled_input2_val; + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + raw_sum, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[Offset(extended_output_shape, b, y, x, c)] = + static_cast(clamped_output); + } + } + } + } +} + +inline void BroadcastAddFivefold(const ArithmeticParams& unswitched_params, + const RuntimeShape& unswitched_input1_shape, + const uint8_t* unswitched_input1_data, + const RuntimeShape& unswitched_input2_shape, + const uint8_t* unswitched_input2_data, + const RuntimeShape& output_shape, + uint8_t* output_data) { + ArithmeticParams switched_params = unswitched_params; + switched_params.input1_offset = unswitched_params.input2_offset; + switched_params.input1_multiplier = unswitched_params.input2_multiplier; + switched_params.input1_shift = unswitched_params.input2_shift; + switched_params.input2_offset = unswitched_params.input1_offset; + switched_params.input2_multiplier = unswitched_params.input1_multiplier; + switched_params.input2_shift = unswitched_params.input1_shift; + + const bool use_unswitched = + unswitched_params.broadcast_category == + tflite::BroadcastableOpCategory::kFirstInputBroadcastsFast; + + const ArithmeticParams& params = + use_unswitched ? unswitched_params : switched_params; + const uint8_t* input1_data = + use_unswitched ? unswitched_input1_data : unswitched_input2_data; + const uint8_t* input2_data = + use_unswitched ? unswitched_input2_data : unswitched_input1_data; + + // Fivefold nested loops. The second input resets its position for each + // iteration of the second loop. The first input resets its position at the + // beginning of the fourth loop. The innermost loop is an elementwise add of + // sections of the arrays. + uint8_t* output_data_ptr = output_data; + const uint8_t* input1_data_ptr = input1_data; + const uint8_t* input2_data_reset = input2_data; + // In the fivefold pattern, y0, y2 and y4 are not broadcast, and so shared + // between input shapes. y3 for input 1 is always broadcast, and so the + // dimension there is 1, whereas optionally y1 might be broadcast for input 2. + // Put another way, + // input1.shape.FlatSize = y0 * y1 * y2 * y4, + // input2.shape.FlatSize = y0 * y2 * y3 * y4. + int y0 = params.broadcast_shape[0]; + int y1 = params.broadcast_shape[1]; + int y2 = params.broadcast_shape[2]; + int y3 = params.broadcast_shape[3]; + int y4 = params.broadcast_shape[4]; + if (y4 > 1) { + // General fivefold pattern, with y4 > 1 so there is a non-broadcast inner + // dimension. + for (int i0 = 0; i0 < y0; ++i0) { + const uint8_t* input2_data_ptr; + for (int i1 = 0; i1 < y1; ++i1) { + input2_data_ptr = input2_data_reset; + for (int i2 = 0; i2 < y2; ++i2) { + for (int i3 = 0; i3 < y3; ++i3) { + AddElementwise(y4, params, input1_data_ptr, input2_data_ptr, + output_data_ptr); + input2_data_ptr += y4; + output_data_ptr += y4; + } + // We have broadcast y4 of input1 data y3 times, and now move on. + input1_data_ptr += y4; + } + } + // We have broadcast y2*y3*y4 of input2 data y1 times, and now move on. + input2_data_reset = input2_data_ptr; + } + } else { + // Special case of y4 == 1, in which the innermost loop is a single element + // and can be combined with the next (y3) as an inner broadcast. + // + // Note that this handles the case of pure scalar broadcast when + // y0 == y1 == y2 == 1. With low overhead it handles cases such as scalar + // broadcast with batch (as y2 > 1). + // + // NOTE The process is the same as the above general case except simplified + // for y4 == 1 and the loop over y3 is contained within the + // AddScalarBroadcast function. + for (int i0 = 0; i0 < y0; ++i0) { + const uint8_t* input2_data_ptr; + for (int i1 = 0; i1 < y1; ++i1) { + input2_data_ptr = input2_data_reset; + for (int i2 = 0; i2 < y2; ++i2) { + AddScalarBroadcast(y3, params, *input1_data_ptr, input2_data_ptr, + output_data_ptr); + input2_data_ptr += y3; + output_data_ptr += y3; + input1_data_ptr += 1; + } + } + input2_data_reset = input2_data_ptr; + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ADD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add_n.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add_n.h new file mode 100644 index 0000000..7b5424c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add_n.h @@ -0,0 +1,86 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ADD_N_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ADD_N_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_ops { + +// T is expected to be either float or int. +template +inline void AddN(const RuntimeShape& input_shape, const size_t num_inputs, + const T* const* input_data, T* output_data) { + // All inputs and output should have the same shape, this is checked during + // Prepare stage. + const size_t size = input_shape.FlatSize(); + for (size_t i = 0; i < size; ++i) { + T x = 0; + for (size_t j = 0; j < num_inputs; ++j) { + x += input_data[j][i]; + } + output_data[i] = x; + } +} + +inline void AddN(const ArithmeticParams& params, + const RuntimeShape& input_shape, const size_t num_inputs, + const int8_t* const* input_data, int8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + // Input offset is negative input zero point. Activation tensors are + // asymmetric quantized so they span the full int8 range. + // All inputs should have same zero-point and scale, this is checked during + // Prepare stage. + TFLITE_DCHECK_GE(-params.input1_offset, std::numeric_limits::min()); + TFLITE_DCHECK_LE(-params.input1_offset, std::numeric_limits::max()); + + // All inputs and output should have the same shape, this is checked during + // Prepare stage. + const size_t size = input_shape.FlatSize(); + for (size_t i = 0; i < size; ++i) { + // accumulate in scaled_x before clamping to avoid overflow + const int32_t x = params.input1_offset; // x = 0 + const int32_t shifted_x = x * (1 << params.left_shift); + int32_t scaled_x = MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_x, params.input1_multiplier, params.input1_shift); + + for (size_t j = 0; j < num_inputs; ++j) { + const int32_t y = params.input1_offset + input_data[j][i]; + const int32_t shifted_y = y * (1 << params.left_shift); + int32_t scaled_y = MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_y, params.input1_multiplier, params.input1_shift); + scaled_x += scaled_y; + } + + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + scaled_x, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[i] = static_cast(clamped_output); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ADD_N_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/arg_min_max.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/arg_min_max.h new file mode 100644 index 0000000..7de12f7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/arg_min_max.h @@ -0,0 +1,88 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ARG_MIN_MAX_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ARG_MIN_MAX_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +template +std::function GetComparefunction(bool is_arg_max) { + if (is_arg_max) { + return std::greater(); + } else { + return std::less(); + } +} + +template +void ArgMinMax(const RuntimeShape& input1_shape, const T1* input1_data, + const T3* input2_data, const RuntimeShape& output_shape, + T2* output_data, const Cmp& cmp) { + TFLITE_DCHECK_GT(input1_shape.DimensionsCount(), 0); + TFLITE_DCHECK_EQ(input1_shape.DimensionsCount() - 1, + output_shape.DimensionsCount()); + int axis = input2_data[0]; + if (axis < 0) { + axis += input1_shape.DimensionsCount(); + } + const int axis_size = input1_shape.Dims(axis); + + int outer_size = 1; + for (int i = 0; i < axis; ++i) { + TFLITE_DCHECK_EQ(input1_shape.Dims(i), output_shape.Dims(i)); + outer_size *= input1_shape.Dims(i); + } + + int inner_size = 1; + const int dims_count = input1_shape.DimensionsCount(); + for (int i = axis + 1; i < dims_count; ++i) { + TFLITE_DCHECK_EQ(input1_shape.Dims(i), output_shape.Dims(i - 1)); + inner_size *= input1_shape.Dims(i); + } + for (int outer = 0; outer < outer_size; ++outer) { + for (int inner = 0; inner < inner_size; ++inner) { + auto min_max_value = input1_data[outer * axis_size * inner_size + inner]; + T2 min_max_index = 0; + for (int i = 1; i < axis_size; ++i) { + const auto& curr_value = + input1_data[(outer * axis_size + i) * inner_size + inner]; + if (cmp(curr_value, min_max_value)) { + min_max_value = curr_value; + min_max_index = static_cast(i); + } + } + output_data[outer * inner_size + inner] = min_max_index; + } + } +} + +template +void ArgMinMax(const RuntimeShape& input1_shape, const T1* input1_data, + const T3* input2_data, const RuntimeShape& output_shape, + T2* output_data, const bool is_arg_max) { + ArgMinMax(input1_shape, input1_data, input2_data, output_shape, output_data, + GetComparefunction(is_arg_max)); +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ARG_MIN_MAX_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_matmul.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_matmul.h new file mode 100644 index 0000000..3695bad --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_matmul.h @@ -0,0 +1,275 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BATCH_MATMUL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BATCH_MATMUL_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { +namespace batch_matmul { + +// Determine which dimension is the broadcast dimension. +inline int broadcast_dim(int lhs_dim, int rhs_dim) { + if (lhs_dim == rhs_dim) return lhs_dim; + if (lhs_dim == 1) return rhs_dim; + TFLITE_DCHECK_EQ(rhs_dim, 1); + return lhs_dim; +} + +// Compute the "extent" for iterating on this dimension. +// If we are broadcasting, then don't advance (i.e return 0). +inline int extent(const RuntimeShape& shape, int x) { + if (shape.Dims(x) == 1) { + return 0; + } + int prod = 1; + for (int i = x + 1; i < shape.DimensionsCount(); ++i) { + prod *= shape.Dims(i); + } + return prod; +} + +} // namespace batch_matmul + +template +inline void BatchMatMul(const RuntimeShape& lhs_shape, const Ta* lhs_data, + const RuntimeShape& rhs_shape, const Tb* rhs_data, + const RuntimeShape& output_shape, Tout* output_data) { + const RuntimeShape extended_lhs_shape = + RuntimeShape::ExtendedShape(5, lhs_shape); + const RuntimeShape extended_rhs_shape = + RuntimeShape::ExtendedShape(5, rhs_shape); + + const int batch_dim0 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(0), extended_rhs_shape.Dims(0)); + const int batch_dim1 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(1), extended_rhs_shape.Dims(1)); + const int batch_dim2 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(2), extended_rhs_shape.Dims(2)); + + const int lhs_ext0 = batch_matmul::extent(extended_lhs_shape, 0); + const int lhs_ext1 = batch_matmul::extent(extended_lhs_shape, 1); + const int lhs_ext2 = batch_matmul::extent(extended_lhs_shape, 2); + const int rhs_ext0 = batch_matmul::extent(extended_rhs_shape, 0); + const int rhs_ext1 = batch_matmul::extent(extended_rhs_shape, 1); + const int rhs_ext2 = batch_matmul::extent(extended_rhs_shape, 2); + + // Set params for each matrix multiply. + const int lhs_rows = extended_lhs_shape.Dims(3); + const int rhs_cols = extended_rhs_shape.Dims(4); + const int accum_depth = extended_lhs_shape.Dims(4); + + for (int b0 = 0; b0 < batch_dim0; ++b0) { + const Ta* lhs_ptr0 = lhs_data + (b0 * lhs_ext0); + const Tb* rhs_ptr0 = rhs_data + (b0 * rhs_ext0); + for (int b1 = 0; b1 < batch_dim1; ++b1) { + const Ta* lhs_ptr1 = lhs_ptr0 + b1 * lhs_ext1; + const Tb* rhs_ptr1 = rhs_ptr0 + b1 * rhs_ext1; + for (int b2 = 0; b2 < batch_dim2; ++b2) { + const Ta* lhs_ptr2 = lhs_ptr1 + b2 * lhs_ext2; + const Tb* rhs_ptr2 = rhs_ptr1 + b2 * rhs_ext2; + Tout* out_ptr = output_data + ((b0 * batch_dim1 * batch_dim2) + + b1 * batch_dim2 + b2) * + lhs_rows * rhs_cols; + for (int j = 0; j < rhs_cols; ++j) { + for (int i = 0; i < lhs_rows; ++i) { + Tout total = 0; + for (int k = 0; k < accum_depth; ++k) { + total += static_cast(lhs_ptr2[accum_depth * i + k]) * + static_cast(rhs_ptr2[j * accum_depth + k]); + } + int idx = lhs_rows * j + i; + out_ptr[idx] = total; + } + } + } + } + } +} + +inline void BatchMatMul(const RuntimeShape& lhs_shape, const int8_t* lhs_data, + const RuntimeShape& rhs_shape, const int8_t* rhs_data, + const float* scaling_factors, + const int32_t* input_offset, int32_t* row_sums, + const RuntimeShape& output_shape, float* output_data, + bool* compute_row_sums) { + const RuntimeShape extended_lhs_shape = + RuntimeShape::ExtendedShape(5, lhs_shape); + const RuntimeShape extended_rhs_shape = + RuntimeShape::ExtendedShape(5, rhs_shape); + + const int batch_dim0 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(0), extended_rhs_shape.Dims(0)); + const int batch_dim1 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(1), extended_rhs_shape.Dims(1)); + const int batch_dim2 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(2), extended_rhs_shape.Dims(2)); + + const int lhs_ext0 = batch_matmul::extent(extended_lhs_shape, 0); + const int lhs_ext1 = batch_matmul::extent(extended_lhs_shape, 1); + const int lhs_ext2 = batch_matmul::extent(extended_lhs_shape, 2); + const int rhs_ext0 = batch_matmul::extent(extended_rhs_shape, 0); + const int rhs_ext1 = batch_matmul::extent(extended_rhs_shape, 1); + const int rhs_ext2 = batch_matmul::extent(extended_rhs_shape, 2); + + // Set params for each matrix multiply. + const int lhs_rows = extended_lhs_shape.Dims(3); + const int rhs_cols = extended_rhs_shape.Dims(4); + const int accum_depth = extended_lhs_shape.Dims(4); + + const int ioff_ext0 = rhs_ext0 == 0 ? 0 : rhs_cols; + const int ioff_ext1 = rhs_ext1 == 0 ? 0 : rhs_cols; + const int ioff_ext2 = rhs_ext2 == 0 ? 0 : rhs_cols; + const int woff_ext0 = lhs_ext0 == 0 ? 0 : lhs_rows; + const int woff_ext1 = lhs_ext1 == 0 ? 0 : lhs_rows; + const int woff_ext2 = lhs_ext2 == 0 ? 0 : lhs_rows; + + if (!compute_row_sums || *compute_row_sums) { + int num_weights_matrices = 1; + for (int i = 1; i < extended_lhs_shape.DimensionsCount() - 2; ++i) { + num_weights_matrices *= extended_lhs_shape.Dims(i); + } + tensor_utils::ReductionSumVector( + lhs_data, row_sums, num_weights_matrices * lhs_rows, accum_depth); + if (compute_row_sums) { + *compute_row_sums = false; + } + } + + for (int b0 = 0; b0 < batch_dim0; ++b0) { + const int8_t* lhs_ptr0 = lhs_data + (b0 * lhs_ext0); + const int8_t* rhs_ptr0 = rhs_data + (b0 * rhs_ext0); + const int32_t* ioff_ptr0 = input_offset + (b0 * ioff_ext0); + const float* scale_ptr0 = scaling_factors + (b0 * ioff_ext0); + const int32_t* woff_ptr0 = row_sums + (b0 * woff_ext0); + for (int b1 = 0; b1 < batch_dim1; ++b1) { + const int8_t* lhs_ptr1 = lhs_ptr0 + b1 * lhs_ext1; + const int8_t* rhs_ptr1 = rhs_ptr0 + b1 * rhs_ext1; + const int32_t* ioff_ptr1 = ioff_ptr0 + (b1 * ioff_ext1); + const float* scale_ptr1 = scale_ptr0 + (b1 * ioff_ext1); + const int32_t* woff_ptr1 = woff_ptr0 + (b1 * woff_ext1); + for (int b2 = 0; b2 < batch_dim2; ++b2) { + const int8_t* lhs_ptr2 = lhs_ptr1 + b2 * lhs_ext2; + const int8_t* rhs_ptr2 = rhs_ptr1 + b2 * rhs_ext2; + const int32_t* ioff_ptr2 = ioff_ptr1 + (b2 * ioff_ext2); + const float* scale_ptr2 = scale_ptr1 + (b2 * ioff_ext2); + const int32_t* woff_ptr2 = woff_ptr1 + (b2 * woff_ext2); + float* out_ptr = output_data + ((b0 * batch_dim1 * batch_dim2) + + b1 * batch_dim2 + b2) * + lhs_rows * rhs_cols; + for (int j = 0; j < rhs_cols; ++j) { + const float batch_scaling_factor = scale_ptr2[j]; + const float batch_offset = static_cast(ioff_ptr2[j]); + for (int i = 0; i < lhs_rows; ++i) { + int32_t total = 0; + for (int k = 0; k < accum_depth; ++k) { + total += + lhs_ptr2[accum_depth * i + k] * rhs_ptr2[j * accum_depth + k]; + } + int32_t row_sum = woff_ptr2[i]; + total -= row_sum * batch_offset; + int idx = lhs_rows * j + i; + out_ptr[idx] += batch_scaling_factor * total; + } + } + } + } + } +} + +template +inline void BatchMatMul(const FullyConnectedParams& params, + const RuntimeShape& lhs_shape, const T* lhs_data, + const RuntimeShape& rhs_shape, const T* rhs_data, + const RuntimeShape& output_shape, T* output_data) { + const RuntimeShape extended_lhs_shape = + RuntimeShape::ExtendedShape(5, lhs_shape); + const RuntimeShape extended_rhs_shape = + RuntimeShape::ExtendedShape(5, rhs_shape); + + const int batch_dim0 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(0), extended_rhs_shape.Dims(0)); + const int batch_dim1 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(1), extended_rhs_shape.Dims(1)); + const int batch_dim2 = batch_matmul::broadcast_dim( + extended_lhs_shape.Dims(2), extended_rhs_shape.Dims(2)); + + const int lhs_ext0 = batch_matmul::extent(extended_lhs_shape, 0); + const int lhs_ext1 = batch_matmul::extent(extended_lhs_shape, 1); + const int lhs_ext2 = batch_matmul::extent(extended_lhs_shape, 2); + const int rhs_ext0 = batch_matmul::extent(extended_rhs_shape, 0); + const int rhs_ext1 = batch_matmul::extent(extended_rhs_shape, 1); + const int rhs_ext2 = batch_matmul::extent(extended_rhs_shape, 2); + + // Set params for each matrix multiply. + const int lhs_rows = extended_lhs_shape.Dims(3); + const int rhs_cols = extended_rhs_shape.Dims(4); + const int accum_depth = extended_lhs_shape.Dims(4); + + const int32_t input_offset = params.input_offset; + const int32_t filter_offset = params.weights_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + + for (int b0 = 0; b0 < batch_dim0; ++b0) { + const T* lhs_ptr0 = lhs_data + (b0 * lhs_ext0); + const T* rhs_ptr0 = rhs_data + (b0 * rhs_ext0); + for (int b1 = 0; b1 < batch_dim1; ++b1) { + const T* lhs_ptr1 = lhs_ptr0 + b1 * lhs_ext1; + const T* rhs_ptr1 = rhs_ptr0 + b1 * rhs_ext1; + for (int b2 = 0; b2 < batch_dim2; ++b2) { + const T* lhs_ptr2 = lhs_ptr1 + b2 * lhs_ext2; + const T* rhs_ptr2 = rhs_ptr1 + b2 * rhs_ext2; + T* out_ptr = output_data + + ((b0 * batch_dim1 * batch_dim2) + b1 * batch_dim2 + b2) * + lhs_rows * rhs_cols; + + for (int j = 0; j < rhs_cols; ++j) { + for (int i = 0; i < lhs_rows; ++i) { + AccumT total = 0; + for (int k = 0; k < accum_depth; ++k) { + AccumT lhs_val = lhs_ptr2[accum_depth * i + k]; + AccumT rhs_val = rhs_ptr2[accum_depth * j + k]; + total += (lhs_val + filter_offset) * (rhs_val + input_offset); + } + int32_t total_scaled = MultiplyByQuantizedMultiplier( + total, output_multiplier, output_shift); + total_scaled += output_offset; + total_scaled = std::max(total_scaled, output_activation_min); + total_scaled = std::min(total_scaled, output_activation_max); + const int idx = lhs_rows * j + i; + out_ptr[idx] = static_cast(total_scaled); + } + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BATCH_MATMUL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_to_space_nd.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_to_space_nd.h new file mode 100644 index 0000000..72c39e6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_to_space_nd.h @@ -0,0 +1,101 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BATCH_TO_SPACE_ND_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BATCH_TO_SPACE_ND_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +// TODO(b/135760455): Move this method anonymous namespace in a cc file. +inline RuntimeShape ExtendShapeBatchToSpace(const RuntimeShape& shape) { + if (shape.DimensionsCount() == 4) { + return shape; + } + RuntimeShape new_shape(4, 1); + new_shape.SetDim(0, shape.Dims(0)); + new_shape.SetDim(1, shape.Dims(1)); + new_shape.SetDim(3, shape.Dims(2)); + return new_shape; +} + +template +inline void BatchToSpaceND(const RuntimeShape& unextended_input1_shape, + const T* input1_data, + const RuntimeShape& unextended_input2_shape, + const int32_t* block_shape_data, + const RuntimeShape& unextended_input3_shape, + const int32_t* crops_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + ruy::profiler::ScopeLabel label("BatchToSpaceND"); + TFLITE_DCHECK_GE(unextended_input1_shape.DimensionsCount(), 3); + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(unextended_input1_shape.DimensionsCount(), + unextended_output_shape.DimensionsCount()); + + const RuntimeShape input1_shape = + ExtendShapeBatchToSpace(unextended_input1_shape); + const RuntimeShape output_shape = + ExtendShapeBatchToSpace(unextended_output_shape); + + const int output_width = output_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_batch_size = output_shape.Dims(0); + + const int depth = input1_shape.Dims(3); + const int input_width = input1_shape.Dims(2); + const int input_height = input1_shape.Dims(1); + const int input_batch_size = input1_shape.Dims(0); + + const int block_shape_height = block_shape_data[0]; + const int block_shape_width = + unextended_input1_shape.DimensionsCount() == 4 ? block_shape_data[1] : 1; + const int crops_top = crops_data[0]; + const int crops_left = + unextended_input1_shape.DimensionsCount() == 4 ? crops_data[2] : 0; + for (int in_batch = 0; in_batch < input_batch_size; ++in_batch) { + const int out_batch = in_batch % output_batch_size; + const int spatial_offset = in_batch / output_batch_size; + for (int in_h = 0; in_h < input_height; ++in_h) { + const int out_h = in_h * block_shape_height + + spatial_offset / block_shape_width - crops_top; + if (out_h < 0 || out_h >= output_height) { + continue; + } + for (int in_w = 0; in_w < input_width; ++in_w) { + const int out_w = in_w * block_shape_width + + spatial_offset % block_shape_width - crops_left; + + if (out_w < 0 || out_w >= output_width) { + continue; + } + T* out = output_data + Offset(output_shape, out_batch, out_h, out_w, 0); + const T* in = + input1_data + Offset(input1_shape, in_batch, in_h, in_w, 0); + memcpy(out, in, depth * sizeof(T)); + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BATCH_TO_SPACE_ND_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h new file mode 100644 index 0000000..66101d9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h @@ -0,0 +1,91 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BINARY_FUNCTION_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BINARY_FUNCTION_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +// Also appears to duplicate MinimumMaximum. +// +// R: Result type. T1: Input 1 type. T2: Input 2 type. +template +inline void BroadcastBinaryFunction4DSlow( + const RuntimeShape& unextended_input1_shape, const T1* input1_data, + const RuntimeShape& unextended_input2_shape, const T2* input2_data, + const RuntimeShape& unextended_output_shape, R* output_data, + R (*func)(T1, T2)) { + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(unextended_input1_shape, + unextended_input2_shape, &desc1, &desc2); + + const int* dims_data = + reinterpret_cast(output_shape.DimsDataUpTo5D()); + for (int b = 0; b < output_shape.Dims(0); ++b) { + int out_idx_b = b * dims_data[1]; + int in_idx1_b = desc1.strides[0] * b; + int in_idx2_b = desc2.strides[0] * b; + for (int y = 0; y < output_shape.Dims(1); ++y) { + int out_idx_y = (out_idx_b + y) * dims_data[2]; + int in_idx1_y = in_idx1_b + desc1.strides[1] * y; + int in_idx2_y = in_idx2_b + desc2.strides[1] * y; + for (int x = 0; x < output_shape.Dims(2); ++x) { + int out_idx_x = (out_idx_y + x) * dims_data[3]; + int in1_idx = in_idx1_y + desc1.strides[2] * x; + int in2_idx = in_idx2_y + desc2.strides[2] * x; + for (int c = 0; c < output_shape.Dims(3); ++c) { + auto out_idx = out_idx_x + c; + auto in1_val = input1_data[in1_idx]; + auto in2_val = input2_data[in2_idx]; + output_data[out_idx] = func(in1_val, in2_val); + in1_idx += desc1.strides[3]; + in2_idx += desc2.strides[3]; + } + } + } + } +} + +// R: Result type. T1: Input 1 type. T2: Input 2 type. +template +inline void BinaryFunction(const RuntimeShape& input1_shape, + const T1* input1_data, + const RuntimeShape& input2_shape, + const T2* input2_data, + const RuntimeShape& output_shape, R* output_data, + R (*func)(T1, T2)) { + const int flat_size = + MatchingFlatSize(input1_shape, input2_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = func(input1_data[i], input2_data[i]); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BINARY_FUNCTION_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_args.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_args.h new file mode 100644 index 0000000..341c418 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_args.h @@ -0,0 +1,56 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BROADCAST_ARGS_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BROADCAST_ARGS_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +void BroadcastArgs(const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + // Gets data at the backward index i of the shape tensor. Returns 1 if the + // index is out of range. + auto get_shape_data = [](const RuntimeShape& shape, const T* data, + int backward_idx) -> T { + int forward_idx = shape.FlatSize() - 1 - backward_idx; + if (forward_idx < 0) return 1; + return data[forward_idx]; + }; + + int output_num_elements = output_shape.FlatSize(); + for (int i = 0; i < output_num_elements; ++i) { + int backward_i = output_num_elements - 1 - i; + int shape1_i = get_shape_data(input1_shape, input1_data, i); + int shape2_i = get_shape_data(input2_shape, input2_data, i); + if (shape1_i == 1) { + output_data[backward_i] = shape2_i; + } else if (shape2_i == 1) { + output_data[backward_i] = shape1_i; + } else { + TFLITE_CHECK_EQ(shape1_i, shape2_i); + output_data[backward_i] = shape1_i; + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BROADCAST_ARGS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_to.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_to.h new file mode 100644 index 0000000..79756cb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_to.h @@ -0,0 +1,97 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BROADCAST_TO_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BROADCAST_TO_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" + +namespace tflite { +namespace reference_ops { +template +void BroadcastImpl(const NdArrayDesc& input_desc, const char* input_data, + const NdArrayDesc& output_desc, char* output_data, + int indexes[N], int dim, const int last_broadcasting_dim, + const int type_size) { + // Copy data from input to output. + if (dim == last_broadcasting_dim) { + int copy_size = output_desc.strides[dim] * type_size; + const char* data_src = + input_data + SubscriptToIndex(input_desc, indexes) * type_size; + char* data_dst = + output_data + SubscriptToIndex(output_desc, indexes) * type_size; + for (int i = 0; i < output_desc.extents[dim]; ++i, data_dst += copy_size) { + memcpy(data_dst, data_src, copy_size); + } + return; + } + + // Recursive call to find the next broadcasting. + for (indexes[dim] = 0; indexes[dim] < input_desc.extents[dim]; + ++indexes[dim]) { + BroadcastImpl(input_desc, input_data, output_desc, output_data, indexes, + dim + 1, last_broadcasting_dim, type_size); + } + + // Duplicate data in output tensor. + indexes[dim] = 0; + if (input_desc.extents[dim] != output_desc.extents[dim]) { + int copy_size = output_desc.strides[dim] * type_size; + char* data_src = + output_data + SubscriptToIndex(output_desc, indexes) * type_size; + char* data_dst = data_src + copy_size; + for (int i = 1; i < output_desc.extents[dim]; ++i, data_dst += copy_size) { + memcpy(data_dst, data_src, copy_size); + } + } +} + +template +inline void BroadcastTo(const RuntimeShape& unextended_input_shape, + const char* input_data, + const RuntimeShape& unextended_output_shape, + char* output_data, TfLiteType data_type) { + NdArrayDesc input_desc; + NdArrayDesc output_desc; + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, unextended_input_shape), + &input_desc); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, unextended_output_shape), + &output_desc); + + // Get the last dimension has broadcasting. At this dimension, the data is + // copied from input tensor to output tensor. + int last_broadcast_dim = -1; + for (int i = N - 1; i >= 0; --i) { + if (input_desc.extents[i] != output_desc.extents[i]) { + last_broadcast_dim = i; + break; + } + } + + // If non-broadcasting, just copy data from input to output tensor. + if (last_broadcast_dim == -1) { + memcpy(output_data, input_data, + unextended_input_shape.FlatSize() * TfLiteTypeGetSize(data_type)); + return; + } + + // Broadcasting using memcpy. + int indexes[N] = {0}; + BroadcastImpl(input_desc, input_data, output_desc, output_data, indexes, 0, + last_broadcast_dim, TfLiteTypeGetSize(data_type)); +} +} // namespace reference_ops +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_BROADCAST_TO_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/ceil.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/ceil.h new file mode 100644 index 0000000..5be295d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/ceil.h @@ -0,0 +1,37 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CEIL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CEIL_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline void Ceil(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; ++i) { + output_data[i] = std::ceil(input_data[i]); + } +} + +} // namespace reference_ops +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CEIL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/comparisons.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/comparisons.h new file mode 100644 index 0000000..f3d6bcc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/comparisons.h @@ -0,0 +1,280 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_COMPARISONS_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_COMPARISONS_H_ + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +template +inline bool EqualFn(T lhs, T rhs) { + return lhs == rhs; +} + +template +inline bool NotEqualFn(T lhs, T rhs) { + return lhs != rhs; +} + +template +inline bool GreaterFn(T lhs, T rhs) { + return lhs > rhs; +} +template +inline bool GreaterEqualFn(T lhs, T rhs) { + return lhs >= rhs; +} +template +inline bool LessFn(T lhs, T rhs) { + return lhs < rhs; +} +template +inline bool LessEqualFn(T lhs, T rhs) { + return lhs <= rhs; +} + +template +using ComparisonFn = bool (*)(T, T); + +template F> +inline void ComparisonImpl( + const ComparisonParams& op_params, const RuntimeShape& input1_shape, + const T* input1_data, const RuntimeShape& input2_shape, + const T* input2_data, const RuntimeShape& output_shape, bool* output_data) { + const int64_t flatsize = + MatchingFlatSize(input1_shape, input2_shape, output_shape); + for (int64_t i = 0; i < flatsize; ++i) { + output_data[i] = F(input1_data[i], input2_data[i]); + } +} + +template F> +inline void Comparison(const ComparisonParams& op_params, + const RuntimeShape& input1_shape, + const float* input1_data, + const RuntimeShape& input2_shape, + const float* input2_data, + const RuntimeShape& output_shape, bool* output_data) { + ComparisonImpl(op_params, input1_shape, input1_data, input2_shape, + input2_data, output_shape, output_data); +} + +template F> +inline void ComparisonWithScaling( + const ComparisonParams& op_params, const RuntimeShape& input1_shape, + const T* input1_data, const RuntimeShape& input2_shape, + const T* input2_data, const RuntimeShape& output_shape, bool* output_data) { + int left_shift = op_params.left_shift; + int32_t input1_offset = op_params.input1_offset; + int32_t input1_multiplier = op_params.input1_multiplier; + int input1_shift = op_params.input1_shift; + int32_t input2_offset = op_params.input2_offset; + int32_t input2_multiplier = op_params.input2_multiplier; + int input2_shift = op_params.input2_shift; + + const int64_t flatsize = + MatchingFlatSize(input1_shape, input2_shape, output_shape); + for (int64_t i = 0; i < flatsize; ++i) { + const int32_t input1_val = input1_offset + input1_data[i]; + const int32_t input2_val = input2_offset + input2_data[i]; + const int32_t shifted_input1_val = input1_val * (1 << left_shift); + const int32_t shifted_input2_val = input2_val * (1 << left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, input1_multiplier, input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, input2_multiplier, input2_shift); + output_data[i] = F(scaled_input1_val, scaled_input2_val); + } +} + +struct BroadcastComparison4DSlowCommon { + const RuntimeShape output_shape; + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; +}; + +inline BroadcastComparison4DSlowCommon BroadcastComparison4DSlowPreprocess( + const RuntimeShape& unextended_input1_shape, + const RuntimeShape& unextended_input2_shape, + const RuntimeShape& unextended_output_shape) { + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(unextended_input1_shape, + unextended_input2_shape, &desc1, &desc2); + return {RuntimeShape::ExtendedShape(4, unextended_output_shape), desc1, + desc2}; +} + +template F> +inline void BroadcastComparison4DSlowImpl( + const ComparisonParams& op_params, + const RuntimeShape& unextended_input1_shape, const T* input1_data, + const RuntimeShape& unextended_input2_shape, const T* input2_data, + const RuntimeShape& unextended_output_shape, bool* output_data) { + const BroadcastComparison4DSlowCommon dims = + BroadcastComparison4DSlowPreprocess(unextended_input1_shape, + unextended_input2_shape, + unextended_output_shape); + + for (int b = 0; b < dims.output_shape.Dims(0); ++b) { + for (int y = 0; y < dims.output_shape.Dims(1); ++y) { + for (int x = 0; x < dims.output_shape.Dims(2); ++x) { + for (int c = 0; c < dims.output_shape.Dims(3); ++c) { + output_data[Offset(dims.output_shape, b, y, x, c)] = + F(input1_data[SubscriptToIndex(dims.desc1, b, y, x, c)], + input2_data[SubscriptToIndex(dims.desc2, b, y, x, c)]); + } + } + } + } +} + +template F> +inline void BroadcastComparison4DSlow(const ComparisonParams& op_params, + const RuntimeShape& input1_shape, + const float* input1_data, + const RuntimeShape& input2_shape, + const float* input2_data, + const RuntimeShape& output_shape, + bool* output_data) { + BroadcastComparison4DSlowImpl(op_params, input1_shape, input1_data, + input2_shape, input2_data, + output_shape, output_data); +} + +template F> +inline void BroadcastComparison4DSlowWithScaling( + const ComparisonParams& op_params, + const RuntimeShape& unextended_input1_shape, const T* input1_data, + const RuntimeShape& unextended_input2_shape, const T* input2_data, + const RuntimeShape& unextended_output_shape, bool* output_data) { + const BroadcastComparison4DSlowCommon dims = + BroadcastComparison4DSlowPreprocess(unextended_input1_shape, + unextended_input2_shape, + unextended_output_shape); + + int left_shift = op_params.left_shift; + int32_t input1_offset = op_params.input1_offset; + int32_t input1_multiplier = op_params.input1_multiplier; + int input1_shift = op_params.input1_shift; + int32_t input2_offset = op_params.input2_offset; + int32_t input2_multiplier = op_params.input2_multiplier; + int input2_shift = op_params.input2_shift; + + for (int b = 0; b < dims.output_shape.Dims(0); ++b) { + for (int y = 0; y < dims.output_shape.Dims(1); ++y) { + for (int x = 0; x < dims.output_shape.Dims(2); ++x) { + for (int c = 0; c < dims.output_shape.Dims(3); ++c) { + const int32_t input1_val = + input1_offset + + input1_data[SubscriptToIndex(dims.desc1, b, y, x, c)]; + const int32_t input2_val = + input2_offset + + input2_data[SubscriptToIndex(dims.desc2, b, y, x, c)]; + const int32_t shifted_input1_val = input1_val * (1 << left_shift); + const int32_t shifted_input2_val = input2_val * (1 << left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, input1_multiplier, input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, input2_multiplier, input2_shift); + output_data[Offset(dims.output_shape, b, y, x, c)] = + F(scaled_input1_val, scaled_input2_val); + } + } + } + } +} + +#define TFLITE_COMPARISON_OP(name) \ + inline void name(const ComparisonParams& op_params, \ + const RuntimeShape& input1_shape, const float* input1_data, \ + const RuntimeShape& input2_shape, const float* input2_data, \ + const RuntimeShape& output_shape, bool* output_data) { \ + Comparison(op_params, input1_shape, input1_data, input2_shape, \ + input2_data, output_shape, output_data); \ + } \ + template \ + inline void name##NoScaling( \ + const ComparisonParams& op_params, const RuntimeShape& input1_shape, \ + const T* input1_data, const RuntimeShape& input2_shape, \ + const T* input2_data, const RuntimeShape& output_shape, \ + bool* output_data) { \ + ComparisonImpl(op_params, input1_shape, input1_data, \ + input2_shape, input2_data, output_shape, \ + output_data); \ + } \ + template \ + inline void name##WithScaling( \ + const ComparisonParams& op_params, const RuntimeShape& input1_shape, \ + const T* input1_data, const RuntimeShape& input2_shape, \ + const T* input2_data, const RuntimeShape& output_shape, \ + bool* output_data) { \ + ComparisonWithScaling(op_params, input1_shape, input1_data, \ + input2_shape, input2_data, \ + output_shape, output_data); \ + } \ + template \ + inline void Broadcast4DSlow##name##NoScaling( \ + const ComparisonParams& op_params, const RuntimeShape& input1_shape, \ + const T* input1_data, const RuntimeShape& input2_shape, \ + const T* input2_data, const RuntimeShape& output_shape, \ + bool* output_data) { \ + BroadcastComparison4DSlowImpl( \ + op_params, input1_shape, input1_data, input2_shape, input2_data, \ + output_shape, output_data); \ + } \ + inline void Broadcast4DSlow##name( \ + const ComparisonParams& op_params, const RuntimeShape& input1_shape, \ + const float* input1_data, const RuntimeShape& input2_shape, \ + const float* input2_data, const RuntimeShape& output_shape, \ + bool* output_data) { \ + BroadcastComparison4DSlow(op_params, input1_shape, input1_data, \ + input2_shape, input2_data, \ + output_shape, output_data); \ + } \ + template \ + inline void Broadcast4DSlow##name##WithScaling( \ + const ComparisonParams& op_params, const RuntimeShape& input1_shape, \ + const T* input1_data, const RuntimeShape& input2_shape, \ + const T* input2_data, const RuntimeShape& output_shape, \ + bool* output_data) { \ + BroadcastComparison4DSlowWithScaling( \ + op_params, input1_shape, input1_data, input2_shape, input2_data, \ + output_shape, output_data); \ + } +TFLITE_COMPARISON_OP(Equal); +TFLITE_COMPARISON_OP(NotEqual); +TFLITE_COMPARISON_OP(Greater); +TFLITE_COMPARISON_OP(GreaterEqual); +TFLITE_COMPARISON_OP(Less); +TFLITE_COMPARISON_OP(LessEqual); +#undef TFLITE_COMPARISON_OP + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_COMPARISONS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/concatenation.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/concatenation.h new file mode 100644 index 0000000..9d03523 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/concatenation.h @@ -0,0 +1,141 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CONCATENATION_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CONCATENATION_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +inline void Concatenation(const ConcatenationParams& params, + const RuntimeShape* const* input_shapes, + const Scalar* const* input_data, + const RuntimeShape& output_shape, + Scalar* output_data) { + int axis = params.axis; + int inputs_count = params.inputs_count; + const int concat_dimensions = output_shape.DimensionsCount(); + TFLITE_DCHECK_LT(axis, concat_dimensions); + + int64_t concat_size = 0; + for (int i = 0; i < inputs_count; i++) { + TFLITE_DCHECK_EQ(input_shapes[i]->DimensionsCount(), concat_dimensions); + for (int j = 0; j < concat_dimensions; j++) { + if (j != axis) { + MatchingDim(*input_shapes[i], j, output_shape, j); + } + } + concat_size += input_shapes[i]->Dims(axis); + } + TFLITE_DCHECK_EQ(concat_size, output_shape.Dims(axis)); + int64_t outer_size = 1; + for (int i = 0; i < axis; ++i) { + outer_size *= output_shape.Dims(i); + } + // For all input arrays, + // FlatSize() = outer_size * Dims(axis) * base_inner_size; + int64_t base_inner_size = 1; + for (int i = axis + 1; i < concat_dimensions; ++i) { + base_inner_size *= output_shape.Dims(i); + } + + Scalar* output_ptr = output_data; + for (int k = 0; k < outer_size; k++) { + for (int i = 0; i < inputs_count; ++i) { + const int copy_size = input_shapes[i]->Dims(axis) * base_inner_size; + const Scalar* input_ptr = input_data[i] + k * copy_size; + memcpy(output_ptr, input_ptr, copy_size * sizeof(Scalar)); + output_ptr += copy_size; + } + } +} + +// TODO(b/174275780): The quantized implementation of concatentation isn't fully +// quantized as it takes scale as a floating point value. This should be fixed +// when optimizng this routine further. +inline void ConcatenationWithScaling(const ConcatenationParams& params, + const RuntimeShape* const* input_shapes, + const uint8_t* const* input_data, + const RuntimeShape& output_shape, + uint8_t* output_data) { + int axis = params.axis; + const int32_t* input_zeropoint = params.input_zeropoint; + const float* input_scale = params.input_scale; + int inputs_count = params.inputs_count; + const int32_t output_zeropoint = params.output_zeropoint; + const float output_scale = params.output_scale; + + const int concat_dimensions = output_shape.DimensionsCount(); + TFLITE_DCHECK_LT(axis, concat_dimensions); + + int64_t concat_size = 0; + for (int i = 0; i < inputs_count; i++) { + TFLITE_DCHECK_EQ(input_shapes[i]->DimensionsCount(), concat_dimensions); + for (int j = 0; j < concat_dimensions; j++) { + if (j != axis) { + MatchingDim(*input_shapes[i], j, output_shape, j); + } + } + concat_size += input_shapes[i]->Dims(axis); + } + TFLITE_DCHECK_EQ(concat_size, output_shape.Dims(axis)); + int64_t outer_size = 1; + for (int i = 0; i < axis; ++i) { + outer_size *= output_shape.Dims(i); + } + // For all input arrays, + // FlatSize() = outer_size * Dims(axis) * base_inner_size; + int64_t base_inner_size = 1; + for (int i = axis + 1; i < concat_dimensions; ++i) { + base_inner_size *= output_shape.Dims(i); + } + + const float inverse_output_scale = 1.f / output_scale; + uint8_t* output_ptr = output_data; + for (int k = 0; k < outer_size; k++) { + for (int i = 0; i < inputs_count; ++i) { + const int copy_size = input_shapes[i]->Dims(axis) * base_inner_size; + const uint8_t* input_ptr = input_data[i] + k * copy_size; + if (input_zeropoint[i] == output_zeropoint && + input_scale[i] == output_scale) { + memcpy(output_ptr, input_ptr, copy_size); + } else { + const float scale = input_scale[i] * inverse_output_scale; + const float bias = -input_zeropoint[i] * scale; + for (int j = 0; j < copy_size; ++j) { + const int32_t value = static_cast(tflite::TfLiteRound( + input_ptr[j] * scale + bias)) + + output_zeropoint; + output_ptr[j] = static_cast( + std::max(std::min(255, value), 0)); + } + } + output_ptr += copy_size; + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CONCATENATION_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h new file mode 100644 index 0000000..a244ec0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h @@ -0,0 +1,287 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CONV_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CONV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline void Conv(const ConvParams& params, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& filter_shape, + const float* filter_data, const RuntimeShape& bias_shape, + const float* bias_data, const RuntimeShape& output_shape, + float* output_data, const RuntimeShape& im2col_shape, + float* im2col_data) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const float output_activation_min = params.float_activation_min; + const float output_activation_max = params.float_activation_max; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + (void)im2col_data; // only used in optimized code. + (void)im2col_shape; // only used in optimized code. + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = input_shape.Dims(3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int filter_input_depth = filter_shape.Dims(3); + const int groups = input_depth / filter_input_depth; + TFLITE_DCHECK_EQ(input_depth % filter_input_depth, 0); + const int filters_per_group = output_depth / groups; + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + const int in_y_origin = (out_y * stride_height) - pad_height; + for (int out_x = 0; out_x < output_width; ++out_x) { + const int in_x_origin = (out_x * stride_width) - pad_width; + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + auto group = out_channel / filters_per_group; + float total = 0.f; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + const int in_y = in_y_origin + dilation_height_factor * filter_y; + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + + if (!is_point_inside_image) { + continue; + } + for (int in_channel = 0; in_channel < filter_input_depth; + ++in_channel) { + float input_value = + input_data[Offset(input_shape, batch, in_y, in_x, + in_channel + group * filter_input_depth)]; + float filter_value = filter_data[Offset( + filter_shape, out_channel, filter_y, filter_x, in_channel)]; + total += (input_value * filter_value); + } + } + } + float bias_value = 0.0f; + if (bias_data) { + bias_value = bias_data[out_channel]; + } + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + ActivationFunctionWithMinMax(total + bias_value, + output_activation_min, + output_activation_max); + } + } + } + } +} + +inline void Conv(const ConvParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& filter_shape, + const uint8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + uint8_t* output_data, const RuntimeShape& im2col_shape, + uint8_t* im2col_data, void* cpu_backend_context) { + (void)cpu_backend_context; // only used in optimized code. + (void)im2col_data; // only used in optimized code. + (void)im2col_shape; // only used in optimized code. + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int32_t input_offset = params.input_offset; + const int32_t filter_offset = params.weights_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = input_shape.Dims(3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int filter_input_depth = filter_shape.Dims(3); + const int groups = input_depth / filter_input_depth; + TFLITE_DCHECK_EQ(input_depth % filter_input_depth, 0); + const int filters_per_group = output_depth / groups; + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + const int in_y_origin = (out_y * stride_height) - pad_height; + for (int out_x = 0; out_x < output_width; ++out_x) { + const int in_x_origin = (out_x * stride_width) - pad_width; + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + auto group = out_channel / filters_per_group; + int32_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + const int in_y = in_y_origin + dilation_height_factor * filter_y; + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + + if (!is_point_inside_image) { + continue; + } + + for (int in_channel = 0; in_channel < filter_input_depth; + ++in_channel) { + int32_t input_val = + input_data[Offset(input_shape, batch, in_y, in_x, + in_channel + group * filter_input_depth)]; + int32_t filter_val = filter_data[Offset( + filter_shape, out_channel, filter_y, filter_x, in_channel)]; + acc += + (filter_val + filter_offset) * (input_val + input_offset); + } + } + } + if (bias_data) { + acc += bias_data[out_channel]; + } + acc = MultiplyByQuantizedMultiplier(acc, output_multiplier, + output_shift); + acc += output_offset; + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + static_cast(acc); + } + } + } + } +} + +inline void HybridConvPerChannel( + const ConvParams& params, float* scaling_factors_ptr, + const RuntimeShape& input_shape, const int8_t* input_data, + const RuntimeShape& filter_shape, const int8_t* filter_data, + const RuntimeShape& bias_shape, const float* bias_data, + const RuntimeShape& output_shape, float* output_data, + const RuntimeShape& im2col_shape, int8_t* im2col_data, + const float* per_channel_scale, int32_t* input_offset) { + (void)im2col_data; // only used in optimized code. + (void)im2col_shape; // only used in optimized code. + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const float output_activation_min = params.float_activation_min; + const float output_activation_max = params.float_activation_max; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = input_shape.Dims(3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int filter_input_depth = filter_shape.Dims(3); + const int groups = input_depth / filter_input_depth; + TFLITE_DCHECK_EQ(input_depth % filter_input_depth, 0); + const int filters_per_group = output_depth / groups; + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + auto group = out_channel / filters_per_group; + const int in_x_origin = (out_x * stride_width) - pad_width; + const int in_y_origin = (out_y * stride_height) - pad_height; + int32_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + for (int in_channel = 0; in_channel < filter_input_depth; + ++in_channel) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + const int in_y = + in_y_origin + dilation_height_factor * filter_y; + // If the location is outside the bounds of the input image, + // use zero as a default value. + if ((in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height)) { + int32_t input_val = input_data[Offset( + input_shape, batch, in_y, in_x, + in_channel + group * filter_input_depth)]; + int32_t filter_val = + filter_data[Offset(filter_shape, out_channel, filter_y, + filter_x, in_channel)]; + acc += filter_val * (input_val - input_offset[batch]); + } + } + } + } + float acc_float = + acc * per_channel_scale[out_channel] * scaling_factors_ptr[batch]; + if (bias_data) { + acc_float += bias_data[out_channel]; + } + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + ActivationFunctionWithMinMax(acc_float, output_activation_min, + output_activation_max); + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CONV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/cumsum.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/cumsum.h new file mode 100644 index 0000000..56698a0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/cumsum.h @@ -0,0 +1,175 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CUMSUM_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CUMSUM_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" + +namespace tflite { +namespace reference_ops { + +template +inline void CumSum(const T* input_data, const RuntimeShape& shape, int32_t axis, + bool exclusive, bool reverse, T* output_data) { + const int32_t rank = shape.DimensionsCount(); + TFLITE_DCHECK_GE(rank, 1); + TFLITE_DCHECK_GE(axis, 0); + TFLITE_DCHECK_LT(axis, rank); + + size_t inner = 1; + size_t outer = 1; + size_t depth = 1; + for (int32_t i = 0; i < rank; i++) { + if (i < axis) + inner *= shape.Dims(i); + else if (i > axis) + outer *= shape.Dims(i); + else + depth = shape.Dims(i); + } + + for (size_t outer_index = 0; outer_index < outer; outer_index++) { + size_t outer_index_adj; + if (reverse) + outer_index_adj = (outer - 1) - outer_index; + else + outer_index_adj = outer_index; + for (size_t inner_index = 0; inner_index < inner; inner_index++) { + T accumulator = 0; + size_t inner_index_adj; + if (reverse) + inner_index_adj = (inner - 1) - inner_index; + else + inner_index_adj = inner_index; + for (size_t depth_index = 0; depth_index < depth; depth_index++) { + size_t depth_index_adj; + if (reverse) + depth_index_adj = (depth - 1) - depth_index; + else + depth_index_adj = depth_index; + + size_t index = outer_index_adj; + index += inner_index_adj * depth * outer; + index += depth_index_adj * outer; + + if (exclusive) { + output_data[index] = accumulator; + accumulator += input_data[index]; + } else { + accumulator += input_data[index]; + output_data[index] = accumulator; + } + } + } + } +} + +// +// Quantized INT8 CUMSUM +// +inline void CumSum(const ArithmeticParams& params, const int8_t* input_data, + const RuntimeShape& shape, int32_t axis, bool exclusive, + bool reverse, int8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + // Input offset is negative input zero point. Activation tensors are + // asymmetric quantized so they span the full int8 range. + // All inputs should have same zero-point and scale, this is checked during + // Prepare stage. + TFLITE_DCHECK_GE(-params.input1_offset, std::numeric_limits::min()); + TFLITE_DCHECK_LE(-params.input1_offset, std::numeric_limits::max()); + + const int32_t rank = shape.DimensionsCount(); + TFLITE_DCHECK_GE(rank, 1); + TFLITE_DCHECK_GE(axis, 0); + TFLITE_DCHECK_LT(axis, rank); + + size_t inner = 1; + size_t outer = 1; + size_t depth = 1; + for (int32_t i = 0; i < rank; i++) { + if (i < axis) + inner *= shape.Dims(i); + else if (i > axis) + outer *= shape.Dims(i); + else + depth = shape.Dims(i); + } + + for (size_t outer_index = 0; outer_index < outer; outer_index++) { + size_t outer_index_adj; + if (reverse) + outer_index_adj = (outer - 1) - outer_index; + else + outer_index_adj = outer_index; + for (size_t inner_index = 0; inner_index < inner; inner_index++) { + int32_t accumulator = params.input1_offset; // accumulator = 0 + accumulator *= (1 << params.left_shift); + accumulator = MultiplyByQuantizedMultiplierSmallerThanOneExp( + accumulator, params.input1_multiplier, params.input1_shift); + + size_t inner_index_adj; + if (reverse) + inner_index_adj = (inner - 1) - inner_index; + else + inner_index_adj = inner_index; + + for (size_t depth_index = 0; depth_index < depth; depth_index++) { + size_t depth_index_adj; + if (reverse) + depth_index_adj = (depth - 1) - depth_index; + else + depth_index_adj = depth_index; + + size_t index = outer_index_adj; + index += inner_index_adj * depth * outer; + index += depth_index_adj * outer; + + const int32_t y = params.input1_offset + input_data[index]; + const int32_t shifted_y = y * (1 << params.left_shift); + const int32_t scaled_y = MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_y, params.input1_multiplier, params.input1_shift); + + int32_t scaled_output; + if (exclusive) { + scaled_output = accumulator; + accumulator += scaled_y; + } else { + accumulator += scaled_y; + scaled_output = accumulator; + } + + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + scaled_output, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[index] = static_cast(clamped_output); + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_CUMSUM_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depth_to_space.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depth_to_space.h new file mode 100644 index 0000000..41b2679 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depth_to_space.h @@ -0,0 +1,79 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTH_TO_SPACE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTH_TO_SPACE_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +inline void DepthToSpace(const tflite::DepthToSpaceParams& op_params, + const RuntimeShape& unextended_input_shape, + const T* input_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + const int input_depth = input_shape.Dims(3); + const int input_width = input_shape.Dims(2); + const int input_height = input_shape.Dims(1); + const int input_batch = input_shape.Dims(0); + + const int output_depth = output_shape.Dims(3); + const int output_width = output_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_batch = output_shape.Dims(0); + + const int32_t block_size = op_params.block_size; + + TFLITE_DCHECK_EQ(input_width * block_size, output_width); + TFLITE_DCHECK_EQ(input_height * block_size, output_height); + TFLITE_DCHECK_EQ(input_depth, output_depth * block_size * block_size); + TFLITE_DCHECK_EQ(input_batch, output_batch); + + for (int out_b = 0; out_b < output_batch; ++out_b) { + for (int out_h = 0; out_h < output_height; ++out_h) { + for (int out_w = 0; out_w < output_width; ++out_w) { + for (int out_d = 0; out_d < output_depth; ++out_d) { + const int in_d = + out_d + ((out_h % block_size) * block_size + out_w % block_size) * + output_depth; + + const int in_w = out_w / block_size; + const int in_h = out_h / block_size; + const int in_b = out_b; + + const int input_index = Offset(input_shape, in_b, in_h, in_w, in_d); + const int output_index = + Offset(output_shape, out_b, out_h, out_w, out_d); + + output_data[output_index] = input_data[input_index]; + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTH_TO_SPACE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h new file mode 100644 index 0000000..33a1b9b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h @@ -0,0 +1,100 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTHWISECONV_FLOAT_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTHWISECONV_FLOAT_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +inline void DepthwiseConv( + const DepthwiseParams& params, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& filter_shape, + const float* filter_data, const RuntimeShape& bias_shape, + const float* bias_data, const RuntimeShape& output_shape, + float* output_data) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int depth_multiplier = params.depth_multiplier; + const float output_activation_min = params.float_activation_min; + const float output_activation_max = params.float_activation_max; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int input_depth = input_shape.Dims(3); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + TFLITE_DCHECK_EQ(output_depth, input_depth * depth_multiplier); + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + + for (int b = 0; b < batches; ++b) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int ic = 0; ic < input_depth; ++ic) { + for (int m = 0; m < depth_multiplier; m++) { + const int oc = m + ic * depth_multiplier; + const int in_x_origin = (out_x * stride_width) - pad_width; + const int in_y_origin = (out_y * stride_height) - pad_height; + float total = 0.f; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + const int in_y = + in_y_origin + dilation_height_factor * filter_y; + // If the location is outside the bounds of the input image, + // use zero as a default value. + if ((in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height)) { + float input_value = + input_data[Offset(input_shape, b, in_y, in_x, ic)]; + float filter_value = filter_data[Offset( + filter_shape, 0, filter_y, filter_x, oc)]; + total += (input_value * filter_value); + } + } + } + float bias_value = 0.0f; + if (bias_data) { + bias_value = bias_data[oc]; + } + output_data[Offset(output_shape, b, out_y, out_x, oc)] = + ActivationFunctionWithMinMax(total + bias_value, + output_activation_min, + output_activation_max); + } + } + } + } + } +} + +} // end namespace reference_ops +} // end namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTHWISECONV_FLOAT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_uint8.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_uint8.h new file mode 100644 index 0000000..4dc5245 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_uint8.h @@ -0,0 +1,319 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTHWISECONV_UINT8_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTHWISECONV_UINT8_H_ + +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +// Used in tests and template parameters to control which version of depthwise +// convolution is called. Primarily for reference code, and specializations +// forced in tests. +enum class DepthwiseConvImplementation { + // Run all tests against kUseStandardEntry even if also testing another + // kernel, since we need to be sure that the main DepthwiseConv() function in + // optimized_ops.h dispatches to a correctly-executing kernel. + kNone = 0, // The "default" option: use the normal + // DepthwiseConv kernel (entry) function. + kUseGenericKernel, // Forced use of generic kernel. + kUseNeon3x3, // 3x3 kernel that uses NEON when available. + kUseNeon3x3DotProduct, // 3x3 kernel that uses dot-product enabled NEON + // when available. + kUseCModel3x3DotProduct, // 3x3 kernel, reference C model that is intended + // to match overall design NEON code. + kUseUnwound3x3DotProduct, // 3x3 kernel, reference C model with unwound loops + // and some arrays. + kUseIntrinsics3x3DotProduct, // 3x3 kernel using NEON intrinsics. +}; + +// Category of depthwise convolution output rounding. +enum class DepthwiseConvOutputRounding { + kNone = 0, // Invalid: specific method must be specified. + kAwayFromZero, // Original method: exact halves rounded away from zero. + kUpward, // Halves towards +infinity: adds 0.5 before truncate. + // This is where a future kNearestEven would be placed. +}; + +// Category of depthwise convolution depth multiplication. +enum class DepthwiseConvDepthMultiplication { + kNoMultiplication = 0, // Depth multiplier = 1. + kUnitInputDepth, // Input depth = 1, output depth = depth multiplier. +}; + +namespace reference_ops { +namespace depthwise_conv { + +template +inline int32_t DepthwiseConvRound(int32_t x, int32_t quantized_multiplier, + int shift) { + TFLITE_DCHECK_NE(output_rounding, DepthwiseConvOutputRounding::kNone); + return MultiplyByQuantizedMultiplier(x, quantized_multiplier, shift); +} + +// Single-rounding MultiplyByQuantizedMultiplier +#if TFLITE_SINGLE_ROUNDING +template <> +inline int32_t DepthwiseConvRound( + int32_t x, int32_t quantized_multiplier, int shift) { + using gemmlowp::RoundingDivideByPOT; + using gemmlowp::SaturatingRoundingDoublingHighMul; + int left_shift = shift > 0 ? shift : 0; + int right_shift = shift > 0 ? 0 : -shift; + return RoundingDivideByPOT(SaturatingRoundingDoublingHighMul( + x * (1 << left_shift), quantized_multiplier), + right_shift); +} + +template <> +inline int32_t DepthwiseConvRound( + int32_t x, int32_t quantized_multiplier, int shift) { + return MultiplyByQuantizedMultiplier(x, quantized_multiplier, shift); +} +// Double-rounding MultiplyByQuantizedMultiplier +#else +template <> +inline int32_t DepthwiseConvRound( + int32_t x, int32_t quantized_multiplier, int shift) { + return MultiplyByQuantizedMultiplier(x, quantized_multiplier, shift); +} + +template <> +inline int32_t DepthwiseConvRound( + int32_t x, int32_t quantized_multiplier, int shift) { + using gemmlowp::SaturatingRoundingDoublingHighMul; + const int left_shift = shift > 0 ? shift : 0; + const int right_shift = shift > 0 ? 0 : -shift; + const int rounding_offset = right_shift > 0 ? 1 << (right_shift - 1) : 0; + return (SaturatingRoundingDoublingHighMul(x * (1 << left_shift), + quantized_multiplier) + + rounding_offset) >> + right_shift; +} +#endif // TFLITE_SINGLE_ROUNDING + +template +struct DepthwiseConvBasicKernel { + static inline void Run( + const DepthwiseParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& filter_shape, + const uint8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + uint8_t* output_data) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int depth_multiplier = params.depth_multiplier; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + const int32_t input_offset = params.input_offset; + const int32_t filter_offset = params.weights_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int input_depth = input_shape.Dims(3); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + TFLITE_DCHECK_EQ(output_depth, input_depth * depth_multiplier); + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + + for (int b = 0; b < batches; ++b) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int ic = 0; ic < input_depth; ++ic) { + for (int m = 0; m < depth_multiplier; m++) { + const int oc = m + ic * depth_multiplier; + const int in_x_origin = (out_x * stride_width) - pad_width; + const int in_y_origin = (out_y * stride_height) - pad_height; + int32_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = + in_x_origin + dilation_width_factor * filter_x; + const int in_y = + in_y_origin + dilation_height_factor * filter_y; + // If the location is outside the bounds of the input image, + // use zero as a default value. + if ((in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height)) { + int32_t input_val = + input_data[Offset(input_shape, b, in_y, in_x, ic)]; + int32_t filter_val = filter_data[Offset( + filter_shape, 0, filter_y, filter_x, oc)]; + acc += (filter_val + filter_offset) * + (input_val + input_offset); + } + } + } + if (bias_data) { + acc += bias_data[oc]; + } + acc = DepthwiseConvRound(acc, output_multiplier, + output_shift); + acc += output_offset; + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_data[Offset(output_shape, b, out_y, out_x, oc)] = + static_cast(acc); + } + } + } + } + } + } + + // TODO(b/148596273): Reconcile reference versions, perhaps with common + // MultiplyByQuantizedMultiplier or DepthwiseConvRound function. + static inline void RunPerChannel( + const DepthwiseParams& params, const RuntimeShape& input_shape, + const int8_t* input_data, const RuntimeShape& filter_shape, + const int8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + int8_t* output_data) { + // Get parameters. + // TODO(b/141565753): Re-introduce ScopedProfilingLabel on Micro. + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int depth_multiplier = params.depth_multiplier; + const int32_t input_offset = params.input_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + const int32_t* output_multiplier = params.output_multiplier_per_channel; + const int32_t* output_shift = params.output_shift_per_channel; + + // Check dimensions of the tensors. + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int input_depth = input_shape.Dims(3); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + TFLITE_DCHECK_EQ(output_depth, input_depth * depth_multiplier); + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + for (int m = 0; m < depth_multiplier; ++m) { + const int output_channel = m + in_channel * depth_multiplier; + const int in_x_origin = (out_x * stride_width) - pad_width; + const int in_y_origin = (out_y * stride_height) - pad_height; + int32_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = + in_x_origin + dilation_width_factor * filter_x; + const int in_y = + in_y_origin + dilation_height_factor * filter_y; + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + if (is_point_inside_image) { + int32_t input_val = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + int32_t filter_val = filter_data[Offset( + filter_shape, 0, filter_y, filter_x, output_channel)]; + // Accumulate with 32 bits accumulator. + // In the nudging process during model quantization, we + // force real value of 0.0 be represented by a quantized + // value. This guarantees that the input_offset is a int8_t, + // even though it is represented using int32_t. int32_t += + // int8_t + // * (int8_t - int8_t) so the highest value we can get from + // each accumulation is [-127, 127] * ([-128, 127] - + // [-128, 127]), which is [-32512, 32512]. log2(32512) + // = 14.98, which means we can accumulate at least 2^16 + // multiplications without overflow. The accumulator is + // applied to a filter so the accumulation logic will hold + // as long as the filter size (filter_y * filter_x * + // in_channel) does not exceed 2^16, which is the case in + // all the models we have seen so far. + acc += filter_val * (input_val + input_offset); + } + } + } + if (bias_data) { + acc += bias_data[output_channel]; + } + acc = DepthwiseConvRound( + acc, output_multiplier[output_channel], + output_shift[output_channel]); + acc += output_offset; + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, + output_channel)] = static_cast(acc); + } + } + } + } + } + } +}; + +} // namespace depthwise_conv + +inline void DepthwiseConv( + const DepthwiseParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& filter_shape, + const uint8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + uint8_t* output_data) { + return depthwise_conv::DepthwiseConvBasicKernel< + DepthwiseConvOutputRounding::kAwayFromZero>::Run(params, input_shape, + input_data, filter_shape, + filter_data, bias_shape, + bias_data, output_shape, + output_data); +} + +} // namespace reference_ops +} // end namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEPTHWISECONV_UINT8_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/dequantize.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/dequantize.h new file mode 100644 index 0000000..70f6009 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/dequantize.h @@ -0,0 +1,78 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEQUANTIZE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEQUANTIZE_H_ + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +// Dequantizes into a float without rounding. +template +inline void Dequantize(const tflite::DequantizationParams& op_params, + const RuntimeShape& input_shape, + const InputT* input_data, + const RuntimeShape& output_shape, OutputT* output_data) { + int32_t zero_point = op_params.zero_point; + const double scale = op_params.scale; + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; i++) { + const int32_t val = input_data[i]; + const OutputT result = static_cast(scale * (val - zero_point)); + output_data[i] = result; + } +} + +// Dequantizes per-channel quantized tensor to float. +template +inline void PerChannelDequantize( + const tflite::PerChannelDequantizationParams& op_params, + const RuntimeShape& input_shape, const T* input_data, + const RuntimeShape& output_shape, float* output_data) { + // Ensure flat size is same. + MatchingFlatSize(input_shape, output_shape); + + const int32_t* zero_point = op_params.zero_point; + const float* scale = op_params.scale; + const int32_t quantized_dimension = op_params.quantized_dimension; + const int32_t num_dims = input_shape.DimensionsCount(); + const int32_t* dims_data = input_shape.DimsData(); + std::vector current_dim(num_dims, 0); + + do { + size_t offset = + ReducedOutputOffset(num_dims, reinterpret_cast(dims_data), + current_dim.data(), 0, nullptr); + const int channel = current_dim[quantized_dimension]; + const int32_t val = input_data[offset]; + const float result = + static_cast(scale[channel] * (val - zero_point[channel])); + output_data[offset] = result; + } while (NextIndex(num_dims, reinterpret_cast(dims_data), + current_dim.data())); +} + +} // namespace reference_ops + +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DEQUANTIZE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/div.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/div.h new file mode 100644 index 0000000..71bbeaf --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/div.h @@ -0,0 +1,247 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DIV_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DIV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { + +namespace reference_ops { + +template +inline void DivCheckArithmeticParams(const ArithmeticParams& params) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + // Input offset is negative input zero point. Activation tensors are + // asymmetric quantized so they span the full int8 range. + constexpr int32_t max_value = + static_cast(std::numeric_limits::max()); + TFLITE_DCHECK_GE(params.input1_offset, -max_value); + TFLITE_DCHECK_LE(params.input1_offset, max_value); + TFLITE_DCHECK_GE(params.input2_offset, -max_value); + TFLITE_DCHECK_LE(params.input2_offset, max_value); + TFLITE_DCHECK_GE(params.output_offset, -max_value); + TFLITE_DCHECK_LE(params.output_offset, max_value); +} + +// Element-wise div that can often be used for inner loop of broadcast Div as +// well as the non-broadcast Div. +template +inline void DivElementwise(int size, const ArithmeticParams& params, + const T* input1_data, const T* input2_data, + T* output_data) { + DivCheckArithmeticParams(params); + + for (int i = 0; i < size; ++i) { + int32_t input1_val = params.input1_offset + input1_data[i]; + int32_t input2_val = params.input2_offset + input2_data[i]; + TFLITE_DCHECK_NE(input2_val, 0); + if (input2_val < 0) { + // Invert signs to avoid a negative input2_val as input2_inv needs to be + // positive to be used as multiplier of MultiplyByQuantizedMultiplier. + input1_val = -input1_val; + input2_val = -input2_val; + } + int recip_shift; + const int32_t input2_inv = GetReciprocal(input2_val, 31, &recip_shift); + const int headroom = CountLeadingSignBits(input1_val); + const int32_t unscaled_quotient = + MultiplyByQuantizedMultiplierGreaterThanOne(input1_val, input2_inv, + headroom); + const int total_shift = params.output_shift - recip_shift - headroom; + const int32_t unclamped_result = + params.output_offset + + MultiplyByQuantizedMultiplierSmallerThanOneExp( + unscaled_quotient, params.output_multiplier, total_shift); + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, unclamped_result)); + output_data[i] = static_cast(clamped_output); + } +} + +inline void Div(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const uint8_t* input1_data, + const RuntimeShape& input2_shape, const uint8_t* input2_data, + const RuntimeShape& output_shape, uint8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + DivElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +inline void Div(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const int8_t* input1_data, + const RuntimeShape& input2_shape, const int8_t* input2_data, + const RuntimeShape& output_shape, int8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + DivElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +template +inline void BroadcastDivSlowQuantized( + const ArithmeticParams& params, const RuntimeShape& unextended_input1_shape, + const T* input1_data, const RuntimeShape& unextended_input2_shape, + const T* input2_data, const RuntimeShape& unextended_output_shape, + T* output_data) { + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), N); + + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(unextended_input1_shape, + unextended_input2_shape, &desc1, &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, unextended_output_shape), + &output_desc); + + DivCheckArithmeticParams(params); + + auto div_func = [&](int indexes[N]) { + int32_t input1_val = + params.input1_offset + input1_data[SubscriptToIndex(desc1, indexes)]; + int32_t input2_val = + params.input2_offset + input2_data[SubscriptToIndex(desc2, indexes)]; + TFLITE_DCHECK_NE(input2_val, 0); + if (input2_val < 0) { + // Invert signs to avoid a negative input2_val as input2_inv needs to be + // positive to be used as multiplier of MultiplyByQuantizedMultiplier. + input1_val = -input1_val; + input2_val = -input2_val; + } + int recip_shift; + const int32_t input2_inv = GetReciprocal(input2_val, 31, &recip_shift); + const int headroom = CountLeadingSignBits(input1_val); + const int32_t unscaled_quotient = + MultiplyByQuantizedMultiplierGreaterThanOne(input1_val, input2_inv, + headroom); + const int total_shift = params.output_shift - recip_shift - headroom; + const int32_t unclamped_result = + params.output_offset + + MultiplyByQuantizedMultiplierSmallerThanOneExp( + unscaled_quotient, params.output_multiplier, total_shift); + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, unclamped_result)); + output_data[SubscriptToIndex(output_desc, indexes)] = + static_cast(clamped_output); + }; + NDOpsHelper(output_desc, div_func); +} + +template +inline void BroadcastDivSlow(const ArithmeticParams& params, + const RuntimeShape& unextended_input1_shape, + const uint8_t* input1_data, + const RuntimeShape& unextended_input2_shape, + const uint8_t* input2_data, + const RuntimeShape& unextended_output_shape, + uint8_t* output_data) { + BroadcastDivSlowQuantized( + params, unextended_input1_shape, input1_data, unextended_input2_shape, + input2_data, unextended_output_shape, output_data); +} + +template +inline void BroadcastDivSlow(const ArithmeticParams& params, + const RuntimeShape& unextended_input1_shape, + const int8_t* input1_data, + const RuntimeShape& unextended_input2_shape, + const int8_t* input2_data, + const RuntimeShape& unextended_output_shape, + int8_t* output_data) { + BroadcastDivSlowQuantized( + params, unextended_input1_shape, input1_data, unextended_input2_shape, + input2_data, unextended_output_shape, output_data); +} + +// TODO(jiawen): We can implement BroadcastDiv on buffers of arbitrary +// dimensionality if the runtime code does a single loop over one dimension +// that handles broadcasting as the base case. The code generator would then +// generate max(D1, D2) nested for loops. +template +void BroadcastDivSlow(const ArithmeticParams& params, + const RuntimeShape& unextended_input1_shape, + const T* input1_data, + const RuntimeShape& unextended_input2_shape, + const T* input2_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + T output_activation_min; + T output_activation_max; + GetActivationParams(params, &output_activation_min, &output_activation_max); + + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), N); + + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(unextended_input1_shape, + unextended_input2_shape, &desc1, &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, unextended_output_shape), + &output_desc); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest + // stride, typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + + auto div_func = [&](int indexes[N]) { + output_data[SubscriptToIndex(output_desc, indexes)] = + ActivationFunctionWithMinMax( + input1_data[SubscriptToIndex(desc1, indexes)] / + input2_data[SubscriptToIndex(desc2, indexes)], + output_activation_min, output_activation_max); + }; + NDOpsHelper(output_desc, div_func); +} + +template +inline void Div(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + T output_activation_min; + T output_activation_max; + GetActivationParams(params, &output_activation_min, &output_activation_max); + + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = ActivationFunctionWithMinMax( + input1_data[i] / input2_data[i], output_activation_min, + output_activation_max); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_DIV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/elu.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/elu.h new file mode 100644 index 0000000..e1d50ab --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/elu.h @@ -0,0 +1,37 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ELU_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ELU_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline void Elu(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + const float val = input_data[i]; + output_data[i] = val < 0.0f ? TfLiteExpm1(val) : val; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ELU_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/exp.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/exp.h new file mode 100644 index 0000000..a9a6ccc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/exp.h @@ -0,0 +1,38 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_EXP_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_EXP_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +inline void Exp(const T* input_data, const size_t num_elements, + T* output_data) { + ruy::profiler::ScopeLabel label("Exp"); + for (size_t idx = 0; idx < num_elements; ++idx) { + output_data[idx] = std::exp(input_data[idx]); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_EXP_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fill.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fill.h new file mode 100644 index 0000000..1f140e2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fill.h @@ -0,0 +1,38 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FILL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FILL_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +void Fill(const RuntimeShape& value_shape, const T* value_data, + const RuntimeShape& output_shape, T* output_data) { + TFLITE_DCHECK_EQ(value_shape.DimensionsCount(), 0); + const int flat_size = output_shape.FlatSize(); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = *value_data; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FILL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor.h new file mode 100644 index 0000000..d1e0421 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor.h @@ -0,0 +1,39 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline void Floor(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; i++) { + int offset = i; + output_data[offset] = std::floor(input_data[offset]); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_div.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_div.h new file mode 100644 index 0000000..dbda3f8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_div.h @@ -0,0 +1,35 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_DIV_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_DIV_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +T FloorDiv(T input1, T input2) { + return std::floor(std::divides()(static_cast(input1), + static_cast(input2))); +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_DIV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_mod.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_mod.h new file mode 100644 index 0000000..20ce18b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_mod.h @@ -0,0 +1,44 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_MOD_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_MOD_H_ + +#include +#include + +namespace tflite { + +namespace reference_ops { + +template +T FloorMod(T input1, T input2) { + struct FloatMod { + float operator()(const float lhs, const float rhs) const { + return std::fmod(lhs, rhs); + } + }; + using ModFunc = typename std::conditional::value, + std::modulus, FloatMod>::type; + ModFunc mod_func; + T trunc_mod = mod_func(input1, input2); + return (trunc_mod != 0) && ((input2 < 0) != (trunc_mod < 0)) + ? (trunc_mod + input2) + : trunc_mod; +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FLOOR_MOD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h new file mode 100644 index 0000000..6cd8f66 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h @@ -0,0 +1,323 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FULLY_CONNECTED_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FULLY_CONNECTED_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +inline void FullyConnected( + const FullyConnectedParams& params, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& weights_shape, + const float* weights_data, const RuntimeShape& bias_shape, + const float* bias_data, const RuntimeShape& output_shape, + float* output_data) { + const float output_activation_min = params.float_activation_min; + const float output_activation_max = params.float_activation_max; + // TODO(b/62193649): This really should be: + // const int batches = ArraySize(output_dims, 1); + // but the current --variable_batch hack consists in overwriting the 3rd + // dimension with the runtime batch size, as we don't keep track for each + // array of which dimension is the batch dimension in it. + const int output_dims_count = output_shape.DimensionsCount(); + const int weights_dims_count = weights_shape.DimensionsCount(); + const int batches = FlatSizeSkipDim(output_shape, output_dims_count - 1); + const int output_depth = MatchingDim(weights_shape, weights_dims_count - 2, + output_shape, output_dims_count - 1); + const int accum_depth = weights_shape.Dims(weights_dims_count - 1); + for (int b = 0; b < batches; ++b) { + for (int out_c = 0; out_c < output_depth; ++out_c) { + float total = 0.f; + for (int d = 0; d < accum_depth; ++d) { + total += input_data[b * accum_depth + d] * + weights_data[out_c * accum_depth + d]; + } + float bias_value = 0.0f; + if (bias_data) { + bias_value = bias_data[out_c]; + } + output_data[out_c + output_depth * b] = ActivationFunctionWithMinMax( + total + bias_value, output_activation_min, output_activation_max); + } + } +} + +inline void FullyConnected( + const FullyConnectedParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& filter_shape, + const uint8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + uint8_t* output_data) { + const int32_t input_offset = params.input_offset; + const int32_t filter_offset = params.weights_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_GE(filter_shape.DimensionsCount(), 2); + TFLITE_DCHECK_GE(output_shape.DimensionsCount(), 1); + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + // TODO(b/62193649): This really should be: + // const int batches = ArraySize(output_dims, 1); + // but the current --variable_batch hack consists in overwriting the 3rd + // dimension with the runtime batch size, as we don't keep track for each + // array of which dimension is the batch dimension in it. + const int output_dim_count = output_shape.DimensionsCount(); + const int filter_dim_count = filter_shape.DimensionsCount(); + const int batches = FlatSizeSkipDim(output_shape, output_dim_count - 1); + const int output_depth = MatchingDim(filter_shape, filter_dim_count - 2, + output_shape, output_dim_count - 1); + const int accum_depth = filter_shape.Dims(filter_dim_count - 1); + for (int b = 0; b < batches; ++b) { + for (int out_c = 0; out_c < output_depth; ++out_c) { + int32_t acc = 0; + for (int d = 0; d < accum_depth; ++d) { + int32_t input_val = input_data[b * accum_depth + d]; + int32_t filter_val = filter_data[out_c * accum_depth + d]; + acc += (filter_val + filter_offset) * (input_val + input_offset); + } + if (bias_data) { + acc += bias_data[out_c]; + } + acc = MultiplyByQuantizedMultiplier(acc, output_multiplier, output_shift); + acc += output_offset; + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_data[out_c + output_depth * b] = static_cast(acc); + } + } +} + +inline void FullyConnected( + const FullyConnectedParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& filter_shape, + const uint8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + int16_t* output_data) { + const int32_t input_offset = params.input_offset; + const int32_t filter_offset = params.weights_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + TFLITE_DCHECK_EQ(output_offset, 0); + // TODO(b/62193649): This really should be: + // const int batches = ArraySize(output_dims, 1); + // but the current --variable_batch hack consists in overwriting the 3rd + // dimension with the runtime batch size, as we don't keep track for each + // array of which dimension is the batch dimension in it. + const int output_dim_count = output_shape.DimensionsCount(); + const int filter_dim_count = filter_shape.DimensionsCount(); + const int batches = FlatSizeSkipDim(output_shape, output_dim_count - 1); + const int output_depth = MatchingDim(filter_shape, filter_dim_count - 2, + output_shape, output_dim_count - 1); + const int accum_depth = filter_shape.Dims(filter_dim_count - 1); + for (int b = 0; b < batches; ++b) { + for (int out_c = 0; out_c < output_depth; ++out_c) { + // Internal accumulation. + // Initialize accumulator with the bias-value. + int32_t accum = bias_data[out_c]; + // Accumulation loop. + for (int d = 0; d < accum_depth; ++d) { + int16_t input_val = input_data[b * accum_depth + d] + input_offset; + int16_t filter_val = + filter_data[out_c * accum_depth + d] + filter_offset; + accum += filter_val * input_val; + } + // Down-scale the final int32_t accumulator to the scale used by our + // (16-bit, typically 3 integer bits) fixed-point format. The quantized + // multiplier and shift here have been pre-computed offline + // (e.g. by toco). + accum = + MultiplyByQuantizedMultiplier(accum, output_multiplier, output_shift); + // Saturate, cast to int16_t, and store to output array. + accum = std::max(accum, output_activation_min - output_offset); + accum = std::min(accum, output_activation_max - output_offset); + accum += output_offset; + output_data[out_c + output_depth * b] = accum; + } + } +} + +inline void ShuffledFullyConnected( + const FullyConnectedParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& weights_shape, + const uint8_t* shuffled_weights_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + int16_t* output_data, uint8_t* shuffled_input_workspace_data) { + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + + TFLITE_DCHECK_GE(input_shape.DimensionsCount(), 1); + TFLITE_DCHECK_GE(weights_shape.DimensionsCount(), 2); + TFLITE_DCHECK_GE(output_shape.DimensionsCount(), 1); + // TODO(b/62193649): This really should be: + // const int batches = ArraySize(output_dims, 1); + // but the current --variable_batch hack consists in overwriting the 3rd + // dimension with the runtime batch size, as we don't keep track for each + // array of which dimension is the batch dimension in it. + const int output_dim_count = output_shape.DimensionsCount(); + const int weights_dim_count = weights_shape.DimensionsCount(); + const int batches = FlatSizeSkipDim(output_shape, output_dim_count - 1); + const int output_depth = MatchingDim(weights_shape, weights_dim_count - 2, + output_shape, output_dim_count - 1); + const int accum_depth = weights_shape.Dims(weights_dim_count - 1); + TFLITE_DCHECK((accum_depth % 16) == 0); + TFLITE_DCHECK((output_depth % 4) == 0); + + // Shuffling and xoring of input activations into the workspace buffer + uint8_t* shuffled_input_workspace_ptr = shuffled_input_workspace_data; + if (batches == 1) { + for (int i = 0; i < accum_depth; i++) { + shuffled_input_workspace_data[i] = input_data[i] ^ 0x80; + } + } else if (batches == 4) { + for (int c = 0; c < accum_depth; c += 16) { + for (int b = 0; b < 4; b++) { + const uint8_t* src_data_ptr = input_data + b * accum_depth + c; + for (int j = 0; j < 16; j++) { + uint8_t src_val = *src_data_ptr++; + // Flip the sign bit, so that the kernel will only need to + // reinterpret these uint8_t values as int8_t, getting for free the + // subtraction of the zero_point value 128. + uint8_t dst_val = src_val ^ 0x80; + *shuffled_input_workspace_ptr++ = dst_val; + } + } + } + } else { + TFLITE_DCHECK(false); + return; + } + + // Actual computation + if (batches == 1) { + int16_t* output_ptr = output_data; + // Shuffled weights have had their sign bit (0x80) pre-flipped (xor'd) + // so that just reinterpreting them as int8_t values is equivalent to + // subtracting 128 from them, thus implementing for free the subtraction of + // the zero_point value 128. + const int8_t* shuffled_weights_ptr = + reinterpret_cast(shuffled_weights_data); + // Likewise, we preshuffled and pre-xored the input data above. + const int8_t* shuffled_input_data = + reinterpret_cast(shuffled_input_workspace_data); + for (int c = 0; c < output_depth; c += 4) { + // Internal accumulation. + // Initialize accumulator with the bias-value. + int32_t accum[4] = {0}; + // Accumulation loop. + for (int d = 0; d < accum_depth; d += 16) { + for (int i = 0; i < 4; i++) { + for (int j = 0; j < 16; j++) { + int8_t input_val = shuffled_input_data[d + j]; + int8_t weights_val = *shuffled_weights_ptr++; + accum[i] += weights_val * input_val; + } + } + } + for (int i = 0; i < 4; i++) { + // Add bias value + int32_t acc = accum[i] + bias_data[c + i]; + // Down-scale the final int32_t accumulator to the scale used by our + // (16-bit, typically 3 integer bits) fixed-point format. The quantized + // multiplier and shift here have been pre-computed offline + // (e.g. by toco). + acc = + MultiplyByQuantizedMultiplier(acc, output_multiplier, output_shift); + // Saturate, cast to int16_t, and store to output array. + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_ptr[c + i] = acc; + } + } + } else if (batches == 4) { + int16_t* output_ptr = output_data; + // Shuffled weights have had their sign bit (0x80) pre-flipped (xor'd) + // so that just reinterpreting them as int8_t values is equivalent to + // subtracting 128 from them, thus implementing for free the subtraction of + // the zero_point value 128. + const int8_t* shuffled_weights_ptr = + reinterpret_cast(shuffled_weights_data); + // Likewise, we preshuffled and pre-xored the input data above. + const int8_t* shuffled_input_data = + reinterpret_cast(shuffled_input_workspace_data); + for (int c = 0; c < output_depth; c += 4) { + const int8_t* shuffled_input_ptr = shuffled_input_data; + // Accumulation loop. + // Internal accumulation. + // Initialize accumulator with the bias-value. + int32_t accum[4][4]; + for (int i = 0; i < 4; i++) { + for (int b = 0; b < 4; b++) { + accum[i][b] = 0; + } + } + for (int d = 0; d < accum_depth; d += 16) { + for (int i = 0; i < 4; i++) { + for (int b = 0; b < 4; b++) { + for (int j = 0; j < 16; j++) { + int8_t input_val = shuffled_input_ptr[16 * b + j]; + int8_t weights_val = shuffled_weights_ptr[16 * i + j]; + accum[i][b] += weights_val * input_val; + } + } + } + shuffled_input_ptr += 64; + shuffled_weights_ptr += 64; + } + for (int i = 0; i < 4; i++) { + for (int b = 0; b < 4; b++) { + // Add bias value + int32_t acc = accum[i][b] + bias_data[c + i]; + // Down-scale the final int32_t accumulator to the scale used by our + // (16-bit, typically 3 integer bits) fixed-point format. The + // quantized multiplier and shift here have been pre-computed offline + // (e.g. by toco). + acc = MultiplyByQuantizedMultiplier(acc, output_multiplier, + output_shift); + // Saturate, cast to int16_t, and store to output array. + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_ptr[b * output_depth + c + i] = acc; + } + } + } + } else { + TFLITE_DCHECK(false); + return; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_FULLY_CONNECTED_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/hard_swish.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/hard_swish.h new file mode 100644 index 0000000..c427205 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/hard_swish.h @@ -0,0 +1,168 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_HARD_SWISH_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_HARD_SWISH_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +inline int16_t SaturatingLeftShift(int16_t value, int amount) { + int64_t result = static_cast(value) * (1 << amount); + result = std::min(result, std::numeric_limits::max()); + result = std::max(result, std::numeric_limits::min()); + return result; +} + +// Similar to ARM instruction SQDMULH. +// Similar to gemmlowp::SaturatingRoundingDoublingHighMul except +// rounding to zero instead of to nearest (SQRDMULH). +inline std::int16_t SaturatingDoublingHighMul(std::int16_t a, std::int16_t b) { + bool overflow = a == b && a == std::numeric_limits::min(); + std::int32_t a_32(a); + std::int32_t b_32(b); + std::int32_t ab_32 = a_32 * b_32; + std::int16_t ab_x2_high16 = static_cast((ab_32) / (1 << 15)); + return overflow ? std::numeric_limits::max() : ab_x2_high16; +} + +template +inline void HardSwish(const RuntimeShape& input_shape, const T* input_data, + const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("ReferenceHardSwish/Float"); + auto matching_size = MatchingFlatSize(input_shape, output_shape); + const T* in_end = input_data + matching_size; + for (; input_data < in_end; input_data++, output_data++) { + const float in = *input_data; + *output_data = + in * std::min(static_cast(6), std::max(static_cast(0), in + 3)) / + 6; + } +} + +template +inline void HardSwish(const HardSwishParams& params, + const RuntimeShape& input_shape, const T* input_data, + const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("ReferenceHardSwish/Quantized"); + + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; i++) { + const int16_t input_value = input_data[i] - params.input_zero_point; + // Left-shift as much as we can without overflow/saturation to put + // significant bits in the high bits of our 16-bit fixedpoint values, so + // that fixed-point approximate computations below are as accurate as + // possible. + const int16_t input_value_on_hires_input_scale = input_value * (1 << 7); + // Compute the input value on essentially the output scale, just not + // right-shifted yet. This is the value that we'll use in the (x >= +3) + // case, and that in the general case we'll multiply against the "relu-ish" + // fixed-point multiplier in [0, 1]. + const int16_t input_value_on_preshift_output_scale = + gemmlowp::SaturatingRoundingDoublingHighMul( + input_value_on_hires_input_scale, + params.output_multiplier_fixedpoint_int16); + // Now compute the "relu-ish multiplier". In the (-3 <= x <= +3) case, that + // is just an affine rescaling of x from [-3, 3] to [0, 1]. In the general + // case, it is just that plus saturation at the boundaries of [-3, 3]. + // First, we rescale from [-3, 3] to [-1, 1], saturating. + // That is done by rescaling the input value with a fixed-point multiplier + // (reluish_multiplier_fixedpoint) and bit-shift such that we represent + // that input value on the scale where the real value 3.0f is represented + // by the quantized value 32768. (+32768 is actually not representable as + // int16_t, so this saturates at +32767, and that is seen empirically to be + // a negligible contribution to numerical error/bias). + // + // This code is careful to correctly implement any magnitude of multiplier, + // involving either a right shift or a left shift, with correct saturation + // behavior in the left-shift case. This forces this code to be more + // complicated, but is necessary for real applications: a partially + // trained quantized MobileNet v3-small model that motivated this code + // exhibits some large [min, max] range boundaries, of the order of + // magnitude of 10 or 100 depending on layers. + // + // The next few lines are basically just an ordinary + // MultiplyByQuantizedMultiplier, except that we are more careful here + // about the fine details of saturation when left-shifting, because here + // overflow in left-shift is a common case, not an anomaly as + // MultiplyByQuantizedMultiplier assumes. + int16_t reluish_value = input_value_on_hires_input_scale; + // Shift left, saturating, as much as we can while ensuring that this + // saturation will not contribute to the result. That is, left shift amount + // reduced by 1. + if (params.reluish_multiplier_exponent > 0) { + reluish_value = SaturatingLeftShift( + reluish_value, params.reluish_multiplier_exponent - 1); + } + // Apply the fixed-point multiplier, dividing the value by a divisor + // ranging in [1, 2]. + reluish_value = gemmlowp::SaturatingRoundingDoublingHighMul( + reluish_value, params.reluish_multiplier_fixedpoint_int16); + // Apply the last bit of left-shift. Thus, in the left-shifting case, if + // any saturation affects the result, it is happening here --- any + // saturation having occurred above is overwritten here, not affecting the + // result. + if (params.reluish_multiplier_exponent > 0) { + reluish_value = SaturatingLeftShift(reluish_value, 1); + } + // Shift right, in the right-shifting case. + if (params.reluish_multiplier_exponent < 0) { + reluish_value = gemmlowp::RoundingDivideByPOT( + reluish_value, -params.reluish_multiplier_exponent); + } + // At this point we have rescaled the value into a 16bit fixedpoint + // reluish_value in [-1, 1]. + // We now convert that to a 16bit fixedpoint value in [0, 1]. + reluish_value = (reluish_value + (1 << 15)) >> 1; + // Use of SaturatingDoublingHighMul here is important to cancel the biases + // from the above SaturatingRoundingDoublingHighMul. + // + // On a partially trained MobileNet-v3-small, + // + // | bias on | ImageNet + // | quantized | Top-1 + // Operation used here | values | accuracy (50k) + // --------------------------------------+------------+----------- + // SaturatingDoublingHighMul | -0.0024 | 58.920 + // SaturatingRoundingDoublingHighMul | -0.0067 | 58.064 + // + // In activations_test, this is covered by this testcase: + // QuantizedActivationsOpTest.HardSwishBias + // + const int16_t preshift_output_value = SaturatingDoublingHighMul( + reluish_value, input_value_on_preshift_output_scale); + // We were so far operating on the pre-shift output scale. Now we finally + // apply that output shift, arriving at the final output scale. + int16_t output_value = gemmlowp::RoundingDivideByPOT( + preshift_output_value, -params.output_multiplier_exponent); + output_value += params.output_zero_point; + output_value = + std::min(output_value, std::numeric_limits::max()); + output_value = + std::max(output_value, std::numeric_limits::min()); + output_data[i] = output_value; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_HARD_SWISH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h new file mode 100644 index 0000000..12064e3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h @@ -0,0 +1,145 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_ADD_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_ADD_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_integer_ops { + +inline void CheckArithmeticParams(const ArithmeticParams& params) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + // Input offset is negative input zero point. Activation tensors are + // asymmetric quantized so they span the full int8 range. + TFLITE_DCHECK_GE(-params.input1_offset, std::numeric_limits::min()); + TFLITE_DCHECK_GE(-params.input2_offset, std::numeric_limits::min()); + TFLITE_DCHECK_LE(-params.input1_offset, std::numeric_limits::max()); + TFLITE_DCHECK_LE(-params.input2_offset, std::numeric_limits::max()); +} + +inline void ElementWise( + int size, const ArithmeticParams& params, const int8_t* input1_data, + const int8_t* input2_data, int8_t* output_data, + void (*check_arithmetic_params)(const ArithmeticParams&), + int8_t (*binary_func)(int8_t, int8_t, const ArithmeticParams&)) { + CheckArithmeticParams(params); + for (int i = 0; i < size; ++i) { + output_data[i] = binary_func(input1_data[i], input2_data[i], params); + } +} + +inline void BroadcastBinaryFunction4DSlow( + const ArithmeticParams& params, const RuntimeShape& input1_shape, + const int8_t* input1_data, const RuntimeShape& input2_shape, + const int8_t* input2_data, const RuntimeShape& output_shape, + int8_t* output_data, + void (*check_arithmetic_params)(const ArithmeticParams&), + int8_t (*binary_func)(int8_t, int8_t, const ArithmeticParams&)) { + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(4, output_shape); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + for (int b = 0; b < extended_output_shape.Dims(0); ++b) { + for (int y = 0; y < extended_output_shape.Dims(1); ++y) { + for (int x = 0; x < extended_output_shape.Dims(2); ++x) { + for (int c = 0; c < extended_output_shape.Dims(3); ++c) { + output_data[Offset(extended_output_shape, b, y, x, c)] = binary_func( + input1_data[SubscriptToIndex(desc1, b, y, x, c)], + input2_data[SubscriptToIndex(desc2, b, y, x, c)], params); + } + } + } + } +} + +inline int8_t AddFunc(int8_t x, int8_t y, const ArithmeticParams& params) { + const int32_t input1_val = params.input1_offset + x; + const int32_t input2_val = params.input2_offset + y; + const int32_t shifted_input1_val = input1_val * (1 << params.left_shift); + const int32_t shifted_input2_val = input2_val * (1 << params.left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, params.input1_multiplier, params.input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, params.input2_multiplier, params.input2_shift); + const int32_t raw_sum = scaled_input1_val + scaled_input2_val; + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + raw_sum, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + return static_cast(clamped_output); +} + +// Element-wise add that can often be used for inner loop of broadcast add as +// well as the non-broadcast add. +inline void AddElementwise(int size, const ArithmeticParams& params, + const int8_t* input1_data, const int8_t* input2_data, + int8_t* output_data) { + ElementWise(size, params, input1_data, input2_data, output_data, + CheckArithmeticParams, AddFunc); +} + +inline void Add(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const int8_t* input1_data, + const RuntimeShape& input2_shape, const int8_t* input2_data, + const RuntimeShape& output_shape, int8_t* output_data) { + CheckArithmeticParams(params); + + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + AddElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +inline void BroadcastAdd4DSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const int8_t* input1_data, + const RuntimeShape& input2_shape, + const int8_t* input2_data, + const RuntimeShape& output_shape, + int8_t* output_data) { + BroadcastBinaryFunction4DSlow(params, input1_shape, input1_data, input2_shape, + input2_data, output_shape, output_data, + CheckArithmeticParams, AddFunc); +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_ADD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h new file mode 100644 index 0000000..3b9adcb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h @@ -0,0 +1,239 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_CONV_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_CONV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +// Fixed-point per-channel-quantization convolution reference kernel. +inline void ConvPerChannel( + const ConvParams& params, const int32_t* output_multiplier, + const int32_t* output_shift, const RuntimeShape& input_shape, + const int8_t* input_data, const RuntimeShape& filter_shape, + const int8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + int8_t* output_data) { + // Get parameters. + const int32_t input_offset = params.input_offset; // r = s(q - Z) + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int32_t output_offset = params.output_offset; + + // Set min and max value of the output. + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + + // Consistency check. + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = input_shape.Dims(3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + // Check dimensions of the tensors. + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int filter_input_depth = filter_shape.Dims(3); + const int groups = input_depth / filter_input_depth; + TFLITE_DCHECK_EQ(input_depth % filter_input_depth, 0); + const int filters_per_group = output_depth / groups; + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + const int in_y_origin = (out_y * stride_height) - pad_height; + for (int out_x = 0; out_x < output_width; ++out_x) { + const int in_x_origin = (out_x * stride_width) - pad_width; + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + auto group = out_channel / filters_per_group; + int32_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + const int in_y = in_y_origin + dilation_height_factor * filter_y; + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + + if (!is_point_inside_image) { + continue; + } + + for (int in_channel = 0; in_channel < filter_input_depth; + ++in_channel) { + int32_t input_val = + input_data[Offset(input_shape, batch, in_y, in_x, + in_channel + group * filter_input_depth)]; + int32_t filter_val = filter_data[Offset( + filter_shape, out_channel, filter_y, filter_x, in_channel)]; + // Accumulate with 32 bits accumulator. + // In the nudging process during model quantization, we force + // real value of 0.0 be represented by a quantized value. This + // guarantees that the input_offset is a int8_t, even though + // it is represented using int32_t. int32_t += int8_t * + // (int8_t - int8_t) so the highest value we can get from each + // accumulation is [-127, 127] * ([-128, 127] - + // [-128, 127]), which is [-32512, 32512]. log2(32512) + // = 14.98, which means we can accumulate at least 2^16 + // multiplications without overflow. The accumulator is + // applied to a filter so the accumulation logic will hold as + // long as the filter size (filter_y * filter_x * in_channel) + // does not exceed 2^16, which is the case in all the models + // we have seen so far. + // TODO(b/174275578): Add a check to make sure the + // accumulator depth is smaller than 2^16. + acc += filter_val * (input_val + input_offset); + } + } + } + + if (bias_data) { + acc += bias_data[out_channel]; + } + acc = MultiplyByQuantizedMultiplier( + acc, output_multiplier[out_channel], output_shift[out_channel]); + acc += output_offset; + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + static_cast(acc); + } + } + } + } +} + + +// Fixed-point per-channel-quantization convolution reference kernel. +// 16-bit data and 8-bit filter +template +inline void ConvPerChannel( + const ConvParams& params, const int32_t* output_multiplier, + const int32_t* output_shift, const RuntimeShape& input_shape, + const int16_t* input_data, const RuntimeShape& filter_shape, + const int8_t* filter_data, const RuntimeShape& bias_shape, + const AccumScalar* bias_data, const RuntimeShape& output_shape, + int16_t* output_data) { + // Get parameters. + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + + // Set min and max value of the output. + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + + // Consistency check. + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = input_shape.Dims(3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + // Check dimensions of the tensors. + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int filter_input_depth = filter_shape.Dims(3); + const int groups = input_depth / filter_input_depth; + TFLITE_DCHECK_EQ(input_depth % filter_input_depth, 0); + const int filters_per_group = output_depth / groups; + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + const int in_y_origin = (out_y * stride_height) - pad_height; + for (int out_x = 0; out_x < output_width; ++out_x) { + const int in_x_origin = (out_x * stride_width) - pad_width; + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + auto group = out_channel / filters_per_group; + AccumScalar acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + const int in_y = in_y_origin + dilation_height_factor * filter_y; + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + + if (!is_point_inside_image) { + continue; + } + + for (int in_channel = 0; in_channel < filter_input_depth; + ++in_channel) { + int32_t input_val = + input_data[Offset(input_shape, batch, in_y, in_x, + in_channel + group * filter_input_depth)]; + int32_t filter_val = filter_data[Offset( + filter_shape, out_channel, filter_y, filter_x, in_channel)]; + // Accumulate with 64 bits accumulator. + // int64_t += int8_t * int16_t so the highest value we can + // get from each accumulation is [-127, 127] * ([-32768, + // 32767] - + // [-32768, 32767]), which is [-8322945, 8322945]. + // log2(8322945) = 22.99. + acc += filter_val * input_val; + } + } + } + if (bias_data) { + acc += bias_data[out_channel]; + } + int32_t scaled_acc = MultiplyByQuantizedMultiplier( + acc, output_multiplier[out_channel], output_shift[out_channel]); + scaled_acc = std::max(scaled_acc, output_activation_min); + scaled_acc = std::min(scaled_acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + static_cast(scaled_acc); + } + } + } + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_CONV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h new file mode 100644 index 0000000..95e7337 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h @@ -0,0 +1,291 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_DEPTHWISE_CONV_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_DEPTHWISE_CONV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { +inline void DepthwiseConvPerChannel( + const DepthwiseParams& params, const int32_t* output_multiplier, + const int32_t* output_shift, const RuntimeShape& input_shape, + const int8_t* input_data, const RuntimeShape& filter_shape, + const int8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + int8_t* output_data) { + // Get parameters. + // TODO(b/141565753): Re-introduce ScopedProfilingLabel on Micro. + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int depth_multiplier = params.depth_multiplier; + const int32_t input_offset = params.input_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + + // Check dimensions of the tensors. + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int input_depth = input_shape.Dims(3); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + TFLITE_DCHECK_EQ(output_depth, input_depth * depth_multiplier); + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + for (int m = 0; m < depth_multiplier; ++m) { + const int output_channel = m + in_channel * depth_multiplier; + const int in_x_origin = (out_x * stride_width) - pad_width; + const int in_y_origin = (out_y * stride_height) - pad_height; + int32_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + const int in_y = + in_y_origin + dilation_height_factor * filter_y; + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + if (is_point_inside_image) { + int32_t input_val = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + int32_t filter_val = filter_data[Offset( + filter_shape, 0, filter_y, filter_x, output_channel)]; + // Accumulate with 32 bits accumulator. + // In the nudging process during model quantization, we force + // real value of 0.0 be represented by a quantized value. This + // guarantees that the input_offset is a int8_t, even though + // it is represented using int32_t. int32_t += int8_t * + // (int8_t - int8_t) so the highest value we can get from each + // accumulation is [-127, 127] * ([-128, 127] - + // [-128, 127]), which is [-32512, 32512]. log2(32512) + // = 14.98, which means we can accumulate at least 2^16 + // multiplications without overflow. The accumulator is + // applied to a filter so the accumulation logic will hold as + // long as the filter size (filter_y * filter_x * in_channel) + // does not exceed 2^16, which is the case in all the models + // we have seen so far. + // TODO(b/174275578): Add a check to make sure the + // accumulator depth is smaller than 2^16. + acc += filter_val * (input_val + input_offset); + } + } + } + if (bias_data) { + acc += bias_data[output_channel]; + } + acc = MultiplyByQuantizedMultiplier( + acc, output_multiplier[output_channel], + output_shift[output_channel]); + acc += output_offset; + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, + output_channel)] = static_cast(acc); + } + } + } + } + } +} + +inline void DepthwiseConvPerChannel( + const DepthwiseParams& params, const int32_t* output_multiplier, + const int32_t* output_shift, const RuntimeShape& input_shape, + const int16_t* input_data, const RuntimeShape& filter_shape, + const int8_t* filter_data, const RuntimeShape& bias_shape, + const std::int64_t* bias_data, const RuntimeShape& output_shape, + int16_t* output_data) { + // Get parameters. + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int depth_multiplier = params.depth_multiplier; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + + // Check dimensions of the tensors. + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int input_depth = input_shape.Dims(3); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + TFLITE_DCHECK_EQ(output_depth, input_depth * depth_multiplier); + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + for (int m = 0; m < depth_multiplier; ++m) { + const int output_channel = m + in_channel * depth_multiplier; + const int in_x_origin = (out_x * stride_width) - pad_width; + const int in_y_origin = (out_y * stride_height) - pad_height; + std::int64_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + const int in_y = + in_y_origin + dilation_height_factor * filter_y; + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + if (is_point_inside_image) { + int32_t input_val = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + int32_t filter_val = filter_data[Offset( + filter_shape, 0, filter_y, filter_x, output_channel)]; + // Accumulate with 64 bits accumulator. + // We assume maximum of 2^16 accumulations as with the 8-bit + // case so actually the value in the accumulator should not + // exceed 40 bits + acc += static_cast(filter_val) * + static_cast(input_val); + } + } + } + if (bias_data) { + acc += bias_data[output_channel]; + } + int32_t scaled_acc = MultiplyByQuantizedMultiplier( + acc, output_multiplier[output_channel], + output_shift[output_channel]); + scaled_acc = std::max(scaled_acc, output_activation_min); + scaled_acc = std::min(scaled_acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, + output_channel)] = + static_cast(scaled_acc); + } + } + } + } + } +} + +inline void DepthwiseConvHybridPerChannel( + const DepthwiseParams& params, float* scaling_factors_ptr, + const RuntimeShape& input_shape, const int8_t* input_data, + const RuntimeShape& filter_shape, const int8_t* filter_data, + const RuntimeShape& bias_shape, const float* bias_data, + const RuntimeShape& output_shape, float* output_data, + const float* per_channel_scale, int32_t* input_offset) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + const int depth_multiplier = params.depth_multiplier; + const float output_activation_min = params.float_activation_min; + const float output_activation_max = params.float_activation_max; + // Check dimensions of the tensors. + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int input_depth = input_shape.Dims(3); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int bias_depth = bias_shape.FlatSize(); + TFLITE_DCHECK_EQ(output_depth, input_depth * depth_multiplier); + TFLITE_DCHECK_EQ(bias_depth, output_depth); + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + for (int m = 0; m < depth_multiplier; ++m) { + const int output_channel = m + in_channel * depth_multiplier; + const int in_x_origin = (out_x * stride_width) - pad_width; + const int in_y_origin = (out_y * stride_height) - pad_height; + int32_t acc = 0; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + const int in_x = in_x_origin + dilation_width_factor * filter_x; + const int in_y = + in_y_origin + dilation_height_factor * filter_y; + // Zero padding by omitting the areas outside the image. + const bool is_point_inside_image = + (in_x >= 0) && (in_x < input_width) && (in_y >= 0) && + (in_y < input_height); + if (is_point_inside_image) { + int32_t input_val = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + int32_t filter_val = filter_data[Offset( + filter_shape, 0, filter_y, filter_x, output_channel)]; + acc += filter_val * (input_val - input_offset[batch]); + } + } + } + float acc_float = static_cast(acc); + acc_float *= + per_channel_scale[output_channel] * scaling_factors_ptr[batch]; + if (bias_data && output_channel < bias_depth) { + acc_float += bias_data[output_channel]; + } + output_data[Offset(output_shape, batch, out_y, out_x, + output_channel)] = + ActivationFunctionWithMinMax(acc_float, output_activation_min, + output_activation_max); + } + } + } + } + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_DEPTHWISE_CONV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h new file mode 100644 index 0000000..4be7987 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h @@ -0,0 +1,126 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_FULLY_CONNECTED_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_FULLY_CONNECTED_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +// For per-channel functions, since it is defined in quantization spec that +// weights are symmetric +// (https://www.tensorflow.org/lite/performance/quantization_spec#symmetric_vs_asymmetric), +// zero_point (params.weights_offset) is always 0. +// However, for per-tensor functions, params.weights_offset is still applied for +// backward compatibility. +template +void FullyConnectedPerChannel( + const FullyConnectedParams& params, const int32_t* output_multiplier, + const int* output_shift, const RuntimeShape& input_shape, + const InputType* input_data, const RuntimeShape& filter_shape, + const WeightType* filter_data, const RuntimeShape& bias_shape, + const BiasType* bias_data, const RuntimeShape& output_shape, + OutputType* output_data) { + const int32_t input_offset = params.input_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_GE(filter_shape.DimensionsCount(), 2); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 2); + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + const int filter_dim_count = filter_shape.DimensionsCount(); + const int batches = output_shape.Dims(0); + const int output_depth = output_shape.Dims(1); + TFLITE_DCHECK_LE(output_depth, filter_shape.Dims(filter_dim_count - 2)); + const int accum_depth = filter_shape.Dims(filter_dim_count - 1); + for (int b = 0; b < batches; ++b) { + for (int out_c = 0; out_c < output_depth; ++out_c) { + BiasType acc = 0; + for (int d = 0; d < accum_depth; ++d) { + int32_t input_val = input_data[b * accum_depth + d]; + int32_t filter_val = filter_data[out_c * accum_depth + d]; + acc += filter_val * (input_val + input_offset); + } + if (bias_data) { + acc += bias_data[out_c]; + } + int32_t acc_scaled = MultiplyByQuantizedMultiplier( + acc, output_multiplier[out_c], output_shift[out_c]); + acc_scaled += output_offset; + acc_scaled = std::max(acc_scaled, output_activation_min); + acc_scaled = std::min(acc_scaled, output_activation_max); + output_data[out_c + output_depth * b] = + static_cast(acc_scaled); + } + } +} + +template +void FullyConnected(const FullyConnectedParams& params, + const RuntimeShape& input_shape, + const InputType* input_data, + const RuntimeShape& filter_shape, + const WeightType* filter_data, + const RuntimeShape& bias_shape, const BiasType* bias_data, + const RuntimeShape& output_shape, OutputType* output_data) { + const int32_t input_offset = params.input_offset; + const int32_t filter_offset = params.weights_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_GE(filter_shape.DimensionsCount(), 2); + TFLITE_DCHECK_GE(output_shape.DimensionsCount(), 1); + + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + const int filter_dim_count = filter_shape.DimensionsCount(); + const int output_dim_count = output_shape.DimensionsCount(); + const int batches = FlatSizeSkipDim(output_shape, output_dim_count - 1); + const int output_depth = output_shape.Dims(output_dim_count - 1); + TFLITE_DCHECK_LE(output_depth, filter_shape.Dims(filter_dim_count - 2)); + const int accum_depth = filter_shape.Dims(filter_dim_count - 1); + for (int b = 0; b < batches; ++b) { + for (int out_c = 0; out_c < output_depth; ++out_c) { + BiasType acc = 0; + for (int d = 0; d < accum_depth; ++d) { + int32_t input_val = input_data[b * accum_depth + d]; + int32_t filter_val = filter_data[out_c * accum_depth + d]; + acc += (filter_val + filter_offset) * (input_val + input_offset); + } + if (bias_data) { + acc += bias_data[out_c]; + } + int32_t acc_scaled = + MultiplyByQuantizedMultiplier(acc, output_multiplier, output_shift); + acc_scaled += output_offset; + acc_scaled = std::max(acc_scaled, output_activation_min); + acc_scaled = std::min(acc_scaled, output_activation_max); + output_data[out_c + output_depth * b] = + static_cast(acc_scaled); + } + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_FULLY_CONNECTED_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/l2normalization.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/l2normalization.h new file mode 100644 index 0000000..582713b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/l2normalization.h @@ -0,0 +1,67 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_L2NORMALIZATION_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_L2NORMALIZATION_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +inline void L2Normalization(int32_t input_zero_point, int32_t outer_size, + int32_t depth, const int8_t* input_data, + int8_t* output_data) { + static constexpr int8_t kMinInt8 = std::numeric_limits::min(); + static constexpr int8_t kMaxInt8 = std::numeric_limits::max(); + // The output scale must be in sync with Prepare(). + // Output is in 1/128 scale so the actual output range is nudged from [-1, 1] + // to [-1, 127/128]. + static constexpr int32_t kOutputScale = 7; + for (int outer_index = 0; outer_index < outer_size; ++outer_index) { + // int32_t = (int8_t - int8_t) ^ 2. + // ([-128, 127] - [-128, 127]) ^ 2 = [0, (2^8 - 1)^2] so the accumulator is + // safe from overflowing in at least 2^16 steps. + int32_t acc = 0; + for (int inner_index = 0; inner_index < depth; ++inner_index) { + int32_t input = + input_data[depth * outer_index + inner_index] - input_zero_point; + acc += input * input; + } + int32_t inv_l2norm_multiplier; + int inv_l2norm_shift; + GetInvSqrtQuantizedMultiplierExp(acc, kReverseShift, &inv_l2norm_multiplier, + &inv_l2norm_shift); + + for (int inner_index = 0; inner_index < depth; ++inner_index) { + int32_t input = + input_data[depth * outer_index + inner_index] - input_zero_point; + + // Rescale and downcast. Rescale is folded into the division. + int32_t output_in_q24 = MultiplyByQuantizedMultiplier( + input, inv_l2norm_multiplier, inv_l2norm_shift + kOutputScale); + output_in_q24 = + std::min(static_cast(kMaxInt8), + std::max(static_cast(kMinInt8), output_in_q24)); + output_data[depth * outer_index + inner_index] = + static_cast(output_in_q24); + } + } +} +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_L2NORMALIZATION_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/logistic.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/logistic.h new file mode 100644 index 0000000..2119103 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/logistic.h @@ -0,0 +1,121 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_LOGISTIC_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_LOGISTIC_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +inline void Logistic(int32_t input_zero_point, int32_t input_range_radius, + int32_t input_multiplier, int32_t input_left_shift, + int32_t input_size, const int8_t* input_data, + int8_t* output_data) { + // Integer bits must be in sync with Prepare() function. + static constexpr int32_t kInputIntegerBits = 4; + static constexpr int32_t kOutputIntegerBits = 8; + static constexpr int8_t kMinInt8 = std::numeric_limits::min(); + static constexpr int8_t kMaxInt8 = std::numeric_limits::max(); + static constexpr int32_t kOutputZeroPoint = -128; + + for (int i = 0; i < input_size; ++i) { + const int32_t input = + static_cast(input_data[i]) - input_zero_point; + if (input <= -input_range_radius) { + output_data[i] = kMinInt8; + } else if (input >= input_range_radius) { + output_data[i] = kMaxInt8; + } else { + const int32_t input_in_q4 = MultiplyByQuantizedMultiplier( + input, input_multiplier, input_left_shift); + using FixedPoint4 = gemmlowp::FixedPoint; + const int32_t output_in_q0 = + gemmlowp::logistic(FixedPoint4::FromRaw(input_in_q4)).raw(); + + // Rescale and downcast. + using gemmlowp::RoundingDivideByPOT; + int32_t output_in_q23 = + RoundingDivideByPOT(output_in_q0, 31 - kOutputIntegerBits); + output_in_q23 = std::min(std::max(output_in_q23 + kOutputZeroPoint, + static_cast(kMinInt8)), + static_cast(kMaxInt8)); + output_data[i] = static_cast(output_in_q23); + } + } +} + +inline void Logistic(int32_t input_multiplier, int32_t input_left_shift, + int32_t input_size, const int16_t* ptr_input_data, + int16_t* ptr_output_data) { + // We use the LUT for sigmoid and take into account, that + // tanh(x) = 2*sigmoid(2*x) - 1 + + // We scale by 3/4 to expand range [-8,8]->[-10.7,10.7]. + // In case of general parameter scale, multiplier 3 is taken into account + // in TanhPrepare function and it is included in + // input_multiplier already. + + TFLITE_DCHECK_GE(input_left_shift, 0); + if (input_multiplier == 0) { // power of two case + input_multiplier = 3 << input_left_shift; + input_left_shift = 0; + } + + int32_t round = (input_left_shift > 0) ? 1 << (input_left_shift - 1) : 0; + + for (int i = 0; i < input_size; ++i, ptr_input_data++, ptr_output_data++) { + int32_t input_data = + ((*ptr_input_data) * input_multiplier + round) >> input_left_shift; + + // We do interpolation on unsigned values. + uint32_t abs_input_data = abs(input_data); + + // We divide by 2 power of 9, because + // we need to divide by 2 in power of 7 for + // the input conversion + 1/4 from the scale above. + + // Define uh as uint32_t type not to make this function overflow. + uint32_t uh = abs_input_data >> 9; + uint32_t result; + + if (uh >= 255) { + // Saturate to maximum. + result = 0x7FFF << 10; + } else { + uint32_t ua = sigmoid_table_uint16[uh]; + uint32_t ub = sigmoid_table_uint16[uh + 1]; + uint32_t ut = abs_input_data & 0x1ff; + // Interpolation is done using the fractional bit. + result = (ua << 9) + ut * (ub - ua); + } + + result = (input_data >= 0) ? (result + (1 << 9)) + : ((1 << (16 + 9)) - result + (1 << 9) - 1); + + // Back to 16-bit. + result >>= 10; + + *ptr_output_data = result; + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_LOGISTIC_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mean.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mean.h new file mode 100644 index 0000000..0ba0f66 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mean.h @@ -0,0 +1,79 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_MEAN_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_MEAN_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +template +inline void Mean(const tflite::MeanParams& op_params, int32_t multiplier, + int32_t shift, const RuntimeShape& unextended_input_shape, + const integer_type* input_data, int32_t input_zero_point, + const RuntimeShape& unextended_output_shape, + integer_type* output_data, int32_t output_zero_point) { + // Current implementation only supports dimension equals 4 and simultaneous + // reduction over width and height. + TFLITE_CHECK_EQ(unextended_input_shape.DimensionsCount(), 4); + TFLITE_CHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + const int output_batch = output_shape.Dims(0); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int output_depth = output_shape.Dims(3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int num_elements_in_axis = input_width * input_height; + + TFLITE_CHECK_EQ(op_params.axis_count, 2); + TFLITE_CHECK((op_params.axis[0] == 1 && op_params.axis[1] == 2) || + (op_params.axis[0] == 2 && op_params.axis[1] == 1)); + TFLITE_CHECK_EQ(output_height, 1); + TFLITE_CHECK_EQ(output_width, 1); + + static constexpr int32_t kMinInt = std::numeric_limits::min(); + static constexpr int32_t kMaxInt = std::numeric_limits::max(); + + for (int out_b = 0; out_b < output_batch; ++out_b) { + for (int out_d = 0; out_d < output_depth; ++out_d) { + int32_t acc = 0; + for (int in_h = 0; in_h < input_height; ++in_h) { + for (int in_w = 0; in_w < input_width; ++in_w) { + acc += input_data[Offset(input_shape, out_b, in_h, in_w, out_d)] - + input_zero_point; + } + } + acc = MultiplyByQuantizedMultiplier(acc, multiplier, shift); + acc = acc > 0 ? (acc + num_elements_in_axis / 2) / num_elements_in_axis + : (acc - num_elements_in_axis / 2) / num_elements_in_axis; + acc += output_zero_point; + acc = std::min(std::max(acc, kMinInt), kMaxInt); + output_data[Offset(output_shape, out_b, 0, 0, out_d)] = + static_cast(acc); + } + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_MEAN_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h new file mode 100644 index 0000000..168e3ae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h @@ -0,0 +1,133 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_MUL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_MUL_H_ + +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +template +void MulElementwise(int size, const ArithmeticParams& params, + const InputType* input1_data, const InputType* input2_data, + OutputType* output_data) { + for (int i = 0; i < size; ++i) { + const int32_t input1_val = params.input1_offset + input1_data[i]; + const int32_t input2_val = params.input2_offset + input2_data[i]; + const int32_t unclamped_result = + params.output_offset + + MultiplyByQuantizedMultiplier(input1_val * input2_val, + params.output_multiplier, + params.output_shift); + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, unclamped_result)); + output_data[i] = static_cast(clamped_output); + } +} + +template +inline void Mul(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + ruy::profiler::ScopeLabel label("Mul/8bit"); + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + MulElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +// Mul with 16 bit inputs and int8_t outputs. +inline void Mul(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const int16_t* input1_data, + const RuntimeShape& input2_shape, const int16_t* input2_data, + const RuntimeShape& output_shape, int8_t* output_data) { + ruy::profiler::ScopeLabel label("Mul/Int16Int8"); + int32_t output_offset = params.output_offset; + int32_t output_activation_min = params.quantized_activation_min; + int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + for (int i = 0; i < flat_size; i++) { + // F0 uses 0 integer bits, range [-1, 1]. + using F0 = gemmlowp::FixedPoint; + + F0 unclamped_result = + F0::FromRaw(input1_data[i]) * F0::FromRaw(input2_data[i]); + int16_t rescaled_result = + gemmlowp::RoundingDivideByPOT(unclamped_result.raw(), 8); + int16_t clamped_result = std::min( + output_activation_max - output_offset, rescaled_result); + clamped_result = std::max(output_activation_min - output_offset, + clamped_result); + output_data[i] = output_offset + clamped_result; + } +} + +template +inline void BroadcastMul4DSlow( + const ArithmeticParams& params, const RuntimeShape& input1_shape, + const T* input1_data, const RuntimeShape& input2_shape, + const T* input2_data, const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("BroadcastMul4DSlow"); + + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + // The input shapes are extended as part of NdArrayDesc initialization. + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(4, output_shape); + + for (int b = 0; b < extended_output_shape.Dims(0); ++b) { + for (int y = 0; y < extended_output_shape.Dims(1); ++y) { + for (int x = 0; x < extended_output_shape.Dims(2); ++x) { + for (int c = 0; c < extended_output_shape.Dims(3); ++c) { + const int32_t input1_val = + params.input1_offset + + input1_data[SubscriptToIndex(desc1, b, y, x, c)]; + const int32_t input2_val = + params.input2_offset + + input2_data[SubscriptToIndex(desc2, b, y, x, c)]; + const int32_t unclamped_result = + params.output_offset + + MultiplyByQuantizedMultiplier(input1_val * input2_val, + params.output_multiplier, + params.output_shift); + const int32_t clamped_output = std::min( + params.quantized_activation_max, + std::max(params.quantized_activation_min, unclamped_result)); + output_data[Offset(extended_output_shape, b, y, x, c)] = + static_cast(clamped_output); + } + } + } + } +} + +} // namespace reference_integer_ops +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_MUL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/pooling.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/pooling.h new file mode 100644 index 0000000..ee026fd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/pooling.h @@ -0,0 +1,264 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_POOLING_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_POOLING_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +inline bool AveragePool(const PoolParams& params, + const RuntimeShape& input_shape, + const int8_t* input_data, + const RuntimeShape& output_shape, int8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + int32_t acc = 0; + int filter_count = 0; + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + acc += + input_data[Offset(input_shape, batch, in_y, in_x, channel)]; + filter_count++; + } + } + if (filter_count == 0) return false; + // Round to the closest integer value. + acc = acc > 0 ? (acc + filter_count / 2) / filter_count + : (acc - filter_count / 2) / filter_count; + acc = std::max(acc, params.quantized_activation_min); + acc = std::min(acc, params.quantized_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + static_cast(acc); + } + } + } + } + return true; +} + +inline void MaxPool(const PoolParams& params, const RuntimeShape& input_shape, + const int8_t* input_data, const RuntimeShape& output_shape, + int8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + TFLITE_DCHECK_GE(params.quantized_activation_min, + std::numeric_limits::min()); + TFLITE_DCHECK_LE(params.quantized_activation_max, + std::numeric_limits::max()); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + int8_t max = std::numeric_limits::lowest(); + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + max = std::max( + max, + input_data[Offset(input_shape, batch, in_y, in_x, channel)]); + } + } + max = std::max(max, params.quantized_activation_min); + max = std::min(max, params.quantized_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + static_cast(max); + } + } + } + } +} + +inline bool AveragePool(const PoolParams& params, + const RuntimeShape& input_shape, + const int16_t* input_data, + const RuntimeShape& output_shape, + int16_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + int32_t acc = 0; + int filter_count = 0; + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + acc += + input_data[Offset(input_shape, batch, in_y, in_x, channel)]; + filter_count++; + } + } + if (filter_count == 0) return false; + // Round to the closest integer value. + acc = acc > 0 ? (acc + filter_count / 2) / filter_count + : (acc - filter_count / 2) / filter_count; + acc = std::max(acc, params.quantized_activation_min); + acc = std::min(acc, params.quantized_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + static_cast(acc); + } + } + } + } + return true; +} + +inline void MaxPool(const PoolParams& params, const RuntimeShape& input_shape, + const int16_t* input_data, const RuntimeShape& output_shape, + int16_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + TFLITE_DCHECK_GE(params.quantized_activation_min, + std::numeric_limits::min()); + TFLITE_DCHECK_LE(params.quantized_activation_max, + std::numeric_limits::max()); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + int16_t max = std::numeric_limits::lowest(); + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + max = std::max( + max, + input_data[Offset(input_shape, batch, in_y, in_x, channel)]); + } + } + max = std::max(max, params.quantized_activation_min); + max = std::min(max, params.quantized_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + static_cast(max); + } + } + } + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_POOLING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/tanh.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/tanh.h new file mode 100644 index 0000000..d7feb45 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/tanh.h @@ -0,0 +1,117 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_TANH_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_TANH_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +inline void Tanh(int32_t input_zero_point, int32_t input_range_radius, + int32_t input_multiplier, int32_t input_shift, + const RuntimeShape& input_shape, const int8_t* input_data, + const RuntimeShape& output_shape, int8_t* output_data) { + // Integer bits must be in sync with Prepare() function. + static constexpr int32_t kInputIntegerBits = 4; + static constexpr int32_t kOutputScale = 7; + static constexpr int32_t kMinInt8 = std::numeric_limits::min(); + static constexpr int32_t kMaxInt8 = std::numeric_limits::max(); + using F4 = gemmlowp::FixedPoint; + + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; ++i) { + const int32_t input = + static_cast(input_data[i]) - input_zero_point; + if (input <= -input_range_radius) { + output_data[i] = kMinInt8; + } else if (input >= input_range_radius) { + output_data[i] = kMaxInt8; + } else { + const int32_t input_in_q4 = + MultiplyByQuantizedMultiplier(input, input_multiplier, input_shift); + const int32_t output_in_q0 = + gemmlowp::tanh(F4::FromRaw(input_in_q4)).raw(); + + // Rescale and downcast. + using gemmlowp::RoundingDivideByPOT; + int32_t output_in_q24 = + RoundingDivideByPOT(output_in_q0, 31 - kOutputScale); + output_in_q24 = std::min(std::max(output_in_q24, kMinInt8), kMaxInt8); + output_data[i] = static_cast(output_in_q24); + } + } +} + +inline void Tanh(int32_t input_multiplier, int32_t input_left_shift, + const RuntimeShape& input_shape, const int16_t* ptr_input_data, + const RuntimeShape& output_shape, int16_t* ptr_output_data) { + // We use the LUT for sigmoid and take into account, that + // tanh(x) = 2*sigmoid(2*x) - 1 + + // We scale by 3/4 to expand range [-8,8]->[-10.7,10.7]. + // In case of general parameter scale, multiplier 3 is taken into account + // in TanhPrepare function and it is included in + // input_multiplier already. + + if (input_multiplier == 0) { // power of two case + input_multiplier = 3 << input_left_shift; + input_left_shift = 0; + } + + int32_t round = (input_left_shift > 0) ? 1 << (input_left_shift - 1) : 0; + + int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; ++i, ptr_input_data++, ptr_output_data++) { + int32_t input_data = + ((*ptr_input_data) * input_multiplier + round) >> input_left_shift; + + uint32_t abs_input_data = abs(input_data); + uint32_t uh = abs_input_data >> 8; + int32_t result; + + if (uh >= 255) { + // Saturate to maximum. + result = 0xFFFF << 8; + } else { + uint32_t ua = sigmoid_table_uint16[uh]; + uint32_t ub = sigmoid_table_uint16[uh + 1]; + + uint8_t ut = abs_input_data & 0xFF; + + result = (ua << 8) + ut * (ub - ua); + } + + result = (input_data >= 0) + ? (result - (1 << (14 + 9)) + (1 << (9 - 2))) + : (-result + (1 << (14 + 9)) + (1 << (9 - 2)) - 1); + + // Convert back to 16-bit. + result >>= (9 - 1); + + *ptr_output_data = result; + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_TANH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/transpose_conv.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/transpose_conv.h new file mode 100644 index 0000000..8ce1cb7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/transpose_conv.h @@ -0,0 +1,224 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_TRANSPOSE_CONV_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_TRANSPOSE_CONV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_integer_ops { + +// Fixed-point per-channel-quantization transpose convolution reference kernel. +inline void TransposeConv( + const ConvParams& params, const int32_t* output_multiplier, + const int32_t* output_shift, const RuntimeShape& input_shape, + const int8_t* input_data, const RuntimeShape& filter_shape, + const int8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + int8_t* output_data, const RuntimeShape& im2col_shape, int8_t* im2col_data, + int32_t* scratch_buffer) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + (void)im2col_data; // only used in optimized code. + (void)im2col_shape; // only used in optimized code. + + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int32_t input_offset = params.input_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + + const int num_elements = output_shape.FlatSize(); + // We need to initialize scratch_buffer to all 0s, as we apply the same + // 'scatter' based trick as in float version. + memset(scratch_buffer, 0, num_elements * sizeof(int32_t)); + + // Loop through input elements one at a time. + for (int batch = 0; batch < batches; ++batch) { + for (int in_y = 0; in_y < input_height; ++in_y) { + for (int in_x = 0; in_x < input_width; ++in_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + // Loop through the output elements it will influence. + const int out_x_origin = (in_x * stride_width) - pad_width; + const int out_y_origin = (in_y * stride_height) - pad_height; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + for (int out_channel = 0; out_channel < output_depth; + ++out_channel) { + // Compute output element location. + const int out_x = out_x_origin + filter_x; + const int out_y = out_y_origin + filter_y; + // We cannot accumulate out of bounds. + if ((out_x >= 0) && (out_x < output_width) && (out_y >= 0) && + (out_y < output_height)) { + const int8_t input_value = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + const int8_t filter_value = + filter_data[Offset(filter_shape, out_channel, filter_y, + filter_x, in_channel)]; + scratch_buffer[Offset(output_shape, batch, out_y, out_x, + out_channel)] += + (input_value + input_offset) * filter_value; + } + } + } + } + } + } + } + } + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + int32_t acc = scratch_buffer[Offset(output_shape, batch, out_y, out_x, + out_channel)]; + if (bias_data) { + acc += bias_data[out_channel]; + } + acc = MultiplyByQuantizedMultiplier( + acc, output_multiplier[out_channel], output_shift[out_channel]); + acc += output_offset; + acc = std::max(acc, output_activation_min); + acc = std::min(acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + static_cast(acc); + } + } + } + } +} + +// int16_t input (zero_point=0), int8_t filter, int32 or int64 accumulator +template +inline void TransposeConv( + const ConvParams& params, const int32_t* output_multiplier, + const int32_t* output_shift, const RuntimeShape& input_shape, + const int16_t* input_data, const RuntimeShape& filter_shape, + const int8_t* filter_data, const RuntimeShape& bias_shape, + const Scalar* bias_data, const RuntimeShape& output_shape, + int16_t* output_data, const RuntimeShape& im2col_shape, int8_t* im2col_data, + Scalar* scratch_buffer) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + (void)im2col_data; // only used in optimized code. + (void)im2col_shape; // only used in optimized code. + + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + + const int num_elements = output_shape.FlatSize(); + // We need to initialize scratch_buffer to all 0s, as we apply the same + // 'scatter' based trick as in float version. + memset(scratch_buffer, 0, num_elements * sizeof(Scalar)); + + // Loop through input elements one at a time. + for (int batch = 0; batch < batches; ++batch) { + for (int in_y = 0; in_y < input_height; ++in_y) { + for (int in_x = 0; in_x < input_width; ++in_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + // Loop through the output elements it will influence. + const int out_x_origin = (in_x * stride_width) - pad_width; + const int out_y_origin = (in_y * stride_height) - pad_height; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + for (int out_channel = 0; out_channel < output_depth; + ++out_channel) { + // Compute output element location. + const int out_x = out_x_origin + filter_x; + const int out_y = out_y_origin + filter_y; + // We cannot accumulate out of bounds. + if ((out_x >= 0) && (out_x < output_width) && (out_y >= 0) && + (out_y < output_height)) { + const int32_t input_value = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + const int32_t filter_value = + filter_data[Offset(filter_shape, out_channel, filter_y, + filter_x, in_channel)]; + scratch_buffer[Offset(output_shape, batch, out_y, out_x, + out_channel)] += + input_value * filter_value; + } + } + } + } + } + } + } + } + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + Scalar acc = scratch_buffer[Offset(output_shape, batch, out_y, out_x, + out_channel)]; + if (bias_data) { + acc += bias_data[out_channel]; + } + int32_t scaled_acc = MultiplyByQuantizedMultiplier( + acc, output_multiplier[out_channel], output_shift[out_channel]); + scaled_acc = std::max(scaled_acc, output_activation_min); + scaled_acc = std::min(scaled_acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + static_cast(scaled_acc); + } + } + } + } +} + +} // namespace reference_integer_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_INTEGER_OPS_TRANSPOSE_CONV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/l2normalization.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/l2normalization.h new file mode 100644 index 0000000..cf32ea5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/l2normalization.h @@ -0,0 +1,90 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_L2NORMALIZATION_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_L2NORMALIZATION_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline void L2Normalization(const tflite::L2NormalizationParams& op_params, + const RuntimeShape& input_shape, + const float* input_data, + const RuntimeShape& output_shape, + float* output_data, float epsilon = 1e-6) { + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + for (int i = 0; i < outer_size; ++i) { + float squared_l2_norm = 0; + for (int c = 0; c < depth; ++c) { + const float val = input_data[depth * i + c]; + squared_l2_norm += val * val; + } + float l2_norm = std::sqrt(squared_l2_norm); + l2_norm = std::max(l2_norm, epsilon); + for (int c = 0; c < depth; ++c) { + output_data[depth * i + c] = input_data[depth * i + c] / l2_norm; + } + } +} + +inline void L2Normalization(const tflite::L2NormalizationParams& op_params, + const RuntimeShape& input_shape, + const uint8_t* input_data, + const RuntimeShape& output_shape, + uint8_t* output_data) { + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int32_t input_zero_point = op_params.input_zero_point; + + for (int i = 0; i < outer_size; ++i) { + int32_t square_l2_norm = 0; + for (int c = 0; c < depth; c++) { + int32_t diff = input_data[depth * i + c] - input_zero_point; + square_l2_norm += diff * diff; + } + int32_t inv_l2norm_multiplier; + int inv_l2norm_shift; + GetInvSqrtQuantizedMultiplierExp(square_l2_norm, kReverseShift, + &inv_l2norm_multiplier, &inv_l2norm_shift); + for (int c = 0; c < depth; c++) { + int32_t diff = input_data[depth * i + c] - input_zero_point; + int32_t rescaled_diff = MultiplyByQuantizedMultiplierSmallerThanOneExp( + 128 * diff, inv_l2norm_multiplier, inv_l2norm_shift); + int32_t unclamped_output_val = 128 + rescaled_diff; + int32_t output_val = + std::min(static_cast(255), + std::max(static_cast(0), unclamped_output_val)); + output_data[depth * i + c] = static_cast(output_val); + } + } +} + +} // namespace reference_ops +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_L2NORMALIZATION_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/leaky_relu.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/leaky_relu.h new file mode 100644 index 0000000..5c05b15 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/leaky_relu.h @@ -0,0 +1,69 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LEAKY_RELU_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LEAKY_RELU_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_ops { + +inline void LeakyRelu(const tflite::LeakyReluParams& params, + const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + const float val = input_data[i]; + // Note that alpha might be > 1 or < 0, so we don't use std::max here. + output_data[i] = val > 0 ? val : val * params.alpha; + } +} + +template +inline void QuantizeLeakyRelu(const LeakyReluParams& params, + const RuntimeShape& input_shape, + const T* input_data, + const RuntimeShape& output_shape, + T* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + static const int32_t quantized_min = std::numeric_limits::min(); + static const int32_t quantized_max = std::numeric_limits::max(); + for (int i = 0; i < flat_size; ++i) { + const int32_t input_value = input_data[i] - params.input_offset; + int32_t unclamped_output; + if (input_value >= 0) { + unclamped_output = params.output_offset + + MultiplyByQuantizedMultiplier( + input_value, params.output_multiplier_identity, + params.output_shift_identity); + } else { + unclamped_output = params.output_offset + + MultiplyByQuantizedMultiplier( + input_value, params.output_multiplier_alpha, + params.output_shift_alpha); + } + const T clamped_output = + std::min(quantized_max, std::max(quantized_min, unclamped_output)); + output_data[i] = static_cast(clamped_output); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LEAKY_RELU_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/log_softmax.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/log_softmax.h new file mode 100644 index 0000000..af55755 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/log_softmax.h @@ -0,0 +1,256 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LOG_SOFTMAX_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LOG_SOFTMAX_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { +namespace reference_ops { + +inline void LogSoftmax(const SoftmaxParams& params, + const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + + for (int i = 0; i < outer_size; ++i) { + // Find max element value which we'll use to ensure numerical stability + // taking advantage of the following equality: + // log(exp(x[i])/sum(exp(x[i]))) == log(exp(x[i]+C)/sum(exp(x[i]+C))) + float max = std::numeric_limits::lowest(); + for (int c = 0; c < depth; ++c) { + max = std::max(max, input_data[i * depth + c]); + } + + // Compute sum. + float sum = 0.f; + for (int c = 0; c < depth; ++c) { + sum += std::exp(input_data[i * depth + c] - max); + } + + // Compute result. + const float log_sum = std::log(sum); + for (int c = 0; c < depth; ++c) { + output_data[i * depth + c] = input_data[i * depth + c] - max - log_sum; + } + } +} + +inline void LogSoftmax(const SoftmaxParams& params, + const RuntimeShape& input_shape, + const uint8_t* input_data, + const RuntimeShape& output_shape, uint8_t* output_data) { + const int32_t input_multiplier = params.input_multiplier; + const int32_t input_left_shift = params.input_left_shift; + const int32_t reverse_scaling_divisor = params.reverse_scaling_divisor; + const int32_t reverse_scaling_right_shift = + params.reverse_scaling_right_shift; + const int diff_min = params.diff_min; + // The representation chosen for the input to the exp() function is Q5.26. + // We need to leave extra space since values that we skip might be as large + // as -32 before multiplying by input_beta_multiplier, and therefore as + // large as -16 afterwards. Note that exp(-8) is definitely not + // insignificant to accumulation, but exp(-16) definitely is. + static constexpr int kScaledDiffIntegerBits = 5; + static constexpr int kAccumulationIntegerBits = 12; + static constexpr int kOutputIntegerBits = 4; + using FixedPointScaledDiff = + gemmlowp::FixedPoint; + using FixedPointAccum = + gemmlowp::FixedPoint; + + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + + for (int i = 0; i < outer_size; ++i) { + uint8_t max_in_row = 0; + for (int c = 0; c < depth; ++c) { + max_in_row = std::max(max_in_row, input_data[i * depth + c]); + } + + FixedPointAccum sum_of_exps = FixedPointAccum::Zero(); + for (int c = 0; c < depth; ++c) { + int32_t input_diff = + static_cast(input_data[i * depth + c]) - max_in_row; + if (input_diff >= diff_min) { + const int32_t input_diff_rescaled = + MultiplyByQuantizedMultiplierGreaterThanOne( + input_diff, input_multiplier, input_left_shift); + const FixedPointScaledDiff scaled_diff_f8 = + FixedPointScaledDiff::FromRaw(input_diff_rescaled); + sum_of_exps = sum_of_exps + gemmlowp::Rescale( + exp_on_negative_values(scaled_diff_f8)); + } + } + + const int32_t fixed_log_sum_of_exps = + log_x_for_x_greater_than_or_equal_to_1( + sum_of_exps) + .raw(); + + // rescaled_diff_min is smallest representable in + // Q(kScaledDiffIntegerBits).(31-kScaledDiffIntegerBits) plus the + // log-sub-exps that will be subtracted in the loop. + // + // The thresholds diff_min, etc are negative. + const int rescaled_diff_min = + fixed_log_sum_of_exps + std::numeric_limits::lowest(); + const int adjusted_diff_min = + std::max(static_cast( + diff_min - 1), // Note use of > below instead of >= above. + MultiplyByQuantizedMultiplierSmallerThanOneExp( + rescaled_diff_min, reverse_scaling_divisor, + -reverse_scaling_right_shift)); + + for (int c = 0; c < depth; ++c) { + int32_t input_diff = + static_cast(input_data[i * depth + c]) - max_in_row; + if (input_diff > adjusted_diff_min) { + const int32_t input_diff_rescaled = + MultiplyByQuantizedMultiplierGreaterThanOne( + input_diff, input_multiplier, input_left_shift); + int32_t unsat_output = + gemmlowp::RoundingDivideByPOT( + (input_diff_rescaled - fixed_log_sum_of_exps), + 31 - kScaledDiffIntegerBits - kOutputIntegerBits) + + 255; + + output_data[i * depth + c] = static_cast( + std::max(std::min(unsat_output, static_cast(255)), + static_cast(0))); + } else { + // Set output to smallest value. + output_data[i * depth + c] = 0; + } + } + } +} + +template +inline void LogSoftmaxQuantized(const SoftmaxParams& params, + const size_t outer_size, const size_t depth, + const RuntimeShape& input_shape, + const T* input_data, + const RuntimeShape& output_shape, + T* output_data) { + const int32_t input_multiplier = params.input_multiplier; + const int32_t input_left_shift = params.input_left_shift; + const int32_t reverse_scaling_divisor = params.reverse_scaling_divisor; + const int32_t reverse_scaling_right_shift = + params.reverse_scaling_right_shift; + const int diff_min = params.diff_min; + + static constexpr T kMinT8 = std::numeric_limits::min(); + static constexpr T kMaxT8 = std::numeric_limits::max(); + static constexpr int32_t kMinInt32 = std::numeric_limits::min(); + + // All IntegerBits must agree with Prepare function. + // Input is chosen as Q5.26 so exp(-1 * 2^5 * 2^-1) = exp(-16) is negligible. + static constexpr int kInputIntegerBits = 5; + static constexpr int kAccumulationIntegerBits = 12; + static constexpr int kOutputIntegerBits = 4; + using F5 = gemmlowp::FixedPoint; + using F12 = gemmlowp::FixedPoint; + + for (size_t outer_index = 0; outer_index < outer_size; ++outer_index) { + T max_in_row = kMinT8; + for (size_t inner_index = 0; inner_index < depth; ++inner_index) { + max_in_row = + std::max(max_in_row, input_data[outer_index * depth + inner_index]); + } + + // Accumulator "sum_of_exps_in_q12" is safe from overflowing in 2^12 steps. + F12 sum_of_exps_in_q12 = F12::FromRaw(0); + for (size_t inner_index = 0; inner_index < depth; ++inner_index) { + int32_t input_diff = + static_cast(input_data[outer_index * depth + inner_index]) - + max_in_row; + if (input_diff >= diff_min) { + const int32_t input_diff_in_q5 = MultiplyByQuantizedMultiplier( + input_diff, input_multiplier, input_left_shift); + sum_of_exps_in_q12 = + sum_of_exps_in_q12 + + gemmlowp::Rescale( + exp_on_negative_values(F5::FromRaw(input_diff_in_q5))); + } + } + + const int32_t log_sum_of_exps_in_q5 = + log_x_for_x_greater_than_or_equal_to_1( + sum_of_exps_in_q12) + .raw(); + + // Potentially reduced the valid range. shifted_log_sum_of_exps_in_q5 is + // smallest representable in Q5.26 plus the log_sum_of_exps. + const int32_t shifted_log_sum_of_exps_in_q5 = + log_sum_of_exps_in_q5 + kMinInt32; + const int32_t adjusted_diff_min = + std::max(static_cast(diff_min - 1), + MultiplyByQuantizedMultiplier(shifted_log_sum_of_exps_in_q5, + reverse_scaling_divisor, + -reverse_scaling_right_shift)); + + for (size_t inner_index = 0; inner_index < depth; ++inner_index) { + int32_t input_diff = + static_cast(input_data[outer_index * depth + inner_index]) - + max_in_row; + // Note use of > below instead of >= above. + if (input_diff > adjusted_diff_min) { + const int32_t input_diff_in_q5 = MultiplyByQuantizedMultiplier( + input_diff, input_multiplier, input_left_shift); + + // Rescale and downcast. + int32_t output_in_q27 = + gemmlowp::RoundingDivideByPOT( + (input_diff_in_q5 - log_sum_of_exps_in_q5), + 31 - kInputIntegerBits - kOutputIntegerBits) + + kMaxT8; + + output_in_q27 = + std::max(std::min(output_in_q27, static_cast(kMaxT8)), + static_cast(kMinT8)); + output_data[outer_index * depth + inner_index] = + static_cast(output_in_q27); + } else { + output_data[outer_index * depth + inner_index] = kMinT8; + } + } + } +} + +inline void LogSoftmax(const SoftmaxParams& params, const size_t outer_size, + const size_t depth, const RuntimeShape& input_shape, + const int8_t* input_data, + const RuntimeShape& output_shape, int8_t* output_data) { + LogSoftmaxQuantized(params, outer_size, depth, input_shape, input_data, + output_shape, output_data); +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LOG_SOFTMAX_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/logistic.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/logistic.h new file mode 100644 index 0000000..5a46190 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/logistic.h @@ -0,0 +1,132 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LOGISTIC_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LOGISTIC_H_ + +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" + +namespace tflite { +namespace reference_ops { + +inline void Logistic(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const float cutoff_upper = 16.619047164916992188f; + const float cutoff_lower = -9.f; + + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + // Rational for using approximation in reference kernel. + // 0. This approximation gives enough precision for float. + // 1. This works around an issue on an embedded chipset where exp() does not + // return correctly as expected - exp(x) should return inf when overflown + // not 1.701417 IEEE 754 defines representation for inf. + // 2. This will speed up calculation and is matching the behavior in the + // optimized kernels. (check the definition of scalar_logistic_op) + + for (int i = 0; i < flat_size; i++) { + float val = input_data[i]; + float result; + if (val > cutoff_upper) { + result = 1.0f; + } else if (val < cutoff_lower) { + result = std::exp(val); + } else { + result = 1.f / (1.f + std::exp(-val)); + } + output_data[i] = result; + } +} + +// Convenience version that allows, for example, generated-code calls to be +// uniform between data types. +inline void Logistic(const LogisticParams&, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& output_shape, + float* output_data) { + // Drop params: not needed. + Logistic(input_shape, input_data, output_shape, output_data); +} + +inline void Logistic(const LogisticParams& params, + const RuntimeShape& input_shape, const int16_t* input_data, + const RuntimeShape& output_shape, int16_t* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; i++) { + // F0 uses 0 integer bits, range [-1, 1]. + // This is the return type of math functions such as tanh, logistic, + // whose range is in [-1, 1]. + using F0 = gemmlowp::FixedPoint; + // F3 uses 3 integer bits, range [-8, 8], the input range expected here. + using F3 = gemmlowp::FixedPoint; + + const F3 input = F3::FromRaw(input_data[i]); + F0 output = gemmlowp::logistic(input); + output_data[i] = output.raw(); + } +} + +// Quantized int8_t logistic activation. Cheats by dequantizing and +// requantizing around the floating point logistic method. This implementation +// is slow on platforms without a floating point unit. + +// TODO(b/141211002): Delete this int8_t implementation once we can reuse the +// approach used in TFLite for int8_t Logistic. +inline void Logistic(const RuntimeShape& input_shape, const int8_t* input_data, + float input_scale, int input_zero_point, + const RuntimeShape& output_shape, int8_t* output_data, + float output_scale, int output_zero_point) { + const float cutoff_upper = 16.619047164916992188f; + const float cutoff_lower = -9.f; + + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + // Rational for using approximation in reference kernel. + // 0. This approximation gives enough precision for float. + // 1. This works around an issue on an embedded chipset where exp() does not + // return correctly as expected - exp(x) should return inf when overflown + // not 1.701417 IEEE 754 defines representation for inf. + // 2. This will speed up calculation and is matching the behavior in the + // optimized kernels. (check the definition of scalar_logistic_op) + + for (int i = 0; i < flat_size; i++) { + // Dequantize. + float val = + static_cast((input_data[i] - input_zero_point) * input_scale); + float result; + if (val > cutoff_upper) { + result = 1.0f; + } else if (val < cutoff_lower) { + result = std::exp(val); + } else { + result = 1.f / (1.f + std::exp(-val)); + } + // Requantize + int8_t output = + static_cast(result / output_scale + output_zero_point); + output_data[i] = output; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LOGISTIC_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/lstm_cell.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/lstm_cell.h new file mode 100644 index 0000000..de1c485 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/lstm_cell.h @@ -0,0 +1,422 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LSTM_CELL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LSTM_CELL_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/concatenation.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +inline void LstmCell( + const LstmCellParams& params, const RuntimeShape& unextended_input_shape, + const float* input_data, const RuntimeShape& unextended_prev_activ_shape, + const float* prev_activ_data, const RuntimeShape& weights_shape, + const float* weights_data, const RuntimeShape& unextended_bias_shape, + const float* bias_data, const RuntimeShape& unextended_prev_state_shape, + const float* prev_state_data, + const RuntimeShape& unextended_output_state_shape, float* output_state_data, + const RuntimeShape& unextended_output_activ_shape, float* output_activ_data, + const RuntimeShape& unextended_concat_temp_shape, float* concat_temp_data, + const RuntimeShape& unextended_activ_temp_shape, float* activ_temp_data) { + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_prev_activ_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_bias_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_prev_state_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_state_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_activ_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_concat_temp_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_activ_temp_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape prev_activ_shape = + RuntimeShape::ExtendedShape(4, unextended_prev_activ_shape); + const RuntimeShape bias_shape = + RuntimeShape::ExtendedShape(4, unextended_bias_shape); + const RuntimeShape prev_state_shape = + RuntimeShape::ExtendedShape(4, unextended_prev_state_shape); + const RuntimeShape output_state_shape = + RuntimeShape::ExtendedShape(4, unextended_output_state_shape); + const RuntimeShape output_activ_shape = + RuntimeShape::ExtendedShape(4, unextended_output_activ_shape); + const RuntimeShape concat_temp_shape = + RuntimeShape::ExtendedShape(4, unextended_concat_temp_shape); + const RuntimeShape activ_temp_shape = + RuntimeShape::ExtendedShape(4, unextended_activ_temp_shape); + TFLITE_DCHECK_GE(weights_shape.DimensionsCount(), 2); + + const int weights_dim_count = weights_shape.DimensionsCount(); + const int batches = + MatchingDim(input_shape, 0, prev_activ_shape, 0, prev_state_shape, 0, + output_state_shape, 0, output_activ_shape, 0); + const int height = + MatchingDim(input_shape, 1, prev_activ_shape, 1, prev_state_shape, 1, + output_state_shape, 1, output_activ_shape, 1); + const int width = + MatchingDim(input_shape, 2, prev_activ_shape, 2, prev_state_shape, 2, + output_state_shape, 2, output_activ_shape, 2); + const int input_depth = input_shape.Dims(3); + const int prev_activ_depth = prev_activ_shape.Dims(3); + const int total_input_depth = prev_activ_depth + input_depth; + TFLITE_DCHECK_EQ(weights_shape.Dims(weights_dim_count - 1), + total_input_depth); + TFLITE_DCHECK_EQ(FlatSizeSkipDim(bias_shape, 3), 1); + const int intern_activ_depth = + MatchingDim(weights_shape, weights_dim_count - 2, bias_shape, 3); + TFLITE_DCHECK_EQ(weights_shape.FlatSize(), + intern_activ_depth * total_input_depth); + TFLITE_DCHECK_EQ(intern_activ_depth % 4, 0); + const int output_depth = + MatchingDim(prev_state_shape, 3, prev_activ_shape, 3, output_state_shape, + 3, output_activ_shape, 3); + TFLITE_DCHECK_EQ(output_depth, intern_activ_depth / 4); + + // Concatenate prev_activ and input data together + float const* concat_input_arrays_data[2] = {input_data, prev_activ_data}; + const RuntimeShape* concat_input_arrays_shapes[2] = {&input_shape, + &prev_activ_shape}; + tflite::ConcatenationParams concat_params; + concat_params.axis = 3; + concat_params.inputs_count = 2; + Concatenation(concat_params, concat_input_arrays_shapes, + concat_input_arrays_data, concat_temp_shape, concat_temp_data); + + // Fully connected + tflite::FullyConnectedParams fc_params; + fc_params.float_activation_min = std::numeric_limits::lowest(); + fc_params.float_activation_max = std::numeric_limits::max(); + FullyConnected(fc_params, concat_temp_shape, concat_temp_data, weights_shape, + weights_data, bias_shape, bias_data, activ_temp_shape, + activ_temp_data); + + // Memory state update (the LSTM "guts") + for (int b = 0; b < batches; ++b) { + for (int w = 0; w < width; ++w) { + for (int h = 0; h < height; ++h) { + for (int c = 0; c < output_depth; ++c) { + const float input_gate = + 1.f / + (1.f + std::exp(-activ_temp_data[Offset(activ_temp_shape, b, h, w, + 0 * output_depth + c)])); + const float new_input = std::tanh(activ_temp_data[Offset( + activ_temp_shape, b, h, w, 1 * output_depth + c)]); + const float forget_gate = + 1.f / + (1.f + std::exp(-activ_temp_data[Offset(activ_temp_shape, b, h, w, + 2 * output_depth + c)])); + const float output_gate = + 1.f / + (1.f + std::exp(-activ_temp_data[Offset(activ_temp_shape, b, h, w, + 3 * output_depth + c)])); + const float new_state = + input_gate * new_input + + forget_gate * + prev_state_data[Offset(prev_state_shape, b, h, w, c)]; + output_state_data[Offset(output_state_shape, b, h, w, c)] = new_state; + output_activ_data[Offset(output_activ_shape, b, h, w, c)] = + output_gate * std::tanh(new_state); + } + } + } + } +} + +// Quantized LSTM cell implementation. +// The quantization of the input, output arrays is as follows: +// - The input activations are quantized as uint8 on the interval +// [-1, 127/128]. +// The rationale for that is that is the natural interval for output +// activations (see next point) and these need to be concatenated together. +// We could accommodate different ranges by re-scaling, but we empirically +// found that setting the input activations range to be [-1, 127/128] in the +// first place, removing the need for re-scaling, greatly improves accuracy. +// - The output activations are quantized as uint8 on the interval +// [-1, 127/128]. +// The rationale for that is that the definition of a LSTM cell makes them +// intrinsically constrained in [-1, 1]; tweaking that to [-1, 127/128] +// makes for simpler, more accurate fixed-point arithmetic. +// - The output-at-previous-timestep state array is obviously quantized as +// the output activations. +// - The internal LSTM memory (not the output-at-previous-timestep, the other +// internal state array) is int16-quantized and may use any power-of-two, +// symmetric range i.e. [-2^N, 2^N * 32767/32768] for any N, which we call +// StateIntegerBits below, see the below discussion of that template +// parameter ("The StateIntegerBits template parameter"). +// - The output of the internal fully-connected node is int16-quantized +// on the interval [-8, 8 * 32767/32768], the rationale for which is +// explained just below ("Why [-8, 8] for fully-connected output?"). +// +// +// === The StateIntegerBits template parameter === +// +// The StateIntegerBits template parameter controls the fixed-point format used +// to represent the internal memory of the LSTM cell (not the +// output-at-previous-timestep, the other internal state array). It's currently +// a template parameter so that the model can control that. The most typical +// value for StateIntegerBits is 4. Other plausible values are anywhere between +// 3 and 5. We might eventually standardize on a single supported value, e.g. 4, +// and drop that template parameter. The reason why it can't be a runtime +// parameter is that this controls the fixed-point format used, i.e. we need to +// generate actually different code based on it. In particular, we generate code +// for a fixed-point tanh() implementation for that format, which internally +// uses a fixed-point exp() implementation, which internally uses a +// barrel-shifter with a number of steps that depends on StateIntegerBits. +// Another consequence of that is that a higher value of StateIntegerBits +// results in a more expensive implementation (more barrel shifter steps +// needed). +// +// +// === Why [-8, 8] for fully-connected output? === +// +// This array is only fed to Logistic and Tanh functions, for which +// the quantized implementation will want to use fixed-point arithmetic, +// requiring a power-of-two representation interval. Thus, we should right +// away quantize this array to a power-of-two interval; otherwise, +// implementation will need to rescale that, losing any benefit that a tighter +// representation interval might otherwise yield, while introducing some +// numerical error and computational overhead. +// +// Now, Logistic and Tanh +// are nearly constant (nearly equal to their horizontal asymptotes) +// outside of a small bounded interval around 0: +// +// Logistic(4) = 1 - 1.8e-2 Tanh(4) = 1 - 6.7e-4 +// Logistic(8) = 1 - 3.4e-4 Tanh(8) = 1 - 2.3e-7 +// Logistic(16) = 1 - 1.1e-7 Tanh(16) = 1 - 2.5e-14 +// +// From this, we see that clamping to [-4, 4] would be too inaccurate +// (the error of 1.8e-2 on Logistic would be felt even in 8bit precision) +// while clamping to [-16, 16] would make no difference even in float32. +// However, for a fixed-point implementation in 16-bit integers, using 5 +// integer bits to represent the [-16, 16] range would leave only 11 +// fractional bits, giving an increment of 2^-11 = 4.9e-4 between consecutive +// representable values. Notice that is higher than the +// worst-case clamping error with clamping to [-8, 8]: 3.4e-4 for Logistic. +// Using [-8, 8] thus seems like the better compromise overall, enjoying +// an increment of 2.4e-4 between representable values and a worst-case +// clamping error of 3.4e-4, both better than the increment of 4.9e-4 with +// [-16, 16]. +// +// Moreover, all other things being equal, it is nice to choose the narrower +// representation range, as that makes the implementation of fixed-point +// math functions a little cheaper (each integer bit requires an additional +// barrel-shifter atep in the implementation of exp(-x)). That is further +// reason to prefer [-8, 8] over [-16, 16]. The choice of [-16, 16] would make +// sense for 32-bit float or 32-bit fixed-point quantization, but we are +// aiming for 16-bit fixed-point quantization of these internal nodes here. +// +template +inline void LstmCell(const LstmCellParams& params, + const RuntimeShape& unextended_input_shape, + const uint8_t* input_data_uint8, + const RuntimeShape& unextended_prev_activ_shape, + const uint8_t* prev_activ_data_uint8, + const RuntimeShape& weights_shape, + const uint8_t* weights_data_uint8, + const RuntimeShape& unextended_bias_shape, + const int32_t* bias_data_int32, + const RuntimeShape& unextended_prev_state_shape, + const int16_t* prev_state_data_int16, + const RuntimeShape& unextended_output_state_shape, + int16_t* output_state_data_int16, + const RuntimeShape& unextended_output_activ_shape, + uint8_t* output_activ_data_uint8, + const RuntimeShape& unextended_concat_temp_shape, + uint8_t* concat_temp_data_uint8, + const RuntimeShape& unextended_activ_temp_shape, + int16_t* activ_temp_data_int16, void* gemmlowp_context) { + (void)gemmlowp_context; // only used in optimized code. + int32_t weights_zero_point = params.weights_zero_point; + int32_t accum_multiplier = params.accum_multiplier; + int accum_shift = params.accum_shift; + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_prev_activ_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_bias_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_prev_state_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_state_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_activ_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_concat_temp_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_activ_temp_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape prev_activ_shape = + RuntimeShape::ExtendedShape(4, unextended_prev_activ_shape); + const RuntimeShape bias_shape = + RuntimeShape::ExtendedShape(4, unextended_bias_shape); + const RuntimeShape prev_state_shape = + RuntimeShape::ExtendedShape(4, unextended_prev_state_shape); + const RuntimeShape output_state_shape = + RuntimeShape::ExtendedShape(4, unextended_output_state_shape); + const RuntimeShape output_activ_shape = + RuntimeShape::ExtendedShape(4, unextended_output_activ_shape); + const RuntimeShape concat_temp_shape = + RuntimeShape::ExtendedShape(4, unextended_concat_temp_shape); + const RuntimeShape activ_temp_shape = + RuntimeShape::ExtendedShape(4, unextended_activ_temp_shape); + TFLITE_DCHECK_GE(weights_shape.DimensionsCount(), 2); + + // Gather dimensions information, and perform consistency checks. + const int weights_dim_count = weights_shape.DimensionsCount(); + const int outer_size = MatchingFlatSizeSkipDim( + input_shape, 3, prev_activ_shape, prev_state_shape, output_state_shape, + output_activ_shape); + const int input_depth = input_shape.Dims(3); + const int prev_activ_depth = prev_activ_shape.Dims(3); + const int total_input_depth = prev_activ_depth + input_depth; + TFLITE_DCHECK_EQ(weights_shape.Dims(weights_dim_count - 1), + total_input_depth); + const int intern_activ_depth = + MatchingDim(weights_shape, weights_dim_count - 2, bias_shape, 3); + TFLITE_DCHECK_EQ(weights_shape.FlatSize(), + intern_activ_depth * total_input_depth); + TFLITE_DCHECK_EQ(FlatSizeSkipDim(bias_shape, 3), 1); + TFLITE_DCHECK_EQ(intern_activ_depth % 4, 0); + const int output_depth = + MatchingDim(prev_state_shape, 3, prev_activ_shape, 3, output_state_shape, + 3, output_activ_shape, 3); + TFLITE_DCHECK_EQ(output_depth, intern_activ_depth / 4); + const int fc_batches = FlatSizeSkipDim(activ_temp_shape, 3); + const int fc_output_depth = + MatchingDim(weights_shape, weights_dim_count - 2, activ_temp_shape, 3); + const int fc_accum_depth = total_input_depth; + TFLITE_DCHECK_EQ(fc_output_depth, 4 * output_depth); + + // Depth-concatenate prev_activ and input data together. + uint8_t const* concat_input_arrays_data[2] = {input_data_uint8, + prev_activ_data_uint8}; + const RuntimeShape* concat_input_arrays_shapes[2] = {&input_shape, + &prev_activ_shape}; + tflite::ConcatenationParams concat_params; + concat_params.axis = 3; + concat_params.inputs_count = 2; + Concatenation(concat_params, concat_input_arrays_shapes, + concat_input_arrays_data, concat_temp_shape, + concat_temp_data_uint8); + + // Implementation of the fully connected node inside the LSTM cell. + // The operands are 8-bit integers, the accumulators are internally 32bit + // integers, and the output is 16-bit fixed-point with 3 integer bits so + // the output range is [-2^3, 2^3] == [-8, 8]. The rationale for that + // is explained in the function comment above. + for (int b = 0; b < fc_batches; ++b) { + for (int out_c = 0; out_c < fc_output_depth; ++out_c) { + // Internal accumulation. + // Initialize accumulator with the bias-value. + int32_t accum = bias_data_int32[out_c]; + // Accumulation loop. + for (int d = 0; d < fc_accum_depth; ++d) { + int16_t input_val = + concat_temp_data_uint8[b * fc_accum_depth + d] - 128; + int16_t weights_val = + weights_data_uint8[out_c * fc_accum_depth + d] - weights_zero_point; + accum += input_val * weights_val; + } + // Down-scale the final int32 accumulator to the scale used by our + // (16-bit, using 3 integer bits) fixed-point format. The quantized + // multiplier and shift here have been pre-computed offline + // (e.g. by toco). + accum = + MultiplyByQuantizedMultiplier(accum, accum_multiplier, accum_shift); + // Saturate, cast to int16, and store to the temporary activations array. + accum = std::max(-32768, std::min(32767, accum)); + activ_temp_data_int16[out_c + fc_output_depth * b] = accum; + } + } + + // Rest of the LSTM cell: tanh and logistic math functions, and some adds + // and muls, all done in 16-bit fixed-point. + for (int b = 0; b < outer_size; ++b) { + for (int c = 0; c < output_depth; ++c) { + // Define the fixed-point data types that we will use here. All use + // int16 as the underlying integer type i.e. all are 16-bit fixed-point. + // They only differ by the number of integral vs. fractional bits, + // determining the range of values that they can represent. + // + // F0 uses 0 integer bits, range [-1, 1]. + // This is the return type of math functions such as tanh, logistic, + // whose range is in [-1, 1]. + using F0 = gemmlowp::FixedPoint; + // F3 uses 3 integer bits, range [-8, 8]. + // This is the range of the previous fully-connected node's output, + // which is our input here. + using F3 = gemmlowp::FixedPoint; + // FS uses StateIntegerBits integer bits, range [-2^StateIntegerBits, + // 2^StateIntegerBits]. It's used to represent the internal state, whose + // number of integer bits is currently dictated by the model. See comment + // on the StateIntegerBits template parameter above. + using FS = gemmlowp::FixedPoint; + // Implementation of input gate, using fixed-point logistic function. + F3 input_gate_input = F3::FromRaw( + activ_temp_data_int16[b * fc_output_depth + 0 * output_depth + c]); + F0 input_gate_output = gemmlowp::logistic(input_gate_input); + // Implementation of input modulation gate, using fixed-point tanh + // function. + F3 input_modulation_gate_input = F3::FromRaw( + activ_temp_data_int16[b * fc_output_depth + 1 * output_depth + c]); + F0 input_modulation_gate_output = + gemmlowp::tanh(input_modulation_gate_input); + // Implementation of forget gate, using fixed-point logistic function. + F3 forget_gate_input = F3::FromRaw( + activ_temp_data_int16[b * fc_output_depth + 2 * output_depth + c]); + F0 forget_gate_output = gemmlowp::logistic(forget_gate_input); + // Implementation of output gate, using fixed-point logistic function. + F3 output_gate_input = F3::FromRaw( + activ_temp_data_int16[b * fc_output_depth + 3 * output_depth + c]); + F0 output_gate_output = gemmlowp::logistic(output_gate_input); + // Implementation of internal multiplication nodes, still in fixed-point. + F0 input_times_input_modulation = + input_gate_output * input_modulation_gate_output; + FS prev_state = FS::FromRaw(prev_state_data_int16[b * output_depth + c]); + FS prev_state_times_forget_state = forget_gate_output * prev_state; + // Implementation of internal addition node, saturating. + FS new_state = gemmlowp::SaturatingAdd( + gemmlowp::Rescale(input_times_input_modulation), + prev_state_times_forget_state); + // Implementation of last internal Tanh node, still in fixed-point. + // Since a Tanh fixed-point implementation is specialized for a given + // number or integer bits, and each specialization can have a substantial + // code size, and we already used above a Tanh on an input with 3 integer + // bits, and per the table in the above function comment there is no + // significant accuracy to be lost by clamping to [-8, +8] for a + // 3-integer-bits representation, let us just do that. This helps people + // porting this to targets where code footprint must be minimized. + F3 new_state_f3 = gemmlowp::Rescale<3>(new_state); + F0 output_activ_int16 = output_gate_output * gemmlowp::tanh(new_state_f3); + // Store the new internal state back to memory, as 16-bit integers. + // Note: here we store the original value with StateIntegerBits, not + // the rescaled 3-integer-bits value fed to tanh. + output_state_data_int16[b * output_depth + c] = new_state.raw(); + // Down-scale the output activations to 8-bit integers, saturating, + // and store back to memory. + int16_t rescaled_output_activ = + gemmlowp::RoundingDivideByPOT(output_activ_int16.raw(), 8); + int16_t clamped_output_activ = std::max( + -128, std::min(127, rescaled_output_activ)); + output_activ_data_uint8[b * output_depth + c] = + 128 + clamped_output_activ; + } + } +} + +} // namespace reference_ops +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_LSTM_CELL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/maximum_minimum.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/maximum_minimum.h new file mode 100644 index 0000000..b005336 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/maximum_minimum.h @@ -0,0 +1,64 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_MAXIMUM_MINIMUM_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_MAXIMUM_MINIMUM_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +void MaximumMinimumBroadcastSlow(const RuntimeShape& unextended_input1_shape, + const T* input1_data, + const RuntimeShape& unextended_input2_shape, + const T* input2_data, + const RuntimeShape& unextended_output_shape, + T* output_data, Op op) { + // Uses element-wise calculation if broadcast is not required. + if (unextended_input1_shape == unextended_input2_shape) { + const int flat_size = + MatchingElementsSize(unextended_input1_shape, unextended_input2_shape, + unextended_output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = op(input1_data[i], input2_data[i]); + } + } else { + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), N); + + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast( + unextended_input1_shape, unextended_input2_shape, &desc1, &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, unextended_output_shape), + &output_desc); + + auto maxmin_func = [&](int indexes[N]) { + output_data[SubscriptToIndex(output_desc, indexes)] = + op(input1_data[SubscriptToIndex(desc1, indexes)], + input2_data[SubscriptToIndex(desc2, indexes)]); + }; + NDOpsHelper(output_desc, maxmin_func); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_MAXIMUM_MINIMUM_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h new file mode 100644 index 0000000..63ece01 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h @@ -0,0 +1,214 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_MUL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_MUL_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" + +namespace tflite { + +namespace reference_ops { + +// Element-wise mul that can often be used for inner loop of broadcast Mul as +// well as the non-broadcast Mul. +inline void MulElementwise(int size, const ArithmeticParams& params, + const uint8_t* input1_data, + const uint8_t* input2_data, uint8_t* output_data) { + for (int i = 0; i < size; ++i) { + const int32_t input1_val = params.input1_offset + input1_data[i]; + const int32_t input2_val = params.input2_offset + input2_data[i]; + const int32_t unclamped_result = + params.output_offset + + MultiplyByQuantizedMultiplier(input1_val * input2_val, + params.output_multiplier, + params.output_shift); + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, unclamped_result)); + output_data[i] = static_cast(clamped_output); + } +} + +template +inline void Mul(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + T output_activation_min; + T output_activation_max; + GetActivationParams(params, &output_activation_min, &output_activation_max); + + const int flat_size = + MatchingExtendedShapeFlatSize(input1_shape, input2_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = ActivationFunctionWithMinMax( + input1_data[i] * input2_data[i], output_activation_min, + output_activation_max); + } +} + +inline void Mul(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const std::complex* input1_data, + const RuntimeShape& input2_shape, + const std::complex* input2_data, + const RuntimeShape& output_shape, + std::complex* output_data) { + const int flat_size = + MatchingExtendedShapeFlatSize(input1_shape, input2_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = input1_data[i] * input2_data[i]; + } +} + +inline void Mul(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const uint8_t* input1_data, + const RuntimeShape& input2_shape, const uint8_t* input2_data, + const RuntimeShape& output_shape, uint8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + const int flat_size = + MatchingExtendedShapeFlatSize(input1_shape, input2_shape, output_shape); + + MulElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +inline void BroadcastMul4DSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const uint8_t* input1_data, + const RuntimeShape& input2_shape, + const uint8_t* input2_data, + const RuntimeShape& output_shape, + uint8_t* output_data) { + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(4, output_shape); + + for (int b = 0; b < extended_output_shape.Dims(0); ++b) { + for (int y = 0; y < extended_output_shape.Dims(1); ++y) { + for (int x = 0; x < extended_output_shape.Dims(2); ++x) { + for (int c = 0; c < extended_output_shape.Dims(3); ++c) { + const int32_t input1_val = + params.input1_offset + + input1_data[SubscriptToIndex(desc1, b, y, x, c)]; + const int32_t input2_val = + params.input2_offset + + input2_data[SubscriptToIndex(desc2, b, y, x, c)]; + const int32_t unclamped_result = + params.output_offset + + MultiplyByQuantizedMultiplier(input1_val * input2_val, + params.output_multiplier, + params.output_shift); + const int32_t clamped_output = std::min( + params.quantized_activation_max, + std::max(params.quantized_activation_min, unclamped_result)); + output_data[Offset(extended_output_shape, b, y, x, c)] = + static_cast(clamped_output); + } + } + } + } +} + +template +void BroadcastMul4DSlow(const ArithmeticParams& params, + const RuntimeShape& unextended_input1_shape, + const T* input1_data, + const RuntimeShape& unextended_input2_shape, + const T* input2_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + T output_activation_min; + T output_activation_max; + GetActivationParams(params, &output_activation_min, &output_activation_max); + + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(unextended_input1_shape, + unextended_input2_shape, &desc1, &desc2); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + for (int b = 0; b < output_shape.Dims(0); ++b) { + for (int y = 0; y < output_shape.Dims(1); ++y) { + for (int x = 0; x < output_shape.Dims(2); ++x) { + for (int c = 0; c < output_shape.Dims(3); ++c) { + output_data[Offset(output_shape, b, y, x, c)] = + ActivationFunctionWithMinMax( + input1_data[SubscriptToIndex(desc1, b, y, x, c)] * + input2_data[SubscriptToIndex(desc2, b, y, x, c)], + output_activation_min, output_activation_max); + } + } + } + } +} + +inline void BroadcastMul4DSlow(const ArithmeticParams& params, + const RuntimeShape& unextended_input1_shape, + const std::complex* input1_data, + const RuntimeShape& unextended_input2_shape, + const std::complex* input2_data, + const RuntimeShape& unextended_output_shape, + std::complex* output_data) { + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(unextended_input1_shape, + unextended_input2_shape, &desc1, &desc2); + + for (int b = 0; b < output_shape.Dims(0); ++b) { + for (int y = 0; y < output_shape.Dims(1); ++y) { + for (int x = 0; x < output_shape.Dims(2); ++x) { + for (int c = 0; c < output_shape.Dims(3); ++c) { + output_data[Offset(output_shape, b, y, x, c)] = + input1_data[SubscriptToIndex(desc1, b, y, x, c)] * + input2_data[SubscriptToIndex(desc2, b, y, x, c)]; + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_MUL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/neg.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/neg.h new file mode 100644 index 0000000..9fc6f39 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/neg.h @@ -0,0 +1,37 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_NEG_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_NEG_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +template +inline void Negate(const RuntimeShape& input_shape, const T* input_data, + const RuntimeShape& output_shape, T* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; ++i) { + output_data[i] = -input_data[i]; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_NEG_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pad.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pad.h new file mode 100644 index 0000000..b4b2a75 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pad.h @@ -0,0 +1,169 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PAD_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PAD_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +// TFLite Pad supports activation tensors with up to 5 dimensions. +constexpr int PadKernelMaxDimensionCount() { return 5; } + +// There are two versions of pad: Pad and PadV2. In PadV2 there is a second +// scalar input that provides the padding value. Therefore pad_value_ptr can be +// equivalent to a simple input1_data. For Pad, it should point to a zero +// value. +// +// Note that two typenames are required, so that T=P=int32_t is considered a +// specialization distinct from P=int32_t. +template +inline void PadImpl(const tflite::PadParams& op_params, + const RuntimeShape& input_shape, const T* input_data, + const P* pad_value_ptr, const RuntimeShape& output_shape, + T* output_data) { + const RuntimeShape ext_input_shape = + RuntimeShape::ExtendedShape(PadKernelMaxDimensionCount(), input_shape); + const RuntimeShape ext_output_shape = + RuntimeShape::ExtendedShape(PadKernelMaxDimensionCount(), output_shape); + TFLITE_DCHECK_LE(op_params.left_padding_count, PadKernelMaxDimensionCount()); + TFLITE_DCHECK_LE(op_params.right_padding_count, PadKernelMaxDimensionCount()); + + // Runtime calls are currently fixed at 5 dimensions. Copy inputs so we can + // pad them to 5 dims (yes, we are "padding the padding"). + int left_padding_copy[PadKernelMaxDimensionCount()]; + for (int i = 0; i < PadKernelMaxDimensionCount(); i++) { + left_padding_copy[i] = 0; + } + for (int i = 0; i < op_params.left_padding_count; ++i) { + left_padding_copy[i + PadKernelMaxDimensionCount() - + op_params.left_padding_count] = op_params.left_padding[i]; + } + int right_padding_copy[PadKernelMaxDimensionCount()]; + for (int i = 0; i < PadKernelMaxDimensionCount(); i++) { + right_padding_copy[i] = 0; + } + for (int i = 0; i < op_params.right_padding_count; ++i) { + right_padding_copy[i + PadKernelMaxDimensionCount() - + op_params.right_padding_count] = + op_params.right_padding[i]; + } + + const int output_batch = ext_output_shape.Dims(0); + const int output_plane = ext_output_shape.Dims(1); + const int output_height = ext_output_shape.Dims(2); + const int output_width = ext_output_shape.Dims(3); + const int output_depth = ext_output_shape.Dims(4); + + const int left_b_padding = left_padding_copy[0]; + const int left_p_padding = left_padding_copy[1]; + const int left_h_padding = left_padding_copy[2]; + const int left_w_padding = left_padding_copy[3]; + const int left_d_padding = left_padding_copy[4]; + + const int right_b_padding = right_padding_copy[0]; + const int right_p_padding = right_padding_copy[1]; + const int right_h_padding = right_padding_copy[2]; + const int right_w_padding = right_padding_copy[3]; + const int right_d_padding = right_padding_copy[4]; + + const T pad_value = *pad_value_ptr; + + const T* in_ptr = input_data; + T* out_ptr = output_data; + for (int out_b = 0; out_b < output_batch; ++out_b) { + for (int out_p = 0; out_p < output_plane; ++out_p) { + for (int out_h = 0; out_h < output_height; ++out_h) { + for (int out_w = 0; out_w < output_width; ++out_w) { + for (int out_d = 0; out_d < output_depth; ++out_d) { + if (out_b < left_b_padding || + out_b >= output_batch - right_b_padding || + out_p < left_p_padding || + out_p >= output_plane - right_p_padding || + out_h < left_h_padding || + out_h >= output_height - right_h_padding || + out_w < left_w_padding || + out_w >= output_width - right_w_padding || + out_d < left_d_padding || + out_d >= output_depth - right_d_padding) { + *out_ptr++ = pad_value; + } else { + *out_ptr++ = *in_ptr++; + } + } + } + } + } + } +} + +template +inline void Pad(const tflite::PadParams& op_params, + const RuntimeShape& input_shape, const T* input_data, + const P* pad_value_ptr, const RuntimeShape& output_shape, + T* output_data) { + PadImpl(op_params, input_shape, input_data, pad_value_ptr, output_shape, + output_data); +} + +// The second (pad-value) input can be int32_t when, say, the first is uint8_t. +template +inline void Pad(const tflite::PadParams& op_params, + const RuntimeShape& input_shape, const T* input_data, + const int32_t* pad_value_ptr, const RuntimeShape& output_shape, + T* output_data) { + const T converted_pad_value = static_cast(*pad_value_ptr); + PadImpl(op_params, input_shape, input_data, &converted_pad_value, + output_shape, output_data); +} + +// This version avoids conflicting template matching. +template <> +inline void Pad(const tflite::PadParams& op_params, + const RuntimeShape& input_shape, const int32_t* input_data, + const int32_t* pad_value_ptr, const RuntimeShape& output_shape, + int32_t* output_data) { + PadImpl(op_params, input_shape, input_data, pad_value_ptr, output_shape, + output_data); +} + +template +inline void PadImageStyle(const tflite::PadParams& op_params, + const RuntimeShape& input_shape, const T* input_data, + const P* pad_value_ptr, + const RuntimeShape& output_shape, T* output_data) { + Pad(op_params, input_shape, input_data, pad_value_ptr, output_shape, + output_data); +} + +template +inline void PadImageStyle(const tflite::PadParams& op_params, + const RuntimeShape& input_shape, + const float* input_data, const P* pad_value_ptr, + const RuntimeShape& output_shape, + float* output_data) { + Pad(op_params, input_shape, input_data, pad_value_ptr, output_shape, + output_data); +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PAD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h new file mode 100644 index 0000000..3657ffd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h @@ -0,0 +1,303 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_POOLING_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_POOLING_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +inline bool AveragePool(const PoolParams& params, + const RuntimeShape& input_shape, + const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + float total = 0.f; + float filter_count = 0; + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + total += + input_data[Offset(input_shape, batch, in_y, in_x, channel)]; + filter_count++; + } + } + if (filter_count == 0) return false; + const float average = total / filter_count; + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + ActivationFunctionWithMinMax(average, params.float_activation_min, + params.float_activation_max); + } + } + } + } + return true; +} + +inline bool AveragePool(const PoolParams& params, + const RuntimeShape& input_shape, + const uint8_t* input_data, + const RuntimeShape& output_shape, + uint8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + int32_t acc = 0; + int filter_count = 0; + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + acc += + input_data[Offset(input_shape, batch, in_y, in_x, channel)]; + filter_count++; + } + } + if (filter_count == 0) return false; + acc = (acc + filter_count / 2) / filter_count; + acc = std::max(acc, params.quantized_activation_min); + acc = std::min(acc, params.quantized_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + static_cast(acc); + } + } + } + } + return true; +} + +inline void L2Pool(const PoolParams& params, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& output_shape, + float* output_data) { + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + float sum_squares = 0.f; + int filter_count = 0; + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + const float val = + input_data[Offset(input_shape, batch, in_y, in_x, channel)]; + sum_squares += val * val; + filter_count++; + } + } + const float l2pool_result = std::sqrt(sum_squares / filter_count); + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + ActivationFunctionWithMinMax(l2pool_result, + params.float_activation_min, + params.float_activation_max); + } + } + } + } +} + +inline void MaxPool(const PoolParams& params, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& output_shape, + float* output_data) { + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + float max = std::numeric_limits::lowest(); + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + max = std::max( + max, + input_data[Offset(input_shape, batch, in_y, in_x, channel)]); + } + } + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + ActivationFunctionWithMinMax(max, params.float_activation_min, + params.float_activation_max); + } + } + } + } +} + +inline void MaxPool(const PoolParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& output_shape, + uint8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + TFLITE_DCHECK_GE(params.quantized_activation_min, 0); + TFLITE_DCHECK_LE(params.quantized_activation_max, 255); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int stride_height = params.stride_height; + const int stride_width = params.stride_width; + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int channel = 0; channel < depth; ++channel) { + const int in_x_origin = + (out_x * stride_width) - params.padding_values.width; + const int in_y_origin = + (out_y * stride_height) - params.padding_values.height; + // Compute the boundaries of the filter region clamped so as to + // ensure that the filter window fits in the input array. + const int filter_x_start = std::max(0, -in_x_origin); + const int filter_x_end = + std::min(params.filter_width, input_width - in_x_origin); + const int filter_y_start = std::max(0, -in_y_origin); + const int filter_y_end = + std::min(params.filter_height, input_height - in_y_origin); + uint8_t max = 0; + for (int filter_y = filter_y_start; filter_y < filter_y_end; + ++filter_y) { + for (int filter_x = filter_x_start; filter_x < filter_x_end; + ++filter_x) { + const int in_x = in_x_origin + filter_x; + const int in_y = in_y_origin + filter_y; + max = std::max( + max, + input_data[Offset(input_shape, batch, in_y, in_x, channel)]); + } + } + max = std::max(max, params.quantized_activation_min); + max = std::min(max, params.quantized_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, channel)] = + static_cast(max); + } + } + } + } +} +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_POOLING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/prelu.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/prelu.h new file mode 100644 index 0000000..6d1dbe0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/prelu.h @@ -0,0 +1,111 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PRELU_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PRELU_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +// Broadcast prelu to output_shape for quantized uint8_t/int8_t data. +template +inline void BroadcastPrelu4DSlow( + const PreluParams& params, const RuntimeShape& input_shape, + const T* input_data, const RuntimeShape& alpha_shape, const T* alpha_data, + const RuntimeShape& output_shape, T* output_data) { + TFLITE_DCHECK_LE(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(alpha_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(output_shape.DimensionsCount(), 4); + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(4, output_shape); + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(input_shape, alpha_shape, &desc1, &desc2); + + for (int b = 0; b < extended_output_shape.Dims(0); ++b) { + for (int y = 0; y < extended_output_shape.Dims(1); ++y) { + for (int x = 0; x < extended_output_shape.Dims(2); ++x) { + for (int c = 0; c < extended_output_shape.Dims(3); ++c) { + int output_index = Offset(extended_output_shape, b, y, x, c); + int input_index = SubscriptToIndex(desc1, b, y, x, c); + const int32_t input_value = + params.input_offset + input_data[input_index]; + int32_t output_value; + if (input_value >= 0) { + output_value = MultiplyByQuantizedMultiplier( + input_value, params.output_multiplier_1, params.output_shift_1); + } else { + auto alpha_index = SubscriptToIndex(desc2, b, y, x, c); + const int32_t alpha_value = + params.alpha_offset + alpha_data[alpha_index]; + + output_value = MultiplyByQuantizedMultiplier( + input_value * alpha_value, params.output_multiplier_2, + params.output_shift_2); + } + output_value += params.output_offset; + + const int32_t quantized_min = std::numeric_limits::min(); + const int32_t quantized_max = std::numeric_limits::max(); + const int32_t clamped_output = + std::min(quantized_max, std::max(quantized_min, output_value)); + output_data[output_index] = static_cast(clamped_output); + } + } + } + } +} + +template +inline void Prelu(const PreluParams& params, const RuntimeShape& input_shape, + const T* input_data, const RuntimeShape& alpha_shape, + const T* alpha_data, const RuntimeShape& output_shape, + T* output_data) { + const int32_t quantized_min = std::numeric_limits::min(); + const int32_t quantized_max = std::numeric_limits::max(); + + const int flat_size = + MatchingElementsSize(input_shape, alpha_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + const int32_t input_value = params.input_offset + input_data[i]; + int32_t output_value; + if (input_value >= 0) { + output_value = MultiplyByQuantizedMultiplier( + input_value, params.output_multiplier_1, params.output_shift_1); + } else { + const int32_t alpha_value = params.alpha_offset + alpha_data[i]; + + output_value = MultiplyByQuantizedMultiplier(input_value * alpha_value, + params.output_multiplier_2, + params.output_shift_2); + } + output_value += params.output_offset; + + const int32_t clamped_output = + std::min(quantized_max, std::max(quantized_min, output_value)); + output_data[i] = static_cast(clamped_output); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PRELU_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h new file mode 100644 index 0000000..760f54d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h @@ -0,0 +1,140 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PROCESS_BROADCAST_SHAPES_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PROCESS_BROADCAST_SHAPES_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +// Consolidates dimensions in broadcast inputs, checks for five-fold pattern. +// +// For example, if sequence of dimensions of one input is +// ..., 1, 3, 1, 7, 9, 5,... and the other is ..., 2, 3, 1, 7, 1, 1, ... +// we can consolidate these as +// ..., 1, 3*7, 9*5, ... and 2, 3*7, 1. +// +// The category is updated in the less-frequent case of shapes that are +// not suited to a fivefold-loop broadcast. +// +// Falls back to generic pattern when it does not know how to process properly. +// +// Returns true iff there is some sort of broadcast, which includes five-fold +// patterns and falling back to generic broadcast. +inline bool ProcessBroadcastShapes(const RuntimeShape& shape0, + const RuntimeShape& shape1, + tflite::ArithmeticParams* params) { + const int dims_count = + std::max(shape0.DimensionsCount(), shape1.DimensionsCount()); + + params->broadcast_category = BroadcastableOpCategory::kGenericBroadcast; + RuntimeShape scalar_shape(dims_count, 1); + + auto extended_shape0 = RuntimeShape::ExtendedShape(dims_count, shape0); + auto extended_shape1 = RuntimeShape::ExtendedShape(dims_count, shape1); + + // Check for "exact" match, implicitly accepting any scalar shapes. + if (extended_shape0 == extended_shape1) { + params->broadcast_category = BroadcastableOpCategory::kNonBroadcast; + return false; + } + + for (int i = dims_count - 1; i >= 0; --i) { + if (extended_shape0.Dims(i) == extended_shape1.Dims(i)) { + continue; + } else if (extended_shape0.Dims(i) == 1) { + params->broadcast_category = + BroadcastableOpCategory::kFirstInputBroadcastsFast; + break; + } else if (extended_shape1.Dims(i) == 1) { + params->broadcast_category = + BroadcastableOpCategory::kSecondInputBroadcastsFast; + break; + } else { + // This case is erroneous: there is a dimension that does not match and + // is not a broadcast from one shape to the other. + params->broadcast_category = BroadcastableOpCategory::kGenericBroadcast; + return true; + } + } + + if (params->broadcast_category != + BroadcastableOpCategory::kFirstInputBroadcastsFast && + params->broadcast_category != + BroadcastableOpCategory::kSecondInputBroadcastsFast) { + // This is unreachable because at least one else clause in the above loop + // must be reached. + TFLITE_DCHECK(false); + params->broadcast_category = BroadcastableOpCategory::kNonBroadcast; + return false; + } + + // From this point it is assumed contractually that corresponding dimensions + // in shape0 and shape1 are either (a) equal or (b) one or other equals 1. + const bool swap_inputs = params->broadcast_category == + BroadcastableOpCategory::kSecondInputBroadcastsFast; + const RuntimeShape* shape_a = + swap_inputs ? &extended_shape1 : &extended_shape0; + const RuntimeShape* shape_b = + swap_inputs ? &extended_shape0 : &extended_shape1; + + int i = dims_count - 1; + params->broadcast_shape[0] = 1; + params->broadcast_shape[1] = 1; + params->broadcast_shape[2] = 1; + params->broadcast_shape[3] = 1; + params->broadcast_shape[4] = 1; + // y_0 is greedy: include dims if both or neither equal 1: in other words, + // test for equality rather than (shape_a->Dims(i) != 1). + while (i >= 0 && shape_a->Dims(i) == shape_b->Dims(i)) { + params->broadcast_shape[4] *= shape_b->Dims(i); + --i; + } + // Here either input_a or input_b has dim of 1 (if i >= 0). If it is input_b + // that has the unit dimension, the next two loops are not entered. + while (i >= 0 && shape_a->Dims(i) == 1) { + params->broadcast_shape[3] *= shape_b->Dims(i); + --i; + } + while (i >= 0 && shape_a->Dims(i) == shape_b->Dims(i)) { + params->broadcast_shape[2] *= shape_a->Dims(i); + --i; + } + // Here either input_a or input_b has dim of 1 (if i >= 0). + while (i >= 0 && shape_b->Dims(i) == 1) { + params->broadcast_shape[1] *= shape_a->Dims(i); + --i; + } + while (i >= 0 && shape_a->Dims(i) == shape_b->Dims(i)) { + params->broadcast_shape[0] *= shape_b->Dims(i); + --i; + } + + // Rarer case is when the broadcast dimensions cannot be handled by a fivefold + // loop. + if (i >= 0) { + params->broadcast_category = BroadcastableOpCategory::kGenericBroadcast; + } + return true; +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PROCESS_BROADCAST_SHAPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/quantize.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/quantize.h new file mode 100644 index 0000000..b791413 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/quantize.h @@ -0,0 +1,89 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_QUANTIZE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_QUANTIZE_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +template +inline void AffineQuantize(const tflite::QuantizationParams& op_params, + const RuntimeShape& input_shape, + const InputT* input_data, + const RuntimeShape& output_shape, + OutputT* output_data) { + const int32_t zero_point = op_params.zero_point; + const double scale = op_params.scale; + const int flat_size = MatchingFlatSize(input_shape, output_shape); + static constexpr int32_t min_val = std::numeric_limits::min(); + static constexpr int32_t max_val = std::numeric_limits::max(); + + for (int i = 0; i < flat_size; i++) { + const InputT val = input_data[i]; + int32_t unclamped = + static_cast(TfLiteRound(val / static_cast(scale))) + + zero_point; + int32_t clamped = std::min(std::max(unclamped, min_val), max_val); + output_data[i] = clamped; + } +} + +// Quantizes per-channel. +template +inline void PerChannelQuantize( + const tflite::PerChannelQuantizationParams& op_params, + const RuntimeShape& input_shape, const InputT* input_data, + const RuntimeShape& output_shape, OutputT* output_data) { + // Ensure flat size is same. + MatchingFlatSize(input_shape, output_shape); + + const int32_t* zero_point = op_params.zero_point; + const float* scale = op_params.scale; + const int32_t quantized_dimension = op_params.quantized_dimension; + const int32_t num_dims = input_shape.DimensionsCount(); + const int32_t* dims_data = input_shape.DimsData(); + std::vector current_dim(num_dims, 0); + static constexpr int32_t min_val = std::numeric_limits::min(); + static constexpr int32_t max_val = std::numeric_limits::max(); + + do { + size_t offset = + ReducedOutputOffset(num_dims, reinterpret_cast(dims_data), + current_dim.data(), 0, nullptr); + const InputT val = input_data[offset]; + const int channel = current_dim[quantized_dimension]; + int32_t unclamped = static_cast(TfLiteRound( + val / static_cast(scale[channel]))) + + zero_point[channel]; + int32_t clamped = std::min(std::max(unclamped, min_val), max_val); + output_data[offset] = static_cast(clamped); + } while (NextIndex(num_dims, reinterpret_cast(dims_data), + current_dim.data())); +} + +} // namespace reference_ops + +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_QUANTIZE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/reduce.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/reduce.h new file mode 100644 index 0000000..54f24f4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/reduce.h @@ -0,0 +1,542 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_REDUCE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_REDUCE_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/max.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/min.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +// Check if the reduction at index is the first one along the dimensions given +// in axis. +inline bool IsFirstReduction(const int* index, const int num_axis, + const int* axis) { + if (num_axis == 0) { + return true; + } + + TFLITE_DCHECK(index != nullptr); + TFLITE_DCHECK(axis != nullptr); + for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx) { + if (index[axis[axis_idx]] != 0) { + return false; + } + } + + return true; +} + +namespace tflite { + +namespace reference_ops { + +// A generic reduce method that can be used for reduce_sum, reduce_mean, etc. +// This method iterates through input data and reduce elements along the +// dimensions given in axis. +template +inline bool Reduce(const In* input_data, const int* input_dims, + const int* output_dims, const int input_num_dims, + const int output_num_dims, const int* axis, + const int num_axis, int* input_iter, + Out reducer(Out current, const In in), Out* output_data) { + // Reset input iterator. + for (int idx = 0; idx < input_num_dims; ++idx) { + input_iter[idx] = 0; + } + // Iterate through input_data. + do { + size_t input_offset = + ReducedOutputOffset(input_num_dims, input_dims, input_iter, 0, nullptr); + size_t output_offset = ReducedOutputOffset(input_num_dims, input_dims, + input_iter, num_axis, axis); + output_data[output_offset] = + reducer(output_data[output_offset], input_data[input_offset]); + } while (NextIndex(input_num_dims, input_dims, input_iter)); + return true; +} + +// Similar to above Reduce function but takes two reducer functions. +// The 'reducer_first' is called with the first value of the reduction, +// 'reducer_next' is then called for all the others. +template +inline bool Reduce(const In* input_data, const int* input_dims, + const int* output_dims, const int input_num_dims, + const int output_num_dims, const int* axis, + const int num_axis, int* input_iter, + const std::function& reducer_first, + const std::function& reducer_next, + Out* output_data) { + // Reset input iterator. + for (int idx = 0; idx < input_num_dims; ++idx) { + input_iter[idx] = 0; + } + // Iterate through input_data. + do { + size_t input_offset = + ReducedOutputOffset(input_num_dims, input_dims, input_iter, 0, nullptr); + size_t output_offset = ReducedOutputOffset(input_num_dims, input_dims, + input_iter, num_axis, axis); + if (IsFirstReduction(input_iter, num_axis, axis)) { + output_data[output_offset] = reducer_first(input_data[input_offset]); + } else { + output_data[output_offset] = + reducer_next(output_data[output_offset], input_data[input_offset]); + } + } while (NextIndex(input_num_dims, input_dims, input_iter)); + return true; +} + +// This method parses the input 'axis' to remove duplicates and handle negative +// values, and returns a valid 'out_axis' +inline bool ResolveAxis(const int num_dims, const int* axis, + const int64_t num_axis, int* out_axis, + int* out_num_axis) { + *out_num_axis = 0; // Just in case. + // Short-circuit axis resolution for scalars; the axis will go unused. + if (num_dims == 0) { + return true; + } + // o(n^2) is fine since out_num_axis should be really small, mostly <= 4 + for (int64_t idx = 0; idx < num_axis; ++idx) { + // Handle negative index. A positive index 'p_idx' can be represented as a + // negative index 'n_idx' as: n_idx = p_idx-num_dims + // eg: For num_dims=3, [0, 1, 2] is the same as [-3, -2, -1] */ + int current = axis[idx] < 0 ? (axis[idx] + num_dims) : axis[idx]; + TFLITE_DCHECK(current >= 0 && current < num_dims); + if (current < 0 || current >= num_dims) { + return false; + } + bool is_dup = false; + for (int j = 0; j < *out_num_axis; ++j) { + if (out_axis[j] == current) { + is_dup = true; + break; + } + } + if (!is_dup) { + out_axis[*out_num_axis] = current; + *out_num_axis += 1; + } + } + return true; +} + +// This method expects that output_data has been initialized. +template +inline bool ReduceSumImpl(const In* input_data, const int* input_dims, + const int* output_dims, const int input_num_dims, + const int output_num_dims, const int* axis, + const int num_axis, int* input_iter, + Out* output_data) { + auto reducer = [](const Out current, const In in) -> Out { + const Out actual_in = static_cast(in); + return current + actual_in; + }; + return Reduce(input_data, input_dims, output_dims, input_num_dims, + output_num_dims, axis, num_axis, input_iter, reducer, + output_data); +} + +template +inline bool InitTensorDataForReduce(const int* dims, const int num_dims, + const T init_value, T* data) { + size_t num_elements = 1; + for (int idx = 0; idx < num_dims; ++idx) { + size_t current = static_cast(dims[idx]); + // Overflow prevention. + if (current > 0 && + num_elements > std::numeric_limits::max() / current) { + return false; + } + num_elements *= current; + } + for (size_t idx = 0; idx < num_elements; ++idx) { + data[idx] = init_value; + } + return true; +} + +// Computes the generic value (i.e., sum/max/min/prod) of elements across +// dimensions given in axis. It needs to pass in init_value and reducer. +template +inline bool ReduceGeneric(const T* input_data, const int* input_dims, + const int input_num_dims, T* output_data, + const int* output_dims, const int output_num_dims, + const int* axis, const int64_t num_axis_dimensions, + bool keep_dims, int* temp_index, int* resolved_axis, + T init_value, + T reducer(const T current, const T in)) { + // Reset output data. + if (!InitTensorDataForReduce(output_dims, output_num_dims, init_value, + output_data)) { + return false; + } + + // Return early when input shape has zero dim. This is done after initializing + // data for output tensor because there are cases that the input tensor is + // empty but output tensor is not. In that case, output tensor should be + // filled with init_value. + for (int i = 0; i < input_num_dims; ++i) { + if (input_dims[i] == 0) return true; + } + + // Resolve axis. + int num_resolved_axis = 0; + if (!ResolveAxis(input_num_dims, axis, num_axis_dimensions, resolved_axis, + &num_resolved_axis)) { + return false; + } + + return Reduce(input_data, input_dims, output_dims, input_num_dims, + output_num_dims, resolved_axis, num_resolved_axis, + temp_index, reducer, output_data); +} + +// Computes the mean of elements across dimensions given in axis. +// It does so in two stages, first calculates the sum of elements along the axis +// then divides it by the number of element in axis. +template +inline bool Mean(const T* input_data, const int* input_dims, + const int input_num_dims, T* output_data, + const int* output_dims, const int output_num_dims, + const int* axis, const int num_axis_dimensions, bool keep_dims, + int* temp_index, int* resolved_axis, U* temp_sum) { + ruy::profiler::ScopeLabel label("Mean"); + // Reset output data. + size_t num_outputs = 1; + for (int idx = 0; idx < output_num_dims; ++idx) { + size_t current = static_cast(output_dims[idx]); + // Overflow prevention. + if (num_outputs > std::numeric_limits::max() / current) { + return false; + } + num_outputs *= current; + } + for (size_t idx = 0; idx < num_outputs; ++idx) { + output_data[idx] = T(); + temp_sum[idx] = U(); + } + + // Resolve axis. + int num_resolved_axis = 0; + if (!ResolveAxis(input_num_dims, axis, num_axis_dimensions, resolved_axis, + &num_resolved_axis)) { + return false; + } + + if (!ReduceSumImpl(input_data, input_dims, output_dims, input_num_dims, + output_num_dims, resolved_axis, num_resolved_axis, + temp_index, temp_sum)) { + return false; + } + + // Calculate mean by dividing output_data by num of aggregated element. + size_t num_elements_in_axis = 1; + for (int idx = 0; idx < num_resolved_axis; ++idx) { + size_t current = static_cast(input_dims[resolved_axis[idx]]); + // Overflow prevention. + if (current > (std::numeric_limits::max() / num_elements_in_axis)) { + return false; + } + num_elements_in_axis *= current; + } + + if (num_elements_in_axis > 0) { + for (size_t idx = 0; idx < num_outputs; ++idx) { + output_data[idx] = + static_cast(temp_sum[idx] / static_cast(num_elements_in_axis)); + } + } + return true; +} + +template +inline void Mean(const tflite::MeanParams& op_params, + const RuntimeShape& unextended_input_shape, + const T* input_data, + const RuntimeShape& unextended_output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("Mean4D"); + + // Current implementation only supports dimension equals 4 and simultaneous + // reduction over width and height. + TFLITE_CHECK_EQ(unextended_input_shape.DimensionsCount(), 4); + TFLITE_CHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + const int output_batch = output_shape.Dims(0); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int output_depth = output_shape.Dims(3); + + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + + TFLITE_CHECK_EQ(op_params.axis_count, 2); + TFLITE_CHECK((op_params.axis[0] == 1 && op_params.axis[1] == 2) || + (op_params.axis[0] == 2 && op_params.axis[1] == 1)); + TFLITE_CHECK_EQ(output_height, 1); + TFLITE_CHECK_EQ(output_width, 1); + + for (int out_b = 0; out_b < output_batch; ++out_b) { + for (int out_d = 0; out_d < output_depth; ++out_d) { + float value = 0; + for (int in_h = 0; in_h < input_height; ++in_h) { + for (int in_w = 0; in_w < input_width; ++in_w) { + value += input_data[Offset(input_shape, out_b, in_h, in_w, out_d)]; + } + } + output_data[Offset(output_shape, out_b, 0, 0, out_d)] = + value / (input_width * input_height); + } + } +} + +inline void Mean(const tflite::MeanParams& op_params, + const RuntimeShape& unextended_input_shape, + const uint8_t* input_data, int32_t input_zero_point, + float input_scale, const RuntimeShape& unextended_output_shape, + uint8_t* output_data, int32_t output_zero_point, + float output_scale) { + ruy::profiler::ScopeLabel label("Mean4D/Uint8"); + + // Current implementation only supports dimension equals 4 and simultaneous + // reduction over width and height. + TFLITE_CHECK_EQ(unextended_input_shape.DimensionsCount(), 4); + TFLITE_CHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + const int output_batch = output_shape.Dims(0); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int output_depth = output_shape.Dims(3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const float num_elements_in_axis = input_width * input_height; + + TFLITE_CHECK_EQ(op_params.axis_count, 2); + TFLITE_CHECK((op_params.axis[0] == 1 && op_params.axis[1] == 2) || + (op_params.axis[0] == 2 && op_params.axis[1] == 1)); + TFLITE_CHECK_EQ(output_height, 1); + TFLITE_CHECK_EQ(output_width, 1); + + constexpr int32_t kMinValue = std::numeric_limits::min(); + constexpr int32_t kMaxValue = std::numeric_limits::max(); + + float temp = input_zero_point * input_scale / output_scale; + temp = temp > 0 ? temp + 0.5f : temp - 0.5f; + int32_t bias = output_zero_point - static_cast(temp); + double real_scale = + static_cast(input_scale / (num_elements_in_axis * output_scale)); + + int32_t multiplier; + int shift; + QuantizeMultiplier(real_scale, &multiplier, &shift); + for (int out_b = 0; out_b < output_batch; ++out_b) { + for (int out_d = 0; out_d < output_depth; ++out_d) { + int32_t acc = 0; + for (int in_h = 0; in_h < input_height; ++in_h) { + for (int in_w = 0; in_w < input_width; ++in_w) { + acc += input_data[Offset(input_shape, out_b, in_h, in_w, out_d)]; + } + } + acc = MultiplyByQuantizedMultiplier(acc, multiplier, shift); + acc += bias; + acc = std::min(std::max(acc, kMinValue), kMaxValue); + output_data[Offset(output_shape, out_b, 0, 0, out_d)] = + static_cast(acc); + } + } +} + +// Computes the mean of elements across dimensions given in axis. +// It does so in two stages, first calculates the sum of elements along the axis +// then divides it by the number of element in axis for quantized values. +template +inline bool QuantizedMeanOrSum(const T* input_data, int32_t input_zero_point, + float input_scale, const int* input_dims, + const int input_num_dims, T* output_data, + int32_t output_zero_point, float output_scale, + const int* output_dims, + const int output_num_dims, const int* axis, + const int num_axis_dimensions, bool keep_dims, + int* temp_index, int* resolved_axis, U* temp_sum, + bool compute_sum) { + const bool uint8_case = std::is_same::value; + const bool int16_case = std::is_same::value; + if (uint8_case) { + ruy::profiler::ScopeLabel label(compute_sum ? "Sum/Uint8" : "Mean/Uint8"); + } else if (int16_case) { + ruy::profiler::ScopeLabel label(compute_sum ? "Sum/Int16" : "Mean/Int16"); + } else { + ruy::profiler::ScopeLabel label(compute_sum ? "Sum/Int8" : "Mean/Int8"); + } + // Reset output data. + size_t num_outputs = 1; + for (int idx = 0; idx < output_num_dims; ++idx) { + size_t current = static_cast(output_dims[idx]); + // Overflow prevention. + if (num_outputs > std::numeric_limits::max() / current) { + return false; + } + num_outputs *= current; + } + for (size_t idx = 0; idx < num_outputs; ++idx) { + output_data[idx] = T(); + temp_sum[idx] = U(); + } + + // Return early when input shape has zero dim. This is done after initializing + // data for output tensor because there are cases that the input tensor is + // empty but output tensor is not. In that case, output tensor should be + // filled with init_value. + for (int i = 0; i < input_num_dims; ++i) { + if (input_dims[i] == 0) return true; + } + + // Resolve axis. + int num_resolved_axis = 0; + if (!ResolveAxis(input_num_dims, axis, num_axis_dimensions, resolved_axis, + &num_resolved_axis)) { + return false; + } + + if (!ReduceSumImpl(input_data, input_dims, output_dims, input_num_dims, + output_num_dims, resolved_axis, num_resolved_axis, + temp_index, temp_sum)) { + return false; + } + + // Calculate mean by dividing output_data by num of aggregated element. + size_t num_elements_in_axis = 1; + for (int idx = 0; idx < num_resolved_axis; ++idx) { + size_t current = static_cast(input_dims[resolved_axis[idx]]); + // Overflow prevention. + if (current > (std::numeric_limits::max() / num_elements_in_axis)) { + return false; + } + num_elements_in_axis *= current; + } + + if (num_elements_in_axis > 0) { + const float scale = input_scale / output_scale; + if (compute_sum) { + // TODO(b/116341117): Eliminate float and do this completely in 8bit. + const float bias = -input_zero_point * scale * num_elements_in_axis; + for (size_t idx = 0; idx < num_outputs; ++idx) { + const U value = + static_cast(TfLiteRound(temp_sum[idx] * scale + bias)) + + output_zero_point; + output_data[idx] = static_cast(value); + } + } else { + const float bias = -input_zero_point * scale; + for (size_t idx = 0; idx < num_outputs; ++idx) { + float float_mean = static_cast(temp_sum[idx]) / + static_cast(num_elements_in_axis); + float result = TfLiteMin( + TfLiteRound(float_mean * scale + bias) + output_zero_point, + static_cast(std::numeric_limits::max())); + result = TfLiteMax(result, + static_cast(std::numeric_limits::min())); + output_data[idx] = static_cast(result); + } + } + } + return true; +} + +template +inline bool QuantizedMeanOrSumExtraArgs( + const T* input_data, int32_t input_zero_point, float input_scale, + const int* input_dims, const int input_num_dims, T* output_data, + float output_scale, int32_t output_multiplier, int output_shift, + int32_t output_zero_point, const int* output_dims, + const int output_num_dims, const int* axis, const int num_axis_dimensions, + bool keep_dims, int* temp_index, int* resolved_axis, U* temp_sum, + bool compute_sum) { + return QuantizedMeanOrSum( + input_data, input_zero_point, input_scale, input_dims, input_num_dims, + output_data, output_zero_point, output_scale, output_dims, + output_num_dims, axis, num_axis_dimensions, keep_dims, temp_index, + resolved_axis, temp_sum, compute_sum); +} + +template +inline bool QuantizedReduceProd(const T* input_data, int32_t input_zero_point, + const RuntimeShape& input_shape, T* output_data, + int32_t output_zero_point, + const RuntimeShape& output_shape, + const int* axis, + const int64_t num_axis_dimensions, + bool keep_dims, int* temp_index, + int* resolved_axis, int32_t* temp_prod, + int32_t scaling_multiplier, int scaling_shift) { + const int32_t kMinValue = std::numeric_limits::min(); + const int32_t kMaxValue = std::numeric_limits::max(); + + // Resolve axis. + int num_resolved_axis = 0; + if (!ResolveAxis(input_shape.DimensionsCount(), axis, num_axis_dimensions, + resolved_axis, &num_resolved_axis)) { + return false; + } + + // Calculate the reduced product by rescaling each multiplication step to + // avoid an overflow. + auto reducer_first = [&](T in) -> int32_t { return in - input_zero_point; }; + + auto reducer_next = [&](int32_t current, T in) -> int32_t { + const int64_t result = + static_cast(current) * (in - input_zero_point); + return MultiplyByQuantizedMultiplier(result, scaling_multiplier, + scaling_shift); + }; + + if (!Reduce( + input_data, input_shape.DimsData(), output_shape.DimsData(), + input_shape.DimensionsCount(), output_shape.DimensionsCount(), + resolved_axis, num_resolved_axis, temp_index, reducer_first, + reducer_next, temp_prod)) { + return false; + } + + for (int i = 0; i < output_shape.FlatSize(); i++) { + int32_t result = + MultiplyByQuantizedMultiplier(static_cast(temp_prod[i]), + scaling_multiplier, scaling_shift) + + output_zero_point; + result = std::min(std::max(result, kMinValue), kMaxValue); + output_data[i] = static_cast(result); + } + + return true; +} + +} // namespace reference_ops + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_REDUCE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/requantize.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/requantize.h new file mode 100644 index 0000000..662046f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/requantize.h @@ -0,0 +1,70 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_REQUANTIZE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_REQUANTIZE_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +inline void Requantize(const input_type* input_data, int32_t size, + int32_t effective_scale_multiplier, + int32_t effective_scale_shift, int32_t input_zeropoint, + int32_t output_zeropoint, output_type* output_data) { + ruy::profiler::ScopeLabel label("Requantize"); + const bool same_scale = + (effective_scale_multiplier == 1 << 30 && effective_scale_shift == 1); + if (same_scale) { + const bool mixed_type_int8_uint8 = + std::is_same::value && + std::is_same::value; + const bool mixed_type_uint8_int8 = + std::is_same::value && + std::is_same::value; + const int32_t zero_point_diff = input_zeropoint - output_zeropoint; + // Fast path to do requantization for the case when just a shift of 128 is + // needed. + if ((mixed_type_int8_uint8 && zero_point_diff == -128) || + (mixed_type_uint8_int8 && zero_point_diff == 128)) { + for (int i = 0; i < size; ++i) { + output_data[i] = input_data[i] ^ 0x80; + } + return; + } + } + static constexpr int32_t kMinOutput = std::numeric_limits::min(); + static constexpr int32_t kMaxOutput = std::numeric_limits::max(); + for (int i = 0; i < size; ++i) { + const int32_t input = input_data[i] - input_zeropoint; + const int32_t output = + MultiplyByQuantizedMultiplier(input, effective_scale_multiplier, + effective_scale_shift) + + output_zeropoint; + const int32_t clamped_output = + std::max(std::min(output, kMaxOutput), kMinOutput); + output_data[i] = static_cast(clamped_output); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_REQUANTIZE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_bilinear.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_bilinear.h new file mode 100644 index 0000000..ec8ec26 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_bilinear.h @@ -0,0 +1,228 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_RESIZE_BILINEAR_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_RESIZE_BILINEAR_H_ + +#include +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +inline void ComputeInterpolationValues(const float value, const float scale, + const bool half_pixel_centers, + int32_t input_size, float* scaled_value, + int32_t* lower_bound, + int32_t* upper_bound) { + if (half_pixel_centers) { + *scaled_value = (value + 0.5f) * scale - 0.5f; + } else { + *scaled_value = value * scale; + } + float scaled_value_floor = std::floor(*scaled_value); + *lower_bound = std::max(static_cast(scaled_value_floor), + static_cast(0)); + *upper_bound = + std::min(static_cast(std::ceil(*scaled_value)), input_size - 1); +} + +template +inline void ResizeBilinear(const tflite::ResizeBilinearParams& op_params, + const RuntimeShape& unextended_input_shape, + const T* input_data, + const RuntimeShape& unextended_output_size_shape, + const int32_t* output_size_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + // If half_pixel_centers is True, align_corners must be False. + TFLITE_DCHECK(!op_params.half_pixel_centers || !op_params.align_corners); + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_size_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_size_shape = + RuntimeShape::ExtendedShape(4, unextended_output_size_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + int32_t batches = MatchingDim(input_shape, 0, output_shape, 0); + int32_t input_height = input_shape.Dims(1); + int32_t input_width = input_shape.Dims(2); + int32_t depth = MatchingDim(input_shape, 3, output_shape, 3); + + TFLITE_DCHECK_EQ(output_size_shape.Dims(0), 1); + TFLITE_DCHECK_EQ(output_size_shape.Dims(1), 1); + TFLITE_DCHECK_EQ(output_size_shape.Dims(2), 1); + TFLITE_DCHECK_EQ(output_size_shape.Dims(3), 2); + int32_t output_height = + output_size_data[Offset(output_size_shape, 0, 0, 0, 0)]; + int32_t output_width = + output_size_data[Offset(output_size_shape, 0, 0, 0, 1)]; + + float height_scale = static_cast(input_height) / output_height; + float width_scale = static_cast(input_width) / output_width; + if (op_params.align_corners && output_height > 1) { + height_scale = static_cast(input_height - 1) / (output_height - 1); + } + if (op_params.align_corners && output_width > 1) { + width_scale = static_cast(input_width - 1) / (output_width - 1); + } + const float rounding_offset = std::numeric_limits::is_integer ? .5f : .0f; + + for (int b = 0; b < batches; ++b) { + for (int y = 0; y < output_height; ++y) { + float input_y; + int32_t y0, y1; + ComputeInterpolationValues(y, height_scale, op_params.half_pixel_centers, + input_height, &input_y, &y0, &y1); + for (int x = 0; x < output_width; ++x) { + float input_x; + int32_t x0, x1; + ComputeInterpolationValues(x, width_scale, op_params.half_pixel_centers, + input_width, &input_x, &x0, &x1); + for (int c = 0; c < depth; ++c) { + T interpolation = + static_cast(input_data[Offset(input_shape, b, y0, x0, c)] * + (1 - (input_y - y0)) * (1 - (input_x - x0)) + + input_data[Offset(input_shape, b, y1, x0, c)] * + (input_y - y0) * (1 - (input_x - x0)) + + input_data[Offset(input_shape, b, y0, x1, c)] * + (1 - (input_y - y0)) * (input_x - x0) + + input_data[Offset(input_shape, b, y1, x1, c)] * + (input_y - y0) * (input_x - x0) + + rounding_offset); + output_data[Offset(output_shape, b, y, x, c)] = interpolation; + } + } + } + } +} + +inline void ComputeInterpolationValuesInteger( + const int32_t value, const int32_t scale_10, const bool half_pixel_centers, + int32_t input_size, int32_t* scaled_value, int32_t* lower_bound, + int32_t* upper_bound) { + if (half_pixel_centers) { + *scaled_value = value * scale_10 + scale_10 / 2 - (1 << 9); + } else { + *scaled_value = value * scale_10; + } + constexpr int32_t zero = 0; + *lower_bound = std::max(*scaled_value / (1 << 10), zero); + *upper_bound = + std::min((*scaled_value + (1 << 10) - 1) / (1 << 10), input_size - 1); +} + +// Same as above but doesn't use any floating-point for the resize +template +inline void ResizeBilinearInteger( + const tflite::ResizeBilinearParams& op_params, + const RuntimeShape& unextended_input_shape, const T* input_data, + const RuntimeShape& unextended_output_size_shape, + const int32_t* output_size_data, + const RuntimeShape& unextended_output_shape, T* output_data) { + // If half_pixel_centers is True, align_corners must be False. + TFLITE_DCHECK(!op_params.half_pixel_centers || !op_params.align_corners); + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_size_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_size_shape = + RuntimeShape::ExtendedShape(4, unextended_output_size_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + const int32_t batches = MatchingDim(input_shape, 0, output_shape, 0); + const int32_t input_height = input_shape.Dims(1); + const int32_t input_width = input_shape.Dims(2); + const int32_t depth = MatchingDim(input_shape, 3, output_shape, 3); + + TFLITE_DCHECK_EQ(output_size_shape.Dims(0), 1); + TFLITE_DCHECK_EQ(output_size_shape.Dims(1), 1); + TFLITE_DCHECK_EQ(output_size_shape.Dims(2), 1); + TFLITE_DCHECK_EQ(output_size_shape.Dims(3), 2); + const int32_t output_height = + output_size_data[Offset(output_size_shape, 0, 0, 0, 0)]; + const int32_t output_width = + output_size_data[Offset(output_size_shape, 0, 0, 0, 1)]; + + int32_t height_scale_10 = + ((1 << 10) * input_height + output_height / 2) / output_height; + int32_t width_scale_10 = + ((1 << 10) * input_width + output_width / 2) / output_width; + if (op_params.align_corners && output_height > 1) { + height_scale_10 = + ((1 << 10) * (input_height - 1) + (output_height - 1) / 2) / + (output_height - 1); + } + if (op_params.align_corners && output_width > 1) { + width_scale_10 = ((1 << 10) * (input_width - 1) + (output_width - 1) / 2) / + (output_width - 1); + } + + for (int b = 0; b < batches; ++b) { + for (int y = 0; y < output_height; ++y) { + int32_t input_y, y0, y1; + ComputeInterpolationValuesInteger(y, height_scale_10, + op_params.half_pixel_centers, + input_height, &input_y, &y0, &y1); + for (int x = 0; x < output_width; ++x) { + int32_t input_x, x0, x1; + ComputeInterpolationValuesInteger(x, width_scale_10, + op_params.half_pixel_centers, + input_width, &input_x, &x0, &x1); + for (int c = 0; c < depth; ++c) { + const int64_t output_20_ll = + static_cast( + input_data[Offset(input_shape, b, y0, x0, c)]) * + ((1 << 10) - (input_y - (1 << 10) * y0)) * + ((1 << 10) - (input_x - (1 << 10) * x0)); + const int64_t output_20_lu = + static_cast( + input_data[Offset(input_shape, b, y1, x0, c)]) * + (input_y - (1 << 10) * y0) * + ((1 << 10) - (input_x - (1 << 10) * x0)); + const int64_t output_20_rl = + static_cast( + input_data[Offset(input_shape, b, y0, x1, c)]) * + ((1 << 10) - (input_y - (1 << 10) * y0)) * + (input_x - (1 << 10) * x0); + const int64_t output_20_ru = + static_cast( + input_data[Offset(input_shape, b, y1, x1, c)]) * + (input_y - (1 << 10) * y0) * (input_x - (1 << 10) * x0); + const int64_t output_20 = + output_20_ll + output_20_lu + output_20_rl + output_20_ru; + const int64_t round = (output_20 > 0) ? (1 << 19) : -(1 << 19); + const T interpolation = + static_cast((output_20 + round) / (1 << 20)); + output_data[Offset(output_shape, b, y, x, c)] = interpolation; + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_RESIZE_BILINEAR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_nearest_neighbor.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_nearest_neighbor.h new file mode 100644 index 0000000..bbed46a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_nearest_neighbor.h @@ -0,0 +1,102 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_RESIZE_NEAREST_NEIGHBOR_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_RESIZE_NEAREST_NEIGHBOR_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline int32_t GetNearestNeighbor(const int input_value, + const int32_t input_size, + const int32_t output_size, + const bool align_corners, + const bool half_pixel_centers) { + const float scale = + (align_corners && output_size > 1) + ? (input_size - 1) / static_cast(output_size - 1) + : input_size / static_cast(output_size); + const float offset = half_pixel_centers ? 0.5f : 0.0f; + int32_t output_value = std::min( + align_corners + ? static_cast(TfLiteRound((input_value + offset) * scale)) + : static_cast(std::floor((input_value + offset) * scale)), + input_size - 1); + if (half_pixel_centers) { + output_value = std::max(static_cast(0), output_value); + } + return output_value; +} + +template +inline void ResizeNearestNeighbor( + const tflite::ResizeNearestNeighborParams& op_params, + const RuntimeShape& unextended_input_shape, const T* input_data, + const RuntimeShape& output_size_shape, const int32_t* output_size_data, + const RuntimeShape& unextended_output_shape, T* output_data) { + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + int32_t batches = MatchingDim(input_shape, 0, output_shape, 0); + int32_t input_height = input_shape.Dims(1); + int32_t input_width = input_shape.Dims(2); + int32_t depth = MatchingDim(input_shape, 3, output_shape, 3); + + // The Tensorflow version of this op allows resize on the width and height + // axis only. + TFLITE_DCHECK_EQ(output_size_shape.FlatSize(), 2); + int32_t output_height = output_size_data[0]; + int32_t output_width = output_size_data[1]; + + const int col_offset = input_shape.Dims(3); + const int row_offset = input_shape.Dims(2) * col_offset; + const int batch_offset = input_shape.Dims(1) * row_offset; + + const T* input_ptr = input_data; + T* output_ptr = output_data; + for (int b = 0; b < batches; ++b) { + for (int y = 0; y < output_height; ++y) { + int32_t in_y = GetNearestNeighbor(y, input_height, output_height, + op_params.align_corners, + op_params.half_pixel_centers); + const T* y_input_ptr = input_ptr + in_y * row_offset; + for (int x = 0; x < output_width; ++x) { + int32_t in_x = GetNearestNeighbor(x, input_width, output_width, + op_params.align_corners, + op_params.half_pixel_centers); + const T* x_input_ptr = y_input_ptr + in_x * col_offset; + memcpy(output_ptr, x_input_ptr, depth * sizeof(T)); + output_ptr += depth; + } + } + input_ptr += batch_offset; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_RESIZE_NEAREST_NEIGHBOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/round.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/round.h new file mode 100644 index 0000000..6999d1e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/round.h @@ -0,0 +1,51 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ROUND_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ROUND_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline float RoundToNearest(float value) { + auto floor_val = std::floor(value); + auto diff = value - floor_val; + if ((diff < 0.5f) || + ((diff == 0.5f) && (static_cast(floor_val) % 2 == 0))) { + return floor_val; + } else { + return floor_val = floor_val + 1.0f; + } +} + +inline void Round(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + // Note that this implementation matches that of tensorFlow tf.round + // and corresponds to the bankers rounding method. + // cfenv (for fesetround) is not yet supported universally on Android, so + // using a work around. + output_data[i] = RoundToNearest(input_data[i]); + } +} + +} // namespace reference_ops +} // namespace tflite +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_ROUND_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/select.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/select.h new file mode 100644 index 0000000..2230c96 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/select.h @@ -0,0 +1,151 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SELECT_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SELECT_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +void Select(const RuntimeShape& input_condition_shape, + const D* input_condition_data, const RuntimeShape& input_x_shape, + const T* input_x_data, const RuntimeShape& input_y_shape, + const T* input_y_data, const RuntimeShape& output_shape, + T* output_data) { + ruy::profiler::ScopeLabel label("Select"); + int64_t flatsize; + // Allow select operator executions on mixed scalar tensors and one element + // tensors. + if (input_condition_shape.FlatSize() == 1 && input_x_shape.FlatSize() == 1 && + input_y_shape.FlatSize() == 1 && output_shape.FlatSize() == 1) { + flatsize = 1; + } else { + flatsize = MatchingFlatSize(input_condition_shape, input_x_shape, + input_y_shape, output_shape); + } + for (int64_t i = 0; i < flatsize; ++i) { + output_data[i] = + input_condition_data[i] ? input_x_data[i] : input_y_data[i]; + } +} + +template +void RankOneSelect(const RuntimeShape& input_condition_shape, + const D* input_condition_data, + const RuntimeShape& input_x_shape, const T* input_x_data, + const RuntimeShape& input_y_shape, const T* input_y_data, + const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("Select/RankOneSelect"); + const int64_t outer_size = input_condition_shape.FlatSize(); + int64_t inner_size; + if (input_condition_shape.DimensionsCount() == 0) { + inner_size = MatchingFlatSize(input_x_shape, input_y_shape, output_shape); + } else { + TFLITE_DCHECK_EQ( + MatchingDim(input_x_shape, 0, input_y_shape, 0, output_shape, 0), + outer_size); + inner_size = + MatchingFlatSizeSkipDim(input_x_shape, 0, input_y_shape, output_shape); + } + + int64_t offset = 0; + for (int64_t i = 0; i < outer_size; i++) { + const T* input_data = input_condition_data[i] ? input_x_data : input_y_data; + memcpy(output_data + offset, input_data + offset, inner_size * sizeof(T)); + offset += inner_size; + } +} + +template +void BroadcastSelect5DSlow(const RuntimeShape& input_condition_shape, + const D* input_condition_data, + const RuntimeShape& input_x_shape, + const T* input_x_data, + const RuntimeShape& input_y_shape, + const T* input_y_data, + const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("Select/BroadcastSelectSlow"); + TFLITE_DCHECK_LE(input_condition_shape.DimensionsCount(), 5); + TFLITE_DCHECK_LE(input_x_shape.DimensionsCount(), 5); + TFLITE_DCHECK_LE(input_y_shape.DimensionsCount(), 5); + TFLITE_DCHECK_LE(output_shape.DimensionsCount(), 5); + + NdArrayDesc<5> desc_condition; + NdArrayDesc<5> desc_x; + NdArrayDesc<5> desc_y; + NdArrayDesc<5> desc_output; + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(5, output_shape); + CopyDimsToDesc(extended_output_shape, &desc_output); + NdArrayDescsForElementwiseBroadcast(input_condition_shape, input_x_shape, + input_y_shape, &desc_condition, &desc_x, + &desc_y); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest + // stride, typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for + // the best cache behavior. + for (int n = 0; n < desc_output.extents[0]; ++n) { + int out_idx_n = desc_output.extents[1] * n; + int cond_idx_n = desc_condition.strides[0] * n; + int in_idx1_n = desc_x.strides[0] * n; + int in_idx2_n = desc_y.strides[0] * n; + for (int b = 0; b < desc_output.extents[1]; ++b) { + int out_idx_b = (out_idx_n + b) * desc_output.extents[2]; + int cond_idx_b = cond_idx_n + desc_condition.strides[1] * b; + int in_idx1_b = in_idx1_n + desc_x.strides[1] * b; + int in_idx2_b = in_idx2_n + desc_y.strides[1] * b; + for (int y = 0; y < desc_output.extents[2]; ++y) { + int out_idx_y = (out_idx_b + y) * desc_output.extents[3]; + int cond_idx_y = cond_idx_b + desc_condition.strides[2] * y; + int in_idx1_y = in_idx1_b + desc_x.strides[2] * y; + int in_idx2_y = in_idx2_b + desc_y.strides[2] * y; + for (int x = 0; x < desc_output.extents[3]; ++x) { + int out_idx = (out_idx_y + x) * desc_output.extents[4]; + int cond_idx = cond_idx_y + desc_condition.strides[3] * x; + int in_idx1 = in_idx1_y + desc_x.strides[3] * x; + int in_idx2 = in_idx2_y + desc_y.strides[3] * x; + for (int c = 0; c < desc_output.extents[4]; ++c) { + output_data[out_idx] = input_condition_data[cond_idx] + ? input_x_data[in_idx1] + : input_y_data[in_idx2]; + out_idx++; + cond_idx += desc_condition.strides[4]; + in_idx1 += desc_x.strides[4]; + in_idx2 += desc_y.strides[4]; + } + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SELECT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/slice.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/slice.h new file mode 100644 index 0000000..8214269 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/slice.h @@ -0,0 +1,80 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SLICE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SLICE_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +template +inline void Slice(const tflite::SliceParams& op_params, + const RuntimeShape& input_shape, + const RuntimeShape& output_shape, + SequentialTensorWriter* writer) { + const RuntimeShape ext_shape = RuntimeShape::ExtendedShape(5, input_shape); + TFLITE_DCHECK_LE(op_params.begin_count, 5); + TFLITE_DCHECK_LE(op_params.size_count, 5); + const int begin_count = op_params.begin_count; + const int size_count = op_params.size_count; + // We front-pad the begin and size vectors. + int start[5]; + int stop[5]; + for (int i = 0; i < 5; ++i) { + int padded_i = 5 - i; + start[i] = + begin_count < padded_i ? 0 : op_params.begin[begin_count - padded_i]; + stop[i] = + (size_count < padded_i || op_params.size[size_count - padded_i] == -1) + ? ext_shape.Dims(i) + : start[i] + op_params.size[size_count - padded_i]; + } + + for (int i0 = start[0]; i0 < stop[0]; ++i0) { + for (int i1 = start[1]; i1 < stop[1]; ++i1) { + for (int i2 = start[2]; i2 < stop[2]; ++i2) { + for (int i3 = start[3]; i3 < stop[3]; ++i3) { + for (int i4 = start[4]; i4 < stop[4]; ++i4) { + writer->Write(Offset(ext_shape, i0, i1, i2, i3, i4)); + } + } + } + } + } +} + +template +inline void Slice(const tflite::SliceParams& op_params, + const RuntimeShape& input_shape, const T* input_data, + const RuntimeShape& output_shape, T* output_data) { + SequentialTensorWriter writer(input_data, output_data); + return Slice(op_params, input_shape, output_shape, &writer); +} + +template +inline void Slice(const tflite::SliceParams& op_params, + const RuntimeShape& input_shape, const TfLiteTensor* input, + const RuntimeShape& output_shape, TfLiteTensor* output) { + SequentialTensorWriter writer(input, output); + return Slice(op_params, input_shape, output_shape, &writer); +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SLICE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/softmax.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/softmax.h new file mode 100644 index 0000000..1c6c0b9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/softmax.h @@ -0,0 +1,233 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SOFTMAX_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SOFTMAX_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" + +namespace tflite { +namespace reference_ops { + +inline void Softmax(const SoftmaxParams& params, + const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + + for (int i = 0; i < outer_size; ++i) { + // Find max element value which we'll use to ensure numerical stability + // taking advantage of the following equality: + // exp(x[i])/sum(exp(x[i])) == exp(x[i]+C)/sum(exp(x[i]+C)) + float max = std::numeric_limits::lowest(); + for (int c = 0; c < depth; ++c) { + max = std::max(max, input_data[i * depth + c]); + } + + // Compute sum. + float sum = 0.f; + for (int c = 0; c < depth; ++c) { + const float exp_c = std::exp((input_data[i * depth + c] - max) * + static_cast(params.beta)); + output_data[i * depth + c] = exp_c; + sum += exp_c; + } + + // Compute result. + for (int c = 0; c < depth; ++c) { + output_data[i * depth + c] = output_data[i * depth + c] / sum; + } + } +} + +// Quantized softmax with int8_t/uint8_t input and int8_t/uint8_t/int16_t +// output. +template +inline void Softmax(const SoftmaxParams& params, + const RuntimeShape& input_shape, const InputT* input_data, + const RuntimeShape& output_shape, OutputT* output_data) { + const int32_t input_beta_multiplier = params.input_multiplier; + const int32_t input_beta_left_shift = params.input_left_shift; + const int diff_min = params.diff_min; + // The representation chosen for the input to the exp() function is Q5.26. + // We need to leave extra space since values that we skip might be as large as + // -32 before multiplying by input_beta_multiplier, and therefore as large as + // -16 afterwards. Note that exp(-8) is definitely not insignificant to + // accumulation, but exp(-16) definitely is. + static const int kScaledDiffIntegerBits = 5; + static const int kAccumulationIntegerBits = 12; + using FixedPointScaledDiff = + gemmlowp::FixedPoint; + using FixedPointAccum = + gemmlowp::FixedPoint; + using FixedPoint0 = gemmlowp::FixedPoint; + + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + + for (int i = 0; i < outer_size; ++i) { + InputT max_in_row = std::numeric_limits::min(); + for (int c = 0; c < depth; ++c) { + max_in_row = std::max(max_in_row, input_data[i * depth + c]); + } + + FixedPointAccum sum_of_exps = FixedPointAccum::Zero(); + for (int c = 0; c < depth; ++c) { + int32_t input_diff = + static_cast(input_data[i * depth + c]) - max_in_row; + if (input_diff >= diff_min) { + const int32_t input_diff_rescaled = + MultiplyByQuantizedMultiplierGreaterThanOne( + input_diff, input_beta_multiplier, input_beta_left_shift); + const FixedPointScaledDiff scaled_diff_f8 = + FixedPointScaledDiff::FromRaw(input_diff_rescaled); + sum_of_exps = sum_of_exps + gemmlowp::Rescale( + exp_on_negative_values(scaled_diff_f8)); + } + } + + int num_bits_over_unit; + FixedPoint0 shifted_scale = FixedPoint0::FromRaw(GetReciprocal( + sum_of_exps.raw(), kAccumulationIntegerBits, &num_bits_over_unit)); + + for (int c = 0; c < depth; ++c) { + int32_t input_diff = + static_cast(input_data[i * depth + c]) - max_in_row; + if (input_diff >= diff_min) { + const int32_t input_diff_rescaled = + MultiplyByQuantizedMultiplierGreaterThanOne( + input_diff, input_beta_multiplier, input_beta_left_shift); + const FixedPointScaledDiff scaled_diff_f8 = + FixedPointScaledDiff::FromRaw(input_diff_rescaled); + + FixedPoint0 exp_in_0 = exp_on_negative_values(scaled_diff_f8); + int32_t unsat_output = gemmlowp::RoundingDivideByPOT( + (shifted_scale * exp_in_0).raw(), + num_bits_over_unit + 31 - (sizeof(OutputT) * 8)); + + const int32_t shifted_output = + unsat_output + + static_cast(std::numeric_limits::min()); + + output_data[i * depth + c] = static_cast(std::max( + std::min(shifted_output, + static_cast(std::numeric_limits::max())), + static_cast(std::numeric_limits::min()))); + } else { + output_data[i * depth + c] = std::numeric_limits::min(); + } + } + } +} + +// Computes exp(input - max_input) +inline int16_t SoftMaxCalculateExp(const SoftmaxParams& params, + const int16_t* input_data, const int depth, + int16_t max_in_row, int i, int c) { + int32_t input_diff = input_data[i * depth + c] - max_in_row; + // scale the input_diff such that [-65535, 0] correspond to [-10.0, 0.0] + // exp lut generated with range [-10, 0], as exp(-10) is negligible. + int32_t scaled_diff = MultiplyByQuantizedMultiplier( + input_diff, params.input_multiplier, params.input_left_shift); + // recenter to [-32768, 32767] + int32_t sym_scaled_diff = scaled_diff + 32767; + int16_t sat_sym_scaled_diff = + std::min(std::max(sym_scaled_diff, static_cast(-32768)), + static_cast(32767)); + // apply the exp() LUT activation function + return LUTLookup(sat_sym_scaled_diff, params.exp_lut); +} +// Quantized softmax with int16_t input and int16_t output. +inline void SoftmaxInt16(const SoftmaxParams& params, + const RuntimeShape& input_shape, + const int16_t* input_data, + const RuntimeShape& output_shape, + int16_t* output_data) { + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + + for (int i = 0; i < outer_size; ++i) { + // Find the largest element + int16_t max_in_row = std::numeric_limits::min(); + for (int c = 0; c < depth; ++c) { + max_in_row = std::max(max_in_row, input_data[i * depth + c]); + } + + // This loops computes the exp values and their sum. We will need the exp + // values later on in the function so we cache them in the output_data + // buffer. This is an optimization done to avoid calculating the exp values + // twice making use of the output_data buffer as scratch memory. + int32_t sum_of_exps = 0; // Q16.15 fixed point format. + int16_t* exp_results_Q015 = output_data + i * depth; + for (int c = 0; c < depth; ++c) { + exp_results_Q015[c] = + SoftMaxCalculateExp(params, input_data, depth, max_in_row, i, c); + sum_of_exps += exp_results_Q015[c]; + } + + // Compute the reciprocal 1/sum_of_exps + uint8_t headroom_plus_one = + CountLeadingZeros(static_cast(sum_of_exps)); + int32_t shifted_sum = + ((static_cast(sum_of_exps) << (headroom_plus_one - 1)) + + (1 << 13)) >> + 14; + // since the LUT computes 1/(1 + x) we need to first compute x = (sum - 1). + // also, the LUT expects a symmetrical input, so we must also recenter x + // from [0, 65535] to [-32768, 32767]. + int32_t sym_shifted_sum = shifted_sum + (-((1 << 15) + (1 << 16))); + int16_t sat_sym_shifted_sum = static_cast( + std::min(std::max(sym_shifted_sum, static_cast(-32768)), + static_cast(32767))); + // apply 1/(1 + x) LUT activation function + int16_t reciprocal_scale_Q015 = + LUTLookup(sat_sym_shifted_sum, params.one_over_one_plus_x_lut); + + // Rescale the exp_result with reciprocal + // range of output is [0, 32767] correspond to [0.0, 1.0] + for (int c = 0; c < depth; ++c) { + uint8_t right_shift = 31 - headroom_plus_one; + int64_t round = 1 << (right_shift - 1); + int32_t result = (static_cast(exp_results_Q015[c]) * + static_cast(reciprocal_scale_Q015) + + round) >> + right_shift; + output_data[i * depth + c] = static_cast( + std::min(std::max(result, static_cast(0)), + static_cast(32767))); + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SOFTMAX_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_batch_nd.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_batch_nd.h new file mode 100644 index 0000000..f21a3a0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_batch_nd.h @@ -0,0 +1,109 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SPACE_TO_BATCH_ND_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SPACE_TO_BATCH_ND_H_ + +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +// TODO(b/135760455): Move this method anonymous namespace in a cc file. +inline RuntimeShape ExtendShapeSpaceToBatch(const RuntimeShape& shape) { + if (shape.DimensionsCount() == 4) { + return shape; + } + RuntimeShape new_shape(4, 1); + new_shape.SetDim(0, shape.Dims(0)); + new_shape.SetDim(1, shape.Dims(1)); + new_shape.SetDim(3, shape.Dims(2)); + return new_shape; +} + +template +inline void SpaceToBatchND(const SpaceToBatchParams& params, + const RuntimeShape& unextended_input1_shape, + const T* input1_data, + const RuntimeShape& unextended_input2_shape, + const int32_t* block_shape_data, + const RuntimeShape& unextended_input3_shape, + const int32_t* paddings_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + ruy::profiler::ScopeLabel label("SpaceToBatchND"); + TFLITE_DCHECK_GE(unextended_input1_shape.DimensionsCount(), 3); + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(unextended_input1_shape.DimensionsCount(), + unextended_output_shape.DimensionsCount()); + + // Extends the input/output shape from 3D to 4D if needed, NHC -> NH1C. + const RuntimeShape input1_shape = + ExtendShapeSpaceToBatch(unextended_input1_shape); + const RuntimeShape output_shape = + ExtendShapeSpaceToBatch(unextended_output_shape); + + const int depth = input1_shape.Dims(3); + const int input_width = input1_shape.Dims(2); + const int input_height = input1_shape.Dims(1); + const int input_batch_size = input1_shape.Dims(0); + + const int output_width = output_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_batch_size = output_shape.Dims(0); + + const int block_shape_height = block_shape_data[0]; + const int block_shape_width = + unextended_input1_shape.DimensionsCount() == 4 ? block_shape_data[1] : 1; + const int padding_top = paddings_data[0]; + const int padding_left = + unextended_input1_shape.DimensionsCount() == 4 ? paddings_data[2] : 0; + + // For uint8 quantized, the correct padding "zero value" is the output offset. + const int32_t pad_value = params.output_offset; + for (int out_b = 0; out_b < output_batch_size; ++out_b) { + int input_batch = out_b % input_batch_size; + int shift_w = (out_b / input_batch_size) % block_shape_width; + int shift_h = (out_b / input_batch_size) / block_shape_width; + for (int out_h = 0; out_h < output_height; ++out_h) { + for (int out_w = 0; out_w < output_width; ++out_w) { + T* out = output_data + Offset(output_shape, out_b, out_h, out_w, 0); + if (out_h * block_shape_height + shift_h < padding_top || + out_h * block_shape_height + shift_h >= + padding_top + input_height || + out_w * block_shape_width + shift_w < padding_left || + out_w * block_shape_width + shift_w >= padding_left + input_width) { + // This may not execute correctly when pad_value != 0 and T != uint8. + memset(out, pad_value, depth * sizeof(T)); + } else { + const T* in = + input1_data + + Offset(input1_shape, input_batch, + (out_h * block_shape_height + shift_h) - padding_top, + (out_w * block_shape_width + shift_w) - padding_left, 0); + memcpy(out, in, depth * sizeof(T)); + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SPACE_TO_BATCH_ND_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_depth.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_depth.h new file mode 100644 index 0000000..53260ae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_depth.h @@ -0,0 +1,80 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SPACE_TO_DEPTH_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SPACE_TO_DEPTH_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace reference_ops { + +template +inline void SpaceToDepth(const tflite::SpaceToDepthParams& op_params, + const RuntimeShape& unextended_input_shape, + const T* input_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(4, unextended_input_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + const int input_depth = input_shape.Dims(3); + const int input_width = input_shape.Dims(2); + const int input_height = input_shape.Dims(1); + const int input_batch = input_shape.Dims(0); + + const int output_depth = output_shape.Dims(3); + const int output_width = output_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_batch = output_shape.Dims(0); + + const int32_t block_size = op_params.block_size; + + TFLITE_DCHECK_EQ(input_width, output_width * block_size); + TFLITE_DCHECK_EQ(input_height, output_height * block_size); + TFLITE_DCHECK_EQ(input_depth * block_size * block_size, output_depth); + TFLITE_DCHECK_EQ(input_batch, output_batch); + + for (int in_b = 0; in_b < input_batch; ++in_b) { + for (int in_h = 0; in_h < input_height; ++in_h) { + for (int in_w = 0; in_w < input_width; ++in_w) { + for (int in_d = 0; in_d < input_depth; ++in_d) { + const int out_d = + in_d + ((in_h % block_size) * block_size + in_w % block_size) * + input_depth; + const int out_w = in_w / block_size; + const int out_h = in_h / block_size; + const int out_b = in_b; + + const int input_index = Offset(input_shape, in_b, in_h, in_w, in_d); + const int output_index = + Offset(output_shape, out_b, out_h, out_w, out_d); + + output_data[output_index] = input_data[input_index]; + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SPACE_TO_DEPTH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/strided_slice.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/strided_slice.h new file mode 100644 index 0000000..493d8f3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/strided_slice.h @@ -0,0 +1,147 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_STRIDED_SLICE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_STRIDED_SLICE_H_ + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/strided_slice_logic.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +template +inline void StridedSlice(const tflite::StridedSliceParams& op_params, + const RuntimeShape& unextended_input_shape, + const RuntimeShape& unextended_output_shape, + SequentialTensorWriter* writer) { + ruy::profiler::ScopeLabel label("StridedSlice"); + + // Note that the output_shape is not used herein. + tflite::StridedSliceParams params_copy = op_params; + + TFLITE_DCHECK_LE(unextended_input_shape.DimensionsCount(), 5); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 5); + const RuntimeShape input_shape = + RuntimeShape::ExtendedShape(5, unextended_input_shape); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(5, unextended_output_shape); + + // Reverse and pad to 5 dimensions because that is what the runtime code + // requires (ie. all shapes must be 5D and are given backwards). + strided_slice::StridedSlicePadIndices(¶ms_copy, 5); + + const int start_0 = + strided_slice::StridedSliceStartForAxis(params_copy, input_shape, 0); + const int stop_0 = strided_slice::StridedSliceEndForAxis( + params_copy, input_shape, 0, start_0); + const int start_1 = + strided_slice::StridedSliceStartForAxis(params_copy, input_shape, 1); + const int stop_1 = strided_slice::StridedSliceEndForAxis( + params_copy, input_shape, 1, start_1); + const int start_2 = + strided_slice::StridedSliceStartForAxis(params_copy, input_shape, 2); + const int stop_2 = strided_slice::StridedSliceEndForAxis( + params_copy, input_shape, 2, start_2); + const int start_3 = + strided_slice::StridedSliceStartForAxis(params_copy, input_shape, 3); + const int stop_3 = strided_slice::StridedSliceEndForAxis( + params_copy, input_shape, 3, start_3); + const int start_4 = + strided_slice::StridedSliceStartForAxis(params_copy, input_shape, 4); + const int stop_4 = strided_slice::StridedSliceEndForAxis( + params_copy, input_shape, 4, start_4); + + auto lc = [&](int end, int stride, int index) { + if (stride < 0) { + return index > end; + } else { + return index < end; + } + }; + // With a static_cast it is not possible to initialize + // a variable of type 'const int *' + // with an rvalue of type 'const int32_t *' (aka 'const long *'). + // reinterpret_cast is required to handle this casting. + const int* shape = reinterpret_cast(input_shape.DimsData()); + const int* stride = reinterpret_cast(params_copy.strides); + const bool inner_stride_is_1 = params_copy.strides[4] == 1; + + for (int offset_0 = start_0; lc(stop_0, stride[0], offset_0); + offset_0 += stride[0]) { + for (int offset_1 = start_1; lc(stop_1, stride[1], offset_1); + offset_1 += stride[1]) { + for (int offset_2 = start_2; lc(stop_2, stride[2], offset_2); + offset_2 += stride[2]) { + for (int offset_3 = start_3; lc(stop_3, stride[3], offset_3); + offset_3 += stride[3]) { + // When the stride is 1, the inner loop is equivalent to the + // optimized slice inner loop. Otherwise, it is identical to the + // strided_slice reference implementation inner loop. + if (inner_stride_is_1) { + const int len = stop_4 - start_4; + int index = start_4 + offset_3 * shape[4] + + offset_2 * shape[3] * shape[4] + + offset_1 * shape[2] * shape[3] * shape[4] + + offset_0 * shape[1] * shape[2] * shape[3] * shape[4]; + if (len > 0) { + writer->WriteN(index, len); + } + } else { + for (int offset_4 = start_4; lc(stop_4, stride[4], offset_4); + offset_4 += stride[4]) { + int index = offset_4 + offset_3 * shape[4] + + offset_2 * shape[3] * shape[4] + + offset_1 * shape[2] * shape[3] * shape[4] + + offset_0 * shape[1] * shape[2] * shape[3] * shape[4]; + writer->Write(index); + } + } + } + } + } + } +} + +template +inline void StridedSlice(const tflite::StridedSliceParams& op_params, + const RuntimeShape& unextended_input_shape, + const T* input_data, + const RuntimeShape& unextended_output_shape, + T* output_data) { + SequentialTensorWriter writer(input_data, output_data); + StridedSlice(op_params, unextended_input_shape, unextended_output_shape, + &writer); +} + +template +inline void StridedSlice(const tflite::StridedSliceParams& op_params, + const RuntimeShape& unextended_input_shape, + const TfLiteTensor* input, + const RuntimeShape& unextended_output_shape, + TfLiteTensor* output) { + SequentialTensorWriter writer(input, output); + StridedSlice(op_params, unextended_input_shape, unextended_output_shape, + &writer); +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_STRIDED_SLICE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/sub.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/sub.h new file mode 100644 index 0000000..44718a8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/sub.h @@ -0,0 +1,479 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SUB_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SUB_H_ + +#include + +#include +#include + +#include "edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h" // from @ruy +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline void SubNonBroadcast(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const float* input1_data, + const RuntimeShape& input2_shape, + const float* input2_data, + const RuntimeShape& output_shape, + float* output_data) { + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = ActivationFunctionWithMinMax( + input1_data[i] - input2_data[i], params.float_activation_min, + params.float_activation_max); + } +} + +inline void SubNonBroadcast(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const int32_t* input1_data, + const RuntimeShape& input2_shape, + const int32_t* input2_data, + const RuntimeShape& output_shape, + int32_t* output_data) { + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + output_data[i] = ActivationFunctionWithMinMax( + input1_data[i] - input2_data[i], params.quantized_activation_min, + params.quantized_activation_max); + } +} + +// TODO(b/151345304): We can implement BroadcastSub on buffers of arbitrary +// dimensionality if the runtime code does a single loop over one dimension +// that handles broadcasting as the base case. The code generator would then +// generate max(D1, D2) nested for loops. +template +inline void BroadcastSubSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const float* input1_data, + const RuntimeShape& input2_shape, + const float* input2_data, + const RuntimeShape& output_shape, + float* output_data) { + ruy::profiler::ScopeLabel label("BroadcastSubSlow/float"); + TFLITE_DCHECK_LE(input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(output_shape.DimensionsCount(), N); + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, output_shape), &output_desc); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + auto sub_func = [&](int indexes[N]) { + output_data[SubscriptToIndex(output_desc, indexes)] = + ActivationFunctionWithMinMax( + input1_data[SubscriptToIndex(desc1, indexes)] - + input2_data[SubscriptToIndex(desc2, indexes)], + params.float_activation_min, params.float_activation_max); + }; + NDOpsHelper(output_desc, sub_func); +} + +template +inline void BroadcastSubSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const int32_t* input1_data, + const RuntimeShape& input2_shape, + const int32_t* input2_data, + const RuntimeShape& output_shape, + int32_t* output_data) { + ruy::profiler::ScopeLabel label("BroadcastSubSlow/int32_t"); + TFLITE_DCHECK_LE(input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(output_shape.DimensionsCount(), N); + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, output_shape), &output_desc); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + auto sub_func = [&](int indexes[N]) { + output_data[SubscriptToIndex(output_desc, indexes)] = + ActivationFunctionWithMinMax( + input1_data[SubscriptToIndex(desc1, indexes)] - + input2_data[SubscriptToIndex(desc2, indexes)], + params.quantized_activation_min, params.quantized_activation_max); + }; + NDOpsHelper(output_desc, sub_func); +} + +template +void BroadcastSubSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const int64_t* input1_data, + const RuntimeShape& input2_shape, + const int64_t* input2_data, + const RuntimeShape& output_shape, int64_t* output_data) { + ruy::profiler::ScopeLabel label("BroadcastSubSlow/int64_t"); + TFLITE_DCHECK_LE(input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(output_shape.DimensionsCount(), N); + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, output_shape), &output_desc); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + auto sub_func = [&](int indexes[N]) { + output_data[SubscriptToIndex(output_desc, indexes)] = + ActivationFunctionWithMinMax( + input1_data[SubscriptToIndex(desc1, indexes)] - + input2_data[SubscriptToIndex(desc2, indexes)], + params.int64_activation_min, params.int64_activation_max); + }; + NDOpsHelper(output_desc, sub_func); +} + +template +void BroadcastSubSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const T* input1_data, + const RuntimeShape& input2_shape, const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("BroadcastSubSlow/templated"); + TFLITE_DCHECK_LE(input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(output_shape.DimensionsCount(), N); + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, output_shape), &output_desc); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + auto sub_func = [&](int indexes[N]) { + output_data[SubscriptToIndex(output_desc, indexes)] = + ActivationFunctionWithMinMax( + input1_data[SubscriptToIndex(desc1, indexes)] - + input2_data[SubscriptToIndex(desc2, indexes)], + params.quantized_activation_min, params.quantized_activation_max); + }; + NDOpsHelper(output_desc, sub_func); +} + +template +inline void BroadcastSub16POTSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const int16_t* input1_data, + const RuntimeShape& input2_shape, + const int16_t* input2_data, + const RuntimeShape& output_shape, + int16_t* output_data) { + ruy::profiler::ScopeLabel label("BroadcastSub16POTSlow/int16_t"); + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, output_shape), &output_desc); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + auto sub_func = [&](int indexes[N]) { + const int32_t input1_val = input1_data[SubscriptToIndex(desc1, indexes)]; + const int32_t input2_val = input2_data[SubscriptToIndex(desc2, indexes)]; + const int32_t scaled_input1_val = + gemmlowp::RoundingDivideByPOT(input1_val, -params.input1_shift); + const int32_t scaled_input2_val = + gemmlowp::RoundingDivideByPOT(input2_val, -params.input2_shift); + const int32_t raw_output = scaled_input1_val - scaled_input2_val; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[SubscriptToIndex(output_desc, indexes)] = + static_cast(clamped_output); + }; + NDOpsHelper(output_desc, sub_func); +} + +template +void BroadcastQuantSubSlow(const ArithmeticParams& params, + const RuntimeShape& input1_shape, + const T* input1_data, + const RuntimeShape& input2_shape, + const T* input2_data, + const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("BroadcastQuantSubSlow/T"); + TFLITE_DCHECK_LE(input1_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(input2_shape.DimensionsCount(), N); + TFLITE_DCHECK_LE(output_shape.DimensionsCount(), N); + NdArrayDesc desc1; + NdArrayDesc desc2; + NdArrayDesc output_desc; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + CopyDimsToDesc(RuntimeShape::ExtendedShape(N, output_shape), &output_desc); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + auto sub_func = [&](int indexes[N]) { + const int32_t input1_val = + params.input1_offset + input1_data[SubscriptToIndex(desc1, indexes)]; + const int32_t input2_val = + params.input2_offset + input2_data[SubscriptToIndex(desc2, indexes)]; + const int32_t shifted_input1_val = input1_val * (1 << params.left_shift); + const int32_t shifted_input2_val = input2_val * (1 << params.left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, params.input1_multiplier, params.input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, params.input2_multiplier, params.input2_shift); + const int32_t raw_sub = scaled_input1_val - scaled_input2_val; + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + raw_sub, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[SubscriptToIndex(output_desc, indexes)] = + static_cast(clamped_output); + }; + NDOpsHelper(output_desc, sub_func); +} + +// Element-wise add that can often be used for inner loop of broadcast add as +// well as the non-broadcast add. +template +inline void SubElementwise(int size, const ArithmeticParams& params, + const T* input1_data, const T* input2_data, + T* output_data) { + for (int i = 0; i < size; ++i) { + const int32_t input1_val = params.input1_offset + input1_data[i]; + const int32_t input2_val = params.input2_offset + input2_data[i]; + const int32_t shifted_input1_val = input1_val * (1 << params.left_shift); + const int32_t shifted_input2_val = input2_val * (1 << params.left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, params.input1_multiplier, params.input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, params.input2_multiplier, params.input2_shift); + const int32_t raw_sub = scaled_input1_val - scaled_input2_val; + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + raw_sub, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + output_data[i] = static_cast(clamped_output); + } +} + +inline void Sub(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const uint8_t* input1_data, + const RuntimeShape& input2_shape, const uint8_t* input2_data, + const RuntimeShape& output_shape, uint8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + TFLITE_DCHECK_GT(params.input1_offset, -256); + TFLITE_DCHECK_GT(params.input2_offset, -256); + TFLITE_DCHECK_LT(params.input1_offset, 256); + TFLITE_DCHECK_LT(params.input2_offset, 256); + SubElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +inline void Sub(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const int8_t* input1_data, + const RuntimeShape& input2_shape, const int8_t* input2_data, + const RuntimeShape& output_shape, int8_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + TFLITE_DCHECK_GE(params.input1_offset, -128); + TFLITE_DCHECK_GE(params.input2_offset, -128); + // offset = -quantization_params.zero_point in PrepareGeneralSubOp(). + // So it's maximum can be 128 not 127. + TFLITE_DCHECK_LE(params.input1_offset, 128); + TFLITE_DCHECK_LE(params.input2_offset, 128); + SubElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +inline void Sub(const ArithmeticParams& params, + const RuntimeShape& input1_shape, const int16_t* input1_data, + const RuntimeShape& input2_shape, const int16_t* input2_data, + const RuntimeShape& output_shape, int16_t* output_data) { + TFLITE_DCHECK_LE(params.quantized_activation_min, + params.quantized_activation_max); + + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + + TFLITE_DCHECK_EQ(params.input1_offset, 0); + TFLITE_DCHECK_EQ(params.input2_offset, 0); + SubElementwise(flat_size, params, input1_data, input2_data, output_data); +} + +template +void Sub(const ArithmeticParams& params, const RuntimeShape& input1_shape, + const T* input1_data, const RuntimeShape& input2_shape, + const T* input2_data, const RuntimeShape& output_shape, + T* output_data) { + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(input1_shape, input2_shape, &desc1, + &desc2); + const RuntimeShape extended_output_shape = + RuntimeShape::ExtendedShape(4, output_shape); + + // In Tensorflow, the dimensions are canonically named (batch_number, row, + // col, channel), with extents (batches, height, width, depth), with the + // trailing dimension changing most rapidly (channels has the smallest stride, + // typically 1 element). + // + // In generated C code, we store arrays with the dimensions reversed. The + // first dimension has smallest stride. + // + // We name our variables by their Tensorflow convention, but generate C code + // nesting loops such that the innermost loop has the smallest stride for the + // best cache behavior. + for (int b = 0; b < extended_output_shape.Dims(0); ++b) { + for (int y = 0; y < extended_output_shape.Dims(1); ++y) { + for (int x = 0; x < extended_output_shape.Dims(2); ++x) { + for (int c = 0; c < extended_output_shape.Dims(3); ++c) { + output_data[Offset(extended_output_shape, b, y, x, c)] = + input1_data[SubscriptToIndex(desc1, b, y, x, c)] - + input2_data[SubscriptToIndex(desc2, b, y, x, c)]; + } + } + } + } +} + +inline void SetActivationMinMax(const ArithmeticParams& params, + int32_t* activation_min, + int32_t* activation_max) { + *activation_min = params.quantized_activation_min; + *activation_max = params.quantized_activation_max; +} + +inline void SetActivationMinMax(const ArithmeticParams& params, + float* activation_min, float* activation_max) { + *activation_min = params.float_activation_min; + *activation_max = params.float_activation_max; +} + +inline void SetActivationMinMax(const ArithmeticParams& params, + int64_t* activation_min, + int64_t* activation_max) { + *activation_min = params.int64_activation_min; + *activation_max = params.int64_activation_max; +} + +template +inline void SubWithActivation( + const ArithmeticParams& params, const RuntimeShape& input1_shape, + const T* input1_data, const RuntimeShape& input2_shape, + const T* input2_data, const RuntimeShape& output_shape, T* output_data) { + ruy::profiler::ScopeLabel label("SubWithActivation"); + const int flat_size = + MatchingElementsSize(input1_shape, input2_shape, output_shape); + T activation_min, activation_max; + SetActivationMinMax(params, &activation_min, &activation_max); + + for (int i = 0; i < flat_size; ++i) { + output_data[i] = ActivationFunctionWithMinMax( + input1_data[i] - input2_data[i], activation_min, activation_max); + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_SUB_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/tanh.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/tanh.h new file mode 100644 index 0000000..b0320fd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/tanh.h @@ -0,0 +1,129 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TANH_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TANH_H_ + +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" + +namespace tflite { +namespace reference_ops { + +inline void Tanh(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; i++) { + float val = input_data[i]; + float result = std::tanh(val); + output_data[i] = result; + } +} + +// Convenience version that allows, for example, generated-code calls to be +// uniform between data types. +inline void Tanh(const TanhParams&, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& output_shape, + float* output_data) { + // Drop params: not needed. + Tanh(input_shape, input_data, output_shape, output_data); +} + +inline void Tanh(const TanhParams& params, const RuntimeShape& input_shape, + const int16_t* input_data, const RuntimeShape& output_shape, + int16_t* output_data) { + const int input_left_shift = params.input_left_shift; + // Support for shifts is limited until we have a parameterized version of + // SaturatingRoundingMultiplyByPOT(). + TFLITE_DCHECK_GE(input_left_shift, 0); + TFLITE_DCHECK_LE(input_left_shift, 1); + + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + // F0 uses 0 integer bits, range [-1, 1]. + // This is the return type of math functions such as tanh, logistic, + // whose range is in [-1, 1]. + using F0 = gemmlowp::FixedPoint; + // F3 uses 3 integer bits, range [-8, 8], the input range expected here. + using F3 = gemmlowp::FixedPoint; + + if (input_left_shift == 0) { + for (int i = 0; i < flat_size; i++) { + F3 input = F3::FromRaw(input_data[i]); + F0 output = gemmlowp::tanh(input); + output_data[i] = output.raw(); + } + } else { + for (int i = 0; i < flat_size; i++) { + F3 input = F3::FromRaw( + gemmlowp::SaturatingRoundingMultiplyByPOT<1>(input_data[i])); + F0 output = gemmlowp::tanh(input); + output_data[i] = output.raw(); + } + } +} + +inline void Tanh(const TanhParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& output_shape, + uint8_t* output_data) { + const int32_t input_zero_point = params.input_zero_point; + const int32_t input_range_radius = params.input_range_radius; + const int32_t input_multiplier = params.input_multiplier; + const int input_left_shift = params.input_left_shift; + const int32_t output_zero_point = 128; + const int flat_size = MatchingFlatSize(input_shape, output_shape); + + for (int i = 0; i < flat_size; i++) { + const uint8_t input_val_u8 = input_data[i]; + const int32_t input_val_centered = + static_cast(input_val_u8) - input_zero_point; + uint8_t output_val; + if (input_val_centered <= -input_range_radius) { + output_val = 0; + } else if (input_val_centered >= input_range_radius) { + output_val = 255; + } else { + const int32_t input_val_rescaled = + MultiplyByQuantizedMultiplierGreaterThanOne( + input_val_centered, input_multiplier, input_left_shift); + using FixedPoint4 = gemmlowp::FixedPoint; + using FixedPoint0 = gemmlowp::FixedPoint; + const FixedPoint4 input_val_f4 = FixedPoint4::FromRaw(input_val_rescaled); + const FixedPoint0 output_val_f0 = gemmlowp::tanh(input_val_f4); + // Convert from Q0.31 to Q24.7. + using gemmlowp::RoundingDivideByPOT; + int32_t output_val_s32 = RoundingDivideByPOT(output_val_f0.raw(), 24); + output_val_s32 += output_zero_point; + if (output_val_s32 == 256) { + output_val_s32 = 255; + } + // Reinterpret as Q0.7, encoded in uint8_t. + TFLITE_DCHECK_GE(output_val_s32, 0); + TFLITE_DCHECK_LE(output_val_s32, 255); + output_val = static_cast(output_val_s32); + } + output_data[i] = output_val; + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TANH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose.h new file mode 100644 index 0000000..d236420 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose.h @@ -0,0 +1,203 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TRANSPOSE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TRANSPOSE_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +namespace transpose_internal { + +// Recursively explores all the dimensions of the output tensor and writes the +// corresponding input tensor data. +// +// - depth: the current depth of the recursion. +// - dims: tensor dimension count, also `perm` size. +// - perm: permutation array. +// - input_data: Running input data pointer. If depth == num_dims-1, this points +// to the first element of the last dimension to traverse. +// - input_stride: Reverse partial product of input shapes. +// - output_data: Running output data pointer. If depth == num_dims-1, this +// points to the first element of the last dimension to traverse. +// - output_stride: Reverse partial product of output shapes. +// - output_shape: Shape of the output tensor. +// +// ## Algorithm explanation +// +// Assume a 3D tensor T with a shape of [I, J, K] stored in row major order. +// T[i, j, k] is at position `i*J*K + j*K + k` in the tensor buffer. +// +// If we want to go through the whole tensor iteratively, we can use loops. +// +// ``` +// for(i = 0; i < I; ++i) { +// for(j = 0; j < J; ++j) { +// for(k = 0; k < K; ++k) { +// T.data[i*J*K + j*K + k] = ... +// } +// } +// } +// ``` +// +// We can also compute the offset as we go through the loops. +// +// ``` +// stride_i = K * J; +// stride_j = K; +// stride_k = 1; +// for(i = 0; i < I; ++i) { +// offset_i = i * stride_i; +// offset_j = 0; +// for(j = 0; j < J; ++j) { +// offset_j += stride_j; +// offset_k = 0; +// for(k = 0; k < K; ++k) { +// offset_k += stride_k; +// T.data[offset_i + offset_j + offset_k] = ... +// } +// } +// } +// ``` +// +// This nicely extends to a recursive version which is the base of this +// algorithm and supports any number of dimensions. +// +// ``` +// shape = [I, J, K] +// strides = [K*J, K, 1] +// void recurse(T* data, shape, strides, depth = 0) { +// if(depth == shape.size) { +// *data = ... +// } else { +// for(a = 0; a < shape[depth]; ++a) { +// recurse(data, shape, strides, depth+1); +// data += strides[depth]; +// } +// } +// } +// ``` +template +void TransposeImpl(const int depth, const int dims, const int32_t* perm, + const T* input_data, const int* input_stride, T* output_data, + const int* output_stride, const int32_t* output_shape) { + const int dimension_size = output_shape[depth]; + if (depth == dims - 1) { + const int loop_stride = input_stride[perm[depth]]; + for (int i = 0; i < dimension_size; ++i) { + output_data[i] = *input_data; + input_data += loop_stride; + } + } else { + for (int i = 0; i < dimension_size; ++i) { + TransposeImpl(depth + 1, dims, perm, input_data, input_stride, + output_data, output_stride, output_shape); + + input_data += input_stride[perm[depth]]; + output_data += output_stride[depth]; + } + } +} + +// Compile-time switch to get the storage type of the transposition. +template +struct TransposeStorageType; + +template <> +struct TransposeStorageType<1> { + using type = int8_t; +}; + +template <> +struct TransposeStorageType<2> { + using type = int16_t; +}; + +template <> +struct TransposeStorageType<4> { + using type = int32_t; +}; + +template <> +struct TransposeStorageType<8> { + using type = int64_t; +}; + +// Sets up the stride arrays for the recursive transpose algorithm. +// +// Implementation notes: +// +// This is a reverse partial product. We could use standard algorithms to +// implement this but the result is not a readable and is tricky to get right +// because the first element must be set to 1, which leads to offset +// shenanigans: +// +// ``` +// stride[dims - 1] = 1; +// std::partial_sum(std::make_reverse_iterator(shape + dims), +// std::make_reverse_iterator(shape + 1), +// stride.rend() - input_rank + 1, std::multiplies()); +// ``` +// +// Note that Abseil isn't used in kernels implementation. That would make the +// above solution more readable. +inline void SetupTransposeStrides( + std::array& stride, const int32_t* shape, + const int dims) { + stride[dims - 1] = 1; + for (int i = dims - 2; i >= 0; --i) { + stride[i] = stride[i + 1] * shape[i + 1]; + } +} + +} // namespace transpose_internal + +// Copies a tensor to an other buffer and permutes its dimensions. +// +// Note: template parameter N is not used anymore. It is kept for API +// compatibility with TFLite micro. +template +void Transpose(const TransposeParams& params, const RuntimeShape& input_shape, + const T* input_data, const RuntimeShape& output_shape, + T* output_data) { + using transpose_internal::SetupTransposeStrides; + using transpose_internal::TransposeImpl; + using transpose_internal::TransposeStorageType; + // Transpose kernel only does rearranging values not numeric evaluations on + // each cell. It's safe to implement per size of scalar type and this trick + // keeps the total code size in a reasonable range. + using StorageType = typename TransposeStorageType::type; + const StorageType* const input_data_storage = + reinterpret_cast(input_data); + StorageType* const output_data_storage = + reinterpret_cast(output_data); + + const int dims = input_shape.DimensionsCount(); + std::array input_stride, output_stride; + SetupTransposeStrides(input_stride, input_shape.DimsData(), dims); + SetupTransposeStrides(output_stride, output_shape.DimsData(), dims); + TransposeImpl(0, dims, ¶ms.perm[0], input_data_storage, + input_stride.data(), output_data_storage, output_stride.data(), + output_shape.DimsData()); +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TRANSPOSE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose_conv.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose_conv.h new file mode 100644 index 0000000..55fae7d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose_conv.h @@ -0,0 +1,225 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TRANSPOSE_CONV_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TRANSPOSE_CONV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +namespace reference_ops { + +inline void TransposeConv( + const ConvParams& params, const RuntimeShape& input_shape, + const float* input_data, const RuntimeShape& filter_shape, + const float* filter_data, const RuntimeShape& bias_shape, + const float* bias_data, const RuntimeShape& output_shape, + float* output_data, const RuntimeShape& im2col_shape, float* im2col_data) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + (void)im2col_data; // only used in optimized code. + (void)im2col_shape; // only used in optimized code. + + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const float output_activation_min = params.float_activation_min; + const float output_activation_max = params.float_activation_max; + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + // Although transpose convolution simplifies to convolution with transposed + // weights for strides of 1, non-unitary striding complicates matters. To + // keep this reference implementation as clear as possible, we use a + // "scatter" access pattern, where we loop through all the input elements, + // computing their influence on the output, rather than looping through the + // output elements in the typical "gather" access pattern of a conv. We + // therefore must initialize the output array to zero. + const int num_elements = output_shape.FlatSize(); + for (int i = 0; i < num_elements; i++) { + output_data[i] = 0.0f; + } + + // Loop through input elements one at a time. + for (int batch = 0; batch < batches; ++batch) { + for (int in_y = 0; in_y < input_height; ++in_y) { + for (int in_x = 0; in_x < input_width; ++in_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + // Loop through the output elements it will influence + const int out_x_origin = (in_x * stride_width) - pad_width; + const int out_y_origin = (in_y * stride_height) - pad_height; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + for (int out_channel = 0; out_channel < output_depth; + ++out_channel) { + // Compute output element location + const int out_x = out_x_origin + filter_x; + const int out_y = out_y_origin + filter_y; + // We cannot accumulate out of bounds + if ((out_x >= 0) && (out_x < output_width) && (out_y >= 0) && + (out_y < output_height)) { + float input_value = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + float filter_value = + filter_data[Offset(filter_shape, out_channel, filter_y, + filter_x, in_channel)]; + output_data[Offset(output_shape, batch, out_y, out_x, + out_channel)] += + input_value * filter_value; + } + } + } + } + } + } + } + } + + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + float acc = output_data[Offset(output_shape, batch, out_y, out_x, + out_channel)]; + if (bias_data) acc += bias_data[out_channel]; + + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + ActivationFunctionWithMinMax(acc, output_activation_min, + output_activation_max); + } + } + } + } +} + +inline void TransposeConv( + const ConvParams& params, const RuntimeShape& input_shape, + const uint8_t* input_data, const RuntimeShape& filter_shape, + const uint8_t* filter_data, const RuntimeShape& bias_shape, + const int32_t* bias_data, const RuntimeShape& output_shape, + uint8_t* output_data, const RuntimeShape& im2col_shape, + uint8_t* im2col_data, int32_t* scratch_buffer) { + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int pad_width = params.padding_values.width; + const int pad_height = params.padding_values.height; + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + (void)im2col_data; // only used in optimized code. + (void)im2col_shape; // only used in optimized code. + + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + const int32_t input_offset = params.input_offset; + const int32_t filter_offset = params.weights_offset; + const int32_t output_offset = params.output_offset; + const int32_t output_multiplier = params.output_multiplier; + const int output_shift = params.output_shift; + const int32_t output_activation_min = params.quantized_activation_min; + const int32_t output_activation_max = params.quantized_activation_max; + TFLITE_DCHECK_LE(output_activation_min, output_activation_max); + if (bias_data) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + const int num_elements = output_shape.FlatSize(); + // We need to initialize scratch_buffer to all 0s, as we apply the same + // 'scatter' based trick as in float version. + memset(scratch_buffer, 0, num_elements * sizeof(int32_t)); + + // Loop through input elements one at a time. + for (int batch = 0; batch < batches; ++batch) { + for (int in_y = 0; in_y < input_height; ++in_y) { + for (int in_x = 0; in_x < input_width; ++in_x) { + for (int in_channel = 0; in_channel < input_depth; ++in_channel) { + // Loop through the output elements it will influence. + const int out_x_origin = (in_x * stride_width) - pad_width; + const int out_y_origin = (in_y * stride_height) - pad_height; + for (int filter_y = 0; filter_y < filter_height; ++filter_y) { + for (int filter_x = 0; filter_x < filter_width; ++filter_x) { + for (int out_channel = 0; out_channel < output_depth; + ++out_channel) { + // Compute output element location. + const int out_x = out_x_origin + filter_x; + const int out_y = out_y_origin + filter_y; + // We cannot accumulate out of bounds. + if ((out_x >= 0) && (out_x < output_width) && (out_y >= 0) && + (out_y < output_height)) { + uint8_t input_value = input_data[Offset( + input_shape, batch, in_y, in_x, in_channel)]; + uint8_t filter_value = + filter_data[Offset(filter_shape, out_channel, filter_y, + filter_x, in_channel)]; + scratch_buffer[Offset(output_shape, batch, out_y, out_x, + out_channel)] += + (input_value + input_offset) * + (filter_value + filter_offset); + } + } + } + } + } + } + } + } + for (int batch = 0; batch < batches; ++batch) { + for (int out_y = 0; out_y < output_height; ++out_y) { + for (int out_x = 0; out_x < output_width; ++out_x) { + for (int out_channel = 0; out_channel < output_depth; ++out_channel) { + int32_t acc = scratch_buffer[Offset(output_shape, batch, out_y, out_x, + out_channel)]; + if (bias_data) { + acc += bias_data[out_channel]; + } + int32_t scaled_acc = MultiplyByQuantizedMultiplier( + acc, output_multiplier, output_shift); + scaled_acc += output_offset; + scaled_acc = std::max(scaled_acc, output_activation_min); + scaled_acc = std::min(scaled_acc, output_activation_max); + output_data[Offset(output_shape, batch, out_y, out_x, out_channel)] = + static_cast(scaled_acc); + } + } + } + } +} + +} // namespace reference_ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_TRANSPOSE_CONV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils.cpp new file mode 100644 index 0000000..6ae01b8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils.cpp @@ -0,0 +1,809 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include +#include +#include +#include +#include +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils_impl.h" + +#if defined(_MSC_VER) +#define __restrict__ __restrict +#endif + +namespace tflite { +namespace tensor_utils { + +namespace { +const int32_t kInt16Max = std::numeric_limits::max(); +const int32_t kInt16Min = std::numeric_limits::min(); +} // namespace + +void PortableSymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float* min_value, + float* max_value, float* scaling_factor) { + auto minmax = std::minmax_element(values, values + size); + *min_value = *minmax.first; + *max_value = *minmax.second; + + PortableSymmetricQuantizeFloats(values, size, quantized_values, *min_value, + *max_value, scaling_factor); +} + +void PortableSymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float min_value, + float max_value, float* scaling_factor) { + const int32_t kScale = 127; + const float range = std::max(std::abs(min_value), std::abs(max_value)); + if (range == 0) { + memset(quantized_values, 0, size * sizeof(int8_t)); + *scaling_factor = 1; + return; + } + *scaling_factor = range / kScale; + const float scaling_factor_inv = kScale / range; + for (int i = 0; i < size; ++i) { + const int32_t quantized_value = + static_cast(TfLiteRound(values[i] * scaling_factor_inv)); + // Clamp: just in case some odd numeric offset. + quantized_values[i] = static_cast( + std::min(kScale, std::max(-kScale, quantized_value))); + } +} + +void PortableAsymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, + float* scaling_factor, int32_t* offset) { + const int32_t kMinScale = -128; + const int32_t kMaxScale = 127; + const double qmin_double = kMinScale; + const double qmax_double = kMaxScale; + const auto minmax = std::minmax_element(values, values + size); + const double rmin = static_cast(std::min(0.0f, *minmax.first)); + const double rmax = static_cast(std::max(0.0f, *minmax.second)); + if (rmin == rmax) { + memset(quantized_values, 0, size * sizeof(int8_t)); + *scaling_factor = 1; + *offset = 0; + return; + } else { + double scale = (rmax - rmin) / (qmax_double - qmin_double); + const double zero_point_from_min = qmin_double - rmin / scale; + const double zero_point_from_max = qmax_double - rmax / scale; + const double zero_point_from_min_error = + std::abs(qmin_double) + std::abs(rmin / scale); + const double zero_point_from_max_error = + std::abs(qmax_double) + std::abs(rmax / scale); + const double zero_point_double = + zero_point_from_min_error < zero_point_from_max_error + ? zero_point_from_min + : zero_point_from_max; + int8_t nudged_zero_point = 0; + if (zero_point_double <= qmin_double) { + nudged_zero_point = kMinScale; + } else if (zero_point_double >= qmax_double) { + nudged_zero_point = kMaxScale; + } else { + nudged_zero_point = static_cast(round(zero_point_double)); + } + *scaling_factor = scale; + *offset = nudged_zero_point; + } + const float scaling_factor_inv = 1.0f / *scaling_factor; + for (int i = 0; i < size; ++i) { + const int32_t quantized_value = static_cast( + TfLiteRound(*offset + values[i] * scaling_factor_inv)); + quantized_values[i] = + std::min(kMaxScale, std::max(kMinScale, quantized_value)); + } +} + +void PortableMatrixBatchVectorMultiplyAccumulate(const float* matrix, + int m_rows, int m_cols, + const float* vector, + int n_batch, float* result) { + float* result_in_batch = result; + for (int b = 0; b < n_batch; b++) { + const float* matrix_ptr = matrix; + for (int r = 0; r < m_rows; r++) { + float dot_prod = 0.0f; + const float* vector_in_batch = vector + b * m_cols; + for (int c = 0; c < m_cols; c++) { + dot_prod += *matrix_ptr++ * *vector_in_batch++; + } + *result_in_batch += dot_prod; + ++result_in_batch; + } + } +} + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, const float* scaling_factors, + int n_batch, float* __restrict__ result) { + for (int batch = 0; batch < n_batch; ++batch, vectors += m_cols) { + const float batch_scaling_factor = scaling_factors[batch]; + // Get the address of the first row. + const int8_t* row_ptr = matrix; + for (int row = 0; row < m_rows; ++row) { + // Initialize the dot product sum for the row to 0. + int32_t dotprod = 0; +#if defined(__GNUC__) + // Prefetch the row to cache. + __builtin_prefetch(row_ptr, 0 /* prefetch for read */, + 3 /* temporal locality */); +#endif + for (int col = 0; col < m_cols; ++col, ++row_ptr) { + dotprod += (*row_ptr) * (vectors[col]); + } // for col + *result += dotprod * batch_scaling_factor; + ++result; + } // for row + } // for batch +} + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, const float* scaling_factors, + int n_batch, float* __restrict__ result, const float* per_channel_scale, + const int32_t* input_offset, int32_t* scratch, int32_t* row_sums, + bool* compute_row_sums, CpuBackendContext* context) { + if (input_offset == nullptr) { + PortableMatrixBatchVectorMultiplyAccumulate( + matrix, m_rows, m_cols, vectors, scaling_factors, n_batch, result); + return; + } + if (!compute_row_sums || *compute_row_sums) { + PortableReductionSumVector(matrix, row_sums, m_rows, m_cols); + if (compute_row_sums) { + *compute_row_sums = false; + } + } + + for (int batch = 0; batch < n_batch; ++batch, vectors += m_cols) { + const float batch_scaling_factor = scaling_factors[batch]; + const int32_t batch_offset = input_offset[batch]; + const int8_t* row_ptr = matrix; + for (int row = 0; row < m_rows; ++row) { + int32_t dotprod = 0; + float scale = batch_scaling_factor; + if (per_channel_scale) { + scale *= per_channel_scale[row]; + } +#if defined(__GNUC__) + // Prefetch the row to cache. + __builtin_prefetch(row_ptr, 0 /* prefetch for read */, + 3 /* temporal locality */); +#endif + for (int col = 0; col < m_cols; ++col, ++row_ptr) { + dotprod += (*row_ptr) * vectors[col]; + } // for col + dotprod -= row_sums[row] * batch_offset; + *result += dotprod * scale; + ++result; + } // for row + } // for batch +} + +void PortableSparseMatrixBatchVectorMultiplyAccumulate1x4( + const float* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const float* __restrict__ vector, int n_batch, float* __restrict__ result) { + const int kBlockSize = 4; + TFLITE_DCHECK_EQ(m_cols % kBlockSize, 0); + for (int batch = 0; batch < n_batch; batch++) { + const float* matrix_ptr = matrix; + for (int row = 0; row < m_rows; row++) { + float dot_prod = 0.0f; + const float* vector_in_batch = vector + batch * m_cols; + for (int i = segments[row]; i < segments[row + 1]; i++) { + const int block_start_index = indices[i] * kBlockSize; + const float* vector_block_in_batch_ptr = + vector_in_batch + block_start_index; + for (int c = 0; c < kBlockSize; c++) { + dot_prod += *matrix_ptr++ * *vector_block_in_batch_ptr++; + } + } + result[batch * m_rows + row] += dot_prod; + } + } +} + +void PortableSparseMatrixBatchVectorMultiplyAccumulate1x16( + const int8_t* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const int8_t* __restrict__ vector, const int32_t* __restrict__ bias_vector, + int n_batch, const int32_t input_offset, const int32_t output_multiplier, + const int32_t output_shift, const int32_t output_offset, + const int32_t output_activation_min, const int32_t output_activation_max, + int8_t* __restrict__ result) { + const int kBlockSize = 16; + TFLITE_DCHECK_EQ(m_cols % kBlockSize, 0); + for (int batch = 0; batch < n_batch; ++batch) { + const int8_t* matrix_ptr = matrix; + for (int row = 0; row < m_rows; ++row) { + int32_t dot_prod = 0; + const int8_t* vector_in_batch = vector + batch * m_cols; + for (int i = segments[row]; i < segments[row + 1]; ++i) { + const int block_start_index = indices[i] * kBlockSize; + const int8_t* vector_block_in_batch_ptr = + vector_in_batch + block_start_index; + for (int c = 0; c < kBlockSize; c++) { + dot_prod += *matrix_ptr * *vector_block_in_batch_ptr++; + dot_prod += *matrix_ptr++ * input_offset; + } + } + const int32_t bias_value = bias_vector != nullptr ? bias_vector[row] : 0; + dot_prod = MultiplyByQuantizedMultiplier(dot_prod + bias_value, + output_multiplier, output_shift); + dot_prod += output_offset; + result[batch * m_rows + row] = + static_cast(ActivationFunctionWithMinMax( + dot_prod, output_activation_min, output_activation_max)); + } + } +} + +void PortableSparseMatrixBatchVectorMultiplyAccumulate( + const float* __restrict__ matrix, const uint8_t* __restrict__ ledger, + int m_rows, int m_cols, const float* __restrict__ vector, int n_batch, + float* __restrict__ result) { + const int kBlockSize = 16; + TFLITE_DCHECK_EQ( // NOLINT + m_cols % kBlockSize, 0); + for (int batch = 0; batch < n_batch; batch++) { + const float* matrix_ptr = matrix; + const uint8_t* ledger_ptr = ledger; + for (int row = 0; row < m_rows; row++) { + float dot_prod = 0.0f; + int num_nonzero_blocks = *ledger_ptr++; + if (num_nonzero_blocks > 0) { + const float* vector_in_batch = vector + batch * m_cols; + for (int i = 0; i < num_nonzero_blocks; i++) { + const int block_start_index = *ledger_ptr++ * kBlockSize; + const float* vector_block_in_batch_ptr = + vector_in_batch + block_start_index; + for (int c = 0; c < kBlockSize; c++) { + dot_prod += *matrix_ptr++ * *vector_block_in_batch_ptr++; + } + } + } + result[batch * m_rows + row] += dot_prod; + } + } +} + +void PortableSparseMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const uint8_t* ledger, const int m_rows, + const int m_cols, const int8_t* __restrict__ vectors, + const float* scaling_factors, int n_batch, float* __restrict__ result) { + static const int kBlockSize = 16; + TFLITE_DCHECK_EQ( // NOLINT + m_cols % kBlockSize, 0); + for (int batch = 0; batch < n_batch; ++batch, vectors += m_cols) { + const float batch_scaling_factor = scaling_factors[batch]; + const uint8_t* ledger_ptr = ledger; + // Get the address of the first row. + const int8_t* row_ptr = matrix; + for (int row = 0; row < m_rows; ++row) { + // Initialize the dot product sum for the row to 0. + int32_t dotprod = 0; +#if defined(__GNUC__) + // Prefetch the row to cache. + __builtin_prefetch(row_ptr, 0 /* prefetch for read */, + 3 /* temporal locality */); +#endif + int num_nonzero_blocks = *ledger_ptr++; + for (int i = 0; i < num_nonzero_blocks; i++) { + const int block_start_index = *ledger_ptr++ * kBlockSize; + const int8_t* vector_block_ptr = vectors + block_start_index; + for (int c = 0; c < kBlockSize; c++) { + dotprod += (*row_ptr++) * (*vector_block_ptr++); + } // for block + } // for num_nonzero_blocks + result[batch * m_rows + row] += dotprod * batch_scaling_factor; + } // for row + } // for batch +} + +template +void PortableMatrixBatchVectorMultiplyAccumulateImpl( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + T* output) { + const int16_t output_max = std::numeric_limits::max(); + const int16_t output_min = std::numeric_limits::min(); + for (int batch = 0; batch < n_batch; ++batch) { + for (int row = 0; row < n_output; ++row) { + int32_t acc = bias[row]; + for (int col = 0; col < n_input; ++col) { + int8_t input_val = input[batch * n_input + col]; + int8_t weights_val = input_to_gate_weights[row * n_input + col]; + acc += input_val * weights_val; + } + acc = MultiplyByQuantizedMultiplier(acc, multiplier, shift); + acc += output_zp; + acc += output[batch * n_output + row]; + if (acc > output_max) { + acc = output_max; + } + if (acc < output_min) { + acc = output_min; + } + output[batch * n_output + row] = static_cast(acc); + } + } +} + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int16_t* output, CpuBackendContext* context) { + PortableMatrixBatchVectorMultiplyAccumulateImpl( + input, bias, input_to_gate_weights, multiplier, shift, n_batch, n_input, + n_output, output_zp, output); +} + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int8_t* output, CpuBackendContext* context) { + PortableMatrixBatchVectorMultiplyAccumulateImpl( + input, bias, input_to_gate_weights, multiplier, shift, n_batch, n_input, + n_output, output_zp, output); +} + +void PortableMatrixBatchVectorMultiply(const int8_t* input, + int32_t input_zeropoint, + const int8_t* input_to_gate_weights, + int32_t input_to_gate_effective_scale_a, + int32_t input_to_gate_effective_scale_b, + int32_t n_batch, int32_t n_input, + int32_t n_cell, int8_t* gate_output, + int8_t gate_output_zp) { + const int32_t int8_max = std::numeric_limits::max(); + const int32_t int8_min = std::numeric_limits::min(); + for (int batch = 0; batch < n_batch; ++batch) { + for (int row = 0; row < n_cell; ++row) { + int32_t acc = 0; + for (int col = 0; col < n_input; ++col) { + int32_t input_val = input[batch * n_input + col]; + int8_t weights_val = input_to_gate_weights[row * n_input + col]; + acc += (input_val - input_zeropoint) * weights_val; + } + acc = MultiplyByQuantizedMultiplier(acc, input_to_gate_effective_scale_a, + input_to_gate_effective_scale_b); + acc += gate_output_zp; + if (acc > int8_max) { + acc = int8_max; + } + if (acc < int8_min) { + acc = int8_min; + } + gate_output[batch * n_cell + row] = static_cast(acc); + } + } +} + +void PortableMatrixBatchVectorMultiply( + const int16_t* hidden, const int8_t* hidden_to_output_weights, + int32_t proj_effective_scale_a, int32_t proj_effective_scale_b, + const int32_t* gate_bias, int32_t n_batch, int32_t n_hidden, + int32_t n_output, int32_t output_zp, int8_t* proj_output) { + const int16_t int8_max = std::numeric_limits::max(); + const int16_t int8_min = std::numeric_limits::min(); + for (int batch = 0; batch < n_batch; ++batch) { + for (int row = 0; row < n_output; ++row) { + int64_t acc = gate_bias[row]; + for (int col = 0; col < n_hidden; ++col) { + int16_t input_val = hidden[batch * n_hidden + col]; + int8_t weights_val = hidden_to_output_weights[row * n_hidden + col]; + int64_t curr = acc; + acc += input_val * weights_val; + if (input_val * weights_val > 0 && acc < curr) { + acc = std::numeric_limits::max(); + } + if (input_val * weights_val < 0 && acc > curr) { + acc = std::numeric_limits::min(); + } + } + acc = MultiplyByQuantizedMultiplier(acc, proj_effective_scale_a, + proj_effective_scale_b); + acc += output_zp; + if (acc > int8_max) { + acc = int8_max; + } + if (acc < int8_min) { + acc = int8_min; + } + proj_output[batch * n_output + row] = acc; + } + } +} + +void PortableApplyLayerNorm(const int16_t* input, + const int16_t* layer_norm_weights, + const int32_t* bias, int32_t layer_norm_scale_a, + int32_t layer_norm_scale_b, int32_t variance_limit, + int n_batch, int n_input, int16_t* output) { + // The square of std::pow(2, 10), which is the extra factor that makes sure + // normalized values has enough resolution. + static const int kTwoToPower20 = 1 << 20; + for (int i = 0; i < n_batch; ++i) { + int64_t sum = 0; + int64_t sum_sq = 0; + for (int j = 0; j < n_input; ++j) { + const int32_t index = i * n_input + j; + int32_t val = static_cast(input[index]); + sum += val; + sum_sq += val * val; + } + int32_t mean = + static_cast(static_cast(sum) * 1024 / n_input); + // TODO(b/173994730): Avoids overflow but only works for POT n_input. + int32_t temp = kTwoToPower20 / n_input; + int64_t variance = + sum_sq * temp - static_cast(mean) * static_cast(mean); + int32_t variance2 = static_cast(variance / kTwoToPower20); + if (variance2 < 1) { + variance2 = variance_limit; + } + int32_t stddev_inverse_a; + int stddev_inverse_b; + GetInvSqrtQuantizedMultiplierExp(variance2, /*reverse_shift*/ -1, + &stddev_inverse_a, &stddev_inverse_b); + + for (int j = 0; j < n_input; ++j) { + const int32_t index = i * n_input + j; + int32_t val = static_cast(input[index]); + int32_t shifted = 1024 * val - mean; + int32_t rescaled = MultiplyByQuantizedMultiplier( + shifted, stddev_inverse_a, stddev_inverse_b); + // TODO(jianlijianli): Saturate this. + int64_t val3 = rescaled * layer_norm_weights[j] + bias[j]; + int32_t val4 = + static_cast((val3 > 0 ? val3 + 512 : val3 - 512) / 1024); + int32_t val5 = MultiplyByQuantizedMultiplier(val4, layer_norm_scale_a, + layer_norm_scale_b + 12); + val5 = std::min(std::max(kInt16Min, val5), kInt16Max); + output[index] = static_cast(val5); + } + } +} + +void PortableApplyLayerNormFloat(const int16_t* input, + const int16_t* layer_norm_weights, + int32_t layer_norm_scale_a, + int32_t layer_norm_scale_b, + const int32_t* bias, int n_batch, int n_input, + int16_t* output) { + const int32_t int16_max = std::numeric_limits::max(); + const int32_t int16_min = std::numeric_limits::min(); + const float layer_norm_scale = + layer_norm_scale_a * + std::pow(2.0, static_cast(layer_norm_scale_b - 31)); + const float bias_scale = + static_cast(std::pow(2.0, -10)) * layer_norm_scale; + + for (int batch = 0; batch < n_batch; ++batch) { + float sum = 0.0f; + float sum_sq = 0.0f; + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + const float value = static_cast(input[index]); + sum += value; + sum_sq += value * value; + } + const float mean = sum / n_input; + float stddev_inv = 0.0f; + const float variance = sum_sq / n_input - mean * mean; + if (variance == 0) { + stddev_inv = 1.0f / std::sqrt(1e-8f); + } else { + stddev_inv = 1.0f / std::sqrt(variance); + } + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + const float normalized_value = + (static_cast(input[index]) - mean) * stddev_inv; + const float weighted_normalized_value = + normalized_value * layer_norm_weights[i] * layer_norm_scale + + bias[i] * bias_scale; + const int32_t quant_output = static_cast(round( + weighted_normalized_value * static_cast(std::pow(2, 12)))); + output[index] = std::min(int16_max, std::max(int16_min, quant_output)); + } + } +} + +void PortableMatrixScalarMultiplyAccumulate(const int8_t* matrix, + int32_t scalar, int32_t n_row, + int32_t n_col, int32_t* output) { + for (int i = 0; i < n_row; ++i) { + int32_t row_sum = 0; + for (int j = 0; j < n_col; ++j) { + row_sum += *matrix++; + } + output[i] += row_sum * scalar; + } +} + +void PortableApplySigmoid(const int16_t* input, int32_t n_batch, + int32_t n_input, int16_t* output) { + for (int batch = 0; batch < n_batch; ++batch) { + for (int c = 0; c < n_input; c++) { + using F3 = gemmlowp::FixedPoint; + using F0 = gemmlowp::FixedPoint; + const int index = batch * n_input + c; + F3 sigmoid_input = F3::FromRaw(input[index]); + F0 sigmoid_output = gemmlowp::logistic(sigmoid_input); + output[index] = sigmoid_output.raw(); + } + } +} + +void PortableApplySigmoidFloat(const int16_t* input, int32_t n_batch, + int32_t n_input, int16_t* output) { + const int32_t int16_max = std::numeric_limits::max(); + const int32_t int16_min = std::numeric_limits::min(); + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + const float float_input = + input[index] * static_cast(std::pow(2, -12)); + const float float_output = 1.0f / (1.0f + std::exp(-float_input)); + const int32_t quant_output = static_cast( + float_output * static_cast(std::pow(2, 15))); + const int32_t quant_output_clamped = + std::min(int16_max, std::max(int16_min, quant_output)); + output[index] = static_cast(quant_output_clamped); + } + } +} + +template +void PortableApplyTanhImpl(const int16_t* input, int32_t n_batch, + int32_t n_input, int16_t* output) { + using FX = gemmlowp::FixedPoint; + using F0 = gemmlowp::FixedPoint; + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + FX tanh_input = FX::FromRaw(input[index]); + F0 tanh_output = gemmlowp::tanh(tanh_input); + output[index] = tanh_output.raw(); + } + } +} + +void PortableApplyTanh(int32_t integer_bits, const int16_t* input, + int32_t n_batch, int32_t n_input, int16_t* output) { + assert(integer_bits <= 6); +#define DISPATCH_TANH(i) \ + case i: \ + PortableApplyTanhImpl(input, n_batch, n_input, output); \ + break; + switch (integer_bits) { + DISPATCH_TANH(0); + DISPATCH_TANH(1); + DISPATCH_TANH(2); + DISPATCH_TANH(3); + DISPATCH_TANH(4); + DISPATCH_TANH(5); + DISPATCH_TANH(6); + default: + return; + } +#undef DISPATCH_TANH +} + +void PortableApplyTanhFloat(const int16_t* input, int32_t n_batch, + int32_t n_input, int32_t integer_bits, + int16_t* output) { + const int32_t int16_max = std::numeric_limits::max(); + const int32_t int16_min = std::numeric_limits::min(); + const double two = 2.0; + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + const float float_input = + input[index] * std::pow(two, static_cast(integer_bits)); + const float float_output = std::tanh(float_input); + const int32_t quant_output = static_cast( + float_output * static_cast(std::pow(2, 15))); + const int32_t quant_output_clamped = + std::min(int16_max, std::max(int16_min, quant_output)); + output[index] = static_cast(quant_output_clamped); + } + } +} + +void PortableCwiseMul(const int16_t* input_1, const int16_t* input_2, + int n_batch, int n_input, int shift, int16_t* output) { + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + const int16_t a = input_1[index]; + const int16_t b = input_2[index]; + const int32_t value = static_cast(a) * static_cast(b); + output[index] = + static_cast(gemmlowp::RoundingDivideByPOT(value, shift)); + } + } +} + +void PortableCwiseMul(const int16_t* input_1, const int16_t* input_2, + int32_t multiplier, int32_t shift, int32_t n_batch, + int32_t n_input, int32_t output_zp, int8_t* output) { + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + const int16_t a = input_1[index]; + const int16_t b = input_2[index]; + int32_t value = static_cast(a) * static_cast(b); + value = MultiplyByQuantizedMultiplier(value, multiplier, shift); + value += output_zp; + value = std::min(std::max(static_cast(-128), value), + static_cast(127)); + + output[index] = static_cast(value); + } + } +} + +void PortableCwiseAdd(const int16_t* input_1, const int16_t* input_2, + int n_batch, int n_input, int16_t* output) { + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + int32_t sum = input_1[index] + input_2[index]; + const int32_t sum_clamped = std::min(kInt16Max, std::max(kInt16Min, sum)); + output[index] = static_cast(sum_clamped); + } + } +} + +float PortableVectorVectorDotProduct(const float* vector1, const float* vector2, + int v_size) { + float result = 0.0; + for (int v = 0; v < v_size; v++) { + result += *vector1++ * *vector2++; + } + return result; +} + +namespace { +inline int32_t VectorVectorDotProduct(const int16_t* vector1, + const int16_t* vector2, int v_size) { + int32_t result = 0; + for (int v = 0; v < v_size; v++) { + result += *vector1++ * *vector2++; + } + return result; +} +} // namespace + +void PortableBatchVectorBatchVectorDotProduct(const int16_t* vector1, + const int16_t* vector2, + int v_size, int n_batch, + int32_t* result) { + for (int b = 0; b < n_batch; b++) { + result[b] = VectorVectorDotProduct(vector1, vector2, v_size); + vector1 += v_size; + vector2 += v_size; + } +} + +void PortableVectorBatchVectorCwiseProductAccumulate( + const int16_t* vector, int v_size, const int16_t* batch_vector, int n_batch, + int32_t multiplier, int shift, int16_t* result) { + for (int b = 0; b < n_batch; b++) { + for (int v = 0; v < v_size; v++) { + int32_t prod = vector[v] * *batch_vector++; + prod = MultiplyByQuantizedMultiplier(prod, multiplier, shift); + int32_t output = prod + *result; + output = std::max(std::min(static_cast(32767), output), + static_cast(-32768)); + *result++ = output; + } + } +} + +void PortableSub1Vector(const float* vector, int v_size, float* result) { + for (int v = 0; v < v_size; v++) { + *result++ = 1.0f - *vector++; + } +} + +void PortableSub1Vector(const int16_t* vector, int v_size, int16_t* result) { + static const int16_t kOne = 32767; + for (int v = 0; v < v_size; v++) { + *result++ = kOne - *vector++; + } +} + +void PortableVectorScalarMultiply(const int8_t* vector, const int v_size, + const float scale, float* result) { + for (int v = 0; v < v_size; ++v) { + *result++ = scale * *vector++; + } +} + +void PortableMeanStddevNormalization(const float* __restrict__ input_vector, + float* __restrict__ output_vector, + int v_size, int n_batch) { + for (int batch = 0; batch < n_batch; ++batch) { + float sum = 0.0f; + for (int i = 0; i < v_size; ++i) { + sum += input_vector[i]; + } + const float mean = sum / v_size; + float sum_diff_sq = 0.0f; + for (int i = 0; i < v_size; ++i) { + const float diff = input_vector[i] - mean; + sum_diff_sq += diff * diff; + } + const float variance = sum_diff_sq / v_size; + constexpr float kNormalizationConstant = 1e-8f; + const float stddev_inv = + 1.0f / std::sqrt(variance + kNormalizationConstant); + for (int i = 0; i < v_size; ++i) { + output_vector[i] = (input_vector[i] - mean) * stddev_inv; + } + input_vector += v_size; + output_vector += v_size; + } +} + +void PortableTwoGateSaturatingAdd(const int8_t* input, int8_t input_zp, + const int8_t* recurrent, int8_t recurrent_zp, + int32_t input_effective_scale_a, + int32_t input_effective_scale_b, + int32_t recurrent_effective_scale_a, + int32_t recurrent_effective_scale_b, + int32_t n_batch, int32_t n_cell, + int16_t* output) { + const int32_t int16_max = std::numeric_limits::max(); + const int32_t int16_min = std::numeric_limits::min(); + for (int i = 0; i < n_batch * n_cell; ++i) { + int32_t x = static_cast(input[i]) - static_cast(input_zp); + int32_t h = + static_cast(recurrent[i]) - static_cast(recurrent_zp); + int32_t x_scaled = MultiplyByQuantizedMultiplier(x, input_effective_scale_a, + input_effective_scale_b); + int32_t h_scaled = MultiplyByQuantizedMultiplier( + h, recurrent_effective_scale_a, recurrent_effective_scale_b); + int32_t y = h_scaled + x_scaled; + if (y > int16_max) { + y = int16_max; + } + if (y < int16_min) { + y = int16_min; + } + output[i] = static_cast(y); + } +} + +} // namespace tensor_utils +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils.h new file mode 100644 index 0000000..06c867c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils.h @@ -0,0 +1,333 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PORTABLE_TENSOR_UTILS_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PORTABLE_TENSOR_UTILS_H_ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils_impl.h" + +#if defined(_MSC_VER) +#define __restrict__ __restrict +#endif + +namespace tflite { +namespace tensor_utils { + +// Check if all entries of a vector are zero for float. +bool IsZeroVector(const float* vector, int v_size) { + return PortableIsZeroVector(vector, v_size); +} + +// Check if all entries of a vector are zero for int8_t. +bool IsZeroVector(const int8_t* vector, int v_size) { + return PortableIsZeroVector(vector, v_size); +} + +void SymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float* min, float* max, + float* scaling_factor) { + PortableSymmetricQuantizeFloats(values, size, quantized_values, min, max, + scaling_factor); +} + +void SymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float min_value, + float max_value, float* scaling_factor) { + PortableSymmetricQuantizeFloats(values, size, quantized_values, min_value, + max_value, scaling_factor); +} + +void AsymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float* scaling_factor, + int32_t* offset) { + PortableAsymmetricQuantizeFloats(values, size, quantized_values, + scaling_factor, offset); +} + +void MatrixBatchVectorMultiplyAccumulate(const float* matrix, int m_rows, + int m_cols, const float* vector, + int n_batch, float* result) { + PortableMatrixBatchVectorMultiplyAccumulate(matrix, m_rows, m_cols, vector, + n_batch, result); +} + +void MatrixBatchVectorMultiplyAccumulate(const int8_t* __restrict__ matrix, + const int m_rows, const int m_cols, + const int8_t* __restrict__ vector, + const float* scaling_factors, + int n_batch, + float* __restrict__ result) { + PortableMatrixBatchVectorMultiplyAccumulate(matrix, m_rows, m_cols, vector, + scaling_factors, n_batch, result); +} + +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, const float* scaling_factors, + int n_batch, float* __restrict__ result, const float* per_channel_scale, + const int32_t* input_offset, int32_t* scratch, int32_t* row_sums, + bool* compute_row_sums, CpuBackendContext* context) { + PortableMatrixBatchVectorMultiplyAccumulate( + matrix, m_rows, m_cols, vectors, scaling_factors, n_batch, result, + per_channel_scale, input_offset, scratch, row_sums, compute_row_sums, + context); +} + +void MatrixBatchVectorMultiplyAccumulate(const int8_t* __restrict__ matrix, + const int m_rows, const int m_cols, + const int8_t* __restrict__ vector, + const float* scaling_factors, + int n_batch, int32_t* scratch, + float* __restrict__ result, + CpuBackendContext* context) { + PortableMatrixBatchVectorMultiplyAccumulate(matrix, m_rows, m_cols, vector, + scaling_factors, n_batch, result); +} + +void SparseMatrixBatchVectorMultiplyAccumulate1x4( + const float* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const float* __restrict__ vector, int n_batch, float* __restrict__ result) { + PortableSparseMatrixBatchVectorMultiplyAccumulate1x4( + matrix, segments, indices, m_rows, m_cols, vector, n_batch, result); +} + +void SparseMatrixBatchVectorMultiplyAccumulate( + const float* __restrict__ matrix, const uint8_t* __restrict__ ledger, + int m_rows, int m_cols, const float* __restrict__ vector, int n_batch, + float* __restrict__ result) { + PortableSparseMatrixBatchVectorMultiplyAccumulate( + matrix, ledger, m_rows, m_cols, vector, n_batch, result); +} + +void SparseMatrixBatchVectorMultiplyAccumulate1x16( + const int8_t* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const int8_t* __restrict__ vector, const int32_t* __restrict__ bias_vector, + int n_batch, const int32_t input_offset, const int32_t output_multiplier, + const int32_t output_shift, const int32_t output_offset, + const int32_t output_activation_min, const int32_t output_activation_max, + + int8_t* __restrict__ result) { + PortableSparseMatrixBatchVectorMultiplyAccumulate1x16( + matrix, segments, indices, m_rows, m_cols, vector, bias_vector, n_batch, + input_offset, output_multiplier, output_shift, output_offset, + output_activation_min, output_activation_max, result); +} + +void SparseMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const uint8_t* ledger, const int m_rows, + const int m_cols, const int8_t* __restrict__ vectors, + const float* scaling_factors, int n_batch, float* __restrict__ result) { + PortableSparseMatrixBatchVectorMultiplyAccumulate( + matrix, ledger, m_rows, m_cols, vectors, scaling_factors, n_batch, + result); +} + +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int16_t* output, CpuBackendContext* context) { + PortableMatrixBatchVectorMultiplyAccumulate( + input, bias, input_to_gate_weights, multiplier, shift, n_batch, n_input, + n_output, output_zp, scratch, output, context); +} + +void MatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int8_t* output, CpuBackendContext* context) { + PortableMatrixBatchVectorMultiplyAccumulate( + input, bias, input_to_gate_weights, multiplier, shift, n_batch, n_input, + n_output, output_zp, scratch, output, context); +} + +void MatrixScalarMultiplyAccumulate(const int8_t* matrix, int32_t scalar, + int32_t n_row, int32_t n_col, + int32_t* output) { + PortableMatrixScalarMultiplyAccumulate(matrix, scalar, n_row, n_col, output); +} + +void MatrixBatchVectorMultiply(const int8_t* input, int32_t input_zeropoint, + const int8_t* input_to_gate_weights, + int32_t input_to_gate_effective_scale_a, + int32_t input_to_gate_effective_scale_b, + int32_t n_batch, int32_t n_input, int32_t n_cell, + int8_t* gate_output, int8_t gate_output_zp) { + PortableMatrixBatchVectorMultiply( + input, input_zeropoint, input_to_gate_weights, + input_to_gate_effective_scale_a, input_to_gate_effective_scale_b, n_batch, + n_input, n_cell, gate_output, gate_output_zp); +} + +void MatrixBatchVectorMultiply(const int16_t* hidden, + const int8_t* hidden_to_output_weights, + int32_t proj_effective_scale_a, + int32_t proj_effective_scale_b, + const int32_t* gate_bias, int32_t n_batch, + int32_t n_hidden, int32_t n_output, + int32_t output_zp, int8_t* proj_output) { + PortableMatrixBatchVectorMultiply(hidden, hidden_to_output_weights, + proj_effective_scale_a, + proj_effective_scale_b, gate_bias, n_batch, + n_hidden, n_output, output_zp, proj_output); +} + +void ApplyLayerNorm(const int16_t* input, const int16_t* layer_norm_weights, + const int32_t* bias, int32_t layer_norm_scale_a, + int32_t layer_norm_scale_b, int32_t variance_limit, + int n_batch, int n_input, int16_t* output) { + PortableApplyLayerNorm(input, layer_norm_weights, bias, layer_norm_scale_a, + layer_norm_scale_b, variance_limit, n_batch, n_input, + output); +} + +void ApplyLayerNormFloat(const int16_t* input, + const int16_t* layer_norm_weights, + int32_t layer_norm_scale_a, int32_t layer_norm_scale_b, + const int32_t* bias, int n_batch, int n_input, + int16_t* output) { + PortableApplyLayerNormFloat(input, layer_norm_weights, layer_norm_scale_a, + layer_norm_scale_b, bias, n_batch, n_input, + output); +} + +void ApplySigmoid(const int16_t* input, int32_t n_batch, int32_t n_input, + int16_t* output) { + PortableApplySigmoid(input, n_batch, n_input, output); +} + +void ApplySigmoidFloat(const int16_t* input, int32_t n_batch, int32_t n_input, + int16_t* output) { + PortableApplySigmoidFloat(input, n_batch, n_input, output); +} + +void ApplyTanh(int32_t integer_bits, const int16_t* input, int32_t n_batch, + int32_t n_input, int16_t* output) { + PortableApplyTanh(integer_bits, input, n_batch, n_input, output); +} + +void ApplyTanhFloat(const int16_t* input, int32_t n_batch, int32_t n_input, + int32_t integer_bits, int16_t* output) { + PortableApplyTanhFloat(input, n_batch, n_input, integer_bits, output); +} + +void CwiseMul(const int16_t* input_1, const int16_t* input_2, int n_batch, + int n_input, int shift, int16_t* output) { + PortableCwiseMul(input_1, input_2, n_batch, n_input, shift, output); +} + +void CwiseMul(const int16_t* input_1, const int16_t* input_2, + int32_t multiplier, int32_t shift, int32_t n_batch, + int32_t n_input, int32_t output_zp, int8_t* output) { + PortableCwiseMul(input_1, input_2, multiplier, shift, n_batch, n_input, + output_zp, output); +} + +void CwiseAdd(const int16_t* input_1, const int16_t* input_2, int n_batch, + int n_input, int16_t* output) { + PortableCwiseAdd(input_1, input_2, n_batch, n_input, output); +} + +void CwiseClipping(float* vector, const int v_size, + const float clipping_value) { + PortableCwiseClipping(vector, v_size, clipping_value); +} + +void CwiseClipping(int16_t* vector, const int v_size, + const int16_t clipping_value) { + PortableCwiseClipping(vector, v_size, clipping_value); +} + +void CwiseClipping(int8_t* vector, const int v_size, + const int8_t clipping_value) { + PortableCwiseClipping(vector, v_size, clipping_value); +} + +void VectorBatchVectorCwiseProductAccumulate(const int16_t* vector, int v_size, + const int16_t* batch_vector, + int n_batch, int32_t multiplier, + int shift, int16_t* result) { + PortableVectorBatchVectorCwiseProductAccumulate( + vector, v_size, batch_vector, n_batch, multiplier, shift, result); +} + +float VectorVectorDotProduct(const float* vector1, const float* vector2, + int v_size) { + return PortableVectorVectorDotProduct(vector1, vector2, v_size); +} + +void BatchVectorBatchVectorDotProduct(const int16_t* vector1, + const int16_t* vector2, int v_size, + int n_batch, int32_t* result) { + PortableBatchVectorBatchVectorDotProduct(vector1, vector2, v_size, n_batch, + result); +} + +void Sub1Vector(const float* vector, int v_size, float* result) { + PortableSub1Vector(vector, v_size, result); +} + +void Sub1Vector(const int16_t* vector, int v_size, int16_t* result) { + PortableSub1Vector(vector, v_size, result); +} + +// Multiply all elements of vector with a scalar. +void VectorScalarMultiply(const int8_t* vector, int v_size, float scale, + float* result) { + PortableVectorScalarMultiply(vector, v_size, scale, result); +} + +void ReductionSumVector(const float* input_vector, float* output_vector, + int output_size, int reduction_size) { + PortableReductionSumVector(input_vector, output_vector, output_size, + reduction_size); +} + +void ReductionSumVector(const int32_t* input_vector, int32_t* output_vector, + int output_size, int reduction_size) { + PortableReductionSumVector(input_vector, output_vector, output_size, + reduction_size); +} + +void ReductionSumVector(const int8_t* input_vector, int32_t* output_vector, + int output_size, int reduction_size) { + PortableReductionSumVector(input_vector, output_vector, output_size, + reduction_size); +} + +void MeanStddevNormalization(const float* input_vector, float* output_vector, + int v_size, int n_batch) { + PortableMeanStddevNormalization(input_vector, output_vector, v_size, n_batch); +} + +void TwoGateSaturatingAdd(const int8_t* input, int8_t input_zp, + const int8_t* recurrent, int8_t recurrent_zp, + int32_t input_effective_scale_a, + int32_t input_effective_scale_b, + int32_t recurrent_effective_scale_a, + int32_t recurrent_effective_scale_b, int32_t n_batch, + int32_t n_cell, int16_t* output) { + PortableTwoGateSaturatingAdd( + input, input_zp, recurrent, recurrent_zp, input_effective_scale_a, + input_effective_scale_b, recurrent_effective_scale_a, + recurrent_effective_scale_b, n_batch, n_cell, output); +} + +} // namespace tensor_utils +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PORTABLE_TENSOR_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils_impl.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils_impl.h new file mode 100644 index 0000000..6c404d5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils_impl.h @@ -0,0 +1,244 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PORTABLE_TENSOR_UTILS_IMPL_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PORTABLE_TENSOR_UTILS_IMPL_H_ + +#include +#include + +#if defined(_MSC_VER) +#define __restrict__ __restrict +#endif + +namespace tflite { + +// Not all backends support CpuBackendContext usage, so forward declare to avoid +// pulling in its implementation. +class CpuBackendContext; + +namespace tensor_utils { + +template +bool PortableIsZeroVector(const T* vector, int v_size) { + for (int i = 0; i < v_size; ++i) { + if (vector[i] != 0) { + return false; + } + } + return true; +} + +void PortableSymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float* min_value, + float* max_value, float* scaling_factor); + +void PortableSymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, float min_value, + float max_value, float* scaling_factor); + +void PortableAsymmetricQuantizeFloats(const float* values, const int size, + int8_t* quantized_values, + float* scaling_factor, int32_t* offset); + +// Multiply a matrix by a batch vector, and store results in a batch-size +// vector. +void PortableMatrixBatchVectorMultiplyAccumulate(const float* matrix, + int m_rows, int m_cols, + const float* vector, + int n_batch, float* result); + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, const float* scaling_factors, + int n_batch, float* __restrict__ result); + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vectors, const float* scaling_factors, + int n_batch, float* __restrict__ result, const float* per_channel_scale, + const int32_t* input_offset, int32_t* scratch, int32_t* row_sums, + bool* compute_row_sums, CpuBackendContext* context); + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const int m_rows, const int m_cols, + const int8_t* __restrict__ vector, const float* scaling_factors, + int n_batch, int32_t* scratch, float* __restrict__ result, + CpuBackendContext* context); + +void PortableSparseMatrixBatchVectorMultiplyAccumulate1x4( + const float* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const float* __restrict__ vector, int n_batch, float* __restrict__ result); + +void PortableSparseMatrixBatchVectorMultiplyAccumulate( + const float* __restrict__ matrix, const uint8_t* __restrict__ ledger, + int m_rows, int m_cols, const float* __restrict__ vector, int n_batch, + float* __restrict__ result); + +void PortableSparseMatrixBatchVectorMultiplyAccumulate1x16( + const int8_t* __restrict__ matrix, const int32_t* __restrict__ segments, + const int32_t* __restrict__ indices, int m_rows, int m_cols, + const int8_t* __restrict__ vector, const int32_t* __restrict__ bias_vector, + int n_batch, const int32_t input_offset, const int32_t output_multiplier, + const int32_t output_shift, const int32_t output_offset, + const int32_t output_activation_min, const int32_t output_activation_max, + int8_t* __restrict__ result); + +void PortableSparseMatrixBatchVectorMultiplyAccumulate( + const int8_t* __restrict__ matrix, const uint8_t* ledger, const int m_rows, + const int m_cols, const int8_t* __restrict__ vectors, + const float* scaling_factors, int n_batch, float* __restrict__ result); + +// Dot product of two vectors. +float PortableVectorVectorDotProduct(const float* vector1, const float* vector2, + int v_size); + +void PortableBatchVectorBatchVectorDotProduct(const int16_t* vector1, + const int16_t* vector2, + int v_size, int n_batch, + int32_t* result); + +void PortableVectorBatchVectorCwiseProductAccumulate( + const int16_t* vector, int v_size, const int16_t* batch_vector, int n_batch, + int32_t multiplier, int shift, int16_t* result); + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int16_t* output, CpuBackendContext* context); + +void PortableMatrixBatchVectorMultiplyAccumulate( + const int8_t* input, const int32_t* bias, + const int8_t* input_to_gate_weights, int32_t multiplier, int32_t shift, + int32_t n_batch, int32_t n_input, int32_t n_output, int32_t output_zp, + int32_t* scratch, int8_t* output, CpuBackendContext* context); + +void PortableMatrixBatchVectorMultiply(const int8_t* input, + int32_t input_zeropoint, + const int8_t* input_to_gate_weights, + int32_t input_to_gate_effective_scale_a, + int32_t input_to_gate_effective_scale_b, + int32_t n_batch, int32_t n_input, + int32_t n_cell, int8_t* gate_output, + int8_t gate_output_zp); + +void PortableMatrixBatchVectorMultiply( + const int16_t* hidden, const int8_t* hidden_to_output_weights, + int32_t proj_effective_scale_a, int32_t proj_effective_scale_b, + const int32_t* gate_bias, int32_t n_batch, int32_t n_hidden, + int32_t n_output, int32_t output_zp, int8_t* proj_output); + +void PortableMatrixScalarMultiplyAccumulate(const int8_t* matrix, + int32_t scalar, int32_t n_row, + int32_t n_col, int32_t* output); + +void PortableApplyLayerNorm(const int16_t* input, + const int16_t* layer_norm_weights, + const int32_t* bias, int32_t layer_norm_scale_a, + int32_t layer_norm_scale_b, int32_t variance_limit, + int n_batch, int n_input, int16_t* output); + +void PortableApplyLayerNormFloat(const int16_t* input, + const int16_t* layer_norm_weights, + int32_t layer_norm_scale_a, + int32_t layer_norm_scale_b, + const int32_t* bias, int n_batch, int n_input, + int16_t* output); + +void PortableApplySigmoid(const int16_t* input, int32_t n_batch, + int32_t n_input, int16_t* output); + +void PortableApplySigmoidFloat(const int16_t* input, int32_t n_batch, + int32_t n_input, int16_t* output); + +void PortableApplyTanh(int32_t integer_bits, const int16_t* input, + int32_t n_batch, int32_t n_input, int16_t* output); + +void PortableApplyTanhFloat(const int16_t* input, int32_t n_batch, + int32_t n_input, int32_t integer_bits, + int16_t* output); + +void PortableCwiseMul(const int16_t* input_1, const int16_t* input_2, + int n_batch, int n_input, int shift, int16_t* output); + +void PortableCwiseMul(const int16_t* input_1, const int16_t* input_2, + int32_t multiplier, int32_t shift, int32_t n_batch, + int32_t n_input, int32_t output_zp, int8_t* output); + +void PortableCwiseAdd(const int16_t* input_1, const int16_t* input_2, + int n_batch, int n_input, int16_t* output); + +template +void PortableCwiseClipping(T* vector, const int v_size, + const T& clipping_value) { + for (int i = 0; i < v_size; i++) { + vector[i] = std::max(std::min(clipping_value, vector[i]), + static_cast(-clipping_value)); + } +} + +// Batch vector initialization with another vector. +void PortableVectorBatchVectorAssign(const float* vector, int v_size, + int n_batch, float* batch_vector); + +// Compute "1.0f - elements of vector" (used in CIFG). +void PortableSub1Vector(const float* vector, int v_size, float* result); + +void PortableSub1Vector(const int16_t* vector, int v_size, int16_t* result); + +// Multiply all elements of vector with a scalar. +void PortableVectorScalarMultiply(const int8_t* vector, int v_size, float scale, + float* result); + +// Reduce-sum on a vector: +// input_vector: pointer to input vector. +// output_vector: pointer to vector. +// output_size: output vector size. +// reduction_size: number of consecutive elements from input vector which are +// added to get one element of output. +template +void PortableReductionSumVector(const INPUT* input_vector, + OUTPUT* output_vector, int output_size, + int reduction_size) { + for (int o = 0; o < output_size; o++) { + OUTPUT result = 0; + for (int r = 0; r < reduction_size; r++) { + result += input_vector[r]; + } + output_vector[o] = result; + input_vector += reduction_size; + } +} + +// Layer norm for each batch. +void PortableMeanStddevNormalization(const float* __restrict__ input_vector, + float* __restrict__ output_vector, + int v_size, int n_batch); + +// Saturate Add. +void PortableTwoGateSaturatingAdd(const int8_t* input, int8_t input_zp, + const int8_t* recurrent, int8_t recurrent_zp, + int32_t input_effective_scale_a, + int32_t input_effective_scale_b, + int32_t recurrent_effective_scale_a, + int32_t recurrent_effective_scale_b, + int32_t n_batch, int32_t n_cell, + int16_t* output); + +} // namespace tensor_utils +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_REFERENCE_PORTABLE_TENSOR_UTILS_IMPL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/runtime_shape.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/runtime_shape.h new file mode 100644 index 0000000..c2678b5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/runtime_shape.h @@ -0,0 +1,158 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_RUNTIME_SHAPE_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_RUNTIME_SHAPE_H_ + +namespace tflite { + +template +struct Dims { + int sizes[N]; + int strides[N]; +}; + +class RuntimeShape { + public: + RuntimeShape& operator=(RuntimeShape const&) = delete; + + // RuntimeShape in TFLM supports up to 5 dimensions. + // The name kMaxSmallSize comes from the same file of the upstream + // tensorflow lite repo and need to be kept the same for max reuse. + static constexpr int kMaxSmallSize = 5; + + RuntimeShape() : size_(0) {} + + explicit RuntimeShape(int dimensions_count) : size_(dimensions_count) {} + + RuntimeShape(int shape_size, int32_t value) : size_(shape_size) { + for (int i = 0; i < shape_size; ++i) { + SetDim(i, value); + } + } + + RuntimeShape(int dimensions_count, const int32_t* dims_data) + : size_(dimensions_count) { + ReplaceWith(dimensions_count, dims_data); + } + + bool operator==(const RuntimeShape& comp) const { + return this->size_ == comp.size_ && + std::memcmp(DimsData(), comp.DimsData(), size_ * sizeof(int32_t)) == + 0; + } + + ~RuntimeShape() {} + + int32_t DimensionsCount() const { return size_; } + int32_t Dims(int i) const { + TFLITE_DCHECK_GE(i, 0); + TFLITE_DCHECK_LT(i, size_); + return dims_[i]; + } + void SetDim(int i, int32_t val) { + TFLITE_DCHECK_GE(i, 0); + TFLITE_DCHECK_LT(i, size_); + dims_[i] = val; + } + + static RuntimeShape ExtendedShape(int new_shape_size, + const RuntimeShape& shape) { + return RuntimeShape(new_shape_size, shape, 1); + } + int32_t* DimsData() { return dims_; } + const int32_t* DimsData() const { return dims_; } + const int32_t* DimsDataUpTo5D() const { return dims_; } + + void ReplaceWith(int dimensions_count, const int32_t* dims_data) { + size_ = dimensions_count; + int32_t* dst_dims = DimsData(); + std::memcpy(dst_dims, dims_data, dimensions_count * sizeof(int32_t)); + } + + // Returns the total count of elements, that is the size when flattened into a + // vector. + int FlatSize() const { + int buffer_size = 1; + const int* dims_data = reinterpret_cast(DimsData()); + for (int i = 0; i < size_; i++) { + buffer_size *= dims_data[i]; + } + return buffer_size; + } + + private: + // For use only by ExtendedShape(), written to guarantee (return-value) copy + // elision in C++17. + // This creates a shape padded to the desired size with the specified value. + RuntimeShape(int new_shape_size, const RuntimeShape& shape, int pad_value) + : size_(new_shape_size) { + // If the following check fails, it is likely because a 4D-only kernel is + // being used with an array of larger dimension count. + TFLITE_CHECK_GE(new_shape_size, shape.DimensionsCount()); + const int size_increase = new_shape_size - shape.DimensionsCount(); + for (int i = 0; i < size_increase; ++i) { + SetDim(i, pad_value); + } + std::memcpy(DimsData() + size_increase, shape.DimsData(), + sizeof(int32_t) * shape.DimensionsCount()); + } + + int32_t size_; + union { + int32_t dims_[kMaxSmallSize]; + }; +}; + +// Since tensors with '0' in their shape are valid in TF, these offset functions +// allow that as long as the corresponding index is also 0. It is upto the +// calling ops to ensure that they perform verification checks on tensor shapes +// if they don't support a particular behavior. + +inline int Offset(const RuntimeShape& shape, int i0, int i1, int i2, int i3) { + TFLITE_DCHECK_EQ(shape.DimensionsCount(), 4); + const int* dims_data = reinterpret_cast(shape.DimsData()); + TFLITE_DCHECK((dims_data[0] == 0 && i0 == 0) || + (i0 >= 0 && i0 < dims_data[0])); + TFLITE_DCHECK((dims_data[1] == 0 && i1 == 0) || + (i1 >= 0 && i1 < dims_data[1])); + TFLITE_DCHECK((dims_data[2] == 0 && i2 == 0) || + (i2 >= 0 && i2 < dims_data[2])); + TFLITE_DCHECK((dims_data[3] == 0 && i3 == 0) || + (i3 >= 0 && i3 < dims_data[3])); + return ((i0 * dims_data[1] + i1) * dims_data[2] + i2) * dims_data[3] + i3; +} + +inline int Offset(const RuntimeShape& shape, int i0, int i1, int i2, int i3, + int i4) { + TFLITE_DCHECK_EQ(shape.DimensionsCount(), 5); + const int* dims_data = reinterpret_cast(shape.DimsData()); + TFLITE_DCHECK((dims_data[0] == 0 && i0 == 0) || + (i0 >= 0 && i0 < dims_data[0])); + TFLITE_DCHECK((dims_data[1] == 0 && i1 == 0) || + (i1 >= 0 && i1 < dims_data[1])); + TFLITE_DCHECK((dims_data[2] == 0 && i2 == 0) || + (i2 >= 0 && i2 < dims_data[2])); + TFLITE_DCHECK((dims_data[3] == 0 && i3 == 0) || + (i3 >= 0 && i3 < dims_data[3])); + TFLITE_DCHECK((dims_data[4] == 0 && i4 == 0) || + (i4 >= 0 && i4 < dims_data[4])); + return (((i0 * dims_data[1] + i1) * dims_data[2] + i2) * dims_data[3] + i3) * + dims_data[4] + + i4; +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_RUNTIME_SHAPE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/strided_slice_logic.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/strided_slice_logic.h new file mode 100644 index 0000000..18a7940 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/strided_slice_logic.h @@ -0,0 +1,274 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_STRIDED_SLICE_LOGIC_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_STRIDED_SLICE_LOGIC_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace strided_slice { + +// Use until std::clamp() is available from C++17. +inline int Clamp(const int v, const int lo, const int hi) { + TFLITE_DCHECK(!(hi < lo)); + if (hi < v) return hi; + if (v < lo) return lo; + return v; +} + +inline void StridedSlicePadIndices(tflite::StridedSliceParams* p, + int dim_count) { + // Add indices and mask bits to fully include extra dimensions + TFLITE_CHECK_LE(dim_count, 5); + TFLITE_CHECK_GE(dim_count, p->start_indices_count); + TFLITE_CHECK_EQ(p->start_indices_count, p->stop_indices_count); + TFLITE_CHECK_EQ(p->stop_indices_count, p->strides_count); + + const int pad_count = dim_count - p->start_indices_count; + + // Pad indices at start, so move arrays by pad_count. + for (int i = p->start_indices_count - 1; i >= 0; --i) { + p->strides[i + pad_count] = p->strides[i]; + p->start_indices[i + pad_count] = p->start_indices[i]; + p->stop_indices[i + pad_count] = p->stop_indices[i]; + } + for (int i = 0; i < pad_count; ++i) { + p->start_indices[i] = 0; + p->stop_indices[i] = 1; + p->strides[i] = 1; + } + + // Pad masks with 0s or 1s as required. + p->shrink_axis_mask <<= pad_count; + p->ellipsis_mask <<= pad_count; + p->new_axis_mask <<= pad_count; + p->begin_mask <<= pad_count; + p->end_mask <<= pad_count; + p->begin_mask |= (1 << pad_count) - 1; + p->end_mask |= (1 << pad_count) - 1; + + p->start_indices_count = dim_count; + p->stop_indices_count = dim_count; + p->strides_count = dim_count; +} + +// Return the index for the first element along that axis. This index will be a +// positive integer between [0, axis_size] (or [-1, axis_size -1] if stride < 0) +// that can be used to index directly into the data. +inline int StridedSliceStartForAxis(const tflite::StridedSliceParams& params, + const RuntimeShape& input_shape, + int32_t axis) { + const int32_t axis_size = input_shape.Dims(axis); + int32_t start = params.start_indices[axis]; + const int32_t stride = params.strides[axis]; + const int32_t begin_mask = (params.begin_mask & 1 << axis); + if (start < 0) { + start += axis_size; + } + if (stride > 0) { + start = Clamp(start, 0, axis_size); + } else { + start = Clamp(start, -1, axis_size - 1); + } + if (begin_mask) { + if (stride > 0) { + start = 0; + } else { + start = axis_size - 1; + } + } + return start; +} + +inline int StridedSliceEndForAxis(const tflite::StridedSliceParams& params, + const RuntimeShape& input_shape, int axis, + int start) { + const auto shrink_axis_mask = params.shrink_axis_mask; + const bool shrink_axis = shrink_axis_mask & (1 << axis); + const int axis_size = input_shape.Dims(axis); + if (shrink_axis) { + if (start >= axis_size) { + return start; + } else { + return start + 1; + } + } + const auto* indices = params.stop_indices; + int end = indices[axis]; + const int32_t stride = params.strides[axis]; + const int32_t end_mask = (params.end_mask & 1 << axis); + if (end < 0) { + end += axis_size; + } + if (stride > 0) { + end = Clamp(end, 0, axis_size); + } else { + end = Clamp(end, -1, axis_size - 1); + } + if (end_mask) { + if (stride > 0) { + end = axis_size; + } else { + end = -1; + } + } + return end; +} + +// Return the index for the first element along that axis. This index will be a +// positive integer between [0, axis_size] (or [-1, axis_size -1] if stride < 0) +// that can be used to index directly into the data. +inline int StartForAxis(const tflite::StridedSliceParams& params, + const RuntimeShape& input_shape, int axis) { + const auto begin_mask = params.begin_mask; + const auto* start_indices = params.start_indices; + const auto* strides = params.strides; + const int axis_size = input_shape.Dims(axis); + if (axis_size == 0) { + return 0; + } + // Begin with the specified index. + int start = start_indices[axis]; + + // begin_mask override + if (begin_mask & 1 << axis) { + if (strides[axis] > 0) { + // Forward iteration - use the first element. These values will get + // clamped below (Note: We could have set them to 0 and axis_size-1, but + // use lowest() and max() to maintain symmetry with StopForAxis()) + start = std::numeric_limits::lowest(); + } else { + // Backward iteration - use the last element. + start = std::numeric_limits::max(); + } + } + + // Handle negative indices + if (start < 0) { + start += axis_size; + } + + // Clamping + if (strides[axis] > 0) { + // Forward iteration + start = Clamp(start, 0, axis_size); + } else { + // Backward iteration + start = Clamp(start, -1, axis_size - 1); + } + + return start; +} + +// Return the "real" index for the end of iteration along that axis. This is an +// "end" in the traditional C sense, in that it points to one past the last +// element. ie. So if you were iterating through all elements of a 1D array of +// size 4, this function would return 4 as the stop, because it is one past the +// "real" indices of 0, 1, 2 & 3. +inline int StopForAxis(const tflite::StridedSliceParams& params, + const RuntimeShape& input_shape, int axis, + int start_for_axis) { + const auto end_mask = params.end_mask; + const auto shrink_axis_mask = params.shrink_axis_mask; + const auto* stop_indices = params.stop_indices; + const auto* strides = params.strides; + const int axis_size = input_shape.Dims(axis); + if (axis_size == 0) { + return 0; + } + + // Begin with the specified index + const bool shrink_axis = shrink_axis_mask & (1 << axis); + int stop = stop_indices[axis]; + + // When shrinking an axis, the end position does not matter (and can be + // incorrect when negative indexing is used, see Issue #19260). Always use + // start_for_axis + 1 to generate a length 1 slice, since start_for_axis has + // already been adjusted for negative indices. + if (shrink_axis) { + return start_for_axis + 1; + } + + // end_mask override + if (end_mask & (1 << axis)) { + if (strides[axis] > 0) { + // Forward iteration - use the last element. These values will get + // clamped below + stop = std::numeric_limits::max(); + } else { + // Backward iteration - use the first element. + stop = std::numeric_limits::lowest(); + } + } + + // Handle negative indices + if (stop < 0) { + stop += axis_size; + } + + // Clamping + // Because the end index points one past the last element, we need slightly + // different clamping ranges depending on the direction. + if (strides[axis] > 0) { + // Forward iteration + stop = Clamp(stop, 0, axis_size); + } else { + // Backward iteration + stop = Clamp(stop, -1, axis_size - 1); + } + + return stop; +} + +inline bool LoopCondition(int index, int stop, int stride) { + // True when we have reached the end of an axis and should loop. + return stride > 0 ? index >= stop : index <= stop; +} + +inline tflite::StridedSliceParams BuildStridedSliceParams( + int begin_mask, int end_mask, int shrink_axis_mask, + const std::vector& start_indices, const std::vector& stop_indices, + const std::vector& strides) { + tflite::StridedSliceParams op_params; + const int dims_count = start_indices.size(); + + op_params.start_indices_count = dims_count; + op_params.stop_indices_count = dims_count; + op_params.strides_count = dims_count; + for (int i = 0; i < dims_count; ++i) { + op_params.start_indices[i] = start_indices[i]; + op_params.stop_indices[i] = stop_indices[i]; + op_params.strides[i] = strides[i]; + } + + op_params.begin_mask = begin_mask; + op_params.ellipsis_mask = 0; + op_params.end_mask = end_mask; + op_params.new_axis_mask = 0; + op_params.shrink_axis_mask = shrink_axis_mask; + + return op_params; +} + +} // namespace strided_slice + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_STRIDED_SLICE_LOGIC_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h new file mode 100644 index 0000000..de2d802 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h @@ -0,0 +1,47 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_TENSOR_CTYPES_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_TENSOR_CTYPES_H_ + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +template +inline T* GetTensorData(TfLiteTensor* tensor) { + return tensor != nullptr ? reinterpret_cast(tensor->data.raw) : nullptr; +} + +template +inline const T* GetTensorData(const TfLiteTensor* tensor) { + return tensor != nullptr ? reinterpret_cast(tensor->data.raw) + : nullptr; +} + +inline RuntimeShape GetTensorShape(const TfLiteTensor* tensor) { + if (tensor == nullptr) { + return RuntimeShape(); + } + + TfLiteIntArray* dims = tensor->dims; + const int dims_size = dims->size; + const int32_t* dims_data = reinterpret_cast(dims->data); + return RuntimeShape(dims_size, dims_data); +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_TENSOR_CTYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_utils.cpp new file mode 100644 index 0000000..7527994 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_utils.cpp @@ -0,0 +1,25 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +============================================================================== +*/ + +// internal/reference_portable_tensor_utils.h has the implementation of the +// functions declared in internal/portable_tensor_utils.h. This somewhat +// confusing setup is derived from how the code is organized in TfLite where it +// is used to select between NEON, SSE and portable implementaitons. See +// https://github.com/tensorflow/tensorflow/blob/d76c23975c4a3a0d7987cfe3f45c76566df06180/tensorflow/lite/kernels/internal/tensor_utils.cc +// for how the code is written in TfLite. + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference_portable_tensor_utils.h" diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h new file mode 100644 index 0000000..9e73812 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h @@ -0,0 +1,1067 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_INTERNAL_TYPES_H_ +#define TENSORFLOW_LITE_KERNELS_INTERNAL_TYPES_H_ + +#include +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/runtime_shape.h" + +namespace tflite { + +enum class FusedActivationFunctionType : uint8_t { + kNone, + kRelu6, + kRelu1, + kRelu +}; +enum class PaddingType : uint8_t { kNone, kSame, kValid }; + +struct PaddingValues { + int16_t width; + int16_t height; + // offset is used for calculating "remaining" padding, for example, `width` + // is 1 and `width_offset` is 1, so padding_left is 1 while padding_right is + // 1 + 1 = 2. + int16_t width_offset; + // Same as width_offset except it's over the height dimension. + int16_t height_offset; +}; + +struct Padding3DValues { + int16_t width; + int16_t height; + int16_t depth; + // offset is used for calculating "remaining" padding, for example, `width` + // is 1 and `width_offset` is 1, so padding_left is 1 while padding_right is + // 1 + 1 = 2. + int16_t width_offset; + // Same as width_offset except it's over the height dimension. + int16_t height_offset; + // Same as width_offset except it's over the depth dimension. + int16_t depth_offset; +}; + +// This enumeration allows for non-default formats for the weights array +// of a fully-connected operator, allowing the use of special optimized +// runtime paths. +enum class FullyConnectedWeightsFormat : uint8_t { + // Default format (flat 2D layout, the inner contiguous dimension + // is input_depth, the outer non-contiguous dimension is output_depth) + kDefault, + // Summary: optimized layout for fast CPU runtime implementation, + // aimed specifically at ARM CPUs at the moment, and specialized for + // 8-bit quantized layers. + // + // The use case we're concerned with here is: 8-bit quantization, + // large weights matrix that doesn't fit in cache (e.g. 4096x2048 in + // a key application that drove this), very small batch size (e.g. 1 -- 4). + // + // Even with 8-bit quantization of weights, the performance of memory + // accesses to the weights can become the dominant issue when + // the batch size is small, so each weight value is used in only a few + // arithmetic ops, i.e. the fully-connected node has a low arithmetic + // intensity. The specific issues that arise are of three kinds: + // (1) One may, ideally, max out DRAM bandwidth, i.e. be truly memory + // bound. That's the "good" issue to run into. + // (2) One may run into sub-optimal pre-fetching: the data hasn't been + // prefetched into the cache by the time we need it. + // (3) One may run into cache aliasing: multiple values that are + // pre-fetched, alias each other in the L1 cache (which typically + // has only 4-way set associativity in ARM CPUs) and thus evict + // each other before we get to using them. + // + // The point of this shuffling is to avoid issues (2) and (3) so that + // we get as fast as possible given only the hard constraint (1). + // This is achieved by turning the difficulty into a solution: the + // difficulty, that each value loaded from memory is used only in + // one kernel iteration, making this operation memory-intensive, hints at + // the solution, of shuffling the weights so that they are stored in the + // exact order as the kernel needs to load them, so that the memory + // accesses made by the kernel are trivial. This solves (2) because the + // trivial memory access pattern allows the CPU's automatic prefetching + // to perform very well (no need even for preload instructions), and this + // solves (3) because the values being loaded concurrently are now + // contiguous in the address space, thus don't alias each other in the cache. + // + // On ARM, we typically want our kernel to process a 4x16 block of weights + // at a time, because: + // - 16 is the number of bytes in a NEON register. + // - 4 is how many rows we need to handle concurrently in the kernel in + // order to have sufficient mutual independence of instructions to + // maximize arithmetic throughput. + // + // Finally, the 'Int8' part in the name refers to the fact that this + // weights format has each weights value encoded as a signed int8_t value, + // even if the data type of the weights buffer is uint8_t. This is intended + // to save runtime kernels the effort to have to XOR the top bit of these + // bytes before using them in signed arithmetic, see this file for more + // explanations on the 'signed int8_t trick' in matrix multiplication kernels: + // + // tensorflow/lite/toco/graph_transformations/ensure_uint8_weights_safe_for_fast_int8_kernels.cc + // + kShuffled4x16Int8, +}; + +// Quantization parameters, determining the mapping of quantized values +// to real values (i.e. determining how quantized values are mathematically +// interpreted). +// +// The correspondence is as follows: +// +// real_value = scale * (quantized_value - zero_point); +// +// In other words, zero_point designates which quantized value corresponds to +// the real 0 value, and scale designates the difference between the real values +// corresponding to consecutive quantized values differing by 1. +struct QuantizationParams { + int32_t zero_point = 0; + double scale = 0.0; +}; + +inline bool operator==(const QuantizationParams& qp1, + const QuantizationParams& qp2) { + return qp1.zero_point == qp2.zero_point && qp1.scale == qp2.scale; +} + +// Quantization parameters for each channel, determining the mapping of +// quantized values to real values. See QuantizationParams for a single set of +// parameters per tensor. This has one parameters set per each channel. +// +// The correspondence is as follows: +// +// real_value = scale[channel] * (quantized_value - zero_point[channel]); +// +struct PerChannelQuantizationParams { + // The following members typically point to the corresponding members of a + // TfLiteAffineQuantization struct. + const float* scale; + const int32_t* zero_point; + int32_t quantized_dimension; +}; + +// Gets next index to iterate through a multidimensional array. +inline bool NextIndex(const int num_dims, const int* dims, int* current) { + if (num_dims == 0) { + return false; + } + TFLITE_DCHECK(dims != nullptr); + TFLITE_DCHECK(current != nullptr); + int carry = 1; + for (int idx = num_dims - 1; idx >= 0; --idx) { + int current_val = current[idx] + carry; + TFLITE_DCHECK_GE(dims[idx], current_val); + if (dims[idx] == current_val) { + current[idx] = 0; + } else { + current[idx] = current_val; + carry = 0; + break; + } + } + return (carry == 0); +} + +// Gets offset of index if reducing on axis. When reducing, the flattened offset +// will not change, if the input index changes on the given axis. For example, +// if you have a 3D tensor and you are reducing to 2D by eliminating axis 0, +// then index (0, 1, 2) and index (1, 1, 2) will map to the same flattened +// offset. +// TODO(kanlig): uses Dims to represent dimensions. +inline size_t ReducedOutputOffset(const int num_dims, const int* dims, + const int* index, const int num_axis, + const int* axis) { + if (num_dims == 0) { + return 0; + } + TFLITE_DCHECK(dims != nullptr); + TFLITE_DCHECK(index != nullptr); + size_t offset = 0; + for (int idx = 0; idx < num_dims; ++idx) { + // if we need to skip this axis + bool is_axis = false; + if (axis != nullptr) { + for (int axis_idx = 0; axis_idx < num_axis; ++axis_idx) { + if (idx == axis[axis_idx]) { + is_axis = true; + break; + } + } + } + if (!is_axis) { + offset = offset * static_cast(dims[idx]) + + static_cast(index[idx]); + } + } + return offset; +} + +// Since tensors with '0' in their shape are valid in TF, these offset functions +// allow that as long as the corresponding index is also 0. It is upto the +// calling ops to ensure that they perform verification checks on tensor shapes +// if they don't support a particular behavior. + +inline int Offset(const Dims<4>& dims, int i0, int i1, int i2, int i3) { + TFLITE_DCHECK((i0 == 0 && dims.sizes[0] == 0) || + (i0 >= 0 && i0 < dims.sizes[0])); + TFLITE_DCHECK((i1 == 0 && dims.sizes[1] == 0) || + (i1 >= 0 && i1 < dims.sizes[1])); + TFLITE_DCHECK((i2 == 0 && dims.sizes[2] == 0) || + (i2 >= 0 && i2 < dims.sizes[2])); + TFLITE_DCHECK((i3 == 0 && dims.sizes[3] == 0) || + (i3 >= 0 && i3 < dims.sizes[3])); + return i0 * dims.strides[0] + i1 * dims.strides[1] + i2 * dims.strides[2] + + i3 * dims.strides[3]; +} + +inline int Offset(const Dims<4>& dims, int* index) { + return Offset(dims, index[0], index[1], index[2], index[3]); +} + +// Get array size, DCHECKing that the dim index is in range. +// +// Note that this will be phased out with Dims<4>, since RuntimeShape::Dims() +// already performs this check. +template +int ArraySize(const Dims& array, int index) { + TFLITE_DCHECK(index >= 0 && index < N); + return array.sizes[index]; +} + +// Get common array size, DCHECKing that they all agree. +template +int MatchingArraySize(const ArrayType1& array1, int index1, + const ArrayType2& array2, int index2) { + TFLITE_DCHECK_EQ(ArraySize(array1, index1), ArraySize(array2, index2)); + return ArraySize(array1, index1); +} + +template +int MatchingArraySize(const ArrayType1& array1, int index1, + const ArrayType2& array2, int index2, Args... args) { + TFLITE_DCHECK_EQ(ArraySize(array1, index1), ArraySize(array2, index2)); + return MatchingArraySize(array1, index1, args...); +} + +// Get common shape dim, DCHECKing that they all agree. +inline int MatchingDim(const RuntimeShape& shape1, int index1, + const RuntimeShape& shape2, int index2) { + TFLITE_DCHECK_EQ(shape1.Dims(index1), shape2.Dims(index2)); + return std::min(shape1.Dims(index1), shape2.Dims(index2)); +} + +template +int MatchingDim(const RuntimeShape& shape1, int index1, + const RuntimeShape& shape2, int index2, Args... args) { + TFLITE_DCHECK_EQ(shape1.Dims(index1), shape2.Dims(index2)); + return MatchingDim(shape1, index1, args...); +} + +// Will be phased out with Dims<4>, replaced by RuntimeShape::FlatSize(). +template +inline int FlatSize(const Dims& dims) { + int flat_size = 1; + for (int i = 0; i < N; ++i) { + flat_size *= dims.sizes[i]; + } + return flat_size; +} + +TFLITE_DEPRECATED("Prefer FlatSize.") +inline int RequiredBufferSizeForDims(const Dims<4>& dims) { + return FlatSize(dims); +} + +inline int MatchingElementsSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0) { + const int size_1 = shape.FlatSize(); + const int size_2 = check_shape_0.FlatSize(); + TFLITE_CHECK_EQ(size_1, size_2); + return size_1; +} + +inline int MatchingElementsSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1) { + const int size_1 = shape.FlatSize(); + const int size_2 = check_shape_0.FlatSize(); + const int size_3 = check_shape_1.FlatSize(); + TFLITE_CHECK_EQ(size_1, size_2); + TFLITE_CHECK_EQ(size_2, size_3); + return size_1; +} + +// Flat size calculation, checking that dimensions match with one or more other +// arrays. +inline int MatchingFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0) { + TFLITE_DCHECK_EQ(shape.DimensionsCount(), check_shape_0.DimensionsCount()); + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + return shape.FlatSize(); +} + +inline int MatchingFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1) { + TFLITE_DCHECK_EQ(shape.DimensionsCount(), check_shape_0.DimensionsCount()); + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + return MatchingFlatSize(shape, check_shape_1); +} + +inline int MatchingFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1, + const RuntimeShape& check_shape_2) { + TFLITE_DCHECK_EQ(shape.DimensionsCount(), check_shape_0.DimensionsCount()); + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + return MatchingFlatSize(shape, check_shape_1, check_shape_2); +} + +inline int MatchingFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1, + const RuntimeShape& check_shape_2, + const RuntimeShape& check_shape_3) { + TFLITE_DCHECK_EQ(shape.DimensionsCount(), check_shape_0.DimensionsCount()); + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + return MatchingFlatSize(shape, check_shape_1, check_shape_2, check_shape_3); +} + +// Flat size calculation, checking that dimensions match with one or more other +// arrays. +template +inline int MatchingFlatSize(const Dims& dims, const Dims& check_dims_0) { + for (int i = 0; i < N; ++i) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + return FlatSize(dims); +} + +template +inline int MatchingFlatSize(const Dims& dims, const Dims& check_dims_0, + const Dims& check_dims_1) { + for (int i = 0; i < N; ++i) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + return MatchingFlatSize(dims, check_dims_1); +} + +template +inline int MatchingFlatSize(const Dims& dims, const Dims& check_dims_0, + const Dims& check_dims_1, + const Dims& check_dims_2) { + for (int i = 0; i < N; ++i) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + return MatchingFlatSize(dims, check_dims_1, check_dims_2); +} + +template +inline int MatchingFlatSize(const Dims& dims, const Dims& check_dims_0, + const Dims& check_dims_1, + const Dims& check_dims_2, + const Dims& check_dims_3) { + for (int i = 0; i < N; ++i) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + return MatchingFlatSize(dims, check_dims_1, check_dims_2, check_dims_3); +} + +// Flat size calculation, checking if their extended shapes match. +inline int MatchingExtendedShapeFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0) { + const int shape_dims = shape.DimensionsCount(); + const int check_shape_0_dims = check_shape_0.DimensionsCount(); + const int min_dims = std::min(shape_dims, check_shape_0_dims); + + for (int i = 0; i < min_dims; ++i) { + TFLITE_DCHECK_EQ(shape.Dims(shape_dims - 1 - i), + check_shape_0.Dims(check_shape_0_dims - 1 - i)); + } + for (int i = min_dims; i < shape_dims; ++i) { + TFLITE_DCHECK_EQ(shape.Dims(shape_dims - 1 - i), 1); + } + for (int i = min_dims; i < check_shape_0_dims; ++i) { + TFLITE_DCHECK_EQ(check_shape_0.Dims(check_shape_0_dims - 1 - i), 1); + } + return shape.FlatSize(); +} + +inline int MatchingExtendedShapeFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1) { + const int flat_size = MatchingExtendedShapeFlatSize(shape, check_shape_0); + TFLITE_DCHECK_EQ(MatchingExtendedShapeFlatSize(shape, check_shape_1), + flat_size); + return flat_size; +} + +inline int MatchingExtendedShapeFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1, + const RuntimeShape& check_shape_2) { + const int flat_size = MatchingExtendedShapeFlatSize(shape, check_shape_0); + TFLITE_DCHECK_EQ( + MatchingExtendedShapeFlatSize(shape, check_shape_1, check_shape_2), + flat_size); + return flat_size; +} + +inline int MatchingExtendedShapeFlatSize(const RuntimeShape& shape, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1, + const RuntimeShape& check_shape_2, + const RuntimeShape& check_shape_3) { + const int flat_size = MatchingExtendedShapeFlatSize(shape, check_shape_0); + TFLITE_DCHECK_EQ(MatchingExtendedShapeFlatSize(shape, check_shape_1, + check_shape_2, check_shape_3), + flat_size); + return flat_size; +} + +// Data is required to be contiguous, and so many operators can use either the +// full array flat size or the flat size with one dimension skipped (commonly +// the depth). +template +inline int FlatSizeSkipDim(const Dims& dims, int skip_dim) { + TFLITE_DCHECK(skip_dim >= 0 && skip_dim < N); + int flat_size = 1; + for (int i = 0; i < N; ++i) { + flat_size *= (i == skip_dim) ? 1 : dims.sizes[i]; + } + return flat_size; +} + +// A combination of MatchingFlatSize() and FlatSizeSkipDim(). +template +inline int MatchingFlatSizeSkipDim(const Dims& dims, int skip_dim, + const Dims& check_dims_0) { + for (int i = 0; i < N; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + } + return FlatSizeSkipDim(dims, skip_dim); +} + +template +inline int MatchingFlatSizeSkipDim(const Dims& dims, int skip_dim, + const Dims& check_dims_0, + const Dims& check_dims_1) { + for (int i = 0; i < N; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + } + return MatchingFlatSizeSkipDim(dims, skip_dim, check_dims_1); +} + +template +inline int MatchingFlatSizeSkipDim(const Dims& dims, int skip_dim, + const Dims& check_dims_0, + const Dims& check_dims_1, + const Dims& check_dims_2) { + for (int i = 0; i < N; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + } + return MatchingFlatSizeSkipDim(dims, skip_dim, check_dims_1, check_dims_2); +} + +template +inline int MatchingFlatSizeSkipDim(const Dims& dims, int skip_dim, + const Dims& check_dims_0, + const Dims& check_dims_1, + const Dims& check_dims_2, + const Dims& check_dims_3) { + for (int i = 0; i < N; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(ArraySize(dims, i), ArraySize(check_dims_0, i)); + } + } + return MatchingFlatSizeSkipDim(dims, skip_dim, check_dims_1, check_dims_2, + check_dims_3); +} + +// Data is required to be contiguous, and so many operators can use either the +// full array flat size or the flat size with one dimension skipped (commonly +// the depth). +inline int FlatSizeSkipDim(const RuntimeShape& shape, int skip_dim) { + const int dims_count = shape.DimensionsCount(); + TFLITE_DCHECK(skip_dim >= 0 && skip_dim < dims_count); + const auto* dims_data = shape.DimsData(); + int flat_size = 1; + for (int i = 0; i < dims_count; ++i) { + flat_size *= (i == skip_dim) ? 1 : dims_data[i]; + } + return flat_size; +} + +// A combination of MatchingFlatSize() and FlatSizeSkipDim(). +inline int MatchingFlatSizeSkipDim(const RuntimeShape& shape, int skip_dim, + const RuntimeShape& check_shape_0) { + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + } + return FlatSizeSkipDim(shape, skip_dim); +} + +inline int MatchingFlatSizeSkipDim(const RuntimeShape& shape, int skip_dim, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1) { + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + } + return MatchingFlatSizeSkipDim(shape, skip_dim, check_shape_1); +} + +inline int MatchingFlatSizeSkipDim(const RuntimeShape& shape, int skip_dim, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1, + const RuntimeShape& check_shape_2) { + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + } + return MatchingFlatSizeSkipDim(shape, skip_dim, check_shape_1, check_shape_2); +} + +inline int MatchingFlatSizeSkipDim(const RuntimeShape& shape, int skip_dim, + const RuntimeShape& check_shape_0, + const RuntimeShape& check_shape_1, + const RuntimeShape& check_shape_2, + const RuntimeShape& check_shape_3) { + const int dims_count = shape.DimensionsCount(); + for (int i = 0; i < dims_count; ++i) { + if (i != skip_dim) { + TFLITE_DCHECK_EQ(shape.Dims(i), check_shape_0.Dims(i)); + } + } + return MatchingFlatSizeSkipDim(shape, skip_dim, check_shape_1, check_shape_2, + check_shape_3); +} + +template +bool IsPackedWithoutStrides(const Dims& dims) { + int expected_stride = 1; + for (int d = 0; d < N; d++) { + if (dims.strides[d] != expected_stride) return false; + expected_stride *= dims.sizes[d]; + } + return true; +} + +template +void ComputeStrides(Dims* dims) { + dims->strides[0] = 1; + for (int d = 1; d < N; d++) { + dims->strides[d] = dims->strides[d - 1] * dims->sizes[d - 1]; + } +} + +enum class BroadcastableOpCategory : uint8_t { + kNone, + kNonBroadcast, // Matching input shapes. + kFirstInputBroadcastsFast, // Fivefold nested loops. + kSecondInputBroadcastsFast, // Fivefold nested loops. + kGenericBroadcast, // Fall-back. +}; + +struct MinMax { + float min; + float max; +}; +static_assert(sizeof(MinMax) == 8, ""); + +struct ActivationParams { + FusedActivationFunctionType activation_type; + // uint8_t, etc, activation params. + int32_t quantized_activation_min; + int32_t quantized_activation_max; +}; + +struct ReluParams : public ActivationParams { + int32_t input_offset; + int32_t output_offset; + int32_t output_multiplier; + int output_shift; +}; + +// Styles of resizing op usages. For example, kImageStyle can be used with a Pad +// op for pattern-specific optimization. +enum class ResizingCategory : uint8_t { + kNone, + kImageStyle, // 4D, operating on inner dimensions, say {0, a, b, 0}. + kGenericResize, +}; + +// For Add, Sub, Mul ops. +struct ArithmeticParams { + // Shape dependent / common to data / op types. + BroadcastableOpCategory broadcast_category; + // uint8_t inference params. + int32_t input1_offset; + int32_t input2_offset; + int32_t output_offset; + int32_t output_multiplier; + int output_shift; + // Add / Sub, not Mul, uint8_t inference params. + int left_shift; + int32_t input1_multiplier; + int input1_shift; + int32_t input2_multiplier; + int input2_shift; + + // TODO(b/158622529): Union the following activation params. + // uint8_t, etc, activation params. + int32_t quantized_activation_min; + int32_t quantized_activation_max; + // float activation params. + float float_activation_min; + float float_activation_max; + // int64_t activation params. + int64_t int64_activation_min; + int64_t int64_activation_max; + + // Processed output dimensions. + // Let input "a" be the one that broadcasts in the faster-changing dimension. + // Then, after coalescing, for shapes {a0, a1, a2, a3, a4} and + // {b0, b1, b2, b3, b4}, + // broadcast_shape[4] = b0 = a0. + // broadcast_shape[3] = b1; a1 = 1. + // broadcast_shape[2] = b2 = a2. + // broadcast_shape[1] = a3; b3 = 1. + // broadcast_shape[0] = b4 = a4. + int broadcast_shape[5]; +}; + +struct ConcatenationParams { + int8_t axis; + const int32_t* input_zeropoint; + const float* input_scale; + uint16_t inputs_count; + int32_t output_zeropoint; + float output_scale; +}; + +struct ComparisonParams { + // uint8_t inference params. + int left_shift; + int32_t input1_offset; + int32_t input1_multiplier; + int input1_shift; + int32_t input2_offset; + int32_t input2_multiplier; + int input2_shift; + // Shape dependent / common to inference types. + bool is_broadcast; +}; + +struct ConvParams { + PaddingType padding_type; + PaddingValues padding_values; + // TODO(starka): This was just "stride", so check that width+height is OK. + int16_t stride_width; + int16_t stride_height; + int16_t dilation_width_factor; + int16_t dilation_height_factor; + // uint8_t inference params. + // TODO(b/65838351): Use smaller types if appropriate. + int32_t input_offset; + int32_t weights_offset; + int32_t output_offset; + int32_t output_multiplier; + int output_shift; + // uint8_t, etc, activation params. + int32_t quantized_activation_min; + int32_t quantized_activation_max; + // float activation params. + float float_activation_min; + float float_activation_max; +}; + +struct Conv3DParams { + Padding3DValues padding_values; + int stride_width; + int stride_height; + int stride_depth; + int dilation_width; + int dilation_height; + int dilation_depth; + // float activation params. + float float_activation_min; + float float_activation_max; +}; + +typedef Conv3DParams Conv3DTransposeParams; + +struct DepthToSpaceParams { + int32_t block_size; +}; + +struct DepthwiseParams { + PaddingType padding_type; + PaddingValues padding_values; + int16_t stride_width; + int16_t stride_height; + int16_t dilation_width_factor; + int16_t dilation_height_factor; + int16_t depth_multiplier; + // uint8_t inference params. + // TODO(b/65838351): Use smaller types if appropriate. + int32_t input_offset; + int32_t weights_offset; + int32_t output_offset; + int32_t output_multiplier; + int output_shift; + // uint8_t, etc, activation params. + int32_t quantized_activation_min; + int32_t quantized_activation_max; + // float activation params. + float float_activation_min; + float float_activation_max; + const int32_t* output_multiplier_per_channel; + const int32_t* output_shift_per_channel; +}; + +struct DequantizationParams { + double scale; + int32_t zero_point; +}; + +struct PerChannelDequantizationParams { + const float* scale; + const int32_t* zero_point; + int32_t quantized_dimension; +}; + +struct FakeQuantParams { + MinMax minmax; + int32_t num_bits; +}; + +struct FullyConnectedParams { + // uint8_t inference params. + // TODO(b/65838351): Use smaller types if appropriate. + int32_t input_offset; + int32_t weights_offset; + int32_t output_offset; + int32_t output_multiplier; + int output_shift; + // uint8_t, etc, activation params. + int32_t quantized_activation_min; + int32_t quantized_activation_max; + // float activation params. + float float_activation_min; + float float_activation_max; + // Mark the operands as cacheable if they are unchanging, e.g. weights. + bool lhs_cacheable; + bool rhs_cacheable; + FullyConnectedWeightsFormat weights_format; +}; + +struct GatherParams { + int16_t axis; + int16_t batch_dims; +}; + +struct L2NormalizationParams { + // uint8_t inference params. + int32_t input_zero_point; +}; + +struct LocalResponseNormalizationParams { + int32_t range; + double bias; + double alpha; + double beta; +}; + +struct HardSwishParams { + // zero_point of the input activations. + int16_t input_zero_point; + // zero_point of the output activations. + int16_t output_zero_point; + // 16bit fixed-point component of the multiplier to apply to go from the + // "high-res input scale", which is the input scale multiplied by 2^7, to the + // "relu-ish scale", which 3.0/32768. + // See the implementation of HardSwishPrepare. + int16_t reluish_multiplier_fixedpoint_int16; + // exponent/bit-shift component of the aforementioned multiplier. + int reluish_multiplier_exponent; + // 16bit fixed-point component of the multiplier to apply to go from the + // "high-res input scale", which is the input scale multiplied by 2^7, to the + // output scale. + // See the implementation of HardSwishPrepare. + int16_t output_multiplier_fixedpoint_int16; + // exponent/bit-shift component of the aforementioned multiplier. + int output_multiplier_exponent; +}; + +struct LogisticParams { + // uint8_t inference params. + int32_t input_zero_point; + int32_t input_range_radius; + int32_t input_multiplier; + int input_left_shift; +}; + +struct LstmCellParams { + int32_t weights_zero_point; + int32_t accum_multiplier; + int accum_shift; + int state_integer_bits; +}; + +struct MeanParams { + int8_t axis_count; + int16_t axis[4]; +}; + +struct PackParams { + int8_t axis; + const int32_t* input_zeropoint; + const float* input_scale; + uint16_t inputs_count; + int32_t output_zeropoint; + float output_scale; +}; + +struct PadParams { + int8_t left_padding_count; + int32_t left_padding[5]; + int8_t right_padding_count; + int32_t right_padding[5]; + ResizingCategory resizing_category; +}; + +struct PreluParams { + int32_t input_offset; + int32_t alpha_offset; + int32_t output_offset; + int32_t output_multiplier_1; + int output_shift_1; + int32_t output_multiplier_2; + int output_shift_2; +}; + +struct PoolParams { + FusedActivationFunctionType activation; + PaddingType padding_type; + PaddingValues padding_values; + int stride_height; + int stride_width; + int filter_height; + int filter_width; + // uint8_t, etc, activation params. + int32_t quantized_activation_min; + int32_t quantized_activation_max; + // float activation params. + float float_activation_min; + float float_activation_max; +}; + +struct ReshapeParams { + int8_t shape_count; + int32_t shape[4]; +}; + +struct ResizeBilinearParams { + bool align_corners; + // half_pixel_centers assumes pixels are of half the actual dimensions, and + // yields more accurate resizes. Corresponds to the same argument for the + // original TensorFlow op in TF2.0. + bool half_pixel_centers; +}; + +struct ResizeNearestNeighborParams { + bool align_corners; + bool half_pixel_centers; +}; + +struct SliceParams { + int8_t begin_count; + int32_t begin[5]; + int8_t size_count; + int32_t size[5]; +}; + +struct SoftmaxParams { + // beta is not really used (not a Tensorflow parameter) and not implemented + // for LogSoftmax. + double beta; + // uint8_t inference params. Used even when beta defaults to 1.0. + int32_t input_multiplier; + int32_t input_left_shift; + // Reverse scaling is only used by LogSoftmax. + int32_t reverse_scaling_divisor; + int32_t reverse_scaling_right_shift; + int diff_min; + int32_t zero_point; + float scale; + float* table; + // int16 LUT for exp(x), where x uniform distributed between [-10.0 , 0.0] + int16_t* exp_lut; + // int16 LUT for 1 / (1 + x), where x uniform distributed between [0.0 , 1.0] + int16_t* one_over_one_plus_x_lut; + uint8_t* uint8_table1; + uint8_t* uint8_table2; +}; + +struct SpaceToBatchParams { + // "Zero" padding for uint8_t means padding with the output offset. + int32_t output_offset; +}; + +struct SpaceToDepthParams { + int32_t block_size; +}; + +struct SplitParams { + // Graphs that split into, say, 2000 nodes are encountered. The indices in + // OperatorEdges are of type uint16_t. + uint16_t num_split; + int16_t axis; +}; + +struct SqueezeParams { + int8_t squeeze_dims_count; + int32_t squeeze_dims[4]; +}; + +struct StridedSliceParams { + int8_t start_indices_count; + int32_t start_indices[5]; + int8_t stop_indices_count; + int32_t stop_indices[5]; + int8_t strides_count; + int32_t strides[5]; + + uint16_t begin_mask; + uint16_t ellipsis_mask; + uint16_t end_mask; + uint16_t new_axis_mask; + uint16_t shrink_axis_mask; +}; + +struct TanhParams { + int32_t input_zero_point; + int32_t input_range_radius; + int32_t input_multiplier; + int input_left_shift; +}; + +constexpr int kTransposeMaxDimensions = 6; + +struct TransposeParams { + int8_t perm_count; + int32_t perm[kTransposeMaxDimensions]; +}; + +struct UnpackParams { + uint16_t num_split; + int16_t axis; +}; + +struct LeakyReluParams { + float alpha; + int32_t input_offset; + int32_t output_offset; + int32_t output_multiplier_alpha; + int32_t output_shift_alpha; + int32_t output_multiplier_identity; + int32_t output_shift_identity; +}; + +template +inline void SetActivationParams(float min, float max, P* params) { + params->float_activation_min = min; + params->float_activation_max = max; +} + +template +inline void SetActivationParams(int32_t min, int32_t max, P* params) { + params->quantized_activation_min = min; + params->quantized_activation_max = max; +} + +template +inline void SetActivationParams(int64_t min, int64_t max, P* params) { + params->int64_activation_min = min; + params->int64_activation_max = max; +} + +template +inline void GetActivationParams(const P& params, int32_t* min, int32_t* max) { + *min = params.quantized_activation_min; + *max = params.quantized_activation_max; +} + +template +inline void GetActivationParams(const P& params, float* min, float* max) { + *min = params.float_activation_min; + *max = params.float_activation_max; +} + +template +inline void GetActivationParams(const P& params, int64_t* min, int64_t* max) { + *min = params.int64_activation_min; + *max = params.int64_activation_max; +} + +// Type trait to check of given type has size smaller than 4 bytes. +template +struct is_small_integer + : public std::integral_constant::value || + std::is_same::value || + std::is_same::value || + std::is_same::value> {}; + +// Type trait to check of given type is int32 or int64. +template +struct is_int32_or_int64 + : public std::integral_constant::value || + std::is_same::value> { +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_INTERNAL_TYPES_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h new file mode 100644 index 0000000..5f33173 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h @@ -0,0 +1,335 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_KERNEL_UTIL_H_ +#define TENSORFLOW_LITE_KERNELS_KERNEL_UTIL_H_ + +#include + +#include +#ifndef TF_LITE_STATIC_MEMORY +#include +#endif // TF_LITE_STATIC_MEMORY + +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +namespace tflite { + +// A fair number of functions in this header have historically been inline. +// It is ok to change functions to not be inline if the latency with +// benchmark_model for MobileNet + MobileBERT is unaffected. If such a change is +// made, move the newly non-inlined function declarations to the top of this +// header file. + +// Note: You must check if result is not null: +// +// TfLiteTensor* my_tensor = GetInput(context, node, kMyTensorIdx); +// TF_LITE_ENSURE(context, my_tensor != nullptr); +// +// This is because the index might point to the optional tensor constant +// (kTfLiteOptionalTensor) in which case there is no tensor to return. +const TfLiteTensor* GetInput(const TfLiteContext* context, + const TfLiteNode* node, int index); + +// Same as `GetInput` but returns boolean and uses output argument for tensor. +// +// TfLiteTensor* my_tensor; +// TF_LITE_ENSURE_OK(context, +// GetInputSafe(context, node, kMyTensorIdx, &my_tensor)); +// // can use my_tensor directly from here onwards, it is not nullptr +// +// Should be used in cases where the binary size is too large. +TfLiteStatus GetInputSafe(const TfLiteContext* context, const TfLiteNode* node, + int index, const TfLiteTensor** tensor); + +// Note: You must check if result is not null: +// +// TfLiteTensor* my_tensor = GetVariableInput(context, node, kMyTensorIdx); +// TF_LITE_ENSURE(context, my_tensor != nullptr); +// +// This is because the index might point to the optional tensor constant +// (kTfLiteOptionalTensor) in which case there is no tensor to return. +TfLiteTensor* GetVariableInput(TfLiteContext* context, const TfLiteNode* node, + int index); + +// Note: You must check if result is not null: +// +// TfLiteTensor* my_tensor = GetOutput(context, node, kMyTensorIdx); +// TF_LITE_ENSURE(context, my_tensor != nullptr); +// +// This is because the index might point to the optional tensor constant +// (kTfLiteOptionalTensor) in which case there is no tensor to return. +TfLiteTensor* GetOutput(TfLiteContext* context, const TfLiteNode* node, + int index); + +// Same as `GetOutput` but returns boolean and uses output argument for tensor. +// +// TfLiteTensor* my_tensor; +// TF_LITE_ENSURE_OK(context, +// GetOutputSafe(context, node, kMyTensorIdx, &my_tensor)); +// // can use my_tensor directly from here onwards, it is not nullptr +// +// Should be used in cases where the binary size is too large. +TfLiteStatus GetOutputSafe(const TfLiteContext* context, const TfLiteNode* node, + int index, TfLiteTensor** tensor); + +// Note: You must check if result is not null: +// +// TfLiteTensor* my_tensor = GetOptionalInputTensor(context, node, kIdx); +// TF_LITE_ENSURE(context, my_tensor != nullptr); +// +// This is because the index might point to the optional tensor constant +// (kTfLiteOptionalTensor) in which case there is no tensor to return. +// +// Deprecated. GetInput has the same functionality. +const TfLiteTensor* GetOptionalInputTensor(const TfLiteContext* context, + const TfLiteNode* node, int index); + +#ifndef TF_LITE_STATIC_MEMORY +// Note: You must check if result is not null: +// +// TfLiteTensor* my_tensor = GetTemporary(context, node, kMyTensorIdx); +// TF_LITE_ENSURE(context, my_tensor != nullptr); +// +// This is because the index might point to the optional tensor constant +// (kTfLiteOptionalTensor) in which case there is no tensor to return. +TfLiteTensor* GetTemporary(TfLiteContext* context, const TfLiteNode* node, + int index); + +// Same as `GetTemporary` but returns boolean and uses output argument for +// tensor. +// +// TfLiteTensor* my_tensor; +// TF_LITE_ENSURE_OK(context, +// GetTemporarySafe(context, node, kMyTensorIdx, +// &my_tensor)); +// // can use my_tensor directly from here onwards, it is not nullptr +// +// Should be used in cases where the binary size is too large. +TfLiteStatus GetTemporarySafe(const TfLiteContext* context, + const TfLiteNode* node, int index, + TfLiteTensor** tensor); + +// Note: You must check if result is not null: +// +// TfLiteTensor* my_tensor = GetIntermediates(context, node, kMyTensorIdx); +// TF_LITE_ENSURE(context, my_tensor != nullptr); +// +// This is because the index might point to the optional tensor constant +// (kTfLiteOptionalTensor) in which case there is no tensor to return. +const TfLiteTensor* GetIntermediates(TfLiteContext* context, + const TfLiteNode* node, int index); + +// Same as `GetIntermediates` but returns boolean and uses output argument for +// tensor. +// +// TfLiteTensor* my_tensor; +// TF_LITE_ENSURE_OK(context, +// GetIntermediatesSafe(context, node, kMyTensorIdx, +// &my_tensor)); +// // can use my_tensor directly from here onwards, it is not nullptr +// +// Should be used in cases where the binary size is too large. +TfLiteStatus GetIntermediatesSafe(const TfLiteContext* context, + const TfLiteNode* node, int index, + TfLiteTensor** tensor); +#endif // TF_LITE_STATIC_MEMORY + +inline int NumDimensions(const TfLiteTensor* t) { return t->dims->size; } +inline int SizeOfDimension(const TfLiteTensor* t, int dim) { + return t->dims->data[dim]; +} + +inline int NumDimensions(const TfLiteEvalTensor* t) { return t->dims->size; } +inline int SizeOfDimension(const TfLiteEvalTensor* t, int dim) { + return t->dims->data[dim]; +} + +inline int NumInputs(const TfLiteNode* node) { + return node->inputs == nullptr ? 0 : node->inputs->size; +} +inline int NumOutputs(const TfLiteNode* node) { + return node->outputs == nullptr ? 0 : node->outputs->size; +} + +#ifndef TF_LITE_STATIC_MEMORY +inline int NumIntermediates(const TfLiteNode* node) { + return node->intermediates->size; +} +#endif // TF_LITE_STATIC_MEMORY + +inline int64_t NumElements(const TfLiteIntArray* dims) { + int64_t count = 1; + for (int i = 0; i < dims->size; ++i) { + count *= dims->data[i]; + } + return count; +} + +inline int64_t NumElements(const TfLiteTensor* t) { + return NumElements(t->dims); +} + +inline int64_t NumElements(const int* dims, int num_dims) { + int64_t count = 1; + for (int i = 0; i < num_dims; ++i) { + count *= dims[i]; + } + return count; +} + +// Determines whether tensor is constant. +// TODO(b/138199592): Introduce new query which checks for constant OR +// persistent-read-only, which would be useful for most tensor kernels that +// are potentially dynamic based on the input tensor value availability at the +// time of prepare. +inline bool IsConstantTensor(const TfLiteTensor* tensor) { + return tensor->allocation_type == kTfLiteMmapRo; +} + +inline bool IsConstantOrPersistentTensor(const TfLiteTensor* tensor) { + return IsConstantTensor(tensor) || + (tensor->allocation_type == kTfLitePersistentRo); +} + +// Determines whether tensor is dynamic. Note that a tensor can be non-const and +// not dynamic. This function specifically checks for a dynamic tensor. +inline bool IsDynamicTensor(const TfLiteTensor* tensor) { + return tensor->allocation_type == kTfLiteDynamic; +} + +// Sets tensor to dynamic. +inline void SetTensorToDynamic(TfLiteTensor* tensor) { + if (tensor->allocation_type != kTfLiteDynamic) { + tensor->allocation_type = kTfLiteDynamic; + tensor->data.raw = nullptr; + } +} + +// Sets tensor to persistent and read-only. +inline void SetTensorToPersistentRo(TfLiteTensor* tensor) { + if (tensor->allocation_type != kTfLitePersistentRo) { + tensor->allocation_type = kTfLitePersistentRo; + tensor->data.raw = nullptr; + } +} + +// Determines whether it is a hybrid op - one that has float inputs and +// quantized weights. +inline bool IsHybridOp(const TfLiteTensor* input, const TfLiteTensor* weight) { + return ((weight->type == kTfLiteUInt8 || weight->type == kTfLiteInt8) && + input->type == kTfLiteFloat32); +} + +// Check dimensionality match and populate OpData for Conv and DepthwiseConv. +TfLiteStatus PopulateConvolutionQuantizationParams( + TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* filter, const TfLiteTensor* bias, TfLiteTensor* output, + const TfLiteFusedActivation& activation, int32_t* multiplier, int* shift, + int32_t* output_activation_min, int32_t* output_activation_max, + int32_t* per_channel_multiplier, int32_t* per_channel_shift); + +TfLiteStatus PopulateConvolutionQuantizationParams( + TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* filter, const TfLiteTensor* bias, TfLiteTensor* output, + const TfLiteFusedActivation& activation, int32_t* multiplier, int* shift, + int32_t* output_activation_min, int32_t* output_activation_max, + int32_t* per_channel_multiplier, int32_t* per_channel_shift, + int num_channels); + +// Calculates the multiplication factor for a quantized convolution (or +// quantized depthwise convolution) involving the given tensors. Returns an +// error if the scales of the tensors are not compatible. +TfLiteStatus GetQuantizedConvolutionMultipler(TfLiteContext* context, + const TfLiteTensor* input, + const TfLiteTensor* filter, + const TfLiteTensor* bias, + TfLiteTensor* output, + double* multiplier); + +TfLiteStatus GetQuantizedConvolutionMultipler(TfLiteContext* context, + const TfLiteTensor* input, + const TfLiteTensor* filter, + TfLiteTensor* output, + double* multiplier); + +// Calculates the useful quantized range of an activation layer given its +// activation tensor. +TfLiteStatus CalculateActivationRangeQuantized(TfLiteContext* context, + TfLiteFusedActivation activation, + TfLiteTensor* output, + int32_t* act_min, + int32_t* act_max); + +// Calculates the useful range of an activation layer given its activation +// tensor.a +template +void CalculateActivationRange(TfLiteFusedActivation activation, + T* activation_min, T* activation_max) { + if (activation == kTfLiteActRelu) { + *activation_min = 0; + *activation_max = std::numeric_limits::max(); + } else if (activation == kTfLiteActRelu6) { + *activation_min = 0; + *activation_max = 6; + } else if (activation == kTfLiteActReluN1To1) { + *activation_min = -1; + *activation_max = 1; + } else { + *activation_min = std::numeric_limits::lowest(); + *activation_max = std::numeric_limits::max(); + } +} + +// Return true if the given tensors have the same shape. +bool HaveSameShapes(const TfLiteTensor* input1, const TfLiteTensor* input2); + +#if !defined(TF_LITE_STATIC_MEMORY) +// Gets the output shape from the input tensor. +TfLiteStatus GetOutputShapeFromInput(TfLiteContext* context, + const TfLiteTensor* input, + TfLiteIntArray** output_shape); + +const std::string GetShapeDebugString(const TfLiteIntArray* shape); + +#endif // !defined(TF_LITE_STATIC_MEMORY) + +// Calculates the output_shape that is necessary for element-wise operations +// with broadcasting involving the two input tensors. +TfLiteStatus CalculateShapeForBroadcast(TfLiteContext* context, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteIntArray** output_shape); + +// Calculates the output_shape that is necessary for element-wise operations +// with broadcasting involving the three input tensors. +TfLiteStatus CalculateShapeForBroadcast(TfLiteContext* context, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + const TfLiteTensor* input3, + TfLiteIntArray** output_shape); + +// Return the size of given type in bytes. Return 0 in case of string. +int TfLiteTypeGetSize(TfLiteType type); + +// Whether the current platform is mobile (Android or iOS). +bool IsMobilePlatform(); + +// Returns whether there is unspecified dimension in the tensor's dim signature. +bool HasUnspecifiedDimension(const TfLiteTensor* tensor); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_KERNEL_UTIL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/kernel_util_lite.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/kernel_util_lite.cpp new file mode 100644 index 0000000..a786b68 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/kernel_util_lite.cpp @@ -0,0 +1,594 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" + +#include +#include + +#include +#include +#include +#include +#ifndef TF_LITE_STATIC_MEMORY +#include +#endif // TF_LITE_STATIC_MEMORY + +#include "edge-impulse-sdk/tensorflow/lite/context_util.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" + +#if defined(__APPLE__) +#include "TargetConditionals.h" +#endif + +namespace tflite { + +namespace { + +// Assumes tensor_index is a valid index (in bounds) +inline TfLiteTensor* GetTensorAtIndex(const TfLiteContext* context, + int tensor_index) { + return context->GetTensor(context, tensor_index); +} + +// Validate in a single place to reduce binary size +inline TfLiteStatus ValidateTensorIndexingSafe(const TfLiteContext* context, + int index, int max_size, + const int* tensor_indices, + int* tensor_index) { + if (index < 0 || index >= max_size) { + TF_LITE_KERNEL_LOG(const_cast(context), + "Invalid tensor index %d (not in [0, %d))\n", index, + max_size); + return kTfLiteError; + } + if (tensor_indices[index] == kTfLiteOptionalTensor) { + TF_LITE_KERNEL_LOG(const_cast(context), + "Tensor at index %d was optional but was expected\n", + index); + return kTfLiteError; + } + + *tensor_index = tensor_indices[index]; + return kTfLiteOk; +} + +// Same as above but returns -1 for invalid inputs instead of status + logging +// error. +inline int ValidateTensorIndexing(const TfLiteContext* context, int index, + int max_size, const int* tensor_indices) { + if (index >= 0 && index < max_size) { + const int tensor_index = tensor_indices[index]; + if (tensor_index != kTfLiteOptionalTensor) { + return tensor_index; + } + } + return -1; +} + +inline TfLiteTensor* GetMutableInput(const TfLiteContext* context, + const TfLiteNode* node, int index) { + const int tensor_index = ValidateTensorIndexing( + context, index, node->inputs->size, node->inputs->data); + if (tensor_index < 0) { + return nullptr; + } + return GetTensorAtIndex(context, tensor_index); +} + +inline TfLiteStatus GetMutableInputSafe(const TfLiteContext* context, + const TfLiteNode* node, int index, + const TfLiteTensor** tensor) { + int tensor_index; + TF_LITE_ENSURE_OK( + context, ValidateTensorIndexingSafe(context, index, node->inputs->size, + node->inputs->data, &tensor_index)); + *tensor = GetTensorAtIndex(context, tensor_index); + return kTfLiteOk; +} + +} // anonymous namespace. + +const TfLiteTensor* GetInput(const TfLiteContext* context, + const TfLiteNode* node, int index) { + return GetMutableInput(context, node, index); +} + +TfLiteStatus GetInputSafe(const TfLiteContext* context, const TfLiteNode* node, + int index, const TfLiteTensor** tensor) { + return GetMutableInputSafe(context, node, index, tensor); +} + +TfLiteTensor* GetVariableInput(TfLiteContext* context, const TfLiteNode* node, + int index) { + TfLiteTensor* tensor = GetMutableInput(context, node, index); + if (tensor == nullptr) return nullptr; + return tensor->is_variable ? tensor : nullptr; +} + +TfLiteTensor* GetOutput(TfLiteContext* context, const TfLiteNode* node, + int index) { + const int tensor_index = ValidateTensorIndexing( + context, index, node->outputs->size, node->outputs->data); + if (tensor_index < 0) { + return nullptr; + } + return GetTensorAtIndex(context, tensor_index); +} + +TfLiteStatus GetOutputSafe(const TfLiteContext* context, const TfLiteNode* node, + int index, TfLiteTensor** tensor) { + int tensor_index; + TF_LITE_ENSURE_OK( + context, ValidateTensorIndexingSafe(context, index, node->outputs->size, + node->outputs->data, &tensor_index)); + *tensor = GetTensorAtIndex(context, tensor_index); + return kTfLiteOk; +} + +const TfLiteTensor* GetOptionalInputTensor(const TfLiteContext* context, + const TfLiteNode* node, int index) { + return GetInput(context, node, index); +} + +#ifndef TF_LITE_STATIC_MEMORY +TfLiteTensor* GetTemporary(TfLiteContext* context, const TfLiteNode* node, + int index) { + const int tensor_index = ValidateTensorIndexing( + context, index, node->temporaries->size, node->temporaries->data); + if (tensor_index < 0) { + return nullptr; + } + return GetTensorAtIndex(context, tensor_index); +} + +TfLiteStatus GetTemporarySafe(const TfLiteContext* context, + const TfLiteNode* node, int index, + TfLiteTensor** tensor) { + int tensor_index; + TF_LITE_ENSURE_OK(context, ValidateTensorIndexingSafe( + context, index, node->temporaries->size, + node->temporaries->data, &tensor_index)); + *tensor = GetTensorAtIndex(context, tensor_index); + return kTfLiteOk; +} + +const TfLiteTensor* GetIntermediates(TfLiteContext* context, + const TfLiteNode* node, int index) { + const int tensor_index = ValidateTensorIndexing( + context, index, node->intermediates->size, node->intermediates->data); + if (tensor_index < 0) { + return nullptr; + } + return GetTensorAtIndex(context, tensor_index); +} + +TfLiteStatus GetIntermediatesSafe(const TfLiteContext* context, + const TfLiteNode* node, int index, + TfLiteTensor** tensor) { + int tensor_index; + TF_LITE_ENSURE_OK(context, ValidateTensorIndexingSafe( + context, index, node->intermediates->size, + node->intermediates->data, &tensor_index)); + *tensor = GetTensorAtIndex(context, tensor_index); + return kTfLiteOk; +} +#endif // TF_LITE_STATIC_MEMORY + +// Per-axis +TfLiteStatus PopulateConvolutionQuantizationParams( + TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* filter, const TfLiteTensor* bias, TfLiteTensor* output, + const TfLiteFusedActivation& activation, int32_t* multiplier, int* shift, + int32_t* output_activation_min, int32_t* output_activation_max, + int32_t* per_channel_multiplier, int32_t* per_channel_shift) { + const auto* affine_quantization = + reinterpret_cast(filter->quantization.params); + return PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, activation, multiplier, shift, + output_activation_min, output_activation_max, per_channel_multiplier, + per_channel_shift, affine_quantization->scale->size); +} + +// Per-axis & per-tensor +TfLiteStatus PopulateConvolutionQuantizationParams( + TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* filter, const TfLiteTensor* bias, TfLiteTensor* output, + const TfLiteFusedActivation& activation, int32_t* multiplier, int* shift, + int32_t* output_activation_min, int32_t* output_activation_max, + int32_t* per_channel_multiplier, int32_t* per_channel_shift, + int num_channels) { + TF_LITE_ENSURE_EQ(context, input->quantization.type, + kTfLiteAffineQuantization); + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + // TODO(jianlijianli): Enable bias type check and bias scale == input scale + // * filter scale for each channel in affine quantization once bias + // quantization is properly populated. + // TF_LITE_ENSURE_EQ(context, bias->quantization.type, + // kTfLiteAffineQuantization); + + // Check data type. + const auto* affine_quantization = + reinterpret_cast(filter->quantization.params); + TF_LITE_ENSURE(context, affine_quantization); + TF_LITE_ENSURE(context, affine_quantization->scale); + const bool is_per_channel = affine_quantization->scale->size > 1; + if (is_per_channel) { + // Currently only Int8/Int16 is supported for per channel quantization. + TF_LITE_ENSURE(context, + input->type == kTfLiteInt8 || input->type == kTfLiteInt16); + TF_LITE_ENSURE(context, + filter->type == kTfLiteInt8 || filter->type == kTfLiteInt4); + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, num_channels); + TF_LITE_ENSURE_EQ( + context, num_channels, + filter->dims->data[affine_quantization->quantized_dimension]); + } + + // Populate multiplier and shift using affine quantization. + const float input_scale = input->params.scale; + const float output_scale = output->params.scale; + const float* filter_scales = affine_quantization->scale->data; + for (int i = 0; i < num_channels; ++i) { + // If per-tensor quantization parameter is specified, broadcast it along the + // quantization dimension (channels_out). + const float scale = is_per_channel ? filter_scales[i] : filter_scales[0]; + const double filter_scale = static_cast(scale); + const double effective_output_scale = static_cast(input_scale) * + filter_scale / + static_cast(output_scale); + int32_t significand; + int channel_shift; + QuantizeMultiplier(effective_output_scale, &significand, &channel_shift); + per_channel_multiplier[i] = significand; + per_channel_shift[i] = channel_shift; + } + + // Populate scalar quantization parameters. + // This check on legacy quantization parameters is kept only for backward + // compatibility. + if (input->type == kTfLiteUInt8) { + // Check bias scale == input scale * filter scale. + double real_multiplier = 0.0; + TF_LITE_ENSURE_STATUS(GetQuantizedConvolutionMultipler( + context, input, filter, bias, output, &real_multiplier)); + int exponent; + + // Populate quantization parameters with multiplier and shift. + QuantizeMultiplier(real_multiplier, multiplier, &exponent); + *shift = -exponent; + } + if (input->type == kTfLiteInt8 || input->type == kTfLiteUInt8 || + input->type == kTfLiteInt16) { + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, activation, output, output_activation_min, + output_activation_max)); + } + return kTfLiteOk; +} + +TfLiteStatus GetQuantizedConvolutionMultipler(TfLiteContext* context, + const TfLiteTensor* input, + const TfLiteTensor* filter, + const TfLiteTensor* bias, + TfLiteTensor* output, + double* multiplier) { + const double input_product_scale = static_cast(input->params.scale) * + static_cast(filter->params.scale); + // The following conditions must be guaranteed by the training pipeline. + if (bias) { + const double bias_scale = static_cast(bias->params.scale); + // Here we're making sure the input_product_scale & bias_scale are about the + // same. Since we have: + // (output - output_zp) * output_scale = + // input_product_scale * input_product + bias * bias_scale ---- (0) + // + // (0) equals: + // (input_product + bias) * input_product_scale ----- (1) + // + + // bias * (bias_scale - input_product_scale) ------ (2) + // + // For the real kernel computation, we're doing (1), so we really need to + // make sure (2) has minimum impact on the output, so: + // bias * (bias_scale - input_product_scale) / output_scale should be + // a small number for an integer. + // Since normally bias should be within a small range. + // We should expect (bias_scale - input_product_scale) / output_scale to + // be a small number like 0.02. + const double scale_diff = std::abs(input_product_scale - bias_scale); + const double output_scale = static_cast(output->params.scale); + + TF_LITE_ENSURE(context, scale_diff / output_scale <= 0.02); + } + return GetQuantizedConvolutionMultipler(context, input, filter, output, + multiplier); +} + +TfLiteStatus GetQuantizedConvolutionMultipler(TfLiteContext* context, + const TfLiteTensor* input, + const TfLiteTensor* filter, + TfLiteTensor* output, + double* multiplier) { + const double input_product_scale = + static_cast(input->params.scale * filter->params.scale); + TF_LITE_ENSURE(context, input_product_scale >= 0); + *multiplier = input_product_scale / static_cast(output->params.scale); + + return kTfLiteOk; +} + +namespace { + +inline TfLiteStatus Quantize(TfLiteContext* context, float scale, + int32_t zero_point, float f, int32_t& q) { + const float tmp = TfLiteRound(f / scale); + const bool no_integer_overflow_from_quantization = + (tmp >= static_cast(std::numeric_limits::min()) && + tmp <= static_cast(std::numeric_limits::max())); + TF_LITE_ENSURE(context, no_integer_overflow_from_quantization); + q = zero_point + static_cast(tmp); + return kTfLiteOk; +} + +TfLiteStatus CalculateActivationRangeQuantizedImpl( + TfLiteContext* context, TfLiteFusedActivation activation, int32_t qmin, + int32_t qmax, TfLiteTensor* output, int32_t* act_min, int32_t* act_max) { + const auto scale = output->params.scale; + const auto zero_point = output->params.zero_point; + + int32_t tmp_q; + if (activation == kTfLiteActRelu) { + TF_LITE_ENSURE_OK(context, + Quantize(context, scale, zero_point, 0.0, tmp_q)); + *act_min = std::max(qmin, tmp_q); + *act_max = qmax; + } else if (activation == kTfLiteActRelu6) { + TF_LITE_ENSURE_OK(context, + Quantize(context, scale, zero_point, 0.0, tmp_q)); + *act_min = std::max(qmin, tmp_q); + TF_LITE_ENSURE_OK(context, + Quantize(context, scale, zero_point, 6.0, tmp_q)); + *act_max = std::min(qmax, tmp_q); + } else if (activation == kTfLiteActReluN1To1) { + TF_LITE_ENSURE_OK(context, + Quantize(context, scale, zero_point, -1.0, tmp_q)); + *act_min = std::max(qmin, tmp_q); + TF_LITE_ENSURE_OK(context, + Quantize(context, scale, zero_point, 1.0, tmp_q)); + *act_max = std::min(qmax, tmp_q); + } else { + *act_min = qmin; + *act_max = qmax; + } + return kTfLiteOk; +} +} // namespace + +TfLiteStatus CalculateActivationRangeQuantized(TfLiteContext* context, + TfLiteFusedActivation activation, + TfLiteTensor* output, + int32_t* act_min, + int32_t* act_max) { + int32_t qmin = 0; + int32_t qmax = 0; + if (output->type == kTfLiteUInt8) { + qmin = std::numeric_limits::min(); + qmax = std::numeric_limits::max(); + } else if (output->type == kTfLiteInt8) { + qmin = std::numeric_limits::min(); + qmax = std::numeric_limits::max(); + } else if (output->type == kTfLiteInt16) { + qmin = std::numeric_limits::min(); + qmax = std::numeric_limits::max(); + } else { + TF_LITE_ENSURE(context, false); + } + + return CalculateActivationRangeQuantizedImpl(context, activation, qmin, qmax, + output, act_min, act_max); +} + +bool HaveSameShapes(const TfLiteTensor* input1, const TfLiteTensor* input2) { + return TfLiteIntArrayEqual(input1->dims, input2->dims); +} + +#ifndef TF_LITE_STATIC_MEMORY +TfLiteStatus GetOutputShapeFromInput(TfLiteContext* context, + const TfLiteTensor* input, + TfLiteIntArray** output_shape) { + if (NumDimensions(input) != 1) { + TF_LITE_KERNEL_LOG(const_cast(context), + "Invalid %dD input tensor (must be a 1D tensor).", + NumDimensions(input)); + return kTfLiteError; + } + const int output_dims = SizeOfDimension(input, 0); + std::unique_ptr shape( + TfLiteIntArrayCreate(output_dims), TfLiteIntArrayFree); + for (int i = 0; i < output_dims; i++) { + shape->data[i] = input->data.i32[i]; + } + *output_shape = shape.release(); + return kTfLiteOk; +} + +// TODO(b/172067338): Having this function be part of TF_LITE_STATIC_MEMORY +// build results in a 6KB size increase, even though the function is unsused for +// that build. What appears to be happening is that while the linker drops the +// unsused function, the string library that gets pulled in is not dropped, +// resulting in the increased binary size. +// Patched by Edge Impulse, issues with building for TinkerGen +// TODO inspect if we still need this +const std::string GetShapeDebugString(const TfLiteIntArray* shape) { + std::string str = "GetShapeDebugString";; + /* + for (int d = 0; d < shape->size; ++d) { + if (str.empty()) + str = "[" + std::to_string(shape->data[d]); + else + // Don't add space after "," to make the output consistent with + // tensorflow::shape_inference::InferenceContext::DebugString() + str += "," + std::to_string(shape->data[d]); + } + if (str.empty()) { + str = "[]"; + } else { + str += "]"; + } + */ + return str; +} + +TfLiteStatus CalculateShapeForBroadcast(TfLiteContext* context, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteIntArray** output_shape) { + const int dims1 = NumDimensions(input1); + const int dims2 = NumDimensions(input2); + const int out_dims = std::max(dims1, dims2); + + std::unique_ptr shape( + TfLiteIntArrayCreate(out_dims), TfLiteIntArrayFree); + for (int i = 0; i < out_dims; ++i) { + const int d1 = i >= dims1 ? 1 : SizeOfDimension(input1, dims1 - i - 1); + const int d2 = i >= dims2 ? 1 : SizeOfDimension(input2, dims2 - i - 1); + if (!(d1 == d2 || d1 == 1 || d2 == 1)) { + TF_LITE_KERNEL_LOG(context, + "Given shapes, %s and %s, are not broadcastable.", + GetShapeDebugString(input1->dims).c_str(), + GetShapeDebugString(input2->dims).c_str()); + return kTfLiteError; + } + + if (d1 == 0 || d2 == 0) { + shape->data[out_dims - i - 1] = 0; + } else { + shape->data[out_dims - i - 1] = std::max(d1, d2); + } + } + *output_shape = shape.release(); + return kTfLiteOk; +} + +TfLiteStatus CalculateShapeForBroadcast(TfLiteContext* context, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + const TfLiteTensor* input3, + TfLiteIntArray** output_shape) { + const int dims1 = NumDimensions(input1); + const int dims2 = NumDimensions(input2); + const int dims3 = NumDimensions(input3); + const int out_dims = std::max(std::max(dims1, dims2), dims3); + std::unique_ptr shape( + TfLiteIntArrayCreate(out_dims), TfLiteIntArrayFree); + for (int i = 0; i < out_dims; ++i) { + const int d1 = i >= dims1 ? 1 : SizeOfDimension(input1, dims1 - i - 1); + const int d2 = i >= dims2 ? 1 : SizeOfDimension(input2, dims2 - i - 1); + const int d3 = i >= dims3 ? 1 : SizeOfDimension(input3, dims3 - i - 1); + const int min_value = std::min(std::min(d1, d2), d3); + int max_value = std::max(std::max(d1, d2), d3); + // If one dimention is 0, others must be 0 or 1. + if (min_value == 0) max_value = 0; + if (!(d1 == 1 || d1 == max_value) || !(d2 == 1 || d2 == max_value) || + !(d3 == 1 || d3 == max_value)) { + TF_LITE_KERNEL_LOG(context, + "Given shapes, %s, %s and %s, are not broadcastable.", + GetShapeDebugString(input1->dims).c_str(), + GetShapeDebugString(input2->dims).c_str(), + GetShapeDebugString(input3->dims).c_str()); + return kTfLiteError; + } + shape->data[out_dims - i - 1] = max_value; + } + *output_shape = shape.release(); + return kTfLiteOk; +} +#endif // TF_LITE_STATIC_MEMORY + +// Size of string is not constant, return 0 in such case. +int TfLiteTypeGetSize(TfLiteType type) { + switch (type) { + case kTfLiteUInt8: + static_assert(sizeof(uint8_t) == 1, ""); + return 1; + case kTfLiteInt8: + static_assert(sizeof(int8_t) == 1, ""); + return 1; + case kTfLiteBool: + return sizeof(bool); + case kTfLiteUInt16: + static_assert(sizeof(uint16_t) == 2, ""); + return 2; + case kTfLiteInt16: + static_assert(sizeof(int16_t) == 2, ""); + return 2; + case kTfLiteFloat16: + static_assert(sizeof(int16_t) == 2, ""); + return 2; + case kTfLiteFloat32: + static_assert(sizeof(float) == 4, ""); + return 4; + case kTfLiteInt32: + static_assert(sizeof(int32_t) == 4, ""); + return 4; + case kTfLiteUInt32: + static_assert(sizeof(uint32_t) == 4, ""); + return 4; + case kTfLiteInt64: + static_assert(sizeof(int64_t) == 8, ""); + return 8; + case kTfLiteUInt64: + static_assert(sizeof(uint64_t) == 8, ""); + return 8; + case kTfLiteFloat64: + static_assert(sizeof(double) == 8, ""); + return 8; + case kTfLiteComplex64: + static_assert(sizeof(std::complex) == 8, ""); + return 8; + case kTfLiteComplex128: + static_assert(sizeof(std::complex) == 16, ""); + return 16; + default: + return 0; + } +} + +bool IsMobilePlatform() { +#if defined(ANDROID) || defined(__ANDROID__) + return true; +#elif defined(__APPLE__) +#if TARGET_IPHONE_SIMULATOR || TARGET_OS_IPHONE + return true; +#endif +#endif + return false; +} + +bool HasUnspecifiedDimension(const TfLiteTensor* tensor) { +#ifndef TF_LITE_STATIC_MEMORY + if (tensor->dims_signature) { + for (int i : TfLiteIntArrayView(tensor->dims_signature)) { + if (i == -1) return true; + } + } +#endif // TF_LITE_STATIC_MEMORY + return false; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h new file mode 100644 index 0000000..d3c50bb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h @@ -0,0 +1,38 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_OP_MACROS_H_ +#define TENSORFLOW_LITE_KERNELS_OP_MACROS_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" + +#if !defined(TF_LITE_MCU_DEBUG_LOG) +#include +#define TFLITE_ABORT abort() +#else +inline void AbortImpl() { + DebugLog("HALTED\n"); + while (1) { + } +} +#define TFLITE_ABORT AbortImpl(); +#endif + +#if defined(NDEBUG) +#define TFLITE_ASSERT_FALSE (static_cast(0)) +#else +#define TFLITE_ASSERT_FALSE TFLITE_ABORT +#endif + +#endif // TENSORFLOW_LITE_KERNELS_OP_MACROS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/padding.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/padding.h new file mode 100644 index 0000000..836ca92 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/kernels/padding.h @@ -0,0 +1,115 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_KERNELS_PADDING_H_ +#define TENSORFLOW_LITE_KERNELS_PADDING_H_ + +#include "edge-impulse-sdk/tensorflow/lite/core/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +inline int ComputePadding(int stride, int dilation_rate, int in_size, + int filter_size, int out_size) { + int effective_filter_size = (filter_size - 1) * dilation_rate + 1; + int padding = ((out_size - 1) * stride + effective_filter_size - in_size) / 2; + return padding > 0 ? padding : 0; +} + +// It's not guaranteed that padding is symmetric. It's important to keep +// offset for algorithms need all paddings. +inline int ComputePaddingWithOffset(int stride, int dilation_rate, int in_size, + int filter_size, int out_size, + int* offset) { + int effective_filter_size = (filter_size - 1) * dilation_rate + 1; + int total_padding = + ((out_size - 1) * stride + effective_filter_size - in_size); + total_padding = total_padding > 0 ? total_padding : 0; + *offset = total_padding % 2; + return total_padding / 2; +} + +// Matching GetWindowedOutputSize in TensorFlow. +inline int ComputeOutSize(TfLitePadding padding, int image_size, + int filter_size, int stride, int dilation_rate = 1) { + int effective_filter_size = (filter_size - 1) * dilation_rate + 1; + + // TODO(b/186448822): This uses 0 since the function has no other way to + // report error case + if (stride == 0) return 0; + + switch (padding) { + case kTfLitePaddingSame: + return (image_size + stride - 1) / stride; + case kTfLitePaddingValid: + return (image_size + stride - effective_filter_size) / stride; + default: + return 0; + } +} + +inline TfLitePaddingValues ComputePaddingHeightWidth( + int stride_height, int stride_width, int dilation_rate_height, + int dilation_rate_width, int in_height, int in_width, int filter_height, + int filter_width, TfLitePadding padding, int* out_height, int* out_width) { + *out_width = ComputeOutSize(padding, in_width, filter_width, stride_width, + dilation_rate_width); + *out_height = ComputeOutSize(padding, in_height, filter_height, stride_height, + dilation_rate_height); + + TfLitePaddingValues padding_values; + int offset = 0; + padding_values.height = + ComputePaddingWithOffset(stride_height, dilation_rate_height, in_height, + filter_height, *out_height, &offset); + padding_values.height_offset = offset; + padding_values.width = + ComputePaddingWithOffset(stride_width, dilation_rate_width, in_width, + filter_width, *out_width, &offset); + padding_values.width_offset = offset; + return padding_values; +} + +inline Padding3DValues ComputePadding3DValues( + int stride_height, int stride_width, int stride_depth, + int dilation_rate_height, int dilation_rate_width, int dilation_rate_depth, + int in_height, int in_width, int in_depth, int filter_height, + int filter_width, int filter_depth, TfLitePadding padding, int* out_height, + int* out_width, int* out_depth) { + *out_width = ComputeOutSize(padding, in_width, filter_width, stride_width, + dilation_rate_width); + *out_height = ComputeOutSize(padding, in_height, filter_height, stride_height, + dilation_rate_height); + *out_depth = ComputeOutSize(padding, in_depth, filter_depth, stride_depth, + dilation_rate_depth); + + Padding3DValues padding_values; + int offset = 0; + padding_values.depth = + ComputePaddingWithOffset(stride_depth, dilation_rate_depth, in_depth, + filter_depth, *out_depth, &offset); + padding_values.depth_offset = offset; + padding_values.height = + ComputePaddingWithOffset(stride_height, dilation_rate_height, in_height, + filter_height, *out_height, &offset); + padding_values.height_offset = offset; + padding_values.width = + ComputePaddingWithOffset(stride_width, dilation_rate_width, in_width, + filter_width, *out_width, &offset); + padding_values.width_offset = offset; + return padding_values; +} +} // namespace tflite + +#endif // TENSORFLOW_LITE_KERNELS_PADDING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.cpp new file mode 100644 index 0000000..e9d2d6f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.cpp @@ -0,0 +1,135 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h" + +namespace tflite { + +AllOpsResolver::AllOpsResolver() { + // Please keep this list of Builtin Operators in alphabetical order. + AddAbs(); + AddAdd(); + AddAddN(); + AddArgMax(); + AddArgMin(); + AddAssignVariable(); + AddAveragePool2D(); + AddBatchMatMul(); + AddBatchToSpaceNd(); + AddBroadcastArgs(); + AddBroadcastTo(); + AddCallOnce(); + AddCast(); + AddCeil(); + AddComplexAbs(); + AddCircularBuffer(); + AddConcatenation(); + AddConv2D(); + AddCos(); + AddCumSum(); + AddDepthToSpace(); + AddDepthwiseConv2D(); + AddDequantize(); + AddDetectionPostprocess(); + AddDiv(); + AddElu(); + AddEqual(); + AddEthosU(); + AddExp(); + AddExpandDims(); + AddFill(); + AddFloor(); + AddFloorDiv(); + AddFloorMod(); + AddFullyConnected(); +#ifndef TF_LITE_STATIC_MEMORY + AddGather(); +#endif // TF_LITE_STATIC_MEMORY + AddGatherNd(); + AddGreater(); + AddGreaterEqual(); + AddHardSwish(); + AddImag(); + AddIf(); + AddL2Normalization(); + AddL2Pool2D(); + AddLeakyRelu(); + AddLess(); + AddLessEqual(); + AddLog(); + AddLogicalAnd(); + AddLogicalNot(); + AddLogicalOr(); + AddLogistic(); + AddLogSoftmax(); + AddMaxPool2D(); + AddMaximum(); + AddMean(); + AddMinimum(); + AddMirrorPad(); + AddMul(); + AddNeg(); + AddNotEqual(); + AddPack(); + AddPad(); + AddPadV2(); + AddPrelu(); + AddQuantize(); + AddReal(); + AddReadVariable(); + AddReduceMax(); + AddReduceMin(); + AddRelu(); + AddRelu6(); + AddReshape(); + AddResizeBilinear(); + AddResizeNearestNeighbor(); + AddRfft2D(); + AddRound(); + AddRsqrt(); +#ifndef TF_LITE_STATIC_MEMORY + AddSelect(); + AddSelectV2(); +#endif // TF_LITE_STATIC_MEMORY + AddShape(); + AddSin(); + AddSlice(); + AddSoftmax(); + AddSpaceToBatchNd(); + AddSpaceToDepth(); + AddSplit(); + AddSplitV(); + AddSqrt(); + AddSquare(); + AddSquaredDifference(); + AddSqueeze(); + AddStridedSlice(); + AddSub(); + AddSum(); + AddSvdf(); + AddTanh(); + AddTranspose(); + AddTransposeConv(); + AddTreeEnsembleClassifier(); + AddUnidirectionalSequenceLstm(); + AddUnpack(); + AddVarHandle(); + AddWhile(); + AddZerosLike(); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h new file mode 100644 index 0000000..8d468ef --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h @@ -0,0 +1,38 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_ALL_OPS_RESOLVER_H_ +#define TENSORFLOW_LITE_MICRO_ALL_OPS_RESOLVER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_mutable_op_resolver.h" + +namespace tflite { + +// The magic number in the template parameter is the maximum number of ops that +// can be added to AllOpsResolver. It can be increased if needed. And most +// applications that care about the memory footprint will want to directly use +// MicroMutableOpResolver and have an application specific template parameter. +// The examples directory has sample code for this. +class AllOpsResolver : public MicroMutableOpResolver<128> { + public: + AllOpsResolver(); + + private: + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ALL_OPS_RESOLVER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/compatibility.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/compatibility.h new file mode 100644 index 0000000..db117ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/compatibility.h @@ -0,0 +1,31 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_COMPATIBILITY_H_ +#define TENSORFLOW_LITE_MICRO_COMPATIBILITY_H_ + +// C++ will automatically create class-specific delete operators for virtual +// objects, which by default call the global delete function. For embedded +// applications we want to avoid this, and won't be calling new/delete on these +// objects, so we need to override the default implementation with one that does +// nothing to avoid linking in ::delete(). +// This macro needs to be included in all subclasses of a virtual base class in +// the private section. + +// Patched by Edge Impulse, +// actually declaring `void operator delete(void* p) {}` +// yields compiler errors on some compilers +#define TF_LITE_REMOVE_VIRTUAL_DELETE + +#endif // TENSORFLOW_LITE_MICRO_COMPATIBILITY_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/debug_log.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/debug_log.h new file mode 100644 index 0000000..f3ba464 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/debug_log.h @@ -0,0 +1,28 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_DEBUG_LOG_H_ +#define TENSORFLOW_LITE_MICRO_DEBUG_LOG_H_ + +// This function should be implemented by each target platform, and provide a +// way for strings to be output to some text stream. For more information, see +// tensorflow/lite/micro/debug_log.cc. +#if defined(__cplusplus) && EI_C_LINKAGE == 1 +extern "C" void DebugLog(const char* s); +#else +void DebugLog(const char* s); +#endif // defined(__cplusplus) && EI_C_LINKAGE == 1 + +#endif // TENSORFLOW_LITE_MICRO_DEBUG_LOG_H_ + diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.cpp new file mode 100644 index 0000000..5ca66ab --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.cpp @@ -0,0 +1,110 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.h" + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_arena_constants.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +// Patched by Edge Impulse +constexpr int FakeMicroContext::kNumScratchBuffers_; + +namespace { +// Dummy static variables to allow creation of dummy MicroAllocator. +// All tests are guarateed to run serially. +static constexpr int KDummyTensorArenaSize = 256; +static uint8_t dummy_tensor_arena[KDummyTensorArenaSize]; +} // namespace + +FakeMicroContext::FakeMicroContext(TfLiteTensor* tensors, + SingleArenaBufferAllocator* allocator, + MicroGraph* micro_graph) + : MicroContext( + MicroAllocator::Create(dummy_tensor_arena, KDummyTensorArenaSize), + nullptr, micro_graph), + tensors_(tensors), + allocator_(allocator) {} + +TfLiteTensor* FakeMicroContext::AllocateTempTfLiteTensor(int tensor_index) { + allocated_tensor_count_++; + return &tensors_[tensor_index]; +} + +void FakeMicroContext::DeallocateTempTfLiteTensor(TfLiteTensor* tensor) { + allocated_tensor_count_--; +} + +bool FakeMicroContext::IsAllTempTfLiteTensorDeallocated() { + return !allocated_tensor_count_; +} + +TfLiteEvalTensor* FakeMicroContext::GetEvalTensor(int tensor_index) { + TfLiteEvalTensor* eval_tensor = + reinterpret_cast(allocator_->AllocateTemp( + sizeof(TfLiteEvalTensor), alignof(TfLiteEvalTensor))); + TFLITE_DCHECK(eval_tensor != nullptr); + + // In unit tests, the TfLiteTensor pointer contains the source of truth for + // buffers and values: + eval_tensor->data = tensors_[tensor_index].data; + eval_tensor->dims = tensors_[tensor_index].dims; + eval_tensor->type = tensors_[tensor_index].type; + return eval_tensor; +} + +void* FakeMicroContext::AllocatePersistentBuffer(size_t bytes) { + // FakeMicroContext use SingleArenaBufferAllocator, which does not + // automatically apply the buffer alignment like MicroAllocator. The buffer + // alignment is potentially wasteful but allows the fake_micro_context to work + // correctly with optimized kernels. + return allocator_->AllocatePersistentBuffer(bytes, + MicroArenaBufferAlignment()); +} + +TfLiteStatus FakeMicroContext::RequestScratchBufferInArena(size_t bytes, + int* buffer_index) { + TFLITE_DCHECK(buffer_index != nullptr); + + if (scratch_buffer_count_ == kNumScratchBuffers_) { + MicroPrintf("Exceeded the maximum number of scratch tensors allowed (%d).", + kNumScratchBuffers_); + return kTfLiteError; + } + + // For tests, we allocate scratch buffers from the tail and keep them around + // for the lifetime of model. This means that the arena size in the tests will + // be more than what we would have if the scratch buffers could share memory. + scratch_buffers_[scratch_buffer_count_] = + allocator_->AllocatePersistentBuffer(bytes, MicroArenaBufferAlignment()); + TFLITE_DCHECK(scratch_buffers_[scratch_buffer_count_] != nullptr); + + *buffer_index = scratch_buffer_count_++; + return kTfLiteOk; +} + +void* FakeMicroContext::GetScratchBuffer(int buffer_index) { + TFLITE_DCHECK(scratch_buffer_count_ <= kNumScratchBuffers_); + if (buffer_index >= scratch_buffer_count_) { + return nullptr; + } + return scratch_buffers_[buffer_index]; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.h new file mode 100644 index 0000000..a7af023 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.h @@ -0,0 +1,56 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_FAKE_MICRO_CONTEXT_H_ +#define TENSORFLOW_LITE_MICRO_FAKE_MICRO_CONTEXT_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" + +namespace tflite { +// A fake of MicroContext for kernel util tests. +class FakeMicroContext : public MicroContext { + public: + FakeMicroContext(TfLiteTensor* tensors, SingleArenaBufferAllocator* allocator, + MicroGraph* micro_graph); + + void* AllocatePersistentBuffer(size_t bytes) override; + TfLiteStatus RequestScratchBufferInArena(size_t bytes, + int* buffer_index) override; + void* GetScratchBuffer(int buffer_index) override; + + TfLiteTensor* AllocateTempTfLiteTensor(int tensor_index) override; + void DeallocateTempTfLiteTensor(TfLiteTensor* tensor) override; + bool IsAllTempTfLiteTensorDeallocated(); + + TfLiteEvalTensor* GetEvalTensor(int tensor_index) override; + + private: + static constexpr int kNumScratchBuffers_ = 12; + + int scratch_buffer_count_ = 0; + uint8_t* scratch_buffers_[kNumScratchBuffers_]; + + TfLiteTensor* tensors_; + int allocated_tensor_count_ = 0; + + SingleArenaBufferAllocator* allocator_; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_FAKE_MICRO_CONTEXT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.cpp new file mode 100644 index 0000000..2fe1663 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.cpp @@ -0,0 +1,34 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { +TfLiteStatus ConvertTensorType(TensorType tensor_type, TfLiteType* type) { + return ConvertTensorType(tensor_type, type, tflite::GetMicroErrorReporter()); +} + +TfLiteStatus CallBuiltinParseFunction(TfLiteBridgeBuiltinParseFunction parser, + const Operator* op, + BuiltinDataAllocator* allocator, + void** builtin_data) { + return parser(op, tflite::GetMicroErrorReporter(), allocator, builtin_data); +} +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h new file mode 100644 index 0000000..a2a1ad4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h @@ -0,0 +1,45 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_FLATBUFFER_CONVERSIONS_BRIDGE_H_ +#define TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_FLATBUFFER_CONVERSIONS_BRIDGE_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +// Forward declaration of the ErrorReporter class to hide it from the TFLM code. +class ErrorReporter; + +using TfLiteBridgeBuiltinDataAllocator = BuiltinDataAllocator; + +using TfLiteBridgeBuiltinParseFunction = + TfLiteStatus (*)(const Operator* op, ErrorReporter* error_reporter, + BuiltinDataAllocator* allocator, void** builtin_data); + +// Converts the tensor data type used in the flatbuffer to the representation +// used by the runtime. +TfLiteStatus ConvertTensorType(TensorType tensor_type, TfLiteType* type); + +// CallBuiltinParseFunction is a wrapper function to wrap the parser function +// calls to Call parser(op, allocator, builtin_data) +TfLiteStatus CallBuiltinParseFunction(TfLiteBridgeBuiltinParseFunction parser, + const Operator* op, + BuiltinDataAllocator* allocator, + void** builtin_data); +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_FLATBUFFER_CONVERSIONS_BRIDGE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.cpp new file mode 100644 index 0000000..e5d779b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.cpp @@ -0,0 +1,85 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h" + +namespace tflite { + +FlexbufferWrapper::FlexbufferWrapper(const uint8_t* buffer, size_t size) + : flexbuffers::Vector(flexbuffers::GetRoot(buffer, size).AsVector()) {} + +int64_t FlexbufferWrapper::ElementAsInt64(size_t i) const { + const uint8_t* elem = data_ + i * byte_width_; + return ::flexbuffers::ReadInt64(elem, byte_width_); +} + +uint64_t FlexbufferWrapper::ElementAsUInt64(size_t i) const { + const uint8_t* elem = data_ + i * byte_width_; + return ::flexbuffers::ReadUInt64(elem, byte_width_); +} + +int32_t FlexbufferWrapper::ElementAsInt32(size_t i) const { + return static_cast(ElementAsInt64(i)); +} + +bool FlexbufferWrapper::ElementAsBool(size_t i) const { + return static_cast(ElementAsUInt64(i)); +} + +double FlexbufferWrapper::ElementAsDouble(size_t i) const { + const uint8_t* elem = data_ + i * byte_width_; + return ::flexbuffers::ReadDouble(elem, byte_width_); +} + +float FlexbufferWrapper::ElementAsFloat(size_t i) const { + return static_cast(FlexbufferWrapper::ElementAsDouble(i)); +} + +// TODO(b/192589496): Ops must always be there. Remove this function when fixed +uint32_t NumSubgraphOperators(const SubGraph* subgraph) { + if (subgraph->operators() != nullptr) { + return subgraph->operators()->size(); + } else { + return 0; + } +} +// TODO(b/192589496): Ops must always be there. Remove this function when fixed +uint32_t NumSubgraphOperators(const Model* model, int subgraph_idx) { + const SubGraph* subgraph = model->subgraphs()->Get(subgraph_idx); + return NumSubgraphOperators(subgraph); +} + +TfLiteIntArray* FlatBufferVectorToTfLiteTypeArray( + const flatbuffers::Vector* flatbuffer_array) { + // On little-endian machines, TfLiteIntArray happens to have the same memory + // layout as flatbuffers:Vector, so we can reinterpret_cast the + // flatbuffer vector and avoid a copy and malloc. + // TODO(b/188459715): audit this usage of const_cast. + return const_cast( + reinterpret_cast(flatbuffer_array)); +} + +TfLiteFloatArray* FlatBufferVectorToTfLiteTypeArray( + const flatbuffers::Vector* flatbuffer_array) { + // On little-endian machines, TfLiteFloatArray happens to have the same memory + // layout as flatbuffers:Vector, so we can reinterpret_cast the + // flatbuffer vector and avoid a copy and malloc. + // TODO(b/188459715): audit this usage of const_cast. + return const_cast( + reinterpret_cast(flatbuffer_array)); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h new file mode 100644 index 0000000..a5a7f9e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h @@ -0,0 +1,65 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef THIRD_PARTY_TFLITE_MICRO_TENSORFLOW_LITE_MICRO_FLATBUFFER_UTILS_H_ +#define THIRD_PARTY_TFLITE_MICRO_TENSORFLOW_LITE_MICRO_FLATBUFFER_UTILS_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { +// Kernels use flexbuffers::Map to pack their init parameters in a tflite file, +// with the parameter names as map keys and the parameter values as the +// corresponding map values. +// Accessing the map values using the flexbuffers:Map class is inline heavy, +// which can cause the code size to bloat beyond what's reasonable for a micro +// application. Use this class instead, when possible. +// FlexbufferWrapper takes advantage of the following properties of +// flexbuffers::Map: +// 1. It can be viewed as a flexbuffers::Vector of the values. +// 2. The values in the vector are ordered alphabetically by their keys. +// 3. All integer and Boolean values are stored as 64-bit numbers. +// 4. All floating point values are stored as double precision numbers. +// The properties are mentioned in the flexbuffers docs, but we rely on +// a unit test to catch design changes. +class FlexbufferWrapper : public flexbuffers::Vector { + public: + // Construct with a serialized flexbuffer 'buffer' of 'size' bytes + explicit FlexbufferWrapper(const uint8_t* buffer, size_t size); + int64_t ElementAsInt64(size_t i) const; + uint64_t ElementAsUInt64(size_t i) const; + int32_t ElementAsInt32(size_t i) const; + bool ElementAsBool(size_t i) const; + double ElementAsDouble(size_t i) const; + float ElementAsFloat(size_t i) const; +}; + +// Return the number of operators in a subgraph tflite +uint32_t NumSubgraphOperators(const SubGraph* subgraph); +uint32_t NumSubgraphOperators(const Model* model, int subgraph_idx); + +// Converts a flatbuffer array to a TfLiteArray. +// TODO(b/188459715): These function convert a const input to a non-const via a +// const_cast. It is unclear exactly why this is required. +TfLiteIntArray* FlatBufferVectorToTfLiteTypeArray( + const flatbuffers::Vector* flatbuffer_array); +TfLiteFloatArray* FlatBufferVectorToTfLiteTypeArray( + const flatbuffers::Vector* flatbuffer_array); + +} // namespace tflite + +#endif // THIRD_PARTY_TFLITE_MICRO_TENSORFLOW_LITE_MICRO_FLATBUFFER_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/ibuffer_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/ibuffer_allocator.h new file mode 100644 index 0000000..287eea3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/ibuffer_allocator.h @@ -0,0 +1,100 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_IBUFFER_ALLOCATOR_H_ +#define TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_IBUFFER_ALLOCATOR_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" + +namespace tflite { +// Interface classes that the TFLM framework relies on to get buffers it needs. +// There are two types of buffers that the TFLM framework requires: persistent +// and non-persistent. Persistent buffers, once allocated, are never freed by +// the TFLM framework. Non-persist buffers can be allocated and deallocated by +// the TFLM framework. This file defines two interfaces classes that TFLM +// framework will rely on to manage these buffers. + +// Interface class for managing persistent buffers. +class IPersistentBufferAllocator { + public: + IPersistentBufferAllocator() {} + virtual ~IPersistentBufferAllocator() {} + + // Allocates persistent memory. The persistent buffer is never freed. + virtual uint8_t* AllocatePersistentBuffer(size_t size, size_t alignment) = 0; + + // Returns the size of all persistent allocations in bytes. + virtual size_t GetPersistentUsedBytes() const = 0; +}; + +// Interface class for managing non-persistent buffers. +// The default non-persistent buffers are temp buffers that are not resizable. +// Support of at least one resizable buffer is required. +class INonPersistentBufferAllocator { + public: + INonPersistentBufferAllocator() {} + virtual ~INonPersistentBufferAllocator() {} + + // Allocates a temporary buffer. This buffer is not resizable. + virtual uint8_t* AllocateTemp(size_t size, size_t alignment) = 0; + + // Signals that a temporary buffer is no longer needed. + virtual void DeallocateTemp(uint8_t* buf) = 0; + + // Returns true if all temporary buffers are already deallocated. + virtual bool IsAllTempDeallocated() = 0; + + // Signals that all temporary allocations can be reclaimed. TFLM calls this + // API when it knows that all temporary buffers that it requested has been + // deallocated. The goal of API is to facilitate implementations of + // INonPersistentBufferAllocator can reuse buffer with some reasonable + // complexity. + virtual TfLiteStatus ResetTempAllocations() = 0; + + // Returns a buffer that is resizable viable ResizeBuffer(). + virtual uint8_t* AllocateResizableBuffer(size_t size, size_t alignment) = 0; + + // Resizes a buffer that is previously returned by the + // AllocateResizableBuffer. + virtual TfLiteStatus ResizeBuffer(uint8_t* resizable_buf, size_t size, + size_t alignment) = 0; + + // Frees up the memory occupied by the resizable buffer. + virtual TfLiteStatus DeallocateResizableBuffer(uint8_t* resizable_buf) = 0; + + // Returns a pointer pointing to the start of the overlay memory, which is + // used for activation tensors and scratch buffers by kernels at Invoke stage. + virtual uint8_t* GetOverlayMemoryAddress() const = 0; + + // Reserves the size of the overlay memory. This overlay is reserved for the + // kernels at Invoke stage. This is referred to as the overlay because before + // Invoket state, the same memory can be used for temp buffers. The layout of + // the memory is planned by the memory planner separately at Invoke stage. + virtual TfLiteStatus ReserveNonPersistentOverlayMemory(size_t size, + size_t alignment) = 0; + + // Returns the size of non-persistent buffer in use. + virtual size_t GetNonPersistentUsedBytes() const = 0; + + // Returns the number of bytes available with a given alignment. This number + // takes in account any temporary allocations. + virtual size_t GetAvailableMemory(size_t alignment) const = 0; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_IBUFFER_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activation_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activation_utils.h new file mode 100644 index 0000000..895b36c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activation_utils.h @@ -0,0 +1,57 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_ACTIVATION_UTILS_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_ACTIVATION_UTILS_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/max.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/min.h" + +namespace tflite { +namespace ops { +namespace micro { + +// Returns the floating point value for a fused activation: +inline float ActivationValFloat(TfLiteFusedActivation act, float a) { + switch (act) { + case kTfLiteActNone: + return a; + case kTfLiteActRelu: + return TfLiteMax(0.0f, a); + case kTfLiteActReluN1To1: + return TfLiteMax(-1.0f, TfLiteMin(a, 1.0f)); + case kTfLiteActRelu6: + return TfLiteMax(0.0f, TfLiteMin(a, 6.0f)); + case kTfLiteActTanh: + return std::tanh(a); + case kTfLiteActSignBit: + return std::signbit(a); + case kTfLiteActSigmoid: + return 1.0f / (1.0f + std::exp(-a)); + } + return 0.0f; // To indicate an unsupported activation (i.e. when a new fused + // activation is added to the enum and not handled here). +} + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_ACTIVATION_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.cpp new file mode 100644 index 0000000..4f4cf81 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.cpp @@ -0,0 +1,120 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +void* ReluInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(ReluOpData)); +} + +TfLiteStatus ReluEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const ReluOpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kActivationsInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kActivationsOutputTensor); + + switch (input->type) { + case kTfLiteFloat32: { + ReluFloat(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; + } + case kTfLiteInt8: { + tflite::ReluQuantized(data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + default: { + MicroPrintf("Only float32 is supported currently, got %s", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + } +} + +void* Relu6Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(Relu6OpData)); +} + +TfLiteStatus Relu6Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const Relu6OpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kActivationsInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kActivationsOutputTensor); + + switch (input->type) { + case kTfLiteFloat32: { + Relu6Float(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; + } + case kTfLiteInt8: { + Relu6Quantized(data.zero_int8, data.six_int8, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + default: { + MicroPrintf("Only float32 is supported currently, got %s", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + } +} + +} // namespace + +TfLiteRegistration Register_RELU() { + return tflite::micro::RegisterOp(ReluInit, ReluPrepare, ReluEval); +} + +TfLiteRegistration Register_RELU6() { + return tflite::micro::RegisterOp(Relu6Init, Relu6Prepare, Relu6Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.h new file mode 100644 index 0000000..c6dddcd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.h @@ -0,0 +1,63 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_ACTIVATIONS_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_ACTIVATIONS_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +extern const int kActivationsInputTensor; +extern const int kActivationsOutputTensor; + +struct ReluOpData { + ReluParams params; +}; + +struct Relu6OpData { + int8_t six_int8; + int8_t zero_int8; +}; + +void ReluQuantized(const ReluOpData& data, const RuntimeShape& input_shape, + const RuntimeShape& output_shape, const int8_t* input_data, + int8_t* output_data); + +template +void CalculateReluOpData(const TfLiteTensor* input, TfLiteTensor* output, + ReluOpData* data); + +void ReluFloat(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data); + +void Relu6Float(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data); + +void Relu6Quantized(int8_t lower, int8_t upper, const RuntimeShape& input_shape, + const int8_t* input_data, const RuntimeShape& output_shape, + int8_t* output_data); + +TfLiteStatus ReluPrepare(TfLiteContext* context, TfLiteNode* node); + +TfLiteStatus Relu6Prepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_ACTIVATIONS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations_common.cpp new file mode 100644 index 0000000..d270813 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/activations_common.cpp @@ -0,0 +1,158 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/activations.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +const int kActivationsInputTensor = 0; +const int kActivationsOutputTensor = 0; + +void ReluQuantized(const ReluOpData& data, const RuntimeShape& input_shape, + const RuntimeShape& output_shape, const int8_t* input_data, + int8_t* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + const int32_t val = static_cast(input_data[i]); + int32_t clamped = + data.params.output_offset + + MultiplyByQuantizedMultiplier(val - data.params.input_offset, + data.params.output_multiplier, + data.params.output_shift); + clamped = std::max(data.params.quantized_activation_min, clamped); + clamped = std::min(data.params.quantized_activation_max, clamped); + output_data[i] = static_cast(clamped); + } +} + +template +void CalculateReluOpData(const TfLiteTensor* input, TfLiteTensor* output, + ReluOpData* data) { + float act_min = 0.0; + float act_max = std::numeric_limits::infinity(); + double real_multiplier = static_cast(input->params.scale) / + static_cast(output->params.scale); + + const RuntimeShape input_shape = GetTensorShape(input); + const RuntimeShape output_shape = GetTensorShape(output); + + QuantizeMultiplier(real_multiplier, &data->params.output_multiplier, + &data->params.output_shift); + + data->params.quantized_activation_min = std::max( + static_cast(std::numeric_limits::min()), + output->params.zero_point + + static_cast(roundf(act_min / output->params.scale))); + data->params.quantized_activation_max = + act_max == std::numeric_limits::infinity() + ? static_cast(std::numeric_limits::max()) + : std::min(static_cast(std::numeric_limits::max()), + output->params.zero_point + + static_cast( + roundf(act_max / output->params.scale))); + data->params.input_offset = input->params.zero_point; + data->params.output_offset = output->params.zero_point; +} + +void ReluFloat(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + const float val = input_data[i]; + const float lower = 0.0f; + const float clamped = val < lower ? lower : val; + output_data[i] = clamped; + } +} + +void Relu6Float(const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& output_shape, float* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + const float val = input_data[i]; + const float upper = 6.0f; + const float lower = 0.0f; + const float clamped = val > upper ? upper : val < lower ? lower : val; + output_data[i] = clamped; + } +} + +void Relu6Quantized(int8_t lower, int8_t upper, const RuntimeShape& input_shape, + const int8_t* input_data, const RuntimeShape& output_shape, + int8_t* output_data) { + const int flat_size = MatchingFlatSize(input_shape, output_shape); + for (int i = 0; i < flat_size; ++i) { + const int8_t val = input_data[i]; + const int8_t clamped = val > upper ? upper : val < lower ? lower : val; + output_data[i] = clamped; + } +} + +TfLiteStatus ReluPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + ReluOpData* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kActivationsInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kActivationsOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + if (input->type == kTfLiteInt8) { + CalculateReluOpData(input, output, data); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Relu6Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + Relu6OpData* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kActivationsInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + + if (input->type == kTfLiteInt8) { + data->six_int8 = FloatToQuantizedType(6.0f, input->params.scale, + input->params.zero_point); + data->zero_int8 = input->params.zero_point; + } + + micro_context->DeallocateTempTfLiteTensor(input); + + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add.cpp new file mode 100644 index 0000000..2140d1f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add.cpp @@ -0,0 +1,1383 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +struct OpData { + bool requires_broadcast; + + // These fields are used in both the general 8-bit -> 8bit quantized path, + // and the special 16-bit -> 16bit quantized path + int input1_shift; + int input2_shift; + int32_t output_activation_min; + int32_t output_activation_max; + + // These fields are used only in the general 8-bit -> 8bit quantized path + int32_t input1_multiplier; + int32_t input2_multiplier; + int32_t output_multiplier; + + int output_shift; + int left_shift; + + int32_t input1_offset; + int32_t input2_offset; + int32_t output_offset; + + // Used only for float evals: + float output_activation_min_f32; + float output_activation_max_f32; +}; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteAddParams* params, + const TfLiteTensor* input1, + const TfLiteTensor* input2, TfLiteTensor* output, + OpData* data) { + data->requires_broadcast = !HaveSameShapes(input1, input2); + + if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + // 8bit -> 8bit general quantized path, with general rescalings + data->input1_offset = -input1->params.zero_point; + data->input2_offset = -input2->params.zero_point; + data->output_offset = output->params.zero_point; + data->left_shift = (output->type == kTfLiteInt16) ? 15 : 20; + const double twice_max_input_scale = + 2 * static_cast( + std::max(input1->params.scale, input2->params.scale)); + const double real_input1_multiplier = + static_cast(input1->params.scale) / twice_max_input_scale; + const double real_input2_multiplier = + static_cast(input2->params.scale) / twice_max_input_scale; + const double real_output_multiplier = + twice_max_input_scale / + ((1 << data->left_shift) * static_cast(output->params.scale)); + + QuantizeMultiplierSmallerThanOneExp( + real_input1_multiplier, &data->input1_multiplier, &data->input1_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_input2_multiplier, &data->input2_multiplier, &data->input2_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->output_multiplier, &data->output_shift); + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + } else if (output->type == kTfLiteFloat32) { + CalculateActivationRange(params->activation, + &data->output_activation_min_f32, + &data->output_activation_max_f32); + } + + return kTfLiteOk; +} + +void UpdateOpParams(tflite::ArithmeticParams* const op_params, + const OpData* data) { + op_params->left_shift = data->left_shift; + op_params->input1_offset = data->input1_offset; + op_params->input1_multiplier = data->input1_multiplier; + op_params->input1_shift = data->input1_shift; + op_params->input2_offset = data->input2_offset; + op_params->input2_multiplier = data->input2_multiplier; + op_params->input2_shift = data->input2_shift; + op_params->output_offset = data->output_offset; + op_params->output_multiplier = data->output_multiplier; + op_params->output_shift = data->output_shift; + SetActivationParams(data->output_activation_min, data->output_activation_max, + op_params); +} + +TfLiteStatus EvalAddQuantizedInt8(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + UpdateOpParams(&op_params, data); + + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (need_broadcast) { + reference_integer_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + arm_elementwise_add_s8( + tflite::micro::GetTensorData(input1), + + tflite::micro::GetTensorData(input2), op_params.input1_offset, + op_params.input1_multiplier, op_params.input1_shift, + op_params.input2_offset, op_params.input2_multiplier, + op_params.input2_shift, op_params.left_shift, + tflite::micro::GetTensorData(output), op_params.output_offset, + op_params.output_multiplier, op_params.output_shift, + op_params.quantized_activation_min, op_params.quantized_activation_max, + MatchingElementsSize(tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorShape(output))); + } + + return kTfLiteOk; +} + +TfLiteStatus EvalAddQuantizedInt16(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + UpdateOpParams(&op_params, data); + + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (need_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + arm_elementwise_add_s16( + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorData(input2), op_params.input1_offset, + op_params.input1_multiplier, op_params.input1_shift, + op_params.input2_offset, op_params.input2_multiplier, + op_params.input2_shift, op_params.left_shift, + tflite::micro::GetTensorData(output), op_params.output_offset, + op_params.output_multiplier, op_params.output_shift, + op_params.quantized_activation_min, op_params.quantized_activation_max, + MatchingElementsSize(tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorShape(output))); + } + + return kTfLiteOk; +} + +void EvalAddFloat(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + SetActivationParams(data->output_activation_min_f32, + data->output_activation_max_f32, &op_params); + if (data->requires_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} + +TfLiteStatus EvalAddQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + switch (output->type) { + case kTfLiteInt8: { + EvalAddQuantizedInt8(context, node, params, data, input1, input2, output); + break; + } + case kTfLiteInt16: { + EvalAddQuantizedInt16(context, node, params, data, input1, input2, + output); + break; + } + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +void* InitAdd(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus PrepareAdd(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + if (input1->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, input1->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, input2->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + } + + OpData* data = static_cast(node->user_data); + auto* params = reinterpret_cast(node->builtin_data); + + TF_LITE_ENSURE_STATUS( + CalculateOpData(context, params, input1, input2, output, data)); + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus EvalAdd(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + if (output->type == kTfLiteFloat32) { + EvalAddFloat(context, node, params, data, input1, input2, output); + } else if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + TF_LITE_ENSURE_OK(context, EvalAddQuantized(context, node, params, data, + input1, input2, output)); + } else { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(output->type), + output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteStatus EvalAddInt8(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(output->type == kTfLiteInt8); + const OpData* data = static_cast(node->user_data); + + TF_LITE_ENSURE_OK(context, EvalAddQuantizedInt8(context, node, params, data, + input1, input2, output)); + + return kTfLiteOk; +} + +TfLiteStatus EvalAddInt16(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(output->type == kTfLiteInt16); + const OpData* data = static_cast(node->user_data); + + TF_LITE_ENSURE_OK(context, EvalAddQuantizedInt16(context, node, params, data, + input1, input2, output)); + + return kTfLiteOk; +} + +TfLiteRegistration Register_ADD() { + return tflite::micro::RegisterOp(InitAdd, PrepareAdd, EvalAdd); +} + +TfLiteRegistration Register_ADD_INT8() { + return tflite::micro::RegisterOp(InitAdd, PrepareAdd, EvalAddInt8); +} + +TfLiteRegistration Register_ADD_INT16() { + return tflite::micro::RegisterOp(InitAdd, PrepareAdd, EvalAddInt16); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" + +#include +#include + +#include "mli_api.h" // NOLINT +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +struct OpData { + bool requires_broadcast; + + // These fields are used in both the general 8-bit -> 8bit quantized path, + // and the special 16-bit -> 16bit quantized path + int input1_shift; + int input2_shift; + int32_t output_activation_min; + int32_t output_activation_max; + + // These fields are used only in the general 8-bit -> 8bit quantized path + int32_t input1_multiplier; + int32_t input2_multiplier; + int32_t output_multiplier; + int output_shift; + int left_shift; + int32_t input1_offset; + int32_t input2_offset; + int32_t output_offset; + + // Used only for float evals: + float output_activation_min_f32; + float output_activation_max_f32; + + // The result of checking if MLI optimized version of tensors can be used. + bool is_mli_applicable; + + // Tensors in MLI format. + mutable ops::micro::MliTensorInterface mli_input1; + mutable ops::micro::MliTensorInterface mli_input2; + mutable ops::micro::MliTensorInterface mli_out; +}; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteAddParams* params, + const TfLiteTensor* input1, + const TfLiteTensor* input2, TfLiteTensor* output, + OpData* data) { + data->requires_broadcast = !HaveSameShapes(input1, input2); + + if (output->type == kTfLiteUInt8 || output->type == kTfLiteInt8) { + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + + // MLI 2.0 optimized version only supports int8_t datatype and min/max + // within container range. Broadcasting isn't supported on the primitive + // level (but might be implemented as part of slicing in future) +#ifdef MLI_2_0 // + data->is_mli_applicable = + (input1->type == kTfLiteInt8) && (input2->type == kTfLiteInt8) && + (output->type == kTfLiteInt8) && !data->requires_broadcast && + data->output_activation_min == std::numeric_limits::min() && + data->output_activation_max == std::numeric_limits::max(); +#else + data->is_mli_applicable = false; +#endif + + if (data->is_mli_applicable) { + data->mli_input1 = + ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_input2 = + ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_out = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + + ops::micro::ConvertToMliTensor(input1, &data->mli_input1); + ops::micro::ConvertToMliTensor(input2, &data->mli_input2); + ops::micro::ConvertToMliTensor(output, &data->mli_out); + /* Flatten tensors to simplify the process (as we don't support + * broadcasting). */ + data->mli_input1.Shape()[0] = + mli_hlp_count_elem_num(data->mli_input1.MliTensor(), 0); + data->mli_input2.Shape()[0] = + mli_hlp_count_elem_num(data->mli_input2.MliTensor(), 0); + data->mli_out.Shape()[0] = + mli_hlp_count_elem_num(data->mli_out.MliTensor(), 0); + data->mli_input1.MemStride()[0] = data->mli_input2.MemStride()[0] = 1; + data->mli_out.MemStride()[0] = 1; + *data->mli_input1.Rank() = *data->mli_input2.Rank() = 1; + *data->mli_out.Rank() = 1; + } + } else { + data->is_mli_applicable = false; + } + +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + // 8bit -> 8bit general quantized path, with general rescalings + data->input1_offset = -input1->params.zero_point; + data->input2_offset = -input2->params.zero_point; + data->output_offset = output->params.zero_point; + data->left_shift = (output->type == kTfLiteInt16) ? 15 : 20; + const double twice_max_input_scale = + 2 * static_cast( + std::max(input1->params.scale, input2->params.scale)); + const double real_input1_multiplier = + static_cast(input1->params.scale) / twice_max_input_scale; + const double real_input2_multiplier = + static_cast(input2->params.scale) / twice_max_input_scale; + const double real_output_multiplier = + twice_max_input_scale / + ((1 << data->left_shift) * static_cast(output->params.scale)); + + QuantizeMultiplierSmallerThanOneExp( + real_input1_multiplier, &data->input1_multiplier, &data->input1_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_input2_multiplier, &data->input2_multiplier, &data->input2_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->output_multiplier, &data->output_shift); + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + } else if (output->type == kTfLiteFloat32) { + CalculateActivationRange(params->activation, + &data->output_activation_min_f32, + &data->output_activation_max_f32); +#endif // !defined(TF_LITE_STRIP_REFERENCE_IMPL) + } + + return kTfLiteOk; +} + +TfLiteStatus EvalAdd(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + tflite::ArithmeticParams op_params; + SetActivationParams(data->output_activation_min_f32, + data->output_activation_max_f32, &op_params); + if (data->requires_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + return kTfLiteOk; +#else + MicroPrintf("Node configuration is not supported by ARC MLI Library."); + return kTfLiteError; +#endif +} + +TfLiteStatus EvalAddQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + tflite::ArithmeticParams op_params; + op_params.left_shift = data->left_shift; + op_params.input1_offset = data->input1_offset; + op_params.input1_multiplier = data->input1_multiplier; + op_params.input1_shift = data->input1_shift; + op_params.input2_offset = data->input2_offset; + op_params.input2_multiplier = data->input2_multiplier; + op_params.input2_shift = data->input2_shift; + op_params.output_offset = data->output_offset; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + SetActivationParams(data->output_activation_min, data->output_activation_max, + &op_params); + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + switch (output->type) { + case kTfLiteInt8: { + if (need_broadcast) { + reference_integer_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_integer_ops::Add( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + break; + } + case kTfLiteInt16: { + if (need_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + false); + } + break; + } + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + return kTfLiteOk; +#else + MicroPrintf("Node configuration is not supported by ARC MLI Library."); + return kTfLiteError; +#endif +} + +TfLiteStatus EvalMLIAddInt8(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { +#ifdef MLI_2_0 + TF_LITE_ENSURE(context, data->is_mli_applicable == true); + TF_LITE_ENSURE(context, input1->type == kTfLiteInt8); + TF_LITE_ENSURE(context, input2->type == kTfLiteInt8); + TF_LITE_ENSURE(context, output->type == kTfLiteInt8); + + ops::micro::MliTensorAttachBuffer(input1, &data->mli_input1); + ops::micro::MliTensorAttachBuffer(input2, &data->mli_input2); + ops::micro::MliTensorAttachBuffer(output, &data->mli_out); + + // mli_mov config and tensors for data in fast (local) memory with interface + mli_mov_cfg_t copy_config; + mli_mov_cfg_for_copy(©_config); + mli_tensor input1_local_tsr = *data->mli_input1.MliTensor(); + mli_tensor input2_local_tsr = *data->mli_input2.MliTensor(); + mli_tensor out_local_tsr = *data->mli_out.MliTensor(); + ops::micro::MliTensorInterface input1_local(&input1_local_tsr); + ops::micro::MliTensorInterface input2_local(&input2_local_tsr); + ops::micro::MliTensorInterface out_local(&out_local_tsr); + + /* allocate the local buffers, and compute the slice size */ + TF_LITE_ENSURE_STATUS(ops::micro::get_arc_scratch_buffer_for_eltwise_tensors( + context, &input1_local, &input2_local, &out_local)); + TF_LITE_ENSURE(context, *input1_local.Rank() == 1 && + *input2_local.Rank() == 1 && + *out_local.Rank() == 1); + uint32_t min_capacity = *input1_local.DataCapacity(); + min_capacity = std::min(min_capacity, *input2_local.DataCapacity()); + min_capacity = std::min(min_capacity, *out_local.DataCapacity()); + const int slice_dim = 0; + const int slice_size = + min_capacity / mli_hlp_tensor_element_size(out_local.MliTensor()); + + /* is_local indicates that the tensor is already in local memory, + so in that case the original tensor can be used, + and there is no need to copy it to the local tensor*/ + const bool input1_is_local = + input1_local.Data() == data->mli_input1.Data(); + const bool input2_is_local = + input2_local.Data() == data->mli_input2.Data(); + const bool out_is_local = + out_local.Data() == data->mli_out.Data(); + + ops::micro::TensorSlicer input1_slice(data->mli_input1.MliTensor(), slice_dim, + slice_size); + ops::micro::TensorSlicer input2_slice(data->mli_input2.MliTensor(), slice_dim, + slice_size); + ops::micro::TensorSlicer out_slice(data->mli_out.MliTensor(), slice_dim, + slice_size); + + mli_tensor* input1_tsr = + input1_is_local ? input1_slice.Sub() : input1_local.MliTensor(); + mli_tensor* input2_tsr = + input2_is_local ? input2_slice.Sub() : input2_local.MliTensor(); + mli_tensor* out_tsr = out_is_local ? out_slice.Sub() : out_local.MliTensor(); + + while (!out_slice.Done()) { + mli_mov_tensor_sync(input1_slice.Sub(), ©_config, input1_tsr); + mli_mov_tensor_sync(input2_slice.Sub(), ©_config, input2_tsr); + + mli_krn_eltwise_add_sa8(input1_tsr, input2_tsr, out_tsr); + + mli_mov_tensor_sync(out_tsr, ©_config, out_slice.Sub()); + input1_slice.Next(); + input2_slice.Next(); + out_slice.Next(); + } + return kTfLiteOk; +#else + return kTfLiteError; +#endif +} + +void* AddInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus AddEval(TfLiteContext* context, TfLiteNode* node) { + TfLiteStatus ret_val = kTfLiteOk; + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + if (data->is_mli_applicable) { + ret_val = + EvalMLIAddInt8(context, node, params, data, input1, input2, output); + } else if (output->type == kTfLiteFloat32) { + ret_val = EvalAdd(context, node, params, data, input1, input2, output); + } else if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + ret_val = + EvalAddQuantized(context, node, params, data, input1, input2, output); + } else { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(output->type), + output->type); + ret_val = kTfLiteError; + } + + return ret_val; +} + +TfLiteRegistration Register_ADD() { + return tflite::micro::RegisterOp(AddInit, AddPrepare, AddEval); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP == 1 +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "sl_mvp_ml_add.h" + +namespace tflite { +namespace sl { +namespace add { + +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +struct OpData { + bool requires_broadcast; + + int input1_shift; + int input2_shift; + int32_t input1_multiplier; + int32_t input2_multiplier; + int32_t output_multiplier; + int output_shift; + int left_shift; + + sli_mvp_ml_add_s8_params_t params; + + // Used only for float evals: + float output_activation_min_f32; + float output_activation_max_f32; +}; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteAddParams* params, + const TfLiteTensor* input1, + const TfLiteTensor* input2, TfLiteTensor* output, + OpData* data) { + data->requires_broadcast = !HaveSameShapes(input1, input2); + + if (output->type == kTfLiteInt8) { + data->params.input1_offset = -input1->params.zero_point; + data->params.input2_offset = -input2->params.zero_point; + data->params.output_offset = output->params.zero_point; + data->params.input1_multiplier = input1->params.scale; + data->params.input2_multiplier = input2->params.scale; + data->params.output_multiplier = 1.0 / output->params.scale; + data->params.length = GetTensorShape(input1).FlatSize(); + + int32_t activation_min; + int32_t activation_max; + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &activation_min, + &activation_max)); + data->params.activation_min = static_cast(activation_min); + data->params.activation_max = static_cast(activation_max); + + // These multipliers and parameters are not used by the MVP codepath, + // however are needed in cases where broadcast is used. + data->left_shift = 20; + const double twice_max_input_scale = + 2 * static_cast( + std::max(input1->params.scale, input2->params.scale)); + const double real_input1_multiplier = + static_cast(input1->params.scale) / twice_max_input_scale; + const double real_input2_multiplier = + static_cast(input2->params.scale) / twice_max_input_scale; + const double real_output_multiplier = + twice_max_input_scale / + ((1 << data->left_shift) * static_cast(output->params.scale)); + + QuantizeMultiplierSmallerThanOneExp( + real_input1_multiplier, &data->input1_multiplier, &data->input1_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_input2_multiplier, &data->input2_multiplier, &data->input2_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->output_multiplier, &data->output_shift); + + } else if (output->type == kTfLiteFloat32) { + CalculateActivationRange(params->activation, + &data->output_activation_min_f32, + &data->output_activation_max_f32); + } + + return kTfLiteOk; +} + +void EvalAdd(TfLiteContext* context, TfLiteNode* node, TfLiteAddParams* params, + const OpData* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + SetActivationParams(data->output_activation_min_f32, + data->output_activation_max_f32, &op_params); + if (data->requires_broadcast) { + reference_ops::BroadcastAdd4DSlow(op_params, tflite::micro::GetTensorShape(input1), tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, + tflite::micro::GetTensorShape(input1), tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), tflite::micro::GetTensorData(output)); + } +} + +TfLiteStatus EvalAddQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + TfLiteStatus status = kTfLiteOk; + tflite::ArithmeticParams op_params; + op_params.left_shift = data->left_shift; + op_params.input1_offset = data->params.input1_offset; + op_params.input1_multiplier = data->input1_multiplier; + op_params.input1_shift = data->input1_shift; + op_params.input2_offset = data->params.input2_offset; + op_params.input2_multiplier = data->input2_multiplier; + op_params.input2_shift = data->input2_shift; + op_params.output_offset = data->params.output_offset; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + op_params.quantized_activation_min = data->params.activation_min; + op_params.quantized_activation_max = data->params.activation_max; + + // TODO: Do we need to support the broadcast scenario? + bool need_broadcast = reference_ops::ProcessBroadcastShapes(tflite::micro::GetTensorShape(input1), tflite::micro::GetTensorShape(input2), &op_params); + + if (need_broadcast) { + reference_integer_ops::BroadcastAdd4DSlow(op_params, + tflite::micro::GetTensorShape(input1), tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), tflite::micro::GetTensorData(output)); + } else { + sli_mvp_ml_add_s8_params_t params = data->params; + params.input1 = tflite::micro::GetTensorData(input1); + params.input2 = tflite::micro::GetTensorData(input2); + params.output = tflite::micro::GetTensorData(output); + sl_status_t ret = sli_mvp_ml_add_s8(¶ms); + if (ret != SL_STATUS_OK) { + status = kTfLiteError; + } + } + + return status; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + const TfLiteTensor* input1 = GetInput(context, node, kInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + const TfLiteTensor* input2 = GetInput(context, node, kInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + OpData* data = static_cast(node->user_data); + auto* params = reinterpret_cast(node->builtin_data); + + TF_LITE_ENSURE_STATUS( + CalculateOpData(context, params, input1, input2, output, data)); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (output->type == kTfLiteFloat32) { + EvalAdd(context, node, params, data, input1, input2, output); + } else if (output->type == kTfLiteInt8) { + TF_LITE_ENSURE_OK(context, EvalAddQuantized(context, node, params, data, + input1, input2, output)); + } else { + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace add +} // namespace sl + +TfLiteRegistration Register_ADD() { + return {/*init=*/sl::add::Init, + /*free=*/nullptr, + /*prepare=*/sl::add::Prepare, + /*invoke=*/sl::add::Eval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#include + +#if ESP_NN +#include "edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h" +#endif + +long long add_total_time = 0; + +namespace tflite { + +void EvalAdd(TfLiteContext* context, TfLiteNode* node, TfLiteAddParams* params, + const OpDataAdd* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + SetActivationParams(data->output_activation_min_f32, + data->output_activation_max_f32, &op_params); + if (data->requires_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} + +TfLiteStatus EvalAddQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpDataAdd* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + op_params.left_shift = data->left_shift; + op_params.input1_offset = data->input1_offset; + op_params.input1_multiplier = data->input1_multiplier; + op_params.input1_shift = data->input1_shift; + op_params.input2_offset = data->input2_offset; + op_params.input2_multiplier = data->input2_multiplier; + op_params.input2_shift = data->input2_shift; + op_params.output_offset = data->output_offset; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + SetActivationParams(data->output_activation_min, data->output_activation_max, + &op_params); + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + switch (output->type) { + case kTfLiteInt8: { + if (need_broadcast) { + reference_integer_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { +#if ESP_NN + const int8_t *input1_data = tflite::micro::GetTensorData(input1); + const int8_t *input2_data = tflite::micro::GetTensorData(input2); + int8_t *out_data = tflite::micro::GetTensorData(output); + + esp_nn_add_elementwise_s8(input1_data, + input2_data, + data->input1_offset, + data->input2_offset, + data->input1_multiplier, + data->input2_multiplier, + data->input1_shift, + data->input2_shift, + data->left_shift, + out_data, + data->output_offset, + data->output_multiplier, + data->output_shift, + data->output_activation_min, + data->output_activation_max, + MatchingElementsSize(tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorShape(output)) + ); +#else + reference_integer_ops::Add( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#endif + } + break; + } + case kTfLiteInt16: { + if (need_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + false); + } + break; + } + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +void* AddInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataAdd)); +} + +TfLiteStatus AddEval(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataAdd* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kAddInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kAddInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kAddOutputTensor); + + long long start_time = esp_timer_get_time(); + + if (output->type == kTfLiteFloat32) { + EvalAdd(context, node, params, data, input1, input2, output); + } else if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + TF_LITE_ENSURE_OK(context, EvalAddQuantized(context, node, params, data, + input1, input2, output)); + } else { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(output->type), + output->type); + return kTfLiteError; + } + add_total_time += esp_timer_get_time() - start_time; + + return kTfLiteOk; +} + +TfLiteRegistration Register_ADD() { + return tflite::micro::RegisterOp(AddInit, AddPrepare, AddEval); +} + +} // namespace tflite + +#else +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +void EvalAdd(TfLiteContext* context, TfLiteNode* node, TfLiteAddParams* params, + const OpDataAdd* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + SetActivationParams(data->output_activation_min_f32, + data->output_activation_max_f32, &op_params); + if (data->requires_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} + +TfLiteStatus EvalAddQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteAddParams* params, const OpDataAdd* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + op_params.left_shift = data->left_shift; + op_params.input1_offset = data->input1_offset; + op_params.input1_multiplier = data->input1_multiplier; + op_params.input1_shift = data->input1_shift; + op_params.input2_offset = data->input2_offset; + op_params.input2_multiplier = data->input2_multiplier; + op_params.input2_shift = data->input2_shift; + op_params.output_offset = data->output_offset; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + SetActivationParams(data->output_activation_min, data->output_activation_max, + &op_params); + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + switch (output->type) { + case kTfLiteInt8: { + if (need_broadcast) { + reference_integer_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_integer_ops::Add( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + break; + } + case kTfLiteInt16: { + if (need_broadcast) { + reference_ops::BroadcastAdd4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Add(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + false); + } + break; + } + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +void* AddInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataAdd)); +} + +TfLiteStatus AddEval(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataAdd* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kAddInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kAddInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kAddOutputTensor); + + if (output->type == kTfLiteFloat32) { + EvalAdd(context, node, params, data, input1, input2, output); + } else if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + TF_LITE_ENSURE_OK(context, EvalAddQuantized(context, node, params, data, + input1, input2, output)); + } else { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(output->type), + output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteRegistration Register_ADD() { + return tflite::micro::RegisterOp(AddInit, AddPrepare, AddEval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h new file mode 100644 index 0000000..e91ffb3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h @@ -0,0 +1,77 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_ADD_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_ADD_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +extern const int kAddInputTensor1; +extern const int kAddInputTensor2; +extern const int kAddOutputTensor; + +struct OpDataAdd { + bool requires_broadcast; + + // These fields are used in both the general 8-bit -> 8bit quantized path, + // and the special 16-bit -> 16bit quantized path + int input1_shift; + int input2_shift; + int32_t output_activation_min; + int32_t output_activation_max; + + // These fields are used only in the general 8-bit -> 8bit quantized path + int32_t input1_multiplier; + int32_t input2_multiplier; + int32_t output_multiplier; + int output_shift; + int left_shift; + int32_t input1_offset; + int32_t input2_offset; + int32_t output_offset; + + // Used only for float evals: + float output_activation_min_f32; + float output_activation_max_f32; +}; + +TfLiteStatus CalculateOpDataAdd(TfLiteContext* context, TfLiteAddParams* params, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteTensor* output, OpDataAdd* data); + +TfLiteStatus AddPrepare(TfLiteContext* context, TfLiteNode* node); + +// Generic must define registration function. +TfLiteRegistration Register_ADD(); + +#if defined(CMSIS_NN) +TfLiteRegistration Register_ADD_INT8(); + +TfLiteRegistration Register_ADD_INT16(); +#else +// Fallback registration +inline TfLiteRegistration Register_ADD_INT8() { return Register_ADD(); } + +inline TfLiteRegistration Register_ADD_INT16() { return Register_ADD(); } +#endif +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_ADD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add_common.cpp new file mode 100644 index 0000000..d9622a2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add_common.cpp @@ -0,0 +1,106 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" + +namespace tflite { + +const int kAddInputTensor1 = 0; +const int kAddInputTensor2 = 1; +const int kAddOutputTensor = 0; + +TfLiteStatus CalculateOpDataAdd(TfLiteContext* context, TfLiteAddParams* params, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteTensor* output, OpDataAdd* data) { + data->requires_broadcast = !HaveSameShapes(input1, input2); + + if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + // 8bit -> 8bit general quantized path, with general rescalings + data->input1_offset = -input1->params.zero_point; + data->input2_offset = -input2->params.zero_point; + data->output_offset = output->params.zero_point; + data->left_shift = (output->type == kTfLiteInt16) ? 15 : 20; + const double twice_max_input_scale = + 2 * static_cast( + std::max(input1->params.scale, input2->params.scale)); + const double real_input1_multiplier = + static_cast(input1->params.scale) / twice_max_input_scale; + const double real_input2_multiplier = + static_cast(input2->params.scale) / twice_max_input_scale; + const double real_output_multiplier = + twice_max_input_scale / + ((1 << data->left_shift) * static_cast(output->params.scale)); + + QuantizeMultiplierSmallerThanOneExp( + real_input1_multiplier, &data->input1_multiplier, &data->input1_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_input2_multiplier, &data->input2_multiplier, &data->input2_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->output_multiplier, &data->output_shift); + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + } else if (output->type == kTfLiteFloat32) { + CalculateActivationRange(params->activation, + &data->output_activation_min_f32, + &data->output_activation_max_f32); + } + + return kTfLiteOk; +} + +TfLiteStatus AddPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kAddInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kAddInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kAddOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + OpDataAdd* data = static_cast(node->user_data); + auto* params = reinterpret_cast(node->builtin_data); + + TF_LITE_ENSURE_STATUS( + CalculateOpDataAdd(context, params, input1, input2, output, data)); + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add_n.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add_n.cpp new file mode 100644 index 0000000..0ec3276 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/add_n.cpp @@ -0,0 +1,215 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add_n.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor0 = 0; +constexpr int kOutputTensor = 0; + +constexpr int kAddNIntegerShift = 20; + +// only used with INT8 tensors +struct OpData { + int32_t output_activation_min; + int32_t output_activation_max; + int32_t input_offset; + int32_t output_offset; + int32_t input_multiplier; + int32_t output_multiplier; + int input_shift; + int output_shift; + int left_shift; + int scratch_index; +}; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + int num_inputs = NumInputs(node); + TF_LITE_ENSURE(context, num_inputs >= 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input_tensor_first = + micro_context->AllocateTempInputTensor(node, kInputTensor0); + TF_LITE_ENSURE(context, input_tensor_first != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + // Check that all tensors have the same shape and type. + TF_LITE_ENSURE_TYPES_EQ(context, output->type, input_tensor_first->type); + for (int i = kInputTensor0 + 1; i < num_inputs; ++i) { + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, i); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, HaveSameShapes(input_tensor_first, input)); + TF_LITE_ENSURE_TYPES_EQ(context, input_tensor_first->type, input->type); + + // Check that all INT8 input tensors have the same zero-point and scale. + if (input_tensor_first->type == kTfLiteInt8) { + TF_LITE_ENSURE(context, input_tensor_first->params.zero_point == + input->params.zero_point); + TF_LITE_ENSURE(context, + input_tensor_first->params.scale == input->params.scale); + } + + micro_context->DeallocateTempTfLiteTensor(input); + } + + if (output->type == kTfLiteFloat32) { + // Allocate scratch buffer space for pointer to each tensor's data + // and store the scratch buffer index in the node's user_data + int scratch_index; + size_t scratch_size = sizeof(float*) * num_inputs; + TF_LITE_ENSURE_OK(context, context->RequestScratchBufferInArena( + context, scratch_size, &scratch_index)); + node->user_data = + reinterpret_castuser_data)>(scratch_index); + } else if (output->type == kTfLiteInt8) { + node->user_data = + context->AllocatePersistentBuffer(context, sizeof(OpData)); + OpData* data = static_cast(node->user_data); + + // Allocate scratch buffer space for pointer to each tensor's data + // and store the scratch buffer index in OpData + size_t scratch_size = sizeof(int8_t*) * num_inputs; + TF_LITE_ENSURE_OK( + context, context->RequestScratchBufferInArena(context, scratch_size, + &data->scratch_index)); + + // 8bit -> 8bit general quantized path, with general rescalings + data->input_offset = -input_tensor_first->params.zero_point; + data->output_offset = output->params.zero_point; + data->left_shift = kAddNIntegerShift; + const double twice_max_input_scale = + 2 * static_cast(input_tensor_first->params.scale); + const double real_input_multiplier = + static_cast(input_tensor_first->params.scale) / + twice_max_input_scale; + const double real_output_multiplier = + twice_max_input_scale / + ((1 << data->left_shift) * static_cast(output->params.scale)); + + QuantizeMultiplierSmallerThanOneExp( + real_input_multiplier, &data->input_multiplier, &data->input_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->output_multiplier, &data->output_shift); + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, kTfLiteActNone, output, &data->output_activation_min, + &data->output_activation_max)); + } else { + MicroPrintf("ADD_N only supports FLOAT32 and INT8, got %s.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + + micro_context->DeallocateTempTfLiteTensor(input_tensor_first); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +template +inline const T** CopyInputsToScratchBuffer(TfLiteContext* context, + TfLiteNode* node, + const int scratch_index) { + int num_inputs = NumInputs(node); + void* scratch_buffer = context->GetScratchBuffer(context, scratch_index); + const T** all_inputs = static_cast(scratch_buffer); + for (int i = 0; i < num_inputs; i++) { + const TfLiteEvalTensor* next_input = + tflite::micro::GetEvalInput(context, node, kInputTensor0 + i); + all_inputs[i] = tflite::micro::GetTensorData(next_input); + } + + return all_inputs; +} + +template +void EvalAddN(TfLiteContext* context, TfLiteNode* node, + TfLiteEvalTensor* output) { + int num_inputs = NumInputs(node); + + int scratch_index = + static_cast(reinterpret_cast(node->user_data)); + const T** all_inputs = + CopyInputsToScratchBuffer(context, node, scratch_index); + + reference_ops::AddN(tflite::micro::GetTensorShape(output), num_inputs, + all_inputs, tflite::micro::GetTensorData(output)); +} + +template +void EvalAddNQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteEvalTensor* output) { + int num_inputs = NumInputs(node); + + OpData* data = static_cast(node->user_data); + const T** all_inputs = + CopyInputsToScratchBuffer(context, node, data->scratch_index); + + ArithmeticParams params; + params.left_shift = data->left_shift; + params.input1_offset = data->input_offset; + params.input1_multiplier = data->input_multiplier; + params.input1_shift = data->input_shift; + params.output_offset = data->output_offset; + params.output_multiplier = data->output_multiplier; + params.output_shift = data->output_shift; + SetActivationParams(data->output_activation_min, data->output_activation_max, + ¶ms); + + reference_ops::AddN(params, tflite::micro::GetTensorShape(output), num_inputs, + all_inputs, tflite::micro::GetTensorData(output)); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + if (output->type == kTfLiteFloat32) { + EvalAddN(context, node, output); + } else if (output->type == kTfLiteInt8) { + EvalAddNQuantized(context, node, output); + } else { + MicroPrintf("ADD_N only supports FLOAT32 and INT8, got %s.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_ADD_N() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/arg_min_max.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/arg_min_max.cpp new file mode 100644 index 0000000..f781ab5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/arg_min_max.cpp @@ -0,0 +1,118 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/arg_min_max.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/comparisons.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kAxis = 1; +constexpr int kOutputTensor = 0; + +template +inline void ArgMinMaxHelper(const RuntimeShape& input1_shape, + const T1* input1_data, const T3* input2_data, + const RuntimeShape& output_shape, T2* output_data, + bool is_arg_max) { + // Use Greater/Less from comparisons.h (formerly from kernels/micro_utils.h + // which was deprecated). Same as gtl::Greater but used here to reduce + // dependencies and binary size for micro environment. + if (is_arg_max) { + reference_ops::ArgMinMax(input1_shape, input1_data, input2_data, + output_shape, output_data, + reference_ops::GreaterFn); + } else { + reference_ops::ArgMinMax(input1_shape, input1_data, input2_data, + output_shape, output_data, + reference_ops::LessFn); + } +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node, bool is_arg_max) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* axis = + tflite::micro::GetEvalInput(context, node, kAxis); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + +#define TF_LITE_ARG_MIN_MAX(data_type, axis_type, output_type) \ + ArgMinMaxHelper(tflite::micro::GetTensorShape(input), \ + tflite::micro::GetTensorData(input), \ + tflite::micro::GetTensorData(axis), \ + tflite::micro::GetTensorShape(output), \ + tflite::micro::GetTensorData(output), \ + is_arg_max) + if (axis->type == kTfLiteInt32) { + if (output->type == kTfLiteInt32) { + switch (input->type) { + case kTfLiteFloat32: + TF_LITE_ARG_MIN_MAX(float, int32_t, int32_t); + break; + case kTfLiteInt8: + TF_LITE_ARG_MIN_MAX(int8_t, int32_t, int32_t); + break; + default: + MicroPrintf( + "Only float32, uint8_t and int8_t are " + "supported currently, got %s.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + } else { + MicroPrintf("Only int32_t are supported currently, got %s.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else { + MicroPrintf("Only int32_t are supported currently, got %s.", + TfLiteTypeGetName(axis->type)); + return kTfLiteError; + } + +#undef TF_LITE_ARG_MIN_MAX + + return kTfLiteOk; +} + +TfLiteStatus ArgMinEval(TfLiteContext* context, TfLiteNode* node) { + return Eval(context, node, false); +} + +TfLiteStatus ArgMaxEval(TfLiteContext* context, TfLiteNode* node) { + return Eval(context, node, true); +} + +} // namespace + +TfLiteRegistration Register_ARG_MAX() { + return tflite::micro::RegisterOp(nullptr, nullptr, ArgMaxEval); +} + +TfLiteRegistration Register_ARG_MIN() { + return tflite::micro::RegisterOp(nullptr, nullptr, ArgMinEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/assign_variable.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/assign_variable.cpp new file mode 100644 index 0000000..e650294 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/assign_variable.cpp @@ -0,0 +1,101 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +namespace { + +constexpr int kInputVariableId = 0; +constexpr int kInputValue = 1; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 0); + + // This must be a TfLiteEvalTensor despite this being in Prepare, because + // CreateTensor allocates a temp tensor from the flatbuffer, which does not + // contain the correct ID generated within the VAR_HANDLE op. EvalTensors are + // all allocated during StartModelAllocation which happens before + // init/prepare, and VAR_HANDLE Prepare() references its own op_data in the + // TfLiteEvalTensor, so reading the ID here is valid. + const TfLiteEvalTensor* input_resource_id_tensor = + tflite::micro::GetEvalInput(context, node, kInputVariableId); + TFLITE_DCHECK(input_resource_id_tensor != nullptr); + TF_LITE_ENSURE(context, (input_resource_id_tensor->type == kTfLiteResource || + input_resource_id_tensor->type == kTfLiteInt32)); + TF_LITE_ENSURE_EQ(context, NumElements(input_resource_id_tensor->dims), 1); + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + TfLiteTensor* input_value = + micro_context->AllocateTempInputTensor(node, kInputValue); + TFLITE_DCHECK(input_value != nullptr); + + MicroGraph& graph_info = micro_context->graph(); + + MicroResourceVariables* resources = graph_info.GetResourceVariables(); + TF_LITE_ENSURE_OK(context, + resources->Allocate(input_resource_id_tensor->data.i32[0], + context, input_value)); + + micro_context->DeallocateTempTfLiteTensor(input_value); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input_id = + tflite::micro::GetEvalInput(context, node, kInputVariableId); + TFLITE_DCHECK(input_id != nullptr); + + const TfLiteEvalTensor* input_value = + tflite::micro::GetEvalInput(context, node, kInputValue); + TFLITE_DCHECK(input_value != nullptr); + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + MicroGraph& graph_info = micro_context->graph(); + + MicroResourceVariables* resources = graph_info.GetResourceVariables(); + if (resources == nullptr) { + MicroPrintf( + "ASSIGN_VARIABLE requires resource variables. Please create " + "ResourceVariables and pass it to the interpreter."); + return kTfLiteError; + } + TF_LITE_ENSURE_OK(context, + resources->Assign(input_id->data.i32[0], input_value)); + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_ASSIGN_VARIABLE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/batch_matmul.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/batch_matmul.cpp new file mode 100644 index 0000000..3858f73 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/batch_matmul.cpp @@ -0,0 +1,644 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_matmul.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { +namespace { + +constexpr int kInputLHSTensor = 0; +constexpr int kInputRHSTensor = 1; +constexpr int kOutputTensor = 0; + +constexpr int kInvalidScratchBufferIndex = -1; + +struct QuantizationOpData { + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t output_multiplier; + int output_shift; // exponent + + // The range of the fused activation layer. For example for kNone and + // int8_t these would be -128 and 127. + int32_t output_activation_min; + int32_t output_activation_max; + + int32_t lhs_zero_point; + int32_t rhs_zero_point; + int32_t output_zero_point; +}; + +struct HybridOpData { + float filter_scale; // RHS tensor scale + + // scratch buffer indices + int input_quantized_index; + int scaling_factors_index; + int input_offsets_index; + + // row_sums_buffer may be re-used across eval calls + int32_t* row_sums_buffer; + + bool compute_row_sums; +}; + +struct OpData { + union { + QuantizationOpData* quantization; + HybridOpData* hybrid; + }; + + // Transpose tensors and state + TfLiteEvalTensor* lhs_transposed_tensor; + TfLiteEvalTensor* rhs_transposed_tensor; + bool rhs_is_transposed; + bool lhs_is_constant_tensor; + bool rhs_is_constant_tensor; +}; + +struct OpContext { + OpContext(TfLiteContext* context, TfLiteNode* node) { + params = reinterpret_cast(node->builtin_data); + opdata = static_cast(node->user_data); + } + + TfLiteBatchMatMulParams* params; + OpData* opdata; +}; + +struct PrepareOpContext : OpContext { + PrepareOpContext(TfLiteContext* context, TfLiteNode* node) + : OpContext(context, node) { + MicroContext* micro_context = GetMicroContext(context); + lhs = micro_context->AllocateTempInputTensor(node, kInputLHSTensor); + rhs = micro_context->AllocateTempInputTensor(node, kInputRHSTensor); + output = micro_context->AllocateTempOutputTensor(node, kOutputTensor); + } + TfLiteTensor* lhs; + TfLiteTensor* rhs; + TfLiteTensor* output; +}; + +struct EvalOpContext : OpContext { + EvalOpContext(TfLiteContext* context, TfLiteNode* node) + : OpContext(context, node) { + lhs = tflite::micro::GetEvalInput(context, node, kInputLHSTensor); + rhs = tflite::micro::GetEvalInput(context, node, kInputRHSTensor); + output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + } + + const TfLiteEvalTensor* lhs; + const TfLiteEvalTensor* rhs; + TfLiteEvalTensor* output; +}; + +TfLiteStatus ResizeOutputTensor(TfLiteContext* context, TfLiteNode* node, + const RuntimeShape& extended_lhs_shape, + const RuntimeShape& extended_rhs_shape, + bool adj_x, bool adj_y, int output_rank, + TfLiteTensor* output) { + auto orig_size = NumElements(output); + + // make sure output tensor dims are not in the FlatBuffer + TfLiteEvalTensor* output_eval = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE_OK(context, tflite::micro::CreateWritableTensorDimsWithCopy( + context, output, output_eval)); + + // Fill in any broadcast dimensions. + for (int i = 0; i < output_rank - 2; ++i) { + const int lhs_dim = extended_lhs_shape.Dims(i); + const int rhs_dim = extended_rhs_shape.Dims(i); + int broadcast_dim = lhs_dim; + if ((lhs_dim != rhs_dim) && (lhs_dim == 1)) { + broadcast_dim = rhs_dim; + } + output->dims->data[i] = broadcast_dim; + } + // Fill in the matmul dimensions. + int lhs_rows_index = adj_x ? output_rank - 1 : output_rank - 2; + int rhs_cols_index = adj_y ? output_rank - 2 : output_rank - 1; + + output->dims->data[output_rank - 2] = extended_lhs_shape.Dims(lhs_rows_index); + output->dims->data[output_rank - 1] = extended_rhs_shape.Dims(rhs_cols_index); + output->dims->size = output_rank; + + // Check that output tensor has not been resized + // since TFLM doesn't support tensor resizing. + TF_LITE_ENSURE_EQ(context, orig_size, NumElements(output)); + + return kTfLiteOk; +} + +TfLiteEvalTensor* AllocInitTransposeTensorFromTfLiteTensor( + TfLiteContext* context, const TfLiteTensor& tensor) { + TfLiteEvalTensor* eval_tensor = static_cast( + context->AllocatePersistentBuffer(context, sizeof(TfLiteEvalTensor))); + + eval_tensor->type = tensor.type; + + const int tensor_rank = NumDimensions(&tensor); + auto eval_dims_size = TfLiteIntArrayGetSizeInBytes(tensor_rank); + eval_tensor->dims = static_cast( + context->AllocatePersistentBuffer(context, eval_dims_size)); + eval_tensor->dims->size = tensor_rank; + for (int i = 0; i < tensor_rank - 2; ++i) { + eval_tensor->dims->data[i] = tensor.dims->data[i]; + } + // Swap last two dimensions. + eval_tensor->dims->data[tensor_rank - 2] = tensor.dims->data[tensor_rank - 1]; + eval_tensor->dims->data[tensor_rank - 1] = tensor.dims->data[tensor_rank - 2]; + + size_t eval_data_size = static_cast(NumElements(&tensor)); + if (tensor.type == kTfLiteFloat32) { + eval_data_size *= sizeof(float); + } + eval_tensor->data.data = + context->AllocatePersistentBuffer(context, eval_data_size); + + return eval_tensor; +} + +// Initializes tensors to store transposed operands. +// Allocate storage for hybrid quantization if needed. +// Allocate normal quantization data if needed. +TfLiteStatus InitializeTemporaries(TfLiteContext* context, TfLiteNode* node, + const PrepareOpContext& op_context) { + OpData* op_data = op_context.opdata; + const TfLiteTensor* lhs = op_context.lhs; + const TfLiteTensor* rhs = op_context.rhs; + + // For "hybrid" quantization, we impose the constraint that the LHS + // is float (typically an activation from a prior layer) and the RHS + // is quantized int8. + bool is_hybrid = (lhs->type == kTfLiteFloat32 && rhs->type == kTfLiteInt8); + if (is_hybrid) { + op_data->hybrid = static_casthybrid)>( + context->AllocatePersistentBuffer(context, sizeof(*op_data->hybrid))); + TF_LITE_ENSURE(context, op_data->hybrid != nullptr); + op_data->hybrid->input_quantized_index = kInvalidScratchBufferIndex; + op_data->hybrid->scaling_factors_index = kInvalidScratchBufferIndex; + op_data->hybrid->row_sums_buffer = nullptr; + op_data->hybrid->input_offsets_index = kInvalidScratchBufferIndex; + } else if (lhs->type == kTfLiteInt8) { + op_data->quantization = static_castquantization)>( + context->AllocatePersistentBuffer(context, + sizeof(*op_data->quantization))); + TF_LITE_ENSURE(context, op_data->quantization != nullptr); + } else { + op_data->quantization = nullptr; // also op_data->hybrid + } + + // tensor for Transposed LHS; + if (op_context.params->adj_x) { + op_data->lhs_transposed_tensor = + AllocInitTransposeTensorFromTfLiteTensor(context, *lhs); + } else { + op_data->lhs_transposed_tensor = nullptr; + } + + // We need a buffer for the RHS if we need to transpose the RHS. We + // transpose by default, so that the two inputs (LHS and RHS) are in a proper + // layout for our fast matrix multiplication routines. If the transpose flag + // is set by the caller, the data is already in the desired layout. + if (!op_context.params->adj_y) { + op_data->rhs_transposed_tensor = + AllocInitTransposeTensorFromTfLiteTensor(context, *rhs); + } else { + op_data->rhs_transposed_tensor = nullptr; + } + + // If we have to perform on-the-fly quantization (with quantized weights and + // float inputs) first we need to quantize the inputs. Allocate temporary + // buffer to store the intermediate quantized values, the batch scaling + // factors, the input offsets, and persistent storage for the sums of the + // rows for each weights matrix. + // RHS = weights, LHS = inputs + if (is_hybrid) { + const int lhs_rank = NumDimensions(lhs); + const int rhs_rank = NumDimensions(rhs); + const int batch_size = op_context.params->adj_x + ? lhs->dims->data[lhs_rank - 1] + : lhs->dims->data[lhs_rank - 2]; + const int num_units = rhs->dims->data[rhs_rank - 1]; + + // Calculate the total number of LHS batches. + int num_batches = 1; + for (int i = 0; i < lhs_rank - 2; ++i) { + num_batches *= lhs->dims->data[i]; + } + int num_weights_matrices = 1; + for (int i = 0; i < rhs_rank - 2; ++i) { + num_weights_matrices *= rhs->dims->data[i]; + } + + const size_t input_quantized_size = static_cast( + NumElements(lhs->dims) * TfLiteTypeGetSize(rhs->type)); + TF_LITE_ENSURE_OK(context, context->RequestScratchBufferInArena( + context, input_quantized_size, + &op_data->hybrid->input_quantized_index)); + + const size_t scaling_factors_size = + static_cast(batch_size * num_batches * sizeof(float)); + TF_LITE_ENSURE_OK(context, context->RequestScratchBufferInArena( + context, scaling_factors_size, + &op_data->hybrid->scaling_factors_index)); + + const size_t input_offsets_size = + static_cast(batch_size * num_batches * sizeof(int32_t)); + TF_LITE_ENSURE_OK(context, context->RequestScratchBufferInArena( + context, input_offsets_size, + &op_data->hybrid->input_offsets_index)); + + const size_t row_sums_size = + static_cast(num_weights_matrices * num_units * sizeof(int32_t)); + op_data->hybrid->row_sums_buffer = static_cast( + context->AllocatePersistentBuffer(context, row_sums_size)); + TF_LITE_ENSURE(context, op_data->hybrid->row_sums_buffer != nullptr); + + op_data->hybrid->compute_row_sums = true; + op_data->hybrid->filter_scale = rhs->params.scale; + } + + return kTfLiteOk; +} + +template +void TransposeRowsColumnsImpl(const TfLiteEvalTensor& tensor_in, + const scalar* input, TfLiteEvalTensor* tensor_out, + scalar* output) { + RuntimeShape transposed_shape(tflite::micro::GetTensorShape(&tensor_in)); + RuntimeShape shape(transposed_shape); + TransposeParams params; + int rank = shape.DimensionsCount(); + params.perm_count = rank; + for (int i = 0; i < rank - 2; ++i) { + params.perm[i] = i; + } + // Transpose the last two dimensions. + params.perm[rank - 2] = rank - 1; + params.perm[rank - 1] = rank - 2; + transposed_shape.SetDim(rank - 1, shape.Dims(rank - 2)); + transposed_shape.SetDim(rank - 2, shape.Dims(rank - 1)); + reference_ops::Transpose(params, shape, input, transposed_shape, output); +} + +TfLiteStatus TransposeRowsColumns(TfLiteContext* context, + const TfLiteEvalTensor& tensor_in, + TfLiteEvalTensor* tensor_out) { + if (tensor_in.type == kTfLiteFloat32) { + TransposeRowsColumnsImpl( + tensor_in, tflite::micro::GetTensorData(&tensor_in), tensor_out, + tflite::micro::GetTensorData(tensor_out)); + return kTfLiteOk; + } else if (tensor_in.type == kTfLiteInt8) { + TransposeRowsColumnsImpl( + tensor_in, tflite::micro::GetTensorData(&tensor_in), tensor_out, + tflite::micro::GetTensorData(tensor_out)); + return kTfLiteOk; + } else { + TF_LITE_KERNEL_LOG(context, + "BATCH_MATMUL can only transpose tensors with float, " + "int8 type."); + return kTfLiteError; + } +} + +RuntimeShape SwapRowColumnDims(const RuntimeShape& shape) { + RuntimeShape swapped_shape(shape); + const int32_t dims = shape.DimensionsCount(); + swapped_shape.SetDim(dims - 2, shape.Dims(dims - 1)); + swapped_shape.SetDim(dims - 1, shape.Dims(dims - 2)); + return swapped_shape; +} + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + PrepareOpContext op_context(context, node); + const TfLiteTensor* lhs_data = op_context.lhs; + TF_LITE_ENSURE(context, lhs_data != nullptr); + const TfLiteTensor* rhs_data = op_context.rhs; + TF_LITE_ENSURE(context, rhs_data != nullptr); + TfLiteTensor* output = op_context.output; + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE(context, lhs_data->type == kTfLiteFloat32 || + lhs_data->type == kTfLiteInt8); + TF_LITE_ENSURE(context, rhs_data->type == kTfLiteFloat32 || + rhs_data->type == kTfLiteInt8); + // Either we have a hybrid quantization with a float32 and an int8 input, + // otherwise both inputs should be of the same type. + TF_LITE_ENSURE(context, (lhs_data->type == kTfLiteFloat32 && + rhs_data->type == kTfLiteInt8) || + lhs_data->type == rhs_data->type); + + const int lhs_rank = NumDimensions(lhs_data); + const int rhs_rank = NumDimensions(rhs_data); + // Support dimensions between 2 and 4, inclusive. + TF_LITE_ENSURE(context, lhs_rank >= 2); + TF_LITE_ENSURE(context, lhs_rank <= 4); + TF_LITE_ENSURE(context, rhs_rank >= 2); + TF_LITE_ENSURE(context, rhs_rank <= 4); + + TF_LITE_ENSURE_OK(context, InitializeTemporaries(context, node, op_context)); + + OpData* op_data = op_context.opdata; + // If the RHS is constant, we only transpose once. + op_data->rhs_is_transposed = false; + op_data->lhs_is_constant_tensor = IsConstantTensor(lhs_data); + op_data->rhs_is_constant_tensor = IsConstantTensor(rhs_data); + + bool adj_x = op_context.params->adj_x; + bool adj_y = op_context.params->adj_y; + + // Note that quantized inference requires that all tensors have their + // parameters set. This is usually done during quantized training. + if (lhs_data->type == kTfLiteInt8) { + TF_LITE_ENSURE(context, op_data->quantization != nullptr); + double real_multiplier = 0.0; + TF_LITE_ENSURE_STATUS(GetQuantizedConvolutionMultipler( + context, lhs_data, rhs_data, output, &real_multiplier)); + QuantizeMultiplier(real_multiplier, + &op_data->quantization->output_multiplier, + &op_data->quantization->output_shift); + // BatchMatMul has no fused activation functions. Therefore, set + // output activation min and max to min and max of int8_t type. + op_data->quantization->output_activation_min = + std::numeric_limits::min(); + op_data->quantization->output_activation_max = + std::numeric_limits::max(); + + // set zero_point for Int8 only + op_data->quantization->lhs_zero_point = lhs_data->params.zero_point; + op_data->quantization->rhs_zero_point = rhs_data->params.zero_point; + op_data->quantization->output_zero_point = output->params.zero_point; + } + + const int output_rank = std::max(lhs_rank, rhs_rank); + const RuntimeShape extended_lhs_shape = + RuntimeShape::ExtendedShape(output_rank, GetTensorShape(lhs_data)); + const RuntimeShape extended_rhs_shape = + RuntimeShape::ExtendedShape(output_rank, GetTensorShape(rhs_data)); + + // Ensure any batch dimensions obey broacasting rules. + for (int i = 0; i < output_rank - 2; ++i) { + const int lhs_dim = extended_lhs_shape.Dims(i); + const int rhs_dim = extended_rhs_shape.Dims(i); + if (lhs_dim != rhs_dim) { + if (lhs_dim != 1) { + TF_LITE_ENSURE_EQ(context, rhs_dim, 1); + } + } + } + // Ensure other dimensions work for matrix multiplication. + int accum_dim_lhs = adj_x ? extended_lhs_shape.Dims(output_rank - 2) + : extended_lhs_shape.Dims(output_rank - 1); + int accum_dim_rhs = adj_y ? extended_rhs_shape.Dims(output_rank - 1) + : extended_rhs_shape.Dims(output_rank - 2); + + TF_LITE_ENSURE_EQ(context, accum_dim_lhs, accum_dim_rhs); + TfLiteStatus status = + ResizeOutputTensor(context, node, extended_lhs_shape, extended_rhs_shape, + adj_x, adj_y, output_rank, output); + + micro_context->DeallocateTempTfLiteTensor(op_context.lhs); + micro_context->DeallocateTempTfLiteTensor(op_context.rhs); + micro_context->DeallocateTempTfLiteTensor(op_context.output); + + return status; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + // This is a builtin op, so we don't use the contents in 'buffer', if any. + // Instead, we allocate a new object to carry information from Prepare() to + // Eval(). + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +TfLiteStatus EvalHybrid(TfLiteContext* context, TfLiteNode* node, + const OpData& data, const RuntimeShape& input_shape, + const TfLiteEvalTensor& input, + const RuntimeShape& filter_shape, + const TfLiteEvalTensor& filter, + TfLiteEvalTensor* output) { + const auto* params = + static_cast(node->builtin_data); + const int32_t num_input_dims = input_shape.DimensionsCount(); + + // Input row/cols have been swapped at this point, so dims are + // {input_size, num_batches} + const int input_size = input_shape.Dims(num_input_dims - 2); + const int batch_size = input_shape.Dims(num_input_dims - 1); + + int num_batches_to_quantize = batch_size; + for (int i = 0; i < input_shape.DimensionsCount() - 2; ++i) { + num_batches_to_quantize *= input_shape.Dims(i); + } + // Quantize input from float to uint8 + quantization params (scaling factor). + float* scaling_factors_ptr = static_cast( + context->GetScratchBuffer(context, data.hybrid->scaling_factors_index)); + int32_t* input_offset_ptr = static_cast( + context->GetScratchBuffer(context, data.hybrid->input_offsets_index)); + int32_t* row_sums_ptr = data.hybrid->row_sums_buffer; + if (!params->asymmetric_quantize_inputs) { + std::fill_n(input_offset_ptr, num_batches_to_quantize, 0); + } + + int8_t* quant_data = static_cast( + context->GetScratchBuffer(context, data.hybrid->input_quantized_index)); + const int8_t* filter_data = tflite::micro::GetTensorData(&filter); + const float* input_ptr = tflite::micro::GetTensorData(&input); + // Quantize each batch independently. + tensor_utils::BatchQuantizeFloats(input_ptr, num_batches_to_quantize, + input_size, quant_data, scaling_factors_ptr, + input_offset_ptr, + params->asymmetric_quantize_inputs); + for (int b = 0; b < num_batches_to_quantize; ++b) { + // Incorporate scaling of the filter. + scaling_factors_ptr[b] *= data.hybrid->filter_scale; + } + + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + int output_size = NumElements(output->dims); + std::fill_n(tflite::micro::GetTensorData(output), output_size, 0.0f); + reference_ops::BatchMatMul( + filter_shape, filter_data, input_shape, quant_data, scaling_factors_ptr, + input_offset_ptr, row_sums_ptr, tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + &(data.hybrid->compute_row_sums)); + + return kTfLiteOk; +} + +TfLiteStatus EvalInt8(TfLiteContext* context, const OpData& data, + const RuntimeShape& lhs_shape, + const TfLiteEvalTensor& lhs, + const RuntimeShape& rhs_shape, + const TfLiteEvalTensor& rhs, + const RuntimeShape& output_shape, + TfLiteEvalTensor* output) { + TF_LITE_ENSURE(context, data.quantization != nullptr); + + // Reuse params struct from FullyConnected Op. + FullyConnectedParams op_params; + op_params.input_offset = -data.quantization->lhs_zero_point; + op_params.weights_offset = + -data.quantization->rhs_zero_point; // filter offset + op_params.output_offset = data.quantization->output_zero_point; + op_params.output_multiplier = data.quantization->output_multiplier; + op_params.output_shift = data.quantization->output_shift; + op_params.quantized_activation_min = data.quantization->output_activation_min; + op_params.quantized_activation_max = data.quantization->output_activation_max; + op_params.lhs_cacheable = data.lhs_is_constant_tensor; + op_params.rhs_cacheable = data.rhs_is_constant_tensor; + + // Note we pass RHS args first, LHS args second. See note for Eval. + reference_ops::BatchMatMul( + op_params, rhs_shape, tflite::micro::GetTensorData(&rhs), + lhs_shape, tflite::micro::GetTensorData(&lhs), output_shape, + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; +} + +TfLiteStatus EvalQuantized(TfLiteContext* context, TfLiteNode* node, + const OpData& data, const RuntimeShape& lhs_shape, + const TfLiteEvalTensor& lhs, + const RuntimeShape& rhs_shape, + const TfLiteEvalTensor& rhs, + TfLiteEvalTensor* output) { + if (lhs.type == kTfLiteFloat32 && rhs.type == kTfLiteInt8) { + TF_LITE_ENSURE(context, data.hybrid != nullptr); + TF_LITE_ENSURE(context, data.hybrid->row_sums_buffer != nullptr); + TF_LITE_ENSURE(context, data.hybrid->input_quantized_index != + kInvalidScratchBufferIndex); + TF_LITE_ENSURE(context, data.hybrid->scaling_factors_index != + kInvalidScratchBufferIndex); + TF_LITE_ENSURE(context, data.hybrid->input_offsets_index != + kInvalidScratchBufferIndex); + return EvalHybrid(context, node, data, lhs_shape, lhs, rhs_shape, rhs, + output); + } else if (lhs.type == kTfLiteInt8 && rhs.type == kTfLiteInt8) { + return EvalInt8(context, data, lhs_shape, lhs, rhs_shape, rhs, + tflite::micro::GetTensorShape(output), output); + } else { + TF_LITE_KERNEL_LOG( + context, "BATCH_MATMUL only supports hybrid, int8 quantization.\n"); + } + return kTfLiteError; +} + +// Perform a batch matrix multiply on +// LHS <..., A, B> X RHS<..., B, C> +// where the leading dimensions of LHS and RHS obey broadcasting rules +// (this Op will apply broadcasting rules). +// We assume that LHS and RHS are both row oriented (adjacent values in memory +// are in the same row) and will output in the same memory layout. However, +// our fast GEMM libraries assume RCC layout (LHS row oriented, +// RHS column oriented, output column oriented). Therefore, we perform +// RHS <..., C, B> X LHS <..., B, A> +// where output is a C X A column-oriented, which is equivalent to +// A X C row-oriented. +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + EvalOpContext op_context(context, node); + OpData* op_data = op_context.opdata; + const TfLiteEvalTensor* lhs = op_context.lhs; + const TfLiteEvalTensor* rhs = op_context.rhs; + TfLiteEvalTensor* output = op_context.output; + RuntimeShape orig_lhs_shape = tflite::micro::GetTensorShape(lhs); + RuntimeShape orig_rhs_shape = tflite::micro::GetTensorShape(rhs); + + bool adj_y = op_context.params->adj_y; + bool adj_x = op_context.params->adj_x; + + TfLiteEvalTensor* rhs_tensor = adj_y ? const_cast(rhs) + : op_data->rhs_transposed_tensor; + TfLiteEvalTensor* lhs_tensor = adj_x ? op_data->lhs_transposed_tensor + : const_cast(lhs); + TF_LITE_ENSURE(context, rhs_tensor != nullptr); + TF_LITE_ENSURE(context, lhs_tensor != nullptr); + if (!adj_y) { + // OLD-TODO(b/154760341) Constant tensors should already be transposed, but + // we transpose once if necessary for now. + if (!(op_data->rhs_is_constant_tensor && op_data->rhs_is_transposed)) { + TransposeRowsColumns(context, *rhs, rhs_tensor); + op_data->rhs_is_transposed = true; + } + } + if (adj_x) { + TransposeRowsColumns(context, *lhs, lhs_tensor); + } + RuntimeShape rhs_shape = + adj_y ? orig_rhs_shape : SwapRowColumnDims(orig_rhs_shape); + RuntimeShape lhs_shape = + adj_x ? orig_lhs_shape : SwapRowColumnDims(orig_lhs_shape); + + switch (rhs->type) { + case kTfLiteFloat32: + // Note we pass RHS args first, LHS args second. See note above. + reference_ops::BatchMatMul( + rhs_shape, tflite::micro::GetTensorData(rhs_tensor), lhs_shape, + tflite::micro::GetTensorData(lhs_tensor), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: + return EvalQuantized(context, node, *op_data, lhs_shape, *lhs_tensor, + rhs_shape, *rhs_tensor, output); + default: + TF_LITE_KERNEL_LOG(context, + "Currently BATCH_MATMUL doesn't support type: %s", + TfLiteTypeGetName(lhs->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_BATCH_MATMUL() { + return {/*init=*/Init, + /*free=*/nullptr, + /*prepare=*/Prepare, + /*invoke=*/Eval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/batch_to_space_nd.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/batch_to_space_nd.cpp new file mode 100644 index 0000000..9959e47 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/batch_to_space_nd.cpp @@ -0,0 +1,112 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/batch_to_space_nd.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kBlockShapeTensor = 1; +constexpr int kCropsTensor = 2; +constexpr int kOutputTensor = 0; + +// Currently, only 3D NHC and 4D NHWC input/output op_context are supported. +// In case of 3D input, it will be extended to 3D NHWC by adding W=1. +// The 4D array need to have exactly 2 spatial dimensions. +// TODO(b/149952582): Support arbitrary dimension in SpaceToBatchND. +const int kInputOutputMinDimensionNum = 3; +const int kInputOutputMaxDimensionNum = 4; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 3); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, input != nullptr && output != nullptr); + + TF_LITE_ENSURE(context, NumDimensions(input) >= kInputOutputMinDimensionNum); + TF_LITE_ENSURE(context, NumDimensions(output) >= kInputOutputMinDimensionNum); + TF_LITE_ENSURE(context, NumDimensions(input) <= kInputOutputMaxDimensionNum); + TF_LITE_ENSURE(context, NumDimensions(output) <= kInputOutputMaxDimensionNum); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* block_shape = + tflite::micro::GetEvalInput(context, node, kBlockShapeTensor); + const TfLiteEvalTensor* crops = + tflite::micro::GetEvalInput(context, node, kCropsTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: + reference_ops::BatchToSpaceND( + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(block_shape), + tflite::micro::GetTensorData(block_shape), + tflite::micro::GetTensorShape(crops), + tflite::micro::GetTensorData(crops), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: + reference_ops::BatchToSpaceND( + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(block_shape), + tflite::micro::GetTensorData(block_shape), + tflite::micro::GetTensorShape(crops), + tflite::micro::GetTensorData(crops), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_BATCH_TO_SPACE_ND() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/broadcast_args.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/broadcast_args.cpp new file mode 100644 index 0000000..002a192 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/broadcast_args.cpp @@ -0,0 +1,91 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_args.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" + +namespace tflite { +namespace { +constexpr int kShape1Tensor = 0; +constexpr int kShape2Tensor = 1; +constexpr int kOutputTensor = 0; + +TfLiteStatus BroadcastArgsPrepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE(context, NumInputs(node) == 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* shape1 = + micro_context->AllocateTempInputTensor(node, kShape1Tensor); + TfLiteTensor* shape2 = + micro_context->AllocateTempInputTensor(node, kShape2Tensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + TF_LITE_ENSURE(context, + shape1->type == kTfLiteInt32 || shape1->type == kTfLiteInt64); + TF_LITE_ENSURE_EQ(context, shape1->type, shape2->type); + TF_LITE_ENSURE_EQ(context, shape1->type, output->type); + + // Ensures the shapes are 1D tensor. + TF_LITE_ENSURE_EQ(context, NumDimensions(shape1), 1); + TF_LITE_ENSURE_EQ(context, NumDimensions(shape2), 1); + + // Ensure the shape of the output tensor is compatible + TF_LITE_ENSURE_EQ(context, NumDimensions(output), 1); + + micro_context->DeallocateTempTfLiteTensor(shape1); + micro_context->DeallocateTempTfLiteTensor(shape2); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus BroadcastArgsEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* shape1 = + micro::GetEvalInput(context, node, kShape1Tensor); + const TfLiteEvalTensor* shape2 = + micro::GetEvalInput(context, node, kShape2Tensor); + TfLiteEvalTensor* output = micro::GetEvalOutput(context, node, kOutputTensor); + + if (output->type == kTfLiteInt32) { + reference_ops::BroadcastArgs( + micro::GetTensorShape(shape1), micro::GetTensorData(shape1), + micro::GetTensorShape(shape2), micro::GetTensorData(shape2), + micro::GetTensorShape(output), micro::GetTensorData(output)); + } else { + reference_ops::BroadcastArgs( + micro::GetTensorShape(shape1), micro::GetTensorData(shape1), + micro::GetTensorShape(shape2), micro::GetTensorData(shape2), + micro::GetTensorShape(output), micro::GetTensorData(output)); + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_BROADCAST_ARGS() { + return tflite::micro::RegisterOp(nullptr, BroadcastArgsPrepare, + BroadcastArgsEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/broadcast_to.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/broadcast_to.cpp new file mode 100644 index 0000000..51b19e0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/broadcast_to.cpp @@ -0,0 +1,123 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/broadcast_to.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" + +namespace tflite { + +namespace { +constexpr int kInputTensor = 0; +constexpr int kShapeTensor = 1; +constexpr int kOutputTensor = 0; +// Support a maximum of 5 dimensions in TFLM. +constexpr int kMaxDims = 5; + +TfLiteStatus ValidateOutputTensor(TfLiteContext* context, TfLiteTensor* input, + TfLiteTensor* shape, TfLiteTensor* output) { + // Ensures the shape is 1D tensor. + TF_LITE_ENSURE_EQ(context, NumDimensions(shape), 1); + + // Ensure output dims is not less than input dims. + int input_num_dims = NumDimensions(input); + int output_num_dims = NumDimensions(output); + int shape_num_dims = SizeOfDimension(shape, 0); + TF_LITE_ENSURE_MSG(context, output_num_dims == shape_num_dims, + "Output must match with the expected shape dimension."); + TF_LITE_ENSURE_MSG(context, input_num_dims <= output_num_dims, + "Output shape must be broadcastable from input shape."); + TF_LITE_ENSURE_MSG(context, output_num_dims <= kMaxDims, + "BroadcastTo only supports 1-5D tensor."); + + // Check if output shape is broadcastable from input shape. + auto get_shape_data = [shape](int i) -> int32_t { + if (shape->type == kTfLiteInt32) { + return GetTensorData(shape)[i]; + } else { + return GetTensorData(shape)[i]; + } + }; + + int extending_dims = output_num_dims - input_num_dims; + for (int idx = 0; idx < input_num_dims; ++idx) { + TF_LITE_ENSURE_MSG( + context, + (SizeOfDimension(input, idx) == 1 || + SizeOfDimension(input, idx) == get_shape_data(extending_dims + idx)), + "Output shape must be broadcastable from input shape."); + } + + // Validating the shape of the output tensor. + tflite::RuntimeShape output_shape = tflite::GetTensorShape(output); + for (int idx = 0; idx < output_num_dims; ++idx) { + TF_LITE_ENSURE(context, output_shape.Dims(idx) == get_shape_data(idx)); + } + return kTfLiteOk; +} + +TfLiteStatus BroadcastToPrepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE(context, NumInputs(node) == 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* shape = + micro_context->AllocateTempInputTensor(node, kShapeTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + TF_LITE_ENSURE_MSG(context, (NumDimensions(input) <= kMaxDims), + "BroadcastTo only supports 1-5D tensor."); + + TF_LITE_ENSURE(context, + shape->type == kTfLiteInt32 || shape->type == kTfLiteInt64); + TF_LITE_ENSURE_EQ(context, input->type, output->type); + + // Does not support String type due to its variable size. This limitation is + // the same as TFLite. + TF_LITE_ENSURE(context, input->type != kTfLiteString); + + TF_LITE_ENSURE_STATUS(ValidateOutputTensor(context, input, shape, output)); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(shape); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus BroadcastToEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = micro::GetEvalOutput(context, node, kOutputTensor); + + // BroadcastTo op support upto 5 dims, different from 8 dims in TFLite. + reference_ops::BroadcastTo( + micro::GetTensorShape(input), input->data.raw, + micro::GetTensorShape(output), output->data.raw, input->type); + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration Register_BROADCAST_TO() { + return tflite::micro::RegisterOp(nullptr, BroadcastToPrepare, + BroadcastToEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/call_once.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/call_once.cpp new file mode 100644 index 0000000..21643c8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/call_once.cpp @@ -0,0 +1,88 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +namespace { + +struct OpData { + int init_subgraph_index; + bool has_run; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + OpData* op_data = reinterpret_cast(node->user_data); + const auto* params = + reinterpret_cast(node->builtin_data); + op_data->init_subgraph_index = params->init_subgraph_index; + op_data->has_run = false; + + TF_LITE_ENSURE(context, NumInputs(node) == 0); + TF_LITE_ENSURE(context, NumOutputs(node) == 0); + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + MicroGraph& graph_info = micro_context->graph(); + + TF_LITE_ENSURE(context, + op_data->init_subgraph_index < graph_info.NumSubgraphs()); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + OpData* op_data = reinterpret_cast(node->user_data); + + // Call once only runs one time then is a no-op for every subsequent call. + if (op_data->has_run) { + return kTfLiteOk; + } + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + MicroGraph& graph_info = micro_context->graph(); + + TF_LITE_ENSURE_OK(context, + graph_info.InvokeSubgraph(op_data->init_subgraph_index)); + + op_data->has_run = true; + + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_CALL_ONCE() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/cast.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/cast.cpp new file mode 100644 index 0000000..19e545f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/cast.cpp @@ -0,0 +1,114 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +template +void copyCast(const FromT* in, ToT* out, int num_elements) { + std::transform(in, in + num_elements, out, + [](FromT a) { return static_cast(a); }); +} + +template +TfLiteStatus copyToTensor(TfLiteContext* context, const FromT* in, + TfLiteEvalTensor* out, int num_elements) { + switch (out->type) { + case kTfLiteInt8: + copyCast(in, out->data.int8, num_elements); + break; + case kTfLiteInt16: + copyCast(in, out->data.i16, num_elements); + break; + case kTfLiteInt32: + copyCast(in, out->data.i32, num_elements); + break; + case kTfLiteFloat32: + copyCast(in, tflite::micro::GetTensorData(out), num_elements); + break; + default: + // Unsupported type. + MicroPrintf("Output type %s (%d) not supported.", + TfLiteTypeGetName(out->type), out->type); + } + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + int num_elements = MatchingFlatSize(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorShape(output)); + + switch (input->type) { + case kTfLiteInt8: + return copyToTensor(context, input->data.int8, output, num_elements); + case kTfLiteInt16: + return copyToTensor(context, tflite::micro::GetTensorData(input), + output, num_elements); + case kTfLiteInt32: + return copyToTensor(context, tflite::micro::GetTensorData(input), + output, num_elements); + case kTfLiteUInt32: + return copyToTensor(context, + tflite::micro::GetTensorData(input), output, + num_elements); + case kTfLiteFloat32: + return copyToTensor(context, tflite::micro::GetTensorData(input), + output, num_elements); + default: + // Unsupported type. + MicroPrintf("Input type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + } + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration Register_CAST() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ceil.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ceil.cpp new file mode 100644 index 0000000..0f09137 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ceil.cpp @@ -0,0 +1,73 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/ceil.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteFloat32); + TF_LITE_ENSURE_TYPES_EQ(context, output->type, input->type); + TF_LITE_ENSURE_EQ(context, output->bytes, input->bytes); + TF_LITE_ENSURE_EQ(context, output->dims->size, input->dims->size); + for (int i = 0; i < output->dims->size; ++i) { + TF_LITE_ENSURE_EQ(context, output->dims->data[i], input->dims->data[i]); + } + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + reference_ops::Ceil(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_CEIL() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.cpp new file mode 100644 index 0000000..bf69599 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.cpp @@ -0,0 +1,117 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +/* + * The circular buffer custom operator is used to implement strided streaming + * convolutions on TFLite Micro. Each time this operator is invoked, it checks + * whether or not to run, based on a predetermined stride in time. If the op + * runs, it inserts the input into the end of the output buffer and shifts the + * output values towards the start of the buffer. It discards the oldest value + * in the output buffer. + * + * Input: [, , , ] + * + * After shifting: + * Output: [, , , ] + * + * We make some assumptions in this custom operator: + * - Input shape must be [1, 1, 1, depth] + * - Output shape must be [1, num_slots, 1, depth] + * - Input and output types must match. + * - Input and output quantization params must be identical. + */ +namespace tflite { + +void* CircularBufferInit(TfLiteContext* context, const char* buffer, + size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + OpDataCircularBuffer* op_data = static_cast( + context->AllocatePersistentBuffer(context, sizeof(OpDataCircularBuffer))); + + if (buffer != nullptr && length > 0) { + const uint8_t* buffer_t = reinterpret_cast(buffer); + tflite::FlexbufferWrapper wrapper(buffer_t, length); + op_data->cycles_max = wrapper.ElementAsInt32(kCircularBufferCyclesMaxIndex); + } else { + op_data->cycles_max = 0; + } + + return op_data; +} + +// Shifts buffer over by the output depth, and write new input to end of buffer. +// num_slots is the number of samples stored in the output buffer. +// depth is the size of each sample. +void EvalInt8(const int8_t* input, int num_slots, int depth, int8_t* output) { + memmove(output, &output[depth], (num_slots - 1) * depth); + memcpy(&output[(num_slots - 1) * depth], input, depth); +} + +TfLiteStatus CircularBufferEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kCircularBufferInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kCircularBufferOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + OpDataCircularBuffer* data = + reinterpret_cast(node->user_data); + + int num_slots = output->dims->data[1]; + int depth = output->dims->data[2] * output->dims->data[3]; + + if (input->type == kTfLiteInt8) { + EvalInt8(tflite::micro::GetTensorData(input), num_slots, depth, + tflite::micro::GetTensorData(output)); + } else { + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + + if (--data->cycles_until_run != 0) { + // Signal the interpreter to end current run if the delay before op invoke + // has not been reached. + // TODO(b/149795762): Add kTfLiteAbort to TfLiteStatus enum. + return static_cast(kTfLiteAbort); + } + + data->cycles_until_run = data->cycles_max; + + return kTfLiteOk; +} + +TfLiteRegistration* Register_CIRCULAR_BUFFER() { + static TfLiteRegistration r = tflite::micro::RegisterOp( + CircularBufferInit, CircularBufferPrepare, CircularBufferEval); + return &r; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.h new file mode 100644 index 0000000..c52a1ec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.h @@ -0,0 +1,48 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_CIRCULAR_BUFFER_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_CIRCULAR_BUFFER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +// The CircularBuffer op has one input and one output tensor. +extern const int kCircularBufferInputTensor; +extern const int kCircularBufferOutputTensor; + +// Indices into the init flexbuffer's vector. +// The parameter's name is in the comment that follows. +// Elements in the vectors are ordered alphabetically by parameter name. +extern const int kCircularBufferCyclesMaxIndex; // 'cycles_max' + +// TODO(b/149795762): Add this to TfLiteStatus enum. +extern const TfLiteStatus kTfLiteAbort; + +// These fields control the stride period of a strided streaming model. This op +// returns kTfLiteAbort until cycles_until_run-- is zero. At this time, +// cycles_until_run is reset to cycles_max. +struct OpDataCircularBuffer { + int cycles_until_run; + int cycles_max; +}; + +TfLiteStatus CircularBufferPrepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_CIRCULAR_BUFFER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer_common.cpp new file mode 100644 index 0000000..b6d1f0d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer_common.cpp @@ -0,0 +1,97 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { + +// The CircularBuffer op has one input and one output tensor. +const int kCircularBufferInputTensor = 0; +const int kCircularBufferOutputTensor = 0; + +// Indices into the init flexbuffer's vector. +// The parameter's name is in the comment that follows. +// Elements in the vectors are ordered alphabetically by parameter name. +const int kCircularBufferCyclesMaxIndex = 0; // 'cycles_max' + +// TODO(b/149795762): Add this to TfLiteStatus enum. +const TfLiteStatus kTfLiteAbort = static_cast(-9); + +TfLiteStatus CircularBufferPrepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kCircularBufferInputTensor); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor( + node, kCircularBufferOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + OpDataCircularBuffer* op_data = + static_cast(node->user_data); + + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_EQ(context, input->dims->data[0], output->dims->data[0]); + TF_LITE_ENSURE_EQ(context, 1, input->dims->data[1]); + TF_LITE_ENSURE_EQ(context, input->dims->data[2], output->dims->data[2]); + TF_LITE_ENSURE_EQ(context, output->dims->data[3], input->dims->data[3]); + + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + // The circular buffer custom operator currently only supports int8. + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteInt8); + + if (op_data->cycles_max <= 0) { + // The last circular buffer layer simply accumulates outputs, and does not + // run periodically. + // TODO(b/150001379): Move this special case logic to the tflite flatbuffer. + static int cb_prepare_count = 0; + cb_prepare_count++; + // These checks specifically work for the only two streaming models + // supported on TFLM. They use the shape of the output tensor along with the + // layer number to determine if the circular buffer period should be 1 or 2. + + // These models are outlined int the following documents: + // https://docs.google.com/document/d/1lc_G2ZFhjiKFo02UHjBaljye1xsL0EkfybkaVELEE3Q/edit?usp=sharing + // https://docs.google.com/document/d/1pGc42PuWyrk-Jy1-9qeqtggvsmHr1ifz8Lmqfpr2rKA/edit?usp=sharing + if (output->dims->data[1] == 5 || output->dims->data[1] == 13 || + output->dims->data[1] == 25 || + (cb_prepare_count == 5 && output->dims->data[2] == 2 && + output->dims->data[3] == 96)) { + op_data->cycles_max = 1; + cb_prepare_count = 0; + } else { + op_data->cycles_max = 2; + } + } + op_data->cycles_until_run = op_data->cycles_max; + node->user_data = op_data; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.h new file mode 100644 index 0000000..2fbf4fe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.h @@ -0,0 +1,22 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_FLEXBUFFERS_GENERATED_DATA_H +#define TENSORFLOW_LITE_MICRO_KERNELS_FLEXBUFFERS_GENERATED_DATA_H + +extern const int g_gen_data_size_circular_buffer_config; +extern const unsigned char g_gen_data_circular_buffer_config[]; + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/comparisons.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/comparisons.cpp new file mode 100644 index 0000000..1a8fbb0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/comparisons.cpp @@ -0,0 +1,606 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/comparisons.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +struct OpData { + ComparisonParams params; +}; + +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +TfLiteStatus EqualEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + RuntimeShape input1_shape = tflite::micro::GetTensorShape(input1); + RuntimeShape input2_shape = tflite::micro::GetTensorShape(input2); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + bool* output_data = tflite::micro::GetTensorData(output); + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + switch (input1->type) { + case kTfLiteBool: + requires_broadcast + ? reference_ops::Broadcast4DSlowEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::EqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteFloat32: + requires_broadcast + ? reference_ops::Broadcast4DSlowEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::EqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt32: + requires_broadcast + ? reference_ops::Broadcast4DSlowEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::EqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt64: + requires_broadcast + ? reference_ops::Broadcast4DSlowEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::EqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt8: + requires_broadcast + ? reference_ops::Broadcast4DSlowEqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::EqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +// TODO(renjieliu): Refactor the logic to avoid duplications. +TfLiteStatus NotEqualEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + RuntimeShape input1_shape = tflite::micro::GetTensorShape(input1); + RuntimeShape input2_shape = tflite::micro::GetTensorShape(input2); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + bool* output_data = tflite::micro::GetTensorData(output); + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + switch (input1->type) { + case kTfLiteBool: + requires_broadcast + ? reference_ops::Broadcast4DSlowNotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::NotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteFloat32: + requires_broadcast + ? reference_ops::Broadcast4DSlowNotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::NotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt32: + requires_broadcast + ? reference_ops::Broadcast4DSlowNotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::NotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt64: + requires_broadcast + ? reference_ops::Broadcast4DSlowNotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::NotEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt8: + requires_broadcast + ? reference_ops::Broadcast4DSlowNotEqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::NotEqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus GreaterEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + RuntimeShape input1_shape = tflite::micro::GetTensorShape(input1); + RuntimeShape input2_shape = tflite::micro::GetTensorShape(input2); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + bool* output_data = tflite::micro::GetTensorData(output); + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + switch (input1->type) { + case kTfLiteFloat32: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt32: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt64: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt8: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus GreaterEqualEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + RuntimeShape input1_shape = tflite::micro::GetTensorShape(input1); + RuntimeShape input2_shape = tflite::micro::GetTensorShape(input2); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + bool* output_data = tflite::micro::GetTensorData(output); + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + switch (input1->type) { + case kTfLiteFloat32: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt32: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt64: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt8: + requires_broadcast + ? reference_ops::Broadcast4DSlowGreaterEqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::GreaterEqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus LessEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + RuntimeShape input1_shape = tflite::micro::GetTensorShape(input1); + RuntimeShape input2_shape = tflite::micro::GetTensorShape(input2); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + bool* output_data = tflite::micro::GetTensorData(output); + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + switch (input1->type) { + case kTfLiteFloat32: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt32: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt64: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt8: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus LessEqualEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + RuntimeShape input1_shape = tflite::micro::GetTensorShape(input1); + RuntimeShape input2_shape = tflite::micro::GetTensorShape(input2); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + bool* output_data = tflite::micro::GetTensorData(output); + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + switch (input1->type) { + case kTfLiteFloat32: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt32: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt64: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessEqualNoScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + case kTfLiteInt8: + requires_broadcast + ? reference_ops::Broadcast4DSlowLessEqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data) + : reference_ops::LessEqualWithScaling( + data->params, input1_shape, + tflite::micro::GetTensorData(input1), input2_shape, + tflite::micro::GetTensorData(input2), output_shape, + output_data); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + OpData* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + + if (input1->type == kTfLiteInt8) { + auto input1_offset = -input1->params.zero_point; + auto input2_offset = -input2->params.zero_point; + const int kLeftShift = 8; + + int32_t input1_multiplier; + int input1_shift; + QuantizeMultiplierSmallerThanOneExp( + static_cast(input1->params.scale), &input1_multiplier, + &input1_shift); + int32_t input2_multiplier; + int input2_shift; + QuantizeMultiplierSmallerThanOneExp( + static_cast(input2->params.scale), &input2_multiplier, + &input2_shift); + + data->params.left_shift = kLeftShift; + data->params.input1_offset = input1_offset; + data->params.input1_multiplier = input1_multiplier; + data->params.input1_shift = input1_shift; + data->params.input2_offset = input2_offset; + data->params.input2_multiplier = input2_multiplier; + data->params.input2_shift = input2_shift; + } + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_EQUAL() { + return tflite::micro::RegisterOp(Init, Prepare, EqualEval); +} + +TfLiteRegistration Register_NOT_EQUAL() { + return tflite::micro::RegisterOp(Init, Prepare, NotEqualEval); +} + +TfLiteRegistration Register_GREATER() { + return tflite::micro::RegisterOp(Init, Prepare, GreaterEval); +} + +TfLiteRegistration Register_GREATER_EQUAL() { + return tflite::micro::RegisterOp(Init, Prepare, GreaterEqualEval); +} + +TfLiteRegistration Register_LESS() { + return tflite::micro::RegisterOp(Init, Prepare, LessEval); +} + +TfLiteRegistration Register_LESS_EQUAL() { + return tflite::micro::RegisterOp(Init, Prepare, LessEqualEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/complex_abs.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/complex_abs.cpp new file mode 100644 index 0000000..94a6107 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/complex_abs.cpp @@ -0,0 +1,103 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include +#include +#include +#include + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace complex_abs { + +using std::complex; + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + // Check type and shape of the input tensor + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + if (input->type != kTfLiteComplex64 || output->type != kTfLiteFloat32) { + TF_LITE_KERNEL_LOG(context, "Types input %s (%d), output %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type, + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + + size_t total_input_els = 1; + for (size_t dim_ix = 0; dim_ix < input->dims->size; dim_ix++) { + total_input_els *= input->dims->data[dim_ix]; + } + + for (size_t ix = 0; ix < total_input_els; ix++) { + output->data.f[ix] = sqrt(pow(input->data.c64[ix].re, 2) + pow(input->data.c64[ix].im, 2)); + } + + return kTfLiteOk; +} + +} // namespace complex_abs +} // namespace micro +} // namespace ops + +TfLiteRegistration Register_COMPLEX_ABS() { + return {/*init=*/nullptr, + /*free=*/nullptr, + /*prepare=*/ops::micro::complex_abs::Prepare, + /*invoke=*/ops::micro::complex_abs::Eval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/concatenation.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/concatenation.cpp new file mode 100644 index 0000000..13a5d63 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/concatenation.cpp @@ -0,0 +1,263 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/concatenation.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +// Patched by Edge Impulse +constexpr int RuntimeShape::kMaxSmallSize; + +namespace { + +constexpr int kMaxInputNum = 10; // Maximum number of input tensors +constexpr int kOutputTensor = 0; + +struct OpData { + ConcatenationParams params; +}; + +// Handles negative axis index, coerces to positive index value. +inline int CalculatePositiveAxis(int axis, const TfLiteTensor* output_tensor) { + if (axis >= 0) { + return axis; + } else { + return NumDimensions(output_tensor) + axis; + } +} + +// The following functions are helpers to get tensor data in the format that the +// reference op implementation expects. They provide the same functionality as +// class VectorOfTensors and class VectorOfQuantizedTensors in TFLite. + +// Gets shapes from a list of tensors. +inline void GetAllInputTensorShapes(const TfLiteContext* context, + const TfLiteNode* node, + RuntimeShape all_shapes[kMaxInputNum]) { + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(node != nullptr); + for (int i = 0; i < node->inputs->size; ++i) { + const TfLiteEvalTensor* t = tflite::micro::GetEvalInput(context, node, i); + RuntimeShape shape = tflite::micro::GetTensorShape(t); + all_shapes[i].ReplaceWith(shape.DimensionsCount(), shape.DimsData()); + } +} + +// Get shape pointers from a list of shapes. +inline void GetShapesPointers(const RuntimeShape* shapes, size_t num, + const RuntimeShape* pointers[]) { + for (size_t i = 0; i < num; ++i) { + pointers[i] = &shapes[i]; + } +} + +// Gets data pointers from a list of tensors. +template +inline void GetAllInputTensorData(const TfLiteContext* context, + const TfLiteNode* node, + T* all_data[kMaxInputNum]) { + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(node != nullptr); + for (int i = 0; i < node->inputs->size; ++i) { + const TfLiteEvalTensor* t = tflite::micro::GetEvalInput(context, node, i); + all_data[i] = tflite::micro::GetTensorData(t); + } +} + +template +void EvalUnquantized(TfLiteContext* context, TfLiteNode* node) { + // Collect the shapes and data pointer of input tensors + RuntimeShape inputs_shape[kMaxInputNum]; + const RuntimeShape* inputs_shape_ptr[kMaxInputNum]; + const data_type* inputs_data[kMaxInputNum]; + GetAllInputTensorShapes(context, node, inputs_shape); + GetShapesPointers(inputs_shape, node->inputs->size, inputs_shape_ptr); + GetAllInputTensorData(context, node, inputs_data); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + reference_ops::Concatenation(data->params, inputs_shape_ptr, inputs_data, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + // This function only checks the types. Additional shape validations are + // performed in the reference implementation called during Eval(). + const TfLiteConcatenationParams* params = + reinterpret_cast(node->builtin_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input_tensor = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input_tensor != nullptr); + TfLiteType input_type = input_tensor->type; + TfLiteTensor* output_tensor = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output_tensor != nullptr); + TfLiteType output_type = output_tensor->type; + + micro_context->DeallocateTempTfLiteTensor(input_tensor); + micro_context->DeallocateTempTfLiteTensor(output_tensor); + + // Check activation and input type + TF_LITE_ENSURE_EQ(context, params->activation, kTfLiteActNone); + TF_LITE_ENSURE(context, + input_type == kTfLiteFloat32 || input_type == kTfLiteInt8 || + input_type == kTfLiteInt16 || input_type == kTfLiteInt32 || + input_type == kTfLiteInt64 || input_type == kTfLiteBool); + + // Output type must match input type + TF_LITE_ENSURE_EQ(context, output_type, input_type); + + // This implementation does not support large number of input tensors + const int num_inputs = NumInputs(node); + TF_LITE_ENSURE(context, num_inputs <= kMaxInputNum); + + // Shapes with dimensions >4 are not yet supported with static allocation. + for (int i = 0; i < num_inputs; ++i) { + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, i); + TF_LITE_ENSURE(context, input != nullptr); + int num_dimensions = NumDimensions(input); + + if (num_dimensions > RuntimeShape::kMaxSmallSize) { + MicroPrintf( + "Op Concatenation does not currently support num dimensions > %d " + "Tensor has %d dimensions.", + RuntimeShape::kMaxSmallSize, num_dimensions); + return kTfLiteError; + } + micro_context->DeallocateTempTfLiteTensor(input); + } + + // Calculate OpData. + TFLITE_DCHECK(node->user_data != nullptr); + OpData* data = static_cast(node->user_data); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + switch (output_type) { // Already know in/outtypes are same. + case kTfLiteBool: + case kTfLiteFloat32: + case kTfLiteInt16: + case kTfLiteInt32: + case kTfLiteInt64: { + data->params.axis = CalculatePositiveAxis(params->axis, output); + data->params.inputs_count = node->inputs->size; + break; + } + case kTfLiteInt8: { + data->params.axis = CalculatePositiveAxis(params->axis, output); + data->params.inputs_count = node->inputs->size; + + float* input_scales = + reinterpret_cast(context->AllocatePersistentBuffer( + context, node->inputs->size * sizeof(float))); + + int32_t* input_zero_points = + reinterpret_cast(context->AllocatePersistentBuffer( + context, node->inputs->size * sizeof(int32_t))); + + // Allocate persistent scale and zeropoint buffers. + // Store input scale and zero point values in OpParams: + for (int i = 0; i < node->inputs->size; ++i) { + TfLiteTensor* t = micro_context->AllocateTempInputTensor(node, i); + TF_LITE_ENSURE(context, t != nullptr); + input_scales[i] = t->params.scale; + input_zero_points[i] = t->params.zero_point; + micro_context->DeallocateTempTfLiteTensor(t); + } + + data->params.input_scale = input_scales; + data->params.input_zeropoint = input_zero_points; + data->params.output_zeropoint = output->params.zero_point; + data->params.output_scale = output->params.scale; + break; + } + default: + MicroPrintf("Op Concatenation does not currently support Type '%s'.", + TfLiteTypeGetName(output_type)); + return kTfLiteError; + } + + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* output_tensor = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, output_tensor != nullptr); + TfLiteType output_type = output_tensor->type; + + switch (output_type) { // Already know in/outtypes are same. + case kTfLiteFloat32: + EvalUnquantized(context, node); + break; + case kTfLiteInt32: + EvalUnquantized(context, node); + break; + case kTfLiteInt8: + EvalUnquantized(context, node); + break; + case kTfLiteInt64: + EvalUnquantized(context, node); + break; + case kTfLiteInt16: + EvalUnquantized(context, node); + break; + case kTfLiteBool: + EvalUnquantized(context, node); + break; + + default: + MicroPrintf("Op Concatenation does not currently support Type '%s'.", + TfLiteTypeGetName(output_type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_CONCATENATION() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.cpp new file mode 100644 index 0000000..32177b3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.cpp @@ -0,0 +1,2213 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +struct OpData { + OpDataConv reference_op_data; + + // Index to buffer for optimizations if applicable. + int buffer_idx; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + int32_t buf_size = 0; + const auto& params = + *(static_cast(node->builtin_data)); + OpData* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + RuntimeShape input_shape = GetTensorShape(input); + RuntimeShape output_shape = GetTensorShape(output); + + // Initialize cmsis_nn input dimensions + cmsis_nn_dims input_dims; + input_dims.n = MatchingDim(input_shape, 0, output_shape, 0); + input_dims.h = input->dims->data[1]; + input_dims.w = input->dims->data[2]; + input_dims.c = input_shape.Dims(3); + + // Initialize cmsis_nn filter dimensions + cmsis_nn_dims filter_dims; + filter_dims.n = output_shape.Dims(3); + filter_dims.h = filter->dims->data[1]; + filter_dims.w = filter->dims->data[2]; + filter_dims.c = input_dims.c; + + // Initialize cmsis_nn output dimensions + cmsis_nn_dims output_dims; + output_dims.n = input_dims.n; + output_dims.h = output->dims->data[1]; + output_dims.w = output->dims->data[2]; + output_dims.c = output_shape.Dims(3); + + if (filter->type == kTfLiteInt4) { + int filter_size = + RuntimeShape(filter->dims->size, + reinterpret_cast(filter->dims->data)) + .FlatSize(); + context->RequestScratchBufferInArena( + context, filter_size, &data->reference_op_data.filter_buffer_index); + } + + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + const int num_channels = filter->dims->data[kConvQuantizedDimension]; + data->reference_op_data.per_channel_output_multiplier = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->reference_op_data.per_channel_output_shift = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + } + + TF_LITE_ENSURE_STATUS(CalculateOpDataConv( + context, node, params, input_dims.w, input_dims.h, filter_dims.w, + filter_dims.h, output_dims.w, output_dims.h, input->type, + &data->reference_op_data)); + + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + // Initialize cmsis_nn convolution parameters + cmsis_nn_conv_params conv_params; + conv_params.input_offset = -input->params.zero_point; + conv_params.output_offset = output->params.zero_point; + conv_params.stride.h = params.stride_height; + conv_params.stride.w = params.stride_width; + conv_params.dilation.h = params.dilation_height_factor; + conv_params.dilation.w = params.dilation_width_factor; + conv_params.padding.h = data->reference_op_data.padding.height; + conv_params.padding.w = data->reference_op_data.padding.width; + conv_params.activation.min = data->reference_op_data.output_activation_min; + conv_params.activation.max = data->reference_op_data.output_activation_max; + + if (input->type == kTfLiteInt8) { + buf_size = arm_convolve_wrapper_s8_get_buffer_size( + &conv_params, &input_dims, &filter_dims, &output_dims); + } else if (input->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, input->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + buf_size = arm_convolve_wrapper_s16_get_buffer_size( + &conv_params, &input_dims, &filter_dims, &output_dims); + } + + if (buf_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, buf_size, &data->buffer_idx)); + } else { + data->buffer_idx = -1; + } + } + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + + return kTfLiteOk; +} + +TfLiteStatus EvalQuantizedPerChannel(TfLiteContext* context, TfLiteNode* node, + const TfLiteConvParams& params, + const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + cmsis_nn_conv_params conv_params; + conv_params.dilation.h = params.dilation_height_factor; + conv_params.dilation.w = params.dilation_width_factor; + + // Initialize cmsis_nn convolution parameters + conv_params.input_offset = -data.reference_op_data.input_zero_point; + conv_params.output_offset = data.reference_op_data.output_zero_point; + conv_params.stride.h = params.stride_height; + conv_params.stride.w = params.stride_width; + conv_params.padding.h = data.reference_op_data.padding.height; + conv_params.padding.w = data.reference_op_data.padding.width; + conv_params.activation.min = data.reference_op_data.output_activation_min; + conv_params.activation.max = data.reference_op_data.output_activation_max; + + // Initialize cmsis_nn per channel quantization parameters + cmsis_nn_per_channel_quant_params quant_params; + quant_params.multiplier = const_cast( + data.reference_op_data.per_channel_output_multiplier); + quant_params.shift = + const_cast(data.reference_op_data.per_channel_output_shift); + + RuntimeShape filter_shape = tflite::micro::GetTensorShape(filter); + RuntimeShape input_shape = tflite::micro::GetTensorShape(input); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + RuntimeShape bias_shape = tflite::micro::GetTensorShape(bias); + + // Consistency check. + TFLITE_DCHECK_LE(conv_params.activation.min, conv_params.activation.max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batch_size = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (tflite::micro::GetOptionalTensorData(bias)) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + // Initialize cmsis_nn dimensions + // Input + cmsis_nn_dims input_dims; + input_dims.n = batch_size; + input_dims.h = input_shape.Dims(1); + input_dims.w = input_shape.Dims(2); + input_dims.c = input_depth; + + // Filter + cmsis_nn_dims filter_dims; + filter_dims.n = output_depth; + filter_dims.h = filter_shape.Dims(1); + filter_dims.w = filter_shape.Dims(2); + filter_dims.c = input_depth; + + // Bias + cmsis_nn_dims bias_dims; + bias_dims.n = 1; + bias_dims.h = 1; + bias_dims.w = 1; + bias_dims.c = output_depth; + + // Output + cmsis_nn_dims output_dims; + output_dims.n = batch_size; + output_dims.h = output_shape.Dims(1); + output_dims.w = output_shape.Dims(2); + output_dims.c = output_depth; + + // Initialize cmsis_nn context + cmsis_nn_context ctx; + ctx.buf = nullptr; + ctx.size = 0; + + if (data.buffer_idx > -1) { + ctx.buf = context->GetScratchBuffer(context, data.buffer_idx); + // Note: ctx.size is currently not used in cmsis_nn. + // The buffer should be allocated in the Prepare function through + // arm_convolve_wrapper_s8_get_buffer_size + } + + // arm_convolve_wrapper_s8 dispatches the optimized kernel accordingly with + // the parameters passed + TFLITE_DCHECK_EQ( + arm_convolve_wrapper_s8( + &ctx, &conv_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, + tflite::micro::GetOptionalTensorData(bias), &output_dims, + tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + + return kTfLiteOk; +} + +TfLiteStatus EvalQuantizedPerChannel16x8( + TfLiteContext* context, TfLiteNode* node, const TfLiteConvParams& params, + const OpData& data, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + cmsis_nn_conv_params conv_params; + conv_params.dilation.h = params.dilation_height_factor; + conv_params.dilation.w = params.dilation_width_factor; + + // Initialize cmsis_nn convolution parameters + conv_params.input_offset = -data.reference_op_data.input_zero_point; + conv_params.output_offset = data.reference_op_data.output_zero_point; + conv_params.stride.h = params.stride_height; + conv_params.stride.w = params.stride_width; + conv_params.padding.h = data.reference_op_data.padding.height; + conv_params.padding.w = data.reference_op_data.padding.width; + conv_params.activation.min = data.reference_op_data.output_activation_min; + conv_params.activation.max = data.reference_op_data.output_activation_max; + + // Initialize cmsis_nn per channel quantization parameters + cmsis_nn_per_channel_quant_params quant_params; + quant_params.multiplier = const_cast( + data.reference_op_data.per_channel_output_multiplier); + quant_params.shift = + const_cast(data.reference_op_data.per_channel_output_shift); + + RuntimeShape filter_shape = tflite::micro::GetTensorShape(filter); + RuntimeShape input_shape = tflite::micro::GetTensorShape(input); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + RuntimeShape bias_shape = tflite::micro::GetTensorShape(bias); + + // Consistency check. + TFLITE_DCHECK_LE(conv_params.activation.min, conv_params.activation.max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batch_size = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + if (tflite::micro::GetOptionalTensorData(bias)) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + // Initialize cmsis_nn dimensions + // Input + cmsis_nn_dims input_dims; + input_dims.n = batch_size; + input_dims.h = input_shape.Dims(1); + input_dims.w = input_shape.Dims(2); + input_dims.c = input_depth; + + // Filter + cmsis_nn_dims filter_dims; + filter_dims.n = output_depth; + filter_dims.h = filter_shape.Dims(1); + filter_dims.w = filter_shape.Dims(2); + filter_dims.c = input_depth; + + // Bias + cmsis_nn_dims bias_dims; + bias_dims.n = 1; + bias_dims.h = 1; + bias_dims.w = 1; + bias_dims.c = output_depth; + + // Output + cmsis_nn_dims output_dims; + output_dims.n = batch_size; + output_dims.h = output_shape.Dims(1); + output_dims.w = output_shape.Dims(2); + output_dims.c = output_depth; + + // Initialize cmsis_nn context + cmsis_nn_context ctx; + ctx.buf = nullptr; + ctx.size = 0; + + if (data.buffer_idx > -1) { + ctx.buf = context->GetScratchBuffer(context, data.buffer_idx); + // Note: ctx.size is currently not used in cmsis_nn. + // The buffer should be allocated in the Prepare function through + // arm_convolve_wrapper_s8_get_buffer_size + } + + TFLITE_DCHECK_EQ( + arm_convolve_wrapper_s16( + &ctx, &conv_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, + tflite::micro::GetOptionalTensorData(bias), &output_dims, + tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + + return kTfLiteOk; +} + +TfLiteStatus EvalInt8(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kConvBiasTensor) + : nullptr; + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kConvOutputTensor); + + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto& params = + *(reinterpret_cast(node->builtin_data)); + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + TfLiteEvalTensor filter_int8 = tflite::micro::MakeUnpackedInt4Tensor( + context, data.reference_op_data.filter_buffer_index, filter); + + return EvalQuantizedPerChannel(context, node, params, data, input, + &filter_int8, bias, output); +} + +TfLiteStatus EvalInt16x8(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kConvBiasTensor) + : nullptr; + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kConvOutputTensor); + + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto& params = + *(reinterpret_cast(node->builtin_data)); + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + return EvalQuantizedPerChannel16x8(context, node, params, data, input, filter, + bias, output); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kConvBiasTensor) + : nullptr; + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kConvOutputTensor); + + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto& params = + *(reinterpret_cast(node->builtin_data)); + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + TF_LITE_ENSURE_EQ(context, input->type, output->type); + TF_LITE_ENSURE_MSG( + context, + input->type == filter->type || + (input->type == kTfLiteInt16 && filter->type == kTfLiteInt8) || + (input->type == kTfLiteInt8 && filter->type == kTfLiteInt4), + "Hybrid models are not supported on TFLite Micro."); + + TfLiteEvalTensor filter_int8 = tflite::micro::MakeUnpackedInt4Tensor( + context, data.reference_op_data.filter_buffer_index, filter); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_CONV_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + tflite::reference_ops::Conv( + ConvParamsFloat(params, data.reference_op_data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr); + break; + } + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_CONV_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + switch (filter_int8.type) { + case kTfLiteInt8: { + return EvalQuantizedPerChannel(context, node, params, data, input, + &filter_int8, bias, output); + } + + default: { + MicroPrintf("Filter type %s (%d) not supported.", + TfLiteTypeGetName(filter->type), filter->type); + return kTfLiteError; + } + } + + break; + case kTfLiteInt16: + return EvalQuantizedPerChannel16x8(context, node, params, data, input, + filter, bias, output); + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_CONV_2D() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +TfLiteRegistration Register_CONV_2D_INT8() { + return tflite::micro::RegisterOp(Init, Prepare, EvalInt8); +} + +TfLiteRegistration Register_CONV_2D_INT16() { + return tflite::micro::RegisterOp(Init, Prepare, EvalInt16x8); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h" + +#include "mli_api.h" // NOLINT +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_function_specializations.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kFilterTensor = 1; +constexpr int kBiasTensor = 2; +constexpr int kOutputTensor = 0; + +// Conv is quantized along dimension 0: +// https://www.tensorflow.org/lite/performance/quantization_spec +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) +constexpr int kConvQuantizedDimension = 3; +#else +constexpr int kConvQuantizedDimension = 0; +#endif + +// This file has 2 implementation of Conv. + +struct OpData { + TfLitePaddingValues padding; + + // Cached tensor zero point values for quantized operations. + int32_t input_zero_point; + int32_t filter_zero_point; + int32_t output_zero_point; + + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t output_multiplier; + int output_shift; + + // Per channel output multiplier and shift. + int32_t* per_channel_output_multiplier; + int32_t* per_channel_output_shift; +#ifdef MLI_2_0 + int8_t* per_channel_scale_frac_bits; +#endif + + // The range of the fused activation layer. For example for kNone and + // uint8_t these would be 0 and 255. + int32_t output_activation_min; + int32_t output_activation_max; + + // The result of checking if MLI optimized version of tensors can be used. + bool is_mli_applicable; + + // Tensors in MLI format. + mutable ops::micro::MliTensorInterface mli_in; + mutable ops::micro::MliTensorInterface mli_weights; + mutable ops::micro::MliTensorInterface mli_bias; + mutable ops::micro::MliTensorInterface mli_out; + mli_conv2d_cfg* cfg; + + // Pointer to the mli convolution function. + conv_func_ptr p_mli_krn_conv2d_sa8_sa8_sa32; +}; + +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) +inline PaddingType RuntimePaddingType(TfLitePadding padding) { + switch (padding) { + case TfLitePadding::kTfLitePaddingSame: + return PaddingType::kSame; + case TfLitePadding::kTfLitePaddingValid: + return PaddingType::kValid; + case TfLitePadding::kTfLitePaddingUnknown: + default: + return PaddingType::kNone; + } +} +#endif + +bool IsMliApplicable(TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* filter, const TfLiteTensor* bias, + const TfLiteConvParams* params) { + const auto* affine_quantization = + reinterpret_cast(filter->quantization.params); + // MLI optimized version only supports int8_t datatype, dilation factor of 1 + // and per-axis quantization of weights (no broadcasting/per-tensor) + bool ret_val = (filter->type == kTfLiteInt8) && + (input->type == kTfLiteInt8) && (bias->type == kTfLiteInt32) && + (params->dilation_width_factor == 1) && + (params->dilation_height_factor == 1) && + (affine_quantization->scale->size == + filter->dims->data[kConvQuantizedDimension]); + return ret_val; +} + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node, + const TfLiteConvParams* params, int width, + int height, int filter_width, int filter_height, + int out_width, int out_height, + const TfLiteType data_type, OpData* data) { + bool has_bias = node->inputs->size == 3; + // Check number of inputs/outputs + TF_LITE_ENSURE(context, has_bias || node->inputs->size == 2); + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + + // Matching GetWindowedOutputSize in TensorFlow. + auto padding = params->padding; + data->padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, + params->dilation_height_factor, params->dilation_width_factor, height, + width, filter_height, filter_width, padding, &out_height, &out_width); + // Note that quantized inference requires that all tensors have their + // parameters set. This is usually done during quantized training. +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kFilterTensor); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kBiasTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + if (data_type != kTfLiteFloat32 && !data->is_mli_applicable) { + int output_channels = filter->dims->data[kConvQuantizedDimension]; + + TF_LITE_ENSURE_STATUS(tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, params->activation, + &data->output_multiplier, &data->output_shift, + &data->output_activation_min, &data->output_activation_max, + data->per_channel_output_multiplier, + reinterpret_cast(data->per_channel_output_shift), + output_channels)); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(bias); + micro_context->DeallocateTempTfLiteTensor(output); +#endif + return kTfLiteOk; +} +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto params = static_cast(node->builtin_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kFilterTensor); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kBiasTensor); + + int input_width = input->dims->data[2]; + int input_height = input->dims->data[1]; +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + int filter_width = filter->dims->data[1]; + int filter_height = filter->dims->data[0]; +#else + int filter_width = filter->dims->data[2]; + int filter_height = filter->dims->data[1]; +#endif + int output_width = output->dims->data[2]; + int output_height = output->dims->data[1]; + + // Dynamically allocate per-channel quantization parameters. + const int num_channels = filter->dims->data[kConvQuantizedDimension]; + data->per_channel_output_multiplier = + reinterpret_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = + reinterpret_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + data->is_mli_applicable = + IsMliApplicable(context, input, filter, bias, params); + + // All per-channel quantized tensors need valid zero point and scale arrays. + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + const auto* affine_quantization = + static_cast(filter->quantization.params); + TF_LITE_ENSURE(context, affine_quantization); + TF_LITE_ENSURE(context, affine_quantization->scale); + TF_LITE_ENSURE(context, affine_quantization->zero_point); + + TF_LITE_ENSURE(context, + affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kConvQuantizedDimension]); + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, + affine_quantization->zero_point->size); + } + + TF_LITE_ENSURE_STATUS(CalculateOpData( + context, node, params, input_width, input_height, filter_width, + filter_height, output_width, output_height, input->type, data)); + + data->input_zero_point = input->params.zero_point; + data->filter_zero_point = filter->params.zero_point; + data->output_zero_point = output->params.zero_point; + + if (data->is_mli_applicable) { + data->mli_in = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_weights = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_bias = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_out = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->cfg = static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_conv2d_cfg))); + +#ifdef MLI_2_0 + data->per_channel_scale_frac_bits = + static_cast(context->AllocatePersistentBuffer( + context, 2 * num_channels * sizeof(int16_t))); +#endif + + // Reuse space allocated for OpData parameters. +#ifdef MLI_2_0 + *data->mli_weights.Scale() = + reinterpret_cast(data->per_channel_output_multiplier); + *data->mli_bias.Scale() = + reinterpret_cast(data->per_channel_output_multiplier) + + num_channels; +#else + *data->mli_weights.Scale() = + static_cast(data->per_channel_output_multiplier); + *data->mli_bias.Scale() = + static_cast(data->per_channel_output_shift); +#endif + +#ifdef MLI_2_0 + *data->mli_weights.ZeroPoint() = + reinterpret_cast(data->per_channel_output_shift); + *data->mli_bias.ZeroPoint() = + reinterpret_cast(data->per_channel_output_shift) + + num_channels; +#else + *data->mli_weights.ZeroPoint() = + reinterpret_cast(&data->filter_zero_point); + *data->mli_bias.ZeroPoint() = + reinterpret_cast(&data->filter_zero_point) + sizeof(int16_t); +#endif + +#ifdef MLI_2_0 + *data->mli_weights.ScaleFracBits() = + reinterpret_cast(data->per_channel_scale_frac_bits); + *data->mli_bias.ScaleFracBits() = + reinterpret_cast(data->per_channel_scale_frac_bits) + + num_channels; +#endif + + ops::micro::ConvertToMliTensor(input, &data->mli_in); + ops::micro::ConvertToMliTensorPerChannel(filter, &data->mli_weights, + /* is_bias_tensor = */ false); + ops::micro::ConvertToMliTensorPerChannel(bias, &data->mli_bias, + /* is_bias_tensor = */ true); +#ifdef MLI_2_0 + ops::micro::AdjustBiasTensor(&data->mli_bias, &data->mli_in, + &data->mli_weights); +#endif + ops::micro::ConvertToMliTensor(output, &data->mli_out); + +#ifdef MLI_2_0 + // Choose convolution mli specialized function. + data->p_mli_krn_conv2d_sa8_sa8_sa32 = + mli_krn_conv2d_hwcn(data->mli_weights.MliTensor()); +#else + data->p_mli_krn_conv2d_sa8_sa8_sa32 = + mli_krn_conv2d_hwcn(data->mli_weights.MliTensor(), data->cfg); +#endif + +#ifdef MLI_2_0 + data->cfg->dilation_width = 1; + data->cfg->dilation_height = 1; +#endif + + if (data->output_activation_min == -128 && + data->output_activation_max == 127) { + data->cfg->relu.type = MLI_RELU_NONE; + } else if (params->activation == kTfLiteActRelu) { + data->cfg->relu.type = MLI_RELU_GEN; + } else if (params->activation == kTfLiteActRelu6) { + data->cfg->relu.type = MLI_RELU_6; + } else if (params->activation == kTfLiteActReluN1To1) { + data->cfg->relu.type = MLI_RELU_1; + } else { + data->cfg->relu.type = MLI_RELU_NONE; + } + data->cfg->stride_width = params->stride_width; + data->cfg->stride_height = params->stride_height; + if (params->padding == kTfLitePaddingValid) { + data->cfg->padding_left = 0; + data->cfg->padding_right = 0; + data->cfg->padding_top = 0; + data->cfg->padding_bottom = 0; + } else { + data->cfg->padding_left = data->padding.width; + data->cfg->padding_right = + data->padding.width + data->padding.width_offset; + data->cfg->padding_top = data->padding.height; + data->cfg->padding_bottom = + data->padding.height + data->padding.height_offset; + } + } + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(bias); + return kTfLiteOk; +} + +TfLiteStatus EvalMliQuantizedPerChannel( + TfLiteContext* context, TfLiteNode* node, TfLiteConvParams* params, + const OpData& data, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + // Run Conv MLI kernel + // MLI optimized version only supports int8_t dataype and dilation factor of 1 + if (data.is_mli_applicable) { + // Copy configuration data from external to local memory + mli_conv2d_cfg cfg_local = *data.cfg; + + ops::micro::MliTensorAttachBuffer(input, &data.mli_in); + ops::micro::MliTensorAttachBuffer(filter, &data.mli_weights); + ops::micro::MliTensorAttachBuffer(bias, &data.mli_bias); + ops::micro::MliTensorAttachBuffer(output, &data.mli_out); + + // for height slicing + const int height_dimension = 1; + int in_slice_height = 0; + int out_slice_height = 0; + const int kernel_height = + static_cast(data.mli_weights.Shape()[KRNL_H_DIM_HWC]); + const int overlap = kernel_height - cfg_local.stride_height; + +// for weight slicing (on output channels) +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + // HWCN layout for weights, output channel dimension is the first dimension. + const int weight_out_ch_dimension = 3; +#else + // NHWC layout for weights, output channel dimension is the first dimension. + const int weight_out_ch_dimension = 0; +#endif + // bias has only 1 dimension + const int bias_out_ch_dimension = 0; + int slice_channels = + static_cast(data.mli_weights.Shape()[weight_out_ch_dimension]); + // Batch-Height-Width-Channel layout means last dimension is output + // channels. + const int out_tensor_ch_dimension = 3; + + // Tensors for data in fast (local) memory and config to copy data from + // external to local memory + mli_tensor weights_local = *data.mli_weights.MliTensor(); + mli_tensor bias_local = *data.mli_bias.MliTensor(); + mli_tensor in_local = *data.mli_in.MliTensor(); + mli_tensor out_local = *data.mli_out.MliTensor(); + + ops::micro::MliTensorInterface weights_local_interface(&weights_local); + ops::micro::MliTensorInterface bias_local_interface(&bias_local); + ops::micro::MliTensorInterface in_local_interface(&in_local); + ops::micro::MliTensorInterface out_local_interface(&out_local); + + mli_mov_cfg_t copy_config; + mli_mov_cfg_for_copy(©_config); + + TF_LITE_ENSURE_STATUS(ops::micro::get_arc_scratch_buffer_for_conv_tensors( + context, &in_local_interface, &weights_local_interface, + &bias_local_interface, &out_local_interface)); + TF_LITE_ENSURE_STATUS(ops::micro::arc_scratch_buffer_calc_slice_size_io( + &in_local_interface, &out_local_interface, kernel_height, + cfg_local.stride_height, cfg_local.padding_top, + cfg_local.padding_bottom, &in_slice_height, &out_slice_height)); + TF_LITE_ENSURE_STATUS( + ops::micro::arc_scratch_buffer_calc_slice_size_weights( + &weights_local_interface, &bias_local_interface, + weight_out_ch_dimension, &slice_channels)); + + /* is_local indicates that the tensor is already in local memory, + so in that case the original tensor can be used, + and there is no need to copy it to the local tensor*/ + const bool in_is_local = + in_local_interface.Data() == data.mli_in.Data(); + const bool out_is_local = + out_local_interface.Data() == data.mli_out.Data(); + const bool b_is_local = + bias_local_interface.Data() == data.mli_bias.Data(); +#ifndef MLI_2_0_KRNL_TEST + const bool w_is_local = weights_local_interface.Data() == + data.mli_weights.Data(); +#endif + +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + ops::micro::TensorSlicer w_slice(data.mli_weights.MliTensor(), + weight_out_ch_dimension, slice_channels, 0, + 0, 0, true); +#else + ops::micro::TensorSlicer w_slice(data.mli_weights.MliTensor(), + weight_out_ch_dimension, slice_channels); +#endif + ops::micro::TensorSlicer b_slice(data.mli_bias.MliTensor(), + bias_out_ch_dimension, slice_channels); + ops::micro::TensorSlicer out_ch_slice(data.mli_out.MliTensor(), + out_tensor_ch_dimension, + slice_channels, 0, 0, 0, true); + +#ifdef MLI_2_0_KRNL_TEST + mli_tensor* w_ptr = &weights_local; +#else + mli_tensor* w_ptr = w_is_local ? w_slice.Sub() : &weights_local; +#endif + mli_tensor* b_ptr = b_is_local ? b_slice.Sub() : &bias_local; + + void* input_buffer_ptr = NULL; + uint32_t input_buffer_size = 0; + + while (!w_slice.Done()) { +#ifndef MLI_2_0_KRNL_TEST + mli_mov_tensor_sync(w_slice.Sub(), ©_config, w_ptr); +#endif + mli_mov_tensor_sync(b_slice.Sub(), ©_config, b_ptr); + + /* mli_in tensor contains batches of HWC tensors. so it is a 4 dimensional + tensor. because the mli kernel will process one HWC tensor at a time, the + 4 dimensional tensor needs to be sliced into nBatch 3 dimensional tensors. + on top of that there could be a need to also slice in the Height + dimension. for that the sliceHeight has been calculated. The tensor slicer + is configured that it will completely slice the nBatch dimension (0) and + slice the height dimension (1) in chunks of 'sliceHeight' */ + ops::micro::TensorSlicer in_slice( + data.mli_in.MliTensor(), height_dimension, in_slice_height, + cfg_local.padding_top, cfg_local.padding_bottom, overlap); + + /* output tensor is already sliced in the output channel dimension. + out_ch_slice.Sub() is the tensor for the amount of output channels of this + iteration of the weight slice loop. This tensor needs to be further + sliced over the batch and height dimension. */ + ops::micro::TensorSlicer out_slice(out_ch_slice.Sub(), height_dimension, + out_slice_height); + + /* setup the pointers to the local or remote tensor to make the code + * inside the loop easier. */ + mli_tensor* in_ptr = in_is_local ? in_slice.Sub() : &in_local; + mli_tensor* out_ptr = out_is_local ? out_slice.Sub() : &out_local; + +#ifdef MLI_2_0_KRNL_TEST + /* Permute weights tensor to the HWCN layout */ + // Checking conditions here to prevent usage non-contiguous buffer memory. + if (data.mli_out.Shape()[out_tensor_ch_dimension] != + out_slice.Sub()->shape[FMAP_C_DIM_HWC] || + data.mli_out.Shape()[height_dimension] != + out_slice.Sub()->shape[FMAP_H_DIM_HWC]) { + MicroPrintf("Slicing is not supported with real-time permutation."); + return kTfLiteError; + } + mli_permute_cfg permute_cfg = {{1, 2, 3, 0}}; + ops::micro::permute_weights(data.mli_weights.MliTensor(), &permute_cfg, + w_ptr, &out_ptr->data); +#endif + + while (!out_slice.Done()) { + if (!out_is_local) { + ops::micro::PrepareLocalTensor(out_slice.Sub(), &out_local); + ops::micro::PrepareLocalTensor(in_slice.Sub(), &in_local); + } + + TF_LITE_ENSURE(context, !in_slice.Done()); + cfg_local.padding_top = in_slice.GetPaddingPre(); + cfg_local.padding_bottom = in_slice.GetPaddingPost(); + + // if same input copy as previous iteration, skip the copy of input +#ifdef MLI_2_0 + if ((in_slice.Sub()->data.mem.pi8 != input_buffer_ptr) || + (mli_hlp_count_elem_num(in_slice.Sub(), 0) != input_buffer_size)) { + mli_mov_tensor_sync(in_slice.Sub(), ©_config, in_ptr); + input_buffer_ptr = in_slice.Sub()->data.mem.pi8; + input_buffer_size = mli_hlp_count_elem_num(in_slice.Sub(), 0); + } + + data.p_mli_krn_conv2d_sa8_sa8_sa32(in_ptr, w_ptr, b_ptr, &cfg_local, + out_ptr); +#else + if ((in_slice.Sub()->data != input_buffer_ptr) || + (mli_hlp_count_elem_num(in_slice.Sub(), 0) != input_buffer_size)) { + mli_mov_tensor_sync(in_slice.Sub(), ©_config, in_ptr); + input_buffer_ptr = in_slice.Sub()->data; + input_buffer_size = mli_hlp_count_elem_num(in_slice.Sub(), 0); + } + data.p_mli_krn_conv2d_sa8_sa8_sa32(in_ptr, w_ptr, b_ptr, &cfg_local, + out_ptr); +#endif + mli_mov_tensor_sync(out_ptr, ©_config, out_slice.Sub()); + + in_slice.Next(); + out_slice.Next(); + } + w_slice.Next(); + b_slice.Next(); + out_ch_slice.Next(); + TF_LITE_ENSURE(context, in_slice.Done()); + } + } + return kTfLiteOk; +} + +void EvalQuantizedPerChannel(TfLiteContext* context, TfLiteNode* node, + TfLiteConvParams* params, const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output, + TfLiteEvalTensor* im2col) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + ConvParams op_params; + op_params.input_offset = -data.input_zero_point; + op_params.output_offset = data.output_zero_point; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.dilation_height_factor = params->dilation_height_factor; + op_params.dilation_width_factor = params->dilation_width_factor; + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.quantized_activation_min = data.output_activation_min; + op_params.quantized_activation_max = data.output_activation_max; + + reference_integer_ops::ConvPerChannel( + op_params, data.per_channel_output_multiplier, + data.per_channel_output_shift, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf("Node configuration is not supported by ARC MLI Library."); +#endif +} + +void EvalQuantizedPerChannelInt16(TfLiteContext* context, TfLiteNode* node, + TfLiteConvParams* params, const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + ConvParams op_params; + op_params.input_offset = -data.input_zero_point; + op_params.output_offset = data.output_zero_point; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.dilation_height_factor = params->dilation_height_factor; + op_params.dilation_width_factor = params->dilation_width_factor; + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.quantized_activation_min = data.output_activation_min; + op_params.quantized_activation_max = data.output_activation_max; + + reference_integer_ops::ConvPerChannel( + op_params, data.per_channel_output_multiplier, + data.per_channel_output_shift, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf("Node configuration is not supported by ARC MLI Library."); +#endif +} + +void EvalFloat(TfLiteContext* context, TfLiteNode* node, + TfLiteConvParams* params, const OpData& data, + const TfLiteEvalTensor* input, const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, TfLiteEvalTensor* im2col, + TfLiteEvalTensor* hwcn_weights, TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + float output_activation_min, output_activation_max; + CalculateActivationRange(params->activation, &output_activation_min, + &output_activation_max); + ConvParams op_params; + op_params.padding_type = RuntimePaddingType(params->padding); + op_params.padding_values.width = data.padding.width; + op_params.padding_values.height = data.padding.height; + op_params.stride_width = params->stride_width; + op_params.stride_height = params->stride_height; + op_params.dilation_width_factor = params->dilation_width_factor; + op_params.dilation_height_factor = params->dilation_height_factor; + op_params.float_activation_min = output_activation_min; + op_params.float_activation_max = output_activation_max; + + reference_ops::Conv(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(im2col), + tflite::micro::GetTensorData(im2col)); +#else + MicroPrintf("Type %s (%d) is not supported by ARC MLI Library.", + TfLiteTypeGetName(input->type), input->type); +#endif +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFilterTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kBiasTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + TF_LITE_ENSURE_EQ(context, input->type, output->type); + TF_LITE_ENSURE_MSG( + context, + input->type == filter->type || + (input->type == kTfLiteInt16 && filter->type == kTfLiteInt8), + "Hybrid models are not supported on TFLite Micro."); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_CONV_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + EvalFloat(context, node, params, data, input, filter, bias, nullptr, + nullptr, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_CONV_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + if (data.is_mli_applicable) { + EvalMliQuantizedPerChannel(context, node, params, data, input, filter, + bias, output); + } else { + EvalQuantizedPerChannel(context, node, params, data, input, filter, + bias, output, nullptr); + } + break; + case kTfLiteInt16: + EvalQuantizedPerChannelInt16(context, node, params, data, input, filter, + bias, output); + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_CONV_2D() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP == 1 + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +#include "sl_mvp_ml_conv2d.h" + +namespace tflite { +namespace sl { +namespace conv2d { + +constexpr int kInputTensor = 0; +constexpr int kFilterTensor = 1; +constexpr int kBiasTensor = 2; +constexpr int kOutputTensor = 0; + +// Conv is quantized along dimension 0 of filter tensor. +// https://www.tensorflow.org/lite/performance/quantization_spec +constexpr int kConvQuantizedDimension = 0; + +enum op_support { kMvp, kCmsisNN, kTFLMrefF32, kTFLMrefI8 }; + +struct OpData { + op_support supported; + float activation_min_f32; + float activation_max_f32; + int scratch_buffer_index; + sli_mvp_ml_conv2d_s8_params_t op_params; + + // CMSIS-NN per channel output multiplier and shift. + int32_t *per_channel_output_multiplier; + int32_t *per_channel_output_shift; +}; + +inline float16_t normalize_fp16(float f) +{ + return (float16_t)std::min(std::max(f, SLI_MVP_FP16_MIN), SLI_MVP_FP16_MAX); +} + +inline PaddingType RuntimePaddingType(TfLitePadding padding) +{ + switch (padding) { + case TfLitePadding::kTfLitePaddingSame: + return PaddingType::kSame; + case TfLitePadding::kTfLitePaddingValid: + return PaddingType::kValid; + case TfLitePadding::kTfLitePaddingUnknown: + default: + return PaddingType::kNone; + } +} + +TfLiteStatus PopulateConvolutionQuantizationParams( + TfLiteContext* context, + const TfLiteTensor* input, + const TfLiteTensor* filter, + TfLiteTensor* output, + const TfLiteFusedActivation& activation, + int32_t* output_activation_min, int32_t* output_activation_max, + float16_t* per_channel_scalers, int num_channels, float accumulator_multipler) +{ + auto affine_quantization = + reinterpret_cast(filter->quantization.params); + + // Populate multiplier and shift using affine quantization. + const float input_scale = input->params.scale; + const float output_scale = output->params.scale; + const float* filter_scales = affine_quantization->scale->data; + + for (int i = 0; i < num_channels; ++i) { + // If per-tensor quantization parameter is specified, broadcast it along the + // quantization dimension (channels_out). + const float filter_scale = filter_scales[i]; + const float effective_output_scale = (input_scale * filter_scale) / output_scale; + const float acc_output_scale = effective_output_scale * accumulator_multipler; + per_channel_scalers[i] = normalize_fp16(acc_output_scale); + } + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, activation, output, output_activation_min, + output_activation_max)); + + return kTfLiteOk; +} + +void *Init(TfLiteContext* context, const char* buffer, size_t length) +{ + (void)buffer; + (void)length; + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) +{ + int scratch_buffer_size = 0; + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto params = static_cast(node->builtin_data); + + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + const TfLiteTensor* bias = GetOptionalInputTensor(context, node, kBiasTensor); + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + const TfLiteTensor* filter = GetInput(context, node, kFilterTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE(context, filter != nullptr); + + data->op_params.batches = input->dims->data[0]; + data->op_params.in_channels = input->dims->data[3]; + data->op_params.input_height = input->dims->data[1]; + data->op_params.input_width = input->dims->data[2]; + data->op_params.out_channels = filter->dims->data[kConvQuantizedDimension]; + data->op_params.output_height = output->dims->data[1]; + data->op_params.output_width = output->dims->data[2]; + data->op_params.filter_height = filter->dims->data[1]; + data->op_params.filter_width = filter->dims->data[2]; + data->op_params.input_offset = -input->params.zero_point; + data->op_params.output_offset = output->params.zero_point; + data->op_params.stride_height = params->stride_height; + data->op_params.stride_width = params->stride_width; + data->op_params.dilation_height = params->dilation_height_factor; + data->op_params.dilation_width = params->dilation_width_factor; + data->op_params.padding = params->padding == kTfLitePaddingSame; + + int dummy_height, dummy_width; + const auto padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, + params->dilation_height_factor, params->dilation_width_factor, + data->op_params.input_height, data->op_params.input_width, + data->op_params.filter_height, data->op_params.filter_width, + params->padding, + &dummy_height, &dummy_width); + + data->op_params.pad_height = padding.height; + data->op_params.pad_width = padding.width; + + const int num_channels = data->op_params.out_channels; + + if (input->type == kTfLiteInt8) { + if (sli_mvp_ml_conv2d_s8_is_supported(&data->op_params)) { + data->supported = kMvp; + + float16_t *bias_data = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(float16_t))); + if(bias != nullptr) { + data->op_params.bias = bias_data; + int32_t i32_bias; + for(int i = 0; i < num_channels; i++) { + i32_bias = bias->data.i32[i]; + bias_data[i] = float16_t(i32_bias * SLI_MVP_ACCUMULATOR_SCALER); + } + } else { + data->op_params.bias = nullptr; + } + + float16_t *scaler_data = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(float16_t))); + data->op_params.output_scaler = scaler_data; + TF_LITE_ENSURE_STATUS(PopulateConvolutionQuantizationParams( + context, input, filter, output, params->activation, + reinterpret_cast(&data->op_params.output_activation_min), + reinterpret_cast(&data->op_params.output_activation_max), + scaler_data, num_channels, SLI_MVP_ACCUMULATOR_MULTIPLIER)); + + } else { + data->per_channel_output_multiplier = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + int32_t dummy_output_multiplier; + int dummy_output_shift; + TF_LITE_ENSURE_STATUS(tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, params->activation, + &dummy_output_multiplier, &dummy_output_shift, + reinterpret_cast(&data->op_params.output_activation_min), + reinterpret_cast(&data->op_params.output_activation_max), + data->per_channel_output_multiplier, + reinterpret_cast(data->per_channel_output_shift), + num_channels)); + + if (data->op_params.dilation_height == 1 && data->op_params.dilation_width == 1) { + data->supported = kCmsisNN; + cmsis_nn_conv_params conv_params; + conv_params.input_offset = data->op_params.input_offset; + conv_params.output_offset = data->op_params.output_offset; + conv_params.stride.h = data->op_params.stride_height; + conv_params.stride.w = data->op_params.stride_width; + conv_params.dilation.h = 1; + conv_params.dilation.w = 1; + conv_params.padding.h = data->op_params.pad_height; + conv_params.padding.w = data->op_params.pad_width; + conv_params.activation.min = data->op_params.output_activation_min; + conv_params.activation.max = data->op_params.output_activation_max; + + cmsis_nn_dims input_dims; + input_dims.n = data->op_params.batches; + input_dims.h = data->op_params.input_height; + input_dims.w = data->op_params.input_width; + input_dims.c = data->op_params.in_channels; + + cmsis_nn_dims filter_dims; + filter_dims.h = data->op_params.filter_height; + filter_dims.w = data->op_params.filter_width; + + cmsis_nn_dims output_dims; + output_dims.h = data->op_params.output_height; + output_dims.w = data->op_params.output_width; + output_dims.c = data->op_params.out_channels; + + scratch_buffer_size = arm_convolve_wrapper_s8_get_buffer_size( + &conv_params, &input_dims, &filter_dims, &output_dims); + } else { + data->supported = kTFLMrefI8; + } + } + + } else if (input->type == kTfLiteFloat32) { + data->supported = kTFLMrefF32; + CalculateActivationRange(params->activation, + &data->activation_min_f32, + &data->activation_max_f32); + + } else { + TF_LITE_KERNEL_LOG(context, "Type %s not currently supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + if(scratch_buffer_size > 0) { + TF_LITE_ENSURE_STATUS( + context->RequestScratchBufferInArena( + context, scratch_buffer_size, &data->scratch_buffer_index)); + } else { + data->scratch_buffer_index = -1; + } + + return kTfLiteOk; +} + +TfLiteStatus eval_mvp_int8(TfLiteContext* context, + OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + TfLiteEvalTensor* output) +{ + data->op_params.input = tflite::micro::GetTensorData(input); + data->op_params.output = tflite::micro::GetTensorData(output); + data->op_params.filter = tflite::micro::GetTensorData(filter); + + TF_LITE_ENSURE_EQ(context, SL_STATUS_OK, sli_mvp_ml_conv2d_s8(&data->op_params)); + + return kTfLiteOk; +} + +TfLiteStatus eval_cmsis_int8(TfLiteContext* context, + OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + cmsis_nn_dims input_dims; + input_dims.n = data->op_params.batches; + input_dims.h = data->op_params.input_height; + input_dims.w = data->op_params.input_width; + input_dims.c = data->op_params.in_channels; + + cmsis_nn_dims filter_dims; + filter_dims.n = data->op_params.out_channels; + filter_dims.h = data->op_params.filter_height; + filter_dims.w = data->op_params.filter_width; + filter_dims.c = data->op_params.in_channels; + + cmsis_nn_dims bias_dims; + bias_dims.n = 1; + bias_dims.h = 1; + bias_dims.w = 1; + bias_dims.c = data->op_params.out_channels; + + cmsis_nn_dims output_dims; + output_dims.n = data->op_params.batches; + output_dims.h = data->op_params.output_height; + output_dims.w = data->op_params.output_width; + output_dims.c = data->op_params.out_channels; + + cmsis_nn_per_channel_quant_params quant_params; + quant_params.multiplier = data->per_channel_output_multiplier; + quant_params.shift = data->per_channel_output_shift; + + cmsis_nn_conv_params conv_params; + conv_params.input_offset = data->op_params.input_offset; + conv_params.output_offset = data->op_params.output_offset; + conv_params.stride.h = data->op_params.stride_height; + conv_params.stride.w = data->op_params.stride_width; + conv_params.dilation.h = 1; + conv_params.dilation.w = 1; + conv_params.padding.h = data->op_params.pad_height; + conv_params.padding.w = data->op_params.pad_width; + conv_params.activation.min = data->op_params.output_activation_min; + conv_params.activation.max = data->op_params.output_activation_max; + + cmsis_nn_context ctx; + ctx.buf = nullptr; + ctx.size = 0; + + if (data->scratch_buffer_index > -1) { + ctx.buf = context->GetScratchBuffer(context, data->scratch_buffer_index); + } + TFLITE_DCHECK_EQ(ARM_MATH_SUCCESS, + arm_convolve_wrapper_s8( + &ctx, &conv_params, &quant_params, + &input_dims, tflite::micro::GetTensorData(input), + &filter_dims, tflite::micro::GetTensorData(filter), + &bias_dims, bias == nullptr ? NULL : tflite::micro::GetTensorData(bias), + &output_dims, tflite::micro::GetTensorData(output))); + + return kTfLiteOk; +} + +TfLiteStatus eval_tflm_int8(OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + ConvParams op_params; + + op_params.input_offset = data->op_params.input_offset; + op_params.output_offset = data->op_params.output_offset; + op_params.stride_height = data->op_params.stride_height; + op_params.stride_width = data->op_params.stride_width; + op_params.dilation_height_factor = data->op_params.dilation_height; + op_params.dilation_width_factor = data->op_params.dilation_width; + op_params.padding_values.height = data->op_params.pad_height; + op_params.padding_values.width = data->op_params.pad_width; + op_params.quantized_activation_min = data->op_params.output_activation_min; + op_params.quantized_activation_max = data->op_params.output_activation_max; + + reference_integer_ops::ConvPerChannel( + op_params, + data->per_channel_output_multiplier, + data->per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + bias == nullptr ? nullptr : tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; +} + +TfLiteStatus eval_float(TfLiteConvParams* params, + const OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + ConvParams op_params; + op_params.padding_type = RuntimePaddingType(params->padding); + op_params.padding_values.width = data->op_params.pad_width; + op_params.padding_values.height = data->op_params.pad_height; + op_params.stride_width = data->op_params.stride_width; + op_params.stride_height = data->op_params.stride_height; + op_params.dilation_width_factor = data->op_params.dilation_width; + op_params.dilation_height_factor = data->op_params.dilation_height; + op_params.float_activation_min = data->activation_min_f32; + op_params.float_activation_max = data->activation_max_f32; + + reference_ops::Conv(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + bias == nullptr ? nullptr : tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + RuntimeShape(), + nullptr); + return kTfLiteOk; +} + +TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node) +{ + TfLiteStatus status = kTfLiteError; + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* params = reinterpret_cast(node->builtin_data); + OpData* data = static_cast(node->user_data); + + const auto input = tflite::micro::GetEvalInput(context, node, kInputTensor); + const auto filter = tflite::micro::GetEvalInput(context, node, kFilterTensor); + const auto bias = NumInputs(node) == 3 + ? tflite::micro::GetEvalInput(context, node, kBiasTensor) + : nullptr; + auto output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (data->supported == kMvp) { + status = eval_mvp_int8(context, data, input, filter, output); + + } else if (data->supported == kCmsisNN) { + status = eval_cmsis_int8(context, data, input, filter, bias, output); + + } else if (data->supported == kTFLMrefI8) { + status = eval_tflm_int8(data, input, filter, bias, output); + + } else if (data->supported == kTFLMrefF32) { + #if EI_TFLITE_DISABLE_CONV_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + status = eval_float(params, data, input, filter, bias, output); + } + + return status; +} + +} // namespace conv2d +} // namespace sl + +TfLiteRegistration Register_CONV_2D() { + return {/*init=*/sl::conv2d::Init, + /*free=*/nullptr, + /*prepare=*/sl::conv2d::Prepare, + /*invoke=*/sl::conv2d::Invoke, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN == 1 +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#include + +#if ESP_NN +#include "edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h" +#endif + + +long long conv_total_time = 0; + +namespace tflite { +namespace { + +struct NodeData { + OpDataConv op_data; +#if ESP_NN + int buffer_idx; +#endif +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(NodeData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + NodeData* data = static_cast(node->user_data); + const auto& params = + *(static_cast(node->builtin_data)); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + const int input_width = input->dims->data[2]; + const int input_height = input->dims->data[1]; + const int filter_width = filter->dims->data[2]; + const int filter_height = filter->dims->data[1]; + const int output_width = output->dims->data[2]; + const int output_height = output->dims->data[1]; + + // Dynamically allocate per-channel quantization parameters. + const int num_channels = filter->dims->data[kConvQuantizedDimension]; + data->op_data.per_channel_output_multiplier = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->op_data.per_channel_output_shift = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + // All per-channel quantized tensors need valid zero point and scale arrays. + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + const auto* affine_quantization = + static_cast(filter->quantization.params); + TFLITE_DCHECK(affine_quantization != nullptr); + TFLITE_DCHECK(affine_quantization->scale != nullptr); + TFLITE_DCHECK(affine_quantization->zero_point != nullptr); + + TF_LITE_ENSURE(context, + affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kConvQuantizedDimension]); + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, + affine_quantization->zero_point->size); + } + + TF_LITE_ENSURE_STATUS(CalculateOpDataConv( + context, node, params, input_width, input_height, filter_width, + filter_height, output_width, output_height, input->type, &data->op_data)); + +#if ESP_NN + if (input->type == kTfLiteInt8) { + data_dims_t input_dims = { + .width = input_width, .height = input_height, + .channels = input->dims->data[3], 1 + }; + data_dims_t output_dims = { + .width = output_width, .height = output_height, + .channels = output->dims->data[3], 1 + }; + data_dims_t filter_dims = {.width = filter_width, .height = filter_height, 0, 0}; + conv_params_t conv_params = { + .in_offset = 0, .out_offset = 0, + .stride = {params.stride_width, params.stride_height}, + .padding = {data->op_data.padding.width, data->op_data.padding.height}, + .dilation = {0, 0}, .activation = {-128, 127} + }; + + int scratch_buf_size = esp_nn_get_conv_scratch_size( + &input_dims, &filter_dims, &output_dims, &conv_params); + if (scratch_buf_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, scratch_buf_size, &data->buffer_idx)); + } else { + data->buffer_idx = -1; + } + } +#endif + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + + return kTfLiteOk; +} + +#if ESP_NN +// Fixed-point per-channel-quantization convolution Int8 function wrapper. +inline void EvalQuantizedPerChannel( + TfLiteContext* context, TfLiteNode* node, const TfLiteConvParams& params, + const NodeData& data, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + + if (dilation_width_factor == 1 && dilation_height_factor == 1) { + // Get parameters. + RuntimeShape filter_shape = tflite::micro::GetTensorShape(filter); + RuntimeShape input_shape = tflite::micro::GetTensorShape(input); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + RuntimeShape bias_shape = tflite::micro::GetTensorShape(bias); + + const int8_t *input_data = tflite::micro::GetTensorData(input); + int8_t *output_data = tflite::micro::GetTensorData(output); + + const int32_t input_offset = -data.op_data.input_zero_point; + const int32_t output_offset = data.op_data.output_zero_point; + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int pad_width = data.op_data.padding.width; + const int pad_height = data.op_data.padding.height; + + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + + // Set min and max value of the output. + const int32_t activation_min = data.op_data.output_activation_min; + const int32_t activation_max = data.op_data.output_activation_max; + + // Consistency check. + TFLITE_DCHECK_LE(activation_min, activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batch_size = MatchingDim(input_shape, 0, output_shape, 0); + const int input_depth = MatchingDim(input_shape, 3, filter_shape, 3); + const int output_depth = MatchingDim(filter_shape, 0, output_shape, 3); + + if (tflite::micro::GetTensorData(bias)) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + void *scratch_buf = NULL; + if (data.buffer_idx > -1) { + scratch_buf = context->GetScratchBuffer(context, data.buffer_idx); + } + esp_nn_set_conv_scratch_buf(scratch_buf); + + const int input_size = input_width * input_height * input_depth; + const int output_size = output_width * output_height * output_depth; + + data_dims_t input_dims = { + .width = input_width, .height = input_height, + .channels = input_depth, 1 + }; + data_dims_t output_dims = { + .width = output_width, .height = output_height, + .channels = output_depth, 1 + }; + data_dims_t filter_dims = {.width = filter_width, .height = filter_height, 0, 0}; + conv_params_t conv_params = { + .in_offset = input_offset, .out_offset = output_offset, + .stride = {stride_width, stride_height}, + .padding = {pad_width, pad_height}, + .dilation = {0, 0}, + .activation = {activation_min, activation_max} + }; + quant_data_t quant_data = { + .shift = data.op_data.per_channel_output_shift, + .mult = data.op_data.per_channel_output_multiplier + }; + + for (int i_batch = 0; i_batch < batch_size; i_batch++) { + esp_nn_conv_s8(&input_dims, input_data + i_batch * input_size, + &filter_dims, tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorData(bias), + &output_dims, output_data + i_batch * output_size, + &conv_params, &quant_data); + } + } else { + reference_integer_ops::ConvPerChannel( + ConvParamsQuantized(params, data.op_data), + data.op_data.per_channel_output_multiplier, + data.op_data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} +#endif + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kConvBiasTensor) + : nullptr; + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kConvOutputTensor); + + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto& params = + *(reinterpret_cast(node->builtin_data)); + TFLITE_DCHECK(node->user_data != nullptr); + const auto& data = *(static_cast(node->user_data)); + + TF_LITE_ENSURE_EQ(context, input->type, output->type); + TF_LITE_ENSURE_MSG(context, input->type == filter->type, + "Hybrid models are not supported on TFLite Micro."); + + long long start_time = esp_timer_get_time(); + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_CONV_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + tflite::reference_ops::Conv( + ConvParamsFloat(params, data.op_data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr); + break; + } + case kTfLiteInt8: { +#if EI_TFLITE_DISABLE_CONV_2D_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif +#if ESP_NN + EvalQuantizedPerChannel(context, node, params, data, input, filter, + bias, output); +#else + reference_integer_ops::ConvPerChannel( + ConvParamsQuantized(params, data.op_data), + data.op_data.per_channel_output_multiplier, + data.op_data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#endif + break; + } + case kTfLiteUInt8: { +#if EI_TFLITE_DISABLE_CONV_2D_IN_U8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + //EvalQuantized + reference_ops::Conv(ConvParamsQuantized(params, data.op_data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr, + nullptr); + break; + } + default: + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + long long time_this_instance = esp_timer_get_time() - start_time; + conv_total_time += time_this_instance; + //printf("time this instance: %llu\n", time_this_instance / 1000); + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_CONV_2D() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#else +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataConv)); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kConvBiasTensor) + : nullptr; + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kConvOutputTensor); + + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto& params = + *(reinterpret_cast(node->builtin_data)); + TFLITE_DCHECK(node->user_data != nullptr); + const auto& data = *(static_cast(node->user_data)); + + TF_LITE_ENSURE_EQ(context, input->type, output->type); + TF_LITE_ENSURE_MSG( + context, + input->type == filter->type || + (input->type == kTfLiteInt16 && filter->type == kTfLiteInt8) || + (input->type == kTfLiteInt8 && filter->type == kTfLiteInt4), + "Hybrid models are not supported on TFLite Micro."); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_CONV_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + tflite::reference_ops::Conv( + ConvParamsFloat(params, data), tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr); + break; + } + case kTfLiteInt16: { + switch (bias->type) { + case kTfLiteInt32: { + reference_integer_ops::ConvPerChannel( + ConvParamsQuantized(params, data), + data.per_channel_output_multiplier, data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + case kTfLiteInt64: { + reference_integer_ops::ConvPerChannel( + ConvParamsQuantized(params, data), + data.per_channel_output_multiplier, data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + default: + MicroPrintf("Bias type %s (%d) not supported.", + TfLiteTypeGetName(bias->type), bias->type); + return kTfLiteError; + } + break; + } + case kTfLiteInt8: { +#if EI_TFLITE_DISABLE_CONV_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + switch (filter->type) { + case kTfLiteInt4: { + int8_t* unpacked_filter_data = static_cast( + context->GetScratchBuffer(context, data.filter_buffer_index)); + tflite::tensor_utils::UnpackDenseInt4IntoInt8( + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(filter).FlatSize(), + unpacked_filter_data); + reference_integer_ops::ConvPerChannel( + ConvParamsQuantized(params, data), + data.per_channel_output_multiplier, data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), unpacked_filter_data, + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + case kTfLiteInt8: { + reference_integer_ops::ConvPerChannel( + ConvParamsQuantized(params, data), + data.per_channel_output_multiplier, data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + default: + MicroPrintf("Weight type %s (%d) not supported.", + TfLiteTypeGetName(filter->type), filter->type); + return kTfLiteError; + } + break; + } + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_CONV_2D() { + return tflite::micro::RegisterOp(Init, ConvPrepare, Eval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h new file mode 100644 index 0000000..2a4b63d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h @@ -0,0 +1,116 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_CONV_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_CONV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +struct OpDataConv { + TfLitePaddingValues padding; + + // Cached tensor zero point values for quantized operations. + int32_t input_zero_point; + int32_t filter_zero_point; + int32_t output_zero_point; + + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t output_multiplier; + int output_shift; + + // Per channel output multiplier and shift. + int32_t* per_channel_output_multiplier; + int32_t* per_channel_output_shift; + + // The range of the fused activation layer. For example for kNone and + // uint8_t these would be 0 and 255. + int32_t output_activation_min; + int32_t output_activation_max; + + // A buffer used to store unpacked filter values. This is used if the source + // tensor is of n-bit precision that cannot be easily processed by kernels. + int filter_buffer_index; +}; + +extern const int kConvInputTensor; +extern const int kConvWeightsTensor; +extern const int kConvBiasTensor; +extern const int kConvOutputTensor; +extern const int kConvQuantizedDimension; + +// Returns a ConvParams struct with all the parameters needed for a +// float computation. +ConvParams ConvParamsFloat(const TfLiteConvParams& params, + const OpDataConv& data); + +// Returns a ConvParams struct with all the parameters needed for a +// quantized computation. +ConvParams ConvParamsQuantized(const TfLiteConvParams& params, + const OpDataConv& data); + +TfLiteStatus CalculateOpDataConv(TfLiteContext* context, TfLiteNode* node, + const TfLiteConvParams& params, int width, + int height, int filter_width, + int filter_height, int out_width, + int out_height, const TfLiteType data_type, + OpDataConv* data); + +TfLiteStatus ConvPrepare(TfLiteContext* context, TfLiteNode* node); + +// This is the most generic TfLiteRegistration. The actual supported types may +// still be target dependent. The only requirement is that every implementation +// (reference or optimized) must define this function. +TfLiteRegistration Register_CONV_2D(); + +#if defined(XTENSA) +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int8 activations and int8 weights and always calls the reference +// implementation. +TfLiteRegistration Register_CONV_2D_INT8REF(); +#else +inline TfLiteRegistration Register_CONV_2D_INT8REF() { + return Register_CONV_2D(); +} +#endif + +#if defined(CMSIS_NN) +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int8 activations and int8 weights and uses the latency optimized +// implementations. +TfLiteRegistration Register_CONV_2D_INT8(); + +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int16 activations and int8 weights and uses the latency optimized +// implementations. +TfLiteRegistration Register_CONV_2D_INT16(); + +#else +inline TfLiteRegistration Register_CONV_2D_INT8() { return Register_CONV_2D(); } + +inline TfLiteRegistration Register_CONV_2D_INT16() { + return Register_CONV_2D(); +} +#endif + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_CONV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv_common.cpp new file mode 100644 index 0000000..fe23085 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv_common.cpp @@ -0,0 +1,204 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { + +const int kConvInputTensor = 0; +const int kConvWeightsTensor = 1; +const int kConvBiasTensor = 2; +const int kConvOutputTensor = 0; + +// Conv is quantized along dimension 0: +// https://www.tensorflow.org/lite/performance/quantization_spec +const int kConvQuantizedDimension = 0; + +// Returns a ConvParams struct with all the parameters needed for a +// float computation. +ConvParams ConvParamsFloat(const TfLiteConvParams& params, + const OpDataConv& data) { + ConvParams op_params; + CalculateActivationRange(params.activation, &op_params.float_activation_min, + &op_params.float_activation_max); + op_params.padding_type = tflite::micro::RuntimePaddingType(params.padding); + op_params.padding_values.width = data.padding.width; + op_params.padding_values.height = data.padding.height; + op_params.stride_width = params.stride_width; + op_params.stride_height = params.stride_height; + op_params.dilation_width_factor = params.dilation_width_factor; + op_params.dilation_height_factor = params.dilation_height_factor; + return op_params; +} + +// Returns a ConvParams struct with all the parameters needed for a +// quantized computation. +ConvParams ConvParamsQuantized(const TfLiteConvParams& params, + const OpDataConv& data) { + ConvParams op_params; + op_params.input_offset = -data.input_zero_point; + op_params.weights_offset = -data.filter_zero_point; + op_params.output_offset = data.output_zero_point; + op_params.output_multiplier = data.output_multiplier; + op_params.output_shift = -data.output_shift; + op_params.padding_type = tflite::micro::RuntimePaddingType(params.padding); + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.stride_height = params.stride_height; + op_params.stride_width = params.stride_width; + op_params.dilation_height_factor = params.dilation_height_factor; + op_params.dilation_width_factor = params.dilation_width_factor; + op_params.quantized_activation_min = data.output_activation_min; + op_params.quantized_activation_max = data.output_activation_max; + return op_params; +} + +TfLiteStatus CalculateOpDataConv(TfLiteContext* context, TfLiteNode* node, + const TfLiteConvParams& params, int width, + int height, int filter_width, + int filter_height, int out_width, + int out_height, const TfLiteType data_type, + OpDataConv* data) { + bool has_bias = node->inputs->size == 3; + // Check number of inputs/outputs + TF_LITE_ENSURE(context, has_bias || node->inputs->size == 2); + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + + // Matching GetWindowedOutputSize in TensorFlow. + auto padding = params.padding; + data->padding = ComputePaddingHeightWidth( + params.stride_height, params.stride_width, params.dilation_height_factor, + params.dilation_width_factor, height, width, filter_height, filter_width, + padding, &out_height, &out_width); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kConvBiasTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + // Note that quantized inference requires that all tensors have their + // parameters set. This is usually done during quantized training. + if (data_type != kTfLiteFloat32) { + int output_channels = filter->dims->data[kConvQuantizedDimension]; + + TF_LITE_ENSURE_STATUS(tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, params.activation, + &data->output_multiplier, &data->output_shift, + &data->output_activation_min, &data->output_activation_max, + data->per_channel_output_multiplier, data->per_channel_output_shift, + output_channels)); + } + + data->input_zero_point = input->params.zero_point; + data->filter_zero_point = filter->params.zero_point; + data->output_zero_point = output->params.zero_point; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(bias); + + return kTfLiteOk; +} + +TfLiteStatus ConvPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpDataConv* data = static_cast(node->user_data); + const auto& params = + *(static_cast(node->builtin_data)); + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + + const int input_width = input->dims->data[2]; + const int input_height = input->dims->data[1]; + const int filter_width = filter->dims->data[2]; + const int filter_height = filter->dims->data[1]; + const int output_width = output->dims->data[2]; + const int output_height = output->dims->data[1]; + + // Dynamically allocate per-channel quantization parameters. + if (input->type != kTfLiteFloat32) { + const int num_channels = filter->dims->data[kConvQuantizedDimension]; + data->per_channel_output_multiplier = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + } + + // All per-channel quantized tensors need valid zero point and scale arrays. + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + const auto* affine_quantization = + static_cast(filter->quantization.params); + TFLITE_DCHECK(affine_quantization != nullptr); + TFLITE_DCHECK(affine_quantization->scale != nullptr); + TFLITE_DCHECK(affine_quantization->zero_point != nullptr); + + TF_LITE_ENSURE(context, + affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kConvQuantizedDimension]); + } + + TF_LITE_ENSURE_STATUS(CalculateOpDataConv( + context, node, params, input_width, input_height, filter_width, + filter_height, output_width, output_height, input->type, data)); + + if (filter->type == kTfLiteInt4) { + int filter_size = + RuntimeShape(filter->dims->size, + reinterpret_cast(filter->dims->data)) + .FlatSize(); + context->RequestScratchBufferInArena(context, filter_size, + &data->filter_buffer_index); + } + + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv_test.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv_test.h new file mode 100644 index 0000000..cdaaefa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/conv_test.h @@ -0,0 +1,114 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_CONV_TEST_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_CONV_TEST_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/testing/micro_test.h" + +namespace tflite { +namespace testing { + +TfLiteStatus InvokeConv(TfLiteTensor* tensors, int tensors_size, + int output_length, TfLiteConvParams* conv_params, + TfLiteRegistration registration, float* output_data); + +TfLiteStatus InvokeConv(TfLiteTensor* tensors, int tensors_size, + int output_length, TfLiteConvParams* conv_params, + TfLiteRegistration registration, int8_t* output_data); + +TfLiteStatus InvokeConv(TfLiteTensor* tensors, int tensors_size, + int output_length, TfLiteConvParams* conv_params, + TfLiteRegistration registration, uint8_t* output_data); + +TfLiteStatus ValidateConvGoldens(TfLiteTensor* tensors, int tensors_size, + const float* expected_output_data, + int output_length, + TfLiteConvParams* conv_params, + TfLiteRegistration registration, + float* output_data, float tolerance = 1e-5); + +TfLiteStatus ValidateConvGoldens(TfLiteTensor* tensors, int tensors_size, + const int8_t* expected_output_data, + int output_length, + TfLiteConvParams* conv_params, + TfLiteRegistration registration, + int8_t* output_data, float tolerance = 1e-5); + +TfLiteStatus ValidateConvGoldens(TfLiteTensor* tensors, int tensors_size, + const uint8_t* expected_output_data, + int output_length, + TfLiteConvParams* conv_params, + TfLiteRegistration registration, + uint8_t* output_data, float tolerance = 1e-5); + +TfLiteStatus TestConvFloat(int* input_dims_data, const float* input_data, + int* filter_dims_data, const float* filter_data, + int* bias_dims_data, const float* bias_data, + int* output_dims_data, + const float* expected_output_data, + TfLiteConvParams* conv_params, + TfLiteRegistration registration, float* output_data); + +TfLiteStatus TestConvQuantizedPerLayer( + int* input_dims_data, const float* input_data, uint8_t* input_quantized, + float input_scale, int* filter_dims_data, const float* filter_data, + uint8_t* filter_quantized, float filter_scale, int* bias_dims_data, + const float* bias_data, int32_t* bias_quantized, int* output_dims_data, + const float* expected_output_data, uint8_t* expected_output_quantized, + float output_scale, TfLiteConvParams* conv_params, + TfLiteRegistration registration, uint8_t* output_data); + +TfLiteStatus TestConvQuantizedPerChannel( + int* input_dims_data, const float* input_data, int8_t* input_quantized, + float input_scale, int input_zero_point, int* filter_dims_data, + const float* filter_data, int8_t* filter_data_quantized, + int* bias_dims_data, const float* bias_data, int32_t* bias_data_quantized, + float* bias_scales, int* bias_zero_points, int* output_dims_data, + const float* expected_output_data, int8_t* expected_output_data_quantized, + float output_scale, int output_zero_point, TfLiteConvParams* conv_params, + TfLiteRegistration registration, int8_t* output_data, + TfLiteType tensor_weight_type = kTfLiteNoType); + +TfLiteStatus TestConvQuantizedPerChannel( + int* input_dims_data, const float* input_data, int16_t* input_quantized, + float input_scale, int input_zero_point, int* filter_dims_data, + const float* filter_data, int8_t* filter_data_quantized, + int* bias_dims_data, const float* bias_data, + std::int64_t* bias_data_quantized, float* bias_scales, + int* bias_zero_points, int* output_dims_data, + const float* expected_output_data, int16_t* expected_output_data_quantized, + float output_scale, int output_zero_point, TfLiteConvParams* conv_params, + TfLiteRegistration registration, int16_t* output_data); + +TfLiteStatus TestConvQuantizedPerChannel( + int* input_dims_data, const float* input_data, int16_t* input_quantized, + float input_scale, int input_zero_point, int* filter_dims_data, + const float* filter_data, int8_t* filter_data_quantized, + int* bias_dims_data, const float* bias_data, int32_t* bias_data_quantized, + float* bias_scales, int* bias_zero_points, int* output_dims_data, + const float* expected_output_data, int16_t* expected_output_data_quantized, + float output_scale, int output_zero_point, TfLiteConvParams* conv_params, + TfLiteRegistration registration, int16_t* output_data); + +} // namespace testing +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_CONV_TEST_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/cumsum.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/cumsum.cpp new file mode 100644 index 0000000..bdc888b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/cumsum.cpp @@ -0,0 +1,175 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/cumsum.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kAxisTensor = 1; +constexpr int kOutputTensor = 0; + +constexpr int kCumSumIntegerShift = 20; + +// only used with INT8 tensors +struct OpData { + int32_t output_activation_min; + int32_t output_activation_max; + int32_t input_offset; + int32_t output_offset; + int32_t input_multiplier; + int32_t output_multiplier; + int input_shift; + int output_shift; + int left_shift; +}; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* axis = + micro_context->AllocateTempInputTensor(node, kAxisTensor); + + TF_LITE_ENSURE(context, + input->type == kTfLiteFloat32 || input->type == kTfLiteInt8); + TF_LITE_ENSURE_EQ(context, axis->type, kTfLiteInt32); + + TF_LITE_ENSURE_EQ(context, NumElements(axis), 1); + + TF_LITE_ENSURE(context, NumDimensions(input) >= 1); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + TF_LITE_ENSURE_EQ(context, input->type, output->type); + TF_LITE_ENSURE(context, HaveSameShapes(input, output)); + + if (output->type == kTfLiteInt8) { + node->user_data = + context->AllocatePersistentBuffer(context, sizeof(OpData)); + OpData* data = static_cast(node->user_data); + + // 8bit -> 8bit general quantized path, with general rescalings + data->input_offset = -input->params.zero_point; + data->output_offset = output->params.zero_point; + data->left_shift = kCumSumIntegerShift; + const double twice_max_input_scale = + 2 * static_cast(input->params.scale); + const double real_input_multiplier = + static_cast(input->params.scale) / twice_max_input_scale; + const double real_output_multiplier = + twice_max_input_scale / + ((1 << data->left_shift) * static_cast(output->params.scale)); + + QuantizeMultiplierSmallerThanOneExp( + real_input_multiplier, &data->input_multiplier, &data->input_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->output_multiplier, &data->output_shift); + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, kTfLiteActNone, output, &data->output_activation_min, + &data->output_activation_max)); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(axis); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* axis_tensor = + tflite::micro::GetEvalInput(context, node, kAxisTensor); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + auto* cs_params = static_cast(node->builtin_data); + auto input_shape = tflite::micro::GetTensorShape(input); + + int32_t axis = *tflite::micro::GetTensorData(axis_tensor); + if (axis < 0) axis += input_shape.DimensionsCount(); + + if (axis < 0 || axis >= input_shape.DimensionsCount()) { + MicroPrintf("CUMSUM Invalid axis: %d", axis); + return kTfLiteError; + } + + switch (input->type) { + case kTfLiteFloat32: { + reference_ops::CumSum(tflite::micro::GetTensorData(input), + input_shape, axis, cs_params->exclusive, + cs_params->reverse, + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + + case kTfLiteInt8: { + auto* data = static_cast(node->user_data); + ArithmeticParams params; + params.left_shift = data->left_shift; + params.input1_offset = data->input_offset; + params.input1_multiplier = data->input_multiplier; + params.input1_shift = data->input_shift; + params.output_offset = data->output_offset; + params.output_multiplier = data->output_multiplier; + params.output_shift = data->output_shift; + SetActivationParams(data->output_activation_min, + data->output_activation_max, ¶ms); + reference_ops::CumSum(params, tflite::micro::GetTensorData(input), + input_shape, axis, cs_params->exclusive, + cs_params->reverse, + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + + default: { + MicroPrintf("CUMSUM only supports FLOAT32 and INT8, got %s.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } + + return kTfLiteError; +} + +} // namespace + +TfLiteRegistration Register_CUMSUM() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depth_to_space.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depth_to_space.cpp new file mode 100644 index 0000000..72e1545 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depth_to_space.cpp @@ -0,0 +1,142 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depth_to_space.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +// input/output tensor shape rank associations +constexpr int kBatchRank = 0; +constexpr int kHeightRank = 1; +constexpr int kWidthRank = 2; +constexpr int kDepthRank = 3; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + auto* params = + reinterpret_cast(node->builtin_data); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_EQ(context, NumDimensions(input), 4); + + auto data_type = output->type; + TF_LITE_ENSURE(context, + data_type == kTfLiteFloat32 || data_type == kTfLiteInt8); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + const int block_size = params->block_size; + TF_LITE_ENSURE(context, block_size > 0); + const int input_height = input->dims->data[kHeightRank]; + const int input_width = input->dims->data[kWidthRank]; + const int input_channels = input->dims->data[kDepthRank]; + int output_height = input_height * block_size; + int output_width = input_width * block_size; + int output_channels = input_channels / block_size / block_size; + + TF_LITE_ENSURE_EQ(context, input_height, output_height / block_size); + TF_LITE_ENSURE_EQ(context, input_width, output_width / block_size); + TF_LITE_ENSURE_EQ(context, input_channels, + output_channels * block_size * block_size); + + // We must update the output tensor dimensions. + // The dims storage is expected to be the same area in memory + // for both TfLiteTensor and TfLiteEvalTensor. This is important + // because TfLiteTensor in the MicroInterpreter is a temporary + // allocation. For the KernelRunner interpreter, TfLiteEvalTensor + // is a temporary allocation. We must therefore relocate the dims + // from the FlatBuffer to the persistant storage arena. + TfLiteEvalTensor* output_eval = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE_OK(context, tflite::micro::CreateWritableTensorDimsWithCopy( + context, output, output_eval)); + output->dims->data[kBatchRank] = input->dims->data[kBatchRank]; + output->dims->data[kHeightRank] = output_height; + output->dims->data[kWidthRank] = output_width; + output->dims->data[kDepthRank] = output_channels; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = + reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + tflite::DepthToSpaceParams op_params; + op_params.block_size = static_cast(params->block_size); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: + reference_ops::DepthToSpace(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: + reference_ops::DepthToSpace(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("DEPTH_TO_SPACE only supports FLOAT32 and INT8, got %s.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_DEPTH_TO_SPACE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.cpp new file mode 100644 index 0000000..000bb0b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.cpp @@ -0,0 +1,2106 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +struct OpData { + OpDataConv reference_op_data; + + // Index to buffer for optimizations if applicable. + int buffer_idx; +}; + +// Always inline for optimal code size. +void PopulateDwConvParams( + cmsis_nn_dw_conv_params* const dw_conv_params, + cmsis_nn_per_channel_quant_params* const quant_params, + cmsis_nn_dims* const input_dims, cmsis_nn_dims* const filter_dims, + cmsis_nn_dims* const bias_dims, cmsis_nn_dims* const output_dims, + const TfLiteDepthwiseConvParams& params, const OpData& data, + const TfLiteEvalTensor* input, const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, TfLiteEvalTensor* output) + __attribute__((always_inline)); + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto& params = + *(reinterpret_cast(node->builtin_data)); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kDepthwiseConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kDepthwiseConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kDepthwiseConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + const TfLiteType data_type = input->type; + int input_width = SizeOfDimension(input, 2); + int input_height = SizeOfDimension(input, 1); + int filter_width = SizeOfDimension(filter, 2); + int filter_height = SizeOfDimension(filter, 1); + int output_width = SizeOfDimension(output, 2); + int output_height = SizeOfDimension(output, 1); + + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + if (input->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, input->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + } + + // All per-channel quantized tensors need valid zero point and scale arrays. + const auto* affine_quantization = + reinterpret_cast( + filter->quantization.params); + TF_LITE_ENSURE(context, affine_quantization); + TF_LITE_ENSURE(context, affine_quantization->scale); + TF_LITE_ENSURE(context, affine_quantization->zero_point); + TF_LITE_ENSURE( + context, affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kDepthwiseConvQuantizedDimension]); + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, + affine_quantization->zero_point->size); + + // Allocate memory for per-channel quantization parameters + const int num_channels = + filter->dims->data[kDepthwiseConvQuantizedDimension]; + + data->reference_op_data.per_channel_output_multiplier = + reinterpret_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->reference_op_data.per_channel_output_shift = + reinterpret_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + } + + if (filter->type == kTfLiteInt4) { + int filter_size = + RuntimeShape(filter->dims->size, + reinterpret_cast(filter->dims->data)) + .FlatSize(); + context->RequestScratchBufferInArena( + context, filter_size, &data->reference_op_data.filter_buffer_index); + } + + TF_LITE_ENSURE_STATUS(CalculateOpDataDepthwiseConv( + context, node, params, input_width, input_height, filter_width, + filter_height, output_width, output_height, data_type, + &data->reference_op_data)); + + if (input->type == kTfLiteInt8) { + RuntimeShape input_shape = GetTensorShape(input); + RuntimeShape output_shape = GetTensorShape(output); + RuntimeShape filter_shape = GetTensorShape(filter); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + const int batch_size = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(output_shape, 3, filter_shape, 3); + TFLITE_DCHECK_EQ(batch_size, 1); /* Only batch = 1 is supported */ + + cmsis_nn_dims input_dims; + input_dims.n = batch_size; + input_dims.h = input_height; + input_dims.w = input_width; + input_dims.c = input_shape.Dims(3); + + cmsis_nn_dims filter_dims; + filter_dims.n = 1; + filter_dims.h = filter_height; + filter_dims.w = filter_width; + filter_dims.c = output_depth; + + cmsis_nn_dims output_dims; + output_dims.n = batch_size; + output_dims.h = output_height; + output_dims.w = output_width; + output_dims.c = output_depth; + + cmsis_nn_dw_conv_params dw_conv_params; + dw_conv_params.padding.h = data->reference_op_data.padding.height; + dw_conv_params.padding.w = data->reference_op_data.padding.width; + dw_conv_params.dilation.h = params.dilation_height_factor; + dw_conv_params.dilation.w = params.dilation_width_factor; + + const int32_t buf_size = arm_depthwise_conv_wrapper_s8_get_buffer_size( + &dw_conv_params, &input_dims, &filter_dims, &output_dims); + + if (buf_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, buf_size, &data->buffer_idx)); + } else { + data->buffer_idx = -1; + } + } + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + + return kTfLiteOk; +} + +inline void PopulateDwConvParams( + cmsis_nn_dw_conv_params* const dw_conv_params, + cmsis_nn_per_channel_quant_params* const quant_params, + cmsis_nn_dims* const input_dims, cmsis_nn_dims* const filter_dims, + cmsis_nn_dims* const bias_dims, cmsis_nn_dims* const output_dims, + const TfLiteDepthwiseConvParams& params, const OpData& data, + const TfLiteEvalTensor* input, const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, TfLiteEvalTensor* output) { + dw_conv_params->dilation.h = params.dilation_height_factor; + dw_conv_params->dilation.w = params.dilation_width_factor; + + dw_conv_params->input_offset = -data.reference_op_data.input_zero_point; + dw_conv_params->output_offset = data.reference_op_data.output_zero_point; + dw_conv_params->stride.h = params.stride_height; + dw_conv_params->stride.w = params.stride_width; + dw_conv_params->padding.h = data.reference_op_data.padding.height; + dw_conv_params->padding.w = data.reference_op_data.padding.width; + + dw_conv_params->activation.min = data.reference_op_data.output_activation_min; + dw_conv_params->activation.max = data.reference_op_data.output_activation_max; + + dw_conv_params->ch_mult = params.depth_multiplier; + + quant_params->multiplier = + data.reference_op_data.per_channel_output_multiplier; + quant_params->shift = data.reference_op_data.per_channel_output_shift; + + RuntimeShape filter_shape = tflite::micro::GetTensorShape(filter); + RuntimeShape input_shape = tflite::micro::GetTensorShape(input); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + RuntimeShape bias_shape = tflite::micro::GetTensorShape(bias); + + TFLITE_DCHECK_LE(dw_conv_params->activation.min, + dw_conv_params->activation.max); + + const int batch_size = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + + if (tflite::micro::GetOptionalTensorData(bias)) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + input_dims->n = batch_size; + input_dims->h = input_shape.Dims(1); + input_dims->w = input_shape.Dims(2); + input_dims->c = input_shape.Dims(3); + + filter_dims->n = filter_shape.Dims(0); + filter_dims->h = filter_shape.Dims(1); + filter_dims->w = filter_shape.Dims(2); + filter_dims->c = output_depth; + + bias_dims->n = 1; + bias_dims->h = 1; + bias_dims->w = 1; + bias_dims->c = output_depth; + + output_dims->n = batch_size; + output_dims->h = output_shape.Dims(1); + output_dims->w = output_shape.Dims(2); + output_dims->c = output_depth; +} + +void EvalQuantizedPerChannel(TfLiteContext* context, TfLiteNode* node, + const TfLiteDepthwiseConvParams& params, + const OpData& data, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + cmsis_nn_dw_conv_params dw_conv_params; + cmsis_nn_per_channel_quant_params quant_params; + cmsis_nn_dims input_dims; + cmsis_nn_dims filter_dims; + cmsis_nn_dims bias_dims; + cmsis_nn_dims output_dims; + + PopulateDwConvParams(&dw_conv_params, &quant_params, &input_dims, + &filter_dims, &bias_dims, &output_dims, params, data, + input, filter, bias, output); + + cmsis_nn_context ctx; + ctx.buf = nullptr; + /* 'size' is unused */ + ctx.size = 0; + + if (data.buffer_idx > -1) { + ctx.buf = context->GetScratchBuffer(context, data.buffer_idx); + } + + TFLITE_DCHECK_EQ( + arm_depthwise_conv_wrapper_s8( + &ctx, &dw_conv_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, + tflite::micro::GetOptionalTensorData(bias), &output_dims, + tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); +} + +void EvalQuantizedPerChannel16x8(TfLiteContext* context, TfLiteNode* node, + const TfLiteDepthwiseConvParams& params, + const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + cmsis_nn_dw_conv_params dw_conv_params; + cmsis_nn_per_channel_quant_params quant_params; + cmsis_nn_dims input_dims; + cmsis_nn_dims filter_dims; + cmsis_nn_dims bias_dims; + cmsis_nn_dims output_dims; + + PopulateDwConvParams(&dw_conv_params, &quant_params, &input_dims, + &filter_dims, &bias_dims, &output_dims, params, data, + input, filter, bias, output); + + cmsis_nn_context ctx; + ctx.buf = nullptr; + /* 'size' is unused */ + ctx.size = 0; + + TFLITE_DCHECK_EQ( + arm_depthwise_conv_s16( + &ctx, &dw_conv_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, + tflite::micro::GetOptionalTensorData(bias), &output_dims, + tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + const auto& params = + *(reinterpret_cast(node->builtin_data)); + const OpData& data = *(static_cast(node->user_data)); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kDepthwiseConvOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kDepthwiseConvBiasTensor) + : nullptr; + + TfLiteEvalTensor filter_int8 = tflite::micro::MakeUnpackedInt4Tensor( + context, data.reference_op_data.filter_buffer_index, filter); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + tflite::reference_ops::DepthwiseConv( + DepthwiseConvParamsFloat(params, data.reference_op_data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + switch (filter_int8.type) { + case kTfLiteInt8: { + EvalQuantizedPerChannel(context, node, params, data, input, + &filter_int8, bias, output); + break; + } + default: { + MicroPrintf("Filter type %s (%d) not supported.", + TfLiteTypeGetName(filter->type), filter->type); + return kTfLiteError; + } + } + break; + case kTfLiteInt16: + EvalQuantizedPerChannel16x8(context, node, params, data, input, filter, + bias, output); + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus EvalInt8(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + const auto& params = + *(reinterpret_cast(node->builtin_data)); + const OpData& data = *(static_cast(node->user_data)); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kDepthwiseConvOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kDepthwiseConvBiasTensor) + : nullptr; + + TfLiteEvalTensor filter_int8 = tflite::micro::MakeUnpackedInt4Tensor( + context, data.reference_op_data.filter_buffer_index, filter); + + EvalQuantizedPerChannel(context, node, params, data, input, &filter_int8, + bias, output); + return kTfLiteOk; +} + +TfLiteStatus EvalInt16x8(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + const auto& params = + *(reinterpret_cast(node->builtin_data)); + const OpData& data = *(static_cast(node->user_data)); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kDepthwiseConvOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kDepthwiseConvBiasTensor) + : nullptr; + + EvalQuantizedPerChannel16x8(context, node, params, data, input, filter, bias, + output); + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_DEPTHWISE_CONV_2D() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +TfLiteRegistration Register_DEPTHWISE_CONV_2D_INT8() { + return tflite::micro::RegisterOp(Init, Prepare, EvalInt8); +} + +TfLiteRegistration Register_DEPTHWISE_CONV_2D_INT16() { + return tflite::micro::RegisterOp(Init, Prepare, EvalInt16x8); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h" + +#include "mli_api.h" // NOLINT +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_uint8.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_function_specializations.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kFilterTensor = 1; +constexpr int kBiasTensor = 2; +constexpr int kOutputTensor = 0; + +// Depthwise conv is quantized along dimension 3: +// https://www.tensorflow.org/lite/performance/quantization_spec +constexpr int kDepthwiseConvQuantizedDimension = 3; + +struct OpData { + TfLitePaddingValues padding; + + // Cached tensor zero point values for quantized operations. + int32_t input_zero_point; + int32_t filter_zero_point; + int32_t output_zero_point; + + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t output_multiplier; + int output_shift; + + // Per channel output multiplier and shift. + int32_t* per_channel_output_multiplier; + int32_t* per_channel_output_shift; +#ifdef MLI_2_0 + int8_t* per_channel_scale_frac_bits; +#endif + + // The range of the fused activation layer. For example for kNone and + // uint8_t these would be 0 and 255. + int32_t output_activation_min; + int32_t output_activation_max; + + // The result of checking if MLI optimized version of tensors can be used. + bool is_mli_applicable; + + // Tensors in MLI format. + mutable ops::micro::MliTensorInterface mli_in; + mutable ops::micro::MliTensorInterface mli_weights; + mutable ops::micro::MliTensorInterface mli_bias; + mutable ops::micro::MliTensorInterface mli_out; + mli_conv2d_cfg* cfg; + + // Pointer to the required depthwise function. For “channel multiplier” + // functionality group convolution is used. + depthwise_func_ptr p_mli_krn_depthwise_conv2d_sa8_sa8_sa32; +}; + +bool IsMliApplicable(TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* filter, const TfLiteTensor* bias, + const TfLiteDepthwiseConvParams* params) { + const auto* affine_quantization = + reinterpret_cast(filter->quantization.params); + +#ifndef MLI_2_0 + const int in_ch = SizeOfDimension(input, 3); + const int filters_num = SizeOfDimension(filter, 3); +#endif + + // MLI optimized version only supports int8_t datatype, dilation factor of 1 + // and per-axis quantization of weights (no broadcasting/per-tensor). For + // MLI 1.1 (in_ch == filters_num) || (in_ch == 1)) is used to prevent usage of + // channel multiplier logic for multichannel input. + + bool ret_val = (filter->type == kTfLiteInt8) && + (input->type == kTfLiteInt8) && (bias->type == kTfLiteInt32) && + (params->dilation_width_factor == 1) && + (params->dilation_height_factor == 1) && + (affine_quantization->scale->size == +#ifdef MLI_2_0 + filter->dims->data[kDepthwiseConvQuantizedDimension]); +#else + filter->dims->data[kDepthwiseConvQuantizedDimension]) && + ((in_ch == filters_num) || (in_ch == 1)); +#endif + return ret_val; +} + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node, + TfLiteDepthwiseConvParams* params, int width, + int height, int filter_width, int filter_height, + const TfLiteType data_type, OpData* data) { + bool has_bias = node->inputs->size == 3; + // Check number of inputs/outputs + TF_LITE_ENSURE(context, has_bias || node->inputs->size == 2); + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + + int unused_output_height, unused_output_width; + data->padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, 1, 1, height, width, + filter_height, filter_width, params->padding, &unused_output_height, + &unused_output_width); + + // Note that quantized inference requires that all tensors have their + // parameters set. This is usually done during quantized training. +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kFilterTensor); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kBiasTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + if (data_type != kTfLiteFloat32 && !data->is_mli_applicable) { + int num_channels = filter->dims->data[kDepthwiseConvQuantizedDimension]; + + return tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, params->activation, + &data->output_multiplier, &data->output_shift, + &data->output_activation_min, &data->output_activation_max, + data->per_channel_output_multiplier, + reinterpret_cast(data->per_channel_output_shift), num_channels); + } + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(bias); + micro_context->DeallocateTempTfLiteTensor(output); + +#endif + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* params = + reinterpret_cast(node->builtin_data); + OpData* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, kOutputTensor); + const TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, kInputTensor); + const TfLiteTensor* filter = micro_context->AllocateTempInputTensor(node, kFilterTensor); + const TfLiteTensor* bias = micro_context->AllocateTempInputTensor(node, kBiasTensor); + const TfLiteType data_type = input->type; + int width = SizeOfDimension(input, 2); + int height = SizeOfDimension(input, 1); + +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + int filter_width = SizeOfDimension(filter, 1); + int filter_height = SizeOfDimension(filter, 0); +#else + int filter_width = SizeOfDimension(filter, 2); + int filter_height = SizeOfDimension(filter, 1); +#endif + + // Per channel quantization is only needed for int8 inference. For other + // quantized types, only a single scale and zero point is needed. + const int num_channels = filter->dims->data[kDepthwiseConvQuantizedDimension]; + // Dynamically allocate per-channel quantization parameters. + data->per_channel_output_multiplier = + reinterpret_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = + reinterpret_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + data->is_mli_applicable = + IsMliApplicable(context, input, filter, bias, params); + + // All per-channel quantized tensors need valid zero point and scale arrays. + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + const auto* affine_quantization = + reinterpret_cast( + filter->quantization.params); + TF_LITE_ENSURE(context, affine_quantization); + TF_LITE_ENSURE(context, affine_quantization->scale); + TF_LITE_ENSURE(context, affine_quantization->zero_point); + TF_LITE_ENSURE( + context, affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kDepthwiseConvQuantizedDimension]); + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, + affine_quantization->zero_point->size); + } + + TF_LITE_ENSURE_STATUS(CalculateOpData(context, node, params, width, height, + filter_width, filter_height, data_type, + data)); + + data->input_zero_point = input->params.zero_point; + data->filter_zero_point = filter->params.zero_point; + data->output_zero_point = output->params.zero_point; + + if (data->is_mli_applicable) { + data->mli_in = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_weights = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_bias = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_out = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->cfg = static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_conv2d_cfg))); + +#ifdef MLI_2_0 + const int num_buffers = 2; + data->per_channel_scale_frac_bits = + static_cast(context->AllocatePersistentBuffer( + context, num_buffers * num_channels * sizeof(int16_t))); +#endif + + // Reuse space allocated for OpData parameters. +#ifdef MLI_2_0 + *data->mli_weights.Scale() = + reinterpret_cast(data->per_channel_output_multiplier); + *data->mli_bias.Scale() = + reinterpret_cast(data->per_channel_output_multiplier) + + num_channels; +#else + *data->mli_weights.Scale() = + static_cast(data->per_channel_output_multiplier); + *data->mli_bias.Scale() = + static_cast(data->per_channel_output_shift); +#endif + +#ifdef MLI_2_0 + *data->mli_weights.ZeroPoint() = + reinterpret_cast(data->per_channel_output_shift); + *data->mli_bias.ZeroPoint() = + reinterpret_cast(data->per_channel_output_shift) + + num_channels; +#else + *data->mli_weights.ZeroPoint() = + reinterpret_cast(&data->filter_zero_point); + *data->mli_bias.ZeroPoint() = + reinterpret_cast(&data->filter_zero_point) + sizeof(int16_t); +#endif + +#ifdef MLI_2_0 + *data->mli_weights.ScaleFracBits() = + reinterpret_cast(data->per_channel_scale_frac_bits); + *data->mli_bias.ScaleFracBits() = + reinterpret_cast(data->per_channel_scale_frac_bits) + + num_channels; +#endif + + ops::micro::ConvertToMliTensor(input, &data->mli_in); + ops::micro::ConvertToMliTensorPerChannel(filter, &data->mli_weights, + /* is_bias_tensor = */ false); + ops::micro::ConvertToMliTensorPerChannel(bias, &data->mli_bias, + /* is_bias_tensor = */ true); +#ifdef MLI_2_0 + ops::micro::AdjustBiasTensor(&data->mli_bias, &data->mli_in, + &data->mli_weights); +#endif + ops::micro::ConvertToMliTensor(output, &data->mli_out); + +#ifdef MLI_2_0 + // Choose group convolution function for "channel multiplier" functionality. + const int in_ch = SizeOfDimension(input, 3); + const int filters_num = SizeOfDimension(filter, 3); + const int channels_num = SizeOfDimension(filter, 2); + if (in_ch == filters_num && channels_num == 1) { + data->p_mli_krn_depthwise_conv2d_sa8_sa8_sa32 = + mli_krn_depthwise_conv2d(data->mli_weights.MliTensor()); + } else { + data->p_mli_krn_depthwise_conv2d_sa8_sa8_sa32 = + mli_krn_group_conv2d(data->mli_weights.MliTensor()); + } +#else + data->p_mli_krn_depthwise_conv2d_sa8_sa8_sa32 = + mli_krn_depthwise_conv2d(data->mli_weights.MliTensor(), data->cfg); +#endif + +#ifdef MLI_2_0 + data->cfg->dilation_width = 1; + data->cfg->dilation_height = 1; +#endif + + if (data->output_activation_min == -128 && + data->output_activation_max == 127) { + data->cfg->relu.type = MLI_RELU_NONE; + } else if (params->activation == kTfLiteActRelu) { + data->cfg->relu.type = MLI_RELU_GEN; + } else if (params->activation == kTfLiteActRelu6) { + data->cfg->relu.type = MLI_RELU_6; + } else if (params->activation == kTfLiteActReluN1To1) { + data->cfg->relu.type = MLI_RELU_1; + } else { + data->cfg->relu.type = MLI_RELU_NONE; + } + + data->cfg->stride_width = params->stride_width; + data->cfg->stride_height = params->stride_height; + if (params->padding == kTfLitePaddingValid) { + data->cfg->padding_left = 0; + data->cfg->padding_right = 0; + data->cfg->padding_top = 0; + data->cfg->padding_bottom = 0; + } else { + data->cfg->padding_left = data->padding.width; + data->cfg->padding_right = + data->padding.width + data->padding.width_offset; + data->cfg->padding_top = data->padding.height; + data->cfg->padding_bottom = + data->padding.height + data->padding.height_offset; + } + } + return kTfLiteOk; +} + +void EvalFloat(TfLiteContext* context, TfLiteNode* node, + TfLiteDepthwiseConvParams* params, const OpData& data, + const TfLiteEvalTensor* input, const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + float output_activation_min, output_activation_max; + CalculateActivationRange(params->activation, &output_activation_min, + &output_activation_max); + + tflite::DepthwiseParams op_params; + // Padding type is ignored, but still set. + op_params.padding_type = PaddingType::kSame; + op_params.padding_values.width = data.padding.width; + op_params.padding_values.height = data.padding.height; + op_params.stride_width = params->stride_width; + op_params.stride_height = params->stride_height; + op_params.dilation_width_factor = params->dilation_width_factor; + op_params.dilation_height_factor = params->dilation_height_factor; + op_params.depth_multiplier = params->depth_multiplier; + op_params.float_activation_min = output_activation_min; + op_params.float_activation_max = output_activation_max; + + tflite::reference_ops::DepthwiseConv( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf("Type %s (%d) is not supported by ARC MLI Library.", + TfLiteTypeGetName(input->type), input->type); +#endif +} +TfLiteStatus EvalMliQuantizedPerChannel( + TfLiteContext* context, TfLiteNode* node, TfLiteDepthwiseConvParams* params, + const OpData& data, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + // Run Depthwise Conv MLI kernel + // MLI optimized version only supports int8_t dataype and dilation factor of 1 + if (data.is_mli_applicable) { + // Copy configuration data from external to local memory + mli_conv2d_cfg cfg_local = *data.cfg; + + ops::micro::MliTensorAttachBuffer(input, &data.mli_in); + ops::micro::MliTensorAttachBuffer(filter, &data.mli_weights); + ops::micro::MliTensorAttachBuffer(bias, &data.mli_bias); + ops::micro::MliTensorAttachBuffer(output, &data.mli_out); + + // for height slicing + const int height_dimension = 1; + int in_slice_height = 0; + int out_slice_height = 0; + uint32_t* mli_weights_shape = data.mli_weights.Shape(); +#ifdef MLI_2_0 + const int kernel_height = + static_cast(mli_weights_shape[KRNL_DW_H_DIM_HW1N]); +#else + const int kernel_height = + static_cast(mli_weights_shape[KRNL_DW_H_DIM_HWC]); +#endif + const int overlap = kernel_height - cfg_local.stride_height; + + // for weight slicing (on output channels) + // HWCN layout for weights, output channel dimension is the first dimension. + const int weight_out_ch_dimension = 3; + // bias has only 1 dimension + const int bias_out_ch_dimension = 0; + // Batch-Height-Width-Channel layout means last dimension is output + // channels. + const int out_tensor_ch_dimension = 3; + const int32_t in_channels = data.mli_in.Shape()[out_tensor_ch_dimension]; + const int32_t out_channels = data.mli_out.Shape()[out_tensor_ch_dimension]; + int slice_channels = + static_cast(mli_weights_shape[weight_out_ch_dimension]); + + // Tensors for data in fast (local) memory + // and config to copy data from external to local memory + mli_tensor weights_local = *data.mli_weights.MliTensor(); + mli_tensor bias_local = *data.mli_bias.MliTensor(); + mli_tensor in_local = *data.mli_in.MliTensor(); + mli_tensor out_local = + *data.mli_out.MliTensor(); // this assumes that output shape + // is already filled in the tensor struct. + + ops::micro::MliTensorInterface weights_local_interface(&weights_local); + ops::micro::MliTensorInterface bias_local_interface(&bias_local); + ops::micro::MliTensorInterface in_local_interface(&in_local); + ops::micro::MliTensorInterface out_local_interface(&out_local); + + mli_mov_cfg_t copy_config; + mli_mov_cfg_for_copy(©_config); + + TF_LITE_ENSURE_STATUS(ops::micro::get_arc_scratch_buffer_for_conv_tensors( + context, &in_local_interface, &weights_local_interface, + &bias_local_interface, &out_local_interface)); + + /* is_local indicates that the tensor is already in local memory, + so in that case the original tensor can be used, + and there is no need to copy it to the local tensor*/ + const bool in_is_local = + in_local_interface.Data() == data.mli_in.Data(); + const bool out_is_local = + out_local_interface.Data() == data.mli_out.Data(); + const bool w_is_local = weights_local_interface.Data() == + data.mli_weights.Data(); + const bool b_is_local = + bias_local_interface.Data() == data.mli_bias.Data(); + + TF_LITE_ENSURE_STATUS(ops::micro::arc_scratch_buffer_calc_slice_size_io( + &in_local_interface, &out_local_interface, kernel_height, + cfg_local.stride_height, cfg_local.padding_top, + cfg_local.padding_bottom, &in_slice_height, &out_slice_height)); + TF_LITE_ENSURE_STATUS( + ops::micro::arc_scratch_buffer_calc_slice_size_weights( + &weights_local_interface, &bias_local_interface, + weight_out_ch_dimension, &slice_channels)); + + /* if input channels is not equal to output channels, a channel multiplier + is used. in this case the slice channels needs to be rounded down to a + multiple of the input channels */ + if (in_channels != out_channels) { + slice_channels = (slice_channels / in_channels) * in_channels; + } + + ops::micro::TensorSlicer b_slice(data.mli_bias.MliTensor(), + bias_out_ch_dimension, slice_channels); + ops::micro::TensorSlicer w_slice(data.mli_weights.MliTensor(), + weight_out_ch_dimension, slice_channels, 0, + 0, 0, true); + ops::micro::TensorSlicer out_ch_slice(data.mli_out.MliTensor(), + out_tensor_ch_dimension, + slice_channels, 0, 0, 0, true); + ops::micro::TensorSlicer in_ch_slice(data.mli_in.MliTensor(), + out_tensor_ch_dimension, + slice_channels, 0, 0, 0, true); + + mli_tensor* w_ptr = w_is_local ? w_slice.Sub() : &weights_local; + mli_tensor* b_ptr = b_is_local ? b_slice.Sub() : &bias_local; + + void* input_buffer_ptr = NULL; + uint32_t input_buffer_size = 0; + int padding_top = cfg_local.padding_top; + int padding_bottom = cfg_local.padding_bottom; + + while (!w_slice.Done()) { + mli_mov_tensor_sync(w_slice.Sub(), ©_config, w_ptr); + mli_mov_tensor_sync(b_slice.Sub(), ©_config, b_ptr); + + /* input tensor is already sliced in the channel dimension. + out_ch_slice.Sub() is the tensor for the amount of channels of this + iteration of the weight slice loop. This tensor needs to be further + sliced over the batch and height dimension. in_ch_slice.Sub() tensor + contains batches of HWC tensors. so it is a 4 dimensional tensor. because + the mli kernel will process one HWC tensor at a time, the 4 dimensional + tensor needs to be sliced into nBatch 3 dimensional tensors. on top of + that there could be a need to also slice in the Height dimension. for that + the sliceHeight has been calculated. The tensor slicer is configured that + it will completely slice the nBatch dimension (0) and slice the height + dimension (1) in chunks of 'sliceHeight' */ + ops::micro::TensorSlicer in_slice(in_ch_slice.Sub(), height_dimension, + in_slice_height, padding_top, + padding_bottom, overlap); + + /* output tensor is already sliced in the output channel dimension. + out_ch_slice.Sub() is the tensor for the amount of output channels of this + iteration of the weight slice loop. This tensor needs to be further + sliced over the batch and height dimension. */ + ops::micro::TensorSlicer out_slice(out_ch_slice.Sub(), height_dimension, + out_slice_height); + + /* setup the pointers to the local or remote tensor to make the code + * inside the loop easier. */ + mli_tensor* in_ptr = in_is_local ? in_slice.Sub() : &in_local; + mli_tensor* out_ptr = out_is_local ? out_slice.Sub() : &out_local; + + while (!out_slice.Done()) { + if (!out_is_local) { + ops::micro::PrepareLocalTensor(out_slice.Sub(), &out_local); + ops::micro::PrepareLocalTensor(in_slice.Sub(), &in_local); + } + TF_LITE_ENSURE(context, !in_slice.Done()); + cfg_local.padding_top = in_slice.GetPaddingPre(); + cfg_local.padding_bottom = in_slice.GetPaddingPost(); + + // if same input copy as previous iteration, skip the copy of input +#ifdef MLI_2_0 + if ((in_slice.Sub()->data.mem.pi8 != input_buffer_ptr) || + (mli_hlp_count_elem_num(in_slice.Sub(), 0) != input_buffer_size)) { + mli_mov_tensor_sync(in_slice.Sub(), ©_config, in_ptr); + input_buffer_ptr = in_slice.Sub()->data.mem.pi8; + input_buffer_size = mli_hlp_count_elem_num(in_slice.Sub(), 0); + } + +#ifdef MLI_2_0_KRNL_TEST + // Checking conditions here to prevent usage non-contiguous buffer + // memory. + if (mli_weights_shape[weight_out_ch_dimension] != + w_slice.Sub()->shape[3]) { + MicroPrintf("Slicing is not supported with real-time permutation."); + return kTfLiteError; + } + uint8_t dim_order[] = {1, 2, 0, 3}; + ops::micro::change_shape(w_ptr, dim_order); +#endif + + data.p_mli_krn_depthwise_conv2d_sa8_sa8_sa32(in_ptr, w_ptr, b_ptr, + &cfg_local, out_ptr); +#else + if ((in_slice.Sub()->data != input_buffer_ptr) || + (mli_hlp_count_elem_num(in_slice.Sub(), 0) != input_buffer_size)) { + mli_mov_tensor_sync(in_slice.Sub(), ©_config, in_ptr); + input_buffer_ptr = in_slice.Sub()->data; + input_buffer_size = mli_hlp_count_elem_num(in_slice.Sub(), 0); + } + data.p_mli_krn_depthwise_conv2d_sa8_sa8_sa32(in_ptr, w_ptr, b_ptr, + &cfg_local, out_ptr); +#endif + + mli_mov_tensor_sync(out_ptr, ©_config, out_slice.Sub()); + + in_slice.Next(); + out_slice.Next(); + } + w_slice.Next(); + b_slice.Next(); + out_ch_slice.Next(); + in_ch_slice.Next(); + TF_LITE_ENSURE(context, in_slice.Done()); + } + } + return kTfLiteOk; +} + +void EvalQuantizedPerChannel(TfLiteContext* context, TfLiteNode* node, + TfLiteDepthwiseConvParams* params, + const OpData& data, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + DepthwiseParams op_params; + op_params.padding_type = PaddingType::kSame; + op_params.padding_values.width = data.padding.width; + op_params.padding_values.height = data.padding.height; + op_params.stride_width = params->stride_width; + op_params.stride_height = params->stride_height; + op_params.dilation_width_factor = params->dilation_width_factor; + op_params.dilation_height_factor = params->dilation_height_factor; + op_params.depth_multiplier = params->depth_multiplier; + op_params.input_offset = -data.input_zero_point; + op_params.weights_offset = 0; + op_params.output_offset = data.output_zero_point; + op_params.quantized_activation_min = std::numeric_limits::min(); + op_params.quantized_activation_max = std::numeric_limits::max(); + + reference_integer_ops::DepthwiseConvPerChannel( + op_params, data.per_channel_output_multiplier, + data.per_channel_output_shift, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf("Node configuration is not supported by ARC MLI Library."); +#endif +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* params = + reinterpret_cast(node->builtin_data); + const OpData& data = *(static_cast(node->user_data)); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFilterTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kBiasTensor) + : nullptr; + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + EvalFloat(context, node, params, data, input, filter, bias, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + if (data.is_mli_applicable) { + EvalMliQuantizedPerChannel(context, node, params, data, input, filter, + bias, output); + } else { + EvalQuantizedPerChannel(context, node, params, data, input, filter, + bias, output); + } + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_DEPTHWISE_CONV_2D() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP == 1 + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" + +#include "sl_mvp_ml_depthwise_conv2d.h" + +namespace tflite { +namespace sl { +namespace depthwise_conv2d { + +constexpr int kInputTensor = 0; +constexpr int kFilterTensor = 1; +constexpr int kBiasTensor = 2; +constexpr int kOutputTensor = 0; + +// Depthwise conv is quantized along dimension 3 of filter tensor. +// https://www.tensorflow.org/lite/performance/quantization_spec +constexpr int kDepthwiseConvQuantizedDimension = 3; + +enum op_support { kMvp, kCmsisNN, kTFLMrefF32, kTFLMrefI8 }; + +struct OpData { + op_support supported; + float activation_min_f32; + float activation_max_f32; + int scratch_buffer_index; + sli_mvp_ml_depthwise_conv2d_s8_params_t op_params; + + // CMSIS-NN per channel output multiplier and shift. + int32_t *per_channel_output_multiplier; + int32_t *per_channel_output_shift; +}; + +inline float16_t normalize_fp16(float f) +{ + return (float16_t)std::min(std::max(f, SLI_MVP_FP16_MIN), SLI_MVP_FP16_MAX); +} + +inline PaddingType RuntimePaddingType(TfLitePadding padding) +{ + switch (padding) { + case TfLitePadding::kTfLitePaddingSame: + return PaddingType::kSame; + case TfLitePadding::kTfLitePaddingValid: + return PaddingType::kValid; + case TfLitePadding::kTfLitePaddingUnknown: + default: + return PaddingType::kNone; + } +} + +TfLiteStatus PopulateConvolutionQuantizationParams( + TfLiteContext* context, + const TfLiteTensor* input, + const TfLiteTensor* filter, + TfLiteTensor* output, + const TfLiteFusedActivation& activation, + int32_t* output_activation_min, int32_t* output_activation_max, + float16_t* per_channel_scalers, int num_channels, float accumulator_multipler) +{ + auto affine_quantization = + reinterpret_cast(filter->quantization.params); + + // Populate multiplier and shift using affine quantization. + const float input_scale = input->params.scale; + const float output_scale = output->params.scale; + const float* filter_scales = affine_quantization->scale->data; + + for (int i = 0; i < num_channels; ++i) { + // If per-tensor quantization parameter is specified, broadcast it along the + // quantization dimension (channels_out). + const float filter_scale = filter_scales[i]; + const float effective_output_scale = (input_scale * filter_scale) / output_scale; + const float acc_output_scale = effective_output_scale * accumulator_multipler; + per_channel_scalers[i] = normalize_fp16(acc_output_scale); + } + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, activation, output, output_activation_min, + output_activation_max)); + + return kTfLiteOk; +} + +void *Init(TfLiteContext* context, const char* buffer, size_t length) +{ + (void)buffer; + (void)length; + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) +{ + int scratch_buffer_size = 0; + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto params = static_cast(node->builtin_data); + + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + const TfLiteTensor* bias = GetOptionalInputTensor(context, node, kBiasTensor); + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + const TfLiteTensor* filter = GetInput(context, node, kFilterTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE(context, filter != nullptr); + + data->op_params.batches = input->dims->data[0]; + data->op_params.in_channels = input->dims->data[3]; + data->op_params.input_height = input->dims->data[1]; + data->op_params.input_width = input->dims->data[2]; + data->op_params.out_channels = filter->dims->data[kDepthwiseConvQuantizedDimension]; + data->op_params.output_height = output->dims->data[1]; + data->op_params.output_width = output->dims->data[2]; + data->op_params.filter_height = filter->dims->data[1]; + data->op_params.filter_width = filter->dims->data[2]; + data->op_params.input_offset = -input->params.zero_point; + data->op_params.output_offset = output->params.zero_point; + data->op_params.stride_height = params->stride_height; + data->op_params.stride_width = params->stride_width; + data->op_params.dilation_height = params->dilation_height_factor; + data->op_params.dilation_width = params->dilation_width_factor; + data->op_params.padding = params->padding == kTfLitePaddingSame; + + int dummy_height, dummy_width; + const auto padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, + params->dilation_height_factor, params->dilation_width_factor, + data->op_params.input_height, data->op_params.input_width, + data->op_params.filter_height, data->op_params.filter_width, + params->padding, + &dummy_height, &dummy_width); + + data->op_params.pad_height = padding.height; + data->op_params.pad_width = padding.width; + + const int num_channels = data->op_params.out_channels; + + if (input->type == kTfLiteInt8) { + if (sli_mvp_ml_depthwise_conv2d_s8_is_supported(&data->op_params)) { + data->supported = kMvp; + + float16_t *bias_data = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(float16_t))); + if(bias != nullptr) { + data->op_params.bias = bias_data; + int32_t i32_bias; + for(int i = 0; i < num_channels; i++) { + i32_bias = bias->data.i32[i]; + bias_data[i] = float16_t(i32_bias * SLI_MVP_ACCUMULATOR_SCALER); + } + } else { + data->op_params.bias = nullptr; + } + + float16_t *scaler_data = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(float16_t))); + data->op_params.output_scaler = scaler_data; + TF_LITE_ENSURE_STATUS(PopulateConvolutionQuantizationParams( + context, input, filter, output, params->activation, + reinterpret_cast(&data->op_params.output_activation_min), + reinterpret_cast(&data->op_params.output_activation_max), + scaler_data, num_channels, SLI_MVP_ACCUMULATOR_MULTIPLIER)); + + } else { + data->per_channel_output_multiplier = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + int32_t dummy_output_multiplier; + int dummy_output_shift; + TF_LITE_ENSURE_STATUS(tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, params->activation, + &dummy_output_multiplier, &dummy_output_shift, + reinterpret_cast(&data->op_params.output_activation_min), + reinterpret_cast(&data->op_params.output_activation_max), + data->per_channel_output_multiplier, + reinterpret_cast(data->per_channel_output_shift), + num_channels)); + + if (data->op_params.dilation_height == 1 && data->op_params.dilation_width == 1) { + data->supported = kCmsisNN; + cmsis_nn_dw_conv_params dw_conv_params; + dw_conv_params.input_offset = data->op_params.input_offset; + dw_conv_params.output_offset = data->op_params.output_offset; + dw_conv_params.stride.h = data->op_params.stride_height; + dw_conv_params.stride.w = data->op_params.stride_width; + dw_conv_params.dilation.h = 1; + dw_conv_params.dilation.w = 1; + dw_conv_params.padding.h = data->op_params.pad_height; + dw_conv_params.padding.w = data->op_params.pad_width; + dw_conv_params.activation.min = data->op_params.output_activation_min; + dw_conv_params.activation.max = data->op_params.output_activation_max; + dw_conv_params.ch_mult = data->op_params.out_channels / data->op_params.in_channels; + + cmsis_nn_dims input_dims; + input_dims.n = data->op_params.batches; + input_dims.h = data->op_params.input_height; + input_dims.w = data->op_params.input_width; + input_dims.c = data->op_params.in_channels; + + cmsis_nn_dims filter_dims; + filter_dims.h = data->op_params.filter_height; + filter_dims.w = data->op_params.filter_width; + + cmsis_nn_dims output_dims; + output_dims.h = data->op_params.output_height; + output_dims.w = data->op_params.output_width; + output_dims.c = data->op_params.out_channels; + + scratch_buffer_size = arm_depthwise_conv_wrapper_s8_get_buffer_size( + &dw_conv_params, &input_dims, &filter_dims, &output_dims); + } else { + data->supported = kTFLMrefI8; + } + } + + } else if (input->type == kTfLiteFloat32) { + data->supported = kTFLMrefF32; + CalculateActivationRange(params->activation, + &data->activation_min_f32, + &data->activation_max_f32); + + } else { + TF_LITE_KERNEL_LOG(context, "Type %s not currently supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + if(scratch_buffer_size > 0) { + TF_LITE_ENSURE_STATUS( + context->RequestScratchBufferInArena( + context, scratch_buffer_size, &data->scratch_buffer_index)); + } else { + data->scratch_buffer_index = -1; + } + + return kTfLiteOk; +} + +TfLiteStatus eval_mvp_int8(TfLiteContext* context, + OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + TfLiteEvalTensor* output) +{ + data->op_params.input = tflite::micro::GetTensorData(input); + data->op_params.output = tflite::micro::GetTensorData(output); + data->op_params.filter = tflite::micro::GetTensorData(filter); + + TF_LITE_ENSURE_EQ(context, SL_STATUS_OK, sli_mvp_ml_depthwise_conv2d_s8(&data->op_params)); + + return kTfLiteOk; +} + +TfLiteStatus eval_cmsis_int8(TfLiteContext* context, + OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + cmsis_nn_dims input_dims; + input_dims.n = data->op_params.batches; + input_dims.h = data->op_params.input_height; + input_dims.w = data->op_params.input_width; + input_dims.c = data->op_params.in_channels; + + cmsis_nn_dims filter_dims; + filter_dims.n = data->op_params.in_channels; + filter_dims.h = data->op_params.filter_height; + filter_dims.w = data->op_params.filter_width; + filter_dims.c = data->op_params.out_channels; + + cmsis_nn_dims bias_dims; + bias_dims.n = 1; + bias_dims.h = 1; + bias_dims.w = 1; + bias_dims.c = data->op_params.out_channels; + + cmsis_nn_dims output_dims; + output_dims.n = data->op_params.batches; + output_dims.h = data->op_params.output_height; + output_dims.w = data->op_params.output_width; + output_dims.c = data->op_params.out_channels; + + cmsis_nn_per_channel_quant_params quant_params; + quant_params.multiplier = data->per_channel_output_multiplier; + quant_params.shift = data->per_channel_output_shift; + + cmsis_nn_dw_conv_params dw_conv_params; + dw_conv_params.input_offset = data->op_params.input_offset; + dw_conv_params.output_offset = data->op_params.output_offset; + dw_conv_params.stride.h = data->op_params.stride_height; + dw_conv_params.stride.w = data->op_params.stride_width; + dw_conv_params.dilation.h = 1; + dw_conv_params.dilation.w = 1; + dw_conv_params.padding.h = data->op_params.pad_height; + dw_conv_params.padding.w = data->op_params.pad_width; + dw_conv_params.activation.min = data->op_params.output_activation_min; + dw_conv_params.activation.max = data->op_params.output_activation_max; + dw_conv_params.ch_mult = data->op_params.out_channels / data->op_params.in_channels; + + cmsis_nn_context ctx; + ctx.buf = nullptr; + ctx.size = 0; + + if (data->scratch_buffer_index > -1) { + ctx.buf = context->GetScratchBuffer(context, data->scratch_buffer_index); + } + TFLITE_DCHECK_EQ(ARM_MATH_SUCCESS, + arm_depthwise_conv_wrapper_s8( + &ctx, &dw_conv_params, &quant_params, + &input_dims, tflite::micro::GetTensorData(input), + &filter_dims, tflite::micro::GetTensorData(filter), + &bias_dims, bias == nullptr ? NULL : tflite::micro::GetTensorData(bias), + &output_dims, tflite::micro::GetTensorData(output))); + + return kTfLiteOk; +} + +TfLiteStatus eval_tflm_int8(OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + DepthwiseParams dw_op_params; + + dw_op_params.input_offset = data->op_params.input_offset; + dw_op_params.output_offset = data->op_params.output_offset; + dw_op_params.stride_height = data->op_params.stride_height; + dw_op_params.stride_width = data->op_params.stride_width; + dw_op_params.dilation_height_factor = data->op_params.dilation_height; + dw_op_params.dilation_width_factor = data->op_params.dilation_width; + dw_op_params.padding_values.height = data->op_params.pad_height; + dw_op_params.padding_values.width = data->op_params.pad_width; + dw_op_params.quantized_activation_min = data->op_params.output_activation_min; + dw_op_params.quantized_activation_max = data->op_params.output_activation_max; + dw_op_params.depth_multiplier = data->op_params.out_channels / data->op_params.in_channels; + + reference_integer_ops::DepthwiseConvPerChannel( + dw_op_params, + data->per_channel_output_multiplier, + data->per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + bias == nullptr ? nullptr : tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; +} + +TfLiteStatus eval_float(TfLiteDepthwiseConvParams* params, + const OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + DepthwiseParams dw_op_params; + + dw_op_params.padding_type = RuntimePaddingType(params->padding); + dw_op_params.padding_values.width = data->op_params.pad_width; + dw_op_params.padding_values.height = data->op_params.pad_height; + dw_op_params.stride_width = data->op_params.stride_width; + dw_op_params.stride_height = data->op_params.stride_height; + dw_op_params.dilation_width_factor = data->op_params.dilation_width; + dw_op_params.dilation_height_factor = data->op_params.dilation_height; + dw_op_params.float_activation_min = data->activation_min_f32; + dw_op_params.float_activation_max = data->activation_max_f32; + dw_op_params.depth_multiplier = data->op_params.out_channels / data->op_params.in_channels; + + reference_ops::DepthwiseConv(dw_op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + bias == nullptr ? nullptr : tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; +} + +TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node) +{ + TfLiteStatus status = kTfLiteError; + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* params = reinterpret_cast(node->builtin_data); + OpData* data = static_cast(node->user_data); + + const auto input = tflite::micro::GetEvalInput(context, node, kInputTensor); + const auto filter = tflite::micro::GetEvalInput(context, node, kFilterTensor); + const auto bias = NumInputs(node) == 3 + ? tflite::micro::GetEvalInput(context, node, kBiasTensor) + : nullptr; + auto output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (data->supported == kMvp) { + status = eval_mvp_int8(context, data, input, filter, output); + + } else if (data->supported == kCmsisNN) { + status = eval_cmsis_int8(context, data, input, filter, bias, output); + + } else if (data->supported == kTFLMrefI8) { + status = eval_tflm_int8(data, input, filter, bias, output); + + } else if (data->supported == kTFLMrefF32) { + #if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + status = eval_float(params, data, input, filter, bias, output); + } + + return status; +} + +} // namespace depthwise_conv2d +} // namespace sl + +TfLiteRegistration Register_DEPTHWISE_CONV_2D() { + return {/*init=*/sl::depthwise_conv2d::Init, + /*free=*/nullptr, + /*prepare=*/sl::depthwise_conv2d::Prepare, + /*invoke=*/sl::depthwise_conv2d::Invoke, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN == 1 +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_uint8.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#include + +#if ESP_NN +#include "edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h" +#endif + +long long dc_total_time = 0; + +namespace tflite { +namespace { + +struct NodeData { + OpDataConv op_data; +#if ESP_NN + int buffer_idx; +#endif +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(NodeData)); +} + +#if ESP_NN +inline void EvalQuantizedPerChannel(TfLiteContext* context, TfLiteNode* node, + const TfLiteDepthwiseConvParams& params, + const NodeData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + const int dilation_width_factor = params.dilation_width_factor; + const int dilation_height_factor = params.dilation_height_factor; + + if (dilation_width_factor == 1 && dilation_height_factor == 1) { + // Get parameters. + RuntimeShape input_shape = tflite::micro::GetTensorShape(input); + RuntimeShape filter_shape = tflite::micro::GetTensorShape(filter); + RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + RuntimeShape bias_shape = tflite::micro::GetTensorShape(bias); + + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(filter_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + const int8_t *input_data = tflite::micro::GetTensorData(input); + int8_t *output_data = tflite::micro::GetTensorData(output); + + const int depth_multiplier = params.depth_multiplier; + const int32_t input_offset = -data.op_data.input_zero_point; + const int32_t output_offset = data.op_data.output_zero_point; + const int stride_width = params.stride_width; + const int stride_height = params.stride_height; + const int pad_width = data.op_data.padding.width; + const int pad_height = data.op_data.padding.height; + + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int input_depth = input_shape.Dims(3); + const int filter_height = filter_shape.Dims(1); + const int filter_width = filter_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + + // Set min and max value of the output. + const int32_t activation_min = data.op_data.output_activation_min; + const int32_t activation_max = data.op_data.output_activation_max; + + // Consistency check. + TFLITE_DCHECK_LE(activation_min, activation_max); + const int batch_size = MatchingDim(input_shape, 0, output_shape, 0); + const int output_depth = MatchingDim(filter_shape, 3, output_shape, 3); + + TFLITE_DCHECK_EQ(output_depth, input_depth * depth_multiplier); + if (tflite::micro::GetTensorData(bias)) { + TFLITE_DCHECK_EQ(bias_shape.FlatSize(), output_depth); + } + + const int input_size = input_width * input_height * input_depth; + const int output_size = output_width * output_height * output_depth; + void *scratch_buf = NULL; + if (data.buffer_idx > -1) { + scratch_buf = context->GetScratchBuffer(context, data.buffer_idx); + } + + esp_nn_set_depthwise_conv_scratch_buf(scratch_buf); + + data_dims_t input_dims = { + .width = input_width, .height = input_height, + .channels = input_depth, 1 + }; + data_dims_t output_dims = { + .width = output_width, .height = output_height, + .channels = output_depth, 1 + }; + data_dims_t filter_dims = {.width = filter_width, .height = filter_height, 0, 0}; + dw_conv_params_t conv_params = { + .in_offset = input_offset, .out_offset = output_offset, + .ch_mult = depth_multiplier, + .stride = {stride_width, stride_height}, + .padding = {pad_width, pad_height}, .dilation = {0, 0}, + .activation = {activation_min, activation_max} + }; + quant_data_t quant_data = { + .shift = data.op_data.per_channel_output_shift, + .mult = data.op_data.per_channel_output_multiplier + }; + + for (int i_batch = 0; i_batch < batch_size; i_batch++) { + esp_nn_depthwise_conv_s8(&input_dims, input_data + i_batch * input_size, + &filter_dims, tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorData(bias), + &output_dims, output_data + i_batch * output_size, + &conv_params, &quant_data); + } + } else { + reference_integer_ops::DepthwiseConvPerChannel( + DepthwiseConvParamsQuantized(params, data.op_data), + data.op_data.per_channel_output_multiplier, + data.op_data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} +#endif + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + NodeData* data = static_cast(node->user_data); + const TfLiteDepthwiseConvParams& params = + *(static_cast(node->builtin_data)); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kConvBiasTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + const int input_width = input->dims->data[2]; + const int input_height = input->dims->data[1]; + const int filter_width = filter->dims->data[2]; + const int filter_height = filter->dims->data[1]; + const int output_width = output->dims->data[2]; + const int output_height = output->dims->data[1]; + + // Dynamically allocate per-channel quantization parameters. + const int num_channels = filter->dims->data[kDepthwiseConvQuantizedDimension]; + data->op_data.per_channel_output_multiplier = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->op_data.per_channel_output_shift = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + // All per-channel quantized tensors need valid zero point and scale arrays. + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + const auto* affine_quantization = + static_cast(filter->quantization.params); + TFLITE_DCHECK(affine_quantization != nullptr); + TFLITE_DCHECK(affine_quantization->scale != nullptr); + TFLITE_DCHECK(affine_quantization->zero_point != nullptr); + + TF_LITE_ENSURE( + context, affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kDepthwiseConvQuantizedDimension]); + + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, + affine_quantization->zero_point->size); + } + + TF_LITE_ENSURE_STATUS(CalculateOpDataDepthwiseConv( + context, node, params, input_width, input_height, filter_width, + filter_height, output_width, output_height, input->type, &data->op_data)); + +#if ESP_NN + if (input->type == kTfLiteInt8) { + data_dims_t input_dims = { + .width = input_width, .height = input_height, + .channels = input->dims->data[3], 1 + }; + data_dims_t output_dims = { + .width = output_width, .height = output_height, + .channels = output->dims->data[3], 1 + }; + data_dims_t filter_dims = {.width = filter_width, .height = filter_height, 0, 0}; + dw_conv_params_t conv_params = { + .in_offset = 0, .out_offset = 0, + .ch_mult = params.depth_multiplier, + .stride = {params.stride_width, params.stride_height}, + .padding = {data->op_data.padding.width, data->op_data.padding.height}, + .dilation = {0, 0}, .activation = {-128, 127} + }; + + int scratch_buf_size = esp_nn_get_depthwise_conv_scratch_size( + &input_dims, &filter_dims, &output_dims, &conv_params); + if (scratch_buf_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, scratch_buf_size, &data->buffer_idx)); + } else { + data->buffer_idx = -1; + } + } +#endif + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(bias); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto& params = + *(reinterpret_cast(node->builtin_data)); + const NodeData& data = *(static_cast(node->user_data)); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kDepthwiseConvOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kDepthwiseConvBiasTensor) + : nullptr; + + long long start_time = esp_timer_get_time(); + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + tflite::reference_ops::DepthwiseConv( + DepthwiseConvParamsFloat(params, data.op_data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif +#if ESP_NN + EvalQuantizedPerChannel(context, node, params, data, input, filter, bias, + output); +#else + reference_integer_ops::DepthwiseConvPerChannel( + DepthwiseConvParamsQuantized(params, data.op_data), + data.op_data.per_channel_output_multiplier, + data.op_data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#endif + break; + case kTfLiteUInt8: +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_U8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + //EvalQuantized(context, node, params, &data, input, filter, bias, output); + reference_ops::DepthwiseConv( + DepthwiseConvParamsQuantized(params, data.op_data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + long long time_this_instance = esp_timer_get_time() - start_time; + dc_total_time += time_this_instance; + // printf("time this instance: %llu\n", time_this_instance / 1000); + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_DEPTHWISE_CONV_2D() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#else +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataConv)); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto& params = + *(reinterpret_cast(node->builtin_data)); + const OpDataConv& data = *(static_cast(node->user_data)); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kDepthwiseConvOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kDepthwiseConvWeightsTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 3) + ? tflite::micro::GetEvalInput(context, node, kDepthwiseConvBiasTensor) + : nullptr; + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + tflite::reference_ops::DepthwiseConv( + DepthwiseConvParamsFloat(params, data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + case kTfLiteInt8: { +#if EI_TFLITE_DISABLE_DEPTHWISE_CONV_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + switch (filter->type) { + case kTfLiteInt4: { + int8_t* unpacked_filter_data = static_cast( + context->GetScratchBuffer(context, data.filter_buffer_index)); + tflite::tensor_utils::UnpackDenseInt4IntoInt8( + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(filter).FlatSize(), + unpacked_filter_data); + reference_integer_ops::DepthwiseConvPerChannel( + DepthwiseConvParamsQuantized(params, data), + data.per_channel_output_multiplier, data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), unpacked_filter_data, + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + case kTfLiteInt8: { + reference_integer_ops::DepthwiseConvPerChannel( + DepthwiseConvParamsQuantized(params, data), + data.per_channel_output_multiplier, data.per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + default: + MicroPrintf("Filter type %s (%d) not supported.", + TfLiteTypeGetName(filter->type), filter->type); + return kTfLiteError; + } + break; + } + default: + MicroPrintf("Input type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_DEPTHWISE_CONV_2D() { + return tflite::micro::RegisterOp(Init, DepthwiseConvPrepare, Eval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h new file mode 100644 index 0000000..000e792 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h @@ -0,0 +1,80 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_DEPTHWISE_CONV_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_DEPTHWISE_CONV_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h" + +namespace tflite { + +extern const int kDepthwiseConvInputTensor; +extern const int kDepthwiseConvWeightsTensor; +extern const int kDepthwiseConvBiasTensor; +extern const int kDepthwiseConvOutputTensor; +extern const int kDepthwiseConvQuantizedDimension; + +// Returns a DepthwiseParams struct with all the parameters needed for a +// float computation. +DepthwiseParams DepthwiseConvParamsFloat( + const TfLiteDepthwiseConvParams& params, const OpDataConv& data); + +// Returns a DepthwiseParams struct with all the parameters needed for a +// quantized computation. +DepthwiseParams DepthwiseConvParamsQuantized( + const TfLiteDepthwiseConvParams& params, const OpDataConv& data); + +TfLiteStatus CalculateOpDataDepthwiseConv( + TfLiteContext* context, TfLiteNode* node, + const TfLiteDepthwiseConvParams& params, int width, int height, + int filter_width, int filter_height, int out_width, int out_height, + const TfLiteType data_type, OpDataConv* data); + +TfLiteStatus DepthwiseConvPrepare(TfLiteContext* context, TfLiteNode* node); + +// This is the most generic TfLiteRegistration. The actual supported types may +// still be target dependent. The only requirement is that every implementation +// (reference or optimized) must define this function. +TfLiteRegistration Register_DEPTHWISE_CONV_2D(); + +#if defined(CMSIS_NN) +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int8 activations and int8 weights and uses the latency optimized +// implementations. +TfLiteRegistration Register_DEPTHWISE_CONV_2D_INT8(); + +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int16 activations and int8 weights and uses the latency optimized +// implementations. +TfLiteRegistration Register_DEPTHWISE_CONV_2D_INT16(); + +#else +inline TfLiteRegistration Register_DEPTHWISE_CONV_2D_INT8() { + return Register_DEPTHWISE_CONV_2D(); +} + +inline TfLiteRegistration Register_DEPTHWISE_CONV_2D_INT16() { + return Register_DEPTHWISE_CONV_2D(); +} +#endif + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_DEPTHWISE_CONV_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv_common.cpp new file mode 100644 index 0000000..5263961 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv_common.cpp @@ -0,0 +1,213 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { + +const int kDepthwiseConvInputTensor = 0; +const int kDepthwiseConvWeightsTensor = 1; +const int kDepthwiseConvBiasTensor = 2; +const int kDepthwiseConvOutputTensor = 0; + +// DepthwiseConv is quantized along dimension 3: +// https://www.tensorflow.org/lite/performance/quantization_spec +const int kDepthwiseConvQuantizedDimension = 3; + +// Returns a DepthwiseParams struct with all the parameters needed for a +// float computation. +DepthwiseParams DepthwiseConvParamsFloat( + const TfLiteDepthwiseConvParams& params, const OpDataConv& data) { + DepthwiseParams op_params; + CalculateActivationRange(params.activation, &op_params.float_activation_min, + &op_params.float_activation_max); + op_params.padding_type = tflite::micro::RuntimePaddingType(params.padding); + op_params.padding_values.width = data.padding.width; + op_params.padding_values.height = data.padding.height; + op_params.stride_width = params.stride_width; + op_params.stride_height = params.stride_height; + op_params.dilation_width_factor = params.dilation_width_factor; + op_params.dilation_height_factor = params.dilation_height_factor; + op_params.depth_multiplier = params.depth_multiplier; + return op_params; +} + +// Returns a DepthwiseParams struct with all the parameters needed for a +// quantized computation. +DepthwiseParams DepthwiseConvParamsQuantized( + const TfLiteDepthwiseConvParams& params, const OpDataConv& data) { + DepthwiseParams op_params; + op_params.input_offset = -data.input_zero_point; + op_params.weights_offset = -data.filter_zero_point; + op_params.output_offset = data.output_zero_point; + op_params.output_multiplier = data.output_multiplier; + op_params.output_shift = -data.output_shift; + op_params.padding_type = tflite::micro::RuntimePaddingType(params.padding); + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.stride_height = params.stride_height; + op_params.stride_width = params.stride_width; + op_params.dilation_height_factor = params.dilation_height_factor; + op_params.dilation_width_factor = params.dilation_width_factor; + op_params.depth_multiplier = params.depth_multiplier; + op_params.quantized_activation_min = data.output_activation_min; + op_params.quantized_activation_max = data.output_activation_max; + return op_params; +} + +TfLiteStatus CalculateOpDataDepthwiseConv( + TfLiteContext* context, TfLiteNode* node, + const TfLiteDepthwiseConvParams& params, int width, int height, + int filter_width, int filter_height, int out_width, int out_height, + const TfLiteType data_type, OpDataConv* data) { + bool has_bias = node->inputs->size == 3; + // Check number of inputs/outputs + TF_LITE_ENSURE(context, has_bias || node->inputs->size == 2); + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + + // Matching GetWindowedOutputSize in TensorFlow. + auto padding = params.padding; + data->padding = ComputePaddingHeightWidth( + params.stride_height, params.stride_width, params.dilation_height_factor, + params.dilation_width_factor, height, width, filter_height, filter_width, + padding, &out_height, &out_width); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kConvBiasTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + // Note that quantized inference requires that all tensors have their + // parameters set. This is usually done during quantized training. + if (data_type != kTfLiteFloat32) { + int output_channels = filter->dims->data[kDepthwiseConvQuantizedDimension]; + + TF_LITE_ENSURE_STATUS(tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, params.activation, + &data->output_multiplier, &data->output_shift, + &data->output_activation_min, &data->output_activation_max, + data->per_channel_output_multiplier, data->per_channel_output_shift, + output_channels)); + } + + data->input_zero_point = input->params.zero_point; + data->filter_zero_point = filter->params.zero_point; + data->output_zero_point = output->params.zero_point; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(bias); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus DepthwiseConvPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpDataConv* data = static_cast(node->user_data); + const auto& params = + *(static_cast(node->builtin_data)); + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kDepthwiseConvOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kDepthwiseConvInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kDepthwiseConvWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + + const int input_width = input->dims->data[2]; + const int input_height = input->dims->data[1]; + const int filter_width = filter->dims->data[2]; + const int filter_height = filter->dims->data[1]; + const int output_width = output->dims->data[2]; + const int output_height = output->dims->data[1]; + + // Dynamically allocate per-channel quantization parameters. + if (input->type != kTfLiteFloat32) { + const int num_channels = filter->dims->data[kDepthwiseConvQuantizedDimension]; + data->per_channel_output_multiplier = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + } + + // All per-channel quantized tensors need valid zero point and scale arrays. + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + const auto* affine_quantization = + static_cast(filter->quantization.params); + TFLITE_DCHECK(affine_quantization != nullptr); + TFLITE_DCHECK(affine_quantization->scale != nullptr); + TFLITE_DCHECK(affine_quantization->zero_point != nullptr); + + TF_LITE_ENSURE( + context, affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kDepthwiseConvQuantizedDimension]); + + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, + affine_quantization->zero_point->size); + } + + if (filter->type == kTfLiteInt4) { + int filter_size = + RuntimeShape(filter->dims->size, + reinterpret_cast(filter->dims->data)) + .FlatSize(); + context->RequestScratchBufferInArena(context, filter_size, + &data->filter_buffer_index); + } + + TF_LITE_ENSURE_STATUS(CalculateOpDataDepthwiseConv( + context, node, params, input_width, input_height, filter_width, + filter_height, output_width, output_height, input->type, data)); + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.cpp new file mode 100644 index 0000000..c41036e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.cpp @@ -0,0 +1,88 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/dequantize.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/quantize.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/requantize.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +void* DequantizeInit(TfLiteContext* context, const char* buffer, + size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(DequantizeOpData)); +} + +TfLiteStatus DequantizeEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + DequantizeOpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + if (output->type == kTfLiteFloat32) { + switch (input->type) { + case kTfLiteInt8: + reference_ops::Dequantize(data->quantization_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt16: + reference_ops::Dequantize(data->quantization_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteUInt8: + reference_ops::Dequantize(data->quantization_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else { + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteRegistration Register_DEQUANTIZE() { + return tflite::micro::RegisterOp(DequantizeInit, DequantizePrepare, + DequantizeEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.h new file mode 100644 index 0000000..ee45f36 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.h @@ -0,0 +1,38 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_DEQUANTIZE_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_DEQUANTIZE_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +struct DequantizeOpData { + tflite::DequantizationParams quantization_params; + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t output_multiplier; + int output_shift; + int32_t output_zero_point; +}; + +TfLiteStatus DequantizePrepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_DEQUANTIZE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize_common.cpp new file mode 100644 index 0000000..e8ae297 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize_common.cpp @@ -0,0 +1,67 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/dequantize.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/quantize.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/requantize.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/dequantize.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { + +TfLiteStatus DequantizePrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + DequantizeOpData* data = static_cast(node->user_data); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + // TODO(b/140515557): Add cached dequant to improve hybrid model performance. + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE(context, input->type == kTfLiteInt8 || + input->type == kTfLiteInt16 || + input->type == kTfLiteUInt8); + TF_LITE_ENSURE(context, output->type == kTfLiteFloat32); + + if (output->type == kTfLiteInt32) { + const double effective_output_scale = + static_cast(input->params.scale) / + static_cast(output->params.scale); + QuantizeMultiplier(effective_output_scale, &data->output_multiplier, + &data->output_shift); + } + + data->quantization_params.zero_point = input->params.zero_point; + data->quantization_params.scale = static_cast(input->params.scale); + data->output_zero_point = output->params.zero_point; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/detection_postprocess.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/detection_postprocess.cpp new file mode 100644 index 0000000..2209a58 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/detection_postprocess.cpp @@ -0,0 +1,807 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +/** + * This version of detection_postprocess is specific to TFLite Micro. It + * contains the following differences between the TFLite version: + * + * 1.) Temporaries (temporary tensors) - Micro use instead scratch buffer API. + * 2.) Output dimensions - the TFLite version does not support undefined out + * dimensions. So model must have static out dimensions. + */ + +// Input tensors +constexpr int kInputTensorBoxEncodings = 0; +constexpr int kInputTensorClassPredictions = 1; +constexpr int kInputTensorAnchors = 2; + +// Output tensors +constexpr int kOutputTensorDetectionBoxes = 0; +constexpr int kOutputTensorDetectionClasses = 1; +constexpr int kOutputTensorDetectionScores = 2; +constexpr int kOutputTensorNumDetections = 3; + +constexpr int kNumCoordBox = 4; +constexpr int kBatchSize = 1; + +constexpr int kNumDetectionsPerClass = 100; + +// Object Detection model produces axis-aligned boxes in two formats: +// BoxCorner represents the lower left corner (xmin, ymin) and +// the upper right corner (xmax, ymax). +// CenterSize represents the center (xcenter, ycenter), height and width. +// BoxCornerEncoding and CenterSizeEncoding are related as follows: +// ycenter = y / y_scale * anchor.h + anchor.y; +// xcenter = x / x_scale * anchor.w + anchor.x; +// half_h = 0.5*exp(h/ h_scale)) * anchor.h; +// half_w = 0.5*exp(w / w_scale)) * anchor.w; +// ymin = ycenter - half_h +// ymax = ycenter + half_h +// xmin = xcenter - half_w +// xmax = xcenter + half_w +struct BoxCornerEncoding { + float ymin; + float xmin; + float ymax; + float xmax; +}; + +struct CenterSizeEncoding { + float y; + float x; + float h; + float w; +}; +// We make sure that the memory allocations are contiguous with static_assert. +static_assert(sizeof(BoxCornerEncoding) == sizeof(float) * kNumCoordBox, + "Size of BoxCornerEncoding is 4 float values"); +static_assert(sizeof(CenterSizeEncoding) == sizeof(float) * kNumCoordBox, + "Size of CenterSizeEncoding is 4 float values"); + +struct OpData { + int max_detections; + int max_classes_per_detection; // Fast Non-Max-Suppression + int detections_per_class; // Regular Non-Max-Suppression + float non_max_suppression_score_threshold; + float intersection_over_union_threshold; + int num_classes; + bool use_regular_non_max_suppression; + CenterSizeEncoding scale_values; + + // Scratch buffers indexes + int active_candidate_idx; + int decoded_boxes_idx; + int scores_idx; + int score_buffer_idx; + int keep_scores_idx; + int scores_after_regular_non_max_suppression_idx; + int sorted_values_idx; + int keep_indices_idx; + int sorted_indices_idx; + int buffer_idx; + int selected_idx; + + // Cached tensor scale and zero point values for quantized operations + TfLiteQuantizationParams input_box_encodings; + TfLiteQuantizationParams input_class_predictions; + TfLiteQuantizationParams input_anchors; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + OpData* op_data = nullptr; + + const uint8_t* buffer_t = reinterpret_cast(buffer); + const flexbuffers::Map& m = flexbuffers::GetRoot(buffer_t, length).AsMap(); + op_data = reinterpret_cast( + context->AllocatePersistentBuffer(context, sizeof(OpData))); + + op_data->max_detections = m["max_detections"].AsInt32(); + op_data->max_classes_per_detection = m["max_classes_per_detection"].AsInt32(); + if (m["detections_per_class"].IsNull()) + op_data->detections_per_class = kNumDetectionsPerClass; + else + op_data->detections_per_class = m["detections_per_class"].AsInt32(); + if (m["use_regular_nms"].IsNull()) + op_data->use_regular_non_max_suppression = false; + else + op_data->use_regular_non_max_suppression = m["use_regular_nms"].AsBool(); + + op_data->non_max_suppression_score_threshold = + m["nms_score_threshold"].AsFloat(); + op_data->intersection_over_union_threshold = m["nms_iou_threshold"].AsFloat(); + op_data->num_classes = m["num_classes"].AsInt32(); + op_data->scale_values.y = m["y_scale"].AsFloat(); + op_data->scale_values.x = m["x_scale"].AsFloat(); + op_data->scale_values.h = m["h_scale"].AsFloat(); + op_data->scale_values.w = m["w_scale"].AsFloat(); + + return op_data; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + auto* op_data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + + // Inputs: box_encodings, scores, anchors + TF_LITE_ENSURE_EQ(context, NumInputs(node), 3); + TfLiteTensor* input_box_encodings = + micro_context->AllocateTempInputTensor(node, kInputTensorBoxEncodings); + TfLiteTensor* input_class_predictions = + micro_context->AllocateTempInputTensor(node, + kInputTensorClassPredictions); + TfLiteTensor* input_anchors = + micro_context->AllocateTempInputTensor(node, kInputTensorAnchors); + TF_LITE_ENSURE_EQ(context, NumDimensions(input_box_encodings), 3); + TF_LITE_ENSURE_EQ(context, NumDimensions(input_class_predictions), 3); + TF_LITE_ENSURE_EQ(context, NumDimensions(input_anchors), 2); + + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 4); + const int num_boxes = input_box_encodings->dims->data[1]; + const int num_classes = op_data->num_classes; + + op_data->input_box_encodings.scale = input_box_encodings->params.scale; + op_data->input_box_encodings.zero_point = + input_box_encodings->params.zero_point; + op_data->input_class_predictions.scale = + input_class_predictions->params.scale; + op_data->input_class_predictions.zero_point = + input_class_predictions->params.zero_point; + op_data->input_anchors.scale = input_anchors->params.scale; + op_data->input_anchors.zero_point = input_anchors->params.zero_point; + + // Scratch tensors + context->RequestScratchBufferInArena(context, num_boxes, + &op_data->active_candidate_idx); + context->RequestScratchBufferInArena(context, + num_boxes * kNumCoordBox * sizeof(float), + &op_data->decoded_boxes_idx); + context->RequestScratchBufferInArena( + context, + input_class_predictions->dims->data[1] * + input_class_predictions->dims->data[2] * sizeof(float), + &op_data->scores_idx); + + // Additional buffers + context->RequestScratchBufferInArena(context, num_boxes * sizeof(float), + &op_data->score_buffer_idx); + context->RequestScratchBufferInArena(context, num_boxes * sizeof(float), + &op_data->keep_scores_idx); + context->RequestScratchBufferInArena( + context, op_data->max_detections * num_boxes * sizeof(float), + &op_data->scores_after_regular_non_max_suppression_idx); + context->RequestScratchBufferInArena( + context, op_data->max_detections * num_boxes * sizeof(float), + &op_data->sorted_values_idx); + context->RequestScratchBufferInArena(context, num_boxes * sizeof(int), + &op_data->keep_indices_idx); + context->RequestScratchBufferInArena( + context, op_data->max_detections * num_boxes * sizeof(int), + &op_data->sorted_indices_idx); + int buffer_size = std::max(num_classes, op_data->max_detections); + context->RequestScratchBufferInArena( + context, buffer_size * num_boxes * sizeof(int), &op_data->buffer_idx); + buffer_size = std::min(num_boxes, op_data->max_detections); + context->RequestScratchBufferInArena( + context, buffer_size * num_boxes * sizeof(int), &op_data->selected_idx); + + // Outputs: detection_boxes, detection_scores, detection_classes, + // num_detections + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 4); + + micro_context->DeallocateTempTfLiteTensor(input_box_encodings); + micro_context->DeallocateTempTfLiteTensor(input_class_predictions); + micro_context->DeallocateTempTfLiteTensor(input_anchors); + + return kTfLiteOk; +} + +class Dequantizer { + public: + Dequantizer(int zero_point, float scale) + : zero_point_(zero_point), scale_(scale) {} + float operator()(uint8_t x) { + return (static_cast(x) - zero_point_) * scale_; + } + + private: + int zero_point_; + float scale_; +}; + +template +T ReInterpretTensor(const TfLiteEvalTensor* tensor) { + const float* tensor_base = tflite::micro::GetTensorData(tensor); + return reinterpret_cast(tensor_base); +} + +template +T ReInterpretTensor(TfLiteEvalTensor* tensor) { + float* tensor_base = tflite::micro::GetTensorData(tensor); + return reinterpret_cast(tensor_base); +} + +TfLiteStatus DecodeCenterSizeBoxes(TfLiteContext* context, TfLiteNode* node, + OpData* op_data) { + // Parse input tensor boxencodings + const TfLiteEvalTensor* input_box_encodings = + tflite::micro::GetEvalInput(context, node, kInputTensorBoxEncodings); + TF_LITE_ENSURE_EQ(context, input_box_encodings->dims->data[0], kBatchSize); + const int num_boxes = input_box_encodings->dims->data[1]; + TF_LITE_ENSURE(context, input_box_encodings->dims->data[2] >= kNumCoordBox); + const TfLiteEvalTensor* input_anchors = + tflite::micro::GetEvalInput(context, node, kInputTensorAnchors); + + // Decode the boxes to get (ymin, xmin, ymax, xmax) based on the anchors + CenterSizeEncoding box_centersize; + CenterSizeEncoding scale_values = op_data->scale_values; + CenterSizeEncoding anchor; + for (int idx = 0; idx < num_boxes; ++idx) { + switch (input_box_encodings->type) { + // Float + case kTfLiteFloat32: { + // Please see DequantizeBoxEncodings function for the support detail. + const int box_encoding_idx = idx * input_box_encodings->dims->data[2]; + const float* boxes = &(tflite::micro::GetTensorData( + input_box_encodings)[box_encoding_idx]); + box_centersize = *reinterpret_cast(boxes); + anchor = + ReInterpretTensor(input_anchors)[idx]; + break; + } + default: + // Unsupported type. + return kTfLiteError; + } + + float ycenter = static_cast(static_cast(box_centersize.y) / + static_cast(scale_values.y) * + static_cast(anchor.h) + + static_cast(anchor.y)); + + float xcenter = static_cast(static_cast(box_centersize.x) / + static_cast(scale_values.x) * + static_cast(anchor.w) + + static_cast(anchor.x)); + + float half_h = + static_cast(0.5 * + (std::exp(static_cast(box_centersize.h) / + static_cast(scale_values.h))) * + static_cast(anchor.h)); + float half_w = + static_cast(0.5 * + (std::exp(static_cast(box_centersize.w) / + static_cast(scale_values.w))) * + static_cast(anchor.w)); + + float* decoded_boxes = reinterpret_cast( + context->GetScratchBuffer(context, op_data->decoded_boxes_idx)); + auto& box = reinterpret_cast(decoded_boxes)[idx]; + box.ymin = ycenter - half_h; + box.xmin = xcenter - half_w; + box.ymax = ycenter + half_h; + box.xmax = xcenter + half_w; + } + return kTfLiteOk; +} + +void DecreasingPartialArgSort(const float* values, int num_values, + int num_to_sort, int* indices) { + std::iota(indices, indices + num_values, 0); + std::partial_sort(indices, indices + num_to_sort, indices + num_values, + [&values](const int i, const int j) { + return std::tie(values[i], j) > std::tie(values[j], i); + }); +} + +template +void InsertionSort(int* start, int* end, Compare compare) { + for (int* i = start; i != end; ++i) { + std::rotate(std::upper_bound(start, i, *i, compare), i, i + 1); + } +} + +template +void TopDownMerge(int* values, int* scratch, const int half_num_values, + int num_values, Compare compare) { + int left = 0; + int right = half_num_values; + + for (int i = 0; i < num_values; i++) { + if (left >= half_num_values || + (right < num_values && compare(values[right], values[left]))) { + scratch[i] = values[right++]; + } else { + scratch[i] = values[left++]; + } + } + memcpy(values, scratch, num_values * sizeof(int)); +} + +template +void MergeSort(int* values, int* scratch, const int num_values, + Compare compare) { + constexpr int threshold = 20; + + if (num_values < threshold) { + InsertionSort(values, values + num_values, compare); + return; + } + + const int half_num_values = num_values / 2; + + MergeSort(values, scratch, half_num_values, compare); + MergeSort(values + half_num_values, scratch, num_values - half_num_values, + compare); + TopDownMerge(values, scratch, half_num_values, num_values, compare); +} + +void DecreasingArgSort(const float* values, int num_values, int* indices, + int* scratch) { + std::iota(indices, indices + num_values, 0); + + MergeSort(indices, scratch, num_values, [&values](const int i, const int j) { + return values[i] > values[j]; + }); +} + +int SelectDetectionsAboveScoreThreshold(const float* values, int size, + const float threshold, + float* keep_values, int* keep_indices) { + int counter = 0; + for (int i = 0; i < size; i++) { + if (values[i] >= threshold) { + keep_values[counter] = values[i]; + keep_indices[counter] = i; + counter++; + } + } + return counter; +} + +bool ValidateBoxes(const float* decoded_boxes, const int num_boxes) { + for (int i = 0; i < num_boxes; ++i) { + // ymax>=ymin, xmax>=xmin + auto& box = reinterpret_cast(decoded_boxes)[i]; + if (box.ymin >= box.ymax || box.xmin >= box.xmax) { + return false; + } + } + return true; +} + +float ComputeIntersectionOverUnion(const float* decoded_boxes, const int i, + const int j) { + auto& box_i = reinterpret_cast(decoded_boxes)[i]; + auto& box_j = reinterpret_cast(decoded_boxes)[j]; + const float area_i = (box_i.ymax - box_i.ymin) * (box_i.xmax - box_i.xmin); + const float area_j = (box_j.ymax - box_j.ymin) * (box_j.xmax - box_j.xmin); + if (area_i <= 0 || area_j <= 0) return 0.0; + const float intersection_ymin = std::max(box_i.ymin, box_j.ymin); + const float intersection_xmin = std::max(box_i.xmin, box_j.xmin); + const float intersection_ymax = std::min(box_i.ymax, box_j.ymax); + const float intersection_xmax = std::min(box_i.xmax, box_j.xmax); + const float intersection_area = + std::max(intersection_ymax - intersection_ymin, 0.0) * + std::max(intersection_xmax - intersection_xmin, 0.0); + return intersection_area / (area_i + area_j - intersection_area); +} + +// NonMaxSuppressionSingleClass() prunes out the box locations with high overlap +// before selecting the highest scoring boxes (max_detections in number) +// It assumes all boxes are good in beginning and sorts based on the scores. +// If lower-scoring box has too much overlap with a higher-scoring box, +// we get rid of the lower-scoring box. +// Complexity is O(N^2) pairwise comparison between boxes +TfLiteStatus NonMaxSuppressionSingleClassHelper( + TfLiteContext* context, TfLiteNode* node, OpData* op_data, + const float* scores, int* selected, int* selected_size, + int max_detections) { + const TfLiteEvalTensor* input_box_encodings = + tflite::micro::GetEvalInput(context, node, kInputTensorBoxEncodings); + const int num_boxes = input_box_encodings->dims->data[1]; + const float non_max_suppression_score_threshold = + op_data->non_max_suppression_score_threshold; + const float intersection_over_union_threshold = + op_data->intersection_over_union_threshold; + // Maximum detections should be positive. + TF_LITE_ENSURE(context, (max_detections >= 0)); + // intersection_over_union_threshold should be positive + // and should be less than 1. + TF_LITE_ENSURE(context, (intersection_over_union_threshold > 0.0f) && + (intersection_over_union_threshold <= 1.0f)); + // Validate boxes + float* decoded_boxes = reinterpret_cast( + context->GetScratchBuffer(context, op_data->decoded_boxes_idx)); + + TF_LITE_ENSURE(context, ValidateBoxes(decoded_boxes, num_boxes)); + + // threshold scores + int* keep_indices = reinterpret_cast( + context->GetScratchBuffer(context, op_data->keep_indices_idx)); + float* keep_scores = reinterpret_cast( + context->GetScratchBuffer(context, op_data->keep_scores_idx)); + int num_scores_kept = SelectDetectionsAboveScoreThreshold( + scores, num_boxes, non_max_suppression_score_threshold, keep_scores, + keep_indices); + int* sorted_indices = reinterpret_cast( + context->GetScratchBuffer(context, op_data->sorted_indices_idx)); + + // Reusing keep_indices for scratch buffer and write back its values + // after the sorting is done. + DecreasingArgSort(keep_scores, num_scores_kept, sorted_indices, keep_indices); + int counter = 0; + for (int i = 0; i < num_boxes; i++) { + if (scores[i] >= non_max_suppression_score_threshold) { + keep_indices[counter] = i; + counter++; + } + } + + const int num_boxes_kept = num_scores_kept; + const int output_size = std::min(num_boxes_kept, max_detections); + *selected_size = 0; + + int num_active_candidate = num_boxes_kept; + uint8_t* active_box_candidate = reinterpret_cast( + context->GetScratchBuffer(context, op_data->active_candidate_idx)); + + for (int row = 0; row < num_boxes_kept; row++) { + active_box_candidate[row] = 1; + } + for (int i = 0; i < num_boxes_kept; ++i) { + if (num_active_candidate == 0 || *selected_size >= output_size) break; + if (active_box_candidate[i] == 1) { + selected[(*selected_size)++] = keep_indices[sorted_indices[i]]; + active_box_candidate[i] = 0; + num_active_candidate--; + } else { + continue; + } + for (int j = i + 1; j < num_boxes_kept; ++j) { + if (active_box_candidate[j] == 1) { + float intersection_over_union = ComputeIntersectionOverUnion( + decoded_boxes, keep_indices[sorted_indices[i]], + keep_indices[sorted_indices[j]]); + + if (intersection_over_union > intersection_over_union_threshold) { + active_box_candidate[j] = 0; + num_active_candidate--; + } + } + } + } + + return kTfLiteOk; +} + +// This function implements a regular version of Non Maximal Suppression (NMS) +// for multiple classes where +// 1) we do NMS separately for each class across all anchors and +// 2) keep only the highest anchor scores across all classes +// 3) The worst runtime of the regular NMS is O(K*N^2) +// where N is the number of anchors and K the number of +// classes. +TfLiteStatus NonMaxSuppressionMultiClassRegularHelper(TfLiteContext* context, + TfLiteNode* node, + OpData* op_data, + const float* scores) { + const TfLiteEvalTensor* input_box_encodings = + tflite::micro::GetEvalInput(context, node, kInputTensorBoxEncodings); + const TfLiteEvalTensor* input_class_predictions = + tflite::micro::GetEvalInput(context, node, kInputTensorClassPredictions); + TfLiteEvalTensor* detection_boxes = + tflite::micro::GetEvalOutput(context, node, kOutputTensorDetectionBoxes); + TfLiteEvalTensor* detection_classes = tflite::micro::GetEvalOutput( + context, node, kOutputTensorDetectionClasses); + TfLiteEvalTensor* detection_scores = + tflite::micro::GetEvalOutput(context, node, kOutputTensorDetectionScores); + TfLiteEvalTensor* num_detections = + tflite::micro::GetEvalOutput(context, node, kOutputTensorNumDetections); + + const int num_boxes = input_box_encodings->dims->data[1]; + const int num_classes = op_data->num_classes; + const int num_detections_per_class = op_data->detections_per_class; + const int max_detections = op_data->max_detections; + const int num_classes_with_background = + input_class_predictions->dims->data[2]; + // The row index offset is 1 if background class is included and 0 otherwise. + int label_offset = num_classes_with_background - num_classes; + TF_LITE_ENSURE(context, num_detections_per_class > 0); + + // For each class, perform non-max suppression. + float* class_scores = reinterpret_cast( + context->GetScratchBuffer(context, op_data->score_buffer_idx)); + int* box_indices_after_regular_non_max_suppression = reinterpret_cast( + context->GetScratchBuffer(context, op_data->buffer_idx)); + float* scores_after_regular_non_max_suppression = + reinterpret_cast(context->GetScratchBuffer( + context, op_data->scores_after_regular_non_max_suppression_idx)); + + int size_of_sorted_indices = 0; + int* sorted_indices = reinterpret_cast( + context->GetScratchBuffer(context, op_data->sorted_indices_idx)); + float* sorted_values = reinterpret_cast( + context->GetScratchBuffer(context, op_data->sorted_values_idx)); + + for (int col = 0; col < num_classes; col++) { + for (int row = 0; row < num_boxes; row++) { + // Get scores of boxes corresponding to all anchors for single class + class_scores[row] = + *(scores + row * num_classes_with_background + col + label_offset); + } + // Perform non-maximal suppression on single class + int selected_size = 0; + int* selected = reinterpret_cast( + context->GetScratchBuffer(context, op_data->selected_idx)); + TF_LITE_ENSURE_STATUS(NonMaxSuppressionSingleClassHelper( + context, node, op_data, class_scores, selected, &selected_size, + num_detections_per_class)); + // Add selected indices from non-max suppression of boxes in this class + int output_index = size_of_sorted_indices; + for (int i = 0; i < selected_size; i++) { + int selected_index = selected[i]; + + box_indices_after_regular_non_max_suppression[output_index] = + (selected_index * num_classes_with_background + col + label_offset); + scores_after_regular_non_max_suppression[output_index] = + class_scores[selected_index]; + output_index++; + } + // Sort the max scores among the selected indices + // Get the indices for top scores + int num_indices_to_sort = std::min(output_index, max_detections); + DecreasingPartialArgSort(scores_after_regular_non_max_suppression, + output_index, num_indices_to_sort, sorted_indices); + + // Copy values to temporary vectors + for (int row = 0; row < num_indices_to_sort; row++) { + int temp = sorted_indices[row]; + sorted_indices[row] = box_indices_after_regular_non_max_suppression[temp]; + sorted_values[row] = scores_after_regular_non_max_suppression[temp]; + } + // Copy scores and indices from temporary vectors + for (int row = 0; row < num_indices_to_sort; row++) { + box_indices_after_regular_non_max_suppression[row] = sorted_indices[row]; + scores_after_regular_non_max_suppression[row] = sorted_values[row]; + } + size_of_sorted_indices = num_indices_to_sort; + } + + // Allocate output tensors + for (int output_box_index = 0; output_box_index < max_detections; + output_box_index++) { + if (output_box_index < size_of_sorted_indices) { + const int anchor_index = floor( + box_indices_after_regular_non_max_suppression[output_box_index] / + num_classes_with_background); + const int class_index = + box_indices_after_regular_non_max_suppression[output_box_index] - + anchor_index * num_classes_with_background - label_offset; + const float selected_score = + scores_after_regular_non_max_suppression[output_box_index]; + // detection_boxes + float* decoded_boxes = reinterpret_cast( + context->GetScratchBuffer(context, op_data->decoded_boxes_idx)); + ReInterpretTensor(detection_boxes)[output_box_index] = + reinterpret_cast(decoded_boxes)[anchor_index]; + // detection_classes + tflite::micro::GetTensorData(detection_classes)[output_box_index] = + class_index; + // detection_scores + tflite::micro::GetTensorData(detection_scores)[output_box_index] = + selected_score; + } else { + ReInterpretTensor( + detection_boxes)[output_box_index] = {0.0f, 0.0f, 0.0f, 0.0f}; + // detection_classes + tflite::micro::GetTensorData(detection_classes)[output_box_index] = + 0.0f; + // detection_scores + tflite::micro::GetTensorData(detection_scores)[output_box_index] = + 0.0f; + } + } + tflite::micro::GetTensorData(num_detections)[0] = + size_of_sorted_indices; + + return kTfLiteOk; +} + +// This function implements a fast version of Non Maximal Suppression for +// multiple classes where +// 1) we keep the top-k scores for each anchor and +// 2) during NMS, each anchor only uses the highest class score for sorting. +// 3) Compared to standard NMS, the worst runtime of this version is O(N^2) +// instead of O(KN^2) where N is the number of anchors and K the number of +// classes. +TfLiteStatus NonMaxSuppressionMultiClassFastHelper(TfLiteContext* context, + TfLiteNode* node, + OpData* op_data, + const float* scores) { + const TfLiteEvalTensor* input_box_encodings = + tflite::micro::GetEvalInput(context, node, kInputTensorBoxEncodings); + const TfLiteEvalTensor* input_class_predictions = + tflite::micro::GetEvalInput(context, node, kInputTensorClassPredictions); + TfLiteEvalTensor* detection_boxes = + tflite::micro::GetEvalOutput(context, node, kOutputTensorDetectionBoxes); + + TfLiteEvalTensor* detection_classes = tflite::micro::GetEvalOutput( + context, node, kOutputTensorDetectionClasses); + TfLiteEvalTensor* detection_scores = + tflite::micro::GetEvalOutput(context, node, kOutputTensorDetectionScores); + TfLiteEvalTensor* num_detections = + tflite::micro::GetEvalOutput(context, node, kOutputTensorNumDetections); + + const int num_boxes = input_box_encodings->dims->data[1]; + const int num_classes = op_data->num_classes; + const int max_categories_per_anchor = op_data->max_classes_per_detection; + const int num_classes_with_background = + input_class_predictions->dims->data[2]; + + // The row index offset is 1 if background class is included and 0 otherwise. + int label_offset = num_classes_with_background - num_classes; + TF_LITE_ENSURE(context, (max_categories_per_anchor > 0)); + const int num_categories_per_anchor = + std::min(max_categories_per_anchor, num_classes); + float* max_scores = reinterpret_cast( + context->GetScratchBuffer(context, op_data->score_buffer_idx)); + int* sorted_class_indices = reinterpret_cast( + context->GetScratchBuffer(context, op_data->buffer_idx)); + + for (int row = 0; row < num_boxes; row++) { + const float* box_scores = + scores + row * num_classes_with_background + label_offset; + int* class_indices = sorted_class_indices + row * num_classes; + DecreasingPartialArgSort(box_scores, num_classes, num_categories_per_anchor, + class_indices); + max_scores[row] = box_scores[class_indices[0]]; + } + + // Perform non-maximal suppression on max scores + int selected_size = 0; + int* selected = reinterpret_cast( + context->GetScratchBuffer(context, op_data->selected_idx)); + TF_LITE_ENSURE_STATUS(NonMaxSuppressionSingleClassHelper( + context, node, op_data, max_scores, selected, &selected_size, + op_data->max_detections)); + + // Allocate output tensors + int output_box_index = 0; + + for (int i = 0; i < selected_size; i++) { + int selected_index = selected[i]; + + const float* box_scores = + scores + selected_index * num_classes_with_background + label_offset; + const int* class_indices = + sorted_class_indices + selected_index * num_classes; + + for (int col = 0; col < num_categories_per_anchor; ++col) { + int box_offset = num_categories_per_anchor * output_box_index + col; + + // detection_boxes + float* decoded_boxes = reinterpret_cast( + context->GetScratchBuffer(context, op_data->decoded_boxes_idx)); + ReInterpretTensor(detection_boxes)[box_offset] = + reinterpret_cast(decoded_boxes)[selected_index]; + + // detection_classes + tflite::micro::GetTensorData(detection_classes)[box_offset] = + class_indices[col]; + + // detection_scores + tflite::micro::GetTensorData(detection_scores)[box_offset] = + box_scores[class_indices[col]]; + + output_box_index++; + } + } + + tflite::micro::GetTensorData(num_detections)[0] = output_box_index; + return kTfLiteOk; +} + +TfLiteStatus NonMaxSuppressionMultiClass(TfLiteContext* context, + TfLiteNode* node, OpData* op_data) { + // Get the input tensors + const TfLiteEvalTensor* input_box_encodings = + tflite::micro::GetEvalInput(context, node, kInputTensorBoxEncodings); + const TfLiteEvalTensor* input_class_predictions = + tflite::micro::GetEvalInput(context, node, kInputTensorClassPredictions); + const int num_boxes = input_box_encodings->dims->data[1]; + const int num_classes = op_data->num_classes; + + TF_LITE_ENSURE_EQ(context, input_class_predictions->dims->data[0], + kBatchSize); + TF_LITE_ENSURE_EQ(context, input_class_predictions->dims->data[1], num_boxes); + const int num_classes_with_background = + input_class_predictions->dims->data[2]; + + TF_LITE_ENSURE(context, (num_classes_with_background - num_classes <= 1)); + TF_LITE_ENSURE(context, (num_classes_with_background >= num_classes)); + + const float* scores; + switch (input_class_predictions->type) { + case kTfLiteFloat32: + scores = tflite::micro::GetTensorData(input_class_predictions); + break; + default: + // Unsupported type. + return kTfLiteError; + } + + if (op_data->use_regular_non_max_suppression) { + TF_LITE_ENSURE_STATUS(NonMaxSuppressionMultiClassRegularHelper( + context, node, op_data, scores)); + } else { + TF_LITE_ENSURE_STATUS( + NonMaxSuppressionMultiClassFastHelper(context, node, op_data, scores)); + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE(context, (kBatchSize == 1)); + auto* op_data = static_cast(node->user_data); + + // These two functions correspond to two blocks in the Object Detection model. + // In future, we would like to break the custom op in two blocks, which is + // currently not feasible because we would like to input quantized inputs + // and do all calculations in float. Mixed quantized/float calculations are + // currently not supported in TFLite. + + // This fills in temporary decoded_boxes + // by transforming input_box_encodings and input_anchors from + // CenterSizeEncodings to BoxCornerEncoding + TF_LITE_ENSURE_STATUS(DecodeCenterSizeBoxes(context, node, op_data)); + + // This fills in the output tensors + // by choosing effective set of decoded boxes + // based on Non Maximal Suppression, i.e. selecting + // highest scoring non-overlapping boxes. + TF_LITE_ENSURE_STATUS(NonMaxSuppressionMultiClass(context, node, op_data)); + + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration* Register_DETECTION_POSTPROCESS() { + static TfLiteRegistration r = tflite::micro::RegisterOp(Init, Prepare, Eval); + return &r; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.h new file mode 100644 index 0000000..f5b9eae --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.h @@ -0,0 +1,25 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_FLEXBUFFERS_GENERATED_DATA_H +#define TENSORFLOW_LITE_MICRO_KERNELS_FLEXBUFFERS_GENERATED_DATA_H + +extern const int g_gen_data_size_none_regular_nms; +extern const unsigned char g_gen_data_none_regular_nms[]; + +extern const int g_gen_data_size_regular_nms; +extern const unsigned char g_gen_data_regular_nms[]; + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/div.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/div.cpp new file mode 100644 index 0000000..e5fb262 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/div.cpp @@ -0,0 +1,208 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/div.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +struct OpDataDiv { + // Parameters used in the quantized paths where the output is 8bit + int32_t input1_zero_point; + int32_t input2_zero_point; + int32_t output_zero_point; + int32_t output_activation_min; + int32_t output_activation_max; + + // Parameters used in all quantized paths + int32_t output_multiplier; + int output_shift; +}; + +TfLiteStatus CalculateOpDataDiv(TfLiteContext* context, TfLiteTensor* input1, + TfLiteTensor* input2, TfLiteTensor* output, + TfLiteDivParams* params, OpDataDiv* data) { + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, input2->type); + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, output->type); + + if (output->type == kTfLiteInt8) { + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + const double real_multiplier = static_cast( + input1->params.scale / (input2->params.scale * output->params.scale)); + QuantizeMultiplier(real_multiplier, &data->output_multiplier, + &data->output_shift); + data->input1_zero_point = input1->params.zero_point; + data->input2_zero_point = input2->params.zero_point; + data->output_zero_point = output->params.zero_point; + } + + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataDiv)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + OpDataDiv* data = static_cast(node->user_data); + auto* params = reinterpret_cast(node->builtin_data); + + TF_LITE_ENSURE_STATUS( + CalculateOpDataDiv(context, input1, input2, output, params, data)); + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +void EvalDiv(TfLiteContext* context, TfLiteNode* node, TfLiteDivParams* params, + const OpDataDiv* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params = {}; + +#define TF_LITE_DIV(type, opname, data_type) \ + data_type output_activation_min, output_activation_max; \ + CalculateActivationRange(params->activation, &output_activation_min, \ + &output_activation_max); \ + SetActivationParams(output_activation_min, output_activation_max, \ + &op_params); \ + type::opname(op_params, tflite::micro::GetTensorShape(input1), \ + tflite::micro::GetTensorData(input1), \ + tflite::micro::GetTensorShape(input2), \ + tflite::micro::GetTensorData(input2), \ + tflite::micro::GetTensorShape(output), \ + tflite::micro::GetTensorData(output)) + + bool requires_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (requires_broadcast) { + TF_LITE_DIV(reference_ops, BroadcastDivSlow, float); + } else { + TF_LITE_DIV(reference_ops, Div, float); + } +#undef TF_LITE_DIV +} + +TfLiteStatus EvalQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteDivParams* params, const OpDataDiv* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params = {}; + +#define TF_LITE_DIV(type, opname, dtype) \ + type::opname(op_params, tflite::micro::GetTensorShape(input1), \ + tflite::micro::GetTensorData(input1), \ + tflite::micro::GetTensorShape(input2), \ + tflite::micro::GetTensorData(input2), \ + tflite::micro::GetTensorShape(output), \ + tflite::micro::GetTensorData(output)) + + if (input1->type == kTfLiteInt8 && input2->type == kTfLiteInt8 && + output->type == kTfLiteInt8) { + SetActivationParams(data->output_activation_min, + data->output_activation_max, &op_params); + op_params.input1_offset = -data->input1_zero_point; + op_params.input2_offset = -data->input2_zero_point; + op_params.output_offset = data->output_zero_point; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + + bool requires_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (requires_broadcast) { + TF_LITE_DIV(reference_ops, BroadcastDivSlow, int8_t); + } else { + TF_LITE_DIV(reference_ops, Div, int8_t); + } +#undef TF_LITE_DIV + } else { + MicroPrintf("Unsupported combination of input and output types in DIV."); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = static_cast(node->builtin_data); + TFLITE_DCHECK(node->user_data != nullptr); + auto* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (output->type == kTfLiteFloat32) { + EvalDiv(context, node, params, data, input1, input2, output); + } else if (output->type == kTfLiteInt8) { + TF_LITE_ENSURE_OK(context, EvalQuantized(context, node, params, data, + input1, input2, output)); + } else { + MicroPrintf( + "DIV only supports FLOAT32, quantized INT8 " + "now, got type %s (%d).", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_DIV() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/elementwise.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/elementwise.cpp new file mode 100644 index 0000000..4ee7f2c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/elementwise.cpp @@ -0,0 +1,430 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace elementwise { +namespace { + +constexpr int kAbsNameId = 0; +constexpr int kRsrqtNameId = 1; + +const int kElementwiseInputTensor = 0; +const int kElementwiseOutputTensor = 0; + +struct OpDataAbsRsqrt { + int32_t multiplier; + int shift; + int input_offset; + int output_offset; + bool needs_rescale; + TfLiteQuantizationType input_quantization_type; + TfLiteType input_type; +}; + +bool IsNumericSupportedType(const TfLiteType type) { + return type == kTfLiteFloat32; +} + +bool IsLogicalSupportedType(const TfLiteType type) { + return type == kTfLiteBool; +} + +bool IsAbsSupportedType(const TfLiteType type) { + return type == kTfLiteFloat32 || type == kTfLiteInt8 || type == kTfLiteInt16; +} + +bool IsRsqrtSupportedType(const TfLiteType type) { + return type == kTfLiteFloat32 || type == kTfLiteInt8; +} + +inline void SetAbsOutputMultiplier(const float input_scale, + const float output_scale, + int32_t* multiplier, int* shift) { + QuantizeMultiplier(static_cast(input_scale / output_scale), + multiplier, shift); +} + +inline void SetRsqrtOutputMultiplier(const float input_scale, + const float output_scale, + int32_t* multiplier, int* shift) { + const double scale = + 1. / static_cast((std::sqrt(input_scale) * output_scale)); + QuantizeMultiplier(scale, multiplier, shift); +} + +typedef bool (*IsSupportedType)(TfLiteType); +template +TfLiteStatus GenericPrepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kElementwiseInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kElementwiseOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + if (!IsSupportedType(input->type)) { + MicroPrintf("Input data type %s (%d) is not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +typedef bool (*IsSupportedType)(TfLiteType); +template +TfLiteStatus PrepareAbsRsqrt(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + if (!IsSupportedType(input->type)) { + MicroPrintf("Input data type %s (%d) is not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + + auto* op_data = static_cast(node->user_data); + op_data->input_type = input->type; + + // For int16 type input, we support both quantized and non-quantized + // evaluation. + if (op_nameid == kAbsNameId) { + op_data->input_quantization_type = input->quantization.type; + } + + if (input->type == kTfLiteInt8 || + (input->type == kTfLiteInt16 && + input->quantization.type != kTfLiteNoQuantization)) { + TF_LITE_ENSURE_EQ(context, input->quantization.type, + kTfLiteAffineQuantization); + TF_LITE_ENSURE_EQ(context, output->quantization.type, + kTfLiteAffineQuantization); + const auto* input_params = + reinterpret_cast(input->quantization.params); + const auto* output_params = reinterpret_cast( + output->quantization.params); + TF_LITE_ENSURE(context, input_params != nullptr); + TF_LITE_ENSURE(context, input_params->scale != nullptr); + TF_LITE_ENSURE(context, input_params->scale->size > 0); + TF_LITE_ENSURE(context, input_params->zero_point->size > 0); + TF_LITE_ENSURE(context, output_params != nullptr); + TF_LITE_ENSURE(context, output_params->scale != nullptr); + TF_LITE_ENSURE(context, output_params->scale->size > 0); + TF_LITE_ENSURE(context, output_params->zero_point->size > 0); + op_data->input_offset = input_params->zero_point->data[0]; + op_data->output_offset = output_params->zero_point->data[0]; + if (input->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, op_data->input_offset, 0); + TF_LITE_ENSURE_EQ(context, op_data->output_offset, 0); + } + const float input_scale = input_params->scale->data[0]; + const float output_scale = output_params->scale->data[0]; + op_data->needs_rescale = input_scale != output_scale; + if (op_nameid == kAbsNameId && op_data->needs_rescale) { + SetAbsOutputMultiplier(input_scale, output_scale, &op_data->multiplier, + &op_data->shift); + } else if (op_nameid == kRsrqtNameId) { + SetRsqrtOutputMultiplier(input_scale, output_scale, &op_data->multiplier, + &op_data->shift); + } + } + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +template +inline TfLiteStatus EvalImplQuantized( + TfLiteContext* context, TfLiteNode* node, + T func(TfLiteContext*, TfLiteNode*, T), + TfLiteStatus validate_input_func(TfLiteContext*, TfLiteNode*, T), + TfLiteType expected_type) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, expected_type); + const size_t num_elements = ElementCount(*input->dims); + const T* in_data = tflite::micro::GetTensorData(input); + T* out_data = tflite::micro::GetTensorData(output); + for (size_t i = 0; i < num_elements; ++i) { + if (validate_input_func) { + TF_LITE_ENSURE_OK(context, + validate_input_func(context, node, in_data[i])); + } + out_data[i] = func(context, node, in_data[i]); + } + return kTfLiteOk; +} + +template +inline T AbsHelper(T i) { + return std::abs(i); +} + +template +inline TfLiteStatus EvalImpl(TfLiteContext* context, TfLiteNode* node, + T func(T), TfLiteStatus validate_input_func(T), + TfLiteType expected_type) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, expected_type); + const size_t num_elements = ElementCount(*input->dims); + const T* in_data = tflite::micro::GetTensorData(input); + T* out_data = tflite::micro::GetTensorData(output); + for (size_t i = 0; i < num_elements; ++i) { + if (validate_input_func) { + TF_LITE_ENSURE_OK(context, validate_input_func(in_data[i])); + } + out_data[i] = func(in_data[i]); + } + return kTfLiteOk; +} + +inline TfLiteStatus EvalNumeric(TfLiteContext* context, TfLiteNode* node, + float float_func(float)) { + return EvalImpl(context, node, float_func, + /*validate_input_func=*/nullptr, kTfLiteFloat32); +} + +inline TfLiteStatus EvalLogical(TfLiteContext* context, TfLiteNode* node, + + bool bool_func(bool)) { + return EvalImpl(context, node, bool_func, + /*validate_input_func=*/nullptr, kTfLiteBool); +} + +void* ElementWiseAbsRsqrtInit(TfLiteContext* context, const char* buffer, + size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataAbsRsqrt)); +} + +template +inline T AbsEvalQuantized(TfLiteContext* context, TfLiteNode* node, T i) { + const auto* op_data = static_cast(node->user_data); + const int kMin = std::numeric_limits::min(); + const int kMax = std::numeric_limits::max(); + + const int32_t value = std::abs(i - op_data->input_offset); + if (!op_data->needs_rescale) { + return static_cast( + std::min(std::max(static_cast(value + op_data->output_offset), + static_cast(kMin)), + static_cast(kMax))); + } + + const int32_t output = tflite::MultiplyByQuantizedMultiplier( + value, op_data->multiplier, op_data->shift) + + op_data->output_offset; + return static_cast(std::min( + std::max(static_cast(output), static_cast(kMin)), + static_cast(kMax))); +} + +template +inline T RsqrtEvalQuantized(TfLiteContext* context, TfLiteNode* node, T i) { + const auto* op_data = static_cast(node->user_data); + const int kMin = std::numeric_limits::min(); + const int kMax = std::numeric_limits::max(); + + const int32_t value = (i - op_data->input_offset); + const int32_t kShift = 20; // Shift to keep value integer. + if (value == 0) { + // Assume that any value close to 0 represents the max output value. + return static_cast(kMax); + } + int32_t inv_sqrt_multiplier; + int inv_sqrt_shift; + GetInvSqrtQuantizedMultiplierExp(value, kReverseShift, &inv_sqrt_multiplier, + &inv_sqrt_shift); + const int32_t data = tflite::MultiplyByQuantizedMultiplier( + static_cast(1), inv_sqrt_multiplier, inv_sqrt_shift + kShift); + const int32_t output = + tflite::MultiplyByQuantizedMultiplier(data, op_data->multiplier, + op_data->shift - kShift) + + op_data->output_offset; + return static_cast(std::min( + std::max(static_cast(output), static_cast(kMin)), + static_cast(kMax))); +} + +template +TfLiteStatus validate_input_func(TfLiteContext* context, TfLiteNode* node, + T i) { + const auto* op_data = static_cast(node->user_data); + + TF_LITE_ENSURE_MSG(context, i >= op_data->input_offset, + "Rsqrt is only defined for positive values"); + return static_cast(kTfLiteOk); +} + +TfLiteStatus AbsEval(TfLiteContext* context, TfLiteNode* node) { + OpDataAbsRsqrt* op_data = reinterpret_cast(node->user_data); + TfLiteType type = op_data->input_type; + TfLiteQuantizationType input_quantization_type = + op_data->input_quantization_type; + TfLiteStatus eval_result; + + switch (type) { + case kTfLiteFloat32: + eval_result = EvalNumeric(context, node, std::abs); + break; + case kTfLiteInt8: + eval_result = + EvalImplQuantized(context, node, AbsEvalQuantized, + /*validate_input_func=*/nullptr, type); + break; + case kTfLiteInt16: + eval_result = + input_quantization_type == kTfLiteNoQuantization + ? EvalImpl(context, node, AbsHelper, + /*validate_input_func=*/nullptr, type) + : EvalImplQuantized(context, node, AbsEvalQuantized, + /*validate_input_func=*/nullptr, + type); + break; + default: + MicroPrintf("Current data type %s is not supported.", + TfLiteTypeGetName(type)); + return kTfLiteError; + break; + } + return eval_result; +} + +TfLiteStatus SinEval(TfLiteContext* context, TfLiteNode* node) { + return EvalNumeric(context, node, std::sin); +} + +TfLiteStatus CosEval(TfLiteContext* context, TfLiteNode* node) { + return EvalNumeric(context, node, std::cos); +} + +TfLiteStatus LogEval(TfLiteContext* context, TfLiteNode* node) { + return EvalNumeric(context, node, std::log); +} + +TfLiteStatus SqrtEval(TfLiteContext* context, TfLiteNode* node) { + return EvalNumeric(context, node, std::sqrt); +} + +TfLiteStatus RsqrtEval(TfLiteContext* context, TfLiteNode* node) { + const auto* op_data = static_cast(node->user_data); + TfLiteType type = op_data->input_type; + switch (type) { + case kTfLiteFloat32: + return EvalImpl( + context, node, [](float f) { return 1.f / std::sqrt(f); }, + /*validate_input_func=*/nullptr, type); + case kTfLiteInt8: + return EvalImplQuantized(context, node, + elementwise::RsqrtEvalQuantized, + elementwise::validate_input_func, type); + + default: + MicroPrintf("Current data type %s is not supported.", + TfLiteTypeGetName(type)); + return kTfLiteError; + } +} + +TfLiteStatus SquareEval(TfLiteContext* context, TfLiteNode* node) { + return EvalNumeric(context, node, [](float f) { return f * f; }); +} + +TfLiteStatus LogicalNotEval(TfLiteContext* context, TfLiteNode* node) { + return EvalLogical(context, node, [](bool v) { return !v; }); +} + +} // namespace +} // namespace elementwise + +TfLiteRegistration Register_ABS() { + return tflite::micro::RegisterOp( + elementwise::ElementWiseAbsRsqrtInit, + elementwise::PrepareAbsRsqrt, + elementwise::AbsEval); +} + +TfLiteRegistration Register_SIN() { + return tflite::micro::RegisterOp( + nullptr, elementwise::GenericPrepare, + elementwise::SinEval); +} + +TfLiteRegistration Register_COS() { + return tflite::micro::RegisterOp( + nullptr, elementwise::GenericPrepare, + elementwise::CosEval); +} + +TfLiteRegistration Register_LOG() { + return tflite::micro::RegisterOp( + nullptr, elementwise::GenericPrepare, + elementwise::LogEval); +} + +TfLiteRegistration Register_SQRT() { + return tflite::micro::RegisterOp( + nullptr, elementwise::GenericPrepare, + elementwise::SqrtEval); +} + +TfLiteRegistration Register_RSQRT() { + return tflite::micro::RegisterOp( + elementwise::ElementWiseAbsRsqrtInit, + elementwise::PrepareAbsRsqrt, + elementwise::RsqrtEval); +} + +TfLiteRegistration Register_SQUARE() { + return tflite::micro::RegisterOp( + nullptr, elementwise::GenericPrepare, + elementwise::SquareEval); +} + +TfLiteRegistration Register_LOGICAL_NOT() { + return tflite::micro::RegisterOp( + nullptr, elementwise::GenericPrepare, + elementwise::LogicalNotEval); +} + +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/elu.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/elu.cpp new file mode 100644 index 0000000..7581772 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/elu.cpp @@ -0,0 +1,151 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/elu.h" + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +// Input/output tensor index. +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +// OLD-TODO(b/142762739): We should figure out a multi-threading plan for most +// of the activation ops below. + +struct OpData { + int8_t table[256]; +}; + +using TransformFunc = float (*)(float); + +template +void PopulateLookupTable(const TfLiteTensor* input, const TfLiteTensor* output, + const TransformFunc transform, OpData* data) { + if (sizeof(T) != 1) { + MicroPrintf("Lookup table valid only for 8bit"); + TFLITE_ABORT; + } + + const float inverse_scale = 1 / output->params.scale; + int32_t maxval = std::numeric_limits::max(); + int32_t minval = std::numeric_limits::min(); + for (int32_t val = minval; val <= maxval; ++val) { + const float dequantized = + input->params.scale * (val - input->params.zero_point); + const float transformed = transform(dequantized); + const float rescaled = TfLiteRound(transformed * inverse_scale); + const int32_t quantized = + static_cast(rescaled + output->params.zero_point); + data->table[static_cast(static_cast(val))] = + static_cast(std::max(std::min(maxval, quantized), minval)); + } +} + +// OLD-TODO(b/143696793): move this to optimized_ops. +void EvalUsingLookupTable(const OpData* data, const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + const int size = MatchingFlatSize(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorShape(output)); + int8_t* output_data = tflite::micro::GetTensorData(output); + const int8_t* input_data = tflite::micro::GetTensorData(input); + + for (int i = 0; i < size; ++i) { + output_data[i] = data->table[static_cast(input_data[i])]; + } +} + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + // Use LUT to handle quantized elu path. + if (input->type == kTfLiteInt8) { + OpData* data = static_cast(node->user_data); + TransformFunc transform = [](float value) { + return value < 0.0f ? std::exp(value) - 1.0f : value; + }; + PopulateLookupTable(input, output, transform, data); + } + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +void* EluInit(TfLiteContext* context, const char* buffer, size_t length) { + // This is a builtin op, so we don't use the contents in 'buffer', if any. + // Instead, we allocate a new object to carry information from Prepare() to + // Eval(). + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus EluPrepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +TfLiteStatus EluEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + switch (input->type) { + case kTfLiteFloat32: { + reference_ops::Elu(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + case kTfLiteInt8: { + const OpData* data = static_cast(node->user_data); + EvalUsingLookupTable(data, input, output); + return kTfLiteOk; + } + default: + MicroPrintf("ELU only supports float32 and int8 currently, got %s.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } +} + +} // namespace + +TfLiteRegistration Register_ELU() { + return tflite::micro::RegisterOp(EluInit, EluPrepare, EluEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ethosu.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ethosu.cpp new file mode 100644 index 0000000..e2bccde --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ethosu.cpp @@ -0,0 +1,214 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#define FLATBUFFERS_LOCALE_INDEPENDENT 0 +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#if EI_CLASSIFIER_TFLITE_ETHOSU_POLYFILL || EI_ETHOS + +#if EI_CLASSIFIER_TFLITE_ETHOSU_POLYFILL +// Modified by Edge Impulse +// Add stub definitions so that EON Compiler can run + +int ethosu_invoke(struct ethosu_driver *drv, + const void *custom_data_ptr, + const int custom_data_size, + const uint64_t *base_addr, + const size_t *base_addr_size, + const int num_base_addr) +{ return 0; } + +// forward declare the struct +struct ethosu_driver; + +struct ethosu_driver *ethosu_reserve_driver(void) { return nullptr; } +void ethosu_release_driver(struct ethosu_driver *drv) {} +#else +#include +#endif +namespace tflite { +namespace { + +constexpr uint8_t CO_TYPE_ETHOSU = 1; + +struct OpData { + int cms_data_size; + int base_addr_idx; + int base_addr_size_idx; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +void Free(TfLiteContext* context, void* buffer) {} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(context != nullptr); + TF_LITE_ENSURE(context, node->inputs->size > 0); + TFLITE_DCHECK(node->user_data != nullptr); + TF_LITE_ENSURE(context, node->custom_initial_data_size > 0); + + OpData* data = static_cast(node->user_data); + int num_base_addr = node->inputs->size + node->outputs->size; + + // Request arrays for the base address pointers and sizes. + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, num_base_addr * sizeof(uint64_t), &data->base_addr_idx)); + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, num_base_addr * sizeof(size_t), &data->base_addr_size_idx)); + + // Get command stream data size. + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* tensor = micro_context->AllocateTempInputTensor(node, 0); + data->cms_data_size = tensor->bytes; + micro_context->DeallocateTempTfLiteTensor(tensor); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(context->GetScratchBuffer != nullptr); + + // Get base addresses. + TfLiteEvalTensor* tensor; + int i = 0; + int num_tensors = 0; + void* cms_data; + uint8_t co_type; + int result; + const OpData* data = static_cast(node->user_data); + uint64_t* base_addrs = static_cast( + context->GetScratchBuffer(context, data->base_addr_idx)); + size_t* base_addrs_size = static_cast( + context->GetScratchBuffer(context, data->base_addr_size_idx)); + + const uint8_t* custom_data = + static_cast(node->custom_initial_data); + auto root = flexbuffers::GetRoot(custom_data, node->custom_initial_data_size); + co_type = root.AsInt8(); + if (co_type != CO_TYPE_ETHOSU) { + MicroPrintf("CO_TYPE != ETHOSU"); + return kTfLiteError; + } + + // Get command stream data address. + tensor = context->GetEvalTensor(context, node->inputs->data[0]); + cms_data = reinterpret_cast(tensor->data.uint8); + + // Get addresses to weights/scratch/input data. + for (i = 1; i < node->inputs->size; ++i) { + tensor = context->GetEvalTensor(context, node->inputs->data[i]); + base_addrs[num_tensors] = + static_cast(reinterpret_cast(tensor->data.uint8)); + size_t byte_size = 1; + for (int k = 0; k < tensor->dims->size; k++) { + byte_size = byte_size * tensor->dims->data[k]; + } + base_addrs_size[num_tensors] = byte_size; + num_tensors++; + } + + // Get addresses to output data. + for (i = 0; i < node->outputs->size; ++i) { + tensor = context->GetEvalTensor(context, node->outputs->data[i]); + base_addrs[num_tensors] = + static_cast(reinterpret_cast(tensor->data.uint8)); + size_t byte_size = 1; + for (int k = 0; k < tensor->dims->size; k++) { + byte_size = byte_size * tensor->dims->data[k]; + } + base_addrs_size[num_tensors] = byte_size; + num_tensors++; + } + + // Ethos-U guarantees that the tensors that require a base pointer are among + // the 8 first tensors + // When Vela optimizes a tflite file it will assign the tensors like this: + // + // +-------+------------------------+ +--------+-------------+ + // | INPUT | Description | | OUTPUT | Description | + // +-------+------------------------+ +--------+-------------+ + // | 0 | Ethos-U command stream | | 0..m | Outputs | + // | 1 | TFLM model | +--------+-------------+ + // | 2 | TFLM arena | + // | 3 | Ethos-U fast scratch | + // | 4..n | Inputs | + // +-------+------------------------+ + // + // This code will assign the NPU base addresses like this: + // + // +--------------+----------------------+ + // | Base address | Description | + // +--------------+----------------------+ + // | 0 | TFLM model | + // | 1 | TFLM arena | + // | 2 | Ethos-U fast scratch | + // | 3..n | Input tensors | + // | n..m | Output tensors | + // +--------------+----------------------+ + // + // The number of base address will be limited to 8. + // + // NOTE! The command stream produced by Vela will access the IFM and OFM + // buffers using base address 1. This means that it is not possible to point + // the input and output tensors outside of the TFLM arena. + num_tensors = std::min(num_tensors, 8); + + struct ethosu_driver* drv = ethosu_reserve_driver(); + result = ethosu_invoke(drv, cms_data, data->cms_data_size, base_addrs, + base_addrs_size, num_tensors); + ethosu_release_driver(drv); + + if (-1 == result) { + return kTfLiteError; + } else { + return kTfLiteOk; + } +} + +} // namespace + +TfLiteRegistration* Register_ETHOSU() { + static TfLiteRegistration r = tflite::micro::RegisterOp(Init, Prepare, Eval); + return &r; +} + +const char* GetString_ETHOSU() { return "ethos-u"; } + +} // namespace tflite + +#else + +// +// This is a stub file for non-Ethos platforms +// +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +TfLiteRegistration* Register_ETHOSU() { return nullptr; } + +const char* GetString_ETHOSU() { return ""; } + +} // namespace tflite + +#endif // Ethos flag \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ethosu.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ethosu.h new file mode 100644 index 0000000..fd61d65 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/ethosu.h @@ -0,0 +1,28 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_ETHOSU_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_ETHOSU_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +TfLiteRegistration* Register_ETHOSU(); + +const char* GetString_ETHOSU(); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_ETHOSU_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/exp.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/exp.cpp new file mode 100644 index 0000000..c727cb9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/exp.cpp @@ -0,0 +1,79 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/exp.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteFloat32); + TF_LITE_ENSURE_TYPES_EQ(context, output->type, input->type); + TF_LITE_ENSURE_EQ(context, output->bytes, input->bytes); + TF_LITE_ENSURE_EQ(context, output->dims->size, input->dims->size); + for (int i = 0; i < output->dims->size; ++i) { + TF_LITE_ENSURE_EQ(context, output->dims->data[i], input->dims->data[i]); + } + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + int flat_size = MatchingFlatSize(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorShape(output)); + + if (input->type == kTfLiteFloat32) { + reference_ops::Exp(tflite::micro::GetTensorData(input), + static_cast(flat_size), + tflite::micro::GetTensorData(output)); + } else { + MicroPrintf("Type %s (%d) currently not supported by Exp.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration Register_EXP() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/expand_dims.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/expand_dims.cpp new file mode 100644 index 0000000..f2b638b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/expand_dims.cpp @@ -0,0 +1,149 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kAxisTensor = 1; +constexpr int kOutputTensor = 0; + +TfLiteStatus GetAxisValueFromTensor(TfLiteContext* context, + const TfLiteTensor* axis, + int32_t* axis_value) { + const int axis_dims = (tflite::GetTensorShape(axis)).DimensionsCount(); + if (axis_dims > 1) { + MicroPrintf("Axis has only one element for Expand_Dims.", axis_dims); + return kTfLiteError; + } + + if (kTfLiteInt32 == (axis->type)) { + const int32_t* axis_ptr = tflite::GetTensorData(axis); + *axis_value = axis_ptr[0]; + return kTfLiteOk; + } else { + MicroPrintf("Axis type %s (%d) not supported by Expand_Dims.", + TfLiteTypeGetName(axis->type), axis->type); + return kTfLiteError; + } +} + +// Verifies that the output tensor's dimension shape is equivalent to inserting +// a dimension of length 1 at the dimension index axis of input's shape as +// defined in https://www.tensorflow.org/api_docs/python/tf/expand_dims. +TfLiteStatus VerifyTensorDim(TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* axis_tensor, + const TfLiteTensor* output) { + int32_t axis_value = 0; + TF_LITE_ENSURE_OK(context, + GetAxisValueFromTensor(context, axis_tensor, &axis_value)); + + tflite::RuntimeShape input_shape = tflite::GetTensorShape(input); + if (axis_value < 0) { + axis_value = input_shape.DimensionsCount() + 1 + axis_value; + } + TF_LITE_ENSURE(context, axis_value <= input_shape.DimensionsCount()); + + // TFLM only supports fixed dimension tensor and assumes that the output shape + // is fully specified in the model. As such, TFLM directly use the pointer to + // the dimension array in the model buffer. + tflite::RuntimeShape output_shape = tflite::GetTensorShape(output); + + TF_LITE_ENSURE(context, output_shape.DimensionsCount() == + input_shape.DimensionsCount() + 1); + for (int i = 0; i < output_shape.DimensionsCount(); ++i) { + if (i < axis_value) { + TF_LITE_ENSURE(context, output_shape.Dims(i) == input_shape.Dims(i)); + } else if (i == axis_value) { + TF_LITE_ENSURE(context, output_shape.Dims(i) == 1); + } else { + TF_LITE_ENSURE(context, output_shape.Dims(i) == input_shape.Dims(i - 1)); + } + } + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* axis = + micro_context->AllocateTempInputTensor(node, kAxisTensor); + TF_LITE_ENSURE(context, axis != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + output->type = input->type; + if (IsDynamicTensor(axis)) { + MicroPrintf("DynamicTensor is not yet supported by Expand_Dims."); + return kTfLiteError; + } + TF_LITE_ENSURE_OK(context, VerifyTensorDim(context, input, axis, output)); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(axis); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +template +void memCopyN(T* out, const T* in, const int num_elements) { + for (int i = 0; i < num_elements; ++i) { + out[i] = in[i]; + } +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + const int flat_size = ElementCount(*input->dims); + + switch (input->type) { + case kTfLiteFloat32: { + memCopyN(tflite::micro::GetTensorData(output), + tflite::micro::GetTensorData(input), flat_size); + } break; + case kTfLiteInt8: { + memCopyN(tflite::micro::GetTensorData(output), + tflite::micro::GetTensorData(input), flat_size); + } break; + default: + MicroPrintf( + "Expand_Dims only currently supports int8 and float32, got %d.", + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration Register_EXPAND_DIMS() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fill.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fill.cpp new file mode 100644 index 0000000..202caef --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fill.cpp @@ -0,0 +1,140 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fill.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +template +TfLiteStatus EnsureEqImpl(TfLiteContext* context, const TfLiteIntArray* array, + const TfLiteTensor* tensor) { + for (int i = 0; i < array->size; ++i) { + TF_LITE_ENSURE_EQ(context, array->data[i], GetTensorData(tensor)[i]); + } + return kTfLiteOk; +} + +// Ensure the equality of an int array and a tensor, which must be +// one-dimensional and of an integer type. +TfLiteStatus EnsureEq(TfLiteContext* context, const TfLiteIntArray* array, + const TfLiteTensor* tensor) { + TF_LITE_ENSURE_EQ(context, NumDimensions(tensor), 1); + const auto tensor_len = tensor->dims->data[0]; + TF_LITE_ENSURE_EQ(context, array->size, tensor_len); + + switch (tensor->type) { + case kTfLiteInt8: + return EnsureEqImpl(context, array, tensor); + case kTfLiteInt16: + return EnsureEqImpl(context, array, tensor); + case kTfLiteInt32: + return EnsureEqImpl(context, array, tensor); + case kTfLiteInt64: + return EnsureEqImpl(context, array, tensor); + default: + MicroPrintf("cannot compare int array to tensor of type %d.", + tensor->type); + return kTfLiteError; + } +} + +constexpr int kDimsTensor = 0; +constexpr int kValueTensor = 1; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + // Ensure inputs and outputs exist. + TfLiteTensor* dims = + micro_context->AllocateTempInputTensor(node, kDimsTensor); + TF_LITE_ENSURE(context, dims != nullptr); + TfLiteTensor* value = + micro_context->AllocateTempInputTensor(node, kValueTensor); + TF_LITE_ENSURE(context, value != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + // The value tensor must be a scalar. + TF_LITE_ENSURE_EQ(context, NumDimensions(value), 0); + + // The value type and output type must match. + TF_LITE_ENSURE_EQ(context, value->type, output->type); + + // The dimension of the output tensor is known in model already. + TFLITE_DCHECK(output->dims != nullptr); + + if (dims->data.data != nullptr) { + // When the dims tensor is specified in model already (i.e. is not an + // activation tensor), the dims tensor must match the output tensor shape. + // As a byproduct, ensures the dims tensor is of an integer type. + TF_LITE_ENSURE_OK(context, EnsureEq(context, output->dims, dims)); + } + + micro_context->DeallocateTempTfLiteTensor(dims); + micro_context->DeallocateTempTfLiteTensor(value); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +template +void FillImpl(const TfLiteEvalTensor* value, TfLiteEvalTensor* output) { + reference_ops::Fill( + micro::GetTensorShape(value), micro::GetTensorData(value), + micro::GetTensorShape(output), micro::GetTensorData(output)); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* value = + micro::GetEvalInput(context, node, kValueTensor); + TfLiteEvalTensor* output = micro::GetEvalOutput(context, node, kOutputTensor); + + switch (value->type) { + case kTfLiteFloat32: + FillImpl(value, output); + break; + case kTfLiteInt32: + FillImpl(value, output); + break; + case kTfLiteInt8: + FillImpl(value, output); + break; + default: + MicroPrintf("Fill only currently supports float32 for input 1, got %d.", + TfLiteTypeGetName(value->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_FILL() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor.cpp new file mode 100644 index 0000000..76c1a19 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor.cpp @@ -0,0 +1,48 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteFloat32); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + reference_ops::Floor(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_FLOOR() { + return tflite::micro::RegisterOp(nullptr, nullptr, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor_div.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor_div.cpp new file mode 100644 index 0000000..9fc135c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor_div.cpp @@ -0,0 +1,130 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_div.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +// Input/output tensor index. +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, input2->type); + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, output->type); + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + return nullptr; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +template +TfLiteStatus EvalFloorDiv(TfLiteContext* context, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + const T* denominator_data = tflite::micro::GetTensorData(input2); + + // Validate the denominator. + for (int i = 0; i < tflite::ElementCount(*input2->dims); ++i) { + if (std::equal_to()(denominator_data[i], 0)) { + MicroPrintf("Division by 0"); + return kTfLiteError; + } + } + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + + if (requires_broadcast) { + reference_ops::BroadcastBinaryFunction4DSlow( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), denominator_data, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), reference_ops::FloorDiv); + } else { + reference_ops::BinaryFunction( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), denominator_data, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), reference_ops::FloorDiv); + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + switch (input1->type) { + case kTfLiteFloat32: { + return EvalFloorDiv(context, input1, input2, output); + } + default: { + MicroPrintf("Type '%s' is not supported by FLOOR_DIV.", + TfLiteTypeGetName(input1->type)); + return kTfLiteError; + } + } +} + +} // namespace + +TfLiteRegistration Register_FLOOR_DIV() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor_mod.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor_mod.cpp new file mode 100644 index 0000000..acf4bbc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/floor_mod.cpp @@ -0,0 +1,128 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/floor_mod.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +// OLD-TODO(b/117523611): We should factor out a binary_op and put binary ops +// there. +namespace tflite { +namespace { + +// Input/output tensor index. +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +// OLD-TODO(b/117912880): Support quantization. + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, input2->type); + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, output->type); + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + return nullptr; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +template +TfLiteStatus EvalFloorMod(TfLiteContext* context, bool requires_broadcast, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + const T* denominator_data = tflite::micro::GetTensorData(input2); + + if (requires_broadcast) { + reference_ops::BroadcastBinaryFunction4DSlow( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), denominator_data, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), reference_ops::FloorMod); + } else { + reference_ops::BinaryFunction( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), denominator_data, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), reference_ops::FloorMod); + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + bool requires_broadcast = !tflite::micro::HaveSameShapes(input1, input2); + + switch (input1->type) { + case kTfLiteFloat32: { + return EvalFloorMod(context, requires_broadcast, input1, input2, + output); + } + default: { + MicroPrintf("Type '%s' is not supported by FLOOR_MOD.", + TfLiteTypeGetName(input1->type)); + return kTfLiteError; + } + } +} + +} // namespace + +TfLiteRegistration Register_FLOOR_MOD() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.cpp new file mode 100644 index 0000000..27ef622 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.cpp @@ -0,0 +1,1809 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +struct OpData { + OpDataFullyConnected reference_op_data; + + // Conv 1x1 that may be invoked in some cases currently need per channel + // quantization. + int32_t* per_channel_output_multiplier; + int32_t* per_channel_output_shift; + + // Index to buffer for optimizations if applicable. + int buffer_idx; + + int32_t batches; + int32_t accum_depth; + int32_t output_depth; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto params = + static_cast(node->builtin_data); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kFullyConnectedInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = micro_context->AllocateTempInputTensor( + node, kFullyConnectedWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kFullyConnectedBiasTensor); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor( + node, kFullyConnectedOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + const RuntimeShape filter_shape = GetTensorShape(filter); + const RuntimeShape output_shape = GetTensorShape(output); + const int filter_dim_count = filter_shape.DimensionsCount(); + const int output_dim_count = output_shape.DimensionsCount(); + cmsis_nn_dims filter_dims; + filter_dims.n = filter_shape.Dims(filter_dim_count - 1); + filter_dims.h = 1; + filter_dims.w = 1; + filter_dims.c = output_shape.Dims(output_dim_count - 1); + + data->accum_depth = filter_shape.Dims(filter_dim_count - 1); + data->batches = FlatSizeSkipDim(output_shape, output_dim_count - 1); + data->output_depth = output_shape.Dims(output_dim_count - 1); + + // Set buffer index to a reset value + data->buffer_idx = -1; + TF_LITE_ENSURE_STATUS(CalculateOpDataFullyConnected( + context, params->activation, input->type, input, filter, bias, output, + &(data->reference_op_data))); + + int32_t buf_size = 0; + + if (input->type == kTfLiteInt16) { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I16 + MicroPrintf("Filter data type %s currently not supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; +#endif + TF_LITE_ENSURE_EQ(context, input->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + buf_size = arm_fully_connected_s16_get_buffer_size(&filter_dims); + } else if (input->type == kTfLiteInt8) { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I8 + MicroPrintf("Filter data type %s currently not supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; +#endif + const RuntimeShape input_shape = GetTensorShape(input); + + TFLITE_DCHECK_GE(output_dim_count, 2); + TFLITE_DCHECK_LE(output_dim_count, 4); + +#if EI_TFLITE_DISABLE_CONV_2D_IN_I8 + buf_size = arm_fully_connected_s8_get_buffer_size(&filter_dims); +#else + if (output_dim_count > 2 && data->accum_depth % 4 == 0) { + data->per_channel_output_multiplier = + static_cast(context->AllocatePersistentBuffer( + context, data->output_depth * sizeof(int32_t))); + data->per_channel_output_shift = + static_cast(context->AllocatePersistentBuffer( + context, data->output_depth * sizeof(int32_t))); + + cmsis_nn_dims input_dims; + input_dims.n = data->batches; + input_dims.h = 1; + input_dims.w = 1; + input_dims.c = data->accum_depth; + + buf_size = arm_convolve_1x1_s8_fast_get_buffer_size(&input_dims); + } else { + buf_size = arm_fully_connected_s8_get_buffer_size(&filter_dims); + } +#endif + } + + if (filter->type == kTfLiteInt4) { + int filter_size = + RuntimeShape(filter->dims->size, + reinterpret_cast(filter->dims->data)) + .FlatSize(); + context->RequestScratchBufferInArena( + context, filter_size, &data->reference_op_data.filter_buffer_index); + } + + if (buf_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, buf_size, &data->buffer_idx)); + } + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + if (bias != nullptr) { + micro_context->DeallocateTempTfLiteTensor(bias); + } + + return kTfLiteOk; +} + +void PopulateCommonParams(TfLiteContext* context, + cmsis_nn_per_tensor_quant_params* const quant_params, + cmsis_nn_dims* const input_dims, + cmsis_nn_dims* const filter_dims, + cmsis_nn_dims* const bias_dims, + cmsis_nn_dims* const output_dims, + cmsis_nn_context* const ctx, const OpData& data) { + quant_params->multiplier = data.reference_op_data.output_multiplier; + quant_params->shift = data.reference_op_data.output_shift; + + input_dims->n = data.batches; + input_dims->h = 1; + input_dims->w = 1; + input_dims->c = data.accum_depth; + + filter_dims->n = data.accum_depth; + filter_dims->h = 1; + filter_dims->w = 1; + filter_dims->c = data.output_depth; + + bias_dims->n = 1; + bias_dims->h = 1; + bias_dims->w = 1; + bias_dims->c = data.output_depth; + + output_dims->n = data.batches; + output_dims->h = 1; + output_dims->w = 1; + output_dims->c = data.output_depth; + + ctx->buf = nullptr; + ctx->size = 0; + if (data.buffer_idx > -1) { + ctx->buf = context->GetScratchBuffer(context, data.buffer_idx); + } +} + +TfLiteStatus EvalQuantizedInt8(TfLiteContext* context, TfLiteNode* node, + const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + const RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + const int output_dim_count = output_shape.DimensionsCount(); + TFLITE_DCHECK_GE(output_dim_count, 2); + TFLITE_DCHECK_LE(output_dim_count, 4); + + cmsis_nn_per_tensor_quant_params quant_params; + cmsis_nn_dims input_dims; + cmsis_nn_dims filter_dims; + cmsis_nn_dims bias_dims; + cmsis_nn_dims output_dims; + cmsis_nn_context ctx; + + PopulateCommonParams(context, &quant_params, &input_dims, &filter_dims, + &bias_dims, &output_dims, &ctx, data); + + const int32_t* bias_data = + tflite::micro::GetOptionalTensorData(bias); + +#if EI_TFLITE_DISABLE_CONV_2D_IN_I8 + cmsis_nn_fc_params fc_params; + fc_params.input_offset = -data.reference_op_data.input_zero_point; + fc_params.output_offset = data.reference_op_data.output_zero_point; + fc_params.filter_offset = 0; + fc_params.activation.min = data.reference_op_data.output_activation_min; + fc_params.activation.max = data.reference_op_data.output_activation_max; + + TF_LITE_ENSURE_EQ( + context, + arm_fully_connected_s8( + &ctx, &fc_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, bias_data, + &output_dims, tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); +#else + + if (output_dim_count > 2 && data.accum_depth % 4 == 0) { + cmsis_nn_conv_params conv_params; + conv_params.dilation.h = 1; + conv_params.dilation.w = 1; + conv_params.input_offset = -data.reference_op_data.input_zero_point; + conv_params.output_offset = data.reference_op_data.output_zero_point; + conv_params.stride.h = 1; + conv_params.stride.w = 1; + conv_params.padding.h = 0; + conv_params.padding.w = 0; + conv_params.activation.min = data.reference_op_data.output_activation_min; + conv_params.activation.max = data.reference_op_data.output_activation_max; + + cmsis_nn_per_channel_quant_params per_channel_quant_params; + per_channel_quant_params.multiplier = + const_cast(data.per_channel_output_multiplier); + per_channel_quant_params.shift = + const_cast(data.per_channel_output_shift); + + for (int i = 0; i < data.output_depth; i++) { + per_channel_quant_params.multiplier[i] = quant_params.multiplier; + per_channel_quant_params.shift[i] = quant_params.shift; + } + + TF_LITE_ENSURE_EQ( + context, + arm_convolve_1x1_s8_fast( + &ctx, &conv_params, &per_channel_quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, bias_data, + &output_dims, tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + } else { + cmsis_nn_fc_params fc_params; + fc_params.input_offset = -data.reference_op_data.input_zero_point; + fc_params.output_offset = data.reference_op_data.output_zero_point; + fc_params.filter_offset = 0; + fc_params.activation.min = data.reference_op_data.output_activation_min; + fc_params.activation.max = data.reference_op_data.output_activation_max; + + TF_LITE_ENSURE_EQ( + context, + arm_fully_connected_s8( + &ctx, &fc_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, bias_data, + &output_dims, tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + } +#endif + + return kTfLiteOk; +} + +TfLiteStatus EvalQuantizedInt16(TfLiteContext* context, TfLiteNode* node, + const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + cmsis_nn_per_tensor_quant_params quant_params; + cmsis_nn_dims input_dims; + cmsis_nn_dims filter_dims; + cmsis_nn_dims bias_dims; + cmsis_nn_dims output_dims; + cmsis_nn_context ctx; + + PopulateCommonParams(context, &quant_params, &input_dims, &filter_dims, + &bias_dims, &output_dims, &ctx, data); + + const int64_t* bias_data = + tflite::micro::GetOptionalTensorData(bias); + + cmsis_nn_fc_params fc_params; + fc_params.input_offset = -data.reference_op_data.input_zero_point; + fc_params.output_offset = data.reference_op_data.output_zero_point; + fc_params.filter_offset = 0; + fc_params.activation.min = data.reference_op_data.output_activation_min; + fc_params.activation.max = data.reference_op_data.output_activation_max; + + TF_LITE_ENSURE_EQ( + context, + arm_fully_connected_s16( + &ctx, &fc_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, bias_data, + &output_dims, tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto* params = + static_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kFullyConnectedInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFullyConnectedWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kFullyConnectedBiasTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kFullyConnectedOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + TfLiteEvalTensor filter_int8 = tflite::micro::MakeUnpackedInt4Tensor( + context, data.reference_op_data.filter_buffer_index, filter); + + // Checks in Prepare ensure input, output and filter types are all the same. + switch (input->type) { + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_F32 + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + const float* bias_data = + tflite::micro::GetOptionalTensorData(bias); + tflite::reference_ops::FullyConnected( + FullyConnectedParamsFloat(params->activation), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), bias_data, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + case kTfLiteInt8: { + switch (filter_int8.type) { + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I8 + MicroPrintf("Filter data type %s currently not supported.", + TfLiteTypeGetName(filter->type)); + return kTfLiteError; +#endif + return EvalQuantizedInt8(context, node, data, input, &filter_int8, + bias, output); + default: + MicroPrintf("Filter Type %s (%d) not supported.", + TfLiteTypeGetName(filter->type), filter->type); + return kTfLiteError; + } + break; + } + case kTfLiteInt16: { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I16 + MicroPrintf("Filter data type %s currently not supported.", + TfLiteTypeGetName(filter->type)); + return kTfLiteError; +#endif + return EvalQuantizedInt16(context, node, data, input, filter, bias, + output); + } + default: { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + } + return kTfLiteOk; +} + +// Note that the current function names are not ideal at all (this EvalInt8 +// function internally calls EvalQuantizedInt8, and there is similar name +// aliasing in the Eval function too). We will be attempting to have a more +// descriptive naming convention but holding off on that for now, since the +// renaming might be coupled with reducing code duplication and some additional +// refactoring. +TfLiteStatus EvalInt8(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kFullyConnectedInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFullyConnectedWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kFullyConnectedBiasTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kFullyConnectedOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + // Checks in Prepare ensure input, output and filter types are all the same. + if (input->type != kTfLiteInt8) { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + + TfLiteEvalTensor filter_int8 = tflite::micro::MakeUnpackedInt4Tensor( + context, data.reference_op_data.filter_buffer_index, filter); + + return EvalQuantizedInt8(context, node, data, input, &filter_int8, bias, + output); +} + +TfLiteStatus EvalInt16(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kFullyConnectedInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFullyConnectedWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kFullyConnectedBiasTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kFullyConnectedOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + // Checks in Prepare ensure input, output and filter types are all the same. + if (input->type != kTfLiteInt16) { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + + return EvalQuantizedInt16(context, node, data, input, filter, bias, output); +} + +} // namespace + +TfLiteRegistration Register_FULLY_CONNECTED() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +TfLiteRegistration Register_FULLY_CONNECTED_INT8() { + return tflite::micro::RegisterOp(Init, Prepare, EvalInt8); +} + +TfLiteRegistration Register_FULLY_CONNECTED_INT16() { + return tflite::micro::RegisterOp(Init, Prepare, EvalInt16); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" + +#include "mli_api.h" // NOLINT +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +struct OpData { + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t output_multiplier; + int output_shift; + // The range of the fused activation layer. For example for kNone and + // uint8_t these would be 0 and 255. + int32_t output_activation_min; + int32_t output_activation_max; + // The index of the temporary tensor where the quantized inputs are cached. + int input_quantized_index; + // Cached tensor zero point values for quantized operations. + int32_t input_zero_point; + int32_t filter_zero_point; + int32_t output_zero_point; + + // The result of checking if MLI optimized version of tensors can be used. + bool is_mli_applicable; + + // Tensors in MLI format. + mutable ops::micro::MliTensorInterface mli_in; + mutable ops::micro::MliTensorInterface mli_weights; + mutable ops::micro::MliTensorInterface mli_bias; + mutable ops::micro::MliTensorInterface mli_out; + +#ifdef MLI_2_0 + mli_fully_connected_cfg* cfg; +#endif +}; + +constexpr int kInputTensor = 0; +constexpr int kWeightsTensor = 1; +constexpr int kBiasTensor = 2; +constexpr int kOutputTensor = 0; + +bool IsMliApplicable(TfLiteContext* context, const TfLiteTensor* input, + const TfLiteTensor* filter, const TfLiteTensor* bias, + const TfLiteFullyConnectedParams* params, + int32_t output_activation_min, + int32_t output_activation_max) { + // MLI optimized version only supports int8_t datatype and no fused Relu and + // symmetric per-tensor quantization of weights (not per-axis) + bool ret_val = + (filter->type == kTfLiteInt8) && (input->type == kTfLiteInt8) && + (bias->type == kTfLiteInt32) && +#ifndef MLI_2_0 + (params->activation == kTfLiteActNone || + (output_activation_min == -128 && output_activation_max == 127)) && +#endif + (filter->params.zero_point == 0); + return ret_val; +} + +TfLiteStatus CalculateOpData(TfLiteContext* context, + const TfLiteFullyConnectedParams* params, + TfLiteType data_type, const TfLiteTensor* input, + const TfLiteTensor* filter, + const TfLiteTensor* bias, TfLiteTensor* output, + OpData* data) { + TfLiteStatus status = kTfLiteOk; +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + if (data_type != kTfLiteFloat32 && !data->is_mli_applicable) { + double real_multiplier = 0.0; + TF_LITE_ENSURE_STATUS(GetQuantizedConvolutionMultipler( + context, input, filter, bias, output, &real_multiplier)); + int exponent; + QuantizeMultiplier(real_multiplier, &data->output_multiplier, &exponent); + data->output_shift = -exponent; + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + } +#endif + return status; +} + +} // namespace + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto params = + static_cast(node->builtin_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kWeightsTensor); + TfLiteTensor* bias = micro_context->AllocateTempInputTensor(node, kBiasTensor); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + TF_LITE_ENSURE_MSG(context, input->type == filter->type, + "Hybrid models are not supported on TFLite Micro."); + + data->input_zero_point = input->params.zero_point; + data->filter_zero_point = filter->params.zero_point; + data->output_zero_point = output->params.zero_point; + + TfLiteStatus status = CalculateOpData(context, params, input->type, input, + filter, bias, output, data); + + data->is_mli_applicable = + IsMliApplicable(context, input, filter, bias, params, + data->output_activation_min, data->output_activation_max); + + if (input->type == kTfLiteInt8 && data->is_mli_applicable) { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; +#endif + data->mli_in = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_weights = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_bias = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_out = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + + ops::micro::ConvertToMliTensor(input, &data->mli_in); + ops::micro::ConvertToMliTensor(filter, &data->mli_weights); + ops::micro::ConvertToMliTensor(bias, &data->mli_bias); +#ifdef MLI_2_0 + ops::micro::AdjustBiasTensor(&data->mli_bias, &data->mli_in, + &data->mli_weights); +#endif + ops::micro::ConvertToMliTensor(output, &data->mli_out); + +#ifdef MLI_2_0 + if (data->output_activation_min == -128 && + data->output_activation_max == 127) { + data->cfg->relu.type = MLI_RELU_NONE; + } else if (params->activation == kTfLiteActRelu) { + data->cfg->relu.type = MLI_RELU_GEN; + } else if (params->activation == kTfLiteActRelu6) { + data->cfg->relu.type = MLI_RELU_6; + } else if (params->activation == kTfLiteActReluN1To1) { + data->cfg->relu.type = MLI_RELU_1; + } else { + data->cfg->relu.type = MLI_RELU_NONE; + } +#endif + + /* The input tensor can have more than 2 dimensions. for the compute this + doesn't make any difference because all the inputs or a batch entry will + be used anyway. because the MLI kernel doesn't recognize the multiple + dimensions, the tensor shape is casted to a {batchnum, inputsize} shape. */ + data->mli_in.Shape()[0] = data->mli_out.Shape()[0]; +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + data->mli_in.Shape()[1] = data->mli_weights.Shape()[0]; +#else + data->mli_in.Shape()[1] = data->mli_weights.Shape()[1]; +#endif + data->mli_in.Shape()[2] = 0; + data->mli_in.Shape()[3] = 0; + data->mli_in.MemStride()[0] = data->mli_in.Shape()[1]; + data->mli_in.MemStride()[1] = 0; + *data->mli_in.Rank() = 2; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(bias); + micro_context->DeallocateTempTfLiteTensor(output); + return status; +} + +TfLiteStatus EvalMliQuantizedInt8(TfLiteContext* context, TfLiteNode* node, + const TfLiteFullyConnectedParams* params, + const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + ops::micro::MliTensorAttachBuffer(input, &data.mli_in); + ops::micro::MliTensorAttachBuffer(filter, &data.mli_weights); + ops::micro::MliTensorAttachBuffer(bias, &data.mli_bias); + ops::micro::MliTensorAttachBuffer(output, &data.mli_out); + + // Tensors for data in fast (local) memory and config to copy data from + // external to local memory + mli_tensor weights_local = *data.mli_weights.MliTensor(); + mli_tensor bias_local = *data.mli_bias.MliTensor(); + mli_tensor in_local = *data.mli_in.MliTensor(); + mli_tensor out_local = *data.mli_out.MliTensor(); + + ops::micro::MliTensorInterface weights_local_interface(&weights_local); + ops::micro::MliTensorInterface bias_local_interface(&bias_local); + ops::micro::MliTensorInterface in_local_interface(&in_local); + ops::micro::MliTensorInterface out_local_interface(&out_local); + + mli_mov_cfg_t copy_config; + mli_mov_cfg_for_copy(©_config); +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + const int weight_out_dimension = 1; +#else + const int weight_out_dimension = 0; +#endif + // bias has only 1 dimension + const int bias_out_ch_dimension = 0; + const int out_tensor_dimension = 1; + const int input_size_dimension = 1; + int slice_size = data.mli_weights.Shape()[weight_out_dimension]; + + /* allocate the local buffers, and compute the slice size */ + TF_LITE_ENSURE_STATUS( + ops::micro::get_arc_scratch_buffer_for_fully_connect_tensors( + context, &in_local_interface, &weights_local_interface, + &bias_local_interface, &out_local_interface)); + TF_LITE_ENSURE_STATUS(ops::micro::arc_scratch_buffer_calc_slice_size_weights( + &weights_local_interface, &bias_local_interface, weight_out_dimension, + &slice_size)); + + int max_out_slice_size = *out_local_interface.DataCapacity() / + mli_hlp_tensor_element_size(&out_local); + + if (slice_size > max_out_slice_size) slice_size = max_out_slice_size; + + /* is_local indicates that the tensor is already in local memory, + so in that case the original tensor can be used, + and there is no need to copy it to the local tensor*/ + const bool in_is_local = + in_local_interface.Data() == data.mli_in.Data(); + const bool out_is_local = + out_local_interface.Data() == data.mli_out.Data(); + const bool b_is_local = + bias_local_interface.Data() == data.mli_bias.Data(); +#ifndef MLI_2_0_KRNL_TEST + const bool w_is_local = + weights_local_interface.Data() == data.mli_weights.Data(); +#endif + +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + ops::micro::TensorSlicer w_slice(data.mli_weights.MliTensor(), + weight_out_dimension, slice_size, 0, 0, 0, + true); +#else + ops::micro::TensorSlicer w_slice(data.mli_weights.MliTensor(), + weight_out_dimension, slice_size); +#endif + ops::micro::TensorSlicer b_slice(data.mli_bias.MliTensor(), + bias_out_ch_dimension, slice_size); + ops::micro::TensorSlicer out_ch_slice(data.mli_out.MliTensor(), + out_tensor_dimension, slice_size, 0, 0, + 0, true); + +#ifdef MLI_2_0_KRNL_TEST + mli_tensor* w_ptr = &weights_local; +#else + mli_tensor* w_ptr = w_is_local ? w_slice.Sub() : &weights_local; +#endif + mli_tensor* b_ptr = b_is_local ? b_slice.Sub() : &bias_local; + + void* input_buffer_ptr = NULL; + + while (!w_slice.Done()) { +#if defined(MLI_2_0) && !defined(MLI_2_0_KRNL_TEST) + w_ptr->el_params.sa.scale.mem.pi16 = NULL; + b_ptr->el_params.sa.scale.mem.pi16 = NULL; +#endif + +#ifndef MLI_2_0_KRNL_TEST + mli_mov_tensor_sync(w_slice.Sub(), ©_config, w_ptr); +#endif + mli_mov_tensor_sync(b_slice.Sub(), ©_config, b_ptr); + + // Slice the input over the batches (one at a time with the size of a + // complete input) + ops::micro::TensorSlicer in_slice( + data.mli_in.MliTensor(), input_size_dimension, + data.mli_in.Shape()[input_size_dimension]); + + /* output tensor is already sliced in the output size dimension. + out_ch_slice.Sub() is the tensor for the amount of output size of this + iteration of the weight slice loop. This tensor needs to be further + sliced over the batch */ + ops::micro::TensorSlicer out_slice(out_ch_slice.Sub(), out_tensor_dimension, + slice_size); + + /* setup the pointers to the local or remote tensor to make the code + * inside the loop easier. */ + mli_tensor* in_ptr = in_is_local ? in_slice.Sub() : &in_local; + mli_tensor* out_ptr = out_is_local ? out_slice.Sub() : &out_local; + +#ifdef MLI_2_0_KRNL_TEST + /* Permute weights tensor to the HWCN layout */ + // Assertion here to prevent usage non-contiguous buffer memory. + if (data.mli_out.Shape()[out_tensor_dimension] != + out_slice.Sub()->shape[0]) { + MicroPrintf("Slicing is not supported with real-time permutation."); + return kTfLiteError; + } + mli_permute_cfg permute_cfg = {{1, 0, 2, 3}}; + ops::micro::permute_weights(data.mli_weights.MliTensor(), &permute_cfg, + w_ptr, &out_ptr->data); +#endif + + while (!out_slice.Done()) { + if (!out_is_local) { + ops::micro::PrepareLocalTensor(out_slice.Sub(), &out_local); + ops::micro::PrepareLocalTensor(in_slice.Sub(), &in_local); + } + // if same input copy as previous iteration, skip the copy of input +#ifdef MLI_2_0 + if (in_slice.Sub()->data.mem.pi8 != input_buffer_ptr) { + mli_mov_tensor_sync(in_slice.Sub(), ©_config, in_ptr); + input_buffer_ptr = in_slice.Sub()->data.mem.pi8; + } + mli_fully_connected_cfg cfg; + cfg.relu.type = MLI_RELU_NONE; + mli_krn_fully_connected_sa8_sa8_sa32(in_ptr, w_ptr, b_ptr, &cfg, out_ptr); +#else + if (in_slice.Sub()->data != input_buffer_ptr) { + mli_mov_tensor_sync(in_slice.Sub(), ©_config, in_ptr); + input_buffer_ptr = in_slice.Sub()->data; + } + mli_krn_fully_connected_sa8_sa8_sa32(in_ptr, w_ptr, b_ptr, out_ptr); +#endif + + mli_mov_tensor_sync(out_ptr, ©_config, out_slice.Sub()); + + in_slice.Next(); + out_slice.Next(); + } + w_slice.Next(); + b_slice.Next(); + out_ch_slice.Next(); + } + return kTfLiteOk; +} + +TfLiteStatus EvalQuantized(TfLiteContext* context, TfLiteNode* node, + const OpData& data, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + tflite::FullyConnectedParams op_params; + op_params.input_offset = -data.input_zero_point; + op_params.weights_offset = -data.filter_zero_point; + op_params.output_offset = data.output_zero_point; + op_params.output_multiplier = data.output_multiplier; + op_params.output_shift = -data.output_shift; + op_params.quantized_activation_min = data.output_activation_min; + op_params.quantized_activation_max = data.output_activation_max; + +#define TF_LITE_FULLY_CONNECTED(output_data_type) \ + reference_ops::FullyConnected( \ + op_params, tflite::micro::GetTensorShape(input), \ + tflite::micro::GetTensorData(input), \ + tflite::micro::GetTensorShape(filter), \ + tflite::micro::GetTensorData(filter), \ + tflite::micro::GetTensorShape(bias), \ + tflite::micro::GetTensorData(bias), \ + tflite::micro::GetTensorShape(output), \ + tflite::micro::GetTensorData(output)) + + switch (output->type) { + case kTfLiteUInt8: + #if EI_TFLITE_DISABLE_FULLY_CONNECTED_OUT_U8 + MicroPrintf("Type %s currently not supported.", + TfLiteTypeGetName(filter->type)); + return kTfLiteError; + #endif + + TF_LITE_FULLY_CONNECTED(uint8_t); + break; + case kTfLiteInt16: + #if EI_TFLITE_DISABLE_FULLY_CONNECTED_OUT_I16 + MicroPrintf("Type %s currently not supported.", + TfLiteTypeGetName(filter->type)); + return kTfLiteError; + #endif + + TF_LITE_FULLY_CONNECTED(int16_t); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + + return kTfLiteOk; +#else + MicroPrintf("Node configuration is not supported by ARC MLI Library."); + return kTfLiteError; +#endif + } +} + +TfLiteStatus EvalFloat(TfLiteContext* context, TfLiteNode* node, + TfLiteFusedActivation activation, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + float output_activation_min, output_activation_max; + CalculateActivationRange(activation, &output_activation_min, + &output_activation_max); + tflite::FullyConnectedParams op_params; + op_params.float_activation_min = output_activation_min; + op_params.float_activation_max = output_activation_max; + tflite::reference_ops::FullyConnected( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; +#else + MicroPrintf("Type %s (%d) is not supported by ARC MLI Library.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto* params = + static_cast(node->builtin_data); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kBiasTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + // Checks in Prepare ensure input, output and filter types are all the same. + switch (input->type) { + case kTfLiteFloat32: + #if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_F32 + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + return EvalFloat(context, node, params->activation, input, filter, bias, + output); + case kTfLiteInt8: + #if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I8 + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + if (data.is_mli_applicable) { + return EvalMliQuantizedInt8(context, node, params, data, input, filter, + bias, output); + } else { + return EvalQuantized(context, node, data, input, filter, bias, output); + } + + case kTfLiteUInt8: + #if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_U8 + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + return EvalQuantized(context, node, data, input, filter, bias, output); + + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteRegistration Register_FULLY_CONNECTED() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP == 1 +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "sl_mvp_ml_fully_connected.h" + +namespace tflite { +namespace sl { +namespace fully_connected { + +struct OpData { + int32_t output_multiplier; + int output_shift; + sli_mvp_ml_fully_connected_s8_params_t op_params; + float16_t *bias_fp16; + bool use_mvp; +}; + +constexpr int kInputTensor = 0; +constexpr int kWeightsTensor = 1; +constexpr int kBiasTensor = 2; +constexpr int kOutputTensor = 0; + +// TODO(b/169801227): This global struct is needed for the linker to drop unused +// code (for example, by using Register_FULLY_CONNECTED_INT8 instead of +// Register_FULLY_CONNECTED). +TfLiteRegistration fully_connected_registration; + +sli_shape_t dims2shape(const TfLiteIntArray *dim) +{ + TFLITE_DCHECK(dim->size <= 4); + + sli_shape_t shape = {0}; + for (int i = 0; i < dim->size; i++) { + shape.dim[i] = dim->data[i]; + } + return shape; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + TfLiteFullyConnectedParams* params = + reinterpret_cast(node->builtin_data); + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + const TfLiteTensor* weight = GetInput(context, node, kWeightsTensor); + const TfLiteTensor* bias = GetInput(context, node, kBiasTensor); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + int32_t output_min; + int32_t output_max; + float16_t *bias_data = nullptr; + int bias_len = 0; + + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + + if (!(input->type == kTfLiteFloat32 || input->type == kTfLiteInt8)) { + // Unsupported datatype used by model + return kTfLiteError; + } + + if (bias) { + RuntimeShape bias_shape = GetTensorShape(bias); + bias_len = bias_shape.FlatSize(); + } + + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &output_min, &output_max)); + + double real_multiplier = 0.0; + TF_LITE_ENSURE_STATUS(GetQuantizedConvolutionMultipler( + context, input, weight, bias, output, &real_multiplier)); + + data->op_params.input = GetTensorData(input); + data->op_params.input_shape = dims2shape(input->dims); + data->op_params.input_offset = -input->params.zero_point; + data->op_params.weight = GetTensorData(weight); + data->op_params.weight_shape = dims2shape(weight->dims); + data->op_params.weight_offset = -weight->params.zero_point; + data->op_params.bias = nullptr; + data->op_params.bias_length = bias_len; + data->op_params.output = GetTensorData(output); + data->op_params.output_shape = dims2shape(output->dims); + data->op_params.output_offset = output->params.zero_point; + data->op_params.output_multiplier = sli_mvp_ml_fully_connected_output_multiplier(real_multiplier); + data->op_params.activation_min = static_cast(output_min); + data->op_params.activation_max = static_cast(output_max); + + data->use_mvp = sli_mvp_ml_fully_connected_s8_is_supported(&data->op_params); + + if (data->use_mvp && bias) { + // Convert int32_t to float16_t as the MVP does not support loading int32 values. + const int32_t *bias_src = GetTensorData(bias); + bias_data = static_cast(context->AllocatePersistentBuffer(context, bias_len * sizeof(float16_t))); + if (bias_data == nullptr) { + return kTfLiteError; + } + sl_status_t status = sli_mvp_ml_fully_connected_bias_convert(bias_src, bias_data, bias_len); + if (status != SL_STATUS_OK) { + return kTfLiteError; + } + data->op_params.bias = bias_data; + } + + if (!data->use_mvp) { + // In this case we have to convert the output scale factor to a + // value in the TensorFlow fixed point format (Q.31 + shift) + int exponent; + QuantizeMultiplier(real_multiplier, &data->output_multiplier, &exponent); + data->output_shift = -exponent; + } + } + + return kTfLiteOk; +} + +TfLiteStatus EvalQuantizedInt8_MVP(TfLiteContext* context, TfLiteNode* node, + const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + sli_mvp_ml_fully_connected_s8_params_t *params = const_cast(&data.op_params); + params->input = tflite::micro::GetTensorData(input); + params->output = tflite::micro::GetTensorData(output); + + sl_status_t result = sli_mvp_ml_fully_connected_s8(params); + if (result == SL_STATUS_OK) { + return kTfLiteOk; + } else { + return kTfLiteError; + } +} + +TfLiteStatus EvalQuantizedInt8(TfLiteContext* context, TfLiteNode* node, + const OpData& data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) { + if (data.use_mvp && input->type == kTfLiteInt8) { + return EvalQuantizedInt8_MVP(context, node, data, input, filter, bias, output); + } + + // The 'if' condition can be removed when null handling of bias is added to + // arm_fully_connected_s8 + if (nullptr != tflite::micro::GetTensorData(bias)) { + const RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 2); + const int batches = output_shape.Dims(0); + const int output_depth = output_shape.Dims(1); + const RuntimeShape filter_shape = tflite::micro::GetTensorShape(filter); + const int filter_dim_count = filter_shape.DimensionsCount(); + const int accum_depth = filter_shape.Dims(filter_dim_count - 1); + const RuntimeShape input_shape = tflite::micro::GetTensorShape(input); + + cmsis_nn_fc_params fc_params; + fc_params.input_offset = data.op_params.input_offset; + fc_params.output_offset = data.op_params.output_offset; + fc_params.filter_offset = data.op_params.weight_offset; + fc_params.activation.min = data.op_params.activation_min; + fc_params.activation.max = data.op_params.activation_max; + + cmsis_nn_per_tensor_quant_params quant_params; + quant_params.multiplier = data.output_multiplier; + // TODO(b/138810107): Figure out whether output shift should be inverted + quant_params.shift = -data.output_shift; + + cmsis_nn_dims input_dims; + input_dims.n = batches; + input_dims.h = 1; + input_dims.w = 1; + input_dims.c = accum_depth; + + cmsis_nn_dims filter_dims; + filter_dims.n = accum_depth; + filter_dims.h = 1; + filter_dims.w = 1; + filter_dims.c = output_depth; + + cmsis_nn_dims bias_dims; + bias_dims.n = 1; + bias_dims.h = 1; + bias_dims.w = 1; + bias_dims.c = output_depth; + + cmsis_nn_dims output_dims; + output_dims.n = batches; + output_dims.h = 1; + output_dims.w = 1; + output_dims.c = output_depth; + + cmsis_nn_context ctx; + ctx.buf = nullptr; + ctx.size = 0; + + TF_LITE_ENSURE_EQ( + context, + arm_fully_connected_s8( + &ctx, &fc_params, &quant_params, &input_dims, + tflite::micro::GetTensorData(input), &filter_dims, + tflite::micro::GetTensorData(filter), &bias_dims, + tflite::micro::GetTensorData(bias), &output_dims, + tflite::micro::GetTensorData(output)), + ARM_MATH_SUCCESS); + } else { + tflite::FullyConnectedParams op_params; + op_params.input_offset = data.op_params.input_offset; + op_params.weights_offset = data.op_params.weight_offset; + op_params.output_offset = data.op_params.output_offset; + op_params.output_multiplier = data.output_multiplier; + // TODO(b/138810107): Figure out whether output shift should be inverted + op_params.output_shift = -data.output_shift; + op_params.quantized_activation_min = data.op_params.activation_min; + op_params.quantized_activation_max = data.op_params.activation_max; + + reference_integer_ops::FullyConnected( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + return kTfLiteOk; +} + +TfLiteStatus EvalFloat(TfLiteContext* context, TfLiteNode* node, + TfLiteFusedActivation activation, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, TfLiteEvalTensor* output) { + float output_activation_min, output_activation_max; + CalculateActivationRange(activation, &output_activation_min, + &output_activation_max); + tflite::FullyConnectedParams op_params; + op_params.float_activation_min = output_activation_min; + op_params.float_activation_max = output_activation_max; + tflite::reference_ops::FullyConnected( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto* params = + static_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kBiasTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + switch (input->type) { + case kTfLiteFloat32: + #if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + return EvalFloat(context, node, params->activation, input, filter, bias, + output); + case kTfLiteInt8: + #if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + return EvalQuantizedInt8(context, node, data, input, filter, bias, + output); + + default: + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +// Note that the current function names are not ideal at all (this EvalInt8 +// function internally calls EvalQuantizedInt8, and there is similar name +// aliasing in the Eval function too). We will be attempting to have a more +// descriptive naming convention but holding off on that for now, since the +// renaming might be coupled with reducing code duplication and some additional +// refactoring. +TfLiteStatus EvalInt8(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kBiasTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + // Checks in Prepare ensure input, output and filter types are all the same. + if (input->type != kTfLiteInt8) { + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + + return EvalQuantizedInt8(context, node, data, input, filter, bias, output); +} + +} // namespace fully_connected +} // namespace sl + +TfLiteRegistration Register_FULLY_CONNECTED() { + return {/*init*/sl::fully_connected::Init, + /*free*/nullptr, + /*prepare*/sl::fully_connected::Prepare, + /*invoke*/sl::fully_connected::Eval, + /*profiling_string*/nullptr, + /*builtin_code*/0, + /*custom_name*/nullptr, + /*version*/0}; +} + +TfLiteRegistration Register_FULLY_CONNECTED_INT8() { + return {/*init*/sl::fully_connected::Init, + /*free*/nullptr, + /*prepare*/sl::fully_connected::Prepare, + /*invoke*/sl::fully_connected::EvalInt8, + /*profiling_string*/nullptr, + /*builtin_code*/0, + /*custom_name*/nullptr, + /*version*/0}; +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN == 1 +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#if ESP_NN +#include "edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h" +#endif + +#include + +long long fc_total_time = 0; + +namespace tflite { +namespace { + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, + sizeof(OpDataFullyConnected)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* data = static_cast(node->user_data); + const auto params = + static_cast(node->builtin_data); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kFullyConnectedInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = micro_context->AllocateTempInputTensor( + node, kFullyConnectedWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kFullyConnectedBiasTensor); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor( + node, kFullyConnectedOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + TF_LITE_ENSURE_MSG(context, input->type == filter->type, + "Hybrid models are not supported on TFLite Micro."); + + TF_LITE_ENSURE_OK(context, CalculateOpDataFullyConnected( + context, params->activation, input->type, + input, filter, bias, output, data)); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + if (bias != nullptr) { + micro_context->DeallocateTempTfLiteTensor(bias); + } + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto* params = + static_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kFullyConnectedInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFullyConnectedWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kFullyConnectedBiasTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kFullyConnectedOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const auto& data = + *(static_cast(node->user_data)); + + long long start_time = esp_timer_get_time(); + // Checks in Prepare ensure input, output and filter types are all the same. + switch (input->type) { + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + tflite::reference_ops::FullyConnected( + FullyConnectedParamsFloat(params->activation), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + + case kTfLiteInt8: { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + const int32_t* bias_data = + nullptr != bias ? tflite::micro::GetTensorData(bias) + : nullptr; +#if ESP_NN + const RuntimeShape& filter_shape = tflite::micro::GetTensorShape(filter); + const RuntimeShape& output_shape = tflite::micro::GetTensorShape(output); + const int filter_dim_count = filter_shape.DimensionsCount(); + const int batches = output_shape.Dims(0); + const int output_depth = output_shape.Dims(1); + TFLITE_DCHECK_LE(output_depth, filter_shape.Dims(filter_dim_count - 2)); + const int accum_depth = filter_shape.Dims(filter_dim_count - 1); + + const int8_t *input_data = tflite::micro::GetTensorData(input); + int8_t *output_data = tflite::micro::GetTensorData(output); + const int8_t *filter_data = tflite::micro::GetTensorData(filter); + + for (int b = 0; b < batches; ++b) { + esp_nn_fully_connected_s8(input_data, -data.input_zero_point, + accum_depth, + filter_data, -data.filter_zero_point, + bias_data, output_data, output_depth, + data.output_zero_point, + data.output_shift, data.output_multiplier, + data.output_activation_min, + data.output_activation_max); + input_data += accum_depth; + output_data += output_depth; + } +#else + tflite::reference_integer_ops::FullyConnected( + FullyConnectedParamsQuantized(data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), bias_data, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#endif + break; + } + + case kTfLiteUInt8: { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_U8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + tflite::reference_ops::FullyConnected( + FullyConnectedParamsQuantized(data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + default: { + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + } + fc_total_time += esp_timer_get_time() - start_time; + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_FULLY_CONNECTED() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#else +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, + sizeof(OpDataFullyConnected)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* data = static_cast(node->user_data); + const auto params = + static_cast(node->builtin_data); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kFullyConnectedInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = micro_context->AllocateTempInputTensor( + node, kFullyConnectedWeightsTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kFullyConnectedBiasTensor); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor( + node, kFullyConnectedOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + if (filter->type == kTfLiteInt4) { + int filter_size = + RuntimeShape(filter->dims->size, + reinterpret_cast(filter->dims->data)) + .FlatSize(); + context->RequestScratchBufferInArena(context, filter_size, + &data->filter_buffer_index); + } + + TF_LITE_ENSURE_OK(context, CalculateOpDataFullyConnected( + context, params->activation, input->type, + input, filter, bias, output, data)); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + if (bias != nullptr) { + micro_context->DeallocateTempTfLiteTensor(bias); + } + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + const auto* params = + static_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kFullyConnectedInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFullyConnectedWeightsTensor); + const TfLiteEvalTensor* bias = + tflite::micro::GetEvalInput(context, node, kFullyConnectedBiasTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kFullyConnectedOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + + const auto& data = + *(static_cast(node->user_data)); + + // Checks in Prepare ensure input, output and filter types are all the same. + switch (input->type) { + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_F32 + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + tflite::reference_ops::FullyConnected( + FullyConnectedParamsFloat(params->activation), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + + case kTfLiteInt8: { +#if EI_TFLITE_DISABLE_FULLY_CONNECTED_IN_I8 + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + switch (filter->type) { + case kTfLiteInt4: { + int8_t* unpacked_filter_data = static_cast( + context->GetScratchBuffer(context, data.filter_buffer_index)); + tflite::tensor_utils::UnpackDenseInt4IntoInt8( + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(filter).FlatSize(), + unpacked_filter_data); + tflite::reference_integer_ops::FullyConnected( + FullyConnectedParamsQuantized(data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), unpacked_filter_data, + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + case kTfLiteInt8: { + tflite::reference_integer_ops::FullyConnected( + FullyConnectedParamsQuantized(data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + default: { + MicroPrintf("Filter type %s (%d) not supported.", + TfLiteTypeGetName(filter->type), input->type); + return kTfLiteError; + } + } + break; + } + + case kTfLiteInt16: { + switch (filter->type) { + case kTfLiteInt8: { + tflite::reference_integer_ops::FullyConnected( + FullyConnectedParamsQuantized(data), + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + } + default: { + MicroPrintf("Filter type %s (%d) not supported.", + TfLiteTypeGetName(filter->type), input->type); + return kTfLiteError; + } + } + break; + } + + default: { + MicroPrintf("Input type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_FULLY_CONNECTED() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h new file mode 100644 index 0000000..b245abe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h @@ -0,0 +1,112 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_FULLY_CONNECTED_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_FULLY_CONNECTED_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +struct OpDataFullyConnected { + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t output_multiplier; + int output_shift; + // The range of the fused activation layer. For example for kNone and + // uint8_t these would be 0 and 255. + int32_t output_activation_min; + int32_t output_activation_max; + // The index of the temporary tensor where the quantized inputs are cached. + int input_quantized_index; + // Cached zero point values of tensors. + int32_t input_zero_point; + int32_t filter_zero_point; + int32_t output_zero_point; + +// TODO(b/258710417): enable by default once optimized fully-connected works for +// all targets. +#if !defined(HEXAGON) + // A buffer used to store unpacked filter values. This is used if the source + // tensor is of n-bit precision that cannot be easily processed by kernels. + int filter_buffer_index; +#endif +}; + +extern const int kFullyConnectedInputTensor; +extern const int kFullyConnectedWeightsTensor; +extern const int kFullyConnectedBiasTensor; +extern const int kFullyConnectedOutputTensor; + +// Returns a FullyConnectedParams struct with all the parameters needed for a +// float computation. +FullyConnectedParams FullyConnectedParamsFloat( + TfLiteFusedActivation activation); + +// Returns a FullyConnectedParams struct with all the parameters needed for a +// quantized computation. +FullyConnectedParams FullyConnectedParamsQuantized( + const OpDataFullyConnected& op_data); + +TfLiteStatus CalculateOpDataFullyConnected( + TfLiteContext* context, TfLiteFusedActivation activation, + TfLiteType data_type, const TfLiteTensor* input, const TfLiteTensor* filter, + const TfLiteTensor* bias, TfLiteTensor* output, OpDataFullyConnected* data); + +// This is the most generic TfLiteRegistration. The actual supported types may +// still be target dependent. The only requirement is that every implementation +// (reference or optimized) must define this function. +TfLiteRegistration Register_FULLY_CONNECTED(); + +#if defined(CMSIS_NN) || defined(HEXAGON) || defined(EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP) +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int8. +TfLiteRegistration Register_FULLY_CONNECTED_INT8(); + +#else +// Note that while this block gets used for both reference and optimized kernels +// that do not have any specialized implementations, the only goal here is to +// define fallback implementation that allow reference kernels to still be used +// from applications that call a more specific kernel variant. + +inline TfLiteRegistration Register_FULLY_CONNECTED_INT8() { + return Register_FULLY_CONNECTED(); +} + +#endif + +#if defined(CMSIS_NN) +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int16. +TfLiteRegistration Register_FULLY_CONNECTED_INT16(); + +#else +// Note that while this block gets used for both reference and optimized kernels +// that do not have any specialized implementations, the only goal here is to +// define fallback implementation that allow reference kernels to still be used +// from applications that call a more specific kernel variant. + +inline TfLiteRegistration Register_FULLY_CONNECTED_INT16() { + return Register_FULLY_CONNECTED(); +} + +#endif + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_FULLY_CONNECTED_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected_common.cpp new file mode 100644 index 0000000..d38ea3e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected_common.cpp @@ -0,0 +1,83 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { + +const int kFullyConnectedInputTensor = 0; +const int kFullyConnectedWeightsTensor = 1; +const int kFullyConnectedBiasTensor = 2; +const int kFullyConnectedOutputTensor = 0; + +FullyConnectedParams FullyConnectedParamsQuantized( + const OpDataFullyConnected& op_data) { + FullyConnectedParams op_params; + op_params.input_offset = -op_data.input_zero_point; + op_params.weights_offset = -op_data.filter_zero_point; + op_params.output_offset = op_data.output_zero_point; + op_params.output_multiplier = op_data.output_multiplier; + op_params.output_shift = op_data.output_shift; + op_params.quantized_activation_min = op_data.output_activation_min; + op_params.quantized_activation_max = op_data.output_activation_max; + return op_params; +} + +FullyConnectedParams FullyConnectedParamsFloat( + TfLiteFusedActivation activation) { + FullyConnectedParams op_params; + CalculateActivationRange(activation, &op_params.float_activation_min, + &op_params.float_activation_max); + return op_params; +} + +TfLiteStatus CalculateOpDataFullyConnected( + TfLiteContext* context, TfLiteFusedActivation activation, + TfLiteType data_type, const TfLiteTensor* input, const TfLiteTensor* filter, + const TfLiteTensor* bias, TfLiteTensor* output, + OpDataFullyConnected* data) { + if (data_type != kTfLiteFloat32) { + double real_multiplier = 0.0; + TF_LITE_ENSURE_STATUS(GetQuantizedConvolutionMultipler( + context, input, filter, bias, output, &real_multiplier)); + QuantizeMultiplier(real_multiplier, &data->output_multiplier, + &data->output_shift); + + data->input_zero_point = input->params.zero_point; + // Filter weights will always be symmetric quantized since we only support + // int8 quantization. See + // https://github.com/tensorflow/tensorflow/issues/44912 for additional + // context. + TFLITE_DCHECK(filter->params.zero_point == 0); + data->filter_zero_point = filter->params.zero_point; + data->output_zero_point = output->params.zero_point; + + return CalculateActivationRangeQuantized(context, activation, output, + &data->output_activation_min, + &data->output_activation_max); + } + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/gather.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/gather.cpp new file mode 100644 index 0000000..4fb05d8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/gather.cpp @@ -0,0 +1,226 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TF_LITE_STATIC_MEMORY + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kInputPositions = 1; +constexpr int kOutputTensor = 0; + +template +TfLiteStatus Gather(const TfLiteGatherParams* params, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* coords, TfLiteEvalTensor* output) { + const InputT* input_data = tflite::micro::GetTensorData(input); + const CoordsT* coords_data = tflite::micro::GetTensorData(coords); + InputT* output_data = tflite::micro::GetTensorData(output); + const TfLiteIntArray* input_dims = input->dims; + const int input_dims_size = input_dims->size; + int axis = params->axis; + if (axis < 0) { + axis += input_dims_size; + } + TFLITE_DCHECK_GE(axis, 0); + TFLITE_DCHECK_LT(axis, input_dims_size); + + int batch_dims = params->batch_dims; + // batch_dims should be in range: [-rank(coords), rank(coords)]. + // Negative batch_dims is added with rank of coords. + const TfLiteIntArray* coords_dims = coords->dims; + const int coords_dims_size = coords_dims->size; + if (batch_dims < 0) { + batch_dims += coords_dims_size; + } + TFLITE_DCHECK_GE(batch_dims, 0); + TFLITE_DCHECK_LT(batch_dims, input_dims_size); + TFLITE_DCHECK_LE(batch_dims, coords_dims_size); + TFLITE_DCHECK_GE(axis, batch_dims); + for (int i = 0; i < batch_dims; ++i) { + TFLITE_DCHECK_EQ(input_dims->data[i], coords_dims->data[i]); + } + + const int axis_size = input_dims->data[axis]; + + int batch_size = 1; + for (int i = 0; i < batch_dims; ++i) { + batch_size *= input_dims->data[i]; + } + int outer_size = 1; + for (int i = batch_dims; i < axis; ++i) { + outer_size *= input_dims->data[i]; + } + int inner_size = 1; + for (int i = axis + 1; i < input_dims_size; ++i) { + inner_size *= input_dims->data[i]; + } + int coord_size = 1; + for (int i = batch_dims; i < coords_dims_size; ++i) { + coord_size *= coords_dims->data[i]; + } + + for (int batch = 0; batch < batch_size; ++batch) { + for (int outer = 0; outer < outer_size; ++outer) { + for (int coord = 0; coord < coord_size; ++coord) { + TFLITE_DCHECK_GE(coords_data[coord], 0); + TFLITE_DCHECK_LT(coords_data[coord], axis_size); + std::memcpy(output_data + + (((batch * outer_size) + outer) * coord_size + coord) * + inner_size, + input_data + (((batch * outer_size) + outer) * axis_size + + coords_data[batch * coord_size + coord]) * + inner_size, + sizeof(InputT) * inner_size); + } + } + } + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + const auto* params = + reinterpret_cast(node->builtin_data); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* coords = + micro_context->AllocateTempInputTensor(node, kInputPositions); + TF_LITE_ENSURE(context, coords != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + switch (coords->type) { + case kTfLiteInt32: + break; + default: + MicroPrintf("Positions of type '%s' are not supported by gather.", + TfLiteTypeGetName(coords->type)); + return kTfLiteError; + break; + } + + // Assign to output the input type. + output->type = input->type; + + // Check conditions for different types. + switch (input->type) { + case kTfLiteFloat32: + case kTfLiteInt8: + break; + default: + MicroPrintf("Type '%s' is not supported by gather.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + break; + } + + int axis = params->axis; + if (axis < 0) { + axis += NumDimensions(input); + } + TF_LITE_ENSURE(context, 0 <= axis && axis < NumDimensions(input)); + + int batch_dims = params->batch_dims; + // batch_dims should be in range: [-rank(coords), rank(coords)]. + // Negative batch_dims is added with rank of coords. + if (batch_dims < 0) { + batch_dims += NumDimensions(coords); + } + TF_LITE_ENSURE(context, batch_dims <= axis); + TF_LITE_ENSURE(context, 0 <= batch_dims && batch_dims < NumDimensions(input)); + TF_LITE_ENSURE(context, batch_dims <= NumDimensions(coords)); + for (int i = 0; i < batch_dims; ++i) { + TF_LITE_ENSURE_EQ(context, input->dims->data[i], coords->dims->data[i]); + } + + // GATHER updates the output tensor dimensions, but TfLiteTensor in the + // MicroInterpreter is a temporary allocation. We must therefore relocate the + // dims from the FlatBuffer to the persistant storage arena. + TfLiteEvalTensor* output_eval = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE_OK(context, tflite::micro::CreateWritableTensorDimsWithCopy( + context, output, output_eval)); + + TfLiteIntArray* output_shape = output->dims; + output_shape->size = + NumDimensions(input) + NumDimensions(coords) - 1 - batch_dims; + int output_index = 0; + for (int i = 0; i < axis; ++i) { + output_shape->data[output_index++] = input->dims->data[i]; + } + for (int i = batch_dims; i < coords->dims->size; ++i) { + output_shape->data[output_index++] = coords->dims->data[i]; + } + for (int i = axis + 1; i < input->dims->size; ++i) { + output_shape->data[output_index++] = input->dims->data[i]; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(coords); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const auto* params = + reinterpret_cast(node->builtin_data); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* coords = + tflite::micro::GetEvalInput(context, node, kInputPositions); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (coords->type == kTfLiteInt32) { + switch (input->type) { + case kTfLiteFloat32: + return Gather(params, input, coords, output); + break; + case kTfLiteInt8: + return Gather(params, input, coords, output); + break; + default: + MicroPrintf("Type '%s' is not supported by gather.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + break; + } + } + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration Register_GATHER() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite +#endif // TF_LITE_STATIC_MEMORY \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/gather_nd.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/gather_nd.cpp new file mode 100644 index 0000000..5e4b261 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/gather_nd.cpp @@ -0,0 +1,212 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +constexpr int kParams = 0; +constexpr int kIndices = 1; +constexpr int kOutputTensor = 0; +constexpr int MAX_INDICES_ND = 5; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* params = micro_context->AllocateTempInputTensor(node, kParams); + TF_LITE_ENSURE(context, params != nullptr); + TfLiteTensor* indices = + micro_context->AllocateTempInputTensor(node, kIndices); + TF_LITE_ENSURE(context, indices != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + switch (params->type) { + case kTfLiteFloat32: + case kTfLiteInt8: + break; + default: + MicroPrintf("Params of type '%s' are not supported by gather_nd.", + TfLiteTypeGetName(params->type)); + return kTfLiteError; + break; + } + switch (indices->type) { + case kTfLiteInt32: + break; + default: + MicroPrintf("Indices of type '%s' are not supported by gather_nd.", + TfLiteTypeGetName(indices->type)); + return kTfLiteError; + } + + const int params_rank = NumDimensions(params); + const int indices_rank = NumDimensions(indices); + const int indices_nd = SizeOfDimension(indices, indices_rank - 1); + if (params_rank < 1) { + MicroPrintf("Params must be at least a vector."); + return kTfLiteError; + } + if (indices_rank < 1) { + MicroPrintf("Indices must be at least a vector."); + return kTfLiteError; + } + if (indices_nd > params_rank) { + MicroPrintf("Index innermost dimension length must be <= params rank."); + return kTfLiteError; + } + if (indices_nd > MAX_INDICES_ND) { + MicroPrintf("Index innermost dimension length must not exceed %d.", + MAX_INDICES_ND); + return kTfLiteError; + } + + // Assign to output the input type. + output->type = params->type; + + // The tensor output dims must be relocated + // from the FlatBuffer to the persistant storage arena. + TfLiteEvalTensor* output_eval = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE_OK(context, tflite::micro::CreateWritableTensorDimsWithCopy( + context, output, output_eval)); + + // TFLM gather_nd does not create the output tensor, but it needs to ensure + // that the output shape is correct. The result shape is + // indices.shape[:-1] + params.shape[indices.shape[-1]:] + TfLiteIntArray* output_shape = output->dims; + int output_index = 0; + for (int i = 0; i < indices_rank - 1; ++i) { + output_shape->data[output_index++] = indices->dims->data[i]; + } + for (int i = indices_nd; i < params_rank; ++i) { + output_shape->data[output_index++] = params->dims->data[i]; + } + output_shape->size = output_index; + + micro_context->DeallocateTempTfLiteTensor(params); + micro_context->DeallocateTempTfLiteTensor(indices); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +template +TfLiteStatus GatherNd(const TfLiteEvalTensor* params, + const TfLiteEvalTensor* indices, + TfLiteEvalTensor* output) { + const int indices_dims = indices->dims->size; + const int indices_nd = indices->dims->data[indices_dims - 1]; + const int params_dims = params->dims->size; + const IndicesT* index_data = tflite::micro::GetTensorData(indices); + const ParamsT* param_data = tflite::micro::GetTensorData(params); + ParamsT* output_data = tflite::micro::GetTensorData(output); + + int n_slices = 1; + for (int i = 0; i < indices_dims - 1; ++i) { + n_slices *= indices->dims->data[i]; + } + + // If indices[-1] == params.rank, fetch single elements. + // If indices[-1] < params.rank, fetch slices. + int slice_size = 1; + for (int i = indices_nd; i < params_dims; ++i) { + slice_size *= params->dims->data[i]; + } + + int params_flat_size = ElementCount(*params->dims); + int remain_flat_size = params_flat_size; + + // Number of elements per dimension + int dims_to_count[MAX_INDICES_ND]; + for (int i = 0; i < indices_nd; ++i) { + dims_to_count[i] = remain_flat_size / params->dims->data[i]; + remain_flat_size = dims_to_count[i]; + } + + for (int i = 0; i < n_slices; ++i) { + int from_pos = 0; + for (int j = 0; j < indices_nd; ++j) { + int offset = i * indices_nd + j; + IndicesT index = index_data[offset]; + from_pos += index * dims_to_count[j]; + } + if (from_pos < 0 || from_pos + slice_size > params_flat_size) { + return kTfLiteError; + } + std::memcpy(output_data + i * slice_size, param_data + from_pos, + sizeof(ParamsT) * slice_size); + } + return kTfLiteOk; +} + +template +TfLiteStatus EvalGatherNd(TfLiteContext* context, + const TfLiteEvalTensor* params, + const TfLiteEvalTensor* indices, + TfLiteEvalTensor* output) { + TfLiteStatus status = kTfLiteError; + switch (params->type) { + case kTfLiteFloat32: + status = GatherNd(params, indices, output); + break; + case kTfLiteInt8: + status = GatherNd(params, indices, output); + break; + default: + MicroPrintf("Params type '%s' are not supported by gather_nd.", + TfLiteTypeGetName(params->type)); + return kTfLiteError; + } + if (status != kTfLiteOk) { + MicroPrintf("gather_nd index out of bounds"); + } + return status; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* params = + tflite::micro::GetEvalInput(context, node, kParams); + const TfLiteEvalTensor* indices = + tflite::micro::GetEvalInput(context, node, kIndices); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + switch (indices->type) { + case kTfLiteInt32: + return EvalGatherNd(context, params, indices, output); + break; + default: + MicroPrintf("Indices of type '%s' are not supported by gather_nd.", + TfLiteTypeGetName(indices->type)); + return kTfLiteError; + } +} +} // namespace + +TfLiteRegistration Register_GATHER_ND() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.cpp new file mode 100644 index 0000000..0f8a718 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.cpp @@ -0,0 +1,75 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/hard_swish.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { +void* HardSwishInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(HardSwishParams)); +} + +TfLiteStatus HardSwishEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kHardSwishInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kHardSwishOutputTensor); + HardSwishParams* params = static_cast(node->user_data); + + switch (input->type) { + case kTfLiteFloat32: { + tflite::reference_ops::HardSwish( + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } break; + case kTfLiteInt8: { + tflite::reference_ops::HardSwish( + *params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } break; + default: { + MicroPrintf("Unsupported type %s", TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_HARD_SWISH() { + return tflite::micro::RegisterOp(HardSwishInit, tflite::HardSwishPrepare, + HardSwishEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.h new file mode 100644 index 0000000..cb34f13 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.h @@ -0,0 +1,30 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_HARD_SWISH_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_HARD_SWISH_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +extern const int kHardSwishInputTensor; +extern const int kHardSwishOutputTensor; + +TfLiteStatus HardSwishPrepare(TfLiteContext* context, TfLiteNode* node); +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_HARD_SWISH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish_common.cpp new file mode 100644 index 0000000..1b82154 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish_common.cpp @@ -0,0 +1,86 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/hard_swish.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/hard_swish.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +const int kHardSwishInputTensor = 0; +const int kHardSwishOutputTensor = 0; + +TfLiteStatus HardSwishPrepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TFLITE_DCHECK(node->user_data != nullptr); + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kHardSwishInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kHardSwishOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + if (input->type == kTfLiteInt8) { + HardSwishParams* params = static_cast(node->user_data); + + params->input_zero_point = input->params.zero_point; + params->output_zero_point = output->params.zero_point; + + const float input_scale = input->params.scale; + const float hires_input_scale = (1.0f / 128.0f) * input_scale; + const float reluish_scale = 3.0f / 32768.0f; + const float output_scale = output->params.scale; + + const double output_multiplier = + static_cast(hires_input_scale / output_scale); + int32_t output_multiplier_fixedpoint_int32; + QuantizeMultiplier(output_multiplier, &output_multiplier_fixedpoint_int32, + ¶ms->output_multiplier_exponent); + DownScaleInt32ToInt16Multiplier( + output_multiplier_fixedpoint_int32, + ¶ms->output_multiplier_fixedpoint_int16); + + TF_LITE_ENSURE(context, params->output_multiplier_exponent <= 0); + + const double reluish_multiplier = + static_cast(hires_input_scale / reluish_scale); + int32_t reluish_multiplier_fixedpoint_int32; + QuantizeMultiplier(reluish_multiplier, &reluish_multiplier_fixedpoint_int32, + ¶ms->reluish_multiplier_exponent); + DownScaleInt32ToInt16Multiplier( + reluish_multiplier_fixedpoint_int32, + ¶ms->reluish_multiplier_fixedpoint_int16); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/if.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/if.cpp new file mode 100644 index 0000000..afa9920 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/if.cpp @@ -0,0 +1,121 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +namespace { + +struct OpData { + int then_subgraph_index; + int else_subgraph_index; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + OpData* op_data = reinterpret_cast(node->user_data); + const auto* params = + reinterpret_cast(node->builtin_data); + op_data->then_subgraph_index = params->then_subgraph_index; + op_data->else_subgraph_index = params->else_subgraph_index; + + TF_LITE_ENSURE(context, node->inputs->size > 0); + + // The first input is the condition. + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + TfLiteTensor* cond = micro_context->AllocateTempInputTensor(node, 0); + + TF_LITE_ENSURE(context, cond != nullptr); + TF_LITE_ENSURE_EQ(context, cond->type, kTfLiteBool); + TF_LITE_ENSURE_EQ(context, NumElements(cond), 1); + + micro_context->DeallocateTempTfLiteTensor(cond); + + // The first input of the node is the condition. The rest of inputs are + // passed to the branch subgraphs. Therefore, the number of subgraph inputs + // will be the number of node inputs - 1. + size_t num_inputs = node->inputs->size - 1; + size_t num_outputs = node->outputs->size; + + MicroGraph& graph_info = micro_context->graph(); + + TF_LITE_ENSURE(context, + op_data->then_subgraph_index < graph_info.NumSubgraphs()); + TF_LITE_ENSURE(context, + op_data->else_subgraph_index < graph_info.NumSubgraphs()); + + TF_LITE_ENSURE_EQ(context, num_inputs, + graph_info.NumSubgraphInputs(op_data->then_subgraph_index)); + TF_LITE_ENSURE_EQ( + context, num_outputs, + graph_info.NumSubgraphOutputs(op_data->then_subgraph_index)); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const OpData* op_data = reinterpret_cast(node->user_data); + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + TfLiteTensor* cond = micro_context->AllocateTempInputTensor(node, 0); + + TF_LITE_ENSURE(context, cond != nullptr); + bool cond_value = cond->data.b[0]; + micro_context->DeallocateTempTfLiteTensor(cond); + + MicroGraph* graph_info = µ_context->graph(); + // Currently we copy the input / output between the subgraphs. + int active_branch_subgraph_index = + cond_value ? op_data->then_subgraph_index : op_data->else_subgraph_index; + + TF_LITE_ENSURE_OK(context, + tflite::micro::CopyOpInputsToSubgraphInputs( + context, node, graph_info, active_branch_subgraph_index, + /*first_tensor_idx=*/1)); + + TF_LITE_ENSURE_OK(context, + graph_info->InvokeSubgraph(active_branch_subgraph_index)); + + TF_LITE_ENSURE_OK( + context, tflite::micro::CopySubgraphOutputsToOpOutputs( + context, node, graph_info, active_branch_subgraph_index)); + + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_IF() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.cpp new file mode 100644 index 0000000..e731f4e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.cpp @@ -0,0 +1,121 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_arena_constants.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h" + +namespace tflite { +namespace micro { + +// TODO(b/161841696): Consider moving away from global arena buffers: +constexpr int KernelRunner::kKernelRunnerBufferSize_; +uint8_t KernelRunner::kKernelRunnerBuffer_[]; + +void ClearBufferApi(TfLiteContext* context_) { + context_->GetScratchBuffer = nullptr; + context_->GetExternalContext = nullptr; + context_->AllocatePersistentBuffer = nullptr; + context_->RequestScratchBufferInArena = nullptr; +} + +KernelRunner::KernelRunner(const TfLiteRegistration& registration, + TfLiteTensor* tensors, int tensors_size, + TfLiteIntArray* inputs, TfLiteIntArray* outputs, + void* builtin_data, TfLiteIntArray* intermediates) + : registration_(registration), + allocator_(SingleArenaBufferAllocator::Create(kKernelRunnerBuffer_, + kKernelRunnerBufferSize_)), + mock_micro_graph_(allocator_), + fake_micro_context_(tensors, allocator_, &mock_micro_graph_) { + // Prepare TfLiteContext: + context_.impl_ = static_cast(&fake_micro_context_); + context_.ReportError = MicroContextReportOpError; + context_.recommended_num_threads = 1; + context_.GetTensor = MicroContextGetTensor; + context_.GetEvalTensor = MicroContextGetEvalTensor; + tflite::micro::ClearBufferApi(&context_); + context_.AllocatePersistentBuffer = MicroContextAllocatePersistentBuffer; + + context_.recommended_num_threads = 0; + + // Prepare TfLiteNode: + node_.inputs = inputs; + node_.outputs = outputs; + node_.builtin_data = builtin_data; + node_.intermediates = intermediates; +} + +bool KernelRunner::ValidateTempBufferDeallocated() { + return fake_micro_context_.IsAllTempTfLiteTensorDeallocated(); +} + +TfLiteStatus KernelRunner::InitAndPrepare(const char* init_data, + size_t length) { + if (registration_.init) { + tflite::micro::ClearBufferApi(&context_); + context_.AllocatePersistentBuffer = MicroContextAllocatePersistentBuffer; + node_.user_data = registration_.init(&context_, init_data, length); + } + + TF_LITE_ENSURE(&context_, ValidateTempBufferDeallocated()); + + if (registration_.prepare) { + tflite ::micro::ClearBufferApi(&context_); + context_.AllocatePersistentBuffer = MicroContextAllocatePersistentBuffer; + context_.RequestScratchBufferInArena = + MicroContextRequestScratchBufferInArena; + context_.GetExternalContext = MicroContextGetExternalContext; + TF_LITE_ENSURE_STATUS(registration_.prepare(&context_, &node_)); + } + + TF_LITE_ENSURE(&context_, ValidateTempBufferDeallocated()); + + return kTfLiteOk; +} + +TfLiteStatus KernelRunner::Invoke() { + tflite::micro::ClearBufferApi(&context_); + context_.GetScratchBuffer = MicroContextGetScratchBuffer; + + if (registration_.invoke == nullptr) { + MicroPrintf("TfLiteRegistration missing invoke function pointer!"); + return kTfLiteError; + } + + TF_LITE_ENSURE_STATUS(registration_.invoke(&context_, &node_)); + + TF_LITE_ENSURE(&context_, ValidateTempBufferDeallocated()); + + return kTfLiteOk; +} + +TfLiteStatus KernelRunner::Free() { + tflite::micro::ClearBufferApi(&context_); + context_.GetScratchBuffer = MicroContextGetScratchBuffer; + + if (registration_.free == nullptr) { + MicroPrintf("TfLiteRegistration missing free function pointer!"); + return kTfLiteError; + } + + registration_.free(&context_, node_.user_data); + return kTfLiteOk; +} +} // namespace micro +} // namespace tflite \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.h new file mode 100644 index 0000000..cf3c690 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_runner.h @@ -0,0 +1,81 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_KERNEL_RUNNER_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_KERNEL_RUNNER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/fake_micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.h" + +namespace tflite { +namespace micro { + +// Helper class to perform a simulated kernel (i.e. TfLiteRegistration) +// lifecycle (init, prepare, invoke). All internal allocations are handled by +// this class. Simply pass in the registration, list of required tensors, inputs +// array, outputs array, and any pre-builtin data. Calling Invoke() will +// automatically walk the kernel and outputs will be ready on the TfLiteTensor +// output provided during construction. +class KernelRunner { + public: + KernelRunner(const TfLiteRegistration& registration, TfLiteTensor* tensors, + int tensors_size, TfLiteIntArray* inputs, + TfLiteIntArray* outputs, void* builtin_data, + TfLiteIntArray* intermediates = nullptr); + + // Calls init and prepare on the kernel (i.e. TfLiteRegistration) struct. Any + // exceptions will be DebugLog'd and returned as a status code. + TfLiteStatus InitAndPrepare(const char* init_data = nullptr, + size_t length = 0); + + // Calls init, prepare, and invoke on a given TfLiteRegistration pointer. + // After successful invoke, results will be available in the output tensor as + // passed into the constructor of this class. + TfLiteStatus Invoke(); + + // Calls Free on a given TfLiteRegistration pointer(if it's implemented). + // After successful Free, kTfLiteOk status will be returned. If Free is not + // implemented for a given kernel kTfLiteError will be returned. + TfLiteStatus Free(); + + // Returns a pointer to the internal MockMicroGraph which KernelRunner uses + // to stub out MicroGraph methods and track invocations on each subgraph. + MockMicroGraph* GetMockGraph() { return &mock_micro_graph_; } + + // Returns true if all temp buffer in tests are deallocated. + // TODO(b/209453859): move this function to private after deallocation checks + // are enabled for all kernel tests. + bool ValidateTempBufferDeallocated(); + + private: + static constexpr int kKernelRunnerBufferSize_ = 10000; + static uint8_t kKernelRunnerBuffer_[kKernelRunnerBufferSize_]; + + TfLiteContext context_ = {}; + TfLiteNode node_ = {}; + const TfLiteRegistration& registration_; + + SingleArenaBufferAllocator* allocator_; + MockMicroGraph mock_micro_graph_; + FakeMicroContext fake_micro_context_; +}; + +} // namespace micro +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_KERNEL_RUNNER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h new file mode 100644 index 0000000..616e7ff --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h @@ -0,0 +1,145 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_KERNEL_UTIL_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_KERNEL_UTIL_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" + +namespace tflite { +namespace micro { + +TfLiteRegistration RegisterOp( + void* (*init)(TfLiteContext* context, const char* buffer, size_t length), + TfLiteStatus (*prepare)(TfLiteContext* context, TfLiteNode* node), + TfLiteStatus (*invoke)(TfLiteContext* context, TfLiteNode* node), + void (*free)(TfLiteContext* context, void* buffer) = nullptr); + +// Prints out n bytes in a int8_t buffer as hex +void PrintNBytes(const int8_t* tensor_data, int n_bytes, + const char* prefix = nullptr); + +// Prints out the the n bytes in a TfLiteEvalTensor as hex +void PrintNBytes(const TfLiteEvalTensor* tensor, int n_bytes, + const char* prefix = nullptr); + +// Prints out the the n bytes in a TfLiteTensor as hex +void PrintNBytes(const TfLiteTensor* tensor, int n_bytes, + const char* prefix = nullptr); + +// Returns a mutable tensor for a given input index. is_variable must be checked +// during prepare when the full TfLiteTensor is available. +TfLiteEvalTensor* GetMutableEvalInput(const TfLiteContext* context, + const TfLiteNode* node, int index); + +// Returns the TfLiteEvalTensor struct for a given input index in a node. +const TfLiteEvalTensor* GetEvalInput(const TfLiteContext* context, + const TfLiteNode* node, int index); + +// Returns the TfLiteEvalTensor struct for a given output index in a node. +TfLiteEvalTensor* GetEvalOutput(const TfLiteContext* context, + const TfLiteNode* node, int index); + +// Returns data for a TfLiteEvalTensor struct that are expected to exist. +template +T* GetTensorData(TfLiteEvalTensor* tensor) { + TFLITE_DCHECK(tensor != nullptr); + return reinterpret_cast(tensor->data.raw); +} + +// Returns const data for a TfLiteEvalTensor struct that are expected to exist. +template +const T* GetTensorData(const TfLiteEvalTensor* tensor) { + TFLITE_DCHECK(tensor != nullptr); + return reinterpret_cast(tensor->data.raw); +} + +// Returns data for a TfLiteEvalTensor struct that could be null. +template +T* GetOptionalTensorData(TfLiteEvalTensor* tensor) { + return tensor == nullptr ? nullptr : reinterpret_cast(tensor->data.raw); +} + +// Returns const data for a TfLiteEvalTensor struct that could be null. +template +const T* GetOptionalTensorData(const TfLiteEvalTensor* tensor) { + return tensor == nullptr ? nullptr + : reinterpret_cast(tensor->data.raw); +} + +// Returns the shape of a TfLiteEvalTensor struct. +const RuntimeShape GetTensorShape(const TfLiteEvalTensor* tensor); + +// Return true if the given tensors have the same shape. +bool HaveSameShapes(const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2); + +PaddingType RuntimePaddingType(TfLitePadding padding); + +// Relocate tensor dims from FlatBuffer to the persistent storage arena. +// The old dims data is copied to the new storage area. +// The tensor and eval_tensor must be the same tensor. +// Only use during Prepare phase. +TfLiteStatus CreateWritableTensorDimsWithCopy(TfLiteContext* context, + TfLiteTensor* tensor, + TfLiteEvalTensor* eval_tensor); + +// Copy all op input tensors to op output tensors. Requires all op input tensor +// shapes and types to be identical to op output tensor shapes and types. +TfLiteStatus CopyOpInputsToOpOutputs(TfLiteContext* context, TfLiteNode* node); + +// Copy all op input tensors to subgraph input tensors. Requires all op input +// tensor shapes and types to be identical to subgraph input tensor shapes and +// types. +TfLiteStatus CopyOpInputsToSubgraphInputs(TfLiteContext* context, + TfLiteNode* node, + MicroGraph* graph_info, + int subgraph_idx, + int first_tensor_idx); + +// Copy all op output tensors to subgraph input tensors. Requires all op output +// tensor shapes and types to be identical to subgraph input tensor shapes and +// types. +TfLiteStatus CopyOpOutputsToSubgraphInputs(TfLiteContext* context, + TfLiteNode* node, + MicroGraph* graph_info, + int subgraph_idx); + +// Copy all subgraph output tensors to op outputs. Requires all subgraph output +// tensor shapes and types to be identical to op output tensor shapes and types. +TfLiteStatus CopySubgraphOutputsToOpOutputs(TfLiteContext* context, + TfLiteNode* node, + MicroGraph* graph_info, + int subgraph_idx); + +// If tensor is INT4, make a new TfLiteEvalTensor with data unpacked into +// a scratch buffer. The returned tensor will have the kTfLiteInt8 type. +// Assume scratch buffer is previously requested in Prepare, and +// scratch_buffer_index can be used to retrieve that buffer. +// If the tensor is not INT4, a shallow copy is returned. +TfLiteEvalTensor MakeUnpackedInt4Tensor(TfLiteContext* context, + int scratch_buffer_index, + const TfLiteEvalTensor* tensor); +} // namespace micro +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_KERNEL_UTIL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util_micro.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util_micro.cpp new file mode 100644 index 0000000..73ab130 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util_micro.cpp @@ -0,0 +1,280 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace micro { + +namespace { + +int ValidateTensorIndexing(const TfLiteContext* context, int index, + int max_size, const int* tensor_indices) { + if (index >= 0 && index < max_size) { + const int tensor_index = tensor_indices[index]; + if (tensor_index != kTfLiteOptionalTensor) { + return tensor_index; + } + } + return -1; +} + +} // namespace + +TfLiteRegistration RegisterOp( + void* (*init)(TfLiteContext* context, const char* buffer, size_t length), + TfLiteStatus (*prepare)(TfLiteContext* context, TfLiteNode* node), + TfLiteStatus (*invoke)(TfLiteContext* context, TfLiteNode* node), + void (*free)(TfLiteContext* context, void* buffer)) { + return {/*init=*/init, + /*free=*/free, + /*prepare=*/prepare, + /*invoke=*/invoke, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0, + /*registration_external=*/nullptr}; +} + +// Returns a mutable tensor for a given input index. is_variable must be checked +// during prepare when the full TfLiteTensor is available. +TfLiteEvalTensor* GetMutableEvalInput(const TfLiteContext* context, + const TfLiteNode* node, int index) { + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(node != nullptr); + const int tensor_index = ValidateTensorIndexing( + context, index, node->inputs->size, node->inputs->data); + + if (tensor_index < 0) { + return nullptr; + } + + return context->GetEvalTensor(context, node->inputs->data[index]); +} + +// Returns the TfLiteEvalTensor struct for a given input index in a node. +const TfLiteEvalTensor* GetEvalInput(const TfLiteContext* context, + const TfLiteNode* node, int index) { + return GetMutableEvalInput(context, node, index); +} + +// Returns the TfLiteEvalTensor struct for a given output index in a node. +TfLiteEvalTensor* GetEvalOutput(const TfLiteContext* context, + const TfLiteNode* node, int index) { + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(node != nullptr); + return context->GetEvalTensor(context, node->outputs->data[index]); +} + +bool HaveSameShapes(const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2) { + TFLITE_DCHECK(input1 != nullptr); + TFLITE_DCHECK(input2 != nullptr); + return TfLiteIntArrayEqual(input1->dims, input2->dims); +} + +const RuntimeShape GetTensorShape(const TfLiteEvalTensor* tensor) { + if (tensor == nullptr || tensor->dims == nullptr) { + return RuntimeShape(); + } + TfLiteIntArray* dims = tensor->dims; + const int dims_size = dims->size; + const int32_t* dims_data = reinterpret_cast(dims->data); + return RuntimeShape(dims_size, dims_data); +} + +PaddingType RuntimePaddingType(TfLitePadding padding) { + switch (padding) { + case TfLitePadding::kTfLitePaddingSame: + return PaddingType::kSame; + case TfLitePadding::kTfLitePaddingValid: + return PaddingType::kValid; + case TfLitePadding::kTfLitePaddingUnknown: + default: + return PaddingType::kNone; + } +} + +// Relocate tensor dims from FlatBuffer to the persistent storage arena. +// The old dims data is copied to the new storage area. +// The tensor and eval_tensor must be the same tensor. +// Only use during Prepare phase. +TfLiteStatus CreateWritableTensorDimsWithCopy(TfLiteContext* context, + TfLiteTensor* tensor, + TfLiteEvalTensor* eval_tensor) { + TF_LITE_ENSURE(context, tensor != nullptr); + TF_LITE_ENSURE(context, eval_tensor != nullptr); + TF_LITE_ENSURE(context, context->AllocatePersistentBuffer != nullptr); + int ranks = tensor->dims->size; + size_t alloc_size = TfLiteIntArrayGetSizeInBytes(ranks); + TfLiteIntArray* new_dims = static_cast( + context->AllocatePersistentBuffer(context, alloc_size)); + TfLiteIntArray* old_dims = tensor->dims; + new_dims->size = ranks; + tensor->dims = new_dims; + eval_tensor->dims = new_dims; + for (int i = 0; i < ranks; i++) { + new_dims->data[i] = old_dims->data[i]; + } + + return kTfLiteOk; +} + +// Verify that both tensors have the same type and size, then return the size +// of both tensors in bytes if they are the same, or -1 if they are different. +size_t ValidateAndGetTensorSizes(const TfLiteEvalTensor* tensor1, + const TfLiteEvalTensor* tensor2) { + TFLITE_DCHECK(tensor1->type == tensor2->type); + size_t tensor1_size = 0; + size_t tensor2_size = 0; + TfLiteEvalTensorByteLength(tensor1, &tensor1_size); + TfLiteEvalTensorByteLength(tensor2, &tensor2_size); + return (tensor1_size == tensor2_size) ? tensor1_size : -1; +} + +TfLiteStatus CopyOpInputsToOpOutputs(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE(context, node->inputs->size == node->outputs->size); + for (int i = 0; i < node->inputs->size; i++) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, i); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, i); + int bytes = ValidateAndGetTensorSizes(input, output); + TF_LITE_ENSURE(context, bytes >= 0); + memcpy(output->data.raw, input->data.raw, bytes); + } + return kTfLiteOk; +} + +// Args: +// 1. int8_t tensor_data - int8_t buffer of unknown size who's data you'd +// like +// to print +// 2. int n_btyes - a small int representing number of bytes you want to +// print +// to debug output. It should always be <= tensor_data's size. +// 3. prefix - optional message you'd like to print before printing bytes +// +// Purpose: +// Function takes in paramaters above and prints n_bytes bytes from the +// tensor_data buffer. This can be use to debug the output of a model and it's +// op. + +void PrintNBytes(const int8_t* tensor_data, int n_bytes, const char* prefix) { + if (prefix != nullptr) { + MicroPrintf("%s", prefix); + } + + for (int i = 0; i < n_bytes; ++i) { + MicroPrintf(" %x", tensor_data[i]); + } + MicroPrintf("\n"); +} + +// same as the PrintNBytes above but the buffer needs to be extracted out of the +// TfLiteEvalTensor* +void PrintNBytes(const TfLiteEvalTensor* tensor, int n_bytes, + const char* prefix) { + const int8_t* tensor_data = tflite::micro::GetTensorData(tensor); + PrintNBytes(tensor_data, n_bytes, prefix); +} + +// same as the PrintNBytes above but the buffer needs to be extracted out of the +// TfLiteEvalTensor* +void PrintNBytes(const TfLiteTensor* tensor, int n_bytes, const char* prefix) { + const int8_t* tensor_data = tflite::GetTensorData(tensor); + PrintNBytes(tensor_data, n_bytes, prefix); +} + +TfLiteStatus CopyOpInputsToSubgraphInputs(TfLiteContext* context, + TfLiteNode* node, + MicroGraph* graph_info, + int subgraph_idx, + int first_tensor_idx) { + TF_LITE_ENSURE(context, + static_cast(node->inputs->size - first_tensor_idx) == + graph_info->NumSubgraphInputs(subgraph_idx)); + for (int i = 0; i < node->inputs->size - first_tensor_idx; i++) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, i + first_tensor_idx); + TfLiteEvalTensor* subgraph_input = + graph_info->GetSubgraphInput(subgraph_idx, i); + int bytes = ValidateAndGetTensorSizes(input, subgraph_input); + TF_LITE_ENSURE(context, bytes >= 0); + memcpy(subgraph_input->data.raw, input->data.raw, bytes); + } + return kTfLiteOk; +} + +TfLiteStatus CopyOpOutputsToSubgraphInputs(TfLiteContext* context, + TfLiteNode* node, + MicroGraph* graph_info, + int subgraph_idx) { + TF_LITE_ENSURE(context, static_cast(node->outputs->size) == + graph_info->NumSubgraphInputs(subgraph_idx)); + for (int i = 0; i < node->outputs->size; i++) { + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, i); + TfLiteEvalTensor* subgraph_input = + graph_info->GetSubgraphInput(subgraph_idx, i); + int bytes = ValidateAndGetTensorSizes(output, subgraph_input); + TF_LITE_ENSURE(context, bytes >= 0); + memcpy(subgraph_input->data.raw, output->data.raw, bytes); + } + return kTfLiteOk; +} + +TfLiteStatus CopySubgraphOutputsToOpOutputs(TfLiteContext* context, + TfLiteNode* node, + MicroGraph* graph_info, + int subgraph_idx) { + TF_LITE_ENSURE(context, static_cast(node->outputs->size) == + graph_info->NumSubgraphOutputs(subgraph_idx)); + for (int i = 0; i < node->outputs->size; i++) { + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, i); + TfLiteEvalTensor* subgraph_output = + graph_info->GetSubgraphOutput(subgraph_idx, i); + int bytes = ValidateAndGetTensorSizes(output, subgraph_output); + TF_LITE_ENSURE(context, bytes >= 0); + memcpy(output->data.raw, subgraph_output->data.raw, bytes); + } + return kTfLiteOk; +} + +TfLiteEvalTensor MakeUnpackedInt4Tensor(TfLiteContext* context, + int scratch_buffer_index, + const TfLiteEvalTensor* tensor) { + if (tensor->type != kTfLiteInt4) { + return *tensor; + } + + TfLiteEvalTensor new_tensor; + new_tensor.data.data = static_cast( + context->GetScratchBuffer(context, scratch_buffer_index)); + new_tensor.dims = tensor->dims; + new_tensor.type = kTfLiteInt8; + tflite::tensor_utils::UnpackDenseInt4IntoInt8( + tflite::micro::GetTensorData(tensor), + tflite::micro::GetTensorShape(tensor).FlatSize(), + tflite::micro::GetTensorData(&new_tensor)); + return new_tensor; +} + +} // namespace micro +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/l2_pool_2d.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/l2_pool_2d.cpp new file mode 100644 index 0000000..8cd1e7e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/l2_pool_2d.cpp @@ -0,0 +1,142 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +// Input/output tensor index. +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +// required rank for input/output tensor shape +constexpr int kTensorShapeRank = 4; + +// input/output tensor shape rank associations +enum { kBatchRank = 0, kHeightRank, kWidthRank, kChannelRank }; + +TfLiteStatus L2Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + auto* params = static_cast(node->builtin_data); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE_EQ(context, NumDimensions(input), kTensorShapeRank); + TF_LITE_ENSURE_EQ(context, NumDimensions(output), kTensorShapeRank); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + int batches = SizeOfDimension(input, kBatchRank); + int height = SizeOfDimension(input, kHeightRank); + int width = SizeOfDimension(input, kWidthRank); + int channels_out = SizeOfDimension(input, kChannelRank); + + // Matching GetWindowedOutputSize in TensorFlow. + auto padding = params->padding; + int out_width, out_height; + + params->computed.padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, 1, 1, height, width, + params->filter_height, params->filter_width, padding, &out_height, + &out_width); + + // We currently don't have a quantized implementation of L2Pool + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteFloat32); + + // We must update the output tensor dimensions. + // The dims storage is expected to be the same area in memory + // for both TfLiteTensor and TfLiteEvalTensor. This is important + // because TfLiteTensor in the MicroInterpreter is a temporary + // allocation. For the KernelRunner interpreter, TfLiteEvalTensor + // is a temporary allocation. We must therefore relocate the dims + // from the FlatBuffer to the persistant storage arena. + TfLiteEvalTensor* output_eval = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE_OK(context, tflite::micro::CreateWritableTensorDimsWithCopy( + context, output, output_eval)); + output->dims->data[kBatchRank] = batches; + output->dims->data[kHeightRank] = out_height; + output->dims->data[kWidthRank] = out_width; + output->dims->data[kChannelRank] = channels_out; + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + + return kTfLiteOk; +} + +void L2EvalFloat(const TfLitePoolParams& params, const TfLiteEvalTensor& input, + tflite::PoolParams* op_params, TfLiteEvalTensor* output) { + float activation_min, activation_max; + CalculateActivationRange(params.activation, &activation_min, &activation_max); + + op_params->float_activation_min = activation_min; + op_params->float_activation_max = activation_max; + reference_ops::L2Pool(*op_params, tflite::micro::GetTensorShape(&input), + tflite::micro::GetTensorData(&input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +TfLiteStatus L2Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = static_cast(node->builtin_data); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + + tflite::PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = params->computed.padding.height; + op_params.padding_values.width = params->computed.padding.width; + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: + L2EvalFloat(*params, *input, &op_params, output); + break; + default: + MicroPrintf("L2_POOL_2D only supports float32 currently, got %s.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_L2_POOL_2D() { + return tflite::micro::RegisterOp(nullptr, L2Prepare, L2Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/l2norm.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/l2norm.cpp new file mode 100644 index 0000000..ede02db --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/l2norm.cpp @@ -0,0 +1,148 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/l2normalization.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/l2normalization.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace l2norm { + +namespace { + +// This file has two implementation of L2Norm. +enum KernelType { + kReference, + kGenericOptimized, +}; + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +} // namespace + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* params = reinterpret_cast(node->builtin_data); + L2NormalizationParams* data = + static_cast(node->user_data); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE(context, NumDimensions(input) <= 4); + + TF_LITE_ENSURE(context, + output->type == kTfLiteFloat32 || output->type == kTfLiteInt8); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + if (output->type == kTfLiteInt8) { + data->input_zero_point = input->params.zero_point; + } else if (output->type == kTfLiteFloat32) { + data->input_zero_point = 0; + } + + // Our implementations don't currently support activations. + TF_LITE_ENSURE_EQ(context, params->activation, kTfLiteActNone); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, + sizeof(L2NormalizationParams)); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const L2NormalizationParams& data = + *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + // TODO(b/143912164): instead of hardcode the epsilon here, we should read it + // from tensorflow, i.e., adding a params. + // We don't compute epsilon for quantized kernel: + // + // epsilon_float = (epsilon_quant - zp) * scale + // so + // espsilon_quant = epsilon_float / scale + zp + // We know epsilon_float is just a very small number to avoid division by + // zero error, and scale is > 1, so the integer value of epsilon for quant + // is just dominated by the zero point. + // Also, GetInvSqrtQuantizedMultiplierExp handles the scenario where the sum + // of input value squared is zero case well. + // So we don't even need to do handle the epsilon for quantized kernel case. + const float epsilon = 1e-6f; + if (output->type == kTfLiteFloat32) { + reference_ops::L2Normalization(data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + epsilon); + } else if (output->type == kTfLiteInt8) { + const auto input_shape = tflite::micro::GetTensorShape(input); + const auto output_shape = tflite::micro::GetTensorShape(output); + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + reference_integer_ops::L2Normalization( + data.input_zero_point, outer_size, depth, + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorData(output)); + } else { + MicroPrintf("Output type is %s, requires float.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace l2norm + +TfLiteRegistration Register_L2NORM_REF() { + return tflite::micro::RegisterOp(l2norm::Init, l2norm::Prepare, l2norm::Eval); +} + +TfLiteRegistration Register_L2_NORMALIZATION() { return Register_L2NORM_REF(); } + +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.cpp new file mode 100644 index 0000000..042528d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.cpp @@ -0,0 +1,95 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/leaky_relu.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +template +void QuantizeLeakyRelu(const LeakyReluOpData& data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + LeakyReluParams op_params = {}; + + op_params.input_offset = data.input_zero_point; + op_params.output_offset = data.output_zero_point; + op_params.output_multiplier_alpha = data.output_multiplier_alpha; + op_params.output_shift_alpha = data.output_shift_alpha; + op_params.output_multiplier_identity = data.output_multiplier_identity; + op_params.output_shift_identity = data.output_shift_identity; + reference_ops::QuantizeLeakyRelu(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +void* LeakyReluInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(LeakyReluOpData)); +} + +TfLiteStatus LeakyReluEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + const LeakyReluOpData& data = *static_cast(node->user_data); + + switch (input->type) { + case kTfLiteFloat32: { + LeakyReluParams op_params = {}; + const auto* params = + static_cast(node->builtin_data); + + op_params.alpha = params->alpha; + reference_ops::LeakyRelu(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + case kTfLiteInt8: { + QuantizeLeakyRelu(data, input, output); + return kTfLiteOk; + } break; + case kTfLiteInt16: { + QuantizeLeakyRelu(data, input, output); + return kTfLiteOk; + } break; + default: + MicroPrintf("Only float32, int8 are supported by LEAKY_RELU, got %s.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + return kTfLiteError; +} + +TfLiteRegistration Register_LEAKY_RELU() { + return tflite::micro::RegisterOp(LeakyReluInit, LeakyReluPrepare, + LeakyReluEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.h new file mode 100644 index 0000000..fe43060 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.h @@ -0,0 +1,43 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_LEAKY_RELU_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_LEAKY_RELU_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +// Input/output tensor index. +extern const int kInputTensor; +extern const int kOutputTensor; + +struct LeakyReluOpData { + // quantization parameters + int32_t output_multiplier_alpha; + int32_t output_shift_alpha; + int32_t output_multiplier_identity; + int32_t output_shift_identity; + int32_t input_zero_point; + int32_t output_zero_point; +}; + +TfLiteStatus CalculateOpDataLeakyRelu(TfLiteContext* context, TfLiteNode* node); + +TfLiteStatus LeakyReluPrepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_LEAKY_RELU_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu_common.cpp new file mode 100644 index 0000000..b71b743 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu_common.cpp @@ -0,0 +1,78 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/leaky_relu.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/leaky_relu.h" + +namespace tflite { + +// Input/output tensor index. +const int kInputTensor = 0; +const int kOutputTensor = 0; + +TfLiteStatus CalculateOpDataLeakyRelu(TfLiteContext* context, + TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + LeakyReluOpData* data = static_cast(node->user_data); + const auto* params = + static_cast(node->builtin_data); + + data->input_zero_point = input->params.zero_point; + data->output_zero_point = output->params.zero_point; + + int output_shift_alpha; + double alpha_multiplier = static_cast( + input->params.scale * params->alpha / output->params.scale); + QuantizeMultiplier(alpha_multiplier, &data->output_multiplier_alpha, + &output_shift_alpha); + data->output_shift_alpha = static_cast(output_shift_alpha); + + int output_shift_identity; + double identity_multiplier = + static_cast(input->params.scale / output->params.scale); + QuantizeMultiplier(identity_multiplier, &data->output_multiplier_identity, + &output_shift_identity); + data->output_shift_identity = static_cast(output_shift_identity); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus LeakyReluPrepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpDataLeakyRelu(context, node); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/log_softmax.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/log_softmax.cpp new file mode 100644 index 0000000..4cfccb2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/log_softmax.cpp @@ -0,0 +1,148 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/log_softmax.h" + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +// used only with quantized data +struct LogSoftmaxOpData { + int32_t input_multiplier; + int32_t input_left_shift; + int32_t reverse_scaling_divisor; + int32_t reverse_scaling_right_shift; + int diff_min; + size_t outer_size; // number of tensor elements skipping computation axis + size_t depth; // number of tensor elements on computation axis +}; + +// input/output tensor index +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + TF_LITE_ENSURE(context, HaveSameShapes(input, output)); + + if (input->type == kTfLiteInt8) { + node->user_data = + context->AllocatePersistentBuffer(context, sizeof(LogSoftmaxOpData)); + auto data = static_cast(node->user_data); + + // quantization datum + constexpr int32_t kOutputZeroPoint = 127; + constexpr float kOutputScale = 16.0 / 256; + constexpr double kBeta = 1.0; + constexpr int kScaledDiffIntegerBits = 5; + + TF_LITE_ENSURE(context, output->params.scale == kOutputScale); + TF_LITE_ENSURE(context, output->params.zero_point == kOutputZeroPoint); + + int input_left_shift; + int reverse_scaling_right_shift; + tflite::PreprocessLogSoftmaxScalingExp( + kBeta, static_cast(input->params.scale), kScaledDiffIntegerBits, + &data->input_multiplier, &input_left_shift, + &data->reverse_scaling_divisor, &reverse_scaling_right_shift); + data->input_left_shift = static_cast(input_left_shift); + data->reverse_scaling_right_shift = + static_cast(-reverse_scaling_right_shift); + // diff_min has a negative value, and is used to limit the maximum magnitude + // of the diffs, which are <= 0. + data->diff_min = + -tflite::CalculateInputRadius(kScaledDiffIntegerBits, input_left_shift); + + RuntimeShape input_shape = GetTensorShape(input); + const int trailing_dim = input_shape.DimensionsCount() - 1; + data->outer_size = + static_cast(FlatSizeSkipDim(input_shape, trailing_dim)); + data->depth = static_cast(input_shape.Dims(trailing_dim)); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus LogSoftmaxPrepare(TfLiteContext* context, TfLiteNode* node) { + return CalculateOpData(context, node); +} + +TfLiteStatus LogSoftmaxEval(TfLiteContext* context, TfLiteNode* node) { + const LogSoftmaxOpData* data = + static_cast(node->user_data); + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + switch (input->type) { + case kTfLiteFloat32: { + SoftmaxParams op_params = {}; + reference_ops::LogSoftmax(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + case kTfLiteInt8: { + SoftmaxParams op_params = {}; + op_params.input_multiplier = data->input_multiplier; + op_params.input_left_shift = data->input_left_shift; + op_params.reverse_scaling_divisor = data->reverse_scaling_divisor; + op_params.reverse_scaling_right_shift = data->reverse_scaling_right_shift; + op_params.diff_min = data->diff_min; + reference_ops::LogSoftmax(op_params, data->outer_size, data->depth, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + default: + MicroPrintf("LOG_SOFTMAX only supports float32, int8, got %s.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } +} + +} // namespace + +TfLiteRegistration Register_LOG_SOFTMAX() { + return tflite::micro::RegisterOp(nullptr, LogSoftmaxPrepare, LogSoftmaxEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.cpp new file mode 100644 index 0000000..2b38501 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.cpp @@ -0,0 +1,44 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { +namespace { + +TfLiteStatus LogicalOrEval(TfLiteContext* context, TfLiteNode* node) { + return LogicalImpl(context, node, LogicalOr); +} + +TfLiteStatus LogicalAndEval(TfLiteContext* context, TfLiteNode* node) { + return LogicalImpl(context, node, LogicalAnd); +} + +} // namespace + +TfLiteRegistration Register_LOGICAL_OR() { + return tflite::micro::RegisterOp(nullptr, nullptr, LogicalOrEval); +} + +TfLiteRegistration Register_LOGICAL_AND() { + return tflite::micro::RegisterOp(nullptr, nullptr, LogicalAndEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.h new file mode 100644 index 0000000..8dadde4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.h @@ -0,0 +1,35 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_LOGICAL_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_LOGICAL_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { +// Input/output tensor index. +extern const int kLogicalInputTensor1; +extern const int kLogicalInputTensor2; +extern const int kLogicalOutputTensor; + +TfLiteStatus LogicalImpl(TfLiteContext* context, TfLiteNode* node, + bool (*func)(bool, bool)); + +bool LogicalOr(bool x, bool y); +bool LogicalAnd(bool x, bool y); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_LOGICAL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical_common.cpp new file mode 100644 index 0000000..1586d2f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logical_common.cpp @@ -0,0 +1,63 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/logical.h" + +namespace tflite { + +// Input/output tensor index. +const int kLogicalInputTensor1 = 0; +const int kLogicalInputTensor2 = 1; +const int kLogicalOutputTensor = 0; + +TfLiteStatus LogicalImpl(TfLiteContext* context, TfLiteNode* node, + bool (*func)(bool, bool)) { + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kLogicalInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kLogicalInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kLogicalOutputTensor); + + if (tflite::micro::HaveSameShapes(input1, input2)) { + reference_ops::BinaryFunction( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), func); + } else { + reference_ops::BroadcastBinaryFunction4DSlow( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), func); + } + + return kTfLiteOk; +} + +bool LogicalOr(bool x, bool y) { return x || y; } + +bool LogicalAnd(bool x, bool y) { return x && y; } + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.cpp new file mode 100644 index 0000000..82579ea --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.cpp @@ -0,0 +1,111 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/logistic.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/logistic.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +void* LogisticInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataLogistic)); +} + +TfLiteStatus LogisticEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kLogisticInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kLogisticOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + OpDataLogistic* data = static_cast(node->user_data); + + if (input->type == kTfLiteFloat32) { + switch (output->type) { + case kTfLiteFloat32: { + reference_ops::Logistic(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else if (input->type == kTfLiteInt16) { + switch (output->type) { + case kTfLiteInt16: { + reference_integer_ops::Logistic( + data->input_multiplier, data->input_left_shift, + NumElements(input->dims), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else if (input->type == kTfLiteInt8) { + switch (output->type) { + case kTfLiteInt8: { + reference_integer_ops::Logistic( + data->input_zero_point, data->input_range_radius, + data->input_multiplier, data->input_left_shift, + NumElements(input->dims), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else { + // TODO(b/141211002): Also support other data types once we have supported + // temporary tensors in TFLM. + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_LOGISTIC() { + return tflite::micro::RegisterOp(LogisticInit, LogisticPrepare, LogisticEval); +} +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.h new file mode 100644 index 0000000..43325e1 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.h @@ -0,0 +1,42 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_LOGISTIC_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_LOGISTIC_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { +extern const int kLogisticInputTensor; +extern const int kLogisticOutputTensor; + +struct OpDataLogistic { + int32_t input_zero_point; + int32_t input_range_radius; + int32_t input_multiplier; + int input_left_shift; +}; + +TfLiteStatus CalculateArithmeticOpDataLogistic(TfLiteContext* context, + TfLiteNode* node, + OpDataLogistic* data); + +TfLiteStatus LogisticPrepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite +#endif // TENSORFLOW_LITE_MICRO_KERNELS_LOGISTIC_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic_common.cpp new file mode 100644 index 0000000..9f27a91 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic_common.cpp @@ -0,0 +1,119 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/logistic.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/logistic.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/logistic.h" + +namespace tflite { +const int kLogisticInputTensor = 0; +const int kLogisticOutputTensor = 0; + +TfLiteStatus CalculateArithmeticOpDataLogistic(TfLiteContext* context, + TfLiteNode* node, + OpDataLogistic* data) { + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kLogisticInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kLogisticOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_EQ(context, output->params.zero_point, + std::numeric_limits::min()); + + static constexpr int kInputIntegerBits = 4; + const double input_real_multiplier = + static_cast(input->params.scale) * + static_cast(1 << (31 - kInputIntegerBits)); + + data->input_zero_point = input->params.zero_point; + + const double q = std::frexp(input_real_multiplier, &data->input_left_shift); + data->input_multiplier = static_cast(TfLiteRound(q * (1ll << 31))); + + data->input_range_radius = + CalculateInputRadius(kInputIntegerBits, data->input_left_shift, 31); + } + + if (input->type == kTfLiteInt16) { + static constexpr int kInputIntegerBits = 3; + static constexpr int kOutputFractionalBits = 15; + + // See comments in TanhPrepare about requiring zero_point==0 + // and a power-of-two ("POT") scale. + + TF_LITE_ENSURE_EQ(context, input->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + + int input_scale_log2_rounded; + bool param_scale_pot = + CheckedLog2(input->params.scale, &input_scale_log2_rounded); + + data->input_left_shift = + (15 - kInputIntegerBits) + input_scale_log2_rounded; + param_scale_pot &= (data->input_left_shift == 0); + + if (param_scale_pot) { + data->input_multiplier = 0; + } else { + // Calculate multiplier to change input scale to 1/(3*4096) + // as required by the table lookup. + // In this scaling +/-2^17 represents +/-10.7 + double multiplier = + static_cast(input->params.scale) * 4096.0 * 3.0; + + data->input_left_shift = 0; + + while (multiplier <= 32767.0 / 2.0 && data->input_left_shift <= 30) { + data->input_left_shift++; + multiplier = multiplier * 2.0; + } + + data->input_multiplier = static_cast(multiplier); + } + + int output_scale_log2_rounded; + TF_LITE_ENSURE( + context, CheckedLog2(output->params.scale, &output_scale_log2_rounded)); + TF_LITE_ENSURE_EQ(context, output_scale_log2_rounded, + -kOutputFractionalBits); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus LogisticPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + OpDataLogistic* data = static_cast(node->user_data); + + return CalculateArithmeticOpDataLogistic(context, node, data); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.cpp new file mode 100644 index 0000000..037caf7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.cpp @@ -0,0 +1,222 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/logistic.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/tanh.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/logistic.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/tanh.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { +namespace lstm_internal { + +const int32_t kInt16Max = std::numeric_limits::max(); +const int32_t kInt16Min = std::numeric_limits::min(); + +void AddElementWise(const int16_t* input_1, const int16_t* input_2, int n_batch, + int n_input, int16_t* output) { + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + int32_t sum = input_1[index] + input_2[index]; + const int32_t sum_clamped = std::min(kInt16Max, std::max(kInt16Min, sum)); + output[index] = static_cast(sum_clamped); + } + } +} + +void AddElementWise(const float* input_1, const float* input_2, int n_batch, + int n_input, float* output) { + for (int batch = 0; batch < n_batch; ++batch) { + for (int i = 0; i < n_input; ++i) { + const int index = batch * n_input + i; + output[index] = input_1[index] + input_2[index]; + } + } +} + +void Sigmoid(const RuntimeShape& data_shape, int16_t* data) { + reference_integer_ops::Logistic( + 0 /*data->input_multiplier*/, 0 /*data->input_left_shift */, + data_shape.FlatSize() /*NumElements(input->dims)*/, + data /* tflite::micro::GetTensorData(input) */, + data /*tflite::micro::GetTensorData(output) */); +} + +void Sigmoid(const RuntimeShape& data_shape, float* data) { + reference_ops::Logistic(data_shape, data, data_shape, data); +} + +void Tanh(int32_t cell_state_scale_power, const RuntimeShape& input_data_shape, + int16_t* input_data, const RuntimeShape& output_data_shape, + int16_t* output_data) { + int32_t tanh_input_left_shift = (15 + cell_state_scale_power) - 3; + if (tanh_input_left_shift < 0) /* handling negative shift value */ + { + int32_t i; + tanh_input_left_shift = -tanh_input_left_shift; + for (i = 0; i < input_data_shape.FlatSize(); i++) { + input_data[i] = input_data[i] >> tanh_input_left_shift; + } + tanh_input_left_shift = 0; + } + reference_integer_ops::Tanh(0, tanh_input_left_shift, input_data_shape, + input_data, output_data_shape, output_data); +} + +void Tanh(int32_t cell_state_scale_power, const RuntimeShape& input_data_shape, + float* input_data, const RuntimeShape& output_data_shape, + float* output_data) { + reference_ops::Tanh(input_data_shape, input_data, output_data_shape, + output_data); +} + +// Input and output have the same shape in LSTM +void Mul(const RuntimeShape& shape, const ArithmeticParams& params, + const int16_t* input1_data, const int16_t* input2_data, + int8_t* output_data) { + return reference_integer_ops::MulElementwise( + shape.FlatSize(), params, input1_data, input2_data, output_data); +} + +// Input and output have the same shape in LSTM +void Mul(const RuntimeShape& shape, const ArithmeticParams& params, + const int16_t* input1_data, const int16_t* input2_data, + int16_t* output_data) { + return reference_integer_ops::MulElementwise( + shape.FlatSize(), params, input1_data, input2_data, output_data); +} + +// Input and output have the same shape in LSTM +void Mul(const RuntimeShape& shape, const ArithmeticParams& params, + const float* input1_data, const float* input2_data, + float* output_data) { + return reference_ops::Mul(params, shape, input1_data, shape, input2_data, + shape, output_data); +} + +void FullyConnected(const FullyConnectedParams& params, + const RuntimeShape& input_shape, const int8_t* input_data, + const RuntimeShape& filter_shape, const int8_t* filter_data, + const RuntimeShape& bias_shape, const int32_t* bias_data, + const RuntimeShape& output_shape, int16_t* output_data) { + return tflite::reference_integer_ops::FullyConnected( + params, input_shape, input_data, filter_shape, filter_data, bias_shape, + bias_data, output_shape, output_data); +} + +void FullyConnected(const FullyConnectedParams& params, + const RuntimeShape& input_shape, const int16_t* input_data, + const RuntimeShape& filter_shape, const int8_t* filter_data, + const RuntimeShape& bias_shape, const int64_t* bias_data, + const RuntimeShape& output_shape, int16_t* output_data) { + return tflite::reference_integer_ops::FullyConnected( + params, input_shape, input_data, filter_shape, filter_data, bias_shape, + bias_data, output_shape, output_data); +} + +void FullyConnected(const FullyConnectedParams& params, + const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& filter_shape, const float* filter_data, + const RuntimeShape& bias_shape, const float* bias_data, + const RuntimeShape& output_shape, float* output_data) { + return tflite::reference_ops::FullyConnected( + params, input_shape, input_data, filter_shape, filter_data, bias_shape, + bias_data, output_shape, output_data); +} + +void Clipping(const int v_size, const CellStateInfo& cell_state_info, + int16_t* vector) { + for (int i = 0; i < v_size; i++) { + vector[i] = + std::max(std::min(cell_state_info.quantized_cell_clip, vector[i]), + static_cast(-cell_state_info.quantized_cell_clip)); + } +} + +void Clipping(const int v_size, const CellStateInfo& cell_state_info, + float* vector) { + for (int i = 0; i < v_size; i++) { + vector[i] = std::max(std::min(cell_state_info.cell_clip, vector[i]), + -cell_state_info.cell_clip); + } +} + +// Increment the data offset so the sigle time step invocation call can access +// the corresponding input/output tensor data at the time step +void LstmStepManager::UpdateTime() { + current_time_ += 1; + TFLITE_DCHECK_LE(current_time_, size_info_.time_steps); + // default as one batch per inference + int input_step = size_info_.input_dimension; + int output_step = size_info_.state_dimension; + // time major: batch inference + if (size_info_.time_major) { + input_step = input_step * size_info_.batch_size; + output_step = output_step * size_info_.batch_size; + } + + input_offset_ += input_step; + output_offset_ += output_step; +} + +// Increment the data offset so the sigle time step invocation call can access +// the corresponding hidden/cell state tensor data at the time step (for single +// batch inference only) +void LstmStepManager::UpdateBatch() { + current_batch_ += 1; + TFLITE_DCHECK_LE(current_batch_, size_info_.batch_size); + // batch inference for time major: no action needed + if (size_info_.time_major) { + return; + } + // otherwise: singe batch inference, go to the next batch + hidden_state_offset_ += size_info_.state_dimension; + cell_state_offset_ += size_info_.state_dimension; +} + +// Input shape for each single time LSTM invocation. +// Multi-batch for time_major input +RuntimeShape LstmStepManager::InputShape() const { + int batch_size = 1; + if (size_info_.time_major) { + batch_size = size_info_.batch_size; + } + const int dims[2] = {batch_size, size_info_.input_dimension}; + const int32_t* dims_data = reinterpret_cast(dims); + return RuntimeShape(2, dims_data); +} + +// State shape (both hidden and cell) for each single time LSTM invocation. +// Multi-batch for time_major input +RuntimeShape LstmStepManager::StateShape() const { + int batch_size = 1; + if (size_info_.time_major) { + batch_size = size_info_.batch_size; + } + const int dims[2] = {batch_size, size_info_.state_dimension}; + const int32_t* dims_data = reinterpret_cast(dims); + return RuntimeShape(2, dims_data); +} + +} // namespace lstm_internal +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.h new file mode 100644 index 0000000..fcdbfe8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.h @@ -0,0 +1,417 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// Functions to perform integer evaulation for standard LSTM (e.g., defined in +// the keras lstm layer, no peephole etc.). Currently used by the 16 bits +// activation case only + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_LSTM_EVAL_GENERAL_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_LSTM_EVAL_GENERAL_H_ +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_shared.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +// Since LSTM includes multiple intermediate stages, introducing the internal +// namespace to expose them for testing +namespace lstm_internal { + +void Sigmoid(const RuntimeShape& data_shape, int16_t* data); + +void Sigmoid(const RuntimeShape& data_shape, float* data); + +void Tanh(int32_t cell_state_scale_power, const RuntimeShape& input_data_shape, + int16_t* input_data, const RuntimeShape& output_data_shape, + int16_t* output_data); + +void Tanh(int32_t cell_state_scale_power, const RuntimeShape& input_data_shape, + float* input_data, const RuntimeShape& output_data_shape, + float* output_data); + +void Mul(const RuntimeShape& shape, const ArithmeticParams& params, + const int16_t* input1_data, const int16_t* input2_data, + int8_t* output_data); + +void Mul(const RuntimeShape& shape, const ArithmeticParams& params, + const int16_t* input1_data, const int16_t* input2_data, + int16_t* output_data); + +void Mul(const RuntimeShape& shape, const ArithmeticParams& params, + const float* input1_data, const float* input2_data, + float* output_data); + +void FullyConnected(const FullyConnectedParams& params, + const RuntimeShape& input_shape, const int8_t* input_data, + const RuntimeShape& filter_shape, const int8_t* filter_data, + const RuntimeShape& bias_shape, const int32_t* bias_data, + const RuntimeShape& output_shape, int16_t* output_data); + +void FullyConnected(const FullyConnectedParams& params, + const RuntimeShape& input_shape, const int16_t* input_data, + const RuntimeShape& filter_shape, const int8_t* filter_data, + const RuntimeShape& bias_shape, const int64_t* bias_data, + const RuntimeShape& output_shape, int16_t* output_data); + +void FullyConnected(const FullyConnectedParams& params, + const RuntimeShape& input_shape, const float* input_data, + const RuntimeShape& filter_shape, const float* filter_data, + const RuntimeShape& bias_shape, const float* bias_data, + const RuntimeShape& output_shape, float* output_data); + +void AddElementWise(const int16_t* input_1, const int16_t* input_2, int n_batch, + int n_input, int16_t* output); + +void AddElementWise(const float* input_1, const float* input_2, int n_batch, + int n_input, float* output); + +void Clipping(const int v_size, const CellStateInfo& cell_state_info, + int16_t* vector); + +void Clipping(const int v_size, const CellStateInfo& cell_state_info, + float* vector); + +// Manages the slice position (offset), slice length (sliced tensor shape), +// and update rules for input/output/hidden state/cell state tensors at each +// time step. +class LstmStepManager { + public: + LstmStepManager() = delete; + // Does not take any ownership, and all pointers must refer to valid objects + // that outlive the one constructed. + explicit LstmStepManager(const LstmSizeInfo* size_info) + : size_info_(*size_info) {} + + void UpdateTime(); + void UpdateBatch(); + + void ResetTime() { current_time_ = 0; } + RuntimeShape InputShape() const; + RuntimeShape StateShape() const; + + int InputOffset() const { return input_offset_; } + int OutputOffset() const { return output_offset_; } + int HiddenStateOffset() const { return hidden_state_offset_; } + int CellStateOffset() const { return cell_state_offset_; } + + private: + int current_time_ = 0; + int current_batch_ = 0; + int input_offset_ = 0; + int output_offset_ = 0; + int hidden_state_offset_ = 0; + int cell_state_offset_ = 0; + // Sizeinfo is from LstmOpData, which reside in the memory arena + // (guarante to outlast LSTMStepManager, which reside in stack) + const LstmSizeInfo& size_info_; +}; + +// Calculates a single LSTM gate. +// Implements the following formula: +// gate = activate(FC(input) + FC(recurrent)) +// Activation is sigmoid except for the "cell" gate (configurable, usually tanh) +template +void CalculateLstmGate( + const LstmStepManager& step_info, const GateParameters& gate_params, + // Input FC + const TfLiteEvalTensor* input, const TfLiteEvalTensor* input_weight, + const TfLiteEvalTensor* input_bias, + // Recurrent FC + const TfLiteEvalTensor* recurrent, const TfLiteEvalTensor* recurrent_weight, + const TfLiteEvalTensor* recurrent_bias, + // Output + CellType* gate_output, + // Scratch arrays + CellType* fc_output_buffer, const TfLiteFusedActivation activation) { + const auto gate_output_shape = step_info.StateShape(); + // Check offset validity to avoid memory overflow + TFLITE_DCHECK_LE(step_info.InputOffset() + step_info.InputShape().FlatSize(), + tflite::micro::GetTensorShape(input).FlatSize()); + TFLITE_DCHECK_LE( + step_info.HiddenStateOffset() + step_info.StateShape().FlatSize(), + tflite::micro::GetTensorShape(recurrent).FlatSize()); + + // Input FC + FullyConnected(gate_params.input_fc_params, step_info.InputShape(), + tflite::micro::GetTensorData(input) + + step_info.InputOffset(), + micro::GetTensorShape(input_weight), + tflite::micro::GetTensorData(input_weight), + tflite::micro::GetTensorShape(input_bias), + tflite::micro::GetOptionalTensorData(input_bias), + gate_output_shape, gate_output); + + // Recurrent FC + FullyConnected(gate_params.recurrent_fc_params, step_info.StateShape(), + tflite::micro::GetTensorData(recurrent) + + step_info.HiddenStateOffset(), + tflite::micro::GetTensorShape(recurrent_weight), + tflite::micro::GetTensorData(recurrent_weight), + tflite::micro::GetTensorShape(recurrent_bias), + tflite::micro::GetOptionalTensorData(recurrent_bias), + gate_output_shape, fc_output_buffer); + + AddElementWise(gate_output, fc_output_buffer, + /*n_batch=*/gate_output_shape.DimsData()[0], + /*n_state=*/gate_output_shape.DimsData()[1], gate_output); + // Apply activation + switch (activation) { + case kTfLiteActSigmoid: + Sigmoid(gate_output_shape, gate_output); + break; + case kTfLiteActTanh: { + // Set the scale power to -12 to avoid shift + Tanh(/*cell_state_scale_power=*/-12, gate_output_shape, gate_output, + gate_output_shape, gate_output); + } break; + default: + // Only Sigmoid or Tanh is used. + TFLITE_ASSERT_FALSE; + } +} + +// Update the cell state using the output from the forget gate, input gate, and +// cell gate Formula: updated_cell_state = forget_gate_output*cell_state + +// input_gate_output * cell_gate_output, where * denotes element wise +// multiplication +template +void UpdateLstmCell(const LstmStepManager& step_info, + TfLiteEvalTensor* cell_state, + // Gate outputs + CellType* forget_gate_output, + const CellType* input_gate_output, + const CellType* cell_gate_output, + // Mul parameters + const ArithmeticParams& forget_cell_mul_params, + const ArithmeticParams& input_mul_params, + const CellStateInfo& cell_state_info, CellType* buffer) { + // Check offset validity to avoid memory overflow + TFLITE_DCHECK_LE( + step_info.CellStateOffset() + step_info.StateShape().FlatSize(), + tflite::micro::GetTensorShape(cell_state).FlatSize()); + + auto cell_state_shape = step_info.StateShape(); + // Forget Gate x Cell State + Mul(cell_state_shape, forget_cell_mul_params, forget_gate_output, + tflite::micro::GetTensorData(cell_state) + + step_info.CellStateOffset(), + tflite::micro::GetTensorData(cell_state) + + step_info.CellStateOffset()); + // Input Gate x Cell Gate + Mul(cell_state_shape, input_mul_params, input_gate_output, cell_gate_output, + buffer); + + // Update the cell state + AddElementWise(tflite::micro::GetTensorData(cell_state) + + step_info.CellStateOffset(), + buffer, + /*n_batch=*/cell_state_shape.DimsData()[0], + /*n_state=*/cell_state_shape.DimsData()[1], + tflite::micro::GetTensorData(cell_state) + + step_info.CellStateOffset()); + + if (cell_state_info.cell_clip > 0) { + Clipping(cell_state_shape.FlatSize(), cell_state_info, + tflite::micro::GetTensorData(cell_state) + + step_info.CellStateOffset()); + } +} + +// Update the hidden state of the LSTM kernel using the following formula: +// updated_hidden_state = Tanh(updated_cell_state) * output_gate_output, * means +// element wise multiplication +template +void UpdateLstmHidden(const LstmStepManager& step_info, + TfLiteEvalTensor* cell_state, + TfLiteEvalTensor* hidden_state, + const CellType* output_gate_output, + const ArithmeticParams& mul_params, + int32_t cell_state_scale_power, CellType* buffer) { + // Check offset validity to avoid memory overflow + TFLITE_DCHECK_LE( + step_info.CellStateOffset() + step_info.StateShape().FlatSize(), + tflite::micro::GetTensorShape(cell_state).FlatSize()); + TFLITE_DCHECK_LE( + step_info.HiddenStateOffset() + step_info.StateShape().FlatSize(), + tflite::micro::GetTensorShape(hidden_state).FlatSize()); + + auto cell_state_shape = step_info.StateShape(); + CellType* cell_state_data = + tflite::micro::GetTensorData(cell_state) + + step_info.CellStateOffset(); + // Tanh(cell_state) + Tanh(cell_state_scale_power, cell_state_shape, cell_state_data, + cell_state_shape, buffer); + // Update the hidden state + Mul(cell_state_shape, mul_params, buffer, output_gate_output, + tflite::micro::GetTensorData(hidden_state) + + step_info.HiddenStateOffset()); +} + +template +void LstmStep(const LstmStepManager& step_info, const OpDataLSTM& op_data, + LSTMKernelContents& kernel_content, + LSTMBuffers& buffers) { + /*Step1: Calculate gate outputs to prepare cell state update*/ + CellType* gate_internal_buffer = buffers.buffer3; + CellType* forget_gate_output = buffers.buffer0; + CalculateLstmGate( + step_info, op_data.forget_gate_parameters, + // Input FC + kernel_content.GetInternalTensor(tflite::kLstmInputTensor), + kernel_content.GetInternalTensor(tflite::kLstmInputToForgetWeightsTensor), + kernel_content.GetInternalTensor(tflite::kLstmForgetGateBiasTensor), + // Recurrent FC + kernel_content.HiddenStateTensor(), + kernel_content.GetInternalTensor( + tflite::kLstmRecurrentToForgetWeightsTensor), + /*recurrent_bias*/ nullptr, + // Output + forget_gate_output, + // Scratch arrays + gate_internal_buffer, kTfLiteActSigmoid); + + // Input Gate calculation; + CellType* input_gate_output = buffers.buffer1; + CalculateLstmGate( + step_info, op_data.input_gate_parameters, + // Input FC + kernel_content.GetInternalTensor(tflite::kLstmInputTensor), + kernel_content.GetInternalTensor(tflite::kLstmInputToInputWeightsTensor), + kernel_content.GetInternalTensor(tflite::kLstmInputGateBiasTensor), + // Recurrent FC + kernel_content.HiddenStateTensor(), + kernel_content.GetInternalTensor( + tflite::kLstmRecurrentToInputWeightsTensor), + /*recurrent_bias*/ nullptr, + // Output + input_gate_output, + // Scratch arrays + gate_internal_buffer, kTfLiteActSigmoid); + + // Cell Gate calculation + CellType* cell_gate_output = buffers.buffer2; + CalculateLstmGate( + step_info, op_data.cell_gate_parameters, + // Input FC + kernel_content.GetInternalTensor(tflite::kLstmInputTensor), + kernel_content.GetInternalTensor(tflite::kLstmInputToCellWeightsTensor), + kernel_content.GetInternalTensor(tflite::kLstmCellGateBiasTensor), + // Recurrent FC + kernel_content.HiddenStateTensor(), + kernel_content.GetInternalTensor( + tflite::kLstmRecurrentToCellWeightsTensor), + /*recurrent_bias*/ nullptr, + // Output + cell_gate_output, + // Scratch arrays + gate_internal_buffer, op_data.cell_gate_nonlinear_type); + + /*Step2: update the cell state */ + const InterGateParameters& inter_gate_params = op_data.inter_gate_parameters; + CellType* updated_input_buffer = buffers.buffer1; // reuse buffer + + UpdateLstmCell(step_info, kernel_content.CellStateTensor(), + forget_gate_output, input_gate_output, + cell_gate_output, + inter_gate_params.forget_cell_mul_params, + inter_gate_params.input_mul_params, + op_data.cell_state_info, updated_input_buffer); + + /*Step3: update the hidden state */ + CellType* output_gate_output = buffers.buffer1; // reuse buffer + CalculateLstmGate( + step_info, op_data.output_gate_parameters, + // Input FC + kernel_content.GetInternalTensor(tflite::kLstmInputTensor), + kernel_content.GetInternalTensor(tflite::kLstmInputToOutputWeightsTensor), + kernel_content.GetInternalTensor(tflite::kLstmOutputGateBiasTensor), + // Recurrent FC + kernel_content.HiddenStateTensor(), + kernel_content.GetInternalTensor( + tflite::kLstmRecurrentToOutputWeightsTensor), + /*recurrent_bias*/ nullptr, + // Output + output_gate_output, + // Scratch arrays + gate_internal_buffer, kTfLiteActSigmoid); + + CellType* tanh_activated_cell_buffer = buffers.buffer0; // reuse buffer + tflite::lstm_internal::UpdateLstmHidden( + step_info, kernel_content.CellStateTensor(), + kernel_content.HiddenStateTensor(), output_gate_output, + inter_gate_params.output_mul_params, + op_data.cell_state_info.cell_state_scale_power, + tanh_activated_cell_buffer); + + /*Step4: copy the update the hidden state to output*/ + // Check offset validity to avoid memory overflow + TFLITE_DCHECK_LE( + step_info.OutputOffset() + step_info.StateShape().FlatSize(), + tflite::micro::GetTensorShape(kernel_content.output_tensor).FlatSize()); + // record the output (from the updated hidden state) + ActivationType* output_ptr = tflite::micro::GetTensorData( + kernel_content.output_tensor); + const auto* hidden_state = kernel_content.HiddenStateTensor(); + std::memcpy(output_ptr + step_info.OutputOffset(), + tflite::micro::GetTensorData(hidden_state) + + step_info.HiddenStateOffset(), + step_info.StateShape().FlatSize() * sizeof(ActivationType)); +} + +} // namespace lstm_internal + +// Evaulate the LSTM kernel with (potential) multi-steps and multi-batch input +// Since +template +TfLiteStatus EvalLstm(const OpDataLSTM& op_data, + LSTMKernelContents& kernel_content, + LSTMBuffers& buffers) { + lstm_internal::LstmStepManager step_info(&op_data.size_info); + const auto& size_info = op_data.size_info; + // time is the first dimention, enable batch computation + if (size_info.time_major) { + for (int t = 0; t < size_info.time_steps; t++) { + lstm_internal::LstmStep( + step_info, op_data, kernel_content, buffers); + // prepare for the next time step + step_info.UpdateTime(); + } + } else { + // batch first, unable to size the input data. single batch inference + for (int b = 0; b < size_info.batch_size; b++) { + for (int t = 0; t < size_info.time_steps; t++) { + lstm_internal::LstmStep( + step_info, op_data, kernel_content, buffers); + // prepare for the next time step + step_info.UpdateTime(); + } + // prepare for the next batch + step_info.UpdateBatch(); + step_info.ResetTime(); + } + } + return kTfLiteOk; +} +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_LSTM_EVAL_16ACT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval_test.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval_test.h new file mode 100644 index 0000000..cfaec49 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval_test.h @@ -0,0 +1,817 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_LSTM_EVAL_TEST_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_LSTM_EVAL_TEST_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/testdata/lstm_test_data.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/testing/micro_test.h" + +namespace tflite { +namespace testing { + +/*Helper Functions (mainly about mimicking the kernel preparation)*/ + +// Create fully connected parameters using quantization settings of input and +// weight tensors. +// Since TfLiteContext is not available during the kernel test, here we mimic +// (put into stack memory) CalculateOpDataFullyConnected in +// tensorflow/lite/micro/kernels/fully_connected_common.cc +template +tflite::FullyConnectedParams CreateFCParams( + const TensorQuantizationParameters& input_quant_params, + const TensorQuantizationParameters& weight_quant_params, + const float nonlinear_activation_input_scale) { + OpDataFullyConnected data; + const double input_product_scale = + input_quant_params.scale * weight_quant_params.scale; + double effective_scale = + input_product_scale / + static_cast(nonlinear_activation_input_scale); + + QuantizeMultiplier(effective_scale, &data.output_multiplier, + &data.output_shift); + + data.input_zero_point = input_quant_params.zero_point; + + data.filter_zero_point = 0; // symmetrically quantized + data.output_zero_point = 0; // symmetrically quantized + + data.output_activation_min = std::numeric_limits::min(); + data.output_activation_max = std::numeric_limits::max(); + + return tflite::FullyConnectedParamsQuantized(data); +} + +inline tflite::FullyConnectedParams CreateFCParamsFloat() { + FullyConnectedParams op_params; + CalculateActivationRange(kTfLiteActNone, &op_params.float_activation_min, + &op_params.float_activation_max); + return op_params; +} + +// Wrapper function to create gate parameters for the four internal LSTM gates +template +tflite::GateParameters CreateGateParams( + const TensorQuantizationParameters& input_quant_params, + const TensorQuantizationParameters& hidden_state_quant_params, + const GateQuantizationParameters& gate_quantization_settings, + const float nonlinear_activation_input_scale) { + tflite::GateParameters gate_params = {}; + gate_params.input_fc_params = CreateFCParams( + input_quant_params, gate_quantization_settings.activation_weight, + nonlinear_activation_input_scale); + gate_params.recurrent_fc_params = CreateFCParams( + hidden_state_quant_params, gate_quantization_settings.recurrent_weight, + nonlinear_activation_input_scale); + return gate_params; +} + +inline tflite::GateParameters CreateGateParamsFloat() { + tflite::GateParameters gate_params = {}; + gate_params.input_fc_params = CreateFCParamsFloat(); + gate_params.recurrent_fc_params = CreateFCParamsFloat(); + return gate_params; +} +// Create parameters for element wise multiplication that happens in a) cell +// state update ; b) hidden state update +// Note that all the output of gates are symmetrically quantized so only scales +// are required for input. However, during the hidden state update phase, the +// output is the updated hidden state, which is asymmetrically quantized. Thus +// output may require zero point +template +tflite::ArithmeticParams CreateInterGateMulParams(const float input1_scale, + const float input2_scale, + const float output_scale, + const int output_zp = 0) { + tflite::ArithmeticParams op_params = {}; + op_params.quantized_activation_min = std::numeric_limits::min(); + op_params.quantized_activation_max = std::numeric_limits::max(); + op_params.input1_offset = 0; + op_params.input2_offset = 0; + op_params.output_offset = output_zp; + + const double input_product_scale = + static_cast(input1_scale) * static_cast(input2_scale); + double effective_scale = + input_product_scale / static_cast(output_scale); + + QuantizeMultiplier(effective_scale, &op_params.output_multiplier, + &op_params.output_shift); + return op_params; +} + +inline tflite::ArithmeticParams CreateInterGateMulParamsFloat() { + tflite::ArithmeticParams op_params = {}; + CalculateActivationRange(kTfLiteActNone, &op_params.float_activation_min, + &op_params.float_activation_max); + return op_params; +} + +// Create the additional information about the cell state, which include: +// cell_state_scale_power: used in integer nonlinear function (e.g., tanh) +// quantized_cell_clip: quantized cell clip range +CellStateInfo CreateLstmCellStateInfo(const float cell_state_scale, + const float cell_clip) { + CellStateInfo cell_state_info; + // cell_state_scale_power: 2^-cell_state_scale_power = cell state scale + int buffer; + tflite::CheckedLog2(cell_state_scale, &buffer); + cell_state_info.cell_state_scale_power = buffer; + // Cell state specifics + cell_state_info.cell_clip = cell_clip; + cell_state_info.quantized_cell_clip = static_cast( + std::min(std::max(static_cast(cell_clip) / + static_cast(cell_state_scale), + -32768.0), + 32767.0)); + return cell_state_info; +} + +// Create LSTMKernelContents from LstmNodeContent by copying TfLiteEvalTensor +// pointers +template +LSTMKernelContents CreateLSTMKernelContent( + LstmNodeContent& + node_contents) { + LSTMKernelContents kernel_content; + // Point to correct tensors + kernel_content.internal_tensors[kLstmInputTensor] = + node_contents.GetEvalTensor(kLstmInputTensor); + kernel_content.internal_tensors[kLstmInputToInputWeightsTensor] = + node_contents.GetEvalTensor(kLstmInputToInputWeightsTensor); + kernel_content.internal_tensors[kLstmInputToForgetWeightsTensor] = + node_contents.GetEvalTensor(kLstmInputToForgetWeightsTensor); + kernel_content.internal_tensors[kLstmInputToCellWeightsTensor] = + node_contents.GetEvalTensor(kLstmInputToCellWeightsTensor); + kernel_content.internal_tensors[kLstmInputToOutputWeightsTensor] = + node_contents.GetEvalTensor(kLstmInputToOutputWeightsTensor); + kernel_content.internal_tensors[kLstmRecurrentToInputWeightsTensor] = + node_contents.GetEvalTensor(kLstmRecurrentToInputWeightsTensor); + kernel_content.internal_tensors[kLstmRecurrentToForgetWeightsTensor] = + node_contents.GetEvalTensor(kLstmRecurrentToForgetWeightsTensor); + kernel_content.internal_tensors[kLstmRecurrentToCellWeightsTensor] = + node_contents.GetEvalTensor(kLstmRecurrentToCellWeightsTensor); + kernel_content.internal_tensors[kLstmRecurrentToOutputWeightsTensor] = + node_contents.GetEvalTensor(kLstmRecurrentToOutputWeightsTensor); + kernel_content.internal_tensors[kLstmInputGateBiasTensor] = + node_contents.GetEvalTensor(kLstmInputGateBiasTensor); + kernel_content.internal_tensors[kLstmForgetGateBiasTensor] = + node_contents.GetEvalTensor(kLstmForgetGateBiasTensor); + kernel_content.internal_tensors[kLstmCellGateBiasTensor] = + node_contents.GetEvalTensor(kLstmCellGateBiasTensor); + kernel_content.internal_tensors[kLstmOutputGateBiasTensor] = + node_contents.GetEvalTensor(kLstmOutputGateBiasTensor); + kernel_content.internal_tensors[kLstmOutputStateTensor] = + node_contents.GetEvalTensor(kLstmOutputStateTensor); + kernel_content.internal_tensors[kLstmOutputGateBiasTensor] = + node_contents.GetEvalTensor(kLstmOutputGateBiasTensor); + kernel_content.internal_tensors[kLstmCellStateTensor] = + node_contents.GetEvalTensor(kLstmCellStateTensor); + // Not used internal tensors + kernel_content.internal_tensors[kLstmCellToInputWeightsTensor] = nullptr; + kernel_content.internal_tensors[kLstmCellToForgetWeightsTensor] = nullptr; + kernel_content.internal_tensors[kLstmCellToOutputWeightsTensor] = nullptr; + kernel_content.internal_tensors[kLstmProjectionWeightsTensor] = nullptr; + kernel_content.internal_tensors[kLstmProjectionBiasTensor] = nullptr; + kernel_content.internal_tensors[kLstmInputLayerNormCoefficientsTensor] = + nullptr; + kernel_content.internal_tensors[kLstmForgetLayerNormCoefficientsTensor] = + nullptr; + kernel_content.internal_tensors[kLstmInputLayerNormCoefficientsTensor] = + nullptr; + kernel_content.internal_tensors[kLstmCellLayerNormCoefficientsTensor] = + nullptr; + kernel_content.internal_tensors[kLstmOutputLayerNormCoefficientsTensor] = + nullptr; + // Output tensor + kernel_content.output_tensor = node_contents.OutputEvalTensor(); + return kernel_content; +} + +// Deduce the size information (Batch (B), Time Steps (T), Input dimension (I), +// State dimension (S)) that defines the LSTM using the input and hidden state +// tensor +LstmSizeInfo CreateLstmSizeInfo( + const bool time_major, const TfLiteIntArray* input_tensor_shape, + const TfLiteIntArray* hidden_state_tensor_shape) { + LstmSizeInfo size_info; + size_info.time_major = time_major; + size_info.batch_size = + time_major ? input_tensor_shape->data[1] : input_tensor_shape->data[0]; + size_info.time_steps = + time_major ? input_tensor_shape->data[0] : input_tensor_shape->data[1]; + size_info.input_dimension = input_tensor_shape->data[2]; + size_info.state_dimension = hidden_state_tensor_shape->data[1]; + return size_info; +} + +// Create the LstmOpData using the LstmNodeContent and +// NodeQuantizationParameters (defined in test_data/lstm_test_data) During the +// actual inference phase, OpDataLSTM is created using information from the +// flatbuffer file. The test divide the complete LSTM node information into +// LstmNodeContent and NodeQuantizationParameters for easy construction +// purposes +template +OpDataLSTM CreateLstmOpData( + LstmNodeContent& + node_contents) { + const auto& builtin_data = node_contents.BuiltinData(); + const auto& quantization_settings = node_contents.QuantizationSettings(); + OpDataLSTM op_data; + + op_data.cell_gate_nonlinear_type = builtin_data.activation; + op_data.size_info = + CreateLstmSizeInfo(builtin_data.time_major, + node_contents.GetEvalTensor(kLstmInputTensor)->dims, + node_contents.HiddenStateEvalTensor()->dims); + + op_data.cell_state_info = CreateLstmCellStateInfo( + quantization_settings.cell_state.scale, builtin_data.cell_clip); + + // Gate Parameters + op_data.forget_gate_parameters = CreateGateParams( + quantization_settings.input, quantization_settings.hidden_state, + quantization_settings.forget_gate, + quantization_settings.nonlinear_activation_input_scale); + op_data.input_gate_parameters = CreateGateParams( + quantization_settings.input, quantization_settings.hidden_state, + quantization_settings.input_gate, + quantization_settings.nonlinear_activation_input_scale); + op_data.cell_gate_parameters = CreateGateParams( + quantization_settings.input, quantization_settings.hidden_state, + quantization_settings.cell_gate, + quantization_settings.nonlinear_activation_input_scale); + op_data.output_gate_parameters = CreateGateParams( + quantization_settings.input, quantization_settings.hidden_state, + quantization_settings.output_gate, + quantization_settings.nonlinear_activation_input_scale); + // Inter gate multiplication parameters + op_data.inter_gate_parameters.forget_cell_mul_params = + CreateInterGateMulParams( + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.cell_state.scale, + quantization_settings.cell_state.scale); + op_data.inter_gate_parameters.input_mul_params = + CreateInterGateMulParams( + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.cell_state.scale); + op_data.inter_gate_parameters.output_mul_params = + CreateInterGateMulParams( + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.hidden_state.scale, + quantization_settings.hidden_state.zero_point); + return op_data; +} + +template +OpDataLSTM CreateLstmOpDataFloat( + LstmNodeContent& node_contents) { + const auto& builtin_data = node_contents.BuiltinData(); + OpDataLSTM op_data; + + op_data.cell_gate_nonlinear_type = builtin_data.activation; + op_data.size_info = + CreateLstmSizeInfo(builtin_data.time_major, + node_contents.GetEvalTensor(kLstmInputTensor)->dims, + node_contents.HiddenStateEvalTensor()->dims); + op_data.cell_state_info.cell_clip = builtin_data.cell_clip; + op_data.cell_state_info.quantized_cell_clip = 0; // No quantization + op_data.cell_state_info.cell_state_scale_power = 0; // No quantization + + // Gate Parameters + op_data.forget_gate_parameters = CreateGateParamsFloat(); + op_data.input_gate_parameters = CreateGateParamsFloat(); + op_data.cell_gate_parameters = CreateGateParamsFloat(); + op_data.output_gate_parameters = CreateGateParamsFloat(); + // Inter gate multiplication parameters + op_data.inter_gate_parameters.forget_cell_mul_params = + CreateInterGateMulParamsFloat(); + op_data.inter_gate_parameters.input_mul_params = + CreateInterGateMulParamsFloat(); + op_data.inter_gate_parameters.output_mul_params = + CreateInterGateMulParamsFloat(); + return op_data; +} + +/*Test Functions Below Here*/ +template +void ValidateResultGoldens(const T* golden, const T* output_data, + const int output_len, const float tolerance) { + for (int i = 0; i < output_len; ++i) { + TF_LITE_MICRO_EXPECT_NEAR(golden[i], output_data[i], tolerance); + } +} + +template +void TestCalculateLstmGateFloat(const TfLiteEvalTensor* input, + const TfLiteEvalTensor* input_weight, + const TfLiteEvalTensor* input_bias, + // Recurrent FC + const TfLiteEvalTensor* recurrent, + const TfLiteEvalTensor* recurrent_weight, + const TfLiteEvalTensor* recurrent_bias, + // Result comparison + TfLiteFusedActivation nonlinear_type, + const float* expected_vals, float tolerance) { + float gate_output[batch_size * state_dimension] = {}; + float fc_output_buffer[batch_size * state_dimension] = {}; + + tflite::GateParameters gate_params = CreateGateParamsFloat(); + + // Create step information: only one time step, no need to update + auto size_info = tflite::testing::CreateLstmSizeInfo( + /*time_major*/ false, input->dims, recurrent->dims); + // revise time_major = true to enable batch inference + size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&size_info); + + tflite::lstm_internal::CalculateLstmGate( + step_info, gate_params, + // Input FC + input, input_weight, input_bias, + // Recurrent FC + recurrent, recurrent_weight, recurrent_bias, + // Output + gate_output, + // Scratch arrays + fc_output_buffer, nonlinear_type); + + ValidateResultGoldens(expected_vals, gate_output, + batch_size * state_dimension, tolerance); +} + +template +void TestCalculateLstmGateInteger( + const TfLiteEvalTensor* input, const TfLiteEvalTensor* input_weight, + const TfLiteEvalTensor* input_bias, + // Recurrent FC + const TfLiteEvalTensor* recurrent, const TfLiteEvalTensor* recurrent_weight, + const TfLiteEvalTensor* recurrent_bias, + // Quantization settings + const NodeQuantizationParameters& node_quantization_settings, + const GateQuantizationParameters& gate_quantization_settings, + // Result comparison + TfLiteFusedActivation nonlinear_type, const float* expected_vals, + float tolerance) { + CellType gate_output[batch_size * state_dimension] = {}; + CellType fc_output_buffer[batch_size * state_dimension] = {}; + + tflite::GateParameters gate_params = CreateGateParams( + node_quantization_settings.input, node_quantization_settings.hidden_state, + gate_quantization_settings, + node_quantization_settings.nonlinear_activation_input_scale); + + // Create step information: only one time step, no need to update + auto size_info = tflite::testing::CreateLstmSizeInfo( + /*time_major*/ false, input->dims, recurrent->dims); + // revise time_major = true to enable batch inference + size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&size_info); + + // only int8 weight is supported now + tflite::lstm_internal::CalculateLstmGate( + step_info, gate_params, + // Input FC + input, input_weight, input_bias, + // Recurrent FC + recurrent, recurrent_weight, recurrent_bias, + // Output + gate_output, + // Scratch arrays + fc_output_buffer, nonlinear_type); + + float gate_output_float[batch_size * state_dimension] = {}; + Dequantize(gate_output, batch_size * state_dimension, + node_quantization_settings.nonlinear_activation_output_scale, 0, + gate_output_float); + + ValidateResultGoldens(expected_vals, gate_output_float, + batch_size * state_dimension, tolerance); +} + +template +void TestUpdateLstmCellFloat( + const GateOutputCheckData& gate_output_data, + LstmNodeContent& node_content, + const float tolerance) { + float buffer[batch_size * state_dimension] = {}; + + auto forget_cell_mul_params = CreateInterGateMulParamsFloat(); + auto input_mul_params = CreateInterGateMulParamsFloat(); + + auto cell_state = node_content.CellStateEvalTensor(); + // Create step information: only one time step, no need to update + auto size_info = tflite::testing::CreateLstmSizeInfo( + /*time_major*/ false, + node_content.GetEvalTensor(tflite::kLstmInputTensor)->dims, + node_content.HiddenStateEvalTensor()->dims); + // revise time_major = true to enable batch inference + size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&size_info); + + // copy the data since it will be updated + float forget_gate[batch_size * state_dimension] = {}; + std::memcpy(forget_gate, gate_output_data.expected_forget_gate_output, + batch_size * state_dimension * sizeof(float)); + + CellStateInfo cell_state_info; + cell_state_info.cell_clip = node_content.BuiltinData().cell_clip; + // Call the function to be tested + tflite::lstm_internal::UpdateLstmCell( + step_info, cell_state, forget_gate, + gate_output_data.expected_input_gate_output, + gate_output_data.expected_cell_gate_output, forget_cell_mul_params, + input_mul_params, cell_state_info, buffer); + + ValidateResultGoldens(gate_output_data.expected_updated_cell, + tflite::micro::GetTensorData(cell_state), + batch_size * state_dimension, tolerance); +} + +template +void TestUpdateLstmCellInteger( + const GateOutputCheckData& gate_output_data, + LstmNodeContent& node_content, + const float tolerance) { + const auto& quantization_settings = node_content.QuantizationSettings(); + CellType quantized_forget_gate[batch_size * state_dimension] = {}; + tflite::Quantize(gate_output_data.expected_forget_gate_output, + quantized_forget_gate, batch_size * state_dimension, + quantization_settings.nonlinear_activation_output_scale, 0); + + CellType quantized_input_gate[batch_size * state_dimension] = {}; + tflite::Quantize(gate_output_data.expected_input_gate_output, + quantized_input_gate, batch_size * state_dimension, + quantization_settings.nonlinear_activation_output_scale, 0); + + CellType quantized_cell_gate[batch_size * state_dimension] = {}; + tflite::Quantize(gate_output_data.expected_cell_gate_output, + quantized_cell_gate, batch_size * state_dimension, + quantization_settings.nonlinear_activation_output_scale, 0); + + CellType buffer[batch_size * state_dimension] = {}; + + auto forget_cell_mul_params = CreateInterGateMulParams( + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.cell_state.scale, + quantization_settings.cell_state.scale); + auto input_mul_params = CreateInterGateMulParams( + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.cell_state.scale); + + auto cell_state_info = + CreateLstmCellStateInfo(quantization_settings.cell_state.scale, + node_content.BuiltinData().cell_clip); + + auto cell_state = node_content.CellStateEvalTensor(); + // Create step information: only one time step, no need to update + auto size_info = tflite::testing::CreateLstmSizeInfo( + /*time_major*/ false, + node_content.GetEvalTensor(tflite::kLstmInputTensor)->dims, + node_content.HiddenStateEvalTensor()->dims); + // revise time_major = true to enable batch inference + size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&size_info); + + // Call the function to be tested + tflite::lstm_internal::UpdateLstmCell( + step_info, cell_state, quantized_forget_gate, quantized_input_gate, + quantized_cell_gate, forget_cell_mul_params, input_mul_params, + cell_state_info, buffer); + + float cell_state_float[batch_size * state_dimension] = {}; + Dequantize(tflite::micro::GetTensorData(cell_state), + batch_size * state_dimension, + quantization_settings.cell_state.scale, + quantization_settings.cell_state.zero_point, cell_state_float); + + ValidateResultGoldens(gate_output_data.expected_updated_cell, + cell_state_float, batch_size * state_dimension, + tolerance); +} + +template +void TestUpdateLstmHiddenFloat( + const GateOutputCheckData& gate_output_data, + LstmNodeContent& node_content, + const float tolerance) { + float buffer[batch_size * state_dimension] = {}; + + auto mul_params = CreateInterGateMulParamsFloat(); + + int32_t cell_state_scale_power = 0; + + // Create step information: only one time step, no need to update + auto size_info = tflite::testing::CreateLstmSizeInfo( + /*time_major*/ false, + node_content.GetEvalTensor(tflite::kLstmInputTensor)->dims, + node_content.HiddenStateEvalTensor()->dims); + // revise time_major = true to enable batch inference + size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&size_info); + + auto cell_state = node_content.CellStateEvalTensor(); + auto hidden_state = node_content.HiddenStateEvalTensor(); + + tflite::lstm_internal::UpdateLstmHidden( + step_info, cell_state, hidden_state, + gate_output_data.expected_output_gate_output, mul_params, + cell_state_scale_power, buffer); + + ValidateResultGoldens(gate_output_data.expected_updated_hidden, + tflite::micro::GetTensorData(hidden_state), + batch_size * state_dimension, tolerance); +} + +template +void TestUpdateLstmHiddenInteger( + const GateOutputCheckData& gate_output_data, + LstmNodeContent& node_content, + const float tolerance) { + const auto& quantization_settings = node_content.QuantizationSettings(); + CellType quantized_output_gate[batch_size * state_dimension] = {}; + tflite::Quantize(gate_output_data.expected_output_gate_output, + quantized_output_gate, batch_size * state_dimension, + quantization_settings.nonlinear_activation_output_scale, 0); + + CellType buffer[batch_size * state_dimension] = {}; + + auto mul_params = CreateInterGateMulParams( + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.nonlinear_activation_output_scale, + quantization_settings.hidden_state.scale, + quantization_settings.hidden_state.zero_point); + + int cell_state_scale_power_buffer; + tflite::CheckedLog2(quantization_settings.cell_state.scale, + &cell_state_scale_power_buffer); + int32_t cell_state_scale_power = cell_state_scale_power_buffer; + + // Create step information: only one time step, no need to update + auto size_info = tflite::testing::CreateLstmSizeInfo( + /*time_major*/ false, + node_content.GetEvalTensor(tflite::kLstmInputTensor)->dims, + node_content.HiddenStateEvalTensor()->dims); + // revise time_major = true to enable batch inference + size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&size_info); + + auto cell_state = node_content.CellStateEvalTensor(); + auto hidden_state = node_content.HiddenStateEvalTensor(); + + tflite::lstm_internal::UpdateLstmHidden( + step_info, cell_state, hidden_state, quantized_output_gate, mul_params, + cell_state_scale_power, buffer); + + float hidden_state_float[batch_size * state_dimension] = {}; + Dequantize(tflite::micro::GetTensorData(hidden_state), + batch_size * state_dimension, + quantization_settings.hidden_state.scale, + quantization_settings.hidden_state.zero_point, hidden_state_float); + + ValidateResultGoldens(gate_output_data.expected_updated_hidden, + hidden_state_float, batch_size * state_dimension, + tolerance); +} + +template +void TestLstmStepFloat( + const GateOutputCheckData& gate_output_data, + const float hidden_state_tolerance, const float cell_state_tolerance, + /*can not be const, state will be updated*/ + LstmNodeContent& node_contents) { + // Mimicking the kernel preparation phase, node_contents approximate the + LSTMKernelContents kernel_content = CreateLSTMKernelContent(node_contents); + LSTMBuffers buffers; + // Scratch buffers on the stack + float buffer0[batch_size * state_dimension] = {}; + buffers.buffer0 = buffer0; + float buffer1[batch_size * state_dimension] = {}; + buffers.buffer1 = buffer1; + float buffer2[batch_size * state_dimension] = {}; + buffers.buffer2 = buffer2; + float buffer3[batch_size * state_dimension] = {}; + buffers.buffer3 = buffer3; + + OpDataLSTM op_data = CreateLstmOpDataFloat(node_contents); + // set time_major to true to test batch inference + op_data.size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&op_data.size_info); + tflite::lstm_internal::LstmStep( + step_info, op_data, kernel_content, buffers); + + ValidateResultGoldens( + gate_output_data.expected_updated_hidden, + tflite::micro::GetTensorData(kernel_content.HiddenStateTensor()), + batch_size * state_dimension, hidden_state_tolerance); + ValidateResultGoldens( + gate_output_data.expected_updated_cell, + tflite::micro::GetTensorData(kernel_content.CellStateTensor()), + batch_size * state_dimension, cell_state_tolerance); +} + +template +void TestLstmStepInteger( + const GateOutputCheckData& gate_output_data, + const float hidden_state_tolerance, const float cell_state_tolerance, + /*can not be const, state will be updated*/ + LstmNodeContent& + node_contents) { + // Mimicking the kernel preparation phase, node_contents approximate the + LSTMKernelContents kernel_content = CreateLSTMKernelContent(node_contents); + LSTMBuffers buffers; + + // Scratch buffers on the stack + CellType buffer0[batch_size * state_dimension] = {}; + buffers.buffer0 = buffer0; + CellType buffer1[batch_size * state_dimension] = {}; + buffers.buffer1 = buffer1; + CellType buffer2[batch_size * state_dimension] = {}; + buffers.buffer2 = buffer2; + CellType buffer3[batch_size * state_dimension] = {}; + buffers.buffer3 = buffer3; + + OpDataLSTM op_data = CreateLstmOpData(node_contents); + // set time_major to true to test batch inference + op_data.size_info.time_major = true; + tflite::lstm_internal::LstmStepManager step_info(&op_data.size_info); + tflite::lstm_internal::LstmStep(step_info, op_data, kernel_content, + buffers); + + const auto& quantization_settings = node_contents.QuantizationSettings(); + float dequantized_hidden_state[batch_size * state_dimension] = {}; + Dequantize( + tflite::micro::GetTensorData( + kernel_content.HiddenStateTensor()), + batch_size * state_dimension, quantization_settings.hidden_state.scale, + quantization_settings.hidden_state.zero_point, dequantized_hidden_state); + + float dequantized_cell_state[batch_size * state_dimension] = {}; + Dequantize( + tflite::micro::GetTensorData(kernel_content.CellStateTensor()), + batch_size * state_dimension, quantization_settings.cell_state.scale, + quantization_settings.cell_state.zero_point, dequantized_cell_state); + + ValidateResultGoldens(gate_output_data.expected_updated_hidden, + dequantized_hidden_state, batch_size * state_dimension, + hidden_state_tolerance); + ValidateResultGoldens(gate_output_data.expected_updated_cell, + dequantized_cell_state, batch_size * state_dimension, + cell_state_tolerance); +} + +template +void TestEvalLstmFloat( + const LstmEvalCheckData< + batch_size * time_steps * input_dimension, batch_size * state_dimension, + batch_size * state_dimension * time_steps>& eval_check_data, + const float hidden_state_tolerance, const float cell_state_tolerance, + LstmNodeContent& node_contents) { + // Mimicking the kernel preparation phase, node_contents approximate the node + LSTMKernelContents kernel_content = CreateLSTMKernelContent(node_contents); + // Scratch buffers on the stack + LSTMBuffers buffers; + float buffer0[batch_size * state_dimension] = {}; + buffers.buffer0 = buffer0; + float buffer1[batch_size * state_dimension] = {}; + buffers.buffer1 = buffer1; + float buffer2[batch_size * state_dimension] = {}; + buffers.buffer2 = buffer2; + float buffer3[batch_size * state_dimension] = {}; + buffers.buffer3 = buffer3; + + OpDataLSTM op_data = CreateLstmOpDataFloat(node_contents); + + tflite::EvalLstm(op_data, kernel_content, + buffers); + + ValidateResultGoldens(eval_check_data.expected_hidden_state, + node_contents.GetHiddenStateData(), + batch_size * state_dimension, hidden_state_tolerance); + + ValidateResultGoldens(eval_check_data.expected_cell_state, + node_contents.GetCellStateData(), + batch_size * state_dimension, cell_state_tolerance); + + ValidateResultGoldens(eval_check_data.expected_output, + node_contents.GetOutputData(), + batch_size * state_dimension, hidden_state_tolerance); +} + +template +void TestEvalLstmInteger( + const LstmEvalCheckData< + batch_size * time_steps * input_dimension, batch_size * state_dimension, + batch_size * state_dimension * time_steps>& eval_check_data, + const float hidden_state_tolerance, const float cell_state_tolerance, + LstmNodeContent& + node_contents) { + // Mimicking the kernel preparation phase, node_contents approximate the node + LSTMKernelContents kernel_content = CreateLSTMKernelContent(node_contents); + // Scratch buffers on the stack + LSTMBuffers buffers; + CellType buffer0[batch_size * state_dimension] = {}; + buffers.buffer0 = buffer0; + CellType buffer1[batch_size * state_dimension] = {}; + buffers.buffer1 = buffer1; + CellType buffer2[batch_size * state_dimension] = {}; + buffers.buffer2 = buffer2; + CellType buffer3[batch_size * state_dimension] = {}; + buffers.buffer3 = buffer3; + + OpDataLSTM op_data = CreateLstmOpData(node_contents); + + tflite::EvalLstm( + op_data, kernel_content, buffers); + + const auto& quantization_settings = node_contents.QuantizationSettings(); + float dequantized_hidden_state[batch_size * state_dimension] = {}; + Dequantize(node_contents.GetHiddenStateData(), batch_size * state_dimension, + quantization_settings.hidden_state.scale, + quantization_settings.hidden_state.zero_point, + dequantized_hidden_state); + + ValidateResultGoldens(eval_check_data.expected_hidden_state, + dequantized_hidden_state, batch_size * state_dimension, + hidden_state_tolerance); + + float dequantized_cell_state[batch_size * state_dimension] = {}; + Dequantize(node_contents.GetCellStateData(), batch_size * state_dimension, + quantization_settings.cell_state.scale, + quantization_settings.cell_state.zero_point, + dequantized_cell_state); + ValidateResultGoldens(eval_check_data.expected_cell_state, + dequantized_cell_state, batch_size * state_dimension, + cell_state_tolerance); + + float dequantized_output[batch_size * state_dimension * time_steps] = {}; + Dequantize(node_contents.GetOutputData(), + batch_size * state_dimension * time_steps, + quantization_settings.output.scale, + quantization_settings.output.zero_point, dequantized_output); + ValidateResultGoldens(eval_check_data.expected_output, dequantized_output, + batch_size * state_dimension, hidden_state_tolerance); +} + +} // namespace testing +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_LSTM_EVAL_TEST_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_shared.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_shared.h new file mode 100644 index 0000000..54020f6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_shared.h @@ -0,0 +1,150 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_LSTM_SHARED_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_LSTM_SHARED_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +// Input Tensors of size {n_batch, n_input} +constexpr int kLstmInputTensor = 0; + +// Input weight tensors of size: {n_cell, n_input} +constexpr int kLstmInputToInputWeightsTensor = 1; // Optional +constexpr int kLstmInputToForgetWeightsTensor = 2; +constexpr int kLstmInputToCellWeightsTensor = 3; +constexpr int kLstmInputToOutputWeightsTensor = 4; + +// Recurrent weight tensors of size {n_cell, n_output} +constexpr int kLstmRecurrentToInputWeightsTensor = 5; // Optional +constexpr int kLstmRecurrentToForgetWeightsTensor = 6; +constexpr int kLstmRecurrentToCellWeightsTensor = 7; +constexpr int kLstmRecurrentToOutputWeightsTensor = 8; + +// Peephole weights tensors of size {n_cell}, representing a diagonal matrix. +constexpr int kLstmCellToInputWeightsTensor = 9; // Optional +constexpr int kLstmCellToForgetWeightsTensor = 10; // Optional +constexpr int kLstmCellToOutputWeightsTensor = 11; // Optional + +// Gates bias tensors of size {n_cell} +constexpr int kLstmInputGateBiasTensor = 12; // Optional +constexpr int kLstmForgetGateBiasTensor = 13; +constexpr int kLstmCellGateBiasTensor = 14; +constexpr int kLstmOutputGateBiasTensor = 15; + +// Projection weight tensor of size {n_output, n_cell} +constexpr int kLstmProjectionWeightsTensor = 16; // Optional +// Projection bias tensor of size {n_output} +constexpr int kLstmProjectionBiasTensor = 17; // Optional + +// These state tensors are defined as variable tensors, and will be modified by +// this op. +constexpr int kLstmOutputStateTensor = 18; +constexpr int kLstmCellStateTensor = 19; + +// Layer norm coefficient tensors of size {n_cell}, representing a diagonal +// matrix. +constexpr int kLstmInputLayerNormCoefficientsTensor = 20; // Optional +constexpr int kLstmForgetLayerNormCoefficientsTensor = 21; // Optional +constexpr int kLstmCellLayerNormCoefficientsTensor = 22; // Optional +constexpr int kLstmOutputLayerNormCoefficientsTensor = 23; // Optional + +// Output tensors. +constexpr int kLstmOutputTensor = 0; + +// Parameters for the two fully conncted computation inside each gate +struct GateParameters { + FullyConnectedParams input_fc_params; + FullyConnectedParams recurrent_fc_params; +}; + +// Paramaters for the element wise multiplications between gate outputs +struct InterGateParameters { + ArithmeticParams forget_cell_mul_params; + ArithmeticParams input_mul_params; + ArithmeticParams output_mul_params; +}; + +// Size information about the LSTM kernel, which is deduced from tensors stored +// in the flat buffer file. +struct LstmSizeInfo { + bool time_major; + int batch_size; + int time_steps; + int input_dimension; + int state_dimension; +}; + +// Contains information about the cell state tensor +struct CellStateInfo { + float cell_clip; + // clipping range for cell state only 16 bits cell is supported (could be + // generalized through templatation) + int16_t quantized_cell_clip; + // 2^-cell_state_scale_power = cell state scale, required by integer tanh + // computation + int32_t cell_state_scale_power; +}; + +// Contains required computation information for LSTM kernel evaluation. +// Specifically, it includes shape and quantization settings for the LSTM +// internal operations. Formatted to support operations defined in the +// tensorflow/lite/kernels/internal/reference/integer_ops +// Should be constructed during the preparation phase +struct OpDataLSTM { + LstmSizeInfo size_info; + CellStateInfo cell_state_info; + TfLiteFusedActivation cell_gate_nonlinear_type; + GateParameters forget_gate_parameters; + GateParameters input_gate_parameters; + GateParameters cell_gate_parameters; + GateParameters output_gate_parameters; + InterGateParameters inter_gate_parameters; + int buffer_indices[4]; // TFLM only +}; + +// Provide an interface to access the internal tensors and buffers used for LSTM +// invocation. Constructed during the invocation phase +struct LSTMKernelContents { + public: + // Internal tensors, fixed (const). see lstm_shared.h for tensor names + const TfLiteEvalTensor* GetInternalTensor(const int tensor_index) const { + return internal_tensors[tensor_index]; + } + // Variable tensors (will be changed, can not be const) + TfLiteEvalTensor* HiddenStateTensor() { + return internal_tensors[kLstmOutputStateTensor]; + } + TfLiteEvalTensor* CellStateTensor() { + return internal_tensors[kLstmCellStateTensor]; + } + // Node internal tensors with indexes defined at the beginning of the file + TfLiteEvalTensor* internal_tensors[24]; + TfLiteEvalTensor* output_tensor; +}; + +template +struct LSTMBuffers { + // TFLM buffers requires buffer index from LstmOpData. + CellType* buffer0; + CellType* buffer1; + CellType* buffer2; + CellType* buffer3; +}; + +} // namespace tflite +#endif // TENSORFLOW_LITE_MICRO_KERNELS_LSTM_SHARED_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/maximum_minimum.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/maximum_minimum.cpp new file mode 100644 index 0000000..c003e68 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/maximum_minimum.cpp @@ -0,0 +1,122 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/maximum_minimum.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +// This file has a reference implementation of TFMaximum/TFMinimum. +enum KernelType { + kReference, +}; + +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +struct OpContext { + OpContext(TfLiteContext* context, TfLiteNode* node) { + input1 = tflite::micro::GetEvalInput(context, node, kInputTensor1); + input2 = tflite::micro::GetEvalInput(context, node, kInputTensor2); + output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + } + const TfLiteEvalTensor* input1; + const TfLiteEvalTensor* input2; + TfLiteEvalTensor* output; +}; + +struct MaximumOp { + template + static data_type op(data_type el1, data_type el2) { + return el1 > el2 ? el1 : el2; + } +}; + +struct MinimumOp { + template + static data_type op(data_type el1, data_type el2) { + return el1 < el2 ? el1 : el2; + } +}; + +template +void TFLiteOperation(TfLiteContext* context, TfLiteNode* node, + const OpContext& op_context) { + reference_ops::MaximumMinimumBroadcastSlow( + tflite::micro::GetTensorShape(op_context.input1), + tflite::micro::GetTensorData(op_context.input1), + tflite::micro::GetTensorShape(op_context.input2), + tflite::micro::GetTensorData(op_context.input2), + tflite::micro::GetTensorShape(op_context.output), + tflite::micro::GetTensorData(op_context.output), + op_type::template op); +} + +template +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + OpContext op_context(context, node); + + if (kernel_type == kReference) { + switch (op_context.output->type) { + case kTfLiteFloat32: + TFLiteOperation(context, node, op_context); + break; + case kTfLiteInt8: + TFLiteOperation(context, node, op_context); + break; + case kTfLiteInt32: + TFLiteOperation(context, node, op_context); + break; + case kTfLiteInt64: + TFLiteOperation(context, node, op_context); + break; + default: + MicroPrintf("Type %s (%d) is not supported by Maximum/Minimum.", + TfLiteTypeGetName(op_context.output->type), + op_context.output->type); + return kTfLiteError; + } + } else { + MicroPrintf("Kernel type not supported by Maximum/Minimum."); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_MAXIMUM() { + return tflite::micro::RegisterOp(nullptr, nullptr, + Eval); +} + +TfLiteRegistration Register_MINIMUM() { + return tflite::micro::RegisterOp(nullptr, nullptr, + Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h new file mode 100644 index 0000000..fd28a32 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h @@ -0,0 +1,152 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +// Forward declaration of all micro op kernel registration methods. These +// registrations are included with the standard `BuiltinOpResolver`. +// +// This header is particularly useful in cases where only a subset of ops are +// needed. In such cases, the client can selectively add only the registrations +// their model requires, using a custom `(Micro)MutableOpResolver`. Selective +// registration in turn allows the linker to strip unused kernels. + +namespace tflite { + +// TFLM is incrementally moving towards a flat tflite namespace +// (https://abseil.io/tips/130). Any new ops (or cleanup of existing ops should +// have their Register function declarations in the tflite namespace. + +TfLiteRegistration Register_ADD(); +TfLiteRegistration Register_ADD_N(); +TfLiteRegistration Register_ARG_MAX(); +TfLiteRegistration Register_ARG_MIN(); +TfLiteRegistration Register_ASSIGN_VARIABLE(); +TfLiteRegistration Register_AVERAGE_POOL_2D(); +TfLiteRegistration Register_BATCH_MATMUL(); +TfLiteRegistration Register_BATCH_TO_SPACE_ND(); +TfLiteRegistration Register_BROADCAST_ARGS(); +TfLiteRegistration Register_BROADCAST_TO(); +TfLiteRegistration Register_CALL_ONCE(); +TfLiteRegistration Register_CAST(); +TfLiteRegistration Register_CEIL(); +TfLiteRegistration Register_COMPLEX_ABS(); +// TODO(b/160234179): Change custom OPs to also return by value. +TfLiteRegistration* Register_CIRCULAR_BUFFER(); +TfLiteRegistration Register_CONCATENATION(); +TfLiteRegistration Register_CONV_2D(); +TfLiteRegistration Register_CUMSUM(); +TfLiteRegistration Register_DEPTH_TO_SPACE(); +TfLiteRegistration Register_DEPTHWISE_CONV_2D(); +TfLiteRegistration Register_DEQUANTIZE(); +TfLiteRegistration Register_DIV(); +TfLiteRegistration Register_ELU(); +TfLiteRegistration Register_EQUAL(); +TfLiteRegistration* Register_ETHOSU(); +TfLiteRegistration Register_EXP(); +TfLiteRegistration Register_EXPAND_DIMS(); +TfLiteRegistration Register_FILL(); +TfLiteRegistration Register_FLOOR(); +TfLiteRegistration Register_FLOOR_DIV(); +TfLiteRegistration Register_FLOOR_MOD(); +TfLiteRegistration Register_FULLY_CONNECTED(); +#ifndef TF_LITE_STATIC_MEMORY +TfLiteRegistration Register_GATHER(); +#endif // TF_LITE_STATIC_MEMORY +TfLiteRegistration Register_GATHER_ND(); +TfLiteRegistration Register_GREATER(); +TfLiteRegistration Register_GREATER_EQUAL(); +TfLiteRegistration Register_HARD_SWISH(); +TfLiteRegistration Register_IMAG(); +TfLiteRegistration Register_IF(); +TfLiteRegistration Register_L2_POOL_2D(); +TfLiteRegistration Register_LEAKY_RELU(); +TfLiteRegistration Register_LESS(); +TfLiteRegistration Register_LESS_EQUAL(); +TfLiteRegistration Register_LOG_SOFTMAX(); +TfLiteRegistration Register_LOGICAL_AND(); +TfLiteRegistration Register_LOGICAL_OR(); +TfLiteRegistration Register_LOGISTIC(); +TfLiteRegistration Register_MAX_POOL_2D(); +TfLiteRegistration Register_MAXIMUM(); +TfLiteRegistration Register_MEAN(); +TfLiteRegistration Register_MINIMUM(); +TfLiteRegistration Register_MIRROR_PAD(); +TfLiteRegistration Register_MUL(); +TfLiteRegistration Register_NEG(); +TfLiteRegistration Register_NOT_EQUAL(); +TfLiteRegistration Register_PACK(); +TfLiteRegistration Register_PAD(); +TfLiteRegistration Register_PADV2(); +TfLiteRegistration Register_PRELU(); +TfLiteRegistration Register_QUANTIZE(); +TfLiteRegistration Register_READ_VARIABLE(); +TfLiteRegistration Register_REAL(); +TfLiteRegistration Register_REDUCE_MAX(); +TfLiteRegistration Register_REDUCE_MIN(); +TfLiteRegistration Register_RELU(); +TfLiteRegistration Register_RELU6(); +TfLiteRegistration Register_RESIZE_BILINEAR(); +TfLiteRegistration Register_RFFT2D(); +#ifndef TF_LITE_STATIC_MEMORY +TfLiteRegistration Register_SELECT(); +TfLiteRegistration Register_SELECT_V2(); +#endif // TF_LITE_STATIC_MEMORY +TfLiteRegistration Register_SHAPE(); +TfLiteRegistration Register_SLICE(); +TfLiteRegistration Register_SOFTMAX(); +TfLiteRegistration Register_SPACE_TO_BATCH_ND(); +TfLiteRegistration Register_SPACE_TO_DEPTH(); +TfLiteRegistration Register_SPLIT_V(); +TfLiteRegistration Register_SQUARED_DIFFERENCE(); +TfLiteRegistration Register_SQUEEZE(); +TfLiteRegistration Register_STRIDED_SLICE(); +TfLiteRegistration Register_SUB(); +TfLiteRegistration Register_SUM(); +TfLiteRegistration Register_SVDF(); +TfLiteRegistration Register_TRANSPOSE(); +TfLiteRegistration Register_TRANSPOSE_CONV(); +// TODO(b/230666079): resolve conflict with xtensa implementation +TfLiteRegistration Register_UNIDIRECTIONAL_SEQUENCE_LSTM(); +TfLiteRegistration Register_VAR_HANDLE(); +TfLiteRegistration Register_WHILE(); +TfLiteRegistration Register_ZEROS_LIKE(); + +namespace ops { +namespace micro { + +TfLiteRegistration Register_ABS(); +TfLiteRegistration Register_COS(); +TfLiteRegistration Register_LOG(); +TfLiteRegistration Register_LOGICAL_NOT(); +TfLiteRegistration Register_RESHAPE(); +TfLiteRegistration Register_RESIZE_NEAREST_NEIGHBOR(); +TfLiteRegistration Register_ROUND(); +TfLiteRegistration Register_RSQRT(); +TfLiteRegistration Register_SIN(); +TfLiteRegistration Register_SPLIT(); +TfLiteRegistration Register_SQRT(); +TfLiteRegistration Register_SQUARE(); +TfLiteRegistration Register_UNPACK(); +TfLiteRegistration Register_L2_NORMALIZATION(); +TfLiteRegistration Register_TANH(); + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_tensor_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_tensor_utils.cpp new file mode 100644 index 0000000..14be12c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_tensor_utils.cpp @@ -0,0 +1,67 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_tensor_utils.h" + +#include +#include +#include +#include +#include +#include + +#include "edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint.h" // from @gemmlowp +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/cppmath.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" + +namespace tflite { + +// Apply sigmoid to elements of a vector. +void PortableApplySigmoidToVector(const float* vector, int v_size, + float* result) { + for (int v = 0; v < v_size; v++) { + result[v] = 1.0f / (1.0f + std::exp(-vector[v])); + } +} + +void PortableApplyTanhToVector(const float* vector, int v_size, float* result) { + for (int v = 0; v < v_size; v++) { + result[v] = std::tanh(vector[v]); + } +} + +void PortableApplyActivationToVector(const float* vector, int v_size, + TfLiteFusedActivation activation, + float* result) { + switch (activation) { + case kTfLiteActNone: + return; + case kTfLiteActRelu: + return tflite::tensor_utils::ApplyReluToVector(vector, v_size, result); + case kTfLiteActReluN1To1: + return tflite::tensor_utils::ApplyRelu1ToVector(vector, v_size, result); + case kTfLiteActRelu6: + return tflite::tensor_utils::ApplyRelu6ToVector(vector, v_size, result); + case kTfLiteActTanh: + return PortableApplyTanhToVector(vector, v_size, result); + case kTfLiteActSignBit: + return tflite::tensor_utils::ApplySignbitToVector(vector, v_size, result); + case kTfLiteActSigmoid: + return PortableApplySigmoidToVector(vector, v_size, result); + } +} + +} // namespace tflite \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_tensor_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_tensor_utils.h new file mode 100644 index 0000000..fb3d97f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_tensor_utils.h @@ -0,0 +1,56 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This file and the associated .cc file is branched from +// tensorflow/lite/kernels/internal/reference_portable_tensor_utils* +// TFLM needs to create its own because the original files are coupled with +// the tensor_utils module, which we cannot reuse due to its use of the +// Eigen library. + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_MICRO_TENSOR_UTILS_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_MICRO_TENSOR_UTILS_H_ + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor_utils.h" + +#if defined(_MSC_VER) +#define __restrict__ __restrict +#endif + +namespace tflite { + +// Not all backends support CpuBackendContext usage, so forward declare to avoid +// pulling in its implementation. +// TODO(b/230666277): consider removing this since micro does not utilize it +class CpuBackendContext; + +// Apply sigmoid to elements of a vector. +void PortableApplySigmoidToVector(const float* vector, int v_size, + float* result); +// Apply tanh to elements of a vector +void PortableApplyTanhToVector(const float* vector, int v_size, float* result); +// Apply appropriate activation function to elements of a vector. +void PortableApplyActivationToVector(const float* vector, int v_size, + TfLiteFusedActivation activation, + float* result); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_MICRO_TENSOR_UTILS_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mirror_pad.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mirror_pad.cpp new file mode 100644 index 0000000..c409fcc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mirror_pad.cpp @@ -0,0 +1,215 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { +namespace { + +struct OpDataMirrorPad { + int input_dims; + int output_size; + int offset; + int output_dims_num_elements_buffer_index; + int input_dims_num_elements_buffer_index; +}; + +// Helper method that fills the left and right pads. +template +inline void GetPadding(const T* data, int offset, int64_t* left_pad, + int64_t* right_pad) { + *left_pad = static_cast(*(data + offset * 2)); + *right_pad = static_cast(*(data + offset * 2 + 1)); +} + +// Given dimension index and the left/right padding. +// Returns the corresponding dimension in the input array. +inline int GetInputDimension(int padded_dimension, int left_pad, int right_pad, + int input_dim_size, int offset) { + if (padded_dimension < left_pad) { + const int original_ind = left_pad + offset - 1; + return original_ind - (std::min(padded_dimension, original_ind - offset)); + } + padded_dimension -= left_pad; + if (padded_dimension >= input_dim_size) { + padded_dimension -= input_dim_size; + const int original_ind = input_dim_size - (1 + offset); + return original_ind - std::min(padded_dimension, original_ind); + } + return padded_dimension; +} + +// Given and index in output array, returns the index of the value +// in input array. +int GetFlatIndex(int index, int num_dims, + const TfLiteEvalTensor* padding_matrix, + const TfLiteIntArray* input_dims, + int* output_dims_num_elements, int* input_dims_num_elements, + const int offset) { + int flat_index = 0; + int64_t left_pad = 0, right_pad = 0, dimension_index, index_in_input; + + for (int i = 0; i < num_dims; ++i) { + switch (padding_matrix->type) { + case kTfLiteInt32: + GetPadding(padding_matrix->data.i32, i, &left_pad, &right_pad); + break; + case kTfLiteInt64: + GetPadding(padding_matrix->data.i64, i, &left_pad, &right_pad); + break; + default: + break; + } + dimension_index = index / output_dims_num_elements[i]; + + index_in_input = GetInputDimension(dimension_index, left_pad, right_pad, + input_dims->data[i], offset); + + flat_index += index_in_input * (input_dims_num_elements)[i]; + index %= output_dims_num_elements[i]; + } + + return flat_index; +} + +template +void MirrorPad(const TfLiteEvalTensor* padding_matrix, + const TfLiteIntArray* input_dims, int* output_dims_num_elements, + int* input_dims_num_elements, const T* input_data, + T* output_data, const int offset, const int num_dims, + const int output_size) { + for (int i = 0; i < output_size; ++i) { + output_data[i] = input_data[GetFlatIndex( + i, num_dims, padding_matrix, input_dims, output_dims_num_elements, + input_dims_num_elements, offset)]; + } +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TfLiteStatus status = kTfLiteOk; + const OpDataMirrorPad* data = + static_cast(node->user_data); + + const TfLiteEvalTensor* input_tensor = + tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* padding_matrix = + tflite::micro::GetEvalInput(context, node, 1); + + TfLiteEvalTensor* output_tensor = + tflite::micro::GetEvalOutput(context, node, 0); + const int input_dims = data->input_dims; + const int output_size = data->output_size; + + int* input_dims_num_elements = (int*)context->GetScratchBuffer( + context, data->input_dims_num_elements_buffer_index); + int* output_dims_num_elements = (int*)context->GetScratchBuffer( + context, data->output_dims_num_elements_buffer_index); + + for (int i = 0; i < input_dims; i++) { + output_dims_num_elements[i] = 1; + input_dims_num_elements[i] = 1; + } + + for (int i = input_dims - 2; i >= 0; i--) { + output_dims_num_elements[i] = + output_dims_num_elements[i + 1] * output_tensor->dims->data[i + 1]; + + input_dims_num_elements[i] = + input_dims_num_elements[i + 1] * input_tensor->dims->data[i + 1]; + } + + switch (output_tensor->type) { + case kTfLiteFloat32: { + MirrorPad(padding_matrix, input_tensor->dims, output_dims_num_elements, + input_dims_num_elements, + tflite::micro::GetTensorData(input_tensor), + tflite::micro::GetTensorData(output_tensor), + data->offset, input_dims, output_size); + break; + } + case kTfLiteInt8: { + MirrorPad(padding_matrix, input_tensor->dims, output_dims_num_elements, + input_dims_num_elements, + tflite::micro::GetTensorData(input_tensor), + tflite::micro::GetTensorData(output_tensor), + data->offset, input_dims, output_size); + break; + } + default: + status = kTfLiteError; + break; + } + +#undef TF_LITE_MIRROR_PAD + + return status; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataMirrorPad)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TFLITE_DCHECK(node->user_data != nullptr); + OpDataMirrorPad* data = static_cast(node->user_data); + + TfLiteTensor* input_tensor = micro_context->AllocateTempInputTensor(node, 0); + TfLiteTensor* padding_matrix = + micro_context->AllocateTempInputTensor(node, 1); + TfLiteTensor* output_tensor = + micro_context->AllocateTempOutputTensor(node, 0); + + TF_LITE_ENSURE_EQ(context, NumDimensions(padding_matrix), 2); + TF_LITE_ENSURE_EQ(context, SizeOfDimension(padding_matrix, 0), + NumDimensions(input_tensor)); + auto* params = + reinterpret_cast(node->builtin_data); + if (params == nullptr) { + return kTfLiteError; + } + + data->offset = + params->mode != TfLiteMirrorPaddingMode::kTfLiteMirrorPaddingReflect ? 0 + : 1; + data->input_dims = NumDimensions(input_tensor); + data->output_size = NumElements(output_tensor); + + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, data->input_dims * sizeof(int), + &data->output_dims_num_elements_buffer_index)); + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, data->input_dims * sizeof(int), + &data->input_dims_num_elements_buffer_index)); + + micro_context->DeallocateTempTfLiteTensor(input_tensor); + micro_context->DeallocateTempTfLiteTensor(padding_matrix); + micro_context->DeallocateTempTfLiteTensor(output_tensor); + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_MIRROR_PAD() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_function_specializations.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_function_specializations.h new file mode 100644 index 0000000..1b7b038 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_function_specializations.h @@ -0,0 +1,145 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "mli_api.h" // NOLINT + +namespace tflite { + +// Convolution specialized function. +typedef mli_status (*conv_func_ptr)(const mli_tensor* /*in*/, + const mli_tensor* /*weights*/, + const mli_tensor* /*bias*/, + const mli_conv2d_cfg* /*cfg*/, + mli_tensor* /*out*/); + +#ifdef MLI_2_0 +conv_func_ptr __attribute__((weak)) +mli_krn_conv2d_hwcn(const mli_tensor* weights) { + int filter_w = weights->shape[KRNL_W_DIM_HWCN]; + int filter_h = weights->shape[KRNL_H_DIM_HWCN]; + + if (filter_w == 1 && filter_h == 1) { + return mli_krn_conv2d_hwcn_sa8_sa8_sa32_k1x1; + } else if (filter_w == 3 && filter_h == 3) { + return mli_krn_conv2d_hwcn_sa8_sa8_sa32_k3x3; + } else if (filter_w == 5 && filter_h == 5) { + return mli_krn_conv2d_hwcn_sa8_sa8_sa32_k5x5; + } else { + return mli_krn_conv2d_hwcn_sa8_sa8_sa32; + } +} +#else +conv_func_ptr __attribute__((weak)) +mli_krn_conv2d_hwcn(const mli_tensor* weights, const mli_conv2d_cfg* cfg) { + return mli_krn_conv2d_nhwc_sa8_sa8_sa32; +} +#endif + +// Depthwise convolution specialized function. +typedef mli_status (*depthwise_func_ptr)(const mli_tensor* /*in*/, + const mli_tensor* /*weights*/, + const mli_tensor* /*bias*/, + const mli_conv2d_cfg* /*cfg*/, + mli_tensor* /*out*/); + +#ifdef MLI_2_0 +depthwise_func_ptr __attribute__((weak)) +mli_krn_depthwise_conv2d(const mli_tensor* weights) { + int filter_w = weights->shape[KRNL_DW_W_DIM_HW1N]; + int filter_h = weights->shape[KRNL_DW_H_DIM_HW1N]; + + if (filter_w == 3 && filter_h == 3) { + return mli_krn_depthwise_conv2d_hwcn_sa8_sa8_sa32_k3x3; + } else if (filter_w == 5 && filter_h == 5) { + return mli_krn_depthwise_conv2d_hwcn_sa8_sa8_sa32_k5x5; + } else { + return mli_krn_depthwise_conv2d_hwcn_sa8_sa8_sa32; + } +} +#else +depthwise_func_ptr __attribute__((weak)) +mli_krn_depthwise_conv2d(const mli_tensor* weights, const mli_conv2d_cfg* cfg) { + return mli_krn_depthwise_conv2d_hwcn_sa8_sa8_sa32; +} +#endif + +#ifdef MLI_2_0 +depthwise_func_ptr __attribute__((weak)) +mli_krn_group_conv2d(const mli_tensor* weights) { + int filter_w = weights->shape[KRNL_DW_W_DIM_HW1N]; + int filter_h = weights->shape[KRNL_DW_H_DIM_HW1N]; + + if (filter_w == 3 && filter_h == 3) { + return mli_krn_group_conv2d_hwcn_sa8_sa8_sa32_k3x3; + } else if (filter_w == 5 && filter_h == 5) { + return mli_krn_group_conv2d_hwcn_sa8_sa8_sa32_k5x5; + } else { + return mli_krn_group_conv2d_hwcn_sa8_sa8_sa32; + } +} +#endif + +// Pooling specialized functions. +typedef mli_status (*pooling_func_ptr)(const mli_tensor* /*in*/, + const mli_pool_cfg* /*cfg*/, + mli_tensor* /*out*/); + +#ifdef MLI_2_0 +pooling_func_ptr __attribute__((weak)) +mli_krn_avepool(const mli_pool_cfg* cfg) { + int filter_w = cfg->kernel_width; + int filter_h = cfg->kernel_height; + + if (filter_w == 2 && filter_h == 2) { + return mli_krn_avepool_hwc_sa8_k2x2; + } else if (filter_w == 3 && filter_h == 3) { + return mli_krn_avepool_hwc_sa8_k3x3; + } else { + return mli_krn_avepool_hwc_sa8; + } +} +#else +pooling_func_ptr __attribute__((weak)) +mli_krn_avepool(const mli_pool_cfg* cfg) { + return mli_krn_avepool_hwc_sa8; +} +#endif + +#ifdef MLI_2_0 +pooling_func_ptr __attribute__((weak)) +mli_krn_maxpool(const mli_pool_cfg* cfg) { + int filter_w = cfg->kernel_width; + int filter_h = cfg->kernel_height; + + if (filter_w == 2 && filter_h == 2) { + return mli_krn_maxpool_hwc_sa8_k2x2; + } else if (filter_w == 3 && filter_h == 3) { + return mli_krn_maxpool_hwc_sa8_k3x3; + } else { + return mli_krn_maxpool_hwc_sa8; + } +} +#else +pooling_func_ptr __attribute__((weak)) +mli_krn_maxpool(const mli_pool_cfg* cfg) { + return mli_krn_maxpool_hwc_sa8; +} +#endif + +} // namespace tflite +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_interface.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_interface.cpp new file mode 100644 index 0000000..bbd5e3a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_interface.cpp @@ -0,0 +1,160 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "mli_interface.h" // NOLINT + +#include + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace ops { +namespace micro { + +#ifndef MLI_2_0 +template <> +int8_t* MliTensorInterface::Data(void) { + TFLITE_DCHECK(tensor_->el_type == MLI_EL_ASYM_I8); + return static_cast(tensor_->data); +} + +template <> +int32_t* MliTensorInterface::Data(void) { + TFLITE_DCHECK(tensor_->el_type == MLI_EL_ASYM_I32); + return static_cast(tensor_->data); +} + +template <> +int32_t* MliTensorInterface::Scale(void) { + return &tensor_->el_params.asym.scale.i32; +} + +template <> +int32_t** MliTensorInterface::Scale(void) { + return &tensor_->el_params.asym.scale.pi32; +} + +template <> +void MliTensorInterface::SetData(int8_t* data, uint32_t capacity) const { + TFLITE_DCHECK(tensor_->el_type == MLI_EL_ASYM_I8); + tensor_->data = data; + tensor_->capacity = capacity; +} + +template <> +void MliTensorInterface::SetData(int32_t* data, uint32_t capacity) const { + TFLITE_DCHECK(tensor_->el_type == MLI_EL_ASYM_I32); + tensor_->data = data; + tensor_->capacity = capacity; +} + +mli_tensor* MliTensorInterface::MliTensor(void) { return tensor_; } + +const mli_tensor* MliTensorInterface::MliTensor(void) const { + return static_cast( + const_cast(this)->MliTensor()); +} + +uint32_t* MliTensorInterface::Rank(void) { return &tensor_->rank; } + +const uint32_t* MliTensorInterface::DataCapacity(void) const { + return &tensor_->capacity; +} + +mli_element_type* MliTensorInterface::ElType(void) { return &tensor_->el_type; } + +template <> +int16_t* MliTensorInterface::ZeroPoint(void) { + return &tensor_->el_params.asym.zero_point.i16; +} + +template <> +int16_t** MliTensorInterface::ZeroPoint(void) { + return &tensor_->el_params.asym.zero_point.pi16; +} + +uint32_t* MliTensorInterface::ZeroPointCapacity(void) { return nullptr; } + +int32_t* MliTensorInterface::Dim(void) { return &tensor_->el_params.asym.dim; } + +uint32_t* MliTensorInterface::ScaleCapacity(void) { return nullptr; } + +template <> +int8_t* MliTensorInterface::ScaleFracBits(void) { + return &tensor_->el_params.asym.scale_frac_bits; +} + +uint32_t* MliTensorInterface::ScaleFracBitsCapacity(void) { return nullptr; } + +int32_t* MliTensorInterface::MemStride(void) { return tensor_->mem_stride; } + +uint32_t* MliTensorInterface::Shape(void) { return tensor_->shape; } + +const uint32_t* MliTensorInterface::Shape(void) const { + return static_cast( + const_cast(this)->Shape()); +} + +void MliTensorInterface::SetScale(float fscale) { + int exp; + frexpf(fscale, &exp); + int frac_bits = 31 - exp; + int32_t iscale = (int32_t)((1ll << frac_bits) * fscale + 0.5f); + *(this->ScaleFracBits()) = frac_bits; + *(this->Scale()) = (int32_t)iscale; +} + +void MliTensorInterface::SetScalePerChannel(float* fscale, + const int num_channels) { + int min_frac_bits; + for (int i = 0; i < num_channels; i++) { + int exp; + frexpf(fscale[i], &exp); + int cur_frac_bits = 31 - exp; + if (i == 0) { + min_frac_bits = cur_frac_bits; + } else { + min_frac_bits = + min_frac_bits < cur_frac_bits ? min_frac_bits : cur_frac_bits; + } + } + *this->ScaleFracBits() = min_frac_bits; + + for (int i = 0; i < num_channels; i++) { + int32_t iscale = (int32_t)((1ll << min_frac_bits) * fscale[i] + 0.5f); + (*this->Scale())[i] = iscale; + } +} + +void MliTensorInterface::SetElType(TfLiteType type) { + if (type == kTfLiteInt8) { + *this->ElType() = MLI_EL_ASYM_I8; + } else if (type == kTfLiteInt32) { + *this->ElType() = MLI_EL_ASYM_I32; + } else { + MicroPrintf("Wrong data type. Expected int8_t or int32_t."); + TFLITE_ABORT; + } +} +#endif + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_interface.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_interface.h new file mode 100644 index 0000000..e08f84a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_interface.h @@ -0,0 +1,80 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_INTERFACE_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_INTERFACE_H_ + +#include "mli_api.h" // NOLINT +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +namespace tflite { +namespace ops { +namespace micro { + +// Abstracts access to mli_tensor fields to use different versions of MLI +// Library (1.x and 2.x) +// Example: +// ops::micro::MliTensorInterface mli_in = +// ops::micro::MliTensorInterface(static_cast( +// context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + +class MliTensorInterface { + public: + // Make sure that lifetime of MliTensorInterface instance isn't bigger than + // related mli_tensor. + MliTensorInterface(mli_tensor* tensor) : tensor_(tensor){}; + MliTensorInterface() = default; + ~MliTensorInterface() = default; + + template + T* Data(); + template + T Scale(); + template + T ZeroPoint(); + template + T ScaleFracBits(); + mli_tensor* MliTensor(); + const mli_tensor* MliTensor() const; + int32_t* Dim(); + uint32_t* Rank(); + uint32_t* Shape(); + const uint32_t* Shape() const; + const uint32_t* DataCapacity() const; + uint32_t* ScaleCapacity(); + mli_element_type* ElType(); + uint32_t* ScaleFracBitsCapacity(); + int32_t* MemStride(); + uint32_t* ZeroPointCapacity(); + + template + void SetData(T* data, uint32_t capacity) const; + void SetScale(float fscale); + void SetScalePerChannel(float* fscale, const int num_channels); + void SetElType(TfLiteType type); + + private: + mli_tensor* tensor_; +}; + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_SLICERS_H_ + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.cpp new file mode 100644 index 0000000..8b65e38 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.cpp @@ -0,0 +1,131 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "mli_slicers.h" // NOLINT + +#include + +namespace tflite { +namespace ops { +namespace micro { + +TensorSlicer::TensorSlicer(const mli_tensor* full_tensor, int slice_dim, + int slice_size, int padding_pre, int padding_post, + int overlap, bool interleave_mode) + : full_tensor_(full_tensor), + sub_tensor_{}, + sub_cfg_{}, + done_(false), + sliceDim_(slice_dim), + pad_pre_(padding_pre), + pad_post_(padding_post), + overlap_(overlap) { + /* In the interleave mode, the slicing happens from the deepest dimension up + to the slice_dim for example in an HWC layout this can mode can be used to + slice in the C dimenstion. in this mode the data is not contiguous in memory + anymore */ + if (interleave_mode) { + for (int i = 0; i < static_cast(full_tensor->rank); i++) { + if (i > slice_dim) { + sub_cfg_.size[i] = 1; + } else if (i == slice_dim) { + sub_cfg_.size[i] = slice_size; + } else { + sub_cfg_.size[i] = full_tensor->shape[i]; + } + } + sub_cfg_.sub_tensor_rank = full_tensor->rank; + + } else { + /* In the not interleaved mode, the slicing happens from the outer most + dimension up to the slice_dim for example in an HWC layout this mode can be + used to slice in the H dimension. in this mode the data of the slice is + still contiguous in memory (if that was the case in the input tensor */ + for (int i = 0; i < static_cast(full_tensor->rank); i++) { + if (i < slice_dim) { + sub_cfg_.size[i] = 1; + } else if (i == slice_dim) { + sub_cfg_.size[i] = slice_size; + } else { + sub_cfg_.size[i] = full_tensor->shape[i]; + } + } + sub_cfg_.sub_tensor_rank = full_tensor->rank - slice_dim; + } + + ComputeSubTensor(); +} + +void TensorSlicer::ComputeSubTensor(void) { + // subtsr_cfg_ is used to keep track of the iteration. + // A copy is created to update it with the correct clipping and padding for + // the current slice + mli_sub_tensor_cfg cfg_new = sub_cfg_; + + // begin and end spans the complete input region including padding areas. + const int begin = (int)sub_cfg_.offset[sliceDim_] - pad_pre_; + // end is clipped to the end of the full input region. this is needed for + // cases where the last slice is smaller than the rest. + const int end = std::min(begin + sub_cfg_.size[sliceDim_] + overlap_, + full_tensor_->shape[sliceDim_] + pad_post_); + // The start coordinate of the subtensor is clipped to zero + cfg_new.offset[sliceDim_] = std::max(begin, 0); + // and the stop coordinate is clipped to the size of the full tensor + const int stop_coord = + std::min(end, static_cast(full_tensor_->shape[sliceDim_])); + // compute the size of the subtensor + cfg_new.size[sliceDim_] = stop_coord - cfg_new.offset[sliceDim_]; + + // compute the padding configuration for the current slice. + actual_padding_pre = cfg_new.offset[sliceDim_] - begin; + actual_padding_post = end - stop_coord; + + mli_hlp_create_subtensor(full_tensor_, &cfg_new, &sub_tensor_); +} + +void TensorSlicer::Next(void) { + for (int i = full_tensor_->rank - 1; i >= 0; i--) { + sub_cfg_.offset[i] += sub_cfg_.size[i]; + if (sub_cfg_.offset[i] >= full_tensor_->shape[i]) { + // wrap + sub_cfg_.offset[i] = 0; + // and continue to the next dimension, if no next dimension we are done. + if (i == 0) done_ = true; + continue; + } else { + // carry is false, so break from the loop + break; + } + } + + if (!done_) ComputeSubTensor(); +} + +bool TensorSlicer::Done(void) { return done_; } + +int TensorSlicer::GetPaddingPre(void) { return actual_padding_pre; } + +int TensorSlicer::GetPaddingPost(void) { return actual_padding_post; } + +mli_tensor* TensorSlicer::Sub(void) { return &sub_tensor_; } + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h new file mode 100644 index 0000000..fa22020 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h @@ -0,0 +1,61 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_SLICERS_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_SLICERS_H_ + +#include "mli_api.h" // NOLINT +namespace tflite { +namespace ops { +namespace micro { + +class TensorSlicer { + public: + TensorSlicer(const mli_tensor* full_tensor, int slice_dim, int slice_size, + int padding_pre = 0, int padding_post = 0, int overlap = 0, + bool interleave_mode = false); + ~TensorSlicer() = default; + + void Next(); + bool Done(); + int GetPaddingPre(); + int GetPaddingPost(); + + mli_tensor* Sub(); + + // Default constructor is deleted + TensorSlicer() = delete; + + private: + const mli_tensor* full_tensor_; + mli_tensor sub_tensor_; + mli_sub_tensor_cfg sub_cfg_; + bool done_; + int sliceDim_; + int pad_pre_, pad_post_, overlap_; + int actual_padding_pre, actual_padding_post; + + void ComputeSubTensor(); +}; + +} // namespace micro +} // namespace ops +} // namespace tflite +#endif // TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_SLICERS_H_ + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h new file mode 100644 index 0000000..4179c74 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h @@ -0,0 +1,315 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_TF_UTILS_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_TF_UTILS_H_ + +#include "mli_api.h" // NOLINT +#include "mli_interface.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#define KRNL_C_DIM_NHWC 0 // output channels + +namespace tflite { +namespace ops { +namespace micro { + +inline void ConvertToMliTensorData(const TfLiteTensor* tfT, + MliTensorInterface* mliT, + bool is_bias_tensor) { + // Data is NULL until MliTensorAttachBuffer is called. + mliT->SetElType(tfT->type); + if (tfT->type == kTfLiteInt8) { + mliT->SetData(nullptr, tfT->bytes); + } else if (tfT->type == kTfLiteInt32) { + mliT->SetData(nullptr, tfT->bytes); + } else { + MicroPrintf("Wrong data type. Expected int8_t or int32_t."); + TFLITE_ABORT; + } + const int32_t dims_count = GetTensorShape(tfT).DimensionsCount(); + *mliT->Rank() = is_bias_tensor ? 1 : dims_count; + + int mli_tensor_memstride = 1; + if (is_bias_tensor) { + mliT->Shape()[0] = GetTensorShape(tfT).Dims(dims_count - 1); + mliT->MemStride()[0] = mli_tensor_memstride; + } else { + for (int i = dims_count - 1; i >= 0; --i) { + mliT->Shape()[i] = GetTensorShape(tfT).Dims(i); + mliT->MemStride()[i] = mli_tensor_memstride; + mli_tensor_memstride *= GetTensorShape(tfT).Dims(i); + } + } +} + +inline void ConvertToMliQuantParams(const TfLiteTensor* tfT, + MliTensorInterface* mliT) { + *mliT->Dim() = -1; +#ifdef MLI_2_0 + *mliT->ZeroPointCapacity() = 0; +#endif + *mliT->ZeroPoint() = tfT->params.zero_point; + float fscale = tfT->params.scale; + mliT->SetScale(fscale); +} + +inline void ConvertToMliQuantParamsPerChannel(const TfLiteTensor* tfT, + MliTensorInterface* mliT, + bool is_bias_tensor) { + // mli tensor scale and zero_point arrays should be allocated at this point +#ifdef MLI_2_0 + TFLITE_DCHECK_NE(*mliT->Scale(), 0); + TFLITE_DCHECK_NE(*mliT->ZeroPoint(), 0); +#else + TFLITE_DCHECK_NE(*mliT->Scale(), 0); + TFLITE_DCHECK_NE(*mliT->ZeroPoint(), 0); +#endif + + // get per channel quantization parameters + const auto* affine_quantization = + reinterpret_cast(tfT->quantization.params); + int32_t quantized_dimension = + is_bias_tensor ? 0 : affine_quantization->quantized_dimension; + const int num_channels = mliT->Shape()[quantized_dimension]; + + *mliT->Dim() = quantized_dimension; + + // set capacities +#ifdef MLI_2_0 + *mliT->ScaleFracBitsCapacity() = num_channels * sizeof(int8_t); + *mliT->ScaleCapacity() = num_channels * sizeof(int16_t); + *mliT->ZeroPointCapacity() = num_channels * sizeof(int16_t); +#endif + float* fscale = affine_quantization->scale->data; + mliT->SetScalePerChannel(fscale, num_channels); + +#ifdef MLI_2_0 + int16_t* zero_point = *mliT->ZeroPoint(); + for (int i = 0; i < num_channels; i++) { + zero_point[i] = tfT->params.zero_point; + } +#endif +} + +template +inline void MliTensorAttachBuffer(const TfLiteEvalTensor*, + const MliTensorInterface*); + +template <> +inline void MliTensorAttachBuffer(const TfLiteEvalTensor* tfT, + const MliTensorInterface* mliT) { + // "const_cast" here used to attach const data buffer to the initially + // non-const mli_tensor. This is required by current implementation of MLI + // backend and planned for redesign due to this and some other aspects. + mliT->SetData( + const_cast(tflite::micro::GetTensorData(tfT)), + *mliT->DataCapacity()); +} + +template <> +inline void MliTensorAttachBuffer(const TfLiteEvalTensor* tfT, + const MliTensorInterface* mliT) { + // "const_cast" here used to attach const data buffer to the initially + // non-const mli_tensor. This is required by current implementation of MLI + // backend and planned for redesign due to this and some other aspects. + mliT->SetData( + const_cast(tflite::micro::GetTensorData(tfT)), + *mliT->DataCapacity()); +} + +inline void ConvertToMliTensor(const TfLiteTensor* tfT, + MliTensorInterface* mliT) { + ConvertToMliTensorData(tfT, mliT, false); + ConvertToMliQuantParams(tfT, mliT); +} + +inline void ConvertToMliTensorPerChannel(const TfLiteTensor* tfT, + MliTensorInterface* mliT, + bool is_bias_tensor) { + ConvertToMliTensorData(tfT, mliT, is_bias_tensor); + ConvertToMliQuantParamsPerChannel(tfT, mliT, is_bias_tensor); +} + +inline void PrepareLocalTensor(mli_tensor* tensor, mli_tensor* tensor_local) { +#ifdef MLI_2_0 + int8_t* local_data = tensor_local->data.mem.pi8; + *tensor_local = *tensor; + tensor_local->data.mem.pi8 = local_data; +#else + int8_t* local_data = static_cast(tensor_local->data); + *tensor_local = *tensor; + tensor_local->data = local_data; +#endif +} + +inline void AdjustBiasTensor(MliTensorInterface* bias, MliTensorInterface* in, + MliTensorInterface* weights) { + int32_t quantized_dimension = *bias->Dim(); + const int num_channels = + quantized_dimension < 0 ? 1 : bias->Shape()[quantized_dimension]; + for (int i = 0; i < num_channels; i++) { + int32_t adjusted_bias_scale = + (*in->Scale()) * (*weights->Scale())[i]; + int in_shift = *in->ScaleFracBits(); + int w_shift = (*weights->ScaleFracBits())[i]; + int b_shift = (*bias->ScaleFracBits())[i]; + int bias_shift = in_shift + w_shift - b_shift; + (*bias->Scale())[i] = + (int16_t)(adjusted_bias_scale >> bias_shift); + } +} + +#ifdef MLI_2_0_KRNL_TEST +// Reorder an array according to given indexes. If backward is true, order of +// index array must be reversed. +inline static void reorder(uint32_t* arr, const uint8_t index[], + bool backward) { + uint32_t temp[MLI_MAX_RANK]; + for (int8_t i = 0; i < MLI_MAX_RANK; i++) { + if (backward) + temp[index[i]] = arr[i]; + else + temp[i] = arr[index[i]]; + } + for (int8_t i = 0; i < MLI_MAX_RANK; i++) { + arr[i] = temp[i]; + } +} + +// Change shape of mli tensor and recalculate mem strides. +inline void change_shape(mli_tensor* mliT, const uint8_t dim_order[]) { + reorder(mliT->shape, dim_order, false); + + // Calculate strides for new layout + int mli_tensor_memstride = 1; + for (int shape_idx = mliT->rank - 1; shape_idx >= 0; --shape_idx) { + mliT->mem_stride[shape_idx] = mli_tensor_memstride; + mli_tensor_memstride *= mliT->shape[shape_idx]; + } +} + +inline void permute_weights(const mli_tensor* weights_src, + const mli_permute_cfg* permute_cfg, + mli_tensor* weights_dst, + mli_data_container* buffer_data) { + mli_tensor buffer = {}; + buffer.el_params = weights_dst->el_params; + buffer.data = *buffer_data; + // Compare weights tensor size and avaliable buffer capacity. + int buffer_size = buffer_data->capacity; + int weights_size = mli_hlp_count_elem_num(weights_src, 0) * + mli_hlp_tensor_element_size(weights_src); + + // Need to change shape of distanation weights buffer according to permute + // dimensions order to calculate slice sizes + change_shape(weights_dst, permute_cfg->perm_dim); + + if (buffer_size >= weights_size) { + mli_mov_cfg_t copy_config; + mli_mov_cfg_for_copy(©_config); + mli_mov_tensor_sync(weights_src, ©_config, &buffer); + mli_krn_permute_sa8(&buffer, permute_cfg, weights_dst); + } else { + // Weights shape is NHWC and output (buffer) shape is HWC where N_w = C_o. + // Buffer size (H_o * W_o) must be more or equal then the weights size (H_w + // * W_w * C_w). So, this is the reason, why buffer size (output tensor) is + // divided by channel shape. + uint32_t slice_size = buffer_size / weights_src->shape[KRNL_C_DIM_NHWC]; + + mli_mov_cfg_t copy_config = {}; + uint32_t src_offsets[] = {0, 0, 0, 0}; + uint32_t src_sizes[] = {0, 0, 0, 0}; + int dst_mem_stride[] = {0, 0, 0, 0}; + + mli_tensor weights_dst_sub_tensor; + mli_sub_tensor_cfg sub_tensor_cfg = {}; + sub_tensor_cfg.sub_tensor_rank = weights_src->rank; + + // Calculate dimensions for slice accroding to buffer capacity. + // Now, after calling change_shape() function, dst weights buffer has the + // MLI layout (HWCN). This means, the innermost dimension (N) of dst weights + // tensor is equal to the innermost dimension of output tensor (N). + sub_tensor_cfg.size[weights_dst->rank - 1] = + src_sizes[weights_dst->rank - 1] = weights_src->shape[KRNL_C_DIM_NHWC]; + // Now need to calculate other shapes for weights slice. Total slice size is + // H*W*C*N, so to calculate sizes for each axis, avaliable slice size is + // divided by shape for each axis. + uint32_t slice_size_left = slice_size; + for (uint32_t i = 0; i < weights_dst->rank - 1; i++) { + sub_tensor_cfg.size[i] = src_sizes[i] = + slice_size_left / weights_dst->shape[i] > 0 ? weights_dst->shape[i] + : slice_size_left; + slice_size_left /= weights_dst->shape[i]; + slice_size_left = slice_size_left > 0 ? slice_size_left : 1; + } + // Need to reorder src tensor sizes because it is still in TFLM format + // (NHWC) and src_sizes array calculated as (HWCN). + reorder(src_sizes, permute_cfg->perm_dim, true); + + sub_tensor_cfg.offset[KRNL_C_DIM_HWCN] = src_offsets[KRNL_H_DIM_HWCN] = 0; + sub_tensor_cfg.offset[KRNL_H_DIM_HWCN] = src_offsets[KRNL_W_DIM_HWCN] = 0; + sub_tensor_cfg.offset[KRNL_W_DIM_HWCN] = src_offsets[KRNL_D_DIM_HWCN] = 0; + sub_tensor_cfg.offset[KRNL_D_DIM_HWCN] = src_offsets[KRNL_C_DIM_HWCN] = 0; + do { + do { + do { + do { + mli_mov_cfg_for_slice(©_config, (int*)src_offsets, + (int*)src_sizes, dst_mem_stride); + mli_mov_tensor_sync(weights_src, ©_config, &buffer); + + mli_hlp_create_subtensor(weights_dst, &sub_tensor_cfg, + &weights_dst_sub_tensor); + mli_krn_permute_sa8(&buffer, permute_cfg, &weights_dst_sub_tensor); + + // For each axis, it is necessary to recalculate the offsets and + // slice sizes. + sub_tensor_cfg.offset[2] = src_offsets[3] += src_sizes[3]; + src_sizes[3] = + std::min(src_sizes[3], weights_src->shape[3] - src_offsets[3]); + } while (src_offsets[3] < weights_src->shape[3]); + + sub_tensor_cfg.offset[1] = src_offsets[2] += src_sizes[2]; + src_sizes[2] = + std::min(src_sizes[2], weights_src->shape[2] - src_offsets[2]); + } while (src_offsets[2] < weights_src->shape[2]); + + sub_tensor_cfg.offset[0] = src_offsets[1] += src_sizes[1]; + src_sizes[1] = + std::min(src_sizes[1], weights_src->shape[1] - src_offsets[1]); + } while (src_offsets[1] < weights_src->shape[1]); + + sub_tensor_cfg.offset[3] = src_offsets[0] += src_sizes[0]; + src_sizes[0] = + std::min(src_sizes[0], weights_src->shape[0] - src_offsets[0]); + } while (src_offsets[0] < weights_src->shape[0]); + } +} +#endif + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_ARC_MLI_TF_UTILS_H_ + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.cpp new file mode 100644 index 0000000..9f00d2e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.cpp @@ -0,0 +1,387 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +void EvalQuantized(TfLiteContext* context, TfLiteNode* node, + const OpDataMul* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params = {}; + + op_params.quantized_activation_min = data->output_activation_min; + op_params.quantized_activation_max = data->output_activation_max; + op_params.float_activation_max = data->output_activation_max_f32; + op_params.input1_offset = -data->input1_zero_point; + op_params.input2_offset = -data->input2_zero_point; + op_params.output_offset = data->output_zero_point; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (need_broadcast) { + if (input1->type == kTfLiteInt8) { + reference_integer_ops::BroadcastMul4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else if (input1->type == kTfLiteInt16) { + reference_integer_ops::BroadcastMul4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + + } else { + if (input1->type == kTfLiteInt8) { + arm_elementwise_mul_s8( + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorData(input2), op_params.input1_offset, + op_params.input2_offset, tflite::micro::GetTensorData(output), + op_params.output_offset, op_params.output_multiplier, + op_params.output_shift, op_params.quantized_activation_min, + op_params.quantized_activation_max, + MatchingElementsSize(tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorShape(output))); + } else if (input1->type == kTfLiteInt16) { + arm_elementwise_mul_s16( + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorData(input2), + op_params.input1_offset, op_params.input2_offset, + tflite::micro::GetTensorData(output), + op_params.output_offset, op_params.output_multiplier, + op_params.output_shift, op_params.quantized_activation_min, + op_params.quantized_activation_max, + MatchingElementsSize(tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorShape(output))); + } + } +} + +} // namespace + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataMul* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kMulInput1Tensor); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kMulInput2Tensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kMulOutputTensor); + + switch (input1->type) { + case kTfLiteInt8: + EvalQuantized(context, node, data, input1, input2, output); + break; + case kTfLiteInt16: + EvalQuantized(context, node, data, input1, input2, output); + break; + case kTfLiteInt32: + EvalMulQuantizedReference(context, node, data, input1, input2, output); + break; + case kTfLiteFloat32: + EvalMulFloatReference(context, node, params, data, input1, input2, + output); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteStatus EvalInt8(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + TFLITE_DCHECK(node->user_data != nullptr); + + const OpDataMul* data = static_cast(node->user_data); + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kMulInput1Tensor); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kMulInput2Tensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kMulOutputTensor); + TFLITE_DCHECK(input1->type == kTfLiteInt8); + + EvalQuantized(context, node, data, input1, input2, output); + + return kTfLiteOk; +} + +TfLiteStatus EvalInt16(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + TFLITE_DCHECK(node->user_data != nullptr); + + const OpDataMul* data = static_cast(node->user_data); + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kMulInput1Tensor); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kMulInput2Tensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kMulOutputTensor); + TFLITE_DCHECK(input1->type == kTfLiteInt16); + + EvalQuantized(context, node, data, input1, input2, output); + + return kTfLiteOk; +} + +TfLiteRegistration Register_MUL() { + return tflite::micro::RegisterOp(MulInit, MulPrepare, Eval); +} + +TfLiteRegistration Register_MUL_INT8() { + return tflite::micro::RegisterOp(MulInit, MulPrepare, EvalInt8); +} + +TfLiteRegistration Register_MUL_INT16() { + return tflite::micro::RegisterOp(MulInit, MulPrepare, EvalInt16); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#if ESP_NN +#include "edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h" +#endif + +#include + +long long mul_total_time = 0; + +namespace tflite { +#if ESP_NN +void MulEvalQuantized(TfLiteContext* context, TfLiteNode* node, + const OpDataMul* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params = {}; + op_params.quantized_activation_min = data->output_activation_min; + op_params.quantized_activation_max = data->output_activation_max; + op_params.float_activation_max = data->output_activation_max_f32; + op_params.input1_offset = -data->input1_zero_point; + op_params.input2_offset = -data->input2_zero_point; + op_params.output_offset = data->output_zero_point; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (need_broadcast) { + reference_integer_ops::BroadcastMul4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + const int8_t *input1_data = tflite::micro::GetTensorData(input1); + const int8_t *input2_data = tflite::micro::GetTensorData(input2); + int8_t *out_data = tflite::micro::GetTensorData(output); + + esp_nn_mul_elementwise_s8(input1_data, input2_data, op_params.input1_offset, + op_params.input2_offset, out_data, op_params.output_offset, + op_params.output_multiplier, op_params.output_shift, + op_params.quantized_activation_min, op_params.quantized_activation_max, + MatchingElementsSize(tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorShape(output))); + } +} +#endif + +TfLiteStatus MulEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataMul* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kMulInput1Tensor); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kMulInput2Tensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kMulOutputTensor); + + long long start_time = esp_timer_get_time(); + switch (input1->type) { + case kTfLiteInt8: +#if ESP_NN + MulEvalQuantized(context, node, data, input1, input2, output); +#else + EvalMulQuantizedReference(context, node, data, input1, input2, output); +#endif + break; + case kTfLiteInt32: + EvalMulQuantizedReference(context, node, data, input1, input2, output); + break; + case kTfLiteFloat32: + EvalMulFloatReference(context, node, params, data, input1, input2, + output); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + mul_total_time += esp_timer_get_time() - start_time; + return kTfLiteOk; +} + +TfLiteRegistration Register_MUL() { + return tflite::micro::RegisterOp(MulInit, MulPrepare, MulEval); +} + +} // namespace tflite + +#else +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +TfLiteStatus MulEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataMul* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kMulInput1Tensor); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kMulInput2Tensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kMulOutputTensor); + + switch (input1->type) { + case kTfLiteInt8: + case kTfLiteInt16: + case kTfLiteInt32: + EvalMulQuantizedReference(context, node, data, input1, input2, output); + break; + case kTfLiteFloat32: + EvalMulFloatReference(context, node, params, data, input1, input2, + output); + break; + default: + MicroPrintf("Type %s (%d) not supported.", + TfLiteTypeGetName(input1->type), input1->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteRegistration Register_MUL() { + return tflite::micro::RegisterOp(MulInit, MulPrepare, MulEval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.h new file mode 100644 index 0000000..61d4605 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.h @@ -0,0 +1,74 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_MUL_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_MUL_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +extern const int kMulInput1Tensor; +extern const int kMulInput2Tensor; +extern const int kMulOutputTensor; + +struct OpDataMul { + int32_t input1_zero_point; + int32_t input2_zero_point; + + int32_t output_activation_min; + int32_t output_activation_max; + int32_t output_zero_point; + int32_t output_multiplier; + int output_shift; + + float output_activation_min_f32; + float output_activation_max_f32; +}; + +void* MulInit(TfLiteContext* context, const char* buffer, size_t length); + +TfLiteStatus CalculateOpDataMul(TfLiteContext* context, TfLiteNode* node, + TfLiteMulParams* params, OpDataMul* data); + +TfLiteStatus MulPrepare(TfLiteContext* context, TfLiteNode* node); + +TfLiteStatus EvalMulQuantizedReference(TfLiteContext* context, TfLiteNode* node, + const OpDataMul* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output); + +void EvalMulFloatReference(TfLiteContext* context, TfLiteNode* node, + TfLiteMulParams* params, const OpDataMul* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output); + +// Generic must define registration function. +TfLiteRegistration Register_MUL(); + +#if defined(CMSIS_NN) +TfLiteRegistration Register_MUL_INT8(); +#else +// Fallback registration +inline TfLiteRegistration Register_MUL_INT8() { return Register_MUL(); } +#endif +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_MUL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul_common.cpp new file mode 100644 index 0000000..187fae2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/mul_common.cpp @@ -0,0 +1,213 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mul.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" + +namespace tflite { + +const int kMulInput1Tensor = 0; +const int kMulInput2Tensor = 1; +const int kMulOutputTensor = 0; + +void* MulInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataMul)); +} + +TfLiteStatus CalculateOpDataMul(TfLiteContext* context, TfLiteNode* node, + TfLiteMulParams* params, OpDataMul* data) { + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kMulInput1Tensor); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kMulInput2Tensor); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kMulOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, input2->type); + + if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + + double real_multiplier = static_cast(input1->params.scale) * + static_cast(input2->params.scale) / + static_cast(output->params.scale); + QuantizeMultiplier(real_multiplier, &data->output_multiplier, + &data->output_shift); + + data->input1_zero_point = input1->params.zero_point; + data->input2_zero_point = input2->params.zero_point; + data->output_zero_point = output->params.zero_point; + + if (input1->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, data->input1_zero_point, 0); + TF_LITE_ENSURE_EQ(context, data->input2_zero_point, 0); + TF_LITE_ENSURE_EQ(context, data->output_zero_point, 0); + } + } else if (output->type == kTfLiteInt32) { + CalculateActivationRange(params->activation, &data->output_activation_min, + &data->output_activation_max); + } else { + CalculateActivationRange(params->activation, + &data->output_activation_min_f32, + &data->output_activation_max_f32); + } + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus MulPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + OpDataMul* data = static_cast(node->user_data); + + return CalculateOpDataMul(context, node, params, data); +} + +TfLiteStatus EvalMulQuantizedReference(TfLiteContext* context, TfLiteNode* node, + const OpDataMul* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params = {}; + op_params.quantized_activation_min = data->output_activation_min; + op_params.quantized_activation_max = data->output_activation_max; + op_params.float_activation_max = data->output_activation_max_f32; + op_params.input1_offset = -data->input1_zero_point; + op_params.input2_offset = -data->input2_zero_point; + op_params.output_offset = data->output_zero_point; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (input1->type == kTfLiteInt8) { + if (need_broadcast) { + reference_integer_ops::BroadcastMul4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_integer_ops::Mul(op_params, + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + } else if (input1->type == kTfLiteInt32) { + if (need_broadcast) { + reference_ops::BroadcastMul4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Mul(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + } else if (input1->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, op_params.input1_offset, 0); + TF_LITE_ENSURE_EQ(context, op_params.input2_offset, 0); + TF_LITE_ENSURE_EQ(context, op_params.output_offset, 0); + + if (need_broadcast) { + reference_integer_ops::BroadcastMul4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_integer_ops::Mul(op_params, + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + } + return kTfLiteOk; +} + +void EvalMulFloatReference(TfLiteContext* context, TfLiteNode* node, + TfLiteMulParams* params, const OpDataMul* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params = {}; + op_params.float_activation_min = data->output_activation_min_f32; + op_params.float_activation_max = data->output_activation_max_f32; + + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + if (need_broadcast) { + reference_ops::BroadcastMul4DSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Mul(op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/neg.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/neg.cpp new file mode 100644 index 0000000..249f7ad --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/neg.cpp @@ -0,0 +1,57 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/neg.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + switch (input->type) { + // TODO(wangtz): handle for kTfLiteInt8 + case kTfLiteFloat32: + reference_ops::Negate(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_NEG() { + return tflite::micro::RegisterOp(nullptr, nullptr, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pack.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pack.cpp new file mode 100644 index 0000000..79615bd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pack.cpp @@ -0,0 +1,112 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +constexpr int kOutputTensor = 0; + +template +TfLiteStatus PackImpl(TfLiteContext* context, TfLiteNode* node, + TfLiteEvalTensor* output, int values_count, int axis) { + const TfLiteEvalTensor* input0 = + tflite::micro::GetEvalInput(context, node, 0); + + const int dimensions = output->dims->size; + const TfLiteIntArray* input_dims = input0->dims; + const TfLiteIntArray* output_dims = output->dims; + + if (axis < 0) { + axis += dimensions; + } + + int outer_size = 1; + for (int i = 0; i < axis; ++i) { + outer_size *= output_dims->data[i]; + } + int copy_size = 1; + for (int i = axis + 1; i < dimensions; ++i) { + copy_size *= output_dims->data[i]; + } + int input_size = 1; + for (int i = 0; i < input_dims->size; ++i) { + input_size *= input_dims->data[i]; + } + TFLITE_DCHECK_EQ(input_size, copy_size * outer_size); + + T* output_data = tflite::micro::GetTensorData(output); + + for (int i = 0; i < values_count; ++i) { + const TfLiteEvalTensor* t = tflite::micro::GetEvalInput(context, node, i); + const T* input_data = tflite::micro::GetTensorData(t); + for (int k = 0; k < outer_size; ++k) { + const T* input_ptr = input_data + copy_size * k; + int loc = k * values_count * copy_size + i * copy_size; + T* output_ptr = output_data + loc; + for (int j = 0; j < copy_size; ++j) output_ptr[j] = input_ptr[j]; + } + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLitePackParams* data = + reinterpret_cast(node->builtin_data); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + switch (output->type) { + case kTfLiteFloat32: { + return PackImpl(context, node, output, data->values_count, + data->axis); + } + case kTfLiteInt8: { + return PackImpl(context, node, output, data->values_count, + data->axis); + } + case kTfLiteInt32: { + return PackImpl(context, node, output, data->values_count, + data->axis); + } + case kTfLiteInt64: { + return PackImpl(context, node, output, data->values_count, + data->axis); + } + default: { + MicroPrintf("Type '%s' is not supported by pack.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_PACK() { + return tflite::micro::RegisterOp(nullptr, nullptr, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pad.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pad.cpp new file mode 100644 index 0000000..a7d7edd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pad.cpp @@ -0,0 +1,230 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pad.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/portable_tensor.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +struct OpData { + PadParams params; + int32_t output_zero_point; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, /*index=*/0); + const TfLiteEvalTensor* constant_values = + NumInputs(node) == 3 + ? tflite::micro::GetEvalInput(context, node, /*index=*/2) + : nullptr; + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, /*index=*/0); + + switch (input->type) { + case kTfLiteFloat32: { + float pad_value = + constant_values == nullptr + ? 0.f + : *tflite::micro::GetTensorData(constant_values); + if (data->params.resizing_category == ResizingCategory::kImageStyle) { + reference_ops::PadImageStyle( + data->params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), &pad_value, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Pad(data->params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + &pad_value, tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + } break; + case kTfLiteInt8: { + int8_t pad_value; + if (constant_values == nullptr) { + pad_value = static_cast(data->output_zero_point); + } else { + pad_value = *tflite::micro::GetTensorData(constant_values); + } + if (data->params.resizing_category == ResizingCategory::kImageStyle) { + reference_ops::PadImageStyle( + data->params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), &pad_value, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + reference_ops::Pad(data->params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + &pad_value, tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + } break; + case kTfLiteInt16: { + int16_t pad_value = + constant_values == nullptr + ? 0 + : *tflite::micro::GetTensorData(constant_values); + reference_ops::Pad(data->params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + &pad_value, tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } break; + case kTfLiteInt32: { + int32_t pad_value = + constant_values == nullptr + ? 0 + : *tflite::micro::GetTensorData(constant_values); + reference_ops::Pad(data->params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + &pad_value, tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } break; + default: + + MicroPrintf("Type %s not currently supported by Pad.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteStatus PadPrepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TFLITE_DCHECK(node->user_data != nullptr); + OpData* data = static_cast(node->user_data); + + TF_LITE_ENSURE(context, NumInputs(node) == 2 || NumInputs(node) == 3); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, /*index=*/0); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* paddings = + micro_context->AllocateTempInputTensor(node, /*index=*/1); + TF_LITE_ENSURE(context, paddings != nullptr); + TfLiteTensor* constant_values = + NumInputs(node) == 3 + ? micro_context->AllocateTempInputTensor(node, /*index=*/2) + : nullptr; + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, /*index=*/0); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_EQ(context, input->type, output->type); + + // Current implementations rely on the inputs being <= 4D. + TF_LITE_ENSURE(context, NumDimensions(input) <= + reference_ops::PadKernelMaxDimensionCount()); + + if (constant_values != nullptr) { + TF_LITE_ENSURE_EQ(context, input->type, constant_values->type); + // Ensure that constant_values is a scalar. + TF_LITE_ENSURE_EQ(context, NumElements(constant_values), 1); + } + + // There must be a pair of paddings for each output dimension. + TF_LITE_ENSURE_EQ(context, GetTensorShape(paddings).FlatSize(), + output->dims->size * 2); + + // On Micro, outputs must be properly sized by the converter. + // NOTE: This data is only available because the paddings buffer is stored in + // the flatbuffer: + TF_LITE_ENSURE(context, IsConstantTensor(paddings)); + const int32_t* paddings_data = GetTensorData(paddings); + for (int i = 0; i < output->dims->size; i++) { + int output_dim = output->dims->data[i]; + int expected_dim = + input->dims->data[i] + paddings_data[i * 2] + paddings_data[i * 2 + 1]; + TF_LITE_ENSURE_EQ(context, output_dim, expected_dim); + } + + // Calculate OpData: + data->params.resizing_category = ResizingCategory::kGenericResize; + const int paddings_total = GetTensorShape(paddings).FlatSize(); + if (paddings_total == 8 && (paddings_data[0] == 0 && paddings_data[1] == 0) && + (paddings_data[6] == 0 && paddings_data[7] == 0)) { + data->params.resizing_category = ResizingCategory::kImageStyle; + } + + const int num_input_dimensions = NumDimensions(input); + data->params.left_padding_count = num_input_dimensions; + data->params.right_padding_count = num_input_dimensions; + + for (int idx = num_input_dimensions - 1; idx >= 0; --idx) { + data->params.left_padding[idx] = paddings_data[idx * 2]; + data->params.right_padding[idx] = paddings_data[idx * 2 + 1]; + } + + if (input->type == kTfLiteInt8) { + if (constant_values == nullptr) { + // Quantized Pad requires that 0 is represented in the quantized + // range. + TF_LITE_ENSURE(context, output->params.zero_point >= + std::numeric_limits::min()); + TF_LITE_ENSURE(context, output->params.zero_point <= + std::numeric_limits::max()); + } else { + // Quantized Pad requires that 'constant_values' is represented in the + // same quantized range as the input and output tensors. + TF_LITE_ENSURE_EQ(context, output->params.zero_point, + constant_values->params.zero_point); + TF_LITE_ENSURE_EQ(context, static_cast(output->params.scale), + static_cast(constant_values->params.scale)); + } + data->output_zero_point = output->params.zero_point; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(paddings); + if (constant_values != nullptr) { + micro_context->DeallocateTempTfLiteTensor(constant_values); + } + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteRegistration Register_PAD() { + return tflite::micro::RegisterOp(Init, PadPrepare, Eval); +} + +// Also register Pad as PadV2. +TfLiteRegistration Register_PADV2() { + return tflite::micro::RegisterOp(Init, PadPrepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pad.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pad.h new file mode 100644 index 0000000..81d1a9f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pad.h @@ -0,0 +1,27 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_PAD_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_PAD_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +TfLiteStatus PadPrepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_PAD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.cpp new file mode 100644 index 0000000..8b6f9e0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.cpp @@ -0,0 +1,1567 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +struct OpData { + OpDataPooling reference_op_data; + + // Index to buffer for optimizations if applicable. + int buffer_idx; +}; + +void PopulateCommonParams( + TfLiteContext* const context, cmsis_nn_dims* const input_dims, + cmsis_nn_dims* const output_dims, cmsis_nn_pool_params* const pool_params, + cmsis_nn_context* const ctx, cmsis_nn_dims* const filter_dims, + const OpData& data, const RuntimeShape& input_shape, + const RuntimeShape& output_shape, const TfLitePoolParams* params) { + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + + input_dims->n = 1; + input_dims->h = input_shape.Dims(1); + input_dims->w = input_shape.Dims(2); + input_dims->c = depth; + + output_dims->n = 1; + output_dims->h = output_shape.Dims(1); + output_dims->w = output_shape.Dims(2); + output_dims->c = depth; + + pool_params->stride.h = params->stride_height; + pool_params->stride.w = params->stride_width; + pool_params->padding.h = data.reference_op_data.padding.height; + pool_params->padding.w = data.reference_op_data.padding.width; + pool_params->activation.min = data.reference_op_data.activation_min; + pool_params->activation.max = data.reference_op_data.activation_max; + + filter_dims->n = 1; + filter_dims->h = params->filter_height; + filter_dims->w = params->filter_width; + filter_dims->c = 1; + ctx->buf = nullptr; + ctx->size = 0; + if (data.buffer_idx > -1) { + ctx->buf = context->GetScratchBuffer(context, data.buffer_idx); + } +} + +void AverageEvalQuantized(TfLiteContext* context, const TfLiteNode* node, + const TfLitePoolParams* params, const OpData& data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + TFLITE_DCHECK((input->type == kTfLiteInt8) || (input->type == kTfLiteInt16)); + + RuntimeShape input_shape = micro::GetTensorShape(input); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + + RuntimeShape output_shape = micro::GetTensorShape(output); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + cmsis_nn_dims input_dims; + cmsis_nn_dims output_dims; + cmsis_nn_pool_params pool_params; + cmsis_nn_dims filter_dims; + cmsis_nn_context ctx; + + PopulateCommonParams(context, &input_dims, &output_dims, &pool_params, &ctx, + &filter_dims, data, input_shape, output_shape, params); + + if (input->type == kTfLiteInt8) { + TFLITE_DCHECK_EQ( + arm_avgpool_s8(&ctx, &pool_params, &input_dims, + micro::GetTensorData(input), &filter_dims, + &output_dims, micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + } else { + TFLITE_DCHECK_EQ( + arm_avgpool_s16(&ctx, &pool_params, &input_dims, + micro::GetTensorData(input), &filter_dims, + &output_dims, micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + } +} + +TfLiteStatus MaxEvalQuantized(TfLiteContext* context, const TfLiteNode* node, + const TfLitePoolParams* params, + const OpData& data, const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + TFLITE_DCHECK((input->type == kTfLiteInt8) || (input->type == kTfLiteInt16)); + + RuntimeShape input_shape = micro::GetTensorShape(input); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + + RuntimeShape output_shape = micro::GetTensorShape(output); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + cmsis_nn_dims input_dims; + cmsis_nn_dims output_dims; + cmsis_nn_pool_params pool_params; + cmsis_nn_dims filter_dims; + cmsis_nn_context ctx; + + PopulateCommonParams(context, &input_dims, &output_dims, &pool_params, &ctx, + &filter_dims, data, input_shape, output_shape, params); + + if (input->type == kTfLiteInt8) { + TFLITE_DCHECK_EQ( + arm_max_pool_s8(&ctx, &pool_params, &input_dims, + micro::GetTensorData(input), &filter_dims, + &output_dims, micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + } else { + TFLITE_DCHECK_EQ( + arm_max_pool_s16(&ctx, &pool_params, &input_dims, + micro::GetTensorData(input), &filter_dims, + &output_dims, micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + } + + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus MaxPrepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_STATUS(PoolingPrepare(context, node)); + // Set buffer index to a reset value + static_cast(node->user_data)->buffer_idx = -1; + return kTfLiteOk; +} + +TfLiteStatus AveragePrepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_STATUS(PoolingPrepare(context, node)); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kPoolingInputTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kPoolingOutputTensor); + + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + RuntimeShape input_shape = GetTensorShape(input); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + + RuntimeShape output_shape = GetTensorShape(output); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int output_width = output_shape.Dims(2); + + const int32_t buffer_size = + input->type == kTfLiteInt16 + ? arm_avgpool_s16_get_buffer_size(output_width, depth) + : arm_avgpool_s8_get_buffer_size(output_width, depth); + + auto* data = static_cast(node->user_data); + if (buffer_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, buffer_size, &data->buffer_idx)); + } else { + data->buffer_idx = -1; + } + } + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + return kTfLiteOk; +} + +TfLiteStatus AverageEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + // Inputs and outputs share the same type, guaranteed by the converter. + if (input->type == kTfLiteFloat32) { +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + AveragePoolingEvalFloat(context, node, params, &data.reference_op_data, + input, output); + } else if (input->type == kTfLiteInt8) { +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + AverageEvalQuantized(context, node, params, data, input, output); + } else if (input->type == kTfLiteInt16) { + AverageEvalQuantized(context, node, params, data, input, output); + } else { + MicroPrintf("Input type %s is not currently supported", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteStatus AverageEvalInt8(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TFLITE_DCHECK(input->type == kTfLiteInt8); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + AverageEvalQuantized(context, node, params, data, input, output); + + return kTfLiteOk; +} + +TfLiteStatus AverageEvalInt16(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TFLITE_DCHECK(input->type == kTfLiteInt16); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + AverageEvalQuantized(context, node, params, data, input, output); + + return kTfLiteOk; +} +TfLiteStatus MaxEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + if (input->type == kTfLiteFloat32) { +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + MaxPoolingEvalFloat(context, node, params, &data.reference_op_data, input, + output); + } else if (input->type == kTfLiteInt8) { +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + MaxEvalQuantized(context, node, params, data, input, output); + } else if (input->type == kTfLiteInt16) { + MaxEvalQuantized(context, node, params, data, input, output); + } else { + MicroPrintf("Input type %s is not currently supported", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteStatus MaxEvalInt8(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TFLITE_DCHECK(input->type == kTfLiteInt8); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + MaxEvalQuantized(context, node, params, data, input, output); + return kTfLiteOk; +} + +TfLiteStatus MaxEvalInt16(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TFLITE_DCHECK(input->type == kTfLiteInt16); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + MaxEvalQuantized(context, node, params, data, input, output); + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_AVERAGE_POOL_2D_INT8() { + return tflite::micro::RegisterOp(Init, AveragePrepare, AverageEvalInt8); +} + +TfLiteRegistration Register_AVERAGE_POOL_2D_INT16() { + return tflite::micro::RegisterOp(Init, AveragePrepare, AverageEvalInt16); +} + +TfLiteRegistration Register_AVERAGE_POOL_2D() { + return tflite::micro::RegisterOp(Init, AveragePrepare, AverageEval); +} + +TfLiteRegistration Register_MAX_POOL_2D_INT8() { + return tflite::micro::RegisterOp(Init, MaxPrepare, MaxEvalInt8); +} + +TfLiteRegistration Register_MAX_POOL_2D_INT16() { + return tflite::micro::RegisterOp(Init, MaxPrepare, MaxEvalInt16); +} + +TfLiteRegistration Register_MAX_POOL_2D() { + return tflite::micro::RegisterOp(Init, MaxPrepare, MaxEval); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" + +#include "mli_api.h" // NOLINT +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_function_specializations.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_slicers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/mli_tf_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +struct OpData { + TfLitePaddingValues padding; + int32_t activation_min; + int32_t activation_max; + float activation_min_f32; + float activation_max_f32; + + // The result of checking if MLI optimized version of tensors can be used. + bool is_mli_applicable; + + // Tensors in MLI format. + mutable ops::micro::MliTensorInterface mli_in; + mutable ops::micro::MliTensorInterface mli_out; + mli_pool_cfg* cfg; + + // Pointer to the mli convolution function. + pooling_func_ptr p_mli_krn_avepool_hwc_sa8; + pooling_func_ptr p_mli_krn_maxpool_hwc_sa8; +}; + +enum MliPoolingType { AveragePooling = 0, MaxPooling = 1 }; + +bool IsMliApplicable(TfLiteContext* context, const TfLiteTensor* input, + const TfLitePoolParams* params) { + // MLI optimized version only supports int8_t datatype and no fused Relu + return (input->type == kTfLiteInt8 && params->activation == kTfLiteActNone); +} + +TfLiteStatus CalculateOpData(TfLiteContext* context, + const TfLitePoolParams* params, + const TfLiteTensor* input, + const TfLiteTensor* output, OpData* data) { + // input: batch, height, width, channel + int height = SizeOfDimension(input, 1); + int width = SizeOfDimension(input, 2); + + int out_height, out_width; + + data->padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, + /*dilation_rate_height=*/1, + /*dilation_rate_width=*/1, height, width, params->filter_height, + params->filter_width, params->padding, &out_height, &out_width); + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + OpData* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + data->is_mli_applicable = IsMliApplicable(context, input, params); + + TF_LITE_ENSURE_STATUS(CalculateOpData(context, params, input, output, data)); + + if (input->type == kTfLiteFloat32) { + CalculateActivationRange(params->activation, &data->activation_min_f32, + &data->activation_max_f32); + } else if (input->type == kTfLiteInt8) { + CalculateActivationRangeQuantized(context, params->activation, output, + &data->activation_min, + &data->activation_max); + } + + if (data->is_mli_applicable) { + data->mli_in = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->mli_out = ops::micro::MliTensorInterface(static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_tensor)))); + data->cfg = static_cast( + context->AllocatePersistentBuffer(context, sizeof(mli_pool_cfg))); + + ops::micro::ConvertToMliTensor(input, &data->mli_in); + ops::micro::ConvertToMliTensor(output, &data->mli_out); + + data->cfg->kernel_width = params->filter_width; + data->cfg->kernel_height = params->filter_height; + data->cfg->stride_width = params->stride_width; + data->cfg->stride_height = params->stride_height; + + if (params->padding == kTfLitePaddingValid) { + data->cfg->padding_left = 0; + data->cfg->padding_right = 0; + data->cfg->padding_top = 0; + data->cfg->padding_bottom = 0; + } else { + data->cfg->padding_left = data->padding.width; + data->cfg->padding_right = + data->padding.width + data->padding.width_offset; + data->cfg->padding_top = data->padding.height; + data->cfg->padding_bottom = + data->padding.height + data->padding.height_offset; + } + + // Choose pooling mli specialized functions. + data->p_mli_krn_avepool_hwc_sa8 = mli_krn_avepool(data->cfg); + data->p_mli_krn_maxpool_hwc_sa8 = mli_krn_maxpool(data->cfg); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +void AverageEvalFloat(TfLiteContext* context, const TfLiteNode* node, + const TfLitePoolParams* params, const OpData& data, + const TfLiteEvalTensor* input, TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + float activation_min, activation_max; + CalculateActivationRange(params->activation, &activation_min, + &activation_max); + + PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.float_activation_min = activation_min; + op_params.float_activation_max = activation_max; + reference_ops::AveragePool(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf("Type %s (%d) is not supported by ARC MLI Library.", + TfLiteTypeGetName(input->type), input->type); +#endif +} + +// Prepare MLI tensors and run Average or Max Pooling +TfLiteStatus EvalMli(TfLiteContext* context, const TfLitePoolParams* params, + const OpData& data, const TfLiteEvalTensor* input, + TfLiteEvalTensor* output, + const MliPoolingType pooling_type) { + mli_pool_cfg cfg_local = *data.cfg; + + ops::micro::MliTensorAttachBuffer(input, &data.mli_in); + ops::micro::MliTensorAttachBuffer(output, &data.mli_out); + + const int height_dimension = 1; + int in_slice_height = 0; + int out_slice_height = 0; + const int overlap = cfg_local.kernel_height - cfg_local.stride_height; + + // Tensors for data in fast (local) memory and config to copy data from + // external to local memory + mli_tensor in_local = *data.mli_in.MliTensor(); + mli_tensor out_local = *data.mli_out.MliTensor(); + + ops::micro::MliTensorInterface in_local_interface(&in_local); + ops::micro::MliTensorInterface out_local_interface(&out_local); + + mli_mov_cfg_t copy_config; + mli_mov_cfg_for_copy(©_config); + TF_LITE_ENSURE_STATUS(get_arc_scratch_buffer_for_pooling_tensors( + context, &in_local_interface, &out_local_interface)); + + bool in_is_local = + in_local_interface.Data() == data.mli_in.Data(); + bool out_is_local = + out_local_interface.Data() == data.mli_out.Data(); + + TF_LITE_ENSURE_STATUS(arc_scratch_buffer_calc_slice_size_io( + &in_local_interface, &out_local_interface, cfg_local.kernel_height, + cfg_local.stride_height, cfg_local.padding_top, cfg_local.padding_bottom, + &in_slice_height, &out_slice_height)); + + /* mli_in tensor contains batches of HWC tensors. so it is a 4 dimensional + tensor. because the mli kernel will process one HWC tensor at a time, the 4 + dimensional tensor needs to be sliced into nBatch 3 dimensional tensors. on + top of that there could be a need to also slice in the Height dimension. + for that the sliceHeight has been calculated. The tensor slicer is + configured that it will completely slice the nBatch dimension (0) and slice + the height dimension (1) in chunks of 'sliceHeight' */ + ops::micro::TensorSlicer in_slice(data.mli_in.MliTensor(), height_dimension, + in_slice_height, cfg_local.padding_top, + cfg_local.padding_bottom, overlap); + ops::micro::TensorSlicer out_slice(data.mli_out.MliTensor(), height_dimension, + out_slice_height); + + /* is_local indicates that the tensor is already in local memory, + so in that case the original tensor can be used, + and there is no need to copy it to the local tensor*/ + mli_tensor* in_ptr = in_is_local ? in_slice.Sub() : &in_local; + mli_tensor* out_ptr = out_is_local ? out_slice.Sub() : &out_local; + + while (!out_slice.Done()) { + if (!out_is_local) { + ops::micro::PrepareLocalTensor(out_slice.Sub(), &out_local); + ops::micro::PrepareLocalTensor(in_slice.Sub(), &in_local); + } + cfg_local.padding_top = in_slice.GetPaddingPre(); + cfg_local.padding_bottom = in_slice.GetPaddingPost(); + + mli_mov_tensor_sync(in_slice.Sub(), ©_config, in_ptr); + if (pooling_type == AveragePooling) { + TFLITE_DCHECK(data.p_mli_krn_avepool_hwc_sa8 != nullptr); + data.p_mli_krn_avepool_hwc_sa8(in_ptr, &cfg_local, out_ptr); + } else if (pooling_type == MaxPooling) { + TFLITE_DCHECK(data.p_mli_krn_maxpool_hwc_sa8 != nullptr); + data.p_mli_krn_maxpool_hwc_sa8(in_ptr, &cfg_local, out_ptr); + } + mli_mov_tensor_sync(out_ptr, ©_config, out_slice.Sub()); + + in_slice.Next(); + out_slice.Next(); + } + return kTfLiteOk; +} + +void AverageEvalQuantized(TfLiteContext* context, const TfLiteNode* node, + const TfLitePoolParams* params, const OpData& data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + TFLITE_DCHECK(input->type == kTfLiteInt8); + + PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.quantized_activation_min = data.activation_min; + op_params.quantized_activation_max = data.activation_max; + + reference_integer_ops::AveragePool( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf("Type %s (%d) is not supported by ARC MLI Library.", + TfLiteTypeGetName(input->type), input->type); +#endif +} + +void MaxEvalFloat(TfLiteContext* context, TfLiteNode* node, + TfLitePoolParams* params, const OpData& data, + const TfLiteEvalTensor* input, TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + tflite::PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.float_activation_min = data.activation_min_f32; + op_params.float_activation_max = data.activation_max_f32; + reference_ops::MaxPool(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf( + + "Node configuration or type %s (%d) is not supported by ARC MLI Library.", + TfLiteTypeGetName(input->type), input->type); +#endif +} + +void MaxEvalQuantized(TfLiteContext* context, TfLiteNode* node, + TfLitePoolParams* params, const OpData& data, + const TfLiteEvalTensor* input, TfLiteEvalTensor* output) { +#if !defined(TF_LITE_STRIP_REFERENCE_IMPL) + TFLITE_DCHECK(input->type == kTfLiteInt8); + tflite::PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data.padding.height; + op_params.padding_values.width = data.padding.width; + op_params.quantized_activation_min = data.activation_min; + op_params.quantized_activation_max = data.activation_max; + + reference_integer_ops::MaxPool(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#else + MicroPrintf( + + "Node configuration or type %s (%d) is not supported by ARC MLI Library.", + TfLiteTypeGetName(input->type), input->type); +#endif +} + +TfLiteStatus AverageEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + // Inputs and outputs share the same type, guaranteed by the converter. + switch (input->type) { + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + AverageEvalFloat(context, node, params, data, input, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + if (data.is_mli_applicable) { + EvalMli(context, params, data, input, output, AveragePooling); + } else { + AverageEvalQuantized(context, node, params, data, input, output); + } + break; + default: + MicroPrintf("Input type %s is not currently supported", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus MaxEval(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + switch (input->type) { + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + MaxEvalFloat(context, node, params, data, input, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + if (data.is_mli_applicable) { + EvalMli(context, params, data, input, output, MaxPooling); + } else { + MaxEvalQuantized(context, node, params, data, input, output); + } + break; + default: + MicroPrintf("Type %s not currently supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_AVERAGE_POOL_2D() { + return tflite::micro::RegisterOp(Init, Prepare, AverageEval); +} + +TfLiteRegistration Register_MAX_POOL_2D() { + return tflite::micro::RegisterOp(Init, Prepare, MaxEval); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP == 1 + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +#include "sl_mvp_ml_pooling.h" + +namespace tflite { +namespace sl { +namespace pooling { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +enum op_support { kMvp, kCmsisNN, kTFLMrefF32}; + +struct OpData { + float activation_min_f32; + float activation_max_f32; + sli_mvp_ml_pooling_s8_params_t op_params; + op_support supported; + int buffer_idx; +}; + +} // namespace + + +void* Init(TfLiteContext* context, const char* buffer, size_t length) +{ + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) +{ + OpData* data = static_cast(node->user_data); + auto* params = reinterpret_cast(node->builtin_data); + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + + data->op_params.padding = params->padding == kTfLitePaddingSame; + data->op_params.stride_height = params->stride_height; + data->op_params.stride_width = params->stride_width; + data->op_params.filter_height = params->filter_height; + data->op_params.filter_width = params->filter_width; + data->op_params.batches = MatchingDim(GetTensorShape(input), 0, + GetTensorShape(output), 0); + data->op_params.channels = MatchingDim(GetTensorShape(input), 3, + GetTensorShape(output), 3); + data->op_params.input_height = SizeOfDimension(input, 1); + data->op_params.input_width = SizeOfDimension(input, 2); + data->op_params.output_height = SizeOfDimension(output, 1); + data->op_params.output_width = SizeOfDimension(output, 2); + + int out_height, out_width; + auto padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, + 1, 1, // dilation rate height/width. + data->op_params.input_height, data->op_params.input_width, + params->filter_height, params->filter_width, + params->padding, + &out_height, &out_width); + TFLITE_DCHECK_EQ(out_height, data->op_params.output_height); + TFLITE_DCHECK_EQ(out_width, data->op_params.output_width); + data->op_params.pad_height = padding.height; + data->op_params.pad_width = padding.width; + + if (input->type == kTfLiteFloat32) { + data->supported = kTFLMrefF32; + CalculateActivationRange(params->activation, + &data->activation_min_f32, + &data->activation_max_f32); + } else { + CalculateActivationRangeQuantized(context, params->activation, output, + reinterpret_cast(&data->op_params.output_activation_min), + reinterpret_cast(&data->op_params.output_activation_max)); + if (input->type != kTfLiteInt8) { + TF_LITE_KERNEL_LOG(context, "Type %s not currently supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + } + + return kTfLiteOk; +} + +TfLiteStatus AveragePrepare(TfLiteContext* context, TfLiteNode* node) +{ + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + + TfLiteStatus status = Prepare(context, node); + + if (status == kTfLiteOk) { + if (input->type == kTfLiteInt8) { + data->supported = sli_mvp_ml_average_pooling_s8_is_supported(&data->op_params) + ? kMvp : kCmsisNN; + if (data->supported == kCmsisNN) { + const int32_t buffer_size = arm_avgpool_s8_get_buffer_size( + data->op_params.output_width, + data->op_params.channels); + + if (buffer_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, buffer_size, &data->buffer_idx)); + } else { + data->buffer_idx = -1; + } + } + } + } + return status; +} + +TfLiteStatus MaxPrepare(TfLiteContext* context, TfLiteNode* node) +{ + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + + TfLiteStatus status = Prepare(context, node); + + if (status == kTfLiteOk) { + if (input->type == kTfLiteInt8) { + data->supported = sli_mvp_ml_max_pooling_s8_is_supported(&data->op_params) + ? kMvp : kCmsisNN; + } + } + + return status; +} + +TfLiteStatus AverageEval(TfLiteContext* context, TfLiteNode* node) +{ + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + data->op_params.input = tflite::micro::GetTensorData(input); + data->op_params.output = tflite::micro::GetTensorData(output); + + if (data->supported == kMvp) { + // Use MVP accelerated kernel. + TF_LITE_ENSURE_EQ(context, + SL_STATUS_OK, + sli_mvp_ml_average_pooling_s8(&data->op_params)); + + } else if (data->supported == kCmsisNN) { + // Use CMSIS-NN optimized kernel. + cmsis_nn_dims input_dims; + input_dims.n = 1; + input_dims.h = data->op_params.input_height; + input_dims.w = data->op_params.input_width; + input_dims.c = data->op_params.channels; + + cmsis_nn_dims output_dims; + output_dims.n = 1; + output_dims.h = data->op_params.output_height; + output_dims.w = data->op_params.output_width; + output_dims.c = data->op_params.channels; + + cmsis_nn_pool_params pool_params; + pool_params.stride.h = data->op_params.stride_height; + pool_params.stride.w = data->op_params.stride_width; + pool_params.padding.h = data->op_params.pad_height; + pool_params.padding.w = data->op_params.pad_width; + pool_params.activation.min = data->op_params.output_activation_min; + pool_params.activation.max = data->op_params.output_activation_max; + + cmsis_nn_dims filter_dims; + filter_dims.n = 1; + filter_dims.h = data->op_params.filter_height; + filter_dims.w = data->op_params.filter_width; + filter_dims.c = 1; + + cmsis_nn_context ctx; + ctx.buf = nullptr; + ctx.size = 0; + if (data->buffer_idx > -1) { + ctx.buf = context->GetScratchBuffer(context, data->buffer_idx); + } + + TFLITE_DCHECK_EQ( + arm_avgpool_s8(&ctx, &pool_params, &input_dims, + data->op_params.input, &filter_dims, + &output_dims, + data->op_params.output), + ARM_MATH_SUCCESS); + } else if (data->supported == kTFLMrefF32) { + #if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + // Use TFLM reference kernel. + tflite::PoolParams op_params; + op_params.stride_height = data->op_params.stride_height; + op_params.stride_width = data->op_params.stride_width; + op_params.filter_height = data->op_params.filter_height; + op_params.filter_width = data->op_params.filter_width; + op_params.padding_values.height = data->op_params.pad_height; + op_params.padding_values.width = data->op_params.pad_width; + op_params.float_activation_min = data->activation_min_f32; + op_params.float_activation_max = data->activation_max_f32; + reference_ops::AveragePool(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + } else { + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteStatus MaxEval(TfLiteContext* context, TfLiteNode* node) +{ + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + data->op_params.input = tflite::micro::GetTensorData(input); + data->op_params.output = tflite::micro::GetTensorData(output); + + if (data->supported == kMvp) { + // Use MVP accelerated kernel. + TF_LITE_ENSURE_EQ(context, + SL_STATUS_OK, + sli_mvp_ml_max_pooling_s8(&data->op_params)); + + } else if (data->supported == kCmsisNN) { + // Use CMSIS-NN optimized kernel. + cmsis_nn_dims input_dims; + input_dims.n = 1; + input_dims.h = data->op_params.input_height; + input_dims.w = data->op_params.input_width; + input_dims.c = data->op_params.channels; + + cmsis_nn_dims output_dims; + output_dims.n = 1; + output_dims.h = data->op_params.output_height; + output_dims.w = data->op_params.output_width; + output_dims.c = data->op_params.channels; + + cmsis_nn_pool_params pool_params; + pool_params.stride.h = data->op_params.stride_height; + pool_params.stride.w = data->op_params.stride_width; + pool_params.padding.h = data->op_params.pad_height; + pool_params.padding.w = data->op_params.pad_width; + pool_params.activation.min = data->op_params.output_activation_min; + pool_params.activation.max = data->op_params.output_activation_max; + + cmsis_nn_dims filter_dims; + filter_dims.n = 1; + filter_dims.h = data->op_params.filter_height; + filter_dims.w = data->op_params.filter_width; + filter_dims.c = 1; + + cmsis_nn_context ctx; + ctx.buf = nullptr; + ctx.size = 0; + + TFLITE_DCHECK_EQ( + arm_max_pool_s8(&ctx, &pool_params, &input_dims, + data->op_params.input, &filter_dims, + &output_dims, + data->op_params.output), + ARM_MATH_SUCCESS); + } else if (data->supported == kTFLMrefF32) { + #if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + #endif + + // Use TFLM reference kernel. + tflite::PoolParams op_params; + op_params.stride_height = data->op_params.stride_height; + op_params.stride_width = data->op_params.stride_width; + op_params.filter_height = data->op_params.filter_height; + op_params.filter_width = data->op_params.filter_width; + op_params.padding_values.height = data->op_params.pad_height; + op_params.padding_values.width = data->op_params.pad_width; + op_params.float_activation_min = data->activation_min_f32; + op_params.float_activation_max = data->activation_max_f32; + reference_ops::MaxPool(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + } else { + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace pooling +} // namespace sl + +TfLiteRegistration Register_MAX_POOL_2D() { + static TfLiteRegistration max_pool_registration = { + /*init=*/sl::pooling::Init, + /*free=*/nullptr, + /*prepare=*/sl::pooling::MaxPrepare, + /*invoke=*/sl::pooling::MaxEval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0 + }; + + return max_pool_registration; +} + +// Just to keep all_ops_resolver() happy during development ... +TfLiteRegistration Register_AVERAGE_POOL_2D() { + static TfLiteRegistration avg_pool_registration = { + /*init=*/sl::pooling::Init, + /*free=*/nullptr, + /*prepare=*/sl::pooling::AveragePrepare, + /*invoke=*/sl::pooling::AverageEval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0 + }; + + return avg_pool_registration; +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#if ESP_NN +#include "edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h" +#endif + +#include + +long long pooling_total_time = 0; + +namespace tflite { + +namespace { +#if ESP_NN +void AverageEvalQuantized(TfLiteContext* context, const TfLiteNode* node, + const TfLitePoolParams* params, const OpDataPooling* data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + + const int stride_height = params->stride_height; + const int stride_width = params->stride_width; + const int filter_height = params->filter_height; + const int filter_width = params->filter_width; + const int activation_min = data->activation_min; + const int activation_max = data->activation_max; + const int pad_height = data->padding.height; + const int pad_width = data->padding.width; + + const RuntimeShape& input_shape = tflite::micro::GetTensorShape(input); + const RuntimeShape& output_shape = tflite::micro::GetTensorShape(output); + TFLITE_DCHECK_LE(activation_min, activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + + const int8_t *input_data = tflite::micro::GetTensorData(input); + int8_t *output_data = tflite::micro::GetTensorData(output); + + const int input_size = input_width * input_height * depth; + const int output_size = output_width * output_height * depth; + + if (depth % 4 == 0) { // S3 version only supports channels multiple of 4 + for (int batch = 0; batch < batches; ++batch) { + esp_nn_avg_pool_s8(input_data, input_width, input_height, + output_data, output_width, output_height, + stride_width, stride_height, + filter_width, filter_height, + pad_width, pad_height, + activation_min, activation_max, depth); + input_data += input_size; + output_data += output_size; + } + } else { + for (int batch = 0; batch < batches; ++batch) { + esp_nn_avg_pool_s8_ansi(input_data, input_width, input_height, + output_data, output_width, output_height, + stride_width, stride_height, + filter_width, filter_height, + pad_width, pad_height, + activation_min, activation_max, depth); + input_data += input_size; + output_data += output_size; + } + } +} + +void MaxEvalQuantized(TfLiteContext* context, TfLiteNode* node, + TfLitePoolParams* params, const OpDataPooling* data, + const TfLiteEvalTensor* input, TfLiteEvalTensor* output) { + + const int stride_height = params->stride_height; + const int stride_width = params->stride_width; + const int filter_height = params->filter_height; + const int filter_width = params->filter_width; + const int activation_min = data->activation_min; + const int activation_max = data->activation_max; + const int pad_height = data->padding.height; + const int pad_width = data->padding.width; + + const RuntimeShape& input_shape = tflite::micro::GetTensorShape(input); + const RuntimeShape& output_shape = tflite::micro::GetTensorShape(output); + TFLITE_DCHECK_LE(activation_min, activation_max); + TFLITE_DCHECK_EQ(input_shape.DimensionsCount(), 4); + TFLITE_DCHECK_EQ(output_shape.DimensionsCount(), 4); + const int batches = MatchingDim(input_shape, 0, output_shape, 0); + const int depth = MatchingDim(input_shape, 3, output_shape, 3); + const int input_height = input_shape.Dims(1); + const int input_width = input_shape.Dims(2); + const int output_height = output_shape.Dims(1); + const int output_width = output_shape.Dims(2); + + const int8_t *input_data = tflite::micro::GetTensorData(input); + int8_t *output_data = tflite::micro::GetTensorData(output); + + const int input_size = input_width * input_height * depth; + const int output_size = output_width * output_height * depth; + if (depth % 4 == 0) { // S3 version only supports channels multiple of 4 + for (int batch = 0; batch < batches; ++batch) { + esp_nn_max_pool_s8(input_data, input_width, input_height, + output_data, output_width, output_height, + stride_width, stride_height, + filter_width, filter_height, + pad_width, pad_height, + activation_min, activation_max, depth); + input_data += input_size; + output_data += output_size; + } + } else { + for (int batch = 0; batch < batches; ++batch) { + esp_nn_max_pool_s8_ansi(input_data, input_width, input_height, + output_data, output_width, output_height, + stride_width, stride_height, + filter_width, filter_height, + pad_width, pad_height, + activation_min, activation_max, depth); + input_data += input_size; + output_data += output_size; + } + } +} +#endif + +TfLiteStatus AverageEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataPooling* data = + static_cast(node->user_data); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + long long start_time = esp_timer_get_time(); + // Inputs and outputs share the same type, guaranteed by the converter. + switch (input->type) { + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + AveragePoolingEvalFloat(context, node, params, data, input, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif +#if ESP_NN + AverageEvalQuantized(context, node, params, data, input, output); +#else + AveragePoolingEvalQuantized(context, node, params, data, input, output); +#endif + break; + default: + TF_LITE_KERNEL_LOG(context, "Input type %s is not currently supported", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + pooling_total_time += esp_timer_get_time() - start_time; + return kTfLiteOk; +} + +TfLiteStatus MaxEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataPooling* data = + static_cast(node->user_data); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + long long start_time = esp_timer_get_time(); + switch (input->type) { + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + MaxPoolingEvalFloat(context, node, params, data, input, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif +#if ESP_NN + MaxEvalQuantized(context, node, params, data, input, output); +#else + MaxPoolingEvalQuantized(context, node, params, data, input, output); +#endif + break; + default: + TF_LITE_KERNEL_LOG(context, "Type %s not currently supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + pooling_total_time += esp_timer_get_time() - start_time; + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataPooling)); +} + +} // namespace + +TfLiteRegistration Register_AVERAGE_POOL_2D() { + return tflite::micro::RegisterOp(Init, PoolingPrepare, AverageEval); +} + +TfLiteRegistration Register_MAX_POOL_2D() { + return tflite::micro::RegisterOp(Init, PoolingPrepare, MaxEval); +} + +} // namespace tflite + +#else +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +TfLiteStatus AverageEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataPooling* data = + static_cast(node->user_data); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + // Inputs and outputs share the same type, guaranteed by the converter. + switch (input->type) { + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + AveragePoolingEvalFloat(context, node, params, data, input, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_AVERAGE_POOL_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + AveragePoolingEvalQuantized(context, node, params, data, input, + output); + break; + case kTfLiteInt16: + AveragePoolingEvalQuantized(context, node, params, data, input, + output); + break; + default: + MicroPrintf("Input type %s is not currently supported", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus MaxEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataPooling* data = + static_cast(node->user_data); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kPoolingInputTensor); + TfLiteEvalTensor* output = + micro::GetEvalOutput(context, node, kPoolingOutputTensor); + + switch (input->type) { + case kTfLiteFloat32: +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + MaxPoolingEvalFloat(context, node, params, data, input, output); + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_MAX_POOL_2D_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + MaxPoolingEvalQuantized(context, node, params, data, input, + output); + break; + case kTfLiteInt16: + MaxPoolingEvalQuantized(context, node, params, data, input, + output); + break; + default: + MicroPrintf("Type %s not currently supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataPooling)); +} + +} // namespace + +TfLiteRegistration Register_AVERAGE_POOL_2D() { + return tflite::micro::RegisterOp(Init, PoolingPrepare, AverageEval); +} + +TfLiteRegistration Register_MAX_POOL_2D() { + return tflite::micro::RegisterOp(Init, PoolingPrepare, MaxEval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h new file mode 100644 index 0000000..d33aa23 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h @@ -0,0 +1,142 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_POOLING_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_POOLING_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +extern const int kPoolingInputTensor; +extern const int kPoolingOutputTensor; + +struct OpDataPooling { + TfLitePaddingValues padding; + int32_t activation_min; + int32_t activation_max; + float activation_min_f32; + float activation_max_f32; +}; + +TfLiteStatus CalculateOpDataPooling(const TfLiteContext* context, + const TfLitePoolParams* params, + const TfLiteTensor* input, + const TfLiteTensor* output, + OpDataPooling* data); + +TfLiteStatus PoolingPrepare(TfLiteContext* context, TfLiteNode* node); + +void AveragePoolingEvalFloat(const TfLiteContext* context, + const TfLiteNode* node, + const TfLitePoolParams* params, + const OpDataPooling* data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output); + +template +void AveragePoolingEvalQuantized(TfLiteContext* context, const TfLiteNode* node, + const TfLitePoolParams* params, + const OpDataPooling* data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + TFLITE_DCHECK(input->type == kTfLiteInt8 || input->type == kTfLiteInt16); + + PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data->padding.height; + op_params.padding_values.width = data->padding.width; + op_params.quantized_activation_min = data->activation_min; + op_params.quantized_activation_max = data->activation_max; + + reference_integer_ops::AveragePool(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +void MaxPoolingEvalFloat(TfLiteContext* context, TfLiteNode* node, + TfLitePoolParams* params, const OpDataPooling* data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output); + +template +void MaxPoolingEvalQuantized(TfLiteContext* context, TfLiteNode* node, + TfLitePoolParams* params, + const OpDataPooling* data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + TFLITE_DCHECK(input->type == kTfLiteInt8 || input->type == kTfLiteInt16); + + tflite::PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data->padding.height; + op_params.padding_values.width = data->padding.width; + op_params.quantized_activation_min = data->activation_min; + op_params.quantized_activation_max = data->activation_max; + + reference_integer_ops::MaxPool(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +#if defined(CMSIS_NN) +TfLiteRegistration Register_AVERAGE_POOL_2D_INT8(); + +TfLiteRegistration Register_MAX_POOL_2D_INT8(); + +TfLiteRegistration Register_AVERAGE_POOL_2D_INT16(); + +TfLiteRegistration Register_MAX_POOL_2D_INT16(); +#else +inline TfLiteRegistration Register_AVERAGE_POOL_2D_INT8() { + return tflite::Register_AVERAGE_POOL_2D(); +} + +inline TfLiteRegistration Register_MAX_POOL_2D_INT8() { + return tflite::Register_MAX_POOL_2D(); +} + +inline TfLiteRegistration Register_AVERAGE_POOL_2D_INT16() { + return tflite::Register_AVERAGE_POOL_2D(); +} + +inline TfLiteRegistration Register_MAX_POOL_2D_INT16() { + return tflite::Register_MAX_POOL_2D(); +} +#endif +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_POOLING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling_common.cpp new file mode 100644 index 0000000..8eb66e7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling_common.cpp @@ -0,0 +1,128 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h" + +namespace tflite { + +const int kPoolingInputTensor = 0; +const int kPoolingOutputTensor = 0; + +TfLiteStatus CalculateOpDataPooling(const TfLiteContext* context, + const TfLitePoolParams* params, + const TfLiteTensor* input, + const TfLiteTensor* output, + OpDataPooling* data) { + // input: batch, height, width, channel + int height = SizeOfDimension(input, 1); + int width = SizeOfDimension(input, 2); + + int out_height, out_width; + + data->padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, + /*dilation_rate_height=*/1, + /*dilation_rate_width=*/1, height, width, params->filter_height, + params->filter_width, params->padding, &out_height, &out_width); + + return kTfLiteOk; +} + +TfLiteStatus PoolingPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + auto* params = reinterpret_cast(node->builtin_data); + + TFLITE_DCHECK(node->user_data != nullptr); + OpDataPooling* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kPoolingInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kPoolingOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_STATUS( + CalculateOpDataPooling(context, params, input, output, data)); + + if (input->type == kTfLiteFloat32) { + CalculateActivationRange(params->activation, &data->activation_min_f32, + &data->activation_max_f32); + } else if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + CalculateActivationRangeQuantized(context, params->activation, output, + &data->activation_min, + &data->activation_max); + } else { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +void AveragePoolingEvalFloat(const TfLiteContext* context, + const TfLiteNode* node, + const TfLitePoolParams* params, + const OpDataPooling* data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data->padding.height; + op_params.padding_values.width = data->padding.width; + op_params.float_activation_min = data->activation_min_f32; + op_params.float_activation_max = data->activation_max_f32; + reference_ops::AveragePool(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +void MaxPoolingEvalFloat(TfLiteContext* context, TfLiteNode* node, + TfLitePoolParams* params, const OpDataPooling* data, + const TfLiteEvalTensor* input, + TfLiteEvalTensor* output) { + tflite::PoolParams op_params; + op_params.stride_height = params->stride_height; + op_params.stride_width = params->stride_width; + op_params.filter_height = params->filter_height; + op_params.filter_width = params->filter_width; + op_params.padding_values.height = data->padding.height; + op_params.padding_values.width = data->padding.width; + op_params.float_activation_min = data->activation_min_f32; + op_params.float_activation_max = data->activation_max_f32; + reference_ops::MaxPool(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.cpp new file mode 100644 index 0000000..bceb7ff --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.cpp @@ -0,0 +1,75 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/prelu.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +void* PreluInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(PreluParams)); +} + +TfLiteStatus PreluEval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const PreluParams& params = + *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* alpha = tflite::micro::GetEvalInput(context, node, 1); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + switch (input->type) { + case kTfLiteFloat32: { + BroadcastPrelu4DSlowFloat(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(alpha), + tflite::micro::GetTensorData(alpha), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + case kTfLiteInt8: { + reference_ops::BroadcastPrelu4DSlow( + params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(alpha), + tflite::micro::GetTensorData(alpha), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + default: + MicroPrintf("Only float32 and uint8_t are supported currently, got %d.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } +} + +TfLiteRegistration Register_PRELU() { + return tflite::micro::RegisterOp(PreluInit, PreluPrepare, PreluEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.h new file mode 100644 index 0000000..d5b780a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.h @@ -0,0 +1,39 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_PRELU_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_PRELU_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +TfLiteStatus CalculatePreluParams(const TfLiteTensor* input, + const TfLiteTensor* alpha, + TfLiteTensor* output, PreluParams* params); + +void BroadcastPrelu4DSlowFloat(const RuntimeShape& unextended_input1_shape, + const float* input1_data, + const RuntimeShape& unextended_input2_shape, + const float* input2_data, + const RuntimeShape& unextended_output_shape, + float* output_data); + +TfLiteStatus PreluPrepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_PRELU_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu_common.cpp new file mode 100644 index 0000000..8c1f2ef --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu_common.cpp @@ -0,0 +1,105 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/prelu.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/prelu.h" + +namespace tflite { + +TfLiteStatus CalculatePreluParams(const TfLiteTensor* input, + const TfLiteTensor* alpha, + TfLiteTensor* output, PreluParams* params) { + if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + double real_multiplier_1 = static_cast(input->params.scale) / + static_cast(output->params.scale); + double real_multiplier_2 = static_cast(input->params.scale) * + static_cast(alpha->params.scale) / + static_cast(output->params.scale); + QuantizeMultiplier(real_multiplier_1, ¶ms->output_multiplier_1, + ¶ms->output_shift_1); + QuantizeMultiplier(real_multiplier_2, ¶ms->output_multiplier_2, + ¶ms->output_shift_2); + + params->input_offset = -input->params.zero_point; + params->alpha_offset = -alpha->params.zero_point; + params->output_offset = output->params.zero_point; + } + + return kTfLiteOk; +} + +void BroadcastPrelu4DSlowFloat(const RuntimeShape& unextended_input1_shape, + const float* input1_data, + const RuntimeShape& unextended_input2_shape, + const float* input2_data, + const RuntimeShape& unextended_output_shape, + float* output_data) { + TFLITE_DCHECK_LE(unextended_input1_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_input2_shape.DimensionsCount(), 4); + TFLITE_DCHECK_LE(unextended_output_shape.DimensionsCount(), 4); + const RuntimeShape output_shape = + RuntimeShape::ExtendedShape(4, unextended_output_shape); + + NdArrayDesc<4> desc1; + NdArrayDesc<4> desc2; + NdArrayDescsForElementwiseBroadcast(unextended_input1_shape, + unextended_input2_shape, &desc1, &desc2); + + for (int b = 0; b < output_shape.Dims(0); ++b) { + for (int y = 0; y < output_shape.Dims(1); ++y) { + for (int x = 0; x < output_shape.Dims(2); ++x) { + for (int c = 0; c < output_shape.Dims(3); ++c) { + auto out_idx = Offset(output_shape, b, y, x, c); + auto in1_idx = SubscriptToIndex(desc1, b, y, x, c); + auto in2_idx = SubscriptToIndex(desc2, b, y, x, c); + auto in1_val = input1_data[in1_idx]; + auto in2_val = input2_data[in2_idx]; + output_data[out_idx] = in1_val >= 0.0f ? in1_val : in1_val * in2_val; + } + } + } + } +} + +TfLiteStatus PreluPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + PreluParams* params = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* alpha = micro_context->AllocateTempInputTensor(node, 1); + TF_LITE_ENSURE(context, alpha != nullptr); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_OK(context, + CalculatePreluParams(input, alpha, output, params)); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(alpha); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.cpp new file mode 100644 index 0000000..487f502 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.cpp @@ -0,0 +1,41 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, + sizeof(OpDataQuantizeReference)); +} + +} // namespace + +TfLiteRegistration Register_QUANTIZE() { + return tflite::micro::RegisterOp(Init, PrepareQuantizeReference, + EvalQuantizeReference); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.h new file mode 100644 index 0000000..ce2c567 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.h @@ -0,0 +1,37 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_QUANTIZE_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_QUANTIZE_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +struct OpDataQuantizeReference { + tflite::QuantizationParams quantization_params; + // The scaling factor from input to output (aka the 'real multiplier') can + // be represented as a fixed point multiplier plus a left shift. + int32_t requantize_output_multiplier; + int requantize_output_shift; + + int32_t input_zero_point; +}; + +TfLiteStatus EvalQuantizeReference(TfLiteContext* context, TfLiteNode* node); +TfLiteStatus PrepareQuantizeReference(TfLiteContext* context, TfLiteNode* node); +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_QUANTIZE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize_common.cpp new file mode 100644 index 0000000..5ba29f4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize_common.cpp @@ -0,0 +1,239 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/quantize.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/requantize.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/quantize.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +TfLiteStatus PrepareQuantizeReference(TfLiteContext* context, + TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + auto* data = static_cast(node->user_data); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + // TODO(b/128934713): Add support for fixed-point per-channel quantization. + // Currently this only support affine per-layer quantization. + TF_LITE_ENSURE_EQ(context, output->quantization.type, + kTfLiteAffineQuantization); + const auto* affine_quantization = + reinterpret_cast(output->quantization.params); + TF_LITE_ENSURE(context, affine_quantization); + TF_LITE_ENSURE(context, affine_quantization->scale); + TF_LITE_ENSURE(context, affine_quantization->scale->size == 1); + + TF_LITE_ENSURE( + context, input->type == kTfLiteFloat32 || input->type == kTfLiteInt32 || + input->type == kTfLiteInt16 || input->type == kTfLiteInt8 || + input->type == kTfLiteUInt8); + TF_LITE_ENSURE(context, output->type == kTfLiteInt8 || + output->type == kTfLiteInt16 || + output->type == kTfLiteInt32 || + output->type == kTfLiteUInt8); + + if ((input->type == kTfLiteInt16 && output->type == kTfLiteInt8) || + (input->type == kTfLiteInt8 && output->type == kTfLiteInt8) || + (input->type == kTfLiteInt8 && output->type == kTfLiteUInt8) || + (input->type == kTfLiteUInt8 && output->type == kTfLiteInt8) || + (input->type == kTfLiteInt8 && output->type == kTfLiteInt16) || + (input->type == kTfLiteInt8 && output->type == kTfLiteInt32) || + (input->type == kTfLiteInt16 && output->type == kTfLiteInt16) || + (input->type == kTfLiteInt16 && output->type == kTfLiteInt32) || + (input->type == kTfLiteInt32 && output->type == kTfLiteInt8) || + (input->type == kTfLiteInt32 && output->type == kTfLiteInt16)) { + double effective_scale = static_cast(input->params.scale) / + static_cast(output->params.scale); + + QuantizeMultiplier(effective_scale, &data->requantize_output_multiplier, + &data->requantize_output_shift); + } + + data->quantization_params.zero_point = output->params.zero_point; + data->quantization_params.scale = static_cast(output->params.scale); + + data->input_zero_point = input->params.zero_point; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus EvalQuantizeReference(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + auto* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + if (input->type == kTfLiteFloat32) { + switch (output->type) { + case kTfLiteInt8: + reference_ops::AffineQuantize( + data->quantization_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt16: + reference_ops::AffineQuantize( + data->quantization_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else if (input->type == kTfLiteInt32) { + size_t size = ElementCount(*input->dims); + switch (output->type) { + case kTfLiteInt8: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt16: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else if (input->type == kTfLiteInt16) { + size_t size = ElementCount(*input->dims); + switch (output->type) { + case kTfLiteInt8: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt16: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + case kTfLiteInt32: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else if (input->type == kTfLiteInt8) { + // Int8 to Int8 requantization, required if the input and output tensors + // have different scales and/or zero points. + size_t size = ElementCount(*input->dims); + switch (output->type) { + case kTfLiteInt8: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + case kTfLiteUInt8: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt16: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt32: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else if (input->type == kTfLiteUInt8) { + size_t size = ElementCount(*input->dims); + switch (output->type) { + case kTfLiteInt8: + reference_ops::Requantize( + tflite::micro::GetTensorData(input), size, + data->requantize_output_multiplier, data->requantize_output_shift, + data->input_zero_point, data->quantization_params.zero_point, + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + } else { + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/read_variable.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/read_variable.cpp new file mode 100644 index 0000000..ba1fe4a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/read_variable.cpp @@ -0,0 +1,87 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +namespace { + +constexpr int kInputVariableId = 0; +constexpr int kOutputValue = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(NumInputs(node) == 1); + TFLITE_DCHECK(NumOutputs(node) == 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input_resource_id_tensor = + micro_context->AllocateTempInputTensor(node, kInputVariableId); + + TFLITE_DCHECK(input_resource_id_tensor != nullptr); + TFLITE_DCHECK(input_resource_id_tensor->type == kTfLiteResource); + TFLITE_DCHECK(NumElements(input_resource_id_tensor) == 1); + + micro_context->DeallocateTempTfLiteTensor(input_resource_id_tensor); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input_resource_id_tensor = + tflite::micro::GetEvalInput(context, node, kInputVariableId); + TFLITE_DCHECK(input_resource_id_tensor != nullptr); + + TfLiteEvalTensor* output_value = + tflite::micro::GetEvalOutput(context, node, kOutputValue); + TFLITE_DCHECK(output_value != nullptr); + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + MicroGraph& graph_info = micro_context->graph(); + + MicroResourceVariables* resources = graph_info.GetResourceVariables(); + if (resources == nullptr) { + MicroPrintf( + "READ_VARIABLE requires resource variables. Please create " + "ResourceVariables and pass it to the interpreter."); + return kTfLiteError; + } + TF_LITE_ENSURE_OK( + context, + resources->Read(input_resource_id_tensor->data.i32[0], output_value)); + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_READ_VARIABLE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/real.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/real.cpp new file mode 100644 index 0000000..6ec5aad --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/real.cpp @@ -0,0 +1,134 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include +#include +#include +#include + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace real { + +using std::complex; + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + if (input->type != kTfLiteComplex64 || output->type != kTfLiteFloat32) { + TF_LITE_KERNEL_LOG(context, "Types input %s (%d), output %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type, + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } + + size_t total_input_els = 1; + for (size_t dim_ix = 0; dim_ix < input->dims->size; dim_ix++) { + total_input_els *= input->dims->data[dim_ix]; + } + + size_t total_output_els = 1; + for (size_t dim_ix = 0; dim_ix < output->dims->size; dim_ix++) { + total_output_els *= output->dims->data[dim_ix]; + } + + TFLITE_DCHECK(total_input_els == total_output_els); + + return kTfLiteOk; +} + +TfLiteStatus RealEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + size_t total_input_els = 1; + for (size_t dim_ix = 0; dim_ix < input->dims->size; dim_ix++) { + total_input_els *= input->dims->data[dim_ix]; + } + + for (size_t ix = 0; ix < total_input_els; ix++) { + output->data.f[ix] = input->data.c64[ix].re; + } + + return kTfLiteOk; +} + +TfLiteStatus ImagEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + size_t total_input_els = 1; + for (size_t dim_ix = 0; dim_ix < input->dims->size; dim_ix++) { + total_input_els *= input->dims->data[dim_ix]; + } + + for (size_t ix = 0; ix < total_input_els; ix++) { + output->data.f[ix] = input->data.c64[ix].im; + } + + return kTfLiteOk; +} + +} // namespace real +} // namespace micro +} // namespace ops + +TfLiteRegistration Register_REAL() { + return {/*init=*/nullptr, + /*free=*/nullptr, + /*prepare=*/ops::micro::real::Prepare, + /*invoke=*/ops::micro::real::RealEval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +TfLiteRegistration Register_IMAG() { + return {/*init=*/nullptr, + /*free=*/nullptr, + /*prepare=*/ops::micro::real::Prepare, + /*invoke=*/ops::micro::real::ImagEval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.cpp new file mode 100644 index 0000000..b346282 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.cpp @@ -0,0 +1,86 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/reduce.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mean.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +void* InitReduce(TfLiteContext* context, const char* buffer, size_t length) { + return context->AllocatePersistentBuffer(context, sizeof(OpDataReduce)); +} + +TfLiteStatus PrepareMax(TfLiteContext* context, TfLiteNode* node) { + return PrepareMinMaxHelper(context, node, + static_cast(node->user_data)); +} + +TfLiteStatus PrepareMin(TfLiteContext* context, TfLiteNode* node) { + return PrepareMinMaxHelper(context, node, + static_cast(node->user_data)); +} + +TfLiteStatus PrepareMeanOrSum(TfLiteContext* context, TfLiteNode* node) { + return PrepareMeanOrSumHelper(context, node, + static_cast(node->user_data)); +} + +TfLiteStatus EvalMean(TfLiteContext* context, TfLiteNode* node) { + return EvalMeanHelper(context, node, + static_cast(node->user_data)); +} + +TfLiteStatus EvalMax(TfLiteContext* context, TfLiteNode* node) { + OpDataReduce* op_data = static_cast(node->user_data); + return EvalMaxHelper(context, node, op_data); +} + +TfLiteStatus EvalMin(TfLiteContext* context, TfLiteNode* node) { + OpDataReduce* op_data = static_cast(node->user_data); + return EvalMinHelper(context, node, op_data); +} + +TfLiteStatus EvalSum(TfLiteContext* context, TfLiteNode* node) { + return EvalSumHelper(context, node, + static_cast(node->user_data)); +} + +TfLiteRegistration Register_MEAN() { + return tflite::micro::RegisterOp(InitReduce, PrepareMeanOrSum, EvalMean); +} + +TfLiteRegistration Register_REDUCE_MAX() { + return tflite::micro::RegisterOp(InitReduce, PrepareMax, EvalMax); +} + +TfLiteRegistration Register_REDUCE_MIN() { + return tflite::micro::RegisterOp(InitReduce, PrepareMin, EvalMin); +} + +TfLiteRegistration Register_SUM() { + return tflite::micro::RegisterOp(InitReduce, PrepareMeanOrSum, EvalSum); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.h new file mode 100644 index 0000000..6780df4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.h @@ -0,0 +1,71 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_REDUCE_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_REDUCE_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +extern const int kMaxNumberOfAxis; +extern const int kMaxNumberOfReducedAxis; + +struct OpDataReduce { + int32_t multiplier; + int shift; + int temp_buffer_idx; + int resolved_axis_idx; + int input_zp; + float input_scale; + int output_zp; + float output_scale; + int num_output_elements; + int num_axis; +}; + +TfLiteStatus PrepareMinMaxHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data); + +TfLiteStatus PrepareMeanOrSumHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data); + +TfLiteStatus EvalMaxHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data); + +TfLiteStatus EvalMinHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data); + +TfLiteStatus EvalMeanHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data); + +TfLiteStatus EvalSumHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data); + +void ReduceResolveAxis(const int* axis_data, int axis_count, + MeanParams* op_params); + +TfLiteRegistration Register_MEAN(); +TfLiteRegistration Register_REDUCE_MAX(); +TfLiteRegistration Register_REDUCE_MIN(); +TfLiteRegistration Register_SUM(); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_REDUCE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce_common.cpp new file mode 100644 index 0000000..a2c5c38 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce_common.cpp @@ -0,0 +1,417 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/mean.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/reduce.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +const int kMaxNumberOfAxis = 5; +const int kMaxNumberOfReducedAxis = 2; + +TfLiteStatus PrepareSimple(TfLiteContext* context, TfLiteNode* node, + int32_t* multiplier, int* shift) { + MicroContext* micro_context = GetMicroContext(context); + + // Inputs Tensor (dtype depends on quantization): + // [0] = Input + // [1] = Axis + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + + // Outputs Tensor (dtype depends on quantization): + // [0] = Output + + // Validate number of inputs and outputs + TF_LITE_ENSURE_EQ(context, node->inputs->size, 2); + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + + // Validate axis type + TfLiteTensor* axis = micro_context->AllocateTempInputTensor(node, 1); + TF_LITE_ENSURE(context, axis != nullptr); + TF_LITE_ENSURE_TYPES_EQ(context, axis->type, kTfLiteInt32); + + if (input->type == kTfLiteInt8) { + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + const double real_multiplier = static_cast(input->params.scale) / + static_cast(output->params.scale); + QuantizeMultiplier(real_multiplier, multiplier, shift); + micro_context->DeallocateTempTfLiteTensor(output); + } + micro_context->DeallocateTempTfLiteTensor(axis); + micro_context->DeallocateTempTfLiteTensor(input); + return kTfLiteOk; +} + +TfLiteStatus PrepareMinMaxHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data) { + TF_LITE_ENSURE_OK(context, PrepareSimple(context, node, &op_data->multiplier, + &op_data->shift)); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TfLiteTensor* axis = micro_context->AllocateTempInputTensor(node, 1); + + op_data->input_scale = input->params.scale; + op_data->output_scale = output->params.scale; + op_data->num_output_elements = NumElements(output); + + context->RequestScratchBufferInArena(context, sizeof(int) * input->dims->size, + &op_data->temp_buffer_idx); + context->RequestScratchBufferInArena( + context, sizeof(int) * static_cast(ElementCount(*axis->dims)), + &op_data->resolved_axis_idx); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(axis); + return kTfLiteOk; +} + +TfLiteStatus PrepareMeanOrSumHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data) { + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TfLiteTensor* axis = micro_context->AllocateTempInputTensor(node, 1); + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + const double real_multiplier = static_cast(input->params.scale) / + static_cast(output->params.scale); + QuantizeMultiplier(real_multiplier, &op_data->multiplier, &op_data->shift); + } + + int output_size = NumElements(output); + op_data->num_axis = NumElements(axis); + + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + context->RequestScratchBufferInArena(context, output_size * sizeof(int32_t), + &op_data->temp_buffer_idx); + op_data->input_zp = input->params.zero_point; + op_data->input_scale = input->params.scale; + op_data->output_zp = output->params.zero_point; + op_data->output_scale = output->params.scale; + } + + TF_LITE_ENSURE_OK( + context, + PrepareSimple(context, node, &(op_data->multiplier), &(op_data->shift))); + // TODO(b/144955155): Support uint8_t(b/144955155) and int8_t(b/144955018) + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(axis); + return kTfLiteOk; +} + +void ResolveAxis(const int* axis_data, int axis_count, + tflite::MeanParams* op_params) { + int i = 0; + for (; i < axis_count; ++i) { + op_params->axis[i] = static_cast(axis_data[i]); + } + for (; i < 4; ++i) { + op_params->axis[i] = 1; + } + op_params->axis_count = axis_count; +} + +template +TfLiteStatus QuantizedMeanOrSum(TfLiteContext* context, TfLiteNode* node, + int* temp_index, int* resolved_axis, + int32_t* temp_sum, OpDataReduce* op_data, + bool compute_sum) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 1); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TfLiteReducerParams* params = + static_cast(node->builtin_data); + + bool result = reference_ops::QuantizedMeanOrSumExtraArgs( + tflite::micro::GetTensorData(input), op_data->input_zp, + op_data->input_scale, &input->dims->data[0], input->dims->size, + tflite::micro::GetTensorData(output), op_data->output_scale, + op_data->multiplier, op_data->shift, op_data->output_zp, + &output->dims->data[0], output->dims->size, + tflite::micro::GetTensorData(axis), op_data->num_axis, + params->keep_dims, temp_index, resolved_axis, temp_sum, compute_sum); + TF_LITE_ENSURE(context, result); + + return kTfLiteOk; +} + +template +TfLiteStatus Mean(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data, int* temp_index, int* resolved_axis, + U* temp_sum) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 1); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TfLiteReducerParams* params = + static_cast(node->builtin_data); + + reference_ops::Mean( + tflite::micro::GetTensorData(input), &input->dims->data[0], + input->dims->size, tflite::micro::GetTensorData(output), + &output->dims->data[0], output->dims->size, + tflite::micro::GetTensorData(axis), op_data->num_axis, + params->keep_dims, temp_index, resolved_axis, temp_sum); + + return kTfLiteOk; +} + +template +TfLiteStatus EvalIntegerMean(TfLiteContext* context, TfLiteNode* node, + int num_axis, OpDataReduce* op_data, + int* temp_index, int* resolved_axis) { + int32_t* temp_sum = static_cast( + context->GetScratchBuffer(context, op_data->temp_buffer_idx)); + + if (op_data->input_zp == op_data->output_zp && + op_data->input_scale == op_data->output_scale) { + Mean(context, node, op_data, temp_index, + resolved_axis, temp_sum); + } else { + QuantizedMeanOrSum(context, node, temp_index, resolved_axis, + temp_sum, op_data, /*compute_sum=*/false); + } + return kTfLiteOk; +} + +TfLiteStatus EvalMeanHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 1); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TfLiteReducerParams* params = + reinterpret_cast(node->builtin_data); + + int num_axis = static_cast(ElementCount(*axis->dims)); + int temp_index[kMaxNumberOfAxis]; + int resolved_axis[kMaxNumberOfReducedAxis]; + + switch (input->type) { + case kTfLiteFloat32: { + tflite::MeanParams op_params; + ResolveAxis(tflite::micro::GetTensorData(axis), num_axis, + &op_params); + + // Special case mean implementation exists for 4D mean across axes 1 + // and 2. + bool special_case_4d_axes_1_and_2 = + input->dims->size == 4 && op_params.axis_count == 2 && + ((op_params.axis[0] == 1 && op_params.axis[1] == 2) || + (op_params.axis[0] == 2 && op_params.axis[1] == 1)); + + // Defer to specialized implementation for 4D Mean across axes 1 & 2. + if (params->keep_dims && special_case_4d_axes_1_and_2) { + reference_ops::Mean(op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + TF_LITE_ENSURE( + context, + reference_ops::Mean( + tflite::micro::GetTensorData(input), input->dims->data, + input->dims->size, tflite::micro::GetTensorData(output), + output->dims->data, output->dims->size, + tflite::micro::GetTensorData(axis), num_axis, + params->keep_dims, temp_index, resolved_axis, + tflite::micro::GetTensorData(output))); + } + } break; + case kTfLiteInt8: { + TF_LITE_ENSURE_OK( + context, EvalIntegerMean(context, node, num_axis, op_data, + temp_index, resolved_axis)); + } break; + case kTfLiteInt16: { + TF_LITE_ENSURE_OK( + context, EvalIntegerMean(context, node, num_axis, op_data, + temp_index, resolved_axis)); + } break; + default: + TF_LITE_ENSURE_MSG(context, false, + "Currently, only float32, int8 or int16 input type " + "is supported."); + } + return kTfLiteOk; +} + +TfLiteStatus EvalMaxHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 1); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + TfLiteReducerParams* params = + static_cast(node->builtin_data); + + // Interpret an axis tensor with null dimensions as a scalar + int num_axis = static_cast(ElementCount(*axis->dims)); + int* temp_buffer = static_cast( + context->GetScratchBuffer(context, op_data->temp_buffer_idx)); + int* resolved_axis = static_cast( + context->GetScratchBuffer(context, op_data->resolved_axis_idx)); + switch (input->type) { + case kTfLiteFloat32: + TF_LITE_ENSURE( + context, + reference_ops::ReduceGeneric( + tflite::micro::GetTensorData(input), input->dims->data, + input->dims->size, tflite::micro::GetTensorData(output), + output->dims->data, output->dims->size, + tflite::micro::GetTensorData(axis), num_axis, + params->keep_dims, temp_buffer, resolved_axis, + std::numeric_limits::lowest(), + [](const float current, const float in) -> float { + return (in > current) ? in : current; + })); + break; + case kTfLiteInt8: + TF_LITE_ENSURE_EQ(context, static_cast(op_data->input_scale), + static_cast(op_data->output_scale)); + TF_LITE_ENSURE_EQ(context, op_data->input_zp, op_data->output_zp); + TF_LITE_ENSURE( + context, + reference_ops::ReduceGeneric( + tflite::micro::GetTensorData(input), input->dims->data, + input->dims->size, tflite::micro::GetTensorData(output), + output->dims->data, output->dims->size, + tflite::micro::GetTensorData(axis), num_axis, + params->keep_dims, temp_buffer, resolved_axis, + std::numeric_limits::lowest(), + [](const int8_t current, const int8_t in) -> int8_t { + return (in > current) ? in : current; + })); + break; + default: + MicroPrintf("Only float32 and int8 types are supported."); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus EvalMinHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 1); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + TfLiteReducerParams* params = + static_cast(node->builtin_data); + + // Interpret an axis tensor with null dimensions as a scalar + int num_axis = static_cast(ElementCount(*axis->dims)); + int* temp_buffer = static_cast( + context->GetScratchBuffer(context, op_data->temp_buffer_idx)); + int* resolved_axis = static_cast( + context->GetScratchBuffer(context, op_data->resolved_axis_idx)); + switch (input->type) { + case kTfLiteFloat32: + TF_LITE_ENSURE( + context, + reference_ops::ReduceGeneric( + tflite::micro::GetTensorData(input), input->dims->data, + input->dims->size, tflite::micro::GetTensorData(output), + output->dims->data, output->dims->size, + tflite::micro::GetTensorData(axis), num_axis, + params->keep_dims, temp_buffer, resolved_axis, + std::numeric_limits::max(), + [](const float current, const float in) -> float { + return (in < current) ? in : current; + })); + break; + case kTfLiteInt8: + TF_LITE_ENSURE_EQ(context, static_cast(op_data->input_scale), + static_cast(op_data->output_scale)); + TF_LITE_ENSURE_EQ(context, op_data->input_zp, op_data->output_zp); + TF_LITE_ENSURE( + context, + reference_ops::ReduceGeneric( + tflite::micro::GetTensorData(input), input->dims->data, + input->dims->size, tflite::micro::GetTensorData(output), + output->dims->data, output->dims->size, + tflite::micro::GetTensorData(axis), num_axis, + params->keep_dims, temp_buffer, resolved_axis, + std::numeric_limits::max(), + [](const int8_t current, const int8_t in) -> int8_t { + return (in < current) ? in : current; + })); + break; + default: + MicroPrintf("Only float32 and int8 types are supported."); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus EvalSumHelper(TfLiteContext* context, TfLiteNode* node, + OpDataReduce* op_data) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 1); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + TfLiteReducerParams* params = + static_cast(node->builtin_data); + + // Interpret an axis tensor with null dimensions as a scalar. + int num_axis = static_cast(ElementCount(*axis->dims)); + int temp_index[kMaxNumberOfAxis]; + int resolved_axis[kMaxNumberOfReducedAxis]; + + switch (input->type) { + case kTfLiteFloat32: { + TF_LITE_ENSURE( + context, + reference_ops::ReduceGeneric( + tflite::micro::GetTensorData(input), input->dims->data, + input->dims->size, tflite::micro::GetTensorData(output), + output->dims->data, output->dims->size, + tflite::micro::GetTensorData(axis), num_axis, + params->keep_dims, temp_index, resolved_axis, /*init_value=*/0.f, + [](const float current, const float in) -> float { + return in + current; + })); + } break; + case kTfLiteInt8: { + int32_t* temp_sum = static_cast( + context->GetScratchBuffer(context, op_data->temp_buffer_idx)); + QuantizedMeanOrSum(context, node, temp_index, resolved_axis, + temp_sum, op_data, /*compute_sum=*/true); + } break; + case kTfLiteInt16: { + int32_t* temp_sum = static_cast( + context->GetScratchBuffer(context, op_data->temp_buffer_idx)); + QuantizedMeanOrSum(context, node, temp_index, resolved_axis, + temp_sum, op_data, /*compute_sum=*/true); + } break; + default: + MicroPrintf("Only float32, int8, and int16 types are supported."); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reshape.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reshape.cpp new file mode 100644 index 0000000..f71298c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/reshape.cpp @@ -0,0 +1,118 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace reshape { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus ReshapeOutput(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + // Tensorflow's Reshape allows one of the shape components to have the + // special -1 value, meaning it will be calculated automatically based on the + // input. Here we calculate what that dimension should be so that the number + // of output elements in the same as the number of input elements. + int num_input_elements = NumElements(input); + TfLiteIntArray* output_shape = output->dims; + + if (NumInputs(node) == 1 && // Legacy scalar supported with params. + output_shape->size == 1 && output_shape->data[0] == 0) { + // Legacy tflite models use a shape parameter of [0] to indicate scalars, + // so adjust accordingly. TODO(b/111614235): Allow zero-sized buffers during + // toco conversion. + output_shape->size = 0; + } + + int num_output_elements = 1; + int stretch_dim = -1; + for (int i = 0; i < output_shape->size; ++i) { + int value = output_shape->data[i]; + if (value == -1) { + TF_LITE_ENSURE_EQ(context, stretch_dim, -1); + stretch_dim = i; + } else { + num_output_elements *= value; + } + } + if (stretch_dim != -1) { + output_shape->data[stretch_dim] = num_input_elements / num_output_elements; + num_output_elements *= output_shape->data[stretch_dim]; + } + + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + TF_LITE_ENSURE_EQ(context, num_input_elements, num_output_elements); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE(context, NumInputs(node) == 1 || NumInputs(node) == 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TF_LITE_ENSURE_EQ(context, ReshapeOutput(context, node), kTfLiteOk); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + // TODO(b/162522304): storing input bytes in OpData increases some models + // significantly, possibly due to alignment issues. + size_t input_bytes; + TF_LITE_ENSURE_STATUS(TfLiteTypeSizeOf(input->type, &input_bytes)); + input_bytes *= ElementCount(*input->dims); + + // Do nothing for in-place reshape. + if (input->data.raw != output->data.raw) { + // Otherwise perform reshape with copy. + memcpy(output->data.raw, input->data.raw, input_bytes); + } + return kTfLiteOk; +} + +} // namespace reshape + +TfLiteRegistration Register_RESHAPE() { + return tflite::micro::RegisterOp(nullptr, reshape::Prepare, reshape::Eval); +} + +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/resize_bilinear.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/resize_bilinear.cpp new file mode 100644 index 0000000..01399ee --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/resize_bilinear.cpp @@ -0,0 +1,116 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_bilinear.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kSizeTensor = 1; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* size = + micro_context->AllocateTempInputTensor(node, kSizeTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + TF_LITE_ENSURE_EQ(context, NumDimensions(input), 4); + TF_LITE_ENSURE_EQ(context, NumDimensions(size), 1); + + TF_LITE_ENSURE_EQ(context, size->type, kTfLiteInt32); + output->type = input->type; + + TF_LITE_ENSURE_MSG(context, IsConstantTensor(size), + "Non constant size tensor not supported"); + + // Ensure params are valid. + auto* params = + reinterpret_cast(node->builtin_data); + if (params->half_pixel_centers && params->align_corners) { + MicroPrintf("If half_pixel_centers is True, align_corners must be False."); + return kTfLiteError; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(size); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = + reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* size = + tflite::micro::GetEvalInput(context, node, kSizeTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (output->type == kTfLiteFloat32) { + tflite::ResizeBilinearParams op_params; + op_params.align_corners = params->align_corners; + op_params.half_pixel_centers = params->half_pixel_centers; + reference_ops::ResizeBilinear(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(size), + tflite::micro::GetTensorData(size), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else if (output->type == kTfLiteInt8) { + tflite::ResizeBilinearParams op_params; + op_params.align_corners = params->align_corners; + op_params.half_pixel_centers = params->half_pixel_centers; + reference_ops::ResizeBilinearInteger( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(size), + tflite::micro::GetTensorData(size), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + MicroPrintf("Output type is %d, requires float or int8.", output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_RESIZE_BILINEAR() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/resize_nearest_neighbor.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/resize_nearest_neighbor.cpp new file mode 100644 index 0000000..d6f3df3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/resize_nearest_neighbor.cpp @@ -0,0 +1,126 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/resize_nearest_neighbor.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace resize_nearest_neighbor { + +constexpr int kInputTensor = 0; +constexpr int kSizeTensor = 1; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* size = + micro_context->AllocateTempInputTensor(node, kSizeTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + // Our current implementations rely on the input being 4D, + // and the size being 1D tensor with exactly 2 elements. + TF_LITE_ENSURE_EQ(context, NumDimensions(input), 4); + TF_LITE_ENSURE_EQ(context, NumDimensions(size), 1); + TF_LITE_ENSURE_EQ(context, size->type, kTfLiteInt32); + TF_LITE_ENSURE_EQ(context, size->dims->data[0], 2); + + output->type = input->type; + + if (!IsConstantTensor(size)) { + MicroPrintf("Dynamic tensors are unsupported in tfmicro."); + return kTfLiteError; + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(size); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = + reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* size = + tflite::micro::GetEvalInput(context, node, kSizeTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + tflite::ResizeNearestNeighborParams op_params; + op_params.align_corners = params->align_corners; + op_params.half_pixel_centers = false; + + if (output->type == kTfLiteFloat32) { + reference_ops::ResizeNearestNeighbor( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(size), + tflite::micro::GetTensorData(size), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else if (output->type == kTfLiteInt8) { + reference_ops::ResizeNearestNeighbor( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(size), + tflite::micro::GetTensorData(size), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else if (output->type == kTfLiteInt16) { + reference_ops::ResizeNearestNeighbor( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(size), + tflite::micro::GetTensorData(size), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + MicroPrintf("Output tensor type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + + return kTfLiteError; + } + + return kTfLiteOk; +} +} // namespace resize_nearest_neighbor + +TfLiteRegistration Register_RESIZE_NEAREST_NEIGHBOR() { + return tflite::micro::RegisterOp(nullptr, resize_nearest_neighbor::Prepare, + resize_nearest_neighbor::Eval); +} + +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/rfft2d.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/rfft2d.cpp new file mode 100644 index 0000000..fe4a16c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/rfft2d.cpp @@ -0,0 +1,207 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include +#include +#include +#include + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" +#include "edge-impulse-sdk/dsp/kissfft/kiss_fftr.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace rfft2d { + +using std::complex; + +constexpr int kInputTensor = 0; +constexpr int kFftLengthTensor = 1; +constexpr int kOutputTensor = 0; + +struct OpData { + int kiss_fft_output_buffer_index; +}; + +bool IsPowerOfTwo(uint32_t v) { return v && !(v & (v - 1)); } + +static int software_rfft(float *fft_input, TfLiteComplex64 *output, size_t n_fft, size_t n_fft_out_features, kiss_fft_cpx *fft_output) { + size_t kiss_fftr_mem_length; + + // create fftr context (this should move to a scratch buffer...) + kiss_fftr_cfg cfg = kiss_fftr_alloc(n_fft, 0, NULL, NULL, &kiss_fftr_mem_length); + if (!cfg) { + ei_free(fft_output); + return -1; + } + + // execute the rfft operation + kiss_fftr(cfg, fft_input, fft_output); + + // and write back to the output + for (size_t ix = 0; ix < n_fft_out_features; ix++) { + output[ix].re = fft_output[ix].r; + output[ix].im = fft_output[ix].i; + } + + ei_free(cfg); + + return 0; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + (void)buffer; + (void)length; + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + // Check type and shape of the input tensor + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + + TfLiteTensor* fft_length = + micro_context->AllocateTempInputTensor(node, kFftLengthTensor); + const int32_t* fft_length_data = GetTensorData(fft_length); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + TF_LITE_ENSURE(context, NumDimensions(input) >= 2); + if (input->type != kTfLiteFloat32) { + context->ReportError(context, + "Type '%s' for input is not supported by rfft2d.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + // Check type and shape of the fft_length tensor + const RuntimeShape fft_length_shape = GetTensorShape(fft_length); + TF_LITE_ENSURE_EQ(context, NumDimensions(fft_length), 1); + TF_LITE_ENSURE_EQ(context, fft_length_shape.Dims(0), 2); + if (fft_length->type != kTfLiteInt32) { + context->ReportError(context, + "Type '%s' for fft_length is not supported by rfft2d.", + TfLiteTypeGetName(fft_length->type)); + return kTfLiteError; + } + + OpData* data = static_cast(node->user_data); + + size_t output_els = output->bytes / sizeof(TfLiteComplex64); + + TF_LITE_ENSURE_STATUS( + context->RequestScratchBufferInArena( + context, output_els * sizeof(kiss_fft_cpx), &data->kiss_fft_output_buffer_index)); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(fft_length); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteTensor* input; + TF_LITE_ENSURE_OK(context, GetInputSafe(context, node, kInputTensor, &input)); + const TfLiteTensor* fft_length; + TF_LITE_ENSURE_OK(context, + GetInputSafe(context, node, kFftLengthTensor, &fft_length)); + const int32_t* fft_length_data = GetTensorData(fft_length); + TfLiteTensor* output; + TF_LITE_ENSURE_OK(context, + GetOutputSafe(context, node, kOutputTensor, &output)); + + if (output->type != kTfLiteComplex64) { + context->ReportError(context, + "Type '%s' for output is not supported by rfft2d.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + + TF_LITE_ENSURE(context, IsPowerOfTwo(fft_length_data[0])); + TF_LITE_ENSURE(context, IsPowerOfTwo(fft_length_data[1])); + + int fft_height, fft_width; + fft_height = fft_length_data[0]; + fft_width = fft_length_data[1]; + + OpData* data = static_cast(node->user_data); + + if (fft_height != 1) { + context->ReportError(context, + "Only supports fft_height 1", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + + kiss_fft_cpx* shift_buffer = (kiss_fft_cpx*)context->GetScratchBuffer(context, data->kiss_fft_output_buffer_index); + + size_t in_row_els = 1; + for (size_t ix = 1; ix < input->dims->size; ix++) { + in_row_els *= input->dims->data[ix]; + } + size_t out_row_els = 1; + for (size_t ix = 1; ix < output->dims->size; ix++) { + out_row_els *= output->dims->data[ix]; + } + + for (size_t row = 0; row < input->dims->data[0]; row++) { + float *in_ptr = &input->data.f[row * in_row_els]; + auto out_ptr = &output->data.c64[row * out_row_els]; + + int x = software_rfft(in_ptr, out_ptr, fft_width, in_row_els, shift_buffer); + if (x != 0) { + context->ReportError(context, + "software_rfft failed (%d)", + x); + return kTfLiteError; + } + } + + return kTfLiteOk; +} + +} // namespace rfft2d +} // namespace micro +} // namespace ops + +TfLiteRegistration Register_RFFT2D() { + return {/*init=*/ops::micro::rfft2d::Init, + /*free=*/nullptr, + /*prepare=*/ops::micro::rfft2d::Prepare, + /*invoke=*/ops::micro::rfft2d::Eval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/round.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/round.cpp new file mode 100644 index 0000000..56e30d3 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/round.cpp @@ -0,0 +1,76 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/round.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace round { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteFloat32); + TF_LITE_ENSURE_TYPES_EQ(context, output->type, input->type); + TF_LITE_ENSURE_EQ(context, output->bytes, input->bytes); + TF_LITE_ENSURE_EQ(context, output->dims->size, input->dims->size); + for (int i = 0; i < output->dims->size; ++i) { + TF_LITE_ENSURE_EQ(context, output->dims->data[i], input->dims->data[i]); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + reference_ops::Round(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; +} +} // namespace round + +TfLiteRegistration Register_ROUND() { + return tflite::micro::RegisterOp(nullptr, round::Prepare, round::Eval); +} + +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.cpp new file mode 100644 index 0000000..b119d67 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.cpp @@ -0,0 +1,397 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h" + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h" + +namespace tflite { +namespace ops { +namespace micro { + +#if (defined(__Xxy)) || (defined(__Xvdsp)) +static void get_arc_two_buffer_sizes(int request_size_1, int request_size_2, + int* grant_size_1, int* grant_size_2) { + int maxrequest = 0; + int secondrequest = 0; + int maxavailable = 0; + int secondavail = 0; + + // determine the largest requested buffer. + if (request_size_1 > request_size_2) { + maxrequest = request_size_1; + secondrequest = request_size_2; + } else { + maxrequest = request_size_2; + secondrequest = request_size_1; + } + + // find the two largest available buffers. + get_arc_scratch_buffer_two_max_sizes(&maxavailable, &secondavail); + + // in case two buffers are available, the largest buffer can go to the largest + // request. + if (secondavail > 0) { // this condition can be enhanced to prevent cases + // where the second buffer is so small that it is + // better to use one buffer and split it. + if (request_size_1 > request_size_2) { + *grant_size_1 = maxavailable; + *grant_size_2 = secondavail; + } else { + *grant_size_1 = secondavail; + *grant_size_2 = maxavailable; + } + } else { + // In case only one buffer is available, + // use only the max buffer, and split it. + *grant_size_1 = maxavailable / 2; + *grant_size_2 = maxavailable / 2; + } +} + +static TfLiteStatus get_arc_scratch_buffer_for_io_tensors( + TfLiteContext* context, MliTensorInterface* in, MliTensorInterface* out) { + int request_size_in = 0; + int request_size_out = 0; + int grant_size_in = 0; + int grant_size_out = 0; + if (!inside_arc_ccm(in->Data())) { + // In case the input tensor contains multiple batches, it has rank 4 + // because the mli kernel cannot operate on batches, we need to have the + // size of a single HWC tensor. that is why the start_rank is 1 in case of + // input rank 4 + int start_rank = *in->Rank() - 3; + request_size_in = mli_hlp_count_elem_num(in->MliTensor(), start_rank) * + mli_hlp_tensor_element_size(in->MliTensor()); + } + if (!inside_arc_ccm(out->Data())) { + // In case the input tensor contains multiple batches, it has rank 4 + // because the mli kernel cannot operate on batches, we need to have the + // size of a single batch. that is why the start_rank is 1 in case of input + // rank 4 + int start_rank = *out->Rank() - 3; + request_size_out = mli_hlp_count_elem_num(out->MliTensor(), start_rank) * + mli_hlp_tensor_element_size(out->MliTensor()); + } + + get_arc_two_buffer_sizes(request_size_in, request_size_out, &grant_size_in, + &grant_size_out); + if (!inside_arc_ccm(in->Data())) { + in->SetData( + static_cast(get_arc_scratch_buffer(grant_size_in)), + grant_size_in); + if (in->Data() == NULL) return kTfLiteError; + } + + if (!inside_arc_ccm(out->Data())) { + out->SetData( + static_cast(get_arc_scratch_buffer(grant_size_out)), + grant_size_out); + if (out->Data() == NULL) return kTfLiteError; + } + + return kTfLiteOk; +} +#endif + +TfLiteStatus get_arc_scratch_buffer_for_conv_tensors( + TfLiteContext* context, MliTensorInterface* in, MliTensorInterface* weights, + MliTensorInterface* bias, MliTensorInterface* out) { + TfLiteStatus ret_val = kTfLiteOk; +#if (defined(__Xxy)) || (defined(__Xvdsp)) + init_arc_scratch_buffers(); + + if (!inside_arc_ccm(bias->Data())) { + uint32_t bias_mem_requirements = + mli_hlp_count_elem_num(bias->MliTensor(), 0) * + mli_hlp_tensor_element_size(bias->MliTensor()); + bias->SetData( + static_cast(get_arc_scratch_buffer(bias_mem_requirements)), + bias_mem_requirements); + } + + if (bias->Data() == NULL) { + int max_bias_size = 0; + get_arc_scratch_buffer_max_size(&max_bias_size); + bias->SetData( + static_cast(get_arc_scratch_buffer(max_bias_size)), + max_bias_size); + if (max_bias_size == 0) ret_val = kTfLiteError; + } + if (bias->Data() == NULL) ret_val = kTfLiteError; + + if (!inside_arc_ccm(weights->Data())) { + int weights_size = mli_hlp_count_elem_num(weights->MliTensor(), 0) * + mli_hlp_tensor_element_size(weights->MliTensor()); + int max_weights_size = 0; + weights->SetData( + static_cast(get_arc_scratch_buffer(weights_size)), + weights_size); + if (weights->Data() == NULL) { + get_arc_scratch_buffer_max_size(&max_weights_size); + weights->SetData( + static_cast(get_arc_scratch_buffer(max_weights_size)), + max_weights_size); + if (max_weights_size == 0) ret_val = kTfLiteError; + } + if (weights->Data() == NULL) ret_val = kTfLiteError; + } + + if (ret_val == kTfLiteOk) { + ret_val = get_arc_scratch_buffer_for_io_tensors(context, in, out); + } +#endif + return ret_val; +} + +TfLiteStatus get_arc_scratch_buffer_for_fully_connect_tensors( + TfLiteContext* context, MliTensorInterface* in, MliTensorInterface* weights, + MliTensorInterface* bias, MliTensorInterface* out) { + TfLiteStatus ret_val = kTfLiteOk; + +#if (defined(__Xxy)) || (defined(__Xvdsp)) + init_arc_scratch_buffers(); + + if (!inside_arc_ccm(bias->Data())) { + int bias_mem_requirements = mli_hlp_count_elem_num(bias->MliTensor(), 0) * + mli_hlp_tensor_element_size(bias->MliTensor()); + bias->SetData( + static_cast(get_arc_scratch_buffer(bias_mem_requirements)), + bias_mem_requirements); + } + + if (bias->Data() == NULL) { + int max_bias_size = 0; + get_arc_scratch_buffer_max_size(&max_bias_size); + bias->SetData( + static_cast(get_arc_scratch_buffer(max_bias_size)), + max_bias_size); + if (max_bias_size == 0) ret_val = kTfLiteError; + } + if (bias->Data() == NULL) ret_val = kTfLiteError; + + if (!inside_arc_ccm(weights->Data())) { + int weights_size = mli_hlp_count_elem_num(weights->MliTensor(), 0) * + mli_hlp_tensor_element_size(weights->MliTensor()); + int max_weights_size = 0; + weights->SetData( + static_cast(get_arc_scratch_buffer(weights_size)), + weights_size); + if (weights->Data() == NULL) { + get_arc_scratch_buffer_max_size(&max_weights_size); + weights->SetData( + static_cast(get_arc_scratch_buffer(max_weights_size)), + max_weights_size); + if (max_weights_size == 0) ret_val = kTfLiteError; + } + if (weights->Data() == NULL) ret_val = kTfLiteError; + } + + /* strategy for FC kernels: + first allocate input, because this cannot be sliced. (in case of batch + processing, only a single input needs to be allocated) then weights & + bias because if fully loaded, they can be reused over batches. then + output. The number of output channels (for weights slicing) depends on + size of output and size of weights&bias */ + + if (!inside_arc_ccm(in->Data())) { + /* In case the input tensor contains multiple batches, + only count the size if the inner most dimension */ + int size_in = mli_hlp_count_elem_num(in->MliTensor(), *in->Rank() - 1) * + mli_hlp_tensor_element_size(in->MliTensor()); + in->SetData(static_cast(get_arc_scratch_buffer(size_in)), + size_in); + if (in->Data() == NULL) { + in->SetData(nullptr, 0); + ret_val = kTfLiteError; + } + } + if (!inside_arc_ccm(out->Data())) { + /* In case the input tensor contains multiple batches, + only count the size if the inner most dimension */ + int out_size = mli_hlp_count_elem_num(out->MliTensor(), *out->Rank() - 1) * + mli_hlp_tensor_element_size(out->MliTensor()); + int max_out_size = 0; + out->SetData(static_cast(get_arc_scratch_buffer(out_size)), + out_size); + if (out->Data() == NULL) { + get_arc_scratch_buffer_max_size(&max_out_size); + out->SetData( + static_cast(get_arc_scratch_buffer(max_out_size)), + max_out_size); + if (max_out_size == 0) ret_val = kTfLiteError; + } + if (out->Data() == NULL) ret_val = kTfLiteError; + } +#endif + return ret_val; +} + +TfLiteStatus get_arc_scratch_buffer_for_eltwise_tensors( + TfLiteContext* context, MliTensorInterface* in1, MliTensorInterface* in2, + MliTensorInterface* out) { + TfLiteStatus ret_val = kTfLiteOk; +#if (defined(__Xxy)) || (defined(__Xvdsp)) + init_arc_scratch_buffers(); + constexpr int tsr_num = 3; + int in1_size = mli_hlp_count_elem_num(in1->MliTensor(), 0) * + mli_hlp_tensor_element_size(in1->MliTensor()); + int in2_size = mli_hlp_count_elem_num(in2->MliTensor(), 0) * + mli_hlp_tensor_element_size(in2->MliTensor()); + int out_size = mli_hlp_count_elem_num(out->MliTensor(), 0) * + mli_hlp_tensor_element_size(out->MliTensor()); + int sizes[tsr_num] = {in1_size, in2_size, out_size}; + MliTensorInterface* in_tensors[tsr_num] = {in1, in2, out}; + for (int i = 0; i < tsr_num; ++i) { + if (!inside_arc_ccm(in_tensors[i]->Data())) { + auto* data_ptr = get_arc_scratch_buffer(sizes[i]); + if (data_ptr == nullptr) { + get_arc_scratch_buffer_max_size(&sizes[i]); + data_ptr = get_arc_scratch_buffer(sizes[i]); + } + if (data_ptr == nullptr || sizes[i] == 0) { + in_tensors[i]->SetData(nullptr, 0); + ret_val = kTfLiteError; + } else { + in_tensors[i]->SetData(static_cast(data_ptr), + sizes[i]); + } + } + } +#endif + return ret_val; +} + +TfLiteStatus arc_scratch_buffer_calc_slice_size_io( + const MliTensorInterface* in, const MliTensorInterface* out, + const int kernel_height, const int stride_height, const int padding_top, + const int padding_bot, int* in_slice_height, int* out_slice_height) { + const int height_dimension = 1; + const int in_height = in->Shape()[height_dimension]; + const int out_height = out->Shape()[height_dimension]; + const int line_size_in = + mli_hlp_count_elem_num(in->MliTensor(), height_dimension + 1) * + mli_hlp_tensor_element_size(in->MliTensor()); + const int line_size_out = + mli_hlp_count_elem_num(out->MliTensor(), height_dimension + 1) * + mli_hlp_tensor_element_size(out->MliTensor()); + int max_lines_in = 0; + int max_lines_out = 0; + int max_out_lines_for_input = 0; + bool fit = + (static_cast(*in->DataCapacity()) >= in_height * line_size_in) && + (static_cast(*out->DataCapacity()) >= out_height * line_size_out); + if (fit) { + // in case both tensors completely fit in the capacity, there is no need + // for slicing. As padding can affect effective input region, we also + // derive it from output height, and rely on a clipping logic which intend + // to reduce last smaller slice. I.e the only slice is a kind of "smaller + // last slice that need to be corrected" + *in_slice_height = std::max(in_height, out_height * stride_height); + *out_slice_height = out_height; + } else { + // First compute how many lines fit into the input tensor, and compute how + // many output lines can be computed with that. + max_lines_in = std::min( + in_height, static_cast(*in->DataCapacity()) / line_size_in); + if (max_lines_in >= in_height) { + max_out_lines_for_input = out_height; + } else if (2 * max_lines_in >= in_height) { + // in this case only two slices are needed, so both could benefit from + // padding. take the MIN to get the worst case. + max_out_lines_for_input = + (max_lines_in + std::min(padding_top, padding_bot) - kernel_height + + 1) / + stride_height; + } else { + max_out_lines_for_input = + (max_lines_in - kernel_height + 1) / stride_height; + } + // Then compute how many output lines fit into the output tensor. + max_lines_out = std::min( + out_height, static_cast(*out->DataCapacity()) / line_size_out); + // the smallest of the two determines the slice height for the output, and + // the derived sliceheight for the input. + *out_slice_height = std::min(max_out_lines_for_input, max_lines_out); + *in_slice_height = *out_slice_height * stride_height; + } + + if ((*in_slice_height > 0) && (*out_slice_height > 0)) { + return kTfLiteOk; + } else { + return kTfLiteError; + } +} + +TfLiteStatus arc_scratch_buffer_calc_slice_size_weights( + const MliTensorInterface* weights, const MliTensorInterface* bias, + const int weight_out_ch_dimension, int* slice_channels) { + const int channels = weights->Shape()[weight_out_ch_dimension]; + const int ch_size_w = + (mli_hlp_count_elem_num(weights->MliTensor(), 0) / channels) * + mli_hlp_tensor_element_size(weights->MliTensor()); + const int ch_size_b = + (mli_hlp_count_elem_num(bias->MliTensor(), 0) / channels) * + mli_hlp_tensor_element_size(bias->MliTensor()); + int max_ch_weigths = 0; + int max_ch_bias = 0; + + bool fit = + (static_cast(*weights->DataCapacity()) >= channels * ch_size_w) && + (static_cast(*bias->DataCapacity()) >= channels * ch_size_b); + if (fit) { + // in case both tensors completely fit in the capacity, there is no need + // for slicing + *slice_channels = channels; + } else { + // First compute how many channels fit into the weights tensor + max_ch_weigths = std::min( + channels, static_cast(*weights->DataCapacity()) / ch_size_w); + // Ten compute how many channels fit into the bias tensor. + max_ch_bias = + std::min(channels, static_cast(*bias->DataCapacity()) / ch_size_b); + // the smallest of the two determines the slice size + *slice_channels = std::min(max_ch_weigths, max_ch_bias); + } + + if (*slice_channels > 0) { + return kTfLiteOk; + } else { + return kTfLiteError; + } +} + +TfLiteStatus get_arc_scratch_buffer_for_pooling_tensors( + TfLiteContext* context, MliTensorInterface* in, MliTensorInterface* out) { +#if (defined(__Xxy)) || (defined(__Xvdsp)) + init_arc_scratch_buffers(); + return get_arc_scratch_buffer_for_io_tensors(context, in, out); +#else + return kTfLiteOk; +#endif +} + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h new file mode 100644 index 0000000..2f60948 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buf_mgr.h @@ -0,0 +1,150 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_ARC_SCRATCH_BUF_MGR_H_ +#define TENSORFLOW_LITE_MICRO_ARC_SCRATCH_BUF_MGR_H_ + +#include "mli_api.h" // NOLINT +#include "mli_interface.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { +namespace ops { +namespace micro { + +/** + * @brief Function to allocate scratch buffers for the convolution tensors + * + * @detail This function will update the data pointers in the 4 tensors with + * pointers to scratch buffers in fast local memory. + * + * @param context [I] pointer to TfLite context (needed for error handling) + * @param in [IO] pointer to the input tensor + * @param weights [IO] pointer to the weights tensor + * @param bias [IO] pointer to the bias tensor + * @param output [IO] pointer to the output tensor + * + * @return Tf Lite status code + */ +TfLiteStatus get_arc_scratch_buffer_for_conv_tensors( + TfLiteContext* context, MliTensorInterface* in, MliTensorInterface* weights, + MliTensorInterface* bias, MliTensorInterface* out); + +/** + * @brief Function to allocate scratch buffers for pooling kernels with only + * input and output buffers + * + * @detail This function will update the data pointers in the 2 tensors with + * pointers to scratch buffers in fast local memory. + * + * @param context [I] pointer to TfLite context (needed for error handling) + * @param in [IO] pointer to the input tensor + * @param output [IO] pointer to the output tensor + * + * @return Tf Lite status code + */ +TfLiteStatus get_arc_scratch_buffer_for_pooling_tensors( + TfLiteContext* context, MliTensorInterface* in, MliTensorInterface* out); + +/** + * @brief Function to allocate scratch buffers for the fully connect tensors + * + * @detail This function will update the data pointers in the 4 tensors with + * pointers to scratch buffers in fast local memory. + * + * @param context [I] pointer to TfLite context (needed for error handling) + * @param in [IO] pointer to the input tensor + * @param weights [IO] pointer to the weights tensor + * @param bias [IO] pointer to the bias tensor + * @param output [IO] pointer to the output tensor + * + * @return Tf Lite status code + */ +TfLiteStatus get_arc_scratch_buffer_for_fully_connect_tensors( + TfLiteContext* context, MliTensorInterface* in, MliTensorInterface* weights, + MliTensorInterface* bias, MliTensorInterface* out); + +/** + * @brief Function to allocate scratch buffers for the eltwise function tensors + * + * @detail This function will update the data pointers in the 3 tensors with + * pointers to scratch buffers in fast local memory. + * + * @param context [I] pointer to TfLite context (needed for error handling) + * @param in1 [IO] pointer to the first input tensor + * @param in2 [IO] pointer to the second input tensor + * @param output [IO] pointer to the output tensor + * + * @return Tf Lite status code + */ +TfLiteStatus get_arc_scratch_buffer_for_eltwise_tensors( + TfLiteContext* context, MliTensorInterface* in1, MliTensorInterface* in2, + MliTensorInterface* out); + +/** + * @brief Function to calculate slice size for io tensors + * + * @detail This function will calculate the slice size in the height dimension + * for input and output tensors. it takes into account the kernel size and the + * padding. the function will look at the capacity filed in the in and out + * tensor to determine the available buffersize. + * + * @param in [I] pointer to the input tensor + * @param out [I] pointer to the output tensor + * @param kernelHeight [I] size of the kernel in height dimension + * @param strideHeight [I] input stride in height dimension + * @param padding_top [I] number of lines with zeros at the top + * @param padding_bot [I] number of lines with zeros at the bottom + * @param inSliceHeight [O] slice size in height dimension for the input + * tensor + * @param outSliceHeight [O] slice size in height dimension for the output + * tensor + * + * @return Tf Lite status code + */ +TfLiteStatus arc_scratch_buffer_calc_slice_size_io( + const MliTensorInterface* in, const MliTensorInterface* out, + const int kernelHeight, const int strideHeight, const int padding_top, + const int padding_bot, int* in_slice_height, int* out_slice_height); + +/** + * @brief Function to calculate slice size for weight slicing + * + * @detail This function will calculate the slice size in the output channel + * dimension for weight and bias tensors. the function will look at the capacity + * filed in the weights and bias tensor to determine the available buffersize. + * + * @param weights [I] pointer to the input tensor + * @param bias [I] pointer to the output tensor + * @param weightOutChDimension [I] dimension of the output channels in the + * weights tensor + * @param sliceChannels [O] slice size in output channel dimension + * + * @return Tf Lite status code + */ +TfLiteStatus arc_scratch_buffer_calc_slice_size_weights( + const MliTensorInterface* weights, const MliTensorInterface* bias, + const int weight_out_ch_dimension, int* slice_channels); + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ARC_SCRATCH_BUF_MGR_H_ + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.cpp new file mode 100644 index 0000000..924cc41 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.cpp @@ -0,0 +1,209 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h" + +#include + +namespace tflite { +namespace ops { +namespace micro { + +/* by default use all the XY memory, and half of the DCCM because DCCM is also + * used for the data section and the stack. the values can be overruled by + * adding a -D option to the makefile of the application + */ + +#ifdef __Xxy + +#ifndef SCRATCH_MEM_X_SIZE +#ifdef core_config_xy_size +#define SCRATCH_MEM_X_SIZE (core_config_xy_size) +#endif +#endif + +#ifndef SCRATCH_MEM_Y_SIZE +#ifdef core_config_xy_size +#define SCRATCH_MEM_Y_SIZE (core_config_xy_size) +#endif +#endif + +#ifndef SCRATCH_MEM_Z_SIZE +#ifdef core_config_dccm_size +#define SCRATCH_MEM_Z_SIZE ((core_config_dccm_size) / 2) +#endif +#endif + +#elif defined(__Xvdsp) + +#ifndef SCRATCH_MEM_VEC_SIZE +#ifdef core_config_vec_mem_size +#define SCRATCH_MEM_VEC_SIZE ((core_config_vec_mem_size * 3) / 4) +#endif +#endif + +#else + +#define SCRATCH_MEM_SIZE (65536) + +#endif + +#ifdef __Xxy + +// Patched by Edge Impulse, ARC GCC fixes +namespace { +#if defined (__GNUC__) +static int8_t scratch_mem_x[SCRATCH_MEM_X_SIZE] __attribute__((section(".Xdata"))); +#else +#pragma Bss(".Xdata") +static int8_t scratch_mem_x[SCRATCH_MEM_X_SIZE]; +#pragma Bss() +#endif + +#if defined (__GNUC__) +static int8_t scratch_mem_y[SCRATCH_MEM_Y_SIZE] __attribute__((section(".Ydata"))); +#else +#pragma Bss(".Ydata") +static int8_t scratch_mem_y[SCRATCH_MEM_Y_SIZE]; +#pragma Bss() +#endif + +#if defined (__GNUC__) +static int8_t scratch_mem_z[SCRATCH_MEM_Z_SIZE] __attribute__((section(".Zdata"))); +#else +#pragma Bss(".Zdata") +static int8_t scratch_mem_z[SCRATCH_MEM_Z_SIZE]; +#pragma Bss() +#endif + +#elif defined(__Xvdsp) + +#pragma Bss(".vecmem_data") +static int8_t scratch_mem_vec_1[SCRATCH_MEM_VEC_SIZE / 4]; +static int8_t scratch_mem_vec_2[SCRATCH_MEM_VEC_SIZE / 4]; +static int8_t scratch_mem_vec_3[SCRATCH_MEM_VEC_SIZE / 2]; +#pragma Bss() + +#else + +static int8_t scratch_mem_stack[SCRATCH_MEM_SIZE]; + +#endif +} // namespace + +#ifdef __Xxy + +static int8_t* scratch_mem[] = {scratch_mem_x, scratch_mem_y, scratch_mem_z}; +static uint32_t scratch_sizes[] = {SCRATCH_MEM_X_SIZE, SCRATCH_MEM_Y_SIZE, + SCRATCH_MEM_Z_SIZE}; + +#elif defined(__Xvdsp) + +static int8_t* scratch_mem[] = {scratch_mem_vec_1, scratch_mem_vec_2, + scratch_mem_vec_3}; +static uint32_t scratch_sizes[] = {SCRATCH_MEM_VEC_SIZE / 4, + SCRATCH_MEM_VEC_SIZE / 4, + SCRATCH_MEM_VEC_SIZE / 2}; + +#else + +static int8_t* scratch_mem[] = {scratch_mem_stack}; +static uint32_t scratch_sizes[] = {SCRATCH_MEM_SIZE}; + +#endif + +void* get_arc_scratch_buffer(int size) { + // Function to asign fast memory from one of 3 scratch buffers. + // Best Fit strategy - memory is allocated from that memory bank that leaves + // the least unused memory. + void* buf = NULL; + int best_mem_idx = -1; + int best_mem_delta = INT_MAX; + const int num_mem = sizeof(scratch_mem) / sizeof(scratch_mem[0]); + // find a local memory that fits the data size. + for (int mem_idx = 0; mem_idx < num_mem; ++mem_idx) { + // Best Fit + if ((size <= static_cast(scratch_sizes[mem_idx])) && + (static_cast(scratch_sizes[mem_idx]) - size < best_mem_delta)) { + best_mem_idx = mem_idx; + best_mem_delta = scratch_sizes[mem_idx] - size; + } + } + if (best_mem_idx >= 0) { + buf = scratch_mem[best_mem_idx]; + scratch_mem[best_mem_idx] += size; + scratch_sizes[best_mem_idx] -= size; + } + return buf; +} + +void get_arc_scratch_buffer_max_size(int* size) { + int maxavailable = 0; + const int num_mem = sizeof(scratch_mem) / sizeof(scratch_mem[0]); + // find the largest available buffer. + for (int i = 0; i < num_mem; i++) { + if (static_cast(scratch_sizes[i]) > maxavailable) { + maxavailable = scratch_sizes[i]; + } + } + *size = maxavailable; +} + +void get_arc_scratch_buffer_two_max_sizes(int* size1, int* size2) { + int maxavailable = 0; + int secondavail = 0; + const int num_mem = sizeof(scratch_mem) / sizeof(scratch_mem[0]); + // find the two largest available buffers. + for (int i = 0; i < num_mem; i++) { + if (static_cast(scratch_sizes[i]) > maxavailable) { + secondavail = maxavailable; + maxavailable = scratch_sizes[i]; + } else if (static_cast(scratch_sizes[i]) > secondavail) { + secondavail = scratch_sizes[i]; + } + } + *size1 = maxavailable; + *size2 = secondavail; +} + +void init_arc_scratch_buffers(void) { +#ifdef __Xxy + scratch_mem[0] = scratch_mem_x; + scratch_mem[1] = scratch_mem_y; + scratch_mem[2] = scratch_mem_z; + scratch_sizes[0] = SCRATCH_MEM_X_SIZE; + scratch_sizes[1] = SCRATCH_MEM_Y_SIZE; + scratch_sizes[2] = SCRATCH_MEM_Z_SIZE; +#elif defined(__Xvdsp) + scratch_mem[0] = scratch_mem_vec_1; + scratch_mem[1] = scratch_mem_vec_2; + scratch_mem[2] = scratch_mem_vec_3; + scratch_sizes[0] = SCRATCH_MEM_VEC_SIZE / 4; + scratch_sizes[1] = SCRATCH_MEM_VEC_SIZE / 4; + scratch_sizes[2] = SCRATCH_MEM_VEC_SIZE / 2; +#else + scratch_mem[0] = scratch_mem_stack; + scratch_sizes[0] = SCRATCH_MEM_SIZE; +#endif +} + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h new file mode 100644 index 0000000..dc704aa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/scratch_buffers.h @@ -0,0 +1,83 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_ARC_SCRATCH_BUFFERS_H_ +#define TENSORFLOW_LITE_MICRO_ARC_SCRATCH_BUFFERS_H_ + +#include "mli_api.h" // NOLINT +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { +namespace ops { +namespace micro { + +void init_arc_scratch_buffers(void); +void* get_arc_scratch_buffer(int size); // Function to assign fast memory + // from one of 3 scratch buffers. + +void get_arc_scratch_buffer_max_size(int* size); +void get_arc_scratch_buffer_two_max_sizes(int* size1, int* size2); + +static inline bool inside_arc_dccm(void* p) { +#if core_config_dccm_present + return ((unsigned)p >= core_config_dccm_base) && + ((unsigned)p < core_config_dccm_base + core_config_dccm_size); +#else + return false; +#endif +} + +static inline bool inside_arc_xccm(void* p) { +#if core_config_xy + return ((unsigned)p >= core_config_xy_x_base) && + ((unsigned)p < core_config_xy_x_base + core_config_xy_size); +#else + return false; +#endif +} + +static inline bool inside_arc_yccm(void* p) { +#if core_config_xy_size + return ((unsigned)p >= core_config_xy_y_base) && + ((unsigned)p < core_config_xy_y_base + core_config_xy_size); +#else + return false; +#endif +} + +static inline bool inside_arc_vccm(void* p) { +#if core_config_vec_mem_size + return ((unsigned)p >= core_config_vec_mem_base) && + ((unsigned)p < core_config_vec_mem_base + core_config_vec_mem_size); +#else + return false; +#endif +} + +static inline bool inside_arc_ccm(void* p) { + return inside_arc_dccm(p) || inside_arc_xccm(p) || inside_arc_yccm(p) || + inside_arc_vccm(p); +} + +} // namespace micro +} // namespace ops +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ARC_SCRATCH_BUFFERS_H_ + +#endif // EI_CLASSIFIER_TFLITE_ENABLE_ARC == 1 diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/select.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/select.cpp new file mode 100644 index 0000000..68cf319 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/select.cpp @@ -0,0 +1,248 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TF_LITE_STATIC_MEMORY +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/select.h" + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +constexpr int kInputTensorCondition = 0; +constexpr int kInputTensorX = 1; +constexpr int kInputTensorY = 2; +constexpr int kOutputTensor = 0; + +enum KernelType { + kVersionOne, + kVersionTwo, +}; + +struct OpData { + bool requires_broadcast; + // True if input condition is scalar or input condition has rank one and + // matches the first dimension of other inputs. + bool has_low_rank_input_condition; +}; + +void* SelectInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + auto* data = static_cast( + context->AllocatePersistentBuffer(context, sizeof(OpData))); + data->requires_broadcast = false; + data->has_low_rank_input_condition = false; + return data; +} + +TfLiteStatus CheckBroadcastShape(TfLiteContext* context, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + const TfLiteTensor* input3, + const TfLiteIntArray* output_shape) { + const int dims1 = NumDimensions(input1); + const int dims2 = NumDimensions(input2); + const int dims3 = NumDimensions(input3); + const int out_dims = std::max(std::max(dims1, dims2), dims3); + TF_LITE_ENSURE_EQ(context, out_dims, output_shape->size); + + for (int i = 0; i < out_dims; ++i) { + const int d1 = i >= dims1 ? 1 : SizeOfDimension(input1, dims1 - i - 1); + const int d2 = i >= dims2 ? 1 : SizeOfDimension(input2, dims2 - i - 1); + const int d3 = i >= dims3 ? 1 : SizeOfDimension(input3, dims3 - i - 1); + const int min_value = std::min(std::min(d1, d2), d3); + int max_value = std::max(std::max(d1, d2), d3); + // If one dimention is 0, others must be 0 or 1. + if (min_value == 0) max_value = 0; + if (!(d1 == 1 || d1 == max_value) || !(d2 == 1 || d2 == max_value) || + !(d3 == 1 || d3 == max_value)) { + MicroPrintf("Given shapes are not broadcastable."); + return kTfLiteError; + } + TF_LITE_ENSURE_EQ(context, output_shape->data[out_dims - i - 1], max_value); + } + return kTfLiteOk; +} + +template +TfLiteStatus SelectPrepare(TfLiteContext* context, TfLiteNode* node) { + OpData* data = reinterpret_cast(node->user_data); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 3); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input_condition = + micro_context->AllocateTempInputTensor(node, kInputTensorCondition); + + TfLiteTensor* input_x = + micro_context->AllocateTempInputTensor(node, kInputTensorX); + + TfLiteTensor* input_y = + micro_context->AllocateTempInputTensor(node, kInputTensorY); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + + // Input must be bool. + TF_LITE_ENSURE_TYPES_EQ(context, input_condition->type, kTfLiteBool); + TF_LITE_ENSURE_TYPES_EQ(context, input_x->type, input_y->type); + output->type = input_x->type; + + // Respect the original output shape when there are mixed shapes to represent + // a scalar data. + if (GetTensorShape(input_condition).FlatSize() == 1 && + GetTensorShape(input_x).FlatSize() == 1 && + GetTensorShape(input_y).FlatSize() == 1 && + GetTensorShape(output).FlatSize() == 1) { + + micro_context->DeallocateTempTfLiteTensor(input_condition); + micro_context->DeallocateTempTfLiteTensor(input_x); + micro_context->DeallocateTempTfLiteTensor(input_y); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; + } + + bool same_shape = HaveSameShapes(input_condition, input_x) && + HaveSameShapes(input_x, input_y); + TfLiteIntArray* output_size; + if (!same_shape) { + switch (kernel_type) { + case kVersionOne: { + bool is_input_condition_scalar = NumDimensions(input_condition) == 0; + bool has_rank_one_input_condition = + NumDimensions(input_condition) == 1 && + SizeOfDimension(input_condition, 0) == SizeOfDimension(input_x, 0); + data->has_low_rank_input_condition = + is_input_condition_scalar || has_rank_one_input_condition; + TF_LITE_ENSURE(context, data->has_low_rank_input_condition); + + output_size = TfLiteIntArrayCopy(input_x->dims); + + // Input tensors must have the same type and size + TF_LITE_ENSURE(context, HaveSameShapes(input_x, input_y)); + break; + } + case kVersionTwo: { + TF_LITE_ENSURE_OK( + context, CheckBroadcastShape(context, input_condition, input_x, input_y, + output->dims)); + data->requires_broadcast = true; + break; + } + default: + micro_context->DeallocateTempTfLiteTensor(input_condition); + micro_context->DeallocateTempTfLiteTensor(input_x); + micro_context->DeallocateTempTfLiteTensor(input_y); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteError; + } + } else { + output_size = TfLiteIntArrayCopy(input_x->dims); + } + + micro_context->DeallocateTempTfLiteTensor(input_condition); + micro_context->DeallocateTempTfLiteTensor(input_x); + micro_context->DeallocateTempTfLiteTensor(input_y); + micro_context->DeallocateTempTfLiteTensor(output); + + TfLiteIntArrayFree(output_size); + + return kTfLiteOk; +} + +template +void CallSelect(const TfLiteEvalTensor* input_condition, + const TfLiteEvalTensor* input_x, + const TfLiteEvalTensor* input_y, TfLiteEvalTensor* output, + bool need_broadcast) { + using Func = decltype(reference_ops::Select)*; + Func select_func; + if (need_broadcast) { + select_func = reference_ops::BroadcastSelect5DSlow; + } else { + select_func = reference_ops::Select; + } + + select_func(tflite::micro::GetTensorShape(input_condition), + tflite::micro::GetTensorData(input_condition), + tflite::micro::GetTensorShape(input_x), + tflite::micro::GetTensorData(input_x), + tflite::micro::GetTensorShape(input_y), + tflite::micro::GetTensorData(input_y), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +} + +TfLiteStatus SelectEval(TfLiteContext* context, TfLiteNode* node) { + OpData* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input_condition = + tflite::micro::GetEvalInput(context, node, kInputTensorX); + + const TfLiteEvalTensor* input_x = + tflite::micro::GetEvalInput(context, node, kInputTensorY); + + const TfLiteEvalTensor* input_y = + tflite::micro::GetEvalInput(context, node, kInputTensorCondition); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + switch (input_x->type) { + case kTfLiteFloat32: + CallSelect(input_condition, input_x, input_y, output, + data->requires_broadcast); + break; + case kTfLiteInt8: + CallSelect(input_condition, input_x, input_y, output, + data->requires_broadcast); + break; + case kTfLiteInt16: + CallSelect(input_condition, input_x, input_y, output, + data->requires_broadcast); + break; + default: + MicroPrintf("Does not support type other than %s, but got %s", + "int8|int16|float32", TfLiteTypeGetName(input_x->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteRegistration Register_SELECT() { + return tflite::micro::RegisterOp(tflite::SelectInit, tflite::SelectPrepare, + tflite::SelectEval); +} + +// SelectV2 op selects values of 'x' if the corresponding value of 'condition' +// is true or the value of 'y' if false. There are valid condition input sizes: +// +// 1. Either the same shape (in which case the select is elementwise), or +// 2. Broadcastable shapes between 'condition', 'x' and 'y'. +TfLiteRegistration Register_SELECT_V2() { + return tflite::micro::RegisterOp(tflite::SelectInit, tflite::SelectPrepare, + tflite::SelectEval); +} + +} // namespace tflite +#endif // TF_LITE_STATIC_MEMORY diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/shape.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/shape.cpp new file mode 100644 index 0000000..21af290 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/shape.cpp @@ -0,0 +1,67 @@ +/* Copyright 2017 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +namespace { +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +void ExtractShape(const TfLiteEvalTensor* input, int32_t* output_data) { + for (int i = 0; i < input->dims->size; ++i) { + output_data[i] = input->dims->data[i]; + } +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + if (output->type != kTfLiteInt32) { + MicroPrintf("Output type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + } else { + ExtractShape(input, tflite::micro::GetTensorData(output)); + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_SHAPE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/slice.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/slice.cpp new file mode 100644 index 0000000..16ce966 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/slice.cpp @@ -0,0 +1,157 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/slice.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kBeginTensor = 1; +constexpr int kSizeTensor = 2; +constexpr int kOutputTensor = 0; + +const int kMaxDim = 5; + +template +void GetBeginAndSizeVectors(int dimensions, const TfLiteEvalTensor* begin, + const TfLiteEvalTensor* size, int32_t* begins, + int32_t* sizes) { + int offset = kMaxDim - dimensions; + for (int idx = 0; idx < dimensions; ++idx) { + begins[offset + idx] = tflite::micro::GetTensorData(begin)[idx]; + sizes[offset + idx] = tflite::micro::GetTensorData(size)[idx]; + } +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 3); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TFLITE_DCHECK(input != nullptr); + TfLiteTensor* begin = + micro_context->AllocateTempInputTensor(node, kBeginTensor); + TFLITE_DCHECK(begin != nullptr); + TfLiteTensor* size = + micro_context->AllocateTempInputTensor(node, kSizeTensor); + TFLITE_DCHECK(size != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TFLITE_DCHECK(output != nullptr); + + // Ensure validity of input tensor and its dimension. + TFLITE_DCHECK(input->type == output->type); + TFLITE_DCHECK(begin->type == size->type); + TFLITE_DCHECK(begin->type == kTfLiteInt32 || begin->type == kTfLiteInt64); + TFLITE_DCHECK(size->type == kTfLiteInt32 || size->type == kTfLiteInt64); + TFLITE_DCHECK(NumDimensions(begin) == 1); + TFLITE_DCHECK(NumDimensions(size) == 1); + TFLITE_DCHECK(NumElements(begin) == NumElements(size)); + TFLITE_DCHECK(NumDimensions(input) <= kMaxDim); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(begin); + micro_context->DeallocateTempTfLiteTensor(size); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* begin = + tflite::micro::GetEvalInput(context, node, kBeginTensor); + const TfLiteEvalTensor* size = + tflite::micro::GetEvalInput(context, node, kSizeTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + tflite::SliceParams op_params; + op_params.begin_count = kMaxDim; + op_params.size_count = kMaxDim; + for (int i = 0; i < kMaxDim; ++i) { + op_params.begin[i] = 0; + op_params.size[i] = 1; + } + + if (begin->type == kTfLiteInt32) { + GetBeginAndSizeVectors(input->dims->size, begin, size, + op_params.begin, op_params.size); + } else if (begin->type == kTfLiteInt64) { + GetBeginAndSizeVectors(input->dims->size, begin, size, + op_params.begin, op_params.size); + } else { + MicroPrintf("Begin tensor type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + + switch (input->type) { + case kTfLiteFloat32: + reference_ops::Slice(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt32: + reference_ops::Slice( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: + reference_ops::Slice( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt16: + reference_ops::Slice( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Input tensor type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_SLICE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.cpp new file mode 100644 index 0000000..d5d6355 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.cpp @@ -0,0 +1,565 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/softmax.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +struct CMSISNNSoftmaxParams { + SoftmaxParams softmax_params; + int32_t num_rows; + int32_t row_size; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, + sizeof(CMSISNNSoftmaxParams)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, NumDimensions(input) >= 1); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE(context, node->user_data != nullptr); + CMSISNNSoftmaxParams* op_data = + static_cast(node->user_data); + + auto* params = static_cast(node->builtin_data); + auto ret_val = CalculateSoftmaxParams(context, input, output, params, + &op_data->softmax_params); + + const auto input_shape = GetTensorShape(input); + const auto output_shape = GetTensorShape(output); + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + op_data->num_rows = outer_size; + op_data->row_size = depth; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return ret_val; +} + +TfLiteStatus SoftmaxEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + TFLITE_DCHECK(node->user_data != nullptr); + const CMSISNNSoftmaxParams op_data = + *static_cast(node->user_data); + + switch (input->type) { + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + tflite::reference_ops::Softmax( + op_data.softmax_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + case kTfLiteInt8: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + if (output->type == kTfLiteInt8) { +#if EI_TFLITE_DISABLE_SOFTMAX_OUT_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + output->type); + return kTfLiteError; +#endif + arm_softmax_s8(tflite::micro::GetTensorData(input), + op_data.num_rows, op_data.row_size, + op_data.softmax_params.input_multiplier, + op_data.softmax_params.input_left_shift, + op_data.softmax_params.diff_min, + tflite::micro::GetTensorData(output)); + } else { +#if EI_TFLITE_DISABLE_SOFTMAX_OUT_I16 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + output->type); + return kTfLiteError; +#endif + arm_softmax_s8_s16(tflite::micro::GetTensorData(input), + op_data.num_rows, op_data.row_size, + op_data.softmax_params.input_multiplier, + op_data.softmax_params.input_left_shift, + op_data.softmax_params.diff_min, + tflite::micro::GetTensorData(output)); + } + return kTfLiteOk; + } + case kTfLiteInt16: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + const cmsis_nn_softmax_lut_s16 softmax_params = { + .exp_lut = op_data.softmax_params.exp_lut, + .one_by_one_lut = op_data.softmax_params.one_over_one_plus_x_lut}; + + TFLITE_DCHECK_EQ( + arm_softmax_s16( + tflite::micro::GetTensorData(input), op_data.num_rows, + op_data.row_size, op_data.softmax_params.input_multiplier, + op_data.softmax_params.input_left_shift, &softmax_params, + tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + return kTfLiteOk; + } + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } +} + +TfLiteStatus SoftmaxEvalInt8(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + TFLITE_DCHECK(node->user_data != nullptr); + const CMSISNNSoftmaxParams op_data = + *static_cast(node->user_data); + + arm_softmax_s8(tflite::micro::GetTensorData(input), op_data.num_rows, + op_data.row_size, op_data.softmax_params.input_multiplier, + op_data.softmax_params.input_left_shift, + op_data.softmax_params.diff_min, + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; +} + +TfLiteStatus SoftmaxEvalInt8_Int16(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + TFLITE_DCHECK(node->user_data != nullptr); + const CMSISNNSoftmaxParams op_data = + *static_cast(node->user_data); + + arm_softmax_s8_s16( + tflite::micro::GetTensorData(input), op_data.num_rows, + op_data.row_size, op_data.softmax_params.input_multiplier, + op_data.softmax_params.input_left_shift, op_data.softmax_params.diff_min, + tflite::micro::GetTensorData(output)); + + return kTfLiteOk; +} + +TfLiteStatus SoftmaxEvalInt16(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + TFLITE_DCHECK(node->user_data != nullptr); + const CMSISNNSoftmaxParams op_data = + *static_cast(node->user_data); + + const cmsis_nn_softmax_lut_s16 softmax_params = { + .exp_lut = op_data.softmax_params.exp_lut, + .one_by_one_lut = op_data.softmax_params.one_over_one_plus_x_lut}; + + TFLITE_DCHECK_EQ( + arm_softmax_s16(tflite::micro::GetTensorData(input), + op_data.num_rows, op_data.row_size, + op_data.softmax_params.input_multiplier, + op_data.softmax_params.input_left_shift, &softmax_params, + tflite::micro::GetTensorData(output)), + ARM_CMSIS_NN_SUCCESS); + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_SOFTMAX() { + return tflite::micro::RegisterOp(Init, Prepare, SoftmaxEval); +} + +TfLiteRegistration Register_SOFTMAX_INT8() { + return tflite::micro::RegisterOp(Init, Prepare, SoftmaxEvalInt8); +} + +TfLiteRegistration Register_SOFTMAX_INT8_INT16() { + return tflite::micro::RegisterOp(Init, Prepare, SoftmaxEvalInt8_Int16); +} + +TfLiteRegistration Register_SOFTMAX_INT16() { + return tflite::micro::RegisterOp(Init, Prepare, SoftmaxEvalInt16); +} + +} // namespace tflite + +#elif EI_CLASSIFIER_TFLITE_ENABLE_ESP_NN == 1 +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/softmax.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#include + +#if ESP_NN +#include "edge-impulse-sdk/porting/espressif/ESP-NN/include/esp_nn.h" +#endif + +long long softmax_total_time = 0; + +namespace tflite { +namespace { +// Softmax parameter data that persists in user_data +const int kInt16LUTArraySize = 513; + +struct NodeData { + SoftmaxParams op_data; +#if ESP_NN + int buffer_idx; +#endif +}; + +static void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(NodeData)); +} + +void SoftmaxQuantized(TfLiteContext* context, const TfLiteEvalTensor* input, + TfLiteEvalTensor* output, const NodeData* data) { + if (input->type == kTfLiteInt8) { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return; +#endif + if (output->type == kTfLiteInt16) { +#if EI_TFLITE_DISABLE_SOFTMAX_OUT_I16 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return; +#endif + tflite::reference_ops::Softmax( + data->op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { +#if EI_TFLITE_DISABLE_SOFTMAX_OUT_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return; +#endif +#if ESP_NN + const int32_t input_beta_multiplier = data->op_data.input_multiplier; + const int32_t input_beta_left_shift = data->op_data.input_left_shift; + const int diff_min = data->op_data.diff_min; + const RuntimeShape input_shape = tflite::micro::GetTensorShape(input); + const RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + const int trailing_dim = input_shape.DimensionsCount() - 1; + const int outer_size = + MatchingFlatSizeSkipDim(input_shape, trailing_dim, output_shape); + const int depth = + MatchingDim(input_shape, trailing_dim, output_shape, trailing_dim); + const int8_t *in_ptr = tflite::micro::GetTensorData(input); + int8_t *out_ptr = tflite::micro::GetTensorData(output); + void *scratch_buf = NULL; + if (data->buffer_idx > -1) { + scratch_buf = context->GetScratchBuffer(context, data->buffer_idx); + } + esp_nn_set_softmax_scratch_buf(scratch_buf); + esp_nn_softmax_s8(in_ptr, outer_size, depth, input_beta_multiplier, + input_beta_left_shift, diff_min, out_ptr); +#else + tflite::reference_ops::Softmax( + data->op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); +#endif + } + } else { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return; +#endif + tflite::reference_ops::SoftmaxInt16( + data->op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} + +static TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + TFLITE_DCHECK(node->user_data != nullptr); + NodeData data = *static_cast(node->user_data); + + long long start_time = esp_timer_get_time(); + switch (input->type) { + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + tflite::reference_ops::Softmax( + data.op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + break; + case kTfLiteInt8: +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + SoftmaxQuantized(context, input, output, &data); + break; + case kTfLiteInt16: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + SoftmaxQuantized(context, input, output, &data); + } + break; + default: + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; + } + softmax_total_time += esp_timer_get_time() - start_time; + return kTfLiteOk; +} + +static TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, NumDimensions(input) >= 1); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE(context, node->user_data != nullptr); + NodeData* data = static_cast(node->user_data); + SoftmaxParams* op_data = static_cast(&data->op_data); + + auto* params = static_cast(node->builtin_data); + auto ret_val = + CalculateSoftmaxParams(context, input, output, params, op_data); + +#if ESP_NN + if (output->type == kTfLiteInt8 && input->type == kTfLiteInt8) { + const int32_t input_width = input->dims->data[1]; + const int32_t input_height = input->dims->data[2]; + int scratch_buf_size = esp_nn_get_softmax_scratch_size(input_width, + input_height); + if (scratch_buf_size > 0) { + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, scratch_buf_size, &data->buffer_idx)); + } + } +#endif + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return ret_val; +} + +} // namespace + +TfLiteRegistration Register_SOFTMAX() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#else +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/softmax.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +void SoftmaxQuantized(const TfLiteEvalTensor* input, TfLiteEvalTensor* output, + const SoftmaxParams& op_data) { + if (input->type == kTfLiteInt8) { + if (output->type == kTfLiteInt16) { + tflite::reference_ops::Softmax( + op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + tflite::reference_ops::Softmax( + op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + } else { + tflite::reference_ops::SoftmaxInt16( + op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} + +TfLiteStatus SoftmaxEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + + TFLITE_DCHECK(node->user_data != nullptr); + SoftmaxParams op_data = *static_cast(node->user_data); + + switch (input->type) { + case kTfLiteFloat32: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_F32 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + tflite::reference_ops::Softmax( + op_data, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } + case kTfLiteInt8: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I8 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + SoftmaxQuantized(input, output, op_data); + return kTfLiteOk; + } + case kTfLiteInt16: { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; +#endif + SoftmaxQuantized(input, output, op_data); + return kTfLiteOk; + } + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } +} +} // namespace + +TfLiteRegistration Register_SOFTMAX() { + return tflite::micro::RegisterOp(SoftmaxInit, SoftmaxPrepare, SoftmaxEval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h new file mode 100644 index 0000000..fb15d38 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h @@ -0,0 +1,70 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_SOFTMAX_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_SOFTMAX_H_ + +#include "edge-impulse-sdk/classifier/ei_classifier_config.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" + +namespace tflite { + +void* SoftmaxInit(TfLiteContext* context, const char* buffer, size_t length); + +// Common helper function to SoftmaxPrepare. +TfLiteStatus CalculateSoftmaxParams(TfLiteContext* context, + const TfLiteTensor* input, + TfLiteTensor* output, + const TfLiteSoftmaxParams* params, + SoftmaxParams* op_data); + +TfLiteStatus SoftmaxPrepare(TfLiteContext* context, TfLiteNode* node); + +// This is the most generic TfLiteRegistration. The actual supported types may +// still be target dependent. The only requirement is that every implementation +// (reference or optimized) must define this function. +TfLiteRegistration Register_SOFTMAX(); + +#if defined(XTENSA) || defined(CMSIS_NN) +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int8 input and int16 output. +TfLiteRegistration Register_SOFTMAX_INT8_INT16(); +#else +inline TfLiteRegistration Register_SOFTMAX_INT8_INT16() { + return Register_SOFTMAX(); +} +#endif + +#if defined(CMSIS_NN) +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int8 input/output and uses the latency optimized implementations. +TfLiteRegistration Register_SOFTMAX_INT8(); + +// Returns a TfLiteRegistration struct for kernel variant that only supports +// int16 input/output and uses the latency optimized implementations. +TfLiteRegistration Register_SOFTMAX_INT16(); + +#else +inline TfLiteRegistration Register_SOFTMAX_INT8() { return Register_SOFTMAX(); } + +inline TfLiteRegistration Register_SOFTMAX_INT16() { + return Register_SOFTMAX(); +} +#endif + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_SOFTMAX_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax_common.cpp new file mode 100644 index 0000000..82ec071 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax_common.cpp @@ -0,0 +1,195 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" + +namespace tflite { + +namespace { +// Softmax parameter data that persists in user_data +const int kInt16LUTArraySize = LUTSize(); + +TfLiteStatus InitializeLutForInt16(TfLiteContext* context, + const TfLiteTensor* input, + TfLiteTensor* output, + SoftmaxParams* op_data) { + // Only allocate LUTs for KTfLiteInt16 data type + if (input->type == kTfLiteInt16) { + void* raw_exp_lut = context->AllocatePersistentBuffer( + context, sizeof(int16_t) * kInt16LUTArraySize); + TF_LITE_ENSURE(context, raw_exp_lut != nullptr); + op_data->exp_lut = reinterpret_cast(raw_exp_lut); + void* one_over_one_plus_x_lut = context->AllocatePersistentBuffer( + context, sizeof(int16_t) * kInt16LUTArraySize); + TF_LITE_ENSURE(context, one_over_one_plus_x_lut != nullptr); + op_data->one_over_one_plus_x_lut = + reinterpret_cast(one_over_one_plus_x_lut); + } + + if (output->type == kTfLiteInt16) { + TF_LITE_ENSURE(context, + input->type == kTfLiteInt8 || input->type == kTfLiteInt16); + } else { + TF_LITE_ENSURE_EQ(context, input->type, output->type); + } + + // Populate LUT if required + if (input->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + // exp LUT only used on negative values + // we consider exp(-10.0) is insignificant to accumulation + const int32_t range = std::numeric_limits::max() - + std::numeric_limits::min(); + LUTPopulate( + 10.0f / range, std::numeric_limits::max(), 2.0f / range, 0, + [](float value) { return std::exp(value); }, op_data->exp_lut); + + LUTPopulate( + 1.0f / range, std::numeric_limits::min(), 2.0f / range, 0, + [](float value) { return 1.0f / (1.0f + value); }, + op_data->one_over_one_plus_x_lut); + + op_data->zero_point = output->params.zero_point; + op_data->scale = output->params.scale; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteStatus CalculateSoftmaxParams(TfLiteContext* context, + const TfLiteTensor* input, + TfLiteTensor* output, + const TfLiteSoftmaxParams* params, + SoftmaxParams* op_data) { +#ifndef EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + if (InitializeLutForInt16(context, input, output, op_data) != kTfLiteOk) { + return kTfLiteError; + } +#endif + + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + if (input->type == kTfLiteInt16) { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + TF_LITE_ENSURE_EQ(context, input->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + TF_LITE_ENSURE_NEAR(context, output->params.scale, 1.f / 32768, + (0.001f * 1.f / 32768)); + } else { // input->type == kTfLiteInt8 +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteInt8); + if (output->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, output->params.zero_point, -32768); + TF_LITE_ENSURE_NEAR(context, output->params.scale, 1.f / 65536, + (0.001f * 1.f / 65536)); + } else { // output->type == kTfLiteint8 + TF_LITE_ENSURE_TYPES_EQ(context, output->type, kTfLiteInt8); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, -128); + TF_LITE_ENSURE(context, output->params.scale == 1.f / 256); + } + } + + static const int kScaledDiffIntegerBits = 5; + + // Calculate input_multiplier and input_left_shift + if (input->type == kTfLiteInt16) { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I16 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + int input_left_shift; + double input_scale_beta_rescale = + static_cast(input->params.scale) * + static_cast(params->beta) / + (10.0 / 65535.0); // scale the input_diff such that [-65535, 0] + // correspond to [-10.0, 0.0] + QuantizeMultiplier(input_scale_beta_rescale, &op_data->input_multiplier, + &input_left_shift); + op_data->input_left_shift = input_left_shift; + } else { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + int input_left_shift; + tflite::PreprocessSoftmaxScaling( + static_cast(params->beta), + static_cast(input->params.scale), kScaledDiffIntegerBits, + &op_data->input_multiplier, &input_left_shift); + op_data->input_left_shift = input_left_shift; + op_data->diff_min = + -1.0 * tflite::CalculateInputRadius(kScaledDiffIntegerBits, + op_data->input_left_shift); + } + } else { +#if EI_TFLITE_DISABLE_SOFTMAX_IN_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(input->type), input->type); + return kTfLiteError; +#endif + TF_LITE_ENSURE_TYPES_EQ(context, input->type, kTfLiteFloat32); + TF_LITE_ENSURE_TYPES_EQ(context, output->type, kTfLiteFloat32); + op_data->beta = static_cast(params->beta); + } + return kTfLiteOk; +} + +void* SoftmaxInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(SoftmaxParams)); +} + +TfLiteStatus SoftmaxPrepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, NumDimensions(input) >= 1); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE(context, node->user_data != nullptr); + SoftmaxParams* op_data = static_cast(node->user_data); + + auto* params = static_cast(node->builtin_data); + auto ret_val = + CalculateSoftmaxParams(context, input, output, params, op_data); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return ret_val; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/space_to_batch_nd.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/space_to_batch_nd.cpp new file mode 100644 index 0000000..5a7f414 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/space_to_batch_nd.cpp @@ -0,0 +1,121 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_batch_nd.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kBlockShapeTensor = 1; +constexpr int kCropsTensor = 2; +constexpr int kOutputTensor = 0; + +// Currently, only 3D NHC and 4D NHWC input/output op_context are supported. +// In case of 3D input, it will be extended to 3D NHWC by adding W=1. +// The 4D array need to have exactly 2 spatial dimensions. +// TODO(b/149952582): Support arbitrary dimension in SpaceToBatchND. +const int kInputOutputMinDimensionNum = 3; +const int kInputOutputMaxDimensionNum = 4; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(SpaceToBatchParams)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 3); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, input != nullptr && output != nullptr); + + TF_LITE_ENSURE(context, NumDimensions(input) >= kInputOutputMinDimensionNum); + TF_LITE_ENSURE(context, NumDimensions(output) >= kInputOutputMinDimensionNum); + TF_LITE_ENSURE(context, NumDimensions(input) <= kInputOutputMaxDimensionNum); + TF_LITE_ENSURE(context, NumDimensions(output) <= kInputOutputMaxDimensionNum); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const SpaceToBatchParams& params = + *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* block_shape = + tflite::micro::GetEvalInput(context, node, kBlockShapeTensor); + const TfLiteEvalTensor* crops = + tflite::micro::GetEvalInput(context, node, kCropsTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: + reference_ops::SpaceToBatchND( + params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(block_shape), + tflite::micro::GetTensorData(block_shape), + tflite::micro::GetTensorShape(crops), + tflite::micro::GetTensorData(crops), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: + reference_ops::SpaceToBatchND( + params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(block_shape), + tflite::micro::GetTensorData(block_shape), + tflite::micro::GetTensorShape(crops), + tflite::micro::GetTensorData(crops), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_SPACE_TO_BATCH_ND() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/space_to_depth.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/space_to_depth.cpp new file mode 100644 index 0000000..2ab0faa --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/space_to_depth.cpp @@ -0,0 +1,127 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/space_to_depth.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; +constexpr int kBatchRank = 0; +constexpr int kHeightRank = 1; +constexpr int kWidthRank = 2; +constexpr int kDepthRank = 3; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + auto* params = + reinterpret_cast(node->builtin_data); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_EQ(context, NumDimensions(input), 4); + + auto data_type = output->type; + TF_LITE_ENSURE(context, + data_type == kTfLiteFloat32 || data_type == kTfLiteInt8); + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + const int block_size = params->block_size; + const int input_height = input->dims->data[kHeightRank]; + const int input_width = input->dims->data[kWidthRank]; + int output_height = input_height / block_size; + int output_width = input_width / block_size; + + TF_LITE_ENSURE_EQ(context, input_height, output_height * block_size); + TF_LITE_ENSURE_EQ(context, input_width, output_width * block_size); + + // Relocate dims to the persistent storage arena before changing them, + // otherwise we'd be modifying temporary copies made by the interpreters each + // time they process the layer. + TfLiteEvalTensor* output_eval = + micro::GetEvalOutput(context, node, kOutputTensor); + TF_LITE_ENSURE_OK(context, micro::CreateWritableTensorDimsWithCopy( + context, output, output_eval)); + + output->dims->data[kBatchRank] = input->dims->data[kBatchRank]; + output->dims->data[kHeightRank] = output_height; + output->dims->data[kWidthRank] = output_width; + output->dims->data[kDepthRank] = + input->dims->data[kDepthRank] * block_size * block_size; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = + reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = micro::GetEvalOutput(context, node, kOutputTensor); + + SpaceToDepthParams op_params; + op_params.block_size = params->block_size; + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: + reference_ops::SpaceToDepth(op_params, micro::GetTensorShape(input), + micro::GetTensorData(input), + micro::GetTensorShape(output), + micro::GetTensorData(output)); + break; + case kTfLiteInt8: + reference_ops::SpaceToDepth(op_params, micro::GetTensorShape(input), + micro::GetTensorData(input), + micro::GetTensorShape(output), + micro::GetTensorData(output)); + break; + default: + MicroPrintf("SPACE_TO_DEPTH only supports FLOAT32 and INT8, got %s.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_SPACE_TO_DEPTH() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/split.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/split.cpp new file mode 100644 index 0000000..d4d5280 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/split.cpp @@ -0,0 +1,128 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace split { + +template +TfLiteStatus SplitImpl(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input, int axis_value) { + const int output_count = NumOutputs(node); + const TfLiteIntArray* input_dims = input->dims; + const TfLiteEvalTensor* output0 = + tflite::micro::GetEvalOutput(context, node, 0); + const TfLiteIntArray* output_dims = output0->dims; + + const int split_dimensions = input_dims->size; + int axis = axis_value < 0 ? axis_value + split_dimensions : axis_value; + + TFLITE_DCHECK_LT(axis, split_dimensions); + TFLITE_DCHECK_EQ(output_dims->size, split_dimensions); + + int64_t split_size = output_dims->data[axis] * output_count; + + TFLITE_DCHECK_EQ(split_size, input_dims->data[axis]); + int64_t outer_size = 1; + for (int i = 0; i < axis; ++i) { + outer_size *= input_dims->data[i]; + } + + int64_t base_inner_size = 1; + for (int i = axis + 1; i < split_dimensions; ++i) { + base_inner_size *= input_dims->data[i]; + } + + const T* input_ptr = tflite::micro::GetTensorData(input); + for (int k = 0; k < outer_size; ++k) { + for (int i = 0; i < output_count; ++i) { + TfLiteEvalTensor* t = tflite::micro::GetEvalOutput(context, node, i); + T* output_data = tflite::micro::GetTensorData(t); + const int copy_size = output_dims->data[axis] * base_inner_size; + T* output_ptr = output_data + k * copy_size; + for (int j = 0; j < copy_size; ++j) output_ptr[j] = input_ptr[j]; + input_ptr += copy_size; + } + } + + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* axis = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, axis != nullptr); + + // Dynamic output tensors are needed if axis tensor is not constant. + // But Micro doesn't support dynamic memory allocation, so we only support + // constant axis tensor for now. + TF_LITE_ENSURE_MSG(context, IsConstantTensor(axis), + "Non constant axis tensor not supported"); + + micro_context->DeallocateTempTfLiteTensor(axis); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 1); + + int axis_value = tflite::micro::GetTensorData(axis)[0]; + if (axis_value < 0) { + axis_value += input->dims->size; + } + + TF_LITE_ENSURE(context, axis_value >= 0); + TF_LITE_ENSURE(context, axis_value < input->dims->size); + + switch (input->type) { + case kTfLiteFloat32: { + return SplitImpl(context, node, input, axis_value); + } + case kTfLiteInt8: { + return SplitImpl(context, node, input, axis_value); + } + case kTfLiteInt16: { + return SplitImpl(context, node, input, axis_value); + } + case kTfLiteInt32: { + return SplitImpl(context, node, input, axis_value); + } + default: + MicroPrintf("Type %s currently not supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace split + +TfLiteRegistration Register_SPLIT() { + return tflite::micro::RegisterOp(nullptr, split::Prepare, split::Eval); +} + +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/split_v.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/split_v.cpp new file mode 100644 index 0000000..caf6083 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/split_v.cpp @@ -0,0 +1,127 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +template +TfLiteStatus SplitImpl(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input, int axis_value) { + const TfLiteIntArray* input_dims = input->dims; + const TfLiteEvalTensor* output0 = + tflite::micro::GetEvalOutput(context, node, 0); + + const int split_dimensions = input_dims->size; + + TFLITE_DCHECK_LT(axis_value, split_dimensions); + TFLITE_DCHECK_EQ(output0->dims->size, split_dimensions); + + int64_t split_size = 0; + const int output_count = NumOutputs(node); + for (int i = 0; i < output_count; i++) { + split_size += + tflite::micro::GetEvalOutput(context, node, i)->dims->data[axis_value]; + } + TFLITE_DCHECK_EQ(split_size, input_dims->data[axis_value]); + int64_t outer_size = 1; + for (int i = 0; i < axis_value; ++i) { + outer_size *= input_dims->data[i]; + } + + int64_t base_inner_size = 1; + for (int i = axis_value + 1; i < split_dimensions; ++i) { + base_inner_size *= input_dims->data[i]; + } + + const T* input_ptr = tflite::micro::GetTensorData(input); + for (int k = 0; k < outer_size; ++k) { + for (int i = 0; i < output_count; ++i) { + TfLiteEvalTensor* output_tensor = + tflite::micro::GetEvalOutput(context, node, i); + T* output_data = tflite::micro::GetTensorData(output_tensor); + const int copy_size = + output_tensor->dims->data[axis_value] * base_inner_size; + T* output_ptr = output_data + k * copy_size; + for (int j = 0; j < copy_size; ++j) output_ptr[j] = input_ptr[j]; + input_ptr += copy_size; + } + } + + return kTfLiteOk; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 3); + + MicroContext* micro_context = GetMicroContext(context); + // Dynamic output tensors are needed if axis tensor is not constant. + // But Micro doesn't support dynamic memory allocation, so we only support + // constant axis tensor for now. + TfLiteTensor* axis = micro_context->AllocateTempInputTensor(node, 2); + TF_LITE_ENSURE_MSG(context, IsConstantTensor(axis), + "Non constant axis tensor not supported"); + micro_context->DeallocateTempTfLiteTensor(axis); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + const TfLiteEvalTensor* axis = tflite::micro::GetEvalInput(context, node, 2); + + int axis_value = tflite::micro::GetTensorData(axis)[0]; + if (axis_value < 0) { + axis_value += input->dims->size; + } + + TF_LITE_ENSURE(context, axis_value >= 0); + TF_LITE_ENSURE(context, axis_value < input->dims->size); + + switch (input->type) { + case kTfLiteFloat32: { + return SplitImpl(context, node, input, axis_value); + } + case kTfLiteInt8: { + return SplitImpl(context, node, input, axis_value); + } + case kTfLiteInt16: { + return SplitImpl(context, node, input, axis_value); + } + case kTfLiteInt32: { + return SplitImpl(context, node, input, axis_value); + } + default: + MicroPrintf("Type %s currently not supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_SPLIT_V() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/squared_difference.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/squared_difference.cpp new file mode 100644 index 0000000..e45cbbe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/squared_difference.cpp @@ -0,0 +1,247 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/binary_function.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { +constexpr int kInputTensor1 = 0; +constexpr int kInputTensor2 = 1; +constexpr int kOutputTensor = 0; + +struct OpData { + bool requires_broadcast; + ArithmeticParams arithmetic_params; +}; + +template +T SquaredDifference(T input1, T input2) { + const T difference = input1 - input2; + return difference * difference; +} + +void* SquaredDifferenceInit(TfLiteContext* context, const char* buffer, + size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus SquaredDifferencePrepare(TfLiteContext* context, + TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + OpData* data = reinterpret_cast(node->user_data); + data->requires_broadcast = false; + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_TYPES_EQ(context, input1->type, input2->type); + output->type = input2->type; + + // Ensure the quantization parameters are equivalent. + if (input1->type == kTfLiteInt8) { + const auto& input1_quantization_params = input1->params; + const auto& input2_quantization_params = input2->params; + const auto& output_quantization_params = output->params; + const int32_t integer_type_min = std::numeric_limits::min(); + const int32_t integer_type_max = std::numeric_limits::max(); + TF_LITE_ENSURE(context, + input1_quantization_params.zero_point >= integer_type_min); + TF_LITE_ENSURE(context, + input1_quantization_params.zero_point <= integer_type_max); + TF_LITE_ENSURE(context, + input2_quantization_params.zero_point >= integer_type_min); + TF_LITE_ENSURE(context, + input2_quantization_params.zero_point <= integer_type_max); + TF_LITE_ENSURE(context, + output_quantization_params.zero_point >= integer_type_min); + TF_LITE_ENSURE(context, + output_quantization_params.zero_point <= integer_type_max); + data->arithmetic_params.input1_offset = + -input1_quantization_params.zero_point; + data->arithmetic_params.input2_offset = + -input2_quantization_params.zero_point; + data->arithmetic_params.output_offset = + output_quantization_params.zero_point; + + // shift to make integer for scales. + // 7 is selected so that maximum shifted result 255^2 * (1 << (7 * 2 )) + // does not overflow signed 32-bit integer + data->arithmetic_params.left_shift = 7; + const double twice_max_input_scale = + 2.0 * static_cast(std::max(input1_quantization_params.scale, + input2_quantization_params.scale)); + const double real_input1_multiplier = + static_cast(input1_quantization_params.scale) / + twice_max_input_scale; + double real_input2_multiplier = + static_cast(input2_quantization_params.scale) / + twice_max_input_scale; + const double real_output_multiplier = + (twice_max_input_scale * twice_max_input_scale) / + static_cast((1 << data->arithmetic_params.left_shift * 2) * + output_quantization_params.scale); + QuantizeMultiplierSmallerThanOneExp( + real_input1_multiplier, &data->arithmetic_params.input1_multiplier, + &data->arithmetic_params.input1_shift); + QuantizeMultiplierSmallerThanOneExp( + real_input2_multiplier, &data->arithmetic_params.input2_multiplier, + &data->arithmetic_params.input2_shift); + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->arithmetic_params.output_multiplier, + &data->arithmetic_params.output_shift); + data->arithmetic_params.quantized_activation_min = + std::numeric_limits::min(); + data->arithmetic_params.quantized_activation_max = + std::numeric_limits::max(); + } + + data->requires_broadcast = !HaveSameShapes(input1, input2); + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +inline int8_t SquaredDifference(int8_t x, int8_t y, + const ArithmeticParams& params) { + const int32_t input1_val = params.input1_offset + x; + const int32_t input2_val = params.input2_offset + y; + const int32_t shifted_input1_val = input1_val * (1 << params.left_shift); + const int32_t shifted_input2_val = input2_val * (1 << params.left_shift); + const int32_t scaled_input1_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input1_val, params.input1_multiplier, params.input1_shift); + const int32_t scaled_input2_val = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + shifted_input2_val, params.input2_multiplier, params.input2_shift); + const int32_t raw_diff = scaled_input1_val - scaled_input2_val; + + // Max of this is 255^2 * (1 << 14), so won't overflow 32 bits. + const int32_t squared_raw_diff = raw_diff * raw_diff; + const int32_t raw_output = + MultiplyByQuantizedMultiplierSmallerThanOneExp( + squared_raw_diff, params.output_multiplier, params.output_shift) + + params.output_offset; + const int32_t clamped_output = + std::min(params.quantized_activation_max, + std::max(params.quantized_activation_min, raw_output)); + return static_cast(clamped_output); +} + +template +void EvalQuantizedSquaredDifference(TfLiteContext* context, TfLiteNode* node, + const OpData* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + const auto* op_data = static_cast(node->user_data); + if (data->requires_broadcast) { + reference_integer_ops::BroadcastBinaryFunction4DSlow( + op_data->arithmetic_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + reference_integer_ops::CheckArithmeticParams, SquaredDifference); + } else { + const int flat_size = tflite::micro::GetTensorShape(input1).FlatSize(); + reference_integer_ops::ElementWise( + flat_size, op_data->arithmetic_params, + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorData(output), + reference_integer_ops::CheckArithmeticParams, SquaredDifference); + } +} + +template +void EvalSquaredDifference(TfLiteContext* context, TfLiteNode* node, + const OpData* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + if (data->requires_broadcast) { + reference_ops::BroadcastBinaryFunction4DSlow( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), SquaredDifference); + } else { + reference_ops::BinaryFunction( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), SquaredDifference); + } +} + +TfLiteStatus SquaredDifferenceEval(TfLiteContext* context, TfLiteNode* node) { + OpData* data = reinterpret_cast(node->user_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (output->type == kTfLiteFloat32) { + EvalSquaredDifference(context, node, data, input1, input2, output); + } else if (output->type == kTfLiteInt32) { + EvalSquaredDifference(context, node, data, input1, input2, output); + } else if (output->type == kTfLiteInt8) { + EvalQuantizedSquaredDifference(context, node, data, input1, input2, + output); + } else { + MicroPrintf( + "SquaredDifference only supports FLOAT32, INT32 and INT8 now, got %d.", + output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration Register_SQUARED_DIFFERENCE() { + return tflite::micro::RegisterOp( + SquaredDifferenceInit, SquaredDifferencePrepare, SquaredDifferenceEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/squeeze.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/squeeze.cpp new file mode 100644 index 0000000..8a42410 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/squeeze.cpp @@ -0,0 +1,118 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +struct SqueezeContext { + SqueezeContext(TfLiteContext* context, TfLiteNode* node) { + params = reinterpret_cast(node->builtin_data); + micro_context = GetMicroContext(context); + input = micro_context->AllocateTempInputTensor(node, 0); + output = micro_context->AllocateTempOutputTensor(node, 0); + } + ~SqueezeContext() { + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + } + MicroContext* micro_context; + TfLiteSqueezeParams* params; + TfLiteTensor* input; + TfLiteTensor* output; +}; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + SqueezeContext op_context(context, node); + const int input_num_dims = NumDimensions(op_context.input); + const int num_squeeze_dims = op_context.params->num_squeeze_dims; + + // Determines number of dimensions of output tensor after squeeze. + const TfLiteIntArray* input_dims = op_context.input->dims; + const TfLiteIntArray* output_dims = op_context.output->dims; + const int* squeeze_dims = op_context.params->squeeze_dims; + + constexpr int max_squeeze_dims = 8; + TF_LITE_ENSURE(context, input_num_dims <= max_squeeze_dims); + bool should_squeeze[max_squeeze_dims] = {}; + + if (num_squeeze_dims == 0) { + for (int idx = 0; idx < input_num_dims; ++idx) { + if (input_dims->data[idx] == 1) { + should_squeeze[idx] = true; + } + } + } else { + for (int idx = 0; idx < num_squeeze_dims; ++idx) { + int current = squeeze_dims[idx] < 0 ? squeeze_dims[idx] + input_num_dims + : squeeze_dims[idx]; + TF_LITE_ENSURE(context, current >= 0 && current < input_num_dims && + input_dims->data[current] == 1); + should_squeeze[current] = true; + } + } + + // Ensure output dimensions are big enough. + for (int in_idx = 0, out_idx = 0; in_idx < input_num_dims; ++in_idx) { + if (!should_squeeze[in_idx]) { + TFLITE_CHECK_GE(output_dims->data[out_idx++], input_dims->data[in_idx]); + } + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + + if (input->type == kTfLiteString) { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + size_t input_byte_size; + size_t output_byte_size; + TF_LITE_ENSURE_OK(context, + TfLiteEvalTensorByteLength(input, &input_byte_size)); + TF_LITE_ENSURE_OK(context, + TfLiteEvalTensorByteLength(output, &output_byte_size)); + + TF_LITE_ENSURE_EQ(context, input_byte_size, output_byte_size); + memcpy(output->data.raw, input->data.raw, input_byte_size); + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_SQUEEZE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/strided_slice.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/strided_slice.cpp new file mode 100644 index 0000000..b8c5d71 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/strided_slice.cpp @@ -0,0 +1,250 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/strided_slice.h" + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { + +constexpr int kInputTensor = 0; +constexpr int kBeginTensor = 1; +constexpr int kEndTensor = 2; +constexpr int kStridesTensor = 3; +constexpr int kOutputTensor = 0; + +struct StridedSliceContext { + StridedSliceContext(TfLiteContext* context, TfLiteNode* node) { + params = reinterpret_cast(node->builtin_data); + micro_context = GetMicroContext(context); + input = micro_context->AllocateTempInputTensor(node, kInputTensor); + begin = micro_context->AllocateTempInputTensor(node, kBeginTensor); + end = micro_context->AllocateTempInputTensor(node, kEndTensor); + strides = micro_context->AllocateTempInputTensor(node, kStridesTensor); + output = micro_context->AllocateTempOutputTensor(node, kOutputTensor); + dims = NumDimensions(input); + } + ~StridedSliceContext() { + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(begin); + micro_context->DeallocateTempTfLiteTensor(end); + micro_context->DeallocateTempTfLiteTensor(strides); + micro_context->DeallocateTempTfLiteTensor(output); + } + const TfLiteStridedSliceParams* params; + MicroContext* micro_context; + TfLiteTensor* input; + TfLiteTensor* begin; + TfLiteTensor* end; + TfLiteTensor* strides; + TfLiteTensor* output; + int dims; +}; + +// This Op only supports 1-4D cases and since we use the reference 4D +// implementation, the 1-3D tensors are mapped to 4D. +const int kMaxDim = 4; + +tflite::StridedSliceParams BuildStridedSliceParams( + StridedSliceContext* op_context) { + tflite::StridedSliceParams op_params; + op_params.start_indices_count = op_context->dims; + op_params.stop_indices_count = op_context->dims; + op_params.strides_count = op_context->dims; + + for (int i = 0; i < op_context->dims; ++i) { + op_params.start_indices[i] = GetTensorData(op_context->begin)[i]; + op_params.stop_indices[i] = GetTensorData(op_context->end)[i]; + op_params.strides[i] = GetTensorData(op_context->strides)[i]; + } + + op_params.begin_mask = op_context->params->begin_mask; + op_params.ellipsis_mask = 0; + op_params.end_mask = op_context->params->end_mask; + op_params.new_axis_mask = 0; + op_params.shrink_axis_mask = op_context->params->shrink_axis_mask; + return op_params; +} + +// Processes the indexing tensors (begin, end and strides) to resize the +// output tensor. This function is callable from both Prepare() and Eval() as +// long as the caller ensures the indexing tensors are present. +TfLiteStatus CheckOutputSize(TfLiteContext* context, + StridedSliceContext* op_context) { + using ::tflite::strided_slice::StartForAxis; + using ::tflite::strided_slice::StopForAxis; + TfLiteIntArray* output_shape = op_context->output->dims; + int shape_size = 0; + auto op_params = BuildStridedSliceParams(op_context); + auto input_shape = GetTensorShape(op_context->input); + for (int idx = 0; idx < op_context->dims; ++idx) { + int32_t stride = GetTensorData(op_context->strides)[idx]; + TF_LITE_ENSURE_MSG(context, stride != 0, "stride value has to be non-zero"); + int32_t begin = StartForAxis(op_params, input_shape, idx); + int32_t end = StopForAxis(op_params, input_shape, idx, begin); + + // When shrinking an axis, the end position does not matter (and can be + // incorrect when negative indexing is used, see Issue #19260). Always use + // begin + 1 to generate a length 1 slice, since begin has + // already been adjusted for negative indices by StartForAxis. + const bool shrink_axis = op_context->params->shrink_axis_mask & (1 << idx); + if (shrink_axis) { + end = begin + 1; + } + + // This is valid for both positive and negative strides + int32_t dim_shape = std::ceil((end - begin) / static_cast(stride)); + dim_shape = dim_shape < 0 ? 0 : dim_shape; + if (!shrink_axis) { + TF_LITE_ENSURE_EQ(context, output_shape->data[shape_size], dim_shape); + shape_size++; + } + } + TF_LITE_ENSURE_EQ(context, output_shape->size, shape_size); + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(StridedSliceParams)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + StridedSliceParams* op_params = + static_cast(node->user_data); + TF_LITE_ENSURE_EQ(context, NumInputs(node), 4); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + StridedSliceContext op_context(context, node); + TF_LITE_ENSURE_MSG(context, op_context.dims <= kMaxDim, + "input dim should not exceed 4"); + auto params = BuildStridedSliceParams(&op_context); + memcpy(op_params, ¶ms, sizeof(StridedSliceParams)); + return CheckOutputSize(context, &op_context); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const StridedSliceParams& op_params = + *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + switch (output->type) { + case kTfLiteFloat32: + #if EI_TFLITE_DISABLE_STRIDED_SLICE_OUT_F32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + #endif + + reference_ops::StridedSlice(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteUInt8: + #if EI_TFLITE_DISABLE_STRIDED_SLICE_OUT_U8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + #endif + + reference_ops::StridedSlice( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: + #if EI_TFLITE_DISABLE_STRIDED_SLICE_OUT_I8 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + #endif + + reference_ops::StridedSlice(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt16: + #if EI_TFLITE_DISABLE_STRIDED_SLICE_OUT_I16 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + #endif + + reference_ops::StridedSlice( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt32: + #if EI_TFLITE_DISABLE_STRIDED_SLICE_OUT_I32 + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + #endif + + reference_ops::StridedSlice( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteBool: + #if EI_TFLITE_DISABLE_STRIDED_SLICE_OUT_BOOL + TF_LITE_KERNEL_LOG(context, "Type %s (%d) not supported.", + TfLiteTypeGetName(output->type), output->type); + return kTfLiteError; + #endif + + reference_ops::StridedSlice(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_STRIDED_SLICE() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.cpp new file mode 100644 index 0000000..266d6b5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.cpp @@ -0,0 +1,168 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/sub.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +void* SubInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataSub)); +} + +void EvalSub(TfLiteContext* context, TfLiteNode* node, TfLiteSubParams* params, + const OpDataSub* data, const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, TfLiteEvalTensor* output) { + float output_activation_min, output_activation_max; + CalculateActivationRange(params->activation, &output_activation_min, + &output_activation_max); + tflite::ArithmeticParams op_params; + SetActivationParams(output_activation_min, output_activation_max, &op_params); + if (data->requires_broadcast) { + tflite::reference_ops::BroadcastSubSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + tflite::reference_ops::SubWithActivation( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } +} + +TfLiteStatus EvalSubQuantized(TfLiteContext* context, TfLiteNode* node, + TfLiteSubParams* params, const OpDataSub* data, + const TfLiteEvalTensor* input1, + const TfLiteEvalTensor* input2, + TfLiteEvalTensor* output) { + tflite::ArithmeticParams op_params; + op_params.left_shift = data->left_shift; + op_params.input1_offset = data->input1_offset; + op_params.input1_multiplier = data->input1_multiplier; + op_params.input1_shift = data->input1_shift; + op_params.input2_offset = data->input2_offset; + op_params.input2_multiplier = data->input2_multiplier; + op_params.input2_shift = data->input2_shift; + op_params.output_offset = data->output_offset; + op_params.output_multiplier = data->output_multiplier; + op_params.output_shift = data->output_shift; + SetActivationParams(data->output_activation_min, data->output_activation_max, + &op_params); + bool need_broadcast = reference_ops::ProcessBroadcastShapes( + tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorShape(input2), &op_params); + + switch (output->type) { + case kTfLiteInt8: { + if (need_broadcast) { + tflite::reference_ops::BroadcastQuantSubSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + tflite::reference_ops::Sub( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + break; + } + case kTfLiteInt16: { + if (need_broadcast) { + tflite::reference_ops::BroadcastQuantSubSlow( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } else { + tflite::reference_ops::Sub( + op_params, tflite::micro::GetTensorShape(input1), + tflite::micro::GetTensorData(input1), + tflite::micro::GetTensorShape(input2), + tflite::micro::GetTensorData(input2), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + } + break; + } + default: + MicroPrintf("Quantized type %s not currently supported.", + TfLiteTypeGetName(output->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus SubEval(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, kSubInputTensor1); + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, kSubInputTensor2); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kSubOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataSub& data = *(static_cast(node->user_data)); + + if (output->type == kTfLiteFloat32) { + EvalSub(context, node, params, &data, input1, input2, output); + } else if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + TF_LITE_ENSURE_OK(context, EvalSubQuantized(context, node, params, &data, + input1, input2, output)); + } else { + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(output->type), + output->type); + return kTfLiteError; + } + + return kTfLiteOk; +} + +TfLiteRegistration Register_SUB() { + return tflite::micro::RegisterOp(SubInit, SubPrepare, SubEval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.h new file mode 100644 index 0000000..36608d5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.h @@ -0,0 +1,60 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_SUB_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_SUB_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +extern const int kSubInputTensor1; +extern const int kSubInputTensor2; +extern const int kSubOutputTensor; + +struct OpDataSub { + bool requires_broadcast; + + // These fields are used in both the general 8-bit -> 8bit quantized path, + // and the special 16-bit -> 16bit quantized path + int input1_shift; + int input2_shift; + int32_t output_activation_min; + int32_t output_activation_max; + + // These fields are used only in the general 8-bit -> 8bit quantized path + int32_t input1_multiplier; + int32_t input2_multiplier; + int32_t output_multiplier; + int output_shift; + int left_shift; + int32_t input1_offset; + int32_t input2_offset; + int32_t output_offset; +}; + +TfLiteStatus CalculateOpDataSub(TfLiteContext* context, TfLiteSubParams* params, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteTensor* output, OpDataSub* data); + +TfLiteStatus SubPrepare(TfLiteContext* context, TfLiteNode* node); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_SUB_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub_common.cpp new file mode 100644 index 0000000..fcb8d4b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/sub_common.cpp @@ -0,0 +1,109 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/add.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/sub.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/sub.h" + +namespace tflite { + +const int kSubInputTensor1 = 0; +const int kSubInputTensor2 = 1; +const int kSubOutputTensor = 0; + +TfLiteStatus CalculateOpDataSub(TfLiteContext* context, TfLiteSubParams* params, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteTensor* output, OpDataSub* data) { + data->requires_broadcast = !HaveSameShapes(input1, input2); + + if (output->type == kTfLiteInt8 || output->type == kTfLiteInt16) { + // 8bit -> 8bit general quantized path, with general rescalings + data->input1_offset = -input1->params.zero_point; + data->input2_offset = -input2->params.zero_point; + data->output_offset = output->params.zero_point; + + // The shift is set to 15 in case of 16-bit and 20 in case of 8-bit, + // accordingly. In case of 16-bit we have 65535 << 15 which is less than 1 + // << 31, therefore the addition will still fit in a 32 bit accumulator. + data->left_shift = output->type == kTfLiteInt16 ? 15 : 20; + const float twice_max_input_scale = + 2 * std::max(input1->params.scale, input2->params.scale); + const double real_input1_multiplier = + static_cast(input1->params.scale) / + static_cast(twice_max_input_scale); + const double real_input2_multiplier = + static_cast(input2->params.scale) / + static_cast(twice_max_input_scale); + const double real_output_multiplier = + static_cast(twice_max_input_scale) / + ((1 << data->left_shift) * static_cast(output->params.scale)); + + QuantizeMultiplierSmallerThanOneExp( + real_input1_multiplier, &data->input1_multiplier, &data->input1_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_input2_multiplier, &data->input2_multiplier, &data->input2_shift); + + QuantizeMultiplierSmallerThanOneExp( + real_output_multiplier, &data->output_multiplier, &data->output_shift); + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, params->activation, output, &data->output_activation_min, + &data->output_activation_max)); + } + + return kTfLiteOk; +} + +TfLiteStatus SubPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpDataSub* data = static_cast(node->user_data); + auto* params = reinterpret_cast(node->builtin_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input1 = + micro_context->AllocateTempInputTensor(node, kSubInputTensor1); + TF_LITE_ENSURE(context, input1 != nullptr); + TfLiteTensor* input2 = + micro_context->AllocateTempInputTensor(node, kSubInputTensor2); + TF_LITE_ENSURE(context, input2 != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kSubOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_STATUS( + CalculateOpDataSub(context, params, input1, input2, output, data)); + + micro_context->DeallocateTempTfLiteTensor(input1); + micro_context->DeallocateTempTfLiteTensor(input2); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.cpp new file mode 100644 index 0000000..e9b50e5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.cpp @@ -0,0 +1,339 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_CMSIS_NN == 1 +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.h" + +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nn_types.h" +#include "edge-impulse-sdk/CMSIS/NN/Include/arm_nnfunctions.h" +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/activation_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataSvdf)); +} + +TfLiteStatus EvalIntegerSVDF(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input_tensor, + const TfLiteEvalTensor* weights_feature_tensor, + const TfLiteEvalTensor* weights_time_tensor, + const TfLiteEvalTensor* bias_tensor, + const TfLiteSVDFParams* params, + TfLiteEvalTensor* activation_state_tensor, + TfLiteEvalTensor* output_tensor, + const OpDataSvdf& data) { + cmsis_nn_dims input_dims; + input_dims.n = input_tensor->dims->data[0]; + input_dims.h = input_tensor->dims->data[1]; + + cmsis_nn_dims weights_feature_dims; + weights_feature_dims.n = weights_feature_tensor->dims->data[0]; + weights_feature_dims.h = weights_feature_tensor->dims->data[1]; + + cmsis_nn_dims weights_time_dims; + weights_time_dims.n = weights_time_tensor->dims->data[0]; + weights_time_dims.h = weights_time_tensor->dims->data[1]; + + cmsis_nn_dims bias_dims; + bias_dims.n = bias_tensor->dims->data[0]; + + cmsis_nn_dims state_dims; + state_dims.n = bias_tensor->dims->data[0]; + state_dims.h = bias_tensor->dims->data[1]; + + cmsis_nn_dims output_dims; + output_dims.n = output_tensor->dims->data[0]; + output_dims.h = output_tensor->dims->data[1]; + + cmsis_nn_svdf_params svdf_params; + svdf_params.rank = params->rank; + svdf_params.input_offset = data.input_zero_point; + svdf_params.output_offset = data.output_zero_point; + + svdf_params.input_activation.min = INT16_MIN; + svdf_params.input_activation.max = INT16_MAX; + + svdf_params.output_activation.min = INT8_MIN; + svdf_params.output_activation.max = INT8_MAX; + + cmsis_nn_per_tensor_quant_params in_quant_params; + in_quant_params.multiplier = data.effective_scale_1_a; + in_quant_params.shift = data.effective_scale_1_b; + + cmsis_nn_per_tensor_quant_params out_quant_params; + out_quant_params.multiplier = data.effective_scale_2_a; + out_quant_params.shift = data.effective_scale_2_b; + + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(context->GetScratchBuffer != nullptr); + + cmsis_nn_context scratch_ctx; + scratch_ctx.buf = static_cast( + context->GetScratchBuffer(context, data.scratch_tensor_index)); + + cmsis_nn_context scratch_output_ctx; + scratch_output_ctx.buf = static_cast( + context->GetScratchBuffer(context, data.scratch_output_tensor_index)); + + int8_t* output_data = tflite::micro::GetTensorData(output_tensor); + + switch (weights_time_tensor->type) { + case kTfLiteInt8: { + arm_svdf_s8( + &scratch_ctx, &scratch_output_ctx, &svdf_params, &in_quant_params, + &out_quant_params, &input_dims, + tflite::micro::GetTensorData(input_tensor), &state_dims, + tflite::micro::GetTensorData(activation_state_tensor), + &weights_feature_dims, + tflite::micro::GetTensorData(weights_feature_tensor), + &weights_time_dims, + tflite::micro::GetTensorData(weights_time_tensor), &bias_dims, + tflite::micro::GetTensorData(bias_tensor), &output_dims, + output_data); + return kTfLiteOk; + } + + case kTfLiteInt16: { + arm_svdf_state_s16_s8( + &scratch_ctx, &scratch_output_ctx, &svdf_params, &in_quant_params, + &out_quant_params, &input_dims, + tflite::micro::GetTensorData(input_tensor), &state_dims, + tflite::micro::GetTensorData(activation_state_tensor), + &weights_feature_dims, + tflite::micro::GetTensorData(weights_feature_tensor), + &weights_time_dims, + tflite::micro::GetTensorData(weights_time_tensor), + &bias_dims, tflite::micro::GetTensorData(bias_tensor), + &output_dims, output_data); + return kTfLiteOk; + } + + default: + MicroPrintf("Could not find matching function for type %s.", + TfLiteTypeGetName(weights_time_tensor->type)); + return kTfLiteError; + } +} + +TfLiteStatus EvalSvdf(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataSvdf& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kSvdfInputTensor); + const TfLiteEvalTensor* weights_feature = + tflite::micro::GetEvalInput(context, node, kSvdfWeightsFeatureTensor); + const TfLiteEvalTensor* weights_time = + tflite::micro::GetEvalInput(context, node, kSvdfWeightsTimeTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 5) + ? tflite::micro::GetEvalInput(context, node, kSvdfBiasTensor) + : nullptr; + TfLiteEvalTensor* activation_state = tflite::micro::GetMutableEvalInput( + context, node, kSvdfInputActivationStateTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kSvdfOutputTensor); + + switch (weights_time->type) { + case kTfLiteFloat32: { + EvalFloatSvdfReference( + context, node, input, weights_feature, weights_time, bias, params, + data.scratch_tensor_index, activation_state, output); + return kTfLiteOk; + } + + case kTfLiteInt8: + case kTfLiteInt16: { + return EvalIntegerSVDF(context, node, input, weights_feature, + weights_time, bias, params, activation_state, + output, data); + } + + default: + MicroPrintf("Type %s not currently supported.", + TfLiteTypeGetName(weights_feature->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus EvalSvdfInt8(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataSvdf& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kSvdfInputTensor); + const TfLiteEvalTensor* weights_feature = + tflite::micro::GetEvalInput(context, node, kSvdfWeightsFeatureTensor); + const TfLiteEvalTensor* weights_time = + tflite::micro::GetEvalInput(context, node, kSvdfWeightsTimeTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 5) + ? tflite::micro::GetEvalInput(context, node, kSvdfBiasTensor) + : nullptr; + TfLiteEvalTensor* activation_state = tflite::micro::GetMutableEvalInput( + context, node, kSvdfInputActivationStateTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kSvdfOutputTensor); + + TFLITE_DCHECK((weights_time->type == kTfLiteInt8) || + (weights_time->type == kTfLiteInt16)); + // Because of the TODO mentioned below, the int16 weight data type is not + // split into a seperate registration. + // TODO(#523): remove 16-bit code when no longer needed. + return EvalIntegerSVDF(context, node, input, weights_feature, weights_time, + bias, params, activation_state, output, data); +} + +} // namespace + +TfLiteRegistration Register_SVDF() { + return tflite::micro::RegisterOp(Init, PrepareSvdf, EvalSvdf); +} + +TfLiteRegistration Register_SVDF_INT8() { + return tflite::micro::RegisterOp(Init, PrepareSvdf, EvalSvdfInt8); +} + +} // namespace tflite + +#else +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/activation_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace { + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataSvdf)); +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + auto* params = reinterpret_cast(node->builtin_data); + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataSvdf& data = *(static_cast(node->user_data)); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kSvdfInputTensor); + const TfLiteEvalTensor* weights_feature = + tflite::micro::GetEvalInput(context, node, kSvdfWeightsFeatureTensor); + const TfLiteEvalTensor* weights_time = + tflite::micro::GetEvalInput(context, node, kSvdfWeightsTimeTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 5) + ? tflite::micro::GetEvalInput(context, node, kSvdfBiasTensor) + : nullptr; + TfLiteEvalTensor* activation_state = tflite::micro::GetMutableEvalInput( + context, node, kSvdfInputActivationStateTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kSvdfOutputTensor); + + switch (weights_feature->type) { + case kTfLiteFloat32: { + EvalFloatSvdfReference( + context, node, input, weights_feature, weights_time, bias, params, + data.scratch_tensor_index, activation_state, output); + return kTfLiteOk; + break; + } + + case kTfLiteInt8: { + switch (weights_time->type) { + case kTfLiteInt16: { + EvalInt16SvdfReference(context, node, input, weights_feature, + weights_time, bias, params, activation_state, + output, data); + return kTfLiteOk; + break; + } + case kTfLiteInt8: { + EvalInt8SvdfReference(context, node, input, weights_feature, + weights_time, bias, params, activation_state, + output, data); + return kTfLiteOk; + break; + } + default: + MicroPrintf("Type %s not currently supported.", + TfLiteTypeGetName(weights_time->type)); + return kTfLiteError; + } + } + + default: + MicroPrintf("Type %s not currently supported.", + TfLiteTypeGetName(weights_feature->type)); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_SVDF() { + return tflite::micro::RegisterOp(Init, PrepareSvdf, Eval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.h new file mode 100644 index 0000000..8bc068e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.h @@ -0,0 +1,99 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_SVDF_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_SVDF_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +struct OpDataSvdf { + int32_t effective_scale_1_a; + int32_t effective_scale_2_a; + // b versions of each scale are kept at int since the numbers are just the + // shift value - typically between [-32, 32]. + int effective_scale_1_b; + int effective_scale_2_b; + int scratch_tensor_index; + int scratch_output_tensor_index; + + // Cached tensor zero point values for quantized operations. + int input_zero_point; + int output_zero_point; + int activation_state_zero_point; +}; + +// Input tensors. +extern const int kSvdfInputTensor; +extern const int kSvdfWeightsFeatureTensor; +extern const int kSvdfWeightsTimeTensor; +extern const int kSvdfBiasTensor; +// This is a variable tensor, and will be modified by this op. +extern const int kSvdfInputActivationStateTensor; + +// Output tensor. +extern const int kSvdfOutputTensor; + +void EvalInt8SvdfReference(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input_tensor, + const TfLiteEvalTensor* weights_feature_tensor, + const TfLiteEvalTensor* weights_time_tensor, + const TfLiteEvalTensor* bias_tensor, + const TfLiteSVDFParams* params, + TfLiteEvalTensor* activation_state_tensor, + TfLiteEvalTensor* output_tensor, + const OpDataSvdf& data); + +// TODO(#523): remove 16-bit code when no longer needed. +void EvalInt16SvdfReference(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input_tensor, + const TfLiteEvalTensor* weights_feature_tensor, + const TfLiteEvalTensor* weights_time_tensor, + const TfLiteEvalTensor* bias_tensor, + const TfLiteSVDFParams* params, + TfLiteEvalTensor* activation_state_tensor, + TfLiteEvalTensor* output_tensor, + const OpDataSvdf& data); + +void EvalFloatSvdfReference( + TfLiteContext* context, TfLiteNode* node, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* weights_feature, + const TfLiteEvalTensor* weights_time, const TfLiteEvalTensor* bias, + const TfLiteSVDFParams* params, int scratch_tensor_index, + TfLiteEvalTensor* activation_state, TfLiteEvalTensor* output); + +TfLiteStatus PrepareSvdf(TfLiteContext* context, TfLiteNode* node); + +// This is the most generic TfLiteRegistration. The actual supported types may +// still be target dependent. The only requirement is that every implementation +// (reference or optimized) must define this function. +TfLiteRegistration Register_SVDF(); + +#if defined(HEXAGON) || defined(CMSIS_NN) +TfLiteRegistration Register_SVDF_INT8(); + +#else +// Note that while this block gets used for both reference and optimized kernels +// that do not have any specialized implementations, the only goal here is to +// define fallback implementation that allow reference kernels to still be used +// from applications that call a more specific kernel variant. + +inline TfLiteRegistration Register_SVDF_INT8() { return Register_SVDF(); } + +#endif +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_SVDF_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf_common.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf_common.cpp new file mode 100644 index 0000000..bdc36b8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf_common.cpp @@ -0,0 +1,516 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/activation_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/svdf.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +/** + * This version of SVDF is specific to TFLite Micro. It contains the following + * differences between the TFLite version: + * + * 1.) Scratch tensor allocation - scratch tensors must be known ahead of time + * for the Micro interpreter. + * 2.) Output dimensions - the TFLite version determines output size and runtime + * and resizes the output tensor. Micro runtime does not support tensor + * resizing. + */ + +const int kSvdfInputTensor = 0; +const int kSvdfWeightsFeatureTensor = 1; +const int kSvdfWeightsTimeTensor = 2; +const int kSvdfBiasTensor = 3; +const int kSvdfInputActivationStateTensor = + 4; // This is a variable tensor, and will be modified by this op. +const int kSvdfOutputTensor = 0; + +template +void EvalIntegerSvdfReference(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input_tensor, + const TfLiteEvalTensor* weights_feature_tensor, + const TfLiteEvalTensor* weights_time_tensor, + const TfLiteEvalTensor* bias_tensor, + const TfLiteSVDFParams* params, + TfLiteEvalTensor* activation_state_tensor, + TfLiteEvalTensor* output_tensor, + const OpDataSvdf& data) { + const int n_rank = params->rank; + const int n_batch = input_tensor->dims->data[0]; + const int n_input = input_tensor->dims->data[1]; + const int n_filter = weights_feature_tensor->dims->data[0]; + const int n_unit = n_filter / n_rank; + const int n_memory = weights_time_tensor->dims->data[1]; + + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(context->GetScratchBuffer != nullptr); + + int32_t* scratch_tensor = static_cast( + context->GetScratchBuffer(context, data.scratch_tensor_index)); + int32_t* scratch_output_tensor = static_cast( + context->GetScratchBuffer(context, data.scratch_output_tensor_index)); + + // Shift states. + T* const state_ptr = tflite::micro::GetTensorData(activation_state_tensor); + + // Left shift the activation_state. + { + T* new_state_start = state_ptr; + const T* old_state_start = state_ptr + 1; + const T* old_state_end = state_ptr + n_batch * n_filter * n_memory; + while (old_state_start != old_state_end) { + *new_state_start++ = *old_state_start++; + } + } + + // Note: no need to clear the latest activation, matmul is not accumulative. + + // Feature matmul. + { + T* state = tflite::micro::GetTensorData(activation_state_tensor); + const int8_t* input = tflite::micro::GetTensorData(input_tensor); + const int8_t* weight_feature = + tflite::micro::GetTensorData(weights_feature_tensor); + const int32_t output_max = std::numeric_limits::max(); + const int32_t output_min = std::numeric_limits::min(); + T* result_in_batch = state + (n_memory - 1); + for (int b = 0; b < n_batch; b++) { + const int8_t* matrix_ptr = weight_feature; + for (int r = 0; r < n_filter; r++) { + int32_t dot_prod = 0; + const int8_t* vector_in_batch = input + b * n_input; + for (int c = 0; c < n_input; c++) { + dot_prod += + *matrix_ptr++ * (*vector_in_batch++ - data.input_zero_point); + } + dot_prod = MultiplyByQuantizedMultiplier( + dot_prod, data.effective_scale_1_a, data.effective_scale_1_b); + dot_prod = std::min(std::max(output_min, dot_prod), output_max); + // The int16 version of the op assumes a zero_point of 0. This + // code accounts for the potentially non-zero zero_point for the int8 + // version of the op. + *result_in_batch = data.activation_state_zero_point + dot_prod; + result_in_batch += n_memory; + } + } + } + + // Time. + { + for (int b = 0; b < n_batch; ++b) { + int32_t* scratch_ptr_batch = scratch_tensor + b * n_filter; + + // Perform batched vector dot product: + const T* vector1_ptr = + tflite::micro::GetTensorData(weights_time_tensor); + const T* vector2_ptr = + tflite::micro::GetTensorData(activation_state_tensor) + + b * n_memory * n_filter; + + for (int i = 0; i < n_filter; i++) { + *scratch_ptr_batch = 0; + for (int j = 0; j < n_memory; j++) { + *scratch_ptr_batch += + *vector1_ptr++ * + (*vector2_ptr++ - data.activation_state_zero_point); + } + scratch_ptr_batch++; + } + } + } + + // Reduce, add bias, rescale, activation. + { + // Add bias. + if (bias_tensor) { + // Vector batch assign: + const int32_t* bias_data = + tflite::micro::GetTensorData(bias_tensor); + for (int i = 0; i < n_batch; ++i) { + int32_t* output_ptr = scratch_output_tensor + i * n_unit; + const int32_t* bias_ptr = bias_data; + for (int j = 0; j < n_unit; ++j) { + *output_ptr++ = *bias_ptr++; + } + } + } else { + int32_t* output_ptr = scratch_output_tensor; + for (int i = 0; i < n_batch * n_unit; ++i) { + *output_ptr++ = 0; + } + } + + // Reduce. + for (int b = 0; b < n_batch; ++b) { + int32_t* output_temp_ptr = scratch_output_tensor + b * n_unit; + int32_t* scratch_ptr_batch = scratch_tensor + b * n_filter; + + // Reduction sum vector + for (int i = 0; i < n_unit; ++i) { + for (int j = 0; j < n_rank; ++j) { + output_temp_ptr[i] += *scratch_ptr_batch++; + } + } + } + + // Rescale. + const int32_t output_max = std::numeric_limits::max(); + const int32_t output_min = std::numeric_limits::min(); + for (int i = 0; i < n_batch * n_unit; ++i) { + int32_t x1 = scratch_output_tensor[i]; + int32_t x2 = MultiplyByQuantizedMultiplier(x1, data.effective_scale_2_a, + data.effective_scale_2_b); + int32_t x3 = x2 + data.output_zero_point; + int32_t x4 = std::min(std::max(output_min, x3), output_max); + tflite::micro::GetTensorData(output_tensor)[i] = + static_cast(x4); + } + } +} + +/** + * Generate two versions of the integer code. One with int16_t type for the + * time weights and the activation state, and another one with int8_t for the + * same. + */ + +void EvalInt16SvdfReference(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input_tensor, + const TfLiteEvalTensor* weights_feature_tensor, + const TfLiteEvalTensor* weights_time_tensor, + const TfLiteEvalTensor* bias_tensor, + const TfLiteSVDFParams* params, + TfLiteEvalTensor* activation_state_tensor, + TfLiteEvalTensor* output_tensor, + const OpDataSvdf& data) { + EvalIntegerSvdfReference( + context, node, input_tensor, weights_feature_tensor, weights_time_tensor, + bias_tensor, params, activation_state_tensor, output_tensor, data); +} + +void EvalInt8SvdfReference(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input_tensor, + const TfLiteEvalTensor* weights_feature_tensor, + const TfLiteEvalTensor* weights_time_tensor, + const TfLiteEvalTensor* bias_tensor, + const TfLiteSVDFParams* params, + TfLiteEvalTensor* activation_state_tensor, + TfLiteEvalTensor* output_tensor, + const OpDataSvdf& data) { + EvalIntegerSvdfReference( + context, node, input_tensor, weights_feature_tensor, weights_time_tensor, + bias_tensor, params, activation_state_tensor, output_tensor, data); +} + +static inline void ApplyTimeWeightsBiasAndActivation( + int batch_size, int memory_size, int num_filters, int num_units, int rank, + const float* const weights_time_ptr, const float* const bias_ptr, + TfLiteFusedActivation activation, float* const state_ptr, + float* const scratch_ptr, float* const output_ptr) { + // Compute matmul(activation_state, weights_time). + for (int b = 0; b < batch_size; ++b) { + // Perform batched vector dot product: + float* scratch_ptr_batch = scratch_ptr + b * num_filters; + const float* vector1_ptr = weights_time_ptr; + const float* vector2_ptr = state_ptr + b * memory_size * num_filters; + for (int i = 0; i < num_filters; ++i) { + *scratch_ptr_batch = 0.f; + for (int j = 0; j < memory_size; ++j) { + *scratch_ptr_batch += *vector1_ptr++ * *vector2_ptr++; + } + scratch_ptr_batch++; + } + } + + // Initialize output with bias if provided. + if (bias_ptr) { + // VectorBatchVectorAssign + for (int i = 0; i < batch_size; ++i) { + float* output_data = output_ptr + i * num_units; + const float* bias_data = bias_ptr; + for (int j = 0; j < num_units; ++j) { + *output_data++ = *bias_data++; + } + } + } else { + float* output_data = output_ptr; + for (int i = 0; i < batch_size * num_units; ++i) { + *output_data++ = 0.0f; + } + } + + // Reduction sum. + for (int b = 0; b < batch_size; ++b) { + float* output_ptr_batch = output_ptr + b * num_units; + float* scratch_ptr_batch = scratch_ptr + b * num_filters; + + // Reduction sum vector + for (int i = 0; i < num_units; ++i) { + for (int j = 0; j < rank; j++) { + output_ptr_batch[i] += *scratch_ptr_batch++; + } + } + } + + // Apply activation. + for (int b = 0; b < batch_size; ++b) { + float* output_ptr_batch = output_ptr + b * num_units; + for (int i = 0; i < num_units; ++i) { + *output_ptr_batch = + tflite::ops::micro::ActivationValFloat(activation, *output_ptr_batch); + ++output_ptr_batch; + } + } +} + +void EvalFloatSvdfReference( + TfLiteContext* context, TfLiteNode* node, const TfLiteEvalTensor* input, + const TfLiteEvalTensor* weights_feature, + const TfLiteEvalTensor* weights_time, const TfLiteEvalTensor* bias, + const TfLiteSVDFParams* params, int scratch_tensor_index, + TfLiteEvalTensor* activation_state, TfLiteEvalTensor* output) { + const int rank = params->rank; + const int batch_size = input->dims->data[0]; + const int input_size = input->dims->data[1]; + const int num_filters = weights_feature->dims->data[0]; + const int num_units = num_filters / rank; + const int memory_size = weights_time->dims->data[1]; + + const float* weights_feature_ptr = + tflite::micro::GetTensorData(weights_feature); + const float* weights_time_ptr = + tflite::micro::GetTensorData(weights_time); + const float* bias_ptr = tflite::micro::GetTensorData(bias); + const float* input_ptr = tflite::micro::GetTensorData(input); + + float* state_ptr = tflite::micro::GetTensorData(activation_state); + + TFLITE_DCHECK(context != nullptr); + TFLITE_DCHECK(context->GetScratchBuffer != nullptr); + + float* scratch_ptr = static_cast( + context->GetScratchBuffer(context, scratch_tensor_index)); + + float* output_ptr = tflite::micro::GetTensorData(output); + + // Left shift the activation_state. + { + float* new_state_start = state_ptr; + const float* old_state_start = state_ptr + 1; + const float* old_state_end = + state_ptr + batch_size * num_filters * memory_size; + while (old_state_start != old_state_end) { + *new_state_start++ = *old_state_start++; + } + } + + // Note: no need to clear the latest activation, matmul is not accumulative. + + // Compute conv1d(inputs, weights_feature). + // The activation_state's rightmost column is used to save current cycle + // activation. This is achieved by starting at state_ptr[memory_size - 1] and + // having the stride equal to memory_size. + + // Perform batched matrix vector multiply operation: + { + const float* matrix = weights_feature_ptr; + const float* vector = input_ptr; + float* result = &state_ptr[memory_size - 1]; + float* result_in_batch = result; + for (int i = 0; i < batch_size; ++i) { + const float* matrix_ptr = matrix; + for (int j = 0; j < num_filters; ++j) { + float dot_prod = 0.0f; + const float* vector_in_batch = vector + i * input_size; + for (int k = 0; k < input_size; ++k) { + dot_prod += *matrix_ptr++ * *vector_in_batch++; + } + *result_in_batch = dot_prod; + result_in_batch += memory_size; + } + } + } + + ApplyTimeWeightsBiasAndActivation( + batch_size, memory_size, num_filters, num_units, rank, weights_time_ptr, + bias_ptr, params->activation, state_ptr, scratch_ptr, output_ptr); +} + +TfLiteStatus PrepareSvdf(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->builtin_data != nullptr); + + const auto* params = static_cast(node->builtin_data); + + MicroContext* micro_context = GetMicroContext(context); + + // Validate Tensor Inputs (dtype depends on quantization): + // [0] = Input, {2, batch_size, input_size} + // [1] = Weights Feature, {2, num_filters, input_size} + // [2] = Weights Time, {2, num_filters, memory_size} + // [3] = Bias (optional), {1, num_units} + // [4] = Activation State (variable), + // {2, batch_size, memory_size * num_filters} + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kSvdfInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* weights_feature = + micro_context->AllocateTempInputTensor(node, kSvdfWeightsFeatureTensor); + TF_LITE_ENSURE(context, weights_feature != nullptr); + TfLiteTensor* weights_time = + micro_context->AllocateTempInputTensor(node, kSvdfWeightsTimeTensor); + TF_LITE_ENSURE(context, weights_time != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kSvdfBiasTensor); + TfLiteTensor* activation_state = micro_context->AllocateTempInputTensor( + node, kSvdfInputActivationStateTensor); + TF_LITE_ENSURE(context, activation_state != nullptr); + + // Define input constants based on input tensor definition above: + const int rank = params->rank; + const int input_size = input->dims->data[1]; + const int batch_size = input->dims->data[0]; + const int num_filters = weights_feature->dims->data[0]; + TF_LITE_ENSURE_EQ(context, num_filters % rank, 0); + const int num_units = num_filters / rank; + const int memory_size = weights_time->dims->data[1]; + + // Validate Input Tensor: + TF_LITE_ENSURE(context, + input->type == kTfLiteFloat32 || input->type == kTfLiteInt8); + TF_LITE_ENSURE_EQ(context, NumDimensions(input), 2); + + // Validate Tensor Output: + // [0] = float/int8_t, {2, batch_size, num_units} + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kSvdfOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE_EQ(context, NumDimensions(output), 2); + TF_LITE_ENSURE_EQ(context, output->dims->data[0], batch_size); + TF_LITE_ENSURE_EQ(context, output->dims->data[1], num_units); + + // Validate Weights Feature Input Tensor: + TF_LITE_ENSURE_EQ(context, NumDimensions(weights_feature), 2); + TF_LITE_ENSURE_EQ(context, weights_feature->dims->data[1], input_size); + + // Validate Weights Time Input Tensor: + TF_LITE_ENSURE_EQ(context, NumDimensions(weights_time), 2); + TF_LITE_ENSURE_EQ(context, weights_time->dims->data[0], num_filters); + TF_LITE_ENSURE_EQ(context, weights_time->dims->data[1], memory_size); + + // Validate Optional Bias Input Tensor: + if (bias != nullptr) { + TF_LITE_ENSURE_EQ(context, bias->dims->data[0], num_units); + } + + // Validate Activation State Input Tensor: + TF_LITE_ENSURE_EQ(context, NumDimensions(activation_state), 2); + TF_LITE_ENSURE_EQ(context, activation_state->dims->data[0], batch_size); + TF_LITE_ENSURE_EQ(context, activation_state->dims->data[1], + memory_size * num_filters); + // Since is_variable is not part of TFLiteEvalTensor, check is_variable here. + TF_LITE_ENSURE_EQ(context, activation_state->is_variable, true); + + TF_LITE_ENSURE_EQ(context, node->inputs->size, 5); + + TFLITE_DCHECK(node->user_data != nullptr); + OpDataSvdf* data = static_cast(node->user_data); + + if (input->type == kTfLiteInt8) { + TF_LITE_ENSURE_EQ(context, weights_feature->type, kTfLiteInt8); + TF_LITE_ENSURE(context, (weights_time->type == kTfLiteInt16) || + (weights_time->type == kTfLiteInt8)); + TF_LITE_ENSURE(context, (activation_state->type == kTfLiteInt16) || + (activation_state->type == kTfLiteInt8)); + if (bias != nullptr) { + TF_LITE_ENSURE_EQ(context, bias->type, kTfLiteInt32); + } + + TF_LITE_ENSURE_TYPES_EQ(context, output->type, kTfLiteInt8); + + const double effective_scale_1 = + static_cast(input->params.scale) * + static_cast(weights_feature->params.scale) / + static_cast(activation_state->params.scale); + const double effective_scale_2 = + static_cast(activation_state->params.scale) * + static_cast(weights_time->params.scale) / + static_cast(output->params.scale); + + // TODO(b/162018098): Use TF_LITE_ENSURE_NEAR when it is ready. + TF_LITE_ENSURE( + context, + std::abs(static_cast(bias->params.scale) - + (static_cast(activation_state->params.scale) * + static_cast(weights_time->params.scale))) < 1e-5); + + QuantizeMultiplier(effective_scale_1, &(data->effective_scale_1_a), + &(data->effective_scale_1_b)); + QuantizeMultiplier(effective_scale_2, &(data->effective_scale_2_a), + &(data->effective_scale_2_b)); + + data->input_zero_point = input->params.zero_point; + data->output_zero_point = output->params.zero_point; + data->activation_state_zero_point = activation_state->params.zero_point; + + TFLITE_DCHECK(context->RequestScratchBufferInArena != nullptr); + + const TfLiteStatus scratch_status = context->RequestScratchBufferInArena( + context, batch_size * num_filters * sizeof(int32_t), + &(data->scratch_tensor_index)); + TF_LITE_ENSURE_OK(context, scratch_status); + + const TfLiteStatus scratch_output_status = + context->RequestScratchBufferInArena( + context, batch_size * num_units * sizeof(int32_t), + &(data->scratch_output_tensor_index)); + TF_LITE_ENSURE_OK(context, scratch_output_status); + } else { + TF_LITE_ENSURE_EQ(context, weights_feature->type, kTfLiteFloat32); + TF_LITE_ENSURE_EQ(context, weights_time->type, kTfLiteFloat32); + TF_LITE_ENSURE_EQ(context, activation_state->type, kTfLiteFloat32); + if (bias != nullptr) { + TF_LITE_ENSURE_EQ(context, bias->type, kTfLiteFloat32); + } + TF_LITE_ENSURE_TYPES_EQ(context, output->type, kTfLiteFloat32); + + TFLITE_DCHECK(context->RequestScratchBufferInArena != nullptr); + const TfLiteStatus scratch_status = context->RequestScratchBufferInArena( + context, batch_size * num_filters * sizeof(float), + &(data->scratch_tensor_index)); + TF_LITE_ENSURE_OK(context, scratch_status); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(weights_feature); + micro_context->DeallocateTempTfLiteTensor(weights_time); + micro_context->DeallocateTempTfLiteTensor(activation_state); + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(bias); + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tanh.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tanh.cpp new file mode 100644 index 0000000..2ae32b6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tanh.cpp @@ -0,0 +1,204 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/tanh.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/tanh.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace activations { +namespace { +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +struct OpData { + int32_t input_zero_point; + int32_t input_range_radius; + int32_t input_multiplier; + int input_left_shift; +}; + +void* TanhInit(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus CalculateArithmeticOpData(TfLiteContext* context, TfLiteNode* node, + OpData* data) { + MicroContext* micro_context = GetMicroContext(context); + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + + TF_LITE_ENSURE_TYPES_EQ(context, input->type, output->type); + + if (input->type == kTfLiteInt8) { + static constexpr int kInputIntegerBits = 4; + const double input_real_multiplier = + static_cast(input->params.scale) * + static_cast(1 << (31 - kInputIntegerBits)); + + const double q = std::frexp(input_real_multiplier, &data->input_left_shift); + data->input_multiplier = static_cast(TfLiteRound(q * (1ll << 31))); + + data->input_range_radius = + CalculateInputRadius(kInputIntegerBits, data->input_left_shift, 31); + } + + if (input->type == kTfLiteInt16) { + static constexpr int kInputIntegerBits = 3; + static constexpr int kOutputFractionalBits = 15; + + // These operators are implemented in fixed-point arithmetic, + // which intrinsically wants symmetric ranges (zero_point==0) + // and power-of-two scales (power-of-two is abbreviated below as POT). + // While more general support would be possible by means of rescaling, + // that would add some overhead and some loss of accuracy and wouldn't + // be used at the moment as current quantized LSTM applications are + // happy with symmetric, power-of-two-scales quantization. So we just + // implement that narrow case only for now. + + TF_LITE_ENSURE_EQ(context, input->params.zero_point, 0); + TF_LITE_ENSURE_EQ(context, output->params.zero_point, 0); + + int input_scale_log2_rounded; + bool param_scale_pot = + CheckedLog2(input->params.scale, &input_scale_log2_rounded); + + data->input_left_shift = + (15 - kInputIntegerBits) + input_scale_log2_rounded; + param_scale_pot &= + (data->input_left_shift == 0 || data->input_left_shift == 1); + + if (param_scale_pot) { + data->input_multiplier = 0; + } else { + // Calculate multiplier to change input scale to 1/(3*4096) + // as required by the table lookup. + // The number 3.0 in the multiplier comes from here, + // because the interval is [-10.7, 10.7] instead of [-8, 8]. + // So, in this scaling +/-2^17 represents +/-10.7. + + double multiplier = + static_cast(input->params.scale) * 4096.0 * 3.0; + data->input_left_shift = 0; + + while (multiplier <= 32767.0 / 2.0 && data->input_left_shift <= 30) { + data->input_left_shift++; + multiplier = multiplier * 2.0; + } + + data->input_multiplier = static_cast(multiplier); + } + + int output_scale_log2_rounded; + TF_LITE_ENSURE( + context, CheckedLog2(output->params.scale, &output_scale_log2_rounded)); + TF_LITE_ENSURE_EQ(context, output_scale_log2_rounded, + -kOutputFractionalBits); + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +TfLiteStatus TanhPrepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + + OpData* data = static_cast(node->user_data); + + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + data->input_zero_point = input->params.zero_point; + TF_LITE_ENSURE_OK(context, CalculateArithmeticOpData(context, node, data)); + + micro_context->DeallocateTempTfLiteTensor(input); + return kTfLiteOk; +} + +} // namespace + +TfLiteStatus TanhEval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + switch (input->type) { + case kTfLiteFloat32: { + reference_ops::Tanh(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + case kTfLiteInt16: { + reference_integer_ops::Tanh( + data.input_multiplier, data.input_left_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + case kTfLiteInt8: { + reference_integer_ops::Tanh( + data.input_zero_point, data.input_range_radius, data.input_multiplier, + data.input_left_shift, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + return kTfLiteOk; + } break; + default: + MicroPrintf("Input %s, output %s not supported.", + TfLiteTypeGetName(input->type), + TfLiteTypeGetName(output->type), context); + return kTfLiteError; + } +} + +} // namespace activations + +TfLiteRegistration Register_TANH() { + return tflite::micro::RegisterOp( + activations::TanhInit, activations::TanhPrepare, activations::TanhEval); +} +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/transpose.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/transpose.cpp new file mode 100644 index 0000000..c0bd6e4 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/transpose.cpp @@ -0,0 +1,122 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kPermTensor = 1; +constexpr int kOutputTensor = 0; + +struct TransposeContext { + TransposeContext(TfLiteContext* context, TfLiteNode* node) { + micro_context = GetMicroContext(context); + input = micro_context->AllocateTempInputTensor(node, kInputTensor); + perm = micro_context->AllocateTempInputTensor(node, kPermTensor); + output = micro_context->AllocateTempOutputTensor(node, kOutputTensor); + } + ~TransposeContext() { + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(perm); + micro_context->DeallocateTempTfLiteTensor(output); + } + MicroContext* micro_context; + TfLiteTensor* input; + TfLiteTensor* perm; + TfLiteTensor* output; +}; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, NumInputs(node), 2); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + + TransposeContext op_context(context, node); + + // Ensure validity of input tensor. + TF_LITE_ENSURE_MSG(context, NumDimensions(op_context.input) <= 5, + "Transpose op only supports 1D-5D input arrays."); + TF_LITE_ENSURE_TYPES_EQ(context, op_context.input->type, + op_context.output->type); + + int dims = NumDimensions(op_context.input); + const int32_t* perm_data = GetTensorData(op_context.perm); + + // Ensure validity of the permutations tensor as a 1D tensor. + TF_LITE_ENSURE_EQ(context, NumDimensions(op_context.perm), 1); + TF_LITE_ENSURE_EQ(context, op_context.perm->dims->data[0], dims); + for (int idx = 0; idx < dims; ++idx) { + TF_LITE_ENSURE_MSG(context, (perm_data[idx] >= 0 && perm_data[idx] < dims), + "Transpose op permutations array is out of bounds."); + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* perm_tensor = + tflite::micro::GetEvalInput(context, node, kPermTensor); + const int32_t* perm_data = perm_tensor->data.i32; + const int size = perm_tensor->dims->data[0]; + TransposeParams params; + params.perm_count = size; + for (int i = 0; i < size; ++i) { + params.perm[i] = perm_data[i]; + } + + // Transpose kernel only does rearranging values not numeric evaluations + // on each cell. It's safe to implement per size of scalar type and this + // trick keeps the total code size in a reasonable range. + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + switch (input->type) { + case kTfLiteFloat32: + reference_ops::Transpose(params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + case kTfLiteInt8: + reference_ops::Transpose(params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output)); + break; + default: + MicroPrintf( + "Type %s is currently not supported by Transpose. " + "Only float32 and int8 is supported", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_TRANSPOSE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/transpose_conv.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/transpose_conv.cpp new file mode 100644 index 0000000..411d4e0 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/transpose_conv.cpp @@ -0,0 +1,708 @@ +// Patched by Edge Impulse to include reference and hardware-accelerated kernels +#include "../../../../classifier/ei_classifier_config.h" +#if 0 == 1 +/* noop */ +#elif EI_CLASSIFIER_TFLITE_ENABLE_SILABS_MVP == 1 + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +using int8 = int8_t; +using int16 = int16_t; +using int32 = int32_t; +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/transpose_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" + +#include "sl_mvp_ml_transpose_conv2d.h" + +namespace tflite { +namespace sl { +namespace transpose_conv2d { + +constexpr int kFilterTensor = 1; +constexpr int kInputTensor = 2; +constexpr int kBiasTensor = 3; +constexpr int kOutputTensor = 0; + +// TransposeConv is quantized along dimension 0 of filter tensor. +// https://www.tensorflow.org/lite/performance/quantization_spec +constexpr int kConvQuantizedDimension = 0; + +enum op_support { kMvp, kTFLMrefF32, kTFLMrefI8 }; + +struct OpData { + op_support supported; + int scratch_buffer_index; + sli_mvp_ml_transpose_conv2d_s8_params_t op_params; + + // Per channel output multiplier and shift. + int32_t *per_channel_output_multiplier; + int32_t *per_channel_output_shift; +}; + +inline float16_t normalize_fp16(float f) +{ + return (float16_t)std::min(std::max(f, SLI_MVP_FP16_MIN), SLI_MVP_FP16_MAX); +} + +inline PaddingType RuntimePaddingType(TfLitePadding padding) +{ + switch (padding) { + case TfLitePadding::kTfLitePaddingSame: + return PaddingType::kSame; + case TfLitePadding::kTfLitePaddingValid: + return PaddingType::kValid; + case TfLitePadding::kTfLitePaddingUnknown: + default: + return PaddingType::kNone; + } +} + +TfLiteStatus PopulateConvolutionQuantizationParams( + TfLiteContext* context, + const TfLiteTensor* input, + const TfLiteTensor* filter, + TfLiteTensor* output, + const TfLiteFusedActivation& activation, + int32_t* output_activation_min, int32_t* output_activation_max, + float16_t* per_channel_scalers, int num_channels, float accumulator_multipler) +{ + auto affine_quantization = + reinterpret_cast(filter->quantization.params); + + // Populate multiplier and shift using affine quantization. + const float input_scale = input->params.scale; + const float output_scale = output->params.scale; + const float* filter_scales = affine_quantization->scale->data; + + for (int i = 0; i < num_channels; ++i) { + // If per-tensor quantization parameter is specified, broadcast it along the + // quantization dimension. + const float filter_scale = filter_scales[i]; + const float effective_output_scale = (input_scale * filter_scale) / output_scale; + const float acc_output_scale = effective_output_scale * accumulator_multipler; + per_channel_scalers[i] = normalize_fp16(acc_output_scale); + } + + TF_LITE_ENSURE_STATUS(CalculateActivationRangeQuantized( + context, activation, output, output_activation_min, + output_activation_max)); + + return kTfLiteOk; +} + +void *Init(TfLiteContext* context, const char* buffer, size_t length) +{ + (void)buffer; + (void)length; + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) +{ + int scratch_buffer_size = 0; + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto params = static_cast(node->builtin_data); + + TfLiteTensor* output = GetOutput(context, node, kOutputTensor); + const TfLiteTensor* bias = GetOptionalInputTensor(context, node, kBiasTensor); + const TfLiteTensor* input = GetInput(context, node, kInputTensor); + const TfLiteTensor* filter = GetInput(context, node, kFilterTensor); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, output != nullptr); + TF_LITE_ENSURE(context, filter != nullptr); + + data->op_params.batches = input->dims->data[0]; + data->op_params.in_channels = input->dims->data[3]; + data->op_params.input_height = input->dims->data[1]; + data->op_params.input_width = input->dims->data[2]; + data->op_params.out_channels = filter->dims->data[kConvQuantizedDimension]; + data->op_params.output_height = output->dims->data[1]; + data->op_params.output_width = output->dims->data[2]; + data->op_params.filter_height = filter->dims->data[1]; + data->op_params.filter_width = filter->dims->data[2]; + data->op_params.input_offset = -input->params.zero_point; + data->op_params.output_offset = output->params.zero_point; + data->op_params.stride_height = params->stride_height; + data->op_params.stride_width = params->stride_width; + data->op_params.padding = params->padding == kTfLitePaddingSame; + + int dummy_height, dummy_width; + const auto padding = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, + 1, 1, //dilation_rate_height and dilation_rate_width + data->op_params.input_height, data->op_params.input_width, + data->op_params.filter_height, data->op_params.filter_width, + params->padding, + &dummy_height, &dummy_width); + + data->op_params.pad_height = padding.height; + data->op_params.pad_width = padding.width; + + const int num_channels = data->op_params.out_channels; + + if (input->type == kTfLiteInt8) { + if (sli_mvp_ml_transpose_conv2d_s8_is_supported(&data->op_params)) { + data->supported = kMvp; + scratch_buffer_size = GetTensorShape(output).FlatSize() * sizeof(float16_t); + + float16_t *bias_data = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(float16_t))); + if(bias != nullptr) { + data->op_params.bias = bias_data; + int32_t i32_bias; + for(int i = 0; i < num_channels; i++) { + i32_bias = bias->data.i32[i]; + bias_data[i] = float16_t(i32_bias * SLI_MVP_ACCUMULATOR_SCALER); + } + } else { + data->op_params.bias = nullptr; + } + + float16_t *scaler_data = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(float16_t))); + data->op_params.output_scaler = scaler_data; + TF_LITE_ENSURE_STATUS(PopulateConvolutionQuantizationParams( + context, input, filter, output, kTfLiteActNone, + reinterpret_cast(&data->op_params.output_activation_min), + reinterpret_cast(&data->op_params.output_activation_max), + scaler_data, num_channels, SLI_MVP_ACCUMULATOR_MULTIPLIER)); + + } else { + data->supported = kTFLMrefI8; + scratch_buffer_size = GetTensorShape(output).FlatSize() * sizeof(int32_t); + data->per_channel_output_multiplier = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + int32_t dummy_output_multiplier; + int dummy_output_shift; + TF_LITE_ENSURE_STATUS(tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, kTfLiteActNone, + &dummy_output_multiplier, &dummy_output_shift, + reinterpret_cast(&data->op_params.output_activation_min), + reinterpret_cast(&data->op_params.output_activation_max), + data->per_channel_output_multiplier, + reinterpret_cast(data->per_channel_output_shift), + num_channels)); + } + + } else if (input->type == kTfLiteFloat32) { + data->supported = kTFLMrefF32; + } else { + TF_LITE_KERNEL_LOG(context, "Type %s not currently supported.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + + if(scratch_buffer_size > 0) { + TF_LITE_ENSURE_STATUS( + context->RequestScratchBufferInArena( + context, scratch_buffer_size, &data->scratch_buffer_index)); + } else { + data->scratch_buffer_index = -1; + } + + return kTfLiteOk; +} + +TfLiteStatus eval_mvp_int8(TfLiteContext* context, + OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + TfLiteEvalTensor* output) +{ + float16_t *scratch; + if (data->scratch_buffer_index > -1) { + scratch = reinterpret_cast(context->GetScratchBuffer(context, data->scratch_buffer_index)); + } else { + return kTfLiteError; + } + + data->op_params.scratch_buffer = scratch; + data->op_params.input = tflite::micro::GetTensorData(input); + data->op_params.output = tflite::micro::GetTensorData(output); + data->op_params.filter = tflite::micro::GetTensorData(filter); + + TF_LITE_ENSURE_EQ(context, SL_STATUS_OK, sli_mvp_ml_transpose_conv2d_s8(&data->op_params)); + + return kTfLiteOk; +} + +TfLiteStatus eval_tflm_int8(TfLiteContext* context, + OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + int32_t *scratch; + ConvParams op_params; + + if (data->scratch_buffer_index > -1) { + scratch = reinterpret_cast(context->GetScratchBuffer(context, data->scratch_buffer_index)); + } else { + return kTfLiteError; + } + + op_params.input_offset = data->op_params.input_offset; + op_params.output_offset = data->op_params.output_offset; + op_params.stride_height = data->op_params.stride_height; + op_params.stride_width = data->op_params.stride_width; + op_params.padding_values.height = data->op_params.pad_height; + op_params.padding_values.width = data->op_params.pad_width; + + reference_integer_ops::TransposeConv(op_params, + data->per_channel_output_multiplier, + data->per_channel_output_shift, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(const_cast(bias)), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + RuntimeShape(), + nullptr, + scratch); + return kTfLiteOk; +} + +TfLiteStatus eval_float(TfLiteConvParams* params, + const OpData* data, + const TfLiteEvalTensor* input, + const TfLiteEvalTensor* filter, + const TfLiteEvalTensor* bias, + TfLiteEvalTensor* output) +{ + ConvParams op_params; + + op_params.padding_type = RuntimePaddingType(params->padding); + op_params.padding_values.width = data->op_params.pad_width; + op_params.padding_values.height = data->op_params.pad_height; + op_params.stride_width = data->op_params.stride_width; + op_params.stride_height = data->op_params.stride_height; + + reference_ops::TransposeConv(op_params, + tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetTensorData(const_cast(bias)), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + RuntimeShape(), + nullptr); + return kTfLiteOk; +} + +TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node) +{ + TfLiteStatus status = kTfLiteError; + + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + auto* params = reinterpret_cast(node->builtin_data); + OpData* data = static_cast(node->user_data); + + const auto input = tflite::micro::GetEvalInput(context, node, kInputTensor); + const auto filter = tflite::micro::GetEvalInput(context, node, kFilterTensor); + const auto bias = NumInputs(node) == 4 + ? tflite::micro::GetEvalInput(context, node, kBiasTensor) + : nullptr; + auto output = tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + if (data->supported == kMvp) { + status = eval_mvp_int8(context, data, input, filter, output); + + } else if (data->supported == kTFLMrefI8) { + status = eval_tflm_int8(context, data, input, filter, bias, output); + + } else if (data->supported == kTFLMrefF32) { + status = eval_float(params, data, input, filter, bias, output); + } + + return status; +} + +} // namespace transpose_conv2d +} // namespace sl + +TfLiteRegistration Register_TRANSPOSE_CONV() { + return {/*init=*/sl::transpose_conv2d::Init, + /*free=*/nullptr, + /*prepare=*/sl::transpose_conv2d::Prepare, + /*invoke=*/sl::transpose_conv2d::Invoke, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; +} + +} // namespace tflite + +#else +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/transpose_conv.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/reference/integer_ops/transpose_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/padding.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +// For the TfLite transpose_conv implementation, input tensor 0 corresponds to +// the OutputShapeTensor. However, since TFLM does not support dynamic tensors, +// the TFLM implementation ignores input tensor 0 and the only inputs we care +// about are kFilterTensor, kInputTensor and kBiasTensor. +constexpr int kFilterTensor = 1; +constexpr int kInputTensor = 2; +constexpr int kBiasTensor = 3; +constexpr int kOutputTensor = 0; + +// Conv is quantized along dimension 0: +// https://www.tensorflow.org/lite/performance/quantization_spec +constexpr int kConvQuantizedDimension = 0; + +struct OpData { + ConvParams params; + + // A scratch buffer is required for quantized implementations. + int scratch_buffer_index; + + // TODO(b/192090531): Remove this once all 8x16 transpose conv models use + // 64-bit biases. + int bias_converted_buffer_index; + + // Multiplier and shift arrays are required for the int8 implementation. + int32_t* per_channel_output_multiplier; + int32_t* per_channel_output_shift; +}; + +inline PaddingType RuntimePaddingType(TfLitePadding padding) { + switch (padding) { + case TfLitePadding::kTfLitePaddingSame: + return PaddingType::kSame; + case TfLitePadding::kTfLitePaddingValid: + return PaddingType::kValid; + case TfLitePadding::kTfLitePaddingUnknown: + default: + return PaddingType::kNone; + } +} + +TfLiteStatus CalculateOpData(TfLiteContext* context, TfLiteNode* node, + const TfLiteTransposeConvParams* params, int width, + int height, int filter_width, int filter_height, + const TfLiteType data_type, OpData* data) { + bool has_bias = node->inputs->size == 4; + // Check number of inputs/outputs + TF_LITE_ENSURE(context, has_bias || node->inputs->size == 3); + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + + // Matching GetWindowedOutputSize in TensorFlow. + auto padding = params->padding; + int unused_output_width; + int unused_output_height; + TfLitePaddingValues padding_values = ComputePaddingHeightWidth( + params->stride_height, params->stride_width, 1, + 1, // Dilation height and width are always 1 for transpose_conv. + height, width, filter_height, filter_width, padding, + &unused_output_height, &unused_output_width); + + data->params.padding_type = RuntimePaddingType(padding); + data->params.padding_values.width = padding_values.width; + data->params.padding_values.height = padding_values.height; + + // Note that quantized inference requires that all tensors have their + // parameters set. This is usually done during quantized training. + if (data_type != kTfLiteFloat32) { + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kFilterTensor); + TF_LITE_ENSURE(context, filter != nullptr); + TfLiteTensor* bias = + micro_context->AllocateTempInputTensor(node, kBiasTensor); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + int output_channels = filter->dims->data[kConvQuantizedDimension]; + + TF_LITE_ENSURE_STATUS(tflite::PopulateConvolutionQuantizationParams( + context, input, filter, bias, output, kTfLiteActNone, + &data->params.output_multiplier, &data->params.output_shift, + &data->params.quantized_activation_min, + &data->params.quantized_activation_max, + data->per_channel_output_multiplier, data->per_channel_output_shift, + output_channels)); + + // TODO(b/192090531): Remove this once all 8x16 transpose conv models use + // 64-bit biases. + if (input->type == kTfLiteInt16) { + TFLITE_DCHECK(filter->type == kTfLiteInt8); + TFLITE_DCHECK(output->type == kTfLiteInt16); + if (bias->type == kTfLiteInt16) { + TFLITE_DCHECK( + context->RequestScratchBufferInArena( + context, GetTensorShape(bias).FlatSize() * sizeof(std::int64_t), + &(data->bias_converted_buffer_index)) == kTfLiteOk); + } + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + micro_context->DeallocateTempTfLiteTensor(output); + if (bias != nullptr) { + micro_context->DeallocateTempTfLiteTensor(bias); + } + } + return kTfLiteOk; +} + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + TFLITE_DCHECK(node->builtin_data != nullptr); + + OpData* data = static_cast(node->user_data); + const auto params = + static_cast(node->builtin_data); + + MicroContext* micro_context = GetMicroContext(context); + + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* filter = + micro_context->AllocateTempInputTensor(node, kFilterTensor); + TF_LITE_ENSURE(context, filter != nullptr); + + // Get height and width of the output. + const int width = SizeOfDimension(output, 2); + const int height = SizeOfDimension(output, 1); + const int filter_width = SizeOfDimension(filter, 2); + const int filter_height = SizeOfDimension(filter, 1); + + // Dynamically allocate per-channel quantization parameters. + const int num_channels = filter->dims->data[kConvQuantizedDimension]; + data->per_channel_output_multiplier = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + data->per_channel_output_shift = + static_cast(context->AllocatePersistentBuffer( + context, num_channels * sizeof(int32_t))); + + // Quantized kernels use an int32 scratch buffer. + if (input->type == kTfLiteInt8) { + TFLITE_DCHECK(context->RequestScratchBufferInArena != nullptr); + TFLITE_DCHECK(context->RequestScratchBufferInArena( + context, + GetTensorShape(output).FlatSize() * sizeof(int32_t), + &(data->scratch_buffer_index)) == kTfLiteOk); + } + + // Quantized 16x8 kernels use an int64 scratch buffer. + if (input->type == kTfLiteInt16) { + TFLITE_DCHECK(context->RequestScratchBufferInArena != nullptr); + TFLITE_DCHECK(context->RequestScratchBufferInArena( + context, + GetTensorShape(output).FlatSize() * sizeof(std::int64_t), + &(data->scratch_buffer_index)) == kTfLiteOk); + } + + // All per-channel quantized tensors need valid zero point and scale arrays. + if (input->type == kTfLiteInt8 || input->type == kTfLiteInt16) { + TF_LITE_ENSURE_EQ(context, filter->quantization.type, + kTfLiteAffineQuantization); + + const auto* affine_quantization = + static_cast(filter->quantization.params); + TF_LITE_ENSURE(context, affine_quantization); + TF_LITE_ENSURE(context, affine_quantization->scale); + TF_LITE_ENSURE(context, affine_quantization->zero_point); + + TF_LITE_ENSURE(context, + affine_quantization->scale->size == 1 || + affine_quantization->scale->size == + filter->dims->data[kConvQuantizedDimension]); + TF_LITE_ENSURE_EQ(context, affine_quantization->scale->size, + affine_quantization->zero_point->size); + } + + TF_LITE_ENSURE_STATUS(CalculateOpData(context, node, params, width, height, + filter_width, filter_height, + input->type, data)); + + // Offsets (zero points) + data->params.input_offset = -input->params.zero_point; + data->params.weights_offset = -filter->params.zero_point; + data->params.output_offset = output->params.zero_point; + + // Stride + data->params.stride_width = params->stride_width; + data->params.stride_height = params->stride_height; + + micro_context->DeallocateTempTfLiteTensor(output); + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(filter); + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + const TfLiteEvalTensor* filter = + tflite::micro::GetEvalInput(context, node, kFilterTensor); + const TfLiteEvalTensor* bias = + (NumInputs(node) == 4) + ? tflite::micro::GetEvalInput(context, node, kBiasTensor) + : nullptr; + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + + TFLITE_DCHECK(node->user_data != nullptr); + const OpData& data = *(static_cast(node->user_data)); + + TF_LITE_ENSURE_EQ(context, input->type, output->type); + TF_LITE_ENSURE_MSG( + context, + input->type == filter->type || + (input->type == kTfLiteInt16 && filter->type == kTfLiteInt8), + "Hybrid models are not supported on TFLite Micro."); + + switch (input->type) { // Already know in/out types are same. + case kTfLiteFloat32: { + const auto& params = + *(reinterpret_cast(node->builtin_data)); + ConvParams op_params = data.params; + CalculateActivationRange(params.activation, + &op_params.float_activation_min, + &op_params.float_activation_max); + + reference_ops::TransposeConv( + op_params, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr); + break; + } + case kTfLiteInt8: { + int32_t* scratch_buffer = static_cast( + context->GetScratchBuffer(context, data.scratch_buffer_index)); + reference_integer_ops::TransposeConv( + data.params, data.per_channel_output_multiplier, + data.per_channel_output_shift, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr, scratch_buffer); + break; + } + case kTfLiteInt16: { + std::int64_t* scratch_buffer = static_cast( + context->GetScratchBuffer(context, data.scratch_buffer_index)); + // TODO(b/192090531): Remove this once all 8x16 transpose conv models use + // 64-bit biases. + if (bias != nullptr && bias->type == kTfLiteInt16) { + std::int64_t* bias_converted_buffer = + static_cast(context->GetScratchBuffer( + context, data.bias_converted_buffer_index)); + for (int i = 0; i < tflite::micro::GetTensorShape(bias).FlatSize(); + i++) { + bias_converted_buffer[i] = bias->data.i16[i]; + } + reference_integer_ops::TransposeConv( + data.params, data.per_channel_output_multiplier, + data.per_channel_output_shift, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), bias_converted_buffer, + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr, scratch_buffer); + } else { + reference_integer_ops::TransposeConv( + data.params, data.per_channel_output_multiplier, + data.per_channel_output_shift, tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorData(input), + tflite::micro::GetTensorShape(filter), + tflite::micro::GetTensorData(filter), + tflite::micro::GetTensorShape(bias), + tflite::micro::GetOptionalTensorData(bias), + tflite::micro::GetTensorShape(output), + tflite::micro::GetTensorData(output), + tflite::micro::GetTensorShape(nullptr), nullptr, scratch_buffer); + } + break; + } + default: + MicroPrintf("Type %s (%d) not supported.", TfLiteTypeGetName(input->type), + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_TRANSPOSE_CONV() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tree_ensemble_classifier.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tree_ensemble_classifier.cpp new file mode 100644 index 0000000..c0f4317 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tree_ensemble_classifier.cpp @@ -0,0 +1,194 @@ +/* Copyright 2023 Edge Impulse Inc. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#define FLATBUFFERS_LOCALE_INDEPENDENT 0 +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include + +#define FEATURE_TYPE float + +namespace tflite { +namespace { + +struct OpDataTree { + uint32_t num_leaf_nodes; + uint32_t num_internal_nodes; + uint32_t num_trees; + const uint16_t* nodes_modes; + const uint16_t* nodes_featureids; + const float* nodes_values; + const uint16_t* nodes_truenodeids; + const uint16_t* nodes_falsenodeids; + const float* nodes_weights; + const uint8_t* nodes_classids; + const uint16_t* tree_root_ids; + const uint8_t* buffer_t; + size_t buffer_length; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + const uint8_t* buffer_t = reinterpret_cast(buffer); + const flexbuffers::Map& m = flexbuffers::GetRoot(buffer_t, length).AsMap(); + + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + OpDataTree* data = static_cast(context->AllocatePersistentBuffer(context, sizeof(OpDataTree))); + + data->buffer_t = buffer_t; + data->buffer_length = length; + + data->num_leaf_nodes = m["num_leaf_nodes"].AsUInt32(); + data->num_internal_nodes = m["num_internal_nodes"].AsUInt32(); + data->num_trees = m["num_trees"].AsUInt32(); + + data->nodes_modes = (uint16_t*)(m["nodes_modes"].AsBlob().data()); + data->nodes_featureids = (uint16_t*)(m["nodes_featureids"].AsBlob().data()); + data->nodes_values = (float*)(m["nodes_values"].AsBlob().data()); + data->nodes_truenodeids = (uint16_t*)(m["nodes_truenodeids"].AsBlob().data()); + data->nodes_falsenodeids = (uint16_t*)(m["nodes_falsenodeids"].AsBlob().data()); + data->nodes_weights = (float*)(m["nodes_weights"].AsBlob().data()); + data->nodes_classids = (uint8_t*)(m["nodes_classids"].AsBlob().data()); + data->tree_root_ids = (uint16_t*)(m["tree_root_ids"].AsBlob().data()); + + return data; +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + + MicroContext* micro_context = GetMicroContext(context); + const OpDataTree* data = static_cast(node->user_data); + const flexbuffers::Map& m = flexbuffers::GetRoot(data->buffer_t, data->buffer_length).AsMap(); + + // The OOB checks below are very important to prevent vulnerabilities where an adversary sends + // us a malicious TFLite model, similar to: https://nvd.nist.gov/vuln/detail/CVE-2022-23560 + + int num_nodes = data->num_leaf_nodes + data->num_internal_nodes; + + // Check that the tree root ids are valid. + for (uint32_t i = 0; i < data->num_trees; i++) { + TF_LITE_ENSURE_EQ(context, data->tree_root_ids[i] < num_nodes, true); + TF_LITE_ENSURE_EQ(context, data->tree_root_ids[i] >= 0, true); + } + + // Check that all node indices are valid + for (uint32_t i = 0; i < data->num_internal_nodes; i++) { + TF_LITE_ENSURE_EQ(context, data->nodes_truenodeids[i] < num_nodes, true); + TF_LITE_ENSURE_EQ(context, data->nodes_truenodeids[i] >= 0, true); + TF_LITE_ENSURE_EQ(context, data->nodes_falsenodeids[i] < num_nodes, true); + TF_LITE_ENSURE_EQ(context, data->nodes_falsenodeids[i] >= 0, true); + } + + // Check all node arrays have the same length + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_featureids"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_values"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_truenodeids"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_internal_nodes, m["nodes_falsenodeids"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_leaf_nodes, m["nodes_weights"].AsBlob().size()); + TF_LITE_ENSURE_EQ(context, data->num_leaf_nodes, m["nodes_classids"].AsBlob().size()); + + // Check data types are supported. Currently we only support one combination. + TF_LITE_ENSURE_EQ(context, strncmp(m["tree_index_type"].AsString().c_str(), "uint16", 6), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["node_value_type"].AsString().c_str(), "float32", 7), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["class_index_type"].AsString().c_str(), "uint8", 5), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["class_weight_type"].AsString().c_str(), "float32", 7), 0); + TF_LITE_ENSURE_EQ(context, strncmp(m["equality_operator"].AsString().c_str(), "leq", 3), 0); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = micro_context->AllocateTempInputTensor(node, 0); + TF_LITE_ENSURE(context, input != nullptr); + TF_LITE_ENSURE(context, NumDimensions(input) == 2); + TfLiteTensor* output = micro_context->AllocateTempOutputTensor(node, 0); + TF_LITE_ENSURE(context, output != nullptr); + + int input_width = SizeOfDimension(input, 1); + int output_width = SizeOfDimension(output, 1); + + // Check that all indices into the input/output tensor are valid + for (uint32_t i = 0; i < data->num_internal_nodes; i++) { + TF_LITE_ENSURE(context, data->nodes_featureids[i] < input_width); + TF_LITE_ENSURE(context, data->nodes_featureids[i] >= 0); + if (!m["nodes_modes"].AsBlob().IsTheEmptyBlob()) { + if (data->nodes_modes[i] == 0) { + TF_LITE_ENSURE(context, data->nodes_classids[i] < output_width); + TF_LITE_ENSURE(context, data->nodes_classids[i] >= 0); + } + } + } + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + + const OpDataTree* data = static_cast(node->user_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, 0); + const float *in_data = tflite::micro::GetTensorData(input); + + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, 0); + float *out_data = tflite::micro::GetTensorData(output); + + const tflite::RuntimeShape output_shape = tflite::micro::GetTensorShape(output); + memset(out_data, 0, output_shape.FlatSize() * sizeof(float)); + + for (uint32_t i = 0; i < data->num_trees; i++) { + uint16_t ix = data->tree_root_ids[i]; + + while (ix < data->num_internal_nodes) { + float node_val = 0; + memcpy(&node_val, (data->nodes_values + ix), sizeof(float)); + + if (in_data[data->nodes_featureids[ix]] <= node_val) { + ix = data->nodes_truenodeids[ix]; + } else { + ix = data->nodes_falsenodeids[ix]; + } + } + ix -= data->num_internal_nodes; + + float weight = 0; + memcpy(&weight, (data->nodes_weights + ix), sizeof(float)); + out_data[data->nodes_classids[ix]] += weight; + } + + return kTfLiteOk; +} + + +} // namespace + +TfLiteRegistration* Register_TreeEnsembleClassifier() { + static TfLiteRegistration r = {Init, + nullptr, + Prepare, + Eval, + /*profiling_string=*/nullptr, + /*builtin_code=*/0, + /*custom_name=*/nullptr, + /*version=*/0}; + return &r; +} + +const char* GetString_TreeEnsembleClassifier() { return "TreeEnsembleClassifier"; } + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tree_ensemble_classifier.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tree_ensemble_classifier.h new file mode 100644 index 0000000..335c312 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/tree_ensemble_classifier.h @@ -0,0 +1,29 @@ +/* Copyright 2023 Edge Impulse Inc. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_KERNELS_TREE_ENSEMBLE_CLASSIFIER_H_ +#define TENSORFLOW_LITE_MICRO_KERNELS_TREE_ENSEMBLE_CLASSIFIER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +TfLiteRegistration* Register_TreeEnsembleClassifier(); + +const char* GetString_TreeEnsembleClassifier(); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_KERNELS_TREE_ENSEMBLE_CLASSIFIER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/unidirectional_sequence_lstm.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/unidirectional_sequence_lstm.cpp new file mode 100644 index 0000000..7ff9a2f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/unidirectional_sequence_lstm.cpp @@ -0,0 +1,589 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// Integer version of unidirectional sequence lstm. Only the standard LSTM +// (defined in the keras LSTM layer, e.g., no peephole etc.) is supported here. +// Currently used by the 16 bits activation case only + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/quantization_util.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_eval.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/lstm_shared.h" + +namespace tflite { + +namespace { +/*Helper Functions*/ + +// Interface to access all the TempTfLiteTensors of the LSTM kernel during the +// preparation phase. Can only be constructed through the constructor to avoid +// memory leakage. All TempTfLiteTensors will be deallocated through the +// destructor. +class LstmTensors { + public: + LstmTensors(const LstmTensors& other) = delete; + LstmTensors& operator=(const LstmTensors& other) = delete; + + LstmTensors(TfLiteContext* context, TfLiteNode* node) { + micro_context_ = GetMicroContext(context); + // 24 internal tensors. see lstm_shared.h for tensor names + for (size_t i = 0; i < 24; i++) { + internal_tensors_[i] = micro_context_->AllocateTempInputTensor(node, i); + } + output_tensor_ = + micro_context_->AllocateTempOutputTensor(node, kLstmOutputTensor); + } + + ~LstmTensors() { + for (size_t i = 0; i < 24; i++) { + if (internal_tensors_[i] != nullptr) { + micro_context_->DeallocateTempTfLiteTensor(internal_tensors_[i]); + } + } + micro_context_->DeallocateTempTfLiteTensor(output_tensor_); + } + + // Verify the LSTM internal tensor properties (e.g., type checks) + // Input/output/states/fc weights tensors are required for kernel evaulation. + // The state tensors should be variables. Variants of the standard LSTM + // are not supported here, therefore their corresponding tensors should be + // invalid + TfLiteStatus ValidateTensorStatus(TfLiteContext* context) const { + // Verify certain tensor properties + // input tensor + TF_LITE_ENSURE(context, internal_tensors_[kLstmInputTensor] != nullptr); + // hidden state + TF_LITE_ENSURE(context, + internal_tensors_[kLstmOutputStateTensor] != nullptr); + TF_LITE_ENSURE(context, + internal_tensors_[kLstmOutputStateTensor]->is_variable); + // hidden state becomes input so they must have the same type + TF_LITE_ENSURE_EQ(context, internal_tensors_[kLstmOutputStateTensor]->type, + internal_tensors_[kLstmInputTensor]->type); + // cell state + TF_LITE_ENSURE(context, internal_tensors_[kLstmCellStateTensor] != nullptr); + TF_LITE_ENSURE(context, + internal_tensors_[kLstmCellStateTensor]->is_variable); + // output + TF_LITE_ENSURE(context, output_tensor_ != nullptr); + // output type is the same as the input type (activations) + TF_LITE_ENSURE_EQ(context, output_tensor_->type, + internal_tensors_[kLstmInputTensor]->type); + + // weight tensors (1-9, see lstm_shared for index definition) + const auto weight_type = + internal_tensors_[kLstmInputToForgetWeightsTensor]->type; + for (size_t i = 1; i < 9; i++) { + TF_LITE_ENSURE(context, internal_tensors_[i] != nullptr); + TF_LITE_ENSURE_EQ(context, internal_tensors_[i]->type, weight_type); + } + + // bias tensors (12-15, see lstm_shared for index definition) + const auto bias_type = internal_tensors_[kLstmForgetGateBiasTensor]->type; + for (size_t i = 12; i < 16; i++) { + TF_LITE_ENSURE(context, internal_tensors_[i] != nullptr); + TF_LITE_ENSURE_EQ(context, internal_tensors_[i]->type, bias_type); + } + // Tensors from LSTM variants are invalid + // No peephole + for (size_t i = 9; i < 12; i++) { + TF_LITE_ENSURE(context, internal_tensors_[i] == nullptr); + } + // No projection + for (size_t i = 16; i < 18; i++) { + TF_LITE_ENSURE(context, internal_tensors_[i] == nullptr); + } + // No internal layer norm + for (size_t i = 20; i < 24; i++) { + TF_LITE_ENSURE(context, internal_tensors_[i] == nullptr); + } + return kTfLiteOk; + } + + // Internal tensors. see lstm_shared.h for tensor names + const TfLiteTensor* GetInternalTensor(const int tensor_index) const { + return internal_tensors_[tensor_index]; + } + + const TfLiteTensor* HiddenStateTensor() const { + return internal_tensors_[kLstmOutputStateTensor]; + } + const TfLiteTensor* CellStateTensor() const { + return internal_tensors_[kLstmCellStateTensor]; + } + const TfLiteTensor* OutputTensor() const { return output_tensor_; } + + private: + // see lstm_shared.h for tensor names + MicroContext* micro_context_; + TfLiteTensor* internal_tensors_[24]; + TfLiteTensor* output_tensor_; +}; + +// Deduce the size information (Batch (B), Time Steps (T), Input dimension (I), +// State dimension (S)) that defines the LSTM using the input and hidden state +// tensor +LstmSizeInfo CreateLstmSizeInfo( + const bool time_major, const TfLiteIntArray* input_tensor_shape, + const TfLiteIntArray* hidden_state_tensor_shape) { + LstmSizeInfo size_info; + size_info.time_major = time_major; + size_info.batch_size = + time_major ? input_tensor_shape->data[1] : input_tensor_shape->data[0]; + size_info.time_steps = + time_major ? input_tensor_shape->data[0] : input_tensor_shape->data[1]; + size_info.input_dimension = input_tensor_shape->data[2]; + size_info.state_dimension = hidden_state_tensor_shape->data[1]; + return size_info; +} + +TfLiteStatus ValidateWeightTensorSize(TfLiteContext* context, + const TfLiteTensor* tensor, int dim1_size, + int dim2_size) { + TF_LITE_ENSURE_EQ(context, tensor->dims->size, 2); + TF_LITE_ENSURE_EQ(context, tensor->dims->data[0], dim1_size); + TF_LITE_ENSURE_EQ(context, tensor->dims->data[1], dim2_size); + return kTfLiteOk; +} + +TfLiteStatus ValidateBiasTensorSize(TfLiteContext* context, + const TfLiteTensor* tensor, int size) { + TF_LITE_ENSURE_EQ(context, tensor->dims->size, 1); + TF_LITE_ENSURE_EQ(context, tensor->dims->data[0], size); + return kTfLiteOk; +} + +// Go through every tensors and make sure their shape match the kernel +// configuration +TfLiteStatus ValidateTensorSize(TfLiteContext* context, + const LstmTensors& tensors, + const LstmSizeInfo& size_info) { + // Input FC weights + for (size_t i = 1; i < 5; i++) { + TF_LITE_ENSURE_OK( + context, ValidateWeightTensorSize(context, tensors.GetInternalTensor(i), + size_info.state_dimension, + size_info.input_dimension)); + } + // Recurrent FC weights + for (size_t i = 5; i < 9; i++) { + TF_LITE_ENSURE_OK( + context, ValidateWeightTensorSize(context, tensors.GetInternalTensor(i), + size_info.state_dimension, + size_info.state_dimension)); + } + // Biases + for (size_t i = 12; i < 16; i++) { + TF_LITE_ENSURE_OK( + context, ValidateBiasTensorSize(context, tensors.GetInternalTensor(i), + size_info.state_dimension)); + } + + // Check the shape of input state tensors. + // These tensor may be 1D or 2D. It's fine as long as the total size is + // correct. + TF_LITE_ENSURE_EQ(context, NumElements(tensors.HiddenStateTensor()), + size_info.batch_size * size_info.state_dimension); + TF_LITE_ENSURE_EQ(context, NumElements(tensors.CellStateTensor()), + size_info.batch_size * size_info.state_dimension); + + // Check the shape of output tensor against that of input tensor + TF_LITE_ENSURE_EQ(context, tensors.OutputTensor()->dims->size, 3); + TF_LITE_ENSURE_EQ(context, + tensors.GetInternalTensor(kLstmInputTensor)->dims->data[0], + tensors.OutputTensor()->dims->data[0]); + TF_LITE_ENSURE_EQ(context, + tensors.GetInternalTensor(kLstmInputTensor)->dims->data[1], + tensors.OutputTensor()->dims->data[1]); + TF_LITE_ENSURE_EQ(context, tensors.OutputTensor()->dims->data[2], + size_info.state_dimension); + return kTfLiteOk; +} + +// Wrapper function to create gate parameters for the four internal LSTM gates +TfLiteStatus CreateGateParams( + TfLiteContext* context, + /*Input tensors*/ + const TfLiteTensor* input, const TfLiteTensor* input_weight, + const TfLiteTensor* input_bias, + /*Hidden state tensors*/ + const TfLiteTensor* hidden_state, const TfLiteTensor* hidden_state_weight, + const TfLiteTensor* hidden_state_bias, + /*Scale of the fc output (input to non-linear activation)*/ + const float nonlinear_activation_input_scale, const TfLiteType cell_type, + tflite::GateParameters& gate_params) { + // A temp tflite tensor to represent the output of fc operation. Only the data + // type and quantization parameters are set since it is only used for + // parameter calculations + TfLiteTensor fc_output_temp; + fc_output_temp.type = cell_type; + fc_output_temp.params.scale = nonlinear_activation_input_scale; + fc_output_temp.params.zero_point = 0; // symmetrical quantized + + // A temp fc opdata to reuse the helper function on creating fc parameters + tflite::OpDataFullyConnected fc_data_temp; + // TODO(b/265853320): due to the lack of precision for the float scale, + // scale_diff / output_scale <= 0.02 (potentially requires 1e-8 precision) can + // not be satisified for the bias. Here we rely on the correctiveness of the + // conversion process (set input_bias=nullptr to avoid checking) for + // tensor scales + TF_LITE_ENSURE_STATUS(CalculateOpDataFullyConnected( + context, kTfLiteActNone, input->type, input, input_weight, + /*input_bias=*/nullptr, &fc_output_temp, &fc_data_temp)); + gate_params.input_fc_params = FullyConnectedParamsQuantized(fc_data_temp); + double real_multiplier = 0.0; + GetQuantizedConvolutionMultipler(context, input, input_weight, nullptr, + &fc_output_temp, &real_multiplier); + + TF_LITE_ENSURE_STATUS(CalculateOpDataFullyConnected( + context, kTfLiteActNone, hidden_state->type, hidden_state, + hidden_state_weight, hidden_state_bias, &fc_output_temp, &fc_data_temp)); + gate_params.recurrent_fc_params = FullyConnectedParamsQuantized(fc_data_temp); + return kTfLiteOk; +} + +// Create parameters for element wise multiplication that happens in a) cell +// state update ; b) hidden state update +// Note that all the output of gates are symmetrically quantized so only scales +// are required for input. However, during the hidden state update phase, the +// output is the updated hidden state, which is asymmetrically quantized. Thus +// output may require zero point +tflite::ArithmeticParams CreateInterGateMulParams(const float input1_scale, + const float input2_scale, + const float output_scale, + const TfLiteType output_type, + const int output_zp = 0) { + tflite::ArithmeticParams op_params = {}; + if (output_type == kTfLiteInt16) { + op_params.quantized_activation_min = std::numeric_limits::min(); + op_params.quantized_activation_max = std::numeric_limits::max(); + } else if (output_type == kTfLiteInt8) { + op_params.quantized_activation_min = std::numeric_limits::min(); + op_params.quantized_activation_max = std::numeric_limits::max(); + } + + op_params.input1_offset = 0; // symmetric + op_params.input2_offset = 0; // symmetric + op_params.output_offset = output_zp; + + const double input_product_scale = + static_cast(input1_scale) * static_cast(input2_scale); + double effective_scale = + input_product_scale / static_cast(output_scale); + + QuantizeMultiplier(effective_scale, &op_params.output_multiplier, + &op_params.output_shift); + return op_params; +} + +// Create the additional information about the cell state, which include: +// cell_state_scale_power: used in integer nonlinear function (e.g., tanh) +// quantized_cell_clip: quantized cell clip range +CellStateInfo CreateLstmCellStateInfo(const float cell_state_scale, + const float cell_clip) { + CellStateInfo cell_state_info; + // cell_state_scale_power: 2^-cell_state_scale_power = cell state scale + int buffer; + tflite::CheckedLog2(cell_state_scale, &buffer); + cell_state_info.cell_state_scale_power = buffer; + // Cell state specifics + cell_state_info.cell_clip = cell_clip; + cell_state_info.quantized_cell_clip = static_cast( + std::min(std::max(static_cast(cell_clip) / + static_cast(cell_state_scale), + static_cast(-32768.0)), + static_cast(32767.0))); + return cell_state_info; +} + +CellStateInfo CreateLstmCellStateInfoFloat(const float cell_clip) { + CellStateInfo cell_state_info; + cell_state_info.cell_clip = cell_clip; + cell_state_info.cell_state_scale_power = 0; // no quantization + cell_state_info.quantized_cell_clip = 0; // no quantization + return cell_state_info; +} + +tflite::FullyConnectedParams CreateFCParamsFloat() { + FullyConnectedParams op_params; + CalculateActivationRange(kTfLiteActNone, &op_params.float_activation_min, + &op_params.float_activation_max); + return op_params; +} + +tflite::GateParameters CreateGateParamsFloat() { + tflite::GateParameters gate_params = {}; + gate_params.input_fc_params = CreateFCParamsFloat(); + gate_params.recurrent_fc_params = CreateFCParamsFloat(); + return gate_params; +} + +tflite::ArithmeticParams CreateInterGateMulParamsFloat() { + tflite::ArithmeticParams op_params = {}; + CalculateActivationRange(kTfLiteActNone, &op_params.float_activation_min, + &op_params.float_activation_max); + return op_params; +} + +TfLiteStatus PrepareGateParametersFloat(TfLiteContext* context, + const LstmTensors& lstm_tensors, + OpDataLSTM* op_data) { + // Gate Parameters + op_data->forget_gate_parameters = CreateGateParamsFloat(); + op_data->input_gate_parameters = CreateGateParamsFloat(); + op_data->cell_gate_parameters = CreateGateParamsFloat(); + op_data->output_gate_parameters = CreateGateParamsFloat(); + // Inter gate multiplication parameters + op_data->inter_gate_parameters.forget_cell_mul_params = + CreateInterGateMulParamsFloat(); + op_data->inter_gate_parameters.input_mul_params = + CreateInterGateMulParamsFloat(); + op_data->inter_gate_parameters.output_mul_params = + CreateInterGateMulParamsFloat(); + return kTfLiteOk; +} + +TfLiteStatus PrepareGateParametersInteger(TfLiteContext* context, + const LstmTensors& lstm_tensors, + OpDataLSTM* op_data) { + float nonlinear_input_scale = 0.00024414062; // 2^-12 Q3.12 -> Q0.15 + TF_LITE_ENSURE_OK( + context, + CreateGateParams( + context, lstm_tensors.GetInternalTensor(kLstmInputTensor), + lstm_tensors.GetInternalTensor(kLstmInputToForgetWeightsTensor), + lstm_tensors.GetInternalTensor(kLstmForgetGateBiasTensor), + lstm_tensors.GetInternalTensor(kLstmOutputStateTensor), + lstm_tensors.GetInternalTensor(kLstmRecurrentToForgetWeightsTensor), + /*hidden_state_bias=*/nullptr, nonlinear_input_scale, kTfLiteInt16, + op_data->forget_gate_parameters)); + TF_LITE_ENSURE_OK( + context, + CreateGateParams( + context, lstm_tensors.GetInternalTensor(kLstmInputTensor), + lstm_tensors.GetInternalTensor(kLstmInputToInputWeightsTensor), + lstm_tensors.GetInternalTensor(kLstmInputGateBiasTensor), + lstm_tensors.GetInternalTensor(kLstmOutputStateTensor), + lstm_tensors.GetInternalTensor(kLstmRecurrentToInputWeightsTensor), + /*hidden_state_bias=*/nullptr, nonlinear_input_scale, kTfLiteInt16, + op_data->input_gate_parameters)); + TF_LITE_ENSURE_OK( + context, + CreateGateParams( + context, lstm_tensors.GetInternalTensor(kLstmInputTensor), + lstm_tensors.GetInternalTensor(kLstmInputToCellWeightsTensor), + lstm_tensors.GetInternalTensor(kLstmCellGateBiasTensor), + lstm_tensors.GetInternalTensor(kLstmOutputStateTensor), + lstm_tensors.GetInternalTensor(kLstmRecurrentToCellWeightsTensor), + /*hidden_state_bias=*/nullptr, nonlinear_input_scale, kTfLiteInt16, + op_data->cell_gate_parameters)); + TF_LITE_ENSURE_OK( + context, + CreateGateParams( + context, lstm_tensors.GetInternalTensor(kLstmInputTensor), + lstm_tensors.GetInternalTensor(kLstmInputToOutputWeightsTensor), + lstm_tensors.GetInternalTensor(kLstmOutputGateBiasTensor), + lstm_tensors.GetInternalTensor(kLstmOutputStateTensor), + lstm_tensors.GetInternalTensor(kLstmRecurrentToOutputWeightsTensor), + /*hidden_state_bias=*/nullptr, nonlinear_input_scale, kTfLiteInt16, + op_data->output_gate_parameters)); + + // Inter gate multiplication parameters + float nonlinear_output_scale = 0.00003051757; // 2^-15 Q3.12 -> Q0.15 + float cell_state_scale = lstm_tensors.CellStateTensor()->params.scale; + // forget gate output (nonlinear output) x cell state -> cell state + op_data->inter_gate_parameters.forget_cell_mul_params = + CreateInterGateMulParams(nonlinear_output_scale, cell_state_scale, + cell_state_scale, kTfLiteInt16); + // input gate output x cell gate output -> cell state + op_data->inter_gate_parameters.input_mul_params = + CreateInterGateMulParams(nonlinear_output_scale, nonlinear_output_scale, + cell_state_scale, kTfLiteInt16); + // tanh output x output gate output -> hidden state (potentially asymmetric) + op_data->inter_gate_parameters.output_mul_params = CreateInterGateMulParams( + nonlinear_output_scale, nonlinear_output_scale, + lstm_tensors.HiddenStateTensor()->params.scale, + lstm_tensors.HiddenStateTensor()->type, + lstm_tensors.HiddenStateTensor()->params.zero_point); + return kTfLiteOk; +} + +LSTMKernelContents CreateLSTMKernelContent(TfLiteContext* context, + TfLiteNode* node) { + LSTMKernelContents kernel_content; + // Point to correct tensors + for (size_t i = 0; i < 24; i++) { + kernel_content.internal_tensors[i] = + tflite::micro::GetMutableEvalInput(context, node, i); + } + // Output tensor + kernel_content.output_tensor = tflite::micro::GetEvalOutput(context, node, 0); + return kernel_content; +} + +template +LSTMBuffers CreateLSTMBuffers(TfLiteContext* context, + const int* buffer_indices) { + LSTMBuffers buffers; + buffers.buffer0 = reinterpret_cast( + context->GetScratchBuffer(context, buffer_indices[0])); + buffers.buffer1 = reinterpret_cast( + context->GetScratchBuffer(context, buffer_indices[1])); + buffers.buffer2 = reinterpret_cast( + context->GetScratchBuffer(context, buffer_indices[2])); + buffers.buffer3 = reinterpret_cast( + context->GetScratchBuffer(context, buffer_indices[3])); + return buffers; +} + +/*Kernel functions*/ + +void* UnidirectionalSequenceLstmInit(TfLiteContext* context, const char* buffer, + size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpDataLSTM)); +} + +TfLiteStatus UnidirectionalSequenceLstmPrepare(TfLiteContext* context, + TfLiteNode* node) { + TF_LITE_ENSURE_EQ(context, node->outputs->size, 1); + TF_LITE_ENSURE_EQ(context, node->inputs->size, 24); + + TFLITE_DCHECK(node->builtin_data != nullptr); + TFLITE_DCHECK(node->user_data != nullptr); + + OpDataLSTM* op_data = reinterpret_cast(node->user_data); + const auto* builtin_data = + static_cast(node->builtin_data); + // All TempTfLiteTensors will be deallocated through the destructor. + LstmTensors lstm_tensors(context, node); + TF_LITE_ENSURE_OK(context, lstm_tensors.ValidateTensorStatus(context)); + + op_data->cell_gate_nonlinear_type = builtin_data->activation; + op_data->size_info = + CreateLstmSizeInfo(builtin_data->time_major, + lstm_tensors.GetInternalTensor(kLstmInputTensor)->dims, + lstm_tensors.HiddenStateTensor()->dims); + TF_LITE_ENSURE_OK( + context, ValidateTensorSize(context, lstm_tensors, op_data->size_info)); + + // Create cell state information and gate parameters (Fully Connected and Mul) + auto cell_state_type = + lstm_tensors.GetInternalTensor(kLstmCellStateTensor)->type; + if (cell_state_type == kTfLiteFloat32) { + op_data->cell_state_info = + CreateLstmCellStateInfoFloat(builtin_data->cell_clip); + TF_LITE_ENSURE_OK( + context, PrepareGateParametersFloat(context, lstm_tensors, op_data)); + } else if (cell_state_type == kTfLiteInt16) { + op_data->cell_state_info = CreateLstmCellStateInfo( + lstm_tensors.CellStateTensor()->params.scale, builtin_data->cell_clip); + TF_LITE_ENSURE_OK( + context, PrepareGateParametersInteger(context, lstm_tensors, op_data)); + } else { + MicroPrintf( + "Cell state type %s (%d) not supported. The quantized Unidirectional " + "Sequence LSTM Op only support int16 cell state", + TfLiteTypeGetName(cell_state_type), cell_state_type); + return kTfLiteError; + } + // request buffers (four buffers) + for (size_t i = 0; i < 4; i++) { + TF_LITE_ENSURE_OK(context, context->RequestScratchBufferInArena( + context, + op_data->size_info.batch_size * + op_data->size_info.state_dimension * + TfLiteTypeGetSize(cell_state_type), + &(op_data->buffer_indices[i]))); + } + return kTfLiteOk; +} + +TfLiteStatus UnidirectionalSequenceLstmEval(TfLiteContext* context, + TfLiteNode* node) { + TFLITE_DCHECK(node->user_data != nullptr); + const OpDataLSTM& op_data = *reinterpret_cast(node->user_data); + auto kernel_content = CreateLSTMKernelContent(context, node); + + const auto activation_type = + kernel_content.internal_tensors[kLstmInputTensor]->type; + const auto weight_type = + kernel_content.internal_tensors[kLstmInputToInputWeightsTensor]->type; + + switch (activation_type) { + case kTfLiteFloat32: { + LSTMBuffers buffers = + CreateLSTMBuffers(context, op_data.buffer_indices); + EvalLstm(op_data, kernel_content, buffers); + break; + } + case kTfLiteInt8: { + switch (weight_type) { + case kTfLiteInt8: { + // 8(activation)x8(weight)->16(cell) LSTM with 32 bits bias + LSTMBuffers buffers = + CreateLSTMBuffers(context, op_data.buffer_indices); + EvalLstm(op_data, kernel_content, + buffers); + break; + } + default: { + MicroPrintf("Filter type %s (%d) not supported.", + TfLiteTypeGetName(weight_type), activation_type); + return kTfLiteError; + } + } + break; + } + case kTfLiteInt16: { + switch (weight_type) { + case kTfLiteInt8: { + // 16(activation)x8(weight)->16(cell) LSTM with 64 bits bias + LSTMBuffers buffers = + CreateLSTMBuffers(context, op_data.buffer_indices); + EvalLstm(op_data, kernel_content, + buffers); + break; + } + default: { + MicroPrintf("Filter type %s (%d) not supported.", + TfLiteTypeGetName(weight_type), weight_type); + return kTfLiteError; + } + } + break; + } + default: { + MicroPrintf("Input type %s (%d) not supported.", + TfLiteTypeGetName(activation_type), activation_type); + return kTfLiteError; + } + } + return kTfLiteOk; +} + +} // namespace + +TfLiteRegistration Register_UNIDIRECTIONAL_SEQUENCE_LSTM() { + return tflite::micro::RegisterOp(UnidirectionalSequenceLstmInit, + UnidirectionalSequenceLstmPrepare, + UnidirectionalSequenceLstmEval); +} +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/unpack.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/unpack.cpp new file mode 100644 index 0000000..c0d3d8b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/unpack.cpp @@ -0,0 +1,112 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace ops { +namespace micro { +namespace unpack { +namespace { + +constexpr int kInputTensor = 0; + +template +TfLiteStatus UnpackImpl(TfLiteContext* context, TfLiteNode* node, + const TfLiteEvalTensor* input, int output_count, + int axis) { + const TfLiteEvalTensor* output0 = + tflite::micro::GetEvalOutput(context, node, 0); + const TfLiteIntArray* input_dims = input->dims; + const TfLiteIntArray* output_dims = output0->dims; + const int dimensions = input_dims->size; + + if (axis < 0) { + axis += input->dims->size; + } + + TFLITE_DCHECK_LT(axis, dimensions); + + int outer_size = 1; + for (int i = 0; i < axis; ++i) { + outer_size *= input_dims->data[i]; + } + int copy_size = 1; + for (int i = axis + 1; i < dimensions; ++i) { + copy_size *= input_dims->data[i]; + } + int output_size = 1; + for (int i = 0; i < output_dims->size; ++i) { + output_size *= output_dims->data[i]; + } + TFLITE_DCHECK_EQ(output_size, copy_size * outer_size); + + const T* input_data = tflite::micro::GetTensorData(input); + + for (int i = 0; i < output_count; ++i) { + TfLiteEvalTensor* t = tflite::micro::GetEvalOutput(context, node, i); + T* output_data = tflite::micro::GetTensorData(t); + for (int k = 0; k < outer_size; ++k) { + T* output_ptr = output_data + copy_size * k; + int loc = k * output_count * copy_size + i * copy_size; + const T* input_ptr = input_data + loc; + for (int j = 0; j < copy_size; ++j) output_ptr[j] = input_ptr[j]; + } + } + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + TfLiteUnpackParams* data = + reinterpret_cast(node->builtin_data); + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + + switch (input->type) { + case kTfLiteFloat32: { + return UnpackImpl(context, node, input, data->num, data->axis); + } + case kTfLiteInt32: { + return UnpackImpl(context, node, input, data->num, data->axis); + } + case kTfLiteInt8: { + return UnpackImpl(context, node, input, data->num, data->axis); + } + default: { + MicroPrintf("Type '%s' is not supported by unpack.", + TfLiteTypeGetName(input->type)); + return kTfLiteError; + } + } + + return kTfLiteOk; +} +} // namespace +} // namespace unpack + +TfLiteRegistration Register_UNPACK() { + return tflite::micro::RegisterOp(nullptr, nullptr, unpack::Eval); +} + +} // namespace micro +} // namespace ops +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/var_handle.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/var_handle.cpp new file mode 100644 index 0000000..2329f2c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/var_handle.cpp @@ -0,0 +1,93 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +namespace { + +struct OpData { + int32_t resource_id; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + OpData* op_data = reinterpret_cast(node->user_data); + const auto* params = + reinterpret_cast(node->builtin_data); + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + MicroGraph& graph_info = micro_context->graph(); + + MicroResourceVariables* resources = graph_info.GetResourceVariables(); + if (resources == nullptr) { + MicroPrintf( + "VAR_HANDLE requires resource variables. Please create " + "ResourceVariables and pass it to the interpreter."); + return kTfLiteError; + } + op_data->resource_id = + resources->CreateIdIfNoneFound(params->container, params->shared_name); + if (op_data->resource_id < 0) { + return kTfLiteError; + } + + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TFLITE_DCHECK(output != nullptr); + + // Assign saved resource_id so this output tensor will always return the + // correct resource id. + output->data.i32 = &op_data->resource_id; + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + OpData* op_data = reinterpret_cast(node->user_data); + + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TFLITE_DCHECK(output != nullptr); + + // Assign saved resource_id so this output tensor will always return the + // correct resource id. + output->data.i32 = &op_data->resource_id; + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_VAR_HANDLE() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/while.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/while.cpp new file mode 100644 index 0000000..ba18ba6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/while.cpp @@ -0,0 +1,133 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/builtin_op_data.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +namespace { + +struct OpData { + int cond_subgraph_index; + int body_subgraph_index; +}; + +void* Init(TfLiteContext* context, const char* buffer, size_t length) { + TFLITE_DCHECK(context->AllocatePersistentBuffer != nullptr); + return context->AllocatePersistentBuffer(context, sizeof(OpData)); +} + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + OpData* op_data = reinterpret_cast(node->user_data); + const auto* params = + reinterpret_cast(node->builtin_data); + + op_data->cond_subgraph_index = params->cond_subgraph_index; + op_data->body_subgraph_index = params->body_subgraph_index; + + // The first input is the condition. + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + + size_t num_inputs = node->inputs->size; + size_t num_outputs = node->outputs->size; + + MicroGraph& graph_info = micro_context->graph(); + + TF_LITE_ENSURE(context, + op_data->cond_subgraph_index < graph_info.NumSubgraphs()); + TF_LITE_ENSURE(context, + op_data->body_subgraph_index < graph_info.NumSubgraphs()); + + TF_LITE_ENSURE_EQ(context, num_inputs, + graph_info.NumSubgraphInputs(op_data->cond_subgraph_index)); + TF_LITE_ENSURE_EQ(context, num_inputs, + graph_info.NumSubgraphInputs(op_data->body_subgraph_index)); + TF_LITE_ENSURE_EQ(context, num_inputs, num_outputs); + TF_LITE_ENSURE_EQ( + context, num_outputs, + graph_info.NumSubgraphOutputs(op_data->body_subgraph_index)); + + return kTfLiteOk; +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const OpData* op_data = reinterpret_cast(node->user_data); + + tflite::MicroContext* micro_context = tflite::GetMicroContext(context); + MicroGraph* graph_info = µ_context->graph(); + + TF_LITE_ENSURE_OK(context, + tflite::micro::CopyOpInputsToSubgraphInputs( + context, node, graph_info, op_data->cond_subgraph_index, + /*first_tensor_idx=*/0)); + + TF_LITE_ENSURE_OK(context, + graph_info->InvokeSubgraph(op_data->cond_subgraph_index)); + + TfLiteEvalTensor* cond_subgraph_output = graph_info->GetSubgraphOutput( + op_data->cond_subgraph_index, /*tensor_idx=*/0); + bool cond_value = cond_subgraph_output->data.b[0]; + + TF_LITE_ENSURE_OK(context, + tflite::micro::CopyOpInputsToSubgraphInputs( + context, node, graph_info, op_data->body_subgraph_index, + /*first_tensor_idx=*/0)); + TF_LITE_ENSURE_OK(context, + tflite::micro::CopyOpInputsToOpOutputs(context, node)); + + while (cond_value == true) { + // Copy output of this iteration back to the body input. + TF_LITE_ENSURE_OK( + context, tflite::micro::CopyOpOutputsToSubgraphInputs( + context, node, graph_info, op_data->body_subgraph_index)); + TF_LITE_ENSURE_OK(context, + graph_info->InvokeSubgraph(op_data->body_subgraph_index)); + + TF_LITE_ENSURE_OK( + context, tflite::micro::CopySubgraphOutputsToOpOutputs( + context, node, graph_info, op_data->body_subgraph_index)); + TF_LITE_ENSURE_OK( + context, tflite::micro::CopyOpOutputsToSubgraphInputs( + context, node, graph_info, op_data->cond_subgraph_index)); + TF_LITE_ENSURE_OK(context, + graph_info->InvokeSubgraph(op_data->cond_subgraph_index)); + + cond_subgraph_output = graph_info->GetSubgraphOutput( + op_data->cond_subgraph_index, /*tensor_idx=*/0); + cond_value = cond_subgraph_output->data.b[0]; + } + + return kTfLiteOk; +} + +} // namespace. + +TfLiteRegistration Register_WHILE() { + return tflite::micro::RegisterOp(Init, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/zeros_like.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/zeros_like.cpp new file mode 100644 index 0000000..c868341 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/kernels/zeros_like.cpp @@ -0,0 +1,88 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +namespace { + +constexpr int kInputTensor = 0; +constexpr int kOutputTensor = 0; + +TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node) { + MicroContext* micro_context = GetMicroContext(context); + + TF_LITE_ENSURE_EQ(context, NumInputs(node), 1); + TF_LITE_ENSURE_EQ(context, NumOutputs(node), 1); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + TfLiteTensor* output = + micro_context->AllocateTempOutputTensor(node, kOutputTensor); + TF_LITE_ENSURE(context, output != nullptr); + output->type = input->type; + + micro_context->DeallocateTempTfLiteTensor(input); + micro_context->DeallocateTempTfLiteTensor(output); + return kTfLiteOk; +} + +template +void resetZeros(T* out, const int num_elements) { + for (int i = 0; i < num_elements; ++i) { + out[i] = static_cast(0); + } +} + +TfLiteStatus Eval(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TfLiteEvalTensor* output = + tflite::micro::GetEvalOutput(context, node, kOutputTensor); + int flat_size = MatchingFlatSize(tflite::micro::GetTensorShape(input), + tflite::micro::GetTensorShape(output)); + switch (input->type) { + case kTfLiteInt64: + resetZeros(tflite::micro::GetTensorData(output), flat_size); + break; + case kTfLiteInt32: + resetZeros(tflite::micro::GetTensorData(output), flat_size); + break; + case kTfLiteInt8: + resetZeros(tflite::micro::GetTensorData(output), flat_size); + break; + case kTfLiteFloat32: + resetZeros(tflite::micro::GetTensorData(output), flat_size); + break; + default: + MicroPrintf( + "ZerosLike only currently supports int64, int32, " + "and float32, got %d.", + input->type); + return kTfLiteError; + } + return kTfLiteOk; +} +} // namespace + +TfLiteRegistration Register_ZEROS_LIKE() { + return tflite::micro::RegisterOp(nullptr, Prepare, Eval); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.cpp new file mode 100644 index 0000000..486b68e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.cpp @@ -0,0 +1,171 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" + +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +uint8_t* AlignPointerUp(uint8_t* data, size_t alignment) { + std::uintptr_t data_as_uintptr_t = reinterpret_cast(data); + uint8_t* aligned_result = reinterpret_cast( + ((data_as_uintptr_t + (alignment - 1)) / alignment) * alignment); + return aligned_result; +} + +uint8_t* AlignPointerDown(uint8_t* data, size_t alignment) { + std::uintptr_t data_as_uintptr_t = reinterpret_cast(data); + uint8_t* aligned_result = + reinterpret_cast((data_as_uintptr_t / alignment) * alignment); + return aligned_result; +} + +size_t AlignSizeUp(size_t size, size_t alignment) { + size_t aligned_size = (((size + (alignment - 1)) / alignment) * alignment); + return aligned_size; +} + +TfLiteStatus TfLiteTypeSizeOf(TfLiteType type, size_t* size) { + switch (type) { + case kTfLiteFloat16: + *size = sizeof(int16_t); + break; + case kTfLiteFloat32: + *size = sizeof(float); + break; + case kTfLiteFloat64: + *size = sizeof(double); + break; + case kTfLiteInt16: + *size = sizeof(int16_t); + break; + case kTfLiteInt32: + *size = sizeof(int32_t); + break; + case kTfLiteUInt32: + *size = sizeof(uint32_t); + break; + case kTfLiteUInt8: + *size = sizeof(uint8_t); + break; + case kTfLiteInt8: + *size = sizeof(int8_t); + break; + case kTfLiteInt64: + *size = sizeof(int64_t); + break; + case kTfLiteUInt64: + *size = sizeof(uint64_t); + break; + case kTfLiteBool: + *size = sizeof(bool); + break; + case kTfLiteResource: + *size = sizeof(int32_t); + break; + case kTfLiteComplex64: + *size = sizeof(float) * 2; + break; + case kTfLiteComplex128: + *size = sizeof(double) * 2; + break; + case kTfLiteInt4: + *size = sizeof(int8_t); + break; + default: + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus BytesRequiredForTensor(const tflite::Tensor& flatbuffer_tensor, + size_t* bytes, size_t* type_size) { + int element_count = 1; + // If flatbuffer_tensor.shape == nullptr, then flatbuffer_tensor is a scalar + // so has 1 element. + if (flatbuffer_tensor.shape() != nullptr) { + for (size_t n = 0; n < flatbuffer_tensor.shape()->Length(); ++n) { + element_count *= flatbuffer_tensor.shape()->Get(n); + } + } + + TfLiteType tf_lite_type; + TF_LITE_ENSURE_STATUS( + ConvertTensorType(flatbuffer_tensor.type(), &tf_lite_type)); + TF_LITE_ENSURE_STATUS(TfLiteTypeSizeOf(tf_lite_type, type_size)); + *bytes = element_count * (*type_size); + return kTfLiteOk; +} + +TfLiteStatus TfLiteEvalTensorByteLength(const TfLiteEvalTensor* eval_tensor, + size_t* out_bytes) { + TFLITE_DCHECK(out_bytes != nullptr); + + int element_count = 1; + // If eval_tensor->dims == nullptr, then tensor is a scalar so has 1 element. + if (eval_tensor->dims != nullptr) { + for (int n = 0; n < eval_tensor->dims->size; ++n) { + element_count *= eval_tensor->dims->data[n]; + } + } + size_t type_size; + TF_LITE_ENSURE_STATUS(TfLiteTypeSizeOf(eval_tensor->type, &type_size)); + *out_bytes = element_count * type_size; + return kTfLiteOk; +} + +TfLiteStatus AllocateOutputDimensionsFromInput(TfLiteContext* context, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteTensor* output) { + const TfLiteTensor* input = nullptr; + + TF_LITE_ENSURE(context, input1->dims != nullptr); + TF_LITE_ENSURE(context, input2->dims != nullptr); + TF_LITE_ENSURE(context, output->dims->size == 0); + + input = input1->dims->size > input2->dims->size ? input1 : input2; + TF_LITE_ENSURE(context, output->type == input->type); + + size_t size = 0; + TfLiteTypeSizeOf(input->type, &size); + const int dimensions_count = tflite::GetTensorShape(input).DimensionsCount(); + for (int i = 0; i < dimensions_count; i++) { + size *= input->dims->data[i]; + } + + output->bytes = size; + + output->dims = + reinterpret_cast(context->AllocatePersistentBuffer( + context, TfLiteIntArrayGetSizeInBytes(size))); + + output->dims->size = input->dims->size; + for (int i = 0; i < dimensions_count; i++) { + output->dims->data[i] = input->dims->data[i]; + } + + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h new file mode 100644 index 0000000..2ceb2bc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h @@ -0,0 +1,65 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MEMORY_HELPERS_H_ +#define TENSORFLOW_LITE_MICRO_MEMORY_HELPERS_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h" + +namespace tflite { + +// Returns the next pointer address aligned to the given alignment. +uint8_t* AlignPointerUp(uint8_t* data, size_t alignment); + +// Returns the previous pointer address aligned to the given alignment. +uint8_t* AlignPointerDown(uint8_t* data, size_t alignment); + +// Returns an increased size that's a multiple of alignment. +size_t AlignSizeUp(size_t size, size_t alignment); + +// Templated version of AlignSizeUp +// Returns an increased size that's a multiple of alignment. +template +size_t AlignSizeUp(size_t count = 1) { + return AlignSizeUp(sizeof(T) * count, alignof(T)); +} + +// Returns size in bytes for a given TfLiteType. +TfLiteStatus TfLiteTypeSizeOf(TfLiteType type, size_t* size); + +// How many bytes are needed to hold a tensor's contents. +TfLiteStatus BytesRequiredForTensor(const tflite::Tensor& flatbuffer_tensor, + size_t* bytes, size_t* type_size); + +// How many bytes are used in a TfLiteEvalTensor instance. The byte length is +// returned in out_bytes. +TfLiteStatus TfLiteEvalTensorByteLength(const TfLiteEvalTensor* eval_tensor, + size_t* out_bytes); + +// Deduce output dimensions from input and allocate given size. +// Useful for operators with two inputs where the largest input should equal the +// output dimension. +TfLiteStatus AllocateOutputDimensionsFromInput(TfLiteContext* context, + const TfLiteTensor* input1, + const TfLiteTensor* input2, + TfLiteTensor* output); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MEMORY_HELPERS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.cpp new file mode 100644 index 0000000..ff98fc2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.cpp @@ -0,0 +1,448 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_string.h" + +namespace tflite { + +namespace { + +// Returns a character representing a numbered buffer +// for GreedyMemoryPlanner::PrintMemoryPlan() +char GetOrdinalCharacter(int i) { + if (i < 10) { + return '0' + i; + } else if (i < 36) { + return 'a' + (i - 10); + } else if (i < 62) { + return 'A' + (i - 36); + } + return '*'; +} + +} // namespace + +// Simple stable in-place sort function. Not time-efficient for large arrays. +// Would normally be in an anonymous namespace to keep it private, but we want +// to be able to test it externally. +void ReverseSortInPlace(int* values, int* ids, int size) { + bool any_swapped; + do { + any_swapped = false; + for (int i = 1; i < size; ++i) { + if (values[i - 1] < values[i]) { + const int value_temp = values[i - 1]; + values[i - 1] = values[i]; + values[i] = value_temp; + const int id_temp = ids[i - 1]; + ids[i - 1] = ids[i]; + ids[i] = id_temp; + any_swapped = true; + } + } + } while (any_swapped); +} + +GreedyMemoryPlanner::GreedyMemoryPlanner() {} + +TfLiteStatus GreedyMemoryPlanner::Init(unsigned char* scratch_buffer, + int scratch_buffer_size) { + // Reset internal states + buffer_count_ = 0; + need_to_calculate_offsets_ = true; + + // Allocate the arrays we need within the scratch buffer arena. + max_buffer_count_ = scratch_buffer_size / per_buffer_size(); + + unsigned char* next_free = scratch_buffer; + requirements_ = reinterpret_cast(next_free); + next_free += sizeof(BufferRequirements) * max_buffer_count_; + + buffer_sizes_sorted_ = reinterpret_cast(next_free); + next_free += sizeof(int) * max_buffer_count_; + + buffer_ids_sorted_ = reinterpret_cast(next_free); + next_free += sizeof(int) * max_buffer_count_; + + buffers_sorted_by_offset_ = reinterpret_cast(next_free); + next_free += sizeof(ListEntry) * max_buffer_count_; + + buffer_offsets_ = reinterpret_cast(next_free); + return kTfLiteOk; +} + +GreedyMemoryPlanner::~GreedyMemoryPlanner() { + // We don't own the scratch buffer, so don't deallocate anything. +} + +TfLiteStatus GreedyMemoryPlanner::AddBuffer(int size, int first_time_used, + int last_time_used) { + if (buffer_count_ >= max_buffer_count_) { + MicroPrintf("Too many buffers (max is %d)", max_buffer_count_); + return kTfLiteError; + } + BufferRequirements* current = &requirements_[buffer_count_]; + current->size = size; + current->first_time_used = first_time_used; + current->last_time_used = last_time_used; + current->offline_offset = kOnlinePlannedBuffer; + ++buffer_count_; + need_to_calculate_offsets_ = true; + return kTfLiteOk; +} + +TfLiteStatus GreedyMemoryPlanner::AddBuffer(int size, int first_time_used, + int last_time_used, + int offline_offset) { + BufferRequirements* current = &requirements_[buffer_count_]; + if (AddBuffer(size, first_time_used, last_time_used) != kTfLiteOk) { + return kTfLiteError; + } + current->offline_offset = offline_offset; + return kTfLiteOk; +} + +bool GreedyMemoryPlanner::DoesEntryOverlapInTime( + const GreedyMemoryPlanner::ListEntry* entry, const int first_time_used, + const int last_time_used) const { + const BufferRequirements* entry_requirements = + &requirements_[entry->requirements_index]; + if (entry_requirements->first_time_used > last_time_used) { + return false; + } + if (first_time_used > entry_requirements->last_time_used) { + return false; + } + return true; +} + +GreedyMemoryPlanner::ListEntry* +GreedyMemoryPlanner::NextSimultaneouslyActiveBuffer( + const GreedyMemoryPlanner::ListEntry* start, const int first_time_used, + const int last_time_used) { + ListEntry* result = nullptr; + ListEntry* candidate_next_entry; + if (start == nullptr) { + candidate_next_entry = &buffers_sorted_by_offset_[first_entry_index_]; + } else { + if (start->next_entry_index == -1) { + return nullptr; + } + candidate_next_entry = &buffers_sorted_by_offset_[start->next_entry_index]; + } + do { + if (DoesEntryOverlapInTime(candidate_next_entry, first_time_used, + last_time_used)) { + result = candidate_next_entry; + break; + } + if (candidate_next_entry->next_entry_index == -1) { + break; + } + candidate_next_entry = + &buffers_sorted_by_offset_[candidate_next_entry->next_entry_index]; + } while (true); + return result; +} + +void GreedyMemoryPlanner::CalculateOffsetsIfNeeded() { + if (!need_to_calculate_offsets_ || (buffer_count_ == 0)) { + return; + } + need_to_calculate_offsets_ = false; + + // Start off by ordering the buffers in descending order of size. + // This helps find a more compact layout. Intuitively, you can think + // about putting the large buffers in place first, and then the + // smaller buffers can fit in the gaps, rather than fragmenting the + // gaps with small buffers at the beginning. Add offline planned offsets + // first in the list, since they have a predetermined offset. + int idx_from_tail = buffer_count_; + int idx_from_head = 0; + for (int i = 0; i < buffer_count_; ++i) { + if (requirements_[i].offline_offset == kOnlinePlannedBuffer) { + idx_from_tail--; + buffer_sizes_sorted_[idx_from_tail] = requirements_[i].size; + buffer_ids_sorted_[idx_from_tail] = i; + buffer_offsets_[i] = -1; + } else { + buffer_sizes_sorted_[idx_from_head] = requirements_[i].size; + buffer_ids_sorted_[idx_from_head] = i; + buffer_offsets_[i] = requirements_[i].offline_offset; + idx_from_head++; + } + } + + // This sorting algorithm is naive, and may end up taking a very long time + // with hundreds of buffers. Do not sort the offline planned offsets. + ReverseSortInPlace(&buffer_sizes_sorted_[idx_from_head], + &buffer_ids_sorted_[idx_from_head], + buffer_count_ - idx_from_head); + + // Initialize the first entry to the first buffer in + // buffer_ids_sorted_. + // - If there are no offline planned offsets, the largest buffer will be + // first, and the buffers will be handled in size order. + // - If offline offsets are present, these will be handled first in order + // for the greedy algorithm to utilized gaps in the offline plan. + first_entry_index_ = 0; + next_free_entry_ = 1; + ListEntry* first_entry = &buffers_sorted_by_offset_[first_entry_index_]; + first_entry->next_entry_index = -1; // to mark the entry as end of list + int buffer_id = buffer_ids_sorted_[0]; + first_entry->requirements_index = buffer_id; + if (requirements_[buffer_id].offline_offset == kOnlinePlannedBuffer) { + buffer_offsets_[buffer_id] = 0; + } + first_entry->offset = buffer_offsets_[buffer_id]; + + // Work through the rest of the buffers to find a good gap to place each one. + for (int i = 1; i < buffer_count_; ++i) { + // The id is the order the buffer was originally added by the client. + buffer_id = buffer_ids_sorted_[i]; + // Look at what size and time range the buffer needs to be active. + BufferRequirements* wanted_requirements = &requirements_[buffer_id]; + const int wanted_size = wanted_requirements->size; + const int wanted_first_time_used = wanted_requirements->first_time_used; + const int wanted_last_time_used = wanted_requirements->last_time_used; + + // Find the first buffer that's active in our time range. All placed + // buffers are stored in the order of their starting position in the arena + // so that it's easy to find the next buffer in memory, and so the gap. + // The candidate_entry variable holds the buffer that we're considering + // placing the current buffer after. + + int candidate_offset = 0; + // Loop through the offset-ordered list of buffers, looking for gaps. + if (wanted_requirements->offline_offset == kOnlinePlannedBuffer) { + ListEntry* prior_entry = nullptr; + while (true) { + // Find out what the next active buffer is. + ListEntry* next_entry = NextSimultaneouslyActiveBuffer( + prior_entry, wanted_first_time_used, wanted_last_time_used); + + if (prior_entry) { + BufferRequirements* candidate_requirements = + &requirements_[prior_entry->requirements_index]; + const int prior_entry_offset = + prior_entry->offset + candidate_requirements->size; + if (prior_entry_offset > candidate_offset) { + candidate_offset = prior_entry_offset; + } + } + if (next_entry == nullptr) { + // We're at the end of the list, so we can always append the buffer + // here. + break; + } + // Find out how much space there is between us and the next buffer. + const int gap = next_entry->offset - candidate_offset; + if (gap >= wanted_size) { + // This entry has a big enough gap between it and the next, so + // use it! + break; + } + // The gap wasn't big enough, so move on to another candidate. + prior_entry = next_entry; + } + } else { + // Offline planned offset are to be considered constant + candidate_offset = wanted_requirements->offline_offset; + } + // At this point, we've either found a gap (possibly at the end of the + // list) and want to place the buffer there, or there are no other active + // buffers in this time range and so we can put it at offset zero. + // Record the buffer's offset in our plan. + buffer_offsets_[buffer_id] = candidate_offset; + // Add the newly-placed buffer to our offset-ordered list, so that + // subsequent passes can fit in their buffers around it. + ListEntry* new_entry = &buffers_sorted_by_offset_[next_free_entry_]; + new_entry->offset = candidate_offset; + new_entry->requirements_index = buffer_id; + const int new_entry_index = next_free_entry_; + ++next_free_entry_; + + if (first_entry->offset > candidate_offset) { + // The new entry offset is smaller than the first entry offset => + // replace the first entry + first_entry = new_entry; + first_entry->next_entry_index = first_entry_index_; + first_entry_index_ = new_entry_index; + } else { + ListEntry* current_entry = first_entry; + // Make sure that we insert the buffer at the correct place in the + // buffer-offset-ordered list + while (true) { + const int next_entry_index = current_entry->next_entry_index; + if (next_entry_index == -1) { + // We're at the end of the list, so just add the new entry here. + current_entry->next_entry_index = new_entry_index; + new_entry->next_entry_index = -1; + break; + } + // not at the end of the list -> take a look at next entry + ListEntry* next_entry = &buffers_sorted_by_offset_[next_entry_index]; + if (next_entry->offset > candidate_offset) { + // We're at the right spot to do an insertion and retain the sorting + // order, so place the new entry here. + new_entry->next_entry_index = current_entry->next_entry_index; + current_entry->next_entry_index = new_entry_index; + break; + } + current_entry = next_entry; + } + } + } +} + +size_t GreedyMemoryPlanner::GetMaximumMemorySize() { + CalculateOffsetsIfNeeded(); + if (buffer_count_ == 0) { + return 0; + } + ListEntry* entry = &buffers_sorted_by_offset_[first_entry_index_]; + size_t max_size = 0; + while (entry) { + BufferRequirements* requirements = + &requirements_[entry->requirements_index]; + const size_t current_size = entry->offset + requirements->size; + if (current_size > max_size) { + max_size = current_size; + } + if (entry->next_entry_index == -1) { + break; + } + entry = &buffers_sorted_by_offset_[entry->next_entry_index]; + } + return max_size; +} + +void GreedyMemoryPlanner::PrintMemoryPlan() { + CalculateOffsetsIfNeeded(); + + for (int i = 0; i < buffer_count_; ++i) { + MicroPrintf("%c (id=%d): size=%d, offset=%d, first_used=%d last_used=%d", + GetOrdinalCharacter(i), i, requirements_[i].size, + buffer_offsets_[i], requirements_[i].first_time_used, + requirements_[i].last_time_used); + } + + constexpr int kLineWidth = 80; + int max_size = kLineWidth; + int max_time = 0; + for (int i = 0; i < buffer_count_; ++i) { + BufferRequirements* requirements = &requirements_[i]; + const int offset = buffer_offsets_[i]; + const int last_time_used = requirements->last_time_used; + const int size = offset + requirements->size; + if (size > max_size) { + max_size = size; + } + if (last_time_used > max_time) { + max_time = last_time_used; + } + } + + char line[kLineWidth + 1]; + for (int t = 0; t <= max_time; ++t) { + for (int c = 0; c < kLineWidth; ++c) { + line[c] = '.'; + } + int memory_use = 0; + for (int i = 0; i < buffer_count_; ++i) { + BufferRequirements* requirements = &requirements_[i]; + if ((t < requirements->first_time_used) || + (t > requirements->last_time_used)) { + continue; + } + const int offset = buffer_offsets_[i]; + if (offset == -1) { + continue; + } + const int size = requirements->size; + memory_use += size; + const int line_start = (offset * kLineWidth) / max_size; + const int line_end = ((offset + size) * kLineWidth) / max_size; + for (int n = line_start; n < line_end; ++n) { + if (line[n] == '.') { + line[n] = GetOrdinalCharacter(i); + } else { + line[n] = '!'; + } + } + } + line[kLineWidth] = 0; + + MicroPrintf("%s%d: %s (%dk)", t < 10 ? " " : "", t, (const char*)line, + (memory_use + 1023) / 1024); + } +} + +int GreedyMemoryPlanner::GetBufferCount() { return buffer_count_; } + +TfLiteStatus GreedyMemoryPlanner::GetOffsetForBuffer(int buffer_index, + int* offset) { + CalculateOffsetsIfNeeded(); + if ((buffer_index < 0) || (buffer_index >= buffer_count_)) { + MicroPrintf("buffer index %d is outside range 0 to %d", buffer_index, + buffer_count_); + return kTfLiteError; + } + *offset = buffer_offsets_[buffer_index]; + return kTfLiteOk; +} + +bool GreedyMemoryPlanner::DoAnyBuffersOverlap() { + CalculateOffsetsIfNeeded(); + bool were_overlaps_found = false; + for (int i = 0; i < buffer_count_; ++i) { + BufferRequirements* a_requirements = &requirements_[i]; + const int a_start_offset = buffer_offsets_[i]; + const int a_first_time_used = a_requirements->first_time_used; + const int a_last_time_used = a_requirements->last_time_used; + const int a_end_offset = a_start_offset + a_requirements->size; + for (int j = 0; j < buffer_count_; ++j) { + if (i == j) { + continue; + } + BufferRequirements* b_requirements = &requirements_[j]; + const int b_start_offset = buffer_offsets_[j]; + const int b_first_time_used = b_requirements->first_time_used; + const int b_last_time_used = b_requirements->last_time_used; + const int b_end_offset = b_start_offset + b_requirements->size; + if ((a_first_time_used > b_last_time_used) || + (b_first_time_used > a_last_time_used)) { + // Buffers don't overlap in time. + continue; + } + if ((a_start_offset >= b_end_offset) || + (b_start_offset >= a_end_offset)) { + // No overlap in memory. + continue; + } + were_overlaps_found = true; + MicroPrintf("Overlap: %d (%d=>%d, %d->%d) vs %d (%d=>%d, %d->%d)", i, + a_first_time_used, a_last_time_used, a_start_offset, + a_end_offset, j, b_first_time_used, b_last_time_used, + b_start_offset, b_end_offset); + } + } + return were_overlaps_found; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h new file mode 100644 index 0000000..d77a595 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h @@ -0,0 +1,165 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_GREEDY_MEMORY_PLANNER_H_ +#define TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_GREEDY_MEMORY_PLANNER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h" + +namespace tflite { + +constexpr int kOnlinePlannedBuffer = -1; + +// A memory planner that uses a greedy algorithm to arrange buffers in memory +// to minimize the overall arena size needed. +// +// The algorithm works like this: +// - The client enters the buffer information through AddBuffer(). +// - When a function like GetOffsetForBuffer() is called, the +// CalculateOffsetsIfNeeded() method is invoked. +// - If an up to date plan is not already present, one will be calculated. +// - The buffers are sorted in descending order of size. +// - The largest buffer is placed at offset zero. +// - The rest of the buffers are looped through in descending size order. +// - The other buffers that need to be in memory at the same time are found. +// - The first gap between simultaneously active buffers that the current +// buffer fits into will be used. +// - If no large-enough gap is found, the current buffer is placed after the +// last buffer that's simultaneously active. +// - This continues until all buffers are placed, and the offsets stored. +// +// This is not guaranteed to produce the best placement, since that's an +// NP-Complete problem, but in practice it should produce one that's decent. +class GreedyMemoryPlanner : public MicroMemoryPlanner { + public: + GreedyMemoryPlanner(); + ~GreedyMemoryPlanner() override; + + // You need to pass in an area of memory to be used for planning. The client + // should ensure the validity of the memory when it needs to use this object. + // This memory isn't owned by this object, so management should be handled by + // the client. This is so it can be stack or globally allocated if necessary + // on devices without dynamic memory allocation. How many buffers can be + // planned for will depend on the size of this scratch memory, so you should + // enlarge it if you see an error when calling AddBuffer(). The memory can be + // reused once you're done with the planner, as long as you copy the + // calculated offsets to another location. Each buffer requires about 36 bytes + // of scratch. + TfLiteStatus Init(unsigned char* scratch_buffer, + int scratch_buffer_size) override; + + // Record details of a buffer we want to place. + TfLiteStatus AddBuffer(int size, int first_time_used, + int last_time_used) override; + + // Record details of an offline planned buffer offset we want to place. + // offline_offset is the buffer offset from the start of the arena. + TfLiteStatus AddBuffer(int size, int first_time_used, int last_time_used, + int offline_offset) override; + + // Returns the high-water mark of used memory. This is the minimum size of a + // memory arena you'd need to allocate to hold these buffers. + size_t GetMaximumMemorySize() override; + + // How many buffers have been recorded. + int GetBufferCount() override; + + // Where a given buffer should be placed in the memory arena. + // This information is stored in the memory arena itself, so once the arena + // is used for inference, it will be overwritten. + TfLiteStatus GetOffsetForBuffer(int buffer_index, int* offset) override; + + // Prints an ascii-art diagram of the buffer layout plan. + void PrintMemoryPlan() override; + + // Debug method to check whether any buffer allocations are overlapping. This + // is an O(N^2) complexity operation, so only use for testing. + bool DoAnyBuffersOverlap(); + + // Used to store a list of buffers ordered by their offset. + struct ListEntry { + int offset; + int requirements_index; + int next_entry_index; + }; + + // Number of bytes required in order to plan a buffer. + static size_t per_buffer_size() { + const int per_buffer_size = + sizeof(BufferRequirements) + // requirements_ + sizeof(int) + // buffer_sizes_sorted_ + sizeof(int) + // buffer_ids_sorted_ + sizeof(ListEntry) + // buffers_sorted_by_offset_ + sizeof(int); // buffer_offsets_; + return per_buffer_size; + } + + private: + // Whether a buffer is active in a given time range. + bool DoesEntryOverlapInTime(const ListEntry* entry, const int first_time_used, + const int last_time_used) const; + + // Walks the list to return the next buffer that is active in a given time + // range, or a null pointer if there are none. + ListEntry* NextSimultaneouslyActiveBuffer(const ListEntry* start, + const int first_time_used, + const int last_time_used); + + // If there isn't an up to date plan, calculate a new one. + void CalculateOffsetsIfNeeded(); + + // How many buffers we can plan for, based on the arena size we're given in + // the constructor. + int max_buffer_count_; + + // The number of buffers added so far. + int buffer_count_; + + // Records the client-provided information about each buffer. + struct BufferRequirements { + int size; + int offline_offset; + int first_time_used; + int last_time_used; + }; + + // Working arrays used during the layout algorithm. + BufferRequirements* requirements_; + // buffer_sizes_sorted_ and buffer_ids_sorted_ are sorted according to: + // { + // offline planned buffers, + // online planned buffers sorted by size + // } + int* buffer_sizes_sorted_; + int* buffer_ids_sorted_; + ListEntry* buffers_sorted_by_offset_; + int next_free_entry_; // Index of the next free entry of + // buffers_sorted_by_offset_ + int first_entry_index_; // Index of the first entry (smallest offset) of + // buffers_sorted_by_offset_ + + // Stores the outcome of the plan, the location of each buffer in the arena. + int* buffer_offsets_; + + // Whether buffers have been added since the last plan was calculated. + bool need_to_calculate_offsets_; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_GREEDY_MEMORY_PLANNER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/linear_memory_planner.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/linear_memory_planner.cpp new file mode 100644 index 0000000..6e21eb6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/linear_memory_planner.cpp @@ -0,0 +1,56 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/linear_memory_planner.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +// Patched by Edge Impulse +constexpr int LinearMemoryPlanner::kMaxBufferCount; + +LinearMemoryPlanner::LinearMemoryPlanner() + : current_buffer_count_(0), next_free_offset_(0) {} +LinearMemoryPlanner::~LinearMemoryPlanner() {} + +TfLiteStatus LinearMemoryPlanner::AddBuffer(int size, int first_time_used, + int last_time_used) { + if (current_buffer_count_ >= kMaxBufferCount) { + MicroPrintf("Too many buffers (max is %d)", kMaxBufferCount); + return kTfLiteError; + } + buffer_offsets_[current_buffer_count_] = next_free_offset_; + next_free_offset_ += size; + ++current_buffer_count_; + return kTfLiteOk; +} + +size_t LinearMemoryPlanner::GetMaximumMemorySize() { return next_free_offset_; } + +int LinearMemoryPlanner::GetBufferCount() { return current_buffer_count_; } + +TfLiteStatus LinearMemoryPlanner::GetOffsetForBuffer(int buffer_index, + int* offset) { + if ((buffer_index < 0) || (buffer_index >= current_buffer_count_)) { + MicroPrintf("buffer index %d is outside range 0 to %d", buffer_index, + current_buffer_count_); + return kTfLiteError; + } + *offset = buffer_offsets_[buffer_index]; + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/linear_memory_planner.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/linear_memory_planner.h new file mode 100644 index 0000000..f699f8b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/linear_memory_planner.h @@ -0,0 +1,49 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_LINEAR_MEMORY_PLANNER_H_ +#define TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_LINEAR_MEMORY_PLANNER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h" + +namespace tflite { + +// The simplest possible memory planner that just lays out all buffers at +// increasing offsets without trying to reuse memory. +class LinearMemoryPlanner : public MicroMemoryPlanner { + public: + LinearMemoryPlanner(); + ~LinearMemoryPlanner() override; + + TfLiteStatus AddBuffer(int size, int first_time_used, + int last_time_used) override; + + size_t GetMaximumMemorySize() override; + int GetBufferCount() override; + TfLiteStatus GetOffsetForBuffer(int buffer_index, int* offset) override; + + private: + static constexpr int kMaxBufferCount = 1024; + size_t buffer_offsets_[kMaxBufferCount]; + int current_buffer_count_; + size_t next_free_offset_; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_LINEAR_MEMORY_PLANNER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/memory_plan_struct.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/memory_plan_struct.h new file mode 100644 index 0000000..5f3b7ef --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/memory_plan_struct.h @@ -0,0 +1,73 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_MEMORY_PLAN_STRUCT_H_ +#define TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_MEMORY_PLAN_STRUCT_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +// This is an experimental feature and subjected to change. +// More description is available at +// tensorflow/lite/micro/docs/offline_memory_plan.md. + +// Describes a buffer's layout inside an arena. This struct should be kept as +// small as possible for memory footprint sensitive applications and should use +// only primitive fields, making it easy to adjust offline. +struct BufferDescriptor { + // Starting offset inside an arena for this buffer. + // Offset is the minimum information needed for the buffer. The user knows + // the model and the size of each buffer in order to lay out a valid buffer + // plan. + int32_t offset; +}; + +// A structure describing the lay out of buffers inside an arena. +struct BufferPlan { + // Number of buffers described in this plan. + int32_t buffer_count; + + // Each element describes one buffer. + // Buffer index is implicit by the order of AddBuffer() call. + // Specifically, indices of activation tensors are 0 … N-1 where N is the + // number of activation tensors. + // The rest are based on the order of OP requests. + // + // This is a flexible array member and should ideally be + // arena_entries[]; However, in order to support a variety + // of compilers (and without needing to add ifdef's), we + // are implementing the flexible array member with an array of + // length 1 as the last member of the struct. When the size of a BufferPlan + // is needed, use the provided SizeOfBufferPlan(buffer_count) that + // accounts for this implemenatation caveat. + BufferDescriptor buffer_plan_entries[1]; +}; + +// Returns size of a BufferPlan given a buffer count. This size is compile time +// known if buffer_count is a compile time constant. +constexpr size_t SizeOfBufferPlan(int32_t buffer_count) { + // Minus 1 because a BufferPlan struct have a BufferDescriptor already. + // Max to provide a lower bound for the corner case of buffer_count = 0. + return sizeof(BufferPlan) + + sizeof(BufferDescriptor) * Max(buffer_count - 1, 0); +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_MEMORY_PLAN_STRUCT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h new file mode 100644 index 0000000..0d0d74f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h @@ -0,0 +1,91 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MICRO_MEMORY_PLANNER_MEMORY_PLANNER_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_MEMORY_PLANNER_MEMORY_PLANNER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +// Interface class for planning the layout of memory buffers during the +// execution of a graph. +// It's designed to be used by a client that iterates in any order through the +// buffers it wants to lay out, and then calls the getter functions for +// information about the calculated layout. For example: +// +// SomeMemoryPlanner planner; +// planner.AddBuffer(100, 0, 1); // Buffer 0 +// planner.AddBuffer(50, 2, 3); // Buffer 1 +// planner.AddBuffer(50, 2, 3); // Buffer 2 +// +// int offset0; +// TF_EXPECT_OK(planner.GetOffsetForBuffer(0, &offset0)); +// int offset1; +// TF_EXPECT_OK(planner.GetOffsetForBuffer(1, &offset1)); +// int offset2; +// TF_EXPECT_OK(planner.GetOffsetForBuffer(2, &offset2)); +// const int arena_size_needed = planner.GetMaximumMemorySize(); +// +// The goal is for applications to be able to experiment with different layout +// strategies without changing their client code, by swapping out classes that +// implement this interface.= +class MicroMemoryPlanner { + public: + MicroMemoryPlanner() {} + virtual ~MicroMemoryPlanner() {} + + // Pass information about a buffer's size and lifetime to the layout + // algorithm. The order this is called implicitly assigns an index to the + // result, so the buffer information that's passed into the N-th call of + // this method will be used as the buffer_index argument to + // GetOffsetForBuffer(). + virtual TfLiteStatus AddBuffer(int size, int first_time_used, + int last_time_used) = 0; + + // Record details of an offline planned buffer offset we want to place. + // offline_offset is the buffer offset from the start of the arena. + // This is to support offline memory planning from the flatbuffer metadata. + // By default, it returns an error. + virtual TfLiteStatus AddBuffer(int size, int first_time_used, + int last_time_used, int offline_offset) { + return kTfLiteError; + } + + // The largest contiguous block of memory that's needed to hold the layout. + virtual size_t GetMaximumMemorySize() = 0; + // How many buffers have been added to the planner. + virtual int GetBufferCount() = 0; + // Calculated layout offset for the N-th buffer added to the planner. + virtual TfLiteStatus GetOffsetForBuffer(int buffer_index, int* offset) = 0; + + // Provides the scratch buffer in case that the memory planner needs it. + // The lifetime of scratch buffers lifetime lasts until the static memory plan + // is committed. + // The default implementation is for the memory planner that does not need + // scratch buffer and simply returns ok. + virtual TfLiteStatus Init(unsigned char* scratch_buffer, + int scratch_buffer_size) { + return kTfLiteOk; + } + + virtual void PrintMemoryPlan() { + // Default does nothing. + } +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_MEMORY_PLANNER_MEMORY_PLANNER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.cpp new file mode 100644 index 0000000..0c1fd6d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.cpp @@ -0,0 +1,66 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +NonPersistentMemoryPlannerShim::NonPersistentMemoryPlannerShim( + const BufferPlan* buffer_plan) + : buffer_plan_(buffer_plan), buffer_request_count_(0) {} + +NonPersistentMemoryPlannerShim::~NonPersistentMemoryPlannerShim() {} + +TfLiteStatus NonPersistentMemoryPlannerShim::AddBuffer(int size, + int first_time_used, + int last_time_used) { + buffer_request_count_++; + if (buffer_request_count_ > buffer_plan_->buffer_count) { + MicroPrintf( + "Attempting to add buffer %d, but only %d buffers in given buffer " + "plan.", + buffer_request_count_, buffer_plan_->buffer_count); + return kTfLiteError; + } + return kTfLiteOk; +} + +size_t NonPersistentMemoryPlannerShim::GetMaximumMemorySize() { + // Simply return 0 to let the framework accept this memory plan + // because the client ensure validity of the memory plan. + return 0; +} + +// How many buffers are in the given memory plan. +int NonPersistentMemoryPlannerShim::GetBufferCount() { + return buffer_plan_->buffer_count; +} + +TfLiteStatus NonPersistentMemoryPlannerShim::GetOffsetForBuffer( + int buffer_request_index, int* offset) { + if (buffer_request_index >= buffer_plan_->buffer_count) { + MicroPrintf( + "Attempting to get offset for buffer %d, but only %d buffers in given " + "buffer plan.", + buffer_request_index, buffer_plan_->buffer_count); + return kTfLiteError; + } + *offset = buffer_plan_->buffer_plan_entries[buffer_request_index].offset; + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.h new file mode 100644 index 0000000..291c678 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.h @@ -0,0 +1,129 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_NON_PERSISTENT_MEMORY_PLANNER_SHIM_H__ +#define TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_NON_PERSISTENT_MEMORY_PLANNER_SHIM_H__ + +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/memory_plan_struct.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h" + +namespace tflite { + +/* This is an experimental feature and subjected to change. + * +The NonPersistentMemoryPlannerShim enables TFLM to work with an external tooling +that can plan the offset of each non persistent buffer for the Model within the +TFLM arena. + +If the NonPersistentMemoryPlannerShim is used, then the final binary does not +have any of the symbols associated with the GreedyMemoryPlanner which results in +a reduced memory footprint. + +Additionally, the offline planning of the non-persistent buffers can be used to +have a more efficient utilization compared to the GreedyMemoryPlanner. + +For example, consider the following hypothetical model: + +A1(400) A2(401) +──┬─────────┐ ┌─────────── + │ │ │ + │ │ │ + │ ▼ ▼ + │ ┌────────┐ + │ │ OP1 │ + │ └───┬────┘ A4(201) + │ A3(10) │ │ + │ │ │ + │ │ │ + │ ┌───┴────┐ │ + │ │ OP2 │◄────────┤ + │ └───┬────┘ │ + │ A5(11) │ A6(202) │ + │ │ │ │ + │ ▼ │ │ + │ ┌────────┐ │ │ + │ │ OP3 │◄─┘ │ + │ └───┬────┘ │ + │ │ A8(200) │ + │ A7(12) │ │ │ + │ │ │ │ + │ ┌───┴────┐◄──┘ │ + └──────►│ OP4 │ │ + └───┬────┘◄────────┘ + │ + A9(13) │ + ▼ + +The GreedyMemoryPlanner will give the following memory layout that requires 1012 +bytes of scratch arena size: + +┌─────────────────────────────────────────┬──────────────────────────┬────────┬───────┐ +│ A2(401) │ A1(400) │ A4(201)│ +A3(10)│ +└─────────────────────────────────────────┴──────────────────────────┴────────┴───────┘ + +┌───────────┬──────┬──────┐ +│ A6(202) │A5(11)│A7(12)│ +└───────────┴──────┴──────┘ + +┌──────────┬───────┐ +│ A8(200) │A9(13) │ +└──────────┴───────┘ + +But a more efficient offline memory plan that requires only 826 bytes of scratch +arena size can be + +┌──────────────────────────────────────┬─────────────────────────────┬───────┬──────┐ +│ A1(400) │ A2(401) │ +A3(10)│A5(11)│ +└──────────────────────────────────────┴─────────────────────────────┴───────┴──────┘ + + ┌────────────────┬────────────┬────────┬───────┐ + │A4(201) │ A8(200) │A9(13) +│A7(12) │ └────────────────┴────────────┴────────┴───────┘ + + ┌─────────────┐ + │ A6(202) │ + └─────────────┘ + +*/ +class NonPersistentMemoryPlannerShim : public MicroMemoryPlanner { + public: + // Does not take ownership of buffer_plan, which must refer to a valid + // BufferPlan that outlives this object. + explicit NonPersistentMemoryPlannerShim(const BufferPlan* buffer_plan); + ~NonPersistentMemoryPlannerShim() override; + + TfLiteStatus GetOffsetForBuffer(int buffer_request_index, + int* offset) override; + + TfLiteStatus AddBuffer(int size, int first_time_used, + int last_time_used) override; + size_t GetMaximumMemorySize() override; + int GetBufferCount() override; + + private: + const BufferPlan* buffer_plan_; // not owned, can't be null + + // The number of buffers requested so far. Used for error checking. + int buffer_request_count_; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MEMORY_PLANNER_NON_PERSISTENT_MEMORY_PLANNER_SHIM_H__ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.cpp new file mode 100644 index 0000000..296a502 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.cpp @@ -0,0 +1,375 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +namespace { +constexpr char kOfflineMemAllocMetadata[] = "OfflineMemoryAllocation"; +constexpr int kUninitializedLifetime = -1; +} // namespace + +// Mark the given Allocation info as first created at the specified allocation +// scope count. Only the first creation must be recorded since the allocation +// scope count monotonically increases throughout the lifetime marking process. +void AllocationInfoBuilder::UpdateFirstCreated(AllocationInfo* current, + int allocation_scope_count) { + TFLITE_DCHECK(current->first_created <= allocation_scope_count); + if (current->first_created == kUninitializedLifetime) { + current->first_created = allocation_scope_count; + } +} + +// Mark the given AllocationInfo as last used at the specified allocation scope +// count. Update the last used marker every time, since the allocation scope +// count monotonically increases through the lifetime marking process. +void AllocationInfoBuilder::UpdateLastUsed(AllocationInfo* current, + int allocation_scope_count) { + TFLITE_DCHECK(current->last_used <= allocation_scope_count); + current->last_used = allocation_scope_count; +} + +TfLiteStatus AllocationInfoBuilder::MarkSubgraphLifetimesIfNecessary( + const Operator* op, internal::ScratchBufferRequest* scratch_buffer_requests, + ScratchBufferHandle* scratch_buffer_handles, + SubgraphAllocations* allocations) { + int first_subgraph_index = -1; + int second_subgraph_index = -1; + const OperatorCode* opcode = + model_->operator_codes()->Get(op->opcode_index()); + switch (opcode->builtin_code()) { + case BuiltinOperator_IF: { + first_subgraph_index = + op->builtin_options_as_IfOptions()->then_subgraph_index(); + second_subgraph_index = + op->builtin_options_as_IfOptions()->else_subgraph_index(); + break; + } + case BuiltinOperator_CALL_ONCE: { + first_subgraph_index = + op->builtin_options_as_CallOnceOptions()->init_subgraph_index(); + break; + } + case BuiltinOperator_WHILE: { + first_subgraph_index = + op->builtin_options_as_WhileOptions()->cond_subgraph_index(); + second_subgraph_index = + op->builtin_options_as_WhileOptions()->body_subgraph_index(); + break; + } + default: { + break; + } + } + if (first_subgraph_index != -1) { + // Enter a new allocation scope for each subgraph. + allocation_scope_count_++; + TF_LITE_ENSURE_STATUS( + MarkAllocationLifetimes(first_subgraph_index, scratch_buffer_requests, + scratch_buffer_handles, allocations)); + } + if (second_subgraph_index != -1) { + // Enter a new allocation scope for each subgraph. + allocation_scope_count_++; + TF_LITE_ENSURE_STATUS( + MarkAllocationLifetimes(second_subgraph_index, scratch_buffer_requests, + scratch_buffer_handles, allocations)); + } + return kTfLiteOk; +} + +TfLiteStatus AllocationInfoBuilder::CreateAllocationInfo( + int scratch_buffer_request_count) { + size_t subgraph_offsets_length = model_->subgraphs()->size() * sizeof(size_t); + info_.subgraph_offsets = + reinterpret_cast(non_persistent_allocator_->AllocateTemp( + subgraph_offsets_length, alignof(size_t))); + if (info_.subgraph_offsets == nullptr) { + MicroPrintf( + "Failed to allocate memory for memory planning, %d bytes required", + subgraph_offsets_length); + return kTfLiteError; + } + size_t tensor_count = 0; + for (size_t subgraph_idx = 0; subgraph_idx < model_->subgraphs()->size(); + subgraph_idx++) { + // Add all tensors in each subgraph to the AllocationInfo array. Even weight + // tensors are added but marked with needs_allocating = false. Including all + // tensors in the graph here simplifies logic. + info_.subgraph_offsets[subgraph_idx] = tensor_count; + tensor_count += model_->subgraphs()->Get(subgraph_idx)->tensors()->size(); + } + info_.tensor_count = tensor_count; + + // Scratch buffer allocations follow tensor allocations, so the scratch offset + // is equal to the number of tensor allocations. + info_.scratch_offset = tensor_count; + info_.allocation_info_count = tensor_count + scratch_buffer_request_count; + info_.scratch_buffer_count = scratch_buffer_request_count; + size_t bytes = sizeof(AllocationInfo) * info_.allocation_info_count; + + // Allocate an array of AllocationInfo structs from the temp section. This + // struct will be used by AllocationInfoBuilder to find buffer usage. + info_.allocation_info = reinterpret_cast( + non_persistent_allocator_->AllocateTemp(bytes, alignof(AllocationInfo))); + if (info_.allocation_info == nullptr) { + MicroPrintf( + "Failed to allocate memory for memory planning, %d bytes required", + bytes); + return kTfLiteError; + } + return kTfLiteOk; +} + +TfLiteStatus AllocationInfoBuilder::FreeAllocationInfo() { + non_persistent_allocator_->DeallocateTemp( + reinterpret_cast(info_.allocation_info)); + non_persistent_allocator_->DeallocateTemp( + reinterpret_cast(info_.subgraph_offsets)); + return kTfLiteOk; +} + +TfLiteStatus AllocationInfoBuilder::ValidateSubgraph( + const SubGraph* subgraph, TfLiteEvalTensor* eval_tensors) { + uint32_t operators_size = NumSubgraphOperators(subgraph); + + for (uint32_t i = 0; i < operators_size; i++) { + const auto op = subgraph->operators()->Get(i); + for (size_t n = 0; + op->intermediates() != nullptr && n < op->intermediates()->size(); + n++) { + const int tensor_index = op->intermediates()->Get(n); + size_t tensor_size = -1; + TF_LITE_ENSURE_STATUS(TfLiteEvalTensorByteLength( + &eval_tensors[tensor_index], &tensor_size)); + if (tensor_size != 0) { + MicroPrintf( + "Does not support intermediate tensor with non-zero size: %d", + tensor_size); + return kTfLiteError; + } + } + } + return kTfLiteOk; +} + +TfLiteStatus AllocationInfoBuilder::InitializeAllocationInfo( + const int32_t* offline_offsets, SubgraphAllocations* allocations) { + AllocationInfo* allocation_info = info_.allocation_info; + // Initialize allocation info for every tensor in every subgraph. + for (size_t subgraph_idx = 0; subgraph_idx < model_->subgraphs()->size(); + subgraph_idx++) { + const SubGraph* subgraph = model_->subgraphs()->Get(subgraph_idx); + TfLiteEvalTensor* eval_tensors = allocations[subgraph_idx].tensors; + AllocationInfo* subgraph_allocation_info = + &allocation_info[info_.subgraph_offsets[subgraph_idx]]; + + // Ensure constraints are met. + TF_LITE_ENSURE_STATUS(ValidateSubgraph(subgraph, eval_tensors)); + + for (size_t i = 0; i < subgraph->tensors()->size(); ++i) { + AllocationInfo* current = &subgraph_allocation_info[i]; + current->output_ptr = &(eval_tensors[i].data.data); + + TF_LITE_ENSURE_STATUS( + TfLiteEvalTensorByteLength(&eval_tensors[i], ¤t->bytes)); + + current->first_created = kUninitializedLifetime; + current->last_used = kUninitializedLifetime; + current->needs_allocating = + (eval_tensors[i].data.data == nullptr) && + (!subgraph->tensors()->Get(i)->is_variable()) && + (current->bytes != 0); + if (offline_offsets) { + current->offline_offset = offline_offsets[i]; + + // Mark offline planned variable tensors so they can get an offline + // offset and be handled offline. + if (subgraph->tensors()->Get(i)->is_variable() && + current->offline_offset != kOnlinePlannedBuffer) { + current->needs_allocating = true; + } + + } else { + current->offline_offset = kOnlinePlannedBuffer; + } + } + } + // Initialize allocation info for every scratch buffer. + AllocationInfo* scratch_allocation_info = + &allocation_info[info_.scratch_offset]; + for (size_t i = 0; i < info_.scratch_buffer_count; i++) { + AllocationInfo* current = &scratch_allocation_info[i]; + current->first_created = kUninitializedLifetime; + current->last_used = kUninitializedLifetime; + current->needs_allocating = true; + current->offline_offset = kOnlinePlannedBuffer; + } + return kTfLiteOk; +} + +TfLiteStatus AllocationInfoBuilder::MarkAllocationLifetimes( + int subgraph_idx, internal::ScratchBufferRequest* scratch_buffer_requests, + ScratchBufferHandle* scratch_buffer_handles, + SubgraphAllocations* allocations) { + const SubGraph* subgraph = model_->subgraphs()->Get(subgraph_idx); + + AllocationInfo* allocation_info = info_.allocation_info; + // Each subgraph's tensor allocations are in a contiguous block starting at + // subgraph_offsets_[subgraph index] with one entry per tensor. + AllocationInfo* subgraph_allocation_info = + &allocation_info[info_.subgraph_offsets[subgraph_idx]]; + + uint32_t operators_size = NumSubgraphOperators(subgraph); + // Mark all inputs as created at the start of the subgraph invocation. + for (size_t i = 0; + subgraph->inputs() != nullptr && i < subgraph->inputs()->size(); ++i) { + const int tensor_index = subgraph->inputs()->Get(i); + AllocationInfo* current = &subgraph_allocation_info[tensor_index]; + UpdateFirstCreated(current, allocation_scope_count_); + // This will ensure that the tensors that are inputs to the subgraphs + // but not used in any ops also have a reasonable lifetime. + UpdateLastUsed(current, allocation_scope_count_); + } + + for (uint32_t i = 0; i < operators_size; i++) { + // Each operator has a new allocation scope. + allocation_scope_count_++; + const auto* op = subgraph->operators()->Get(i); + // Figure out when the first creation and use of each tensor is. + for (size_t n = 0; op->outputs() != nullptr && n < op->outputs()->size(); + ++n) { + const int tensor_index = op->outputs()->Get(n); + AllocationInfo* current = &subgraph_allocation_info[tensor_index]; + UpdateFirstCreated(current, allocation_scope_count_); + } + + // Keep track of scope count before any subgraphs, so that scratch buffers' + // lifetime within a control flow op properly overlaps with all subgraphs. + int start_allocation_scope_count = allocation_scope_count_; + + // Control flow operators can invoke subgraphs. Plan these subgraphs + // before continuing on to the rest of the graph. + MarkSubgraphLifetimesIfNecessary(op, scratch_buffer_requests, + scratch_buffer_handles, allocations); + + // Figure out when the last use of each tensor is. + for (size_t n = 0; op->inputs() != nullptr && n < op->inputs()->size(); + ++n) { + const int tensor_index = op->inputs()->Get(n); + // Optional bias tensors can have an index of -1 when they are omitted. + if (tensor_index >= 0) { + AllocationInfo* current = &subgraph_allocation_info[tensor_index]; + // No need to update creation since it is either marked by the subgraph + // or producer op, or it is not part of the memory plan (weight, bias + // tensor). + UpdateLastUsed(current, allocation_scope_count_); + } + } + for (size_t n = 0; op->outputs() != nullptr && n < op->outputs()->size(); + ++n) { + const int tensor_index = op->outputs()->Get(n); + AllocationInfo* current = &subgraph_allocation_info[tensor_index]; + UpdateLastUsed(current, allocation_scope_count_); + } + + // Mark thse lifetime of scratch buffers belonging to the current node. This + // operation is O(N * M) where N is the total number of visited nodes and M + // is the total number of scratch buffers. + // TODO(b/217794030): Optimize this memory planning code. + AllocationInfo* scratch_allocation_info = + &allocation_info[info_.scratch_offset]; + for (size_t scratch_idx = 0; scratch_idx < info_.scratch_buffer_count; + scratch_idx++) { + internal::ScratchBufferRequest request = + scratch_buffer_requests[scratch_idx]; + AllocationInfo* current = &scratch_allocation_info[scratch_idx]; + if (request.node_idx == static_cast(i) && + request.subgraph_idx == static_cast(subgraph_idx)) { + ScratchBufferHandle* current_handle = + &(scratch_buffer_handles[scratch_idx]); + current->output_ptr = reinterpret_cast(¤t_handle->data); + current->bytes = request.bytes; + UpdateFirstCreated(current, start_allocation_scope_count); + UpdateLastUsed(current, allocation_scope_count_); + } + } + } + + // Mark all outputs as persistent to the end of the subgraph invocation. + for (size_t i = 0; + subgraph->outputs() != nullptr && i < subgraph->outputs()->size(); ++i) { + const int tensor_index = subgraph->outputs()->Get(i); + AllocationInfo* current = &subgraph_allocation_info[tensor_index]; + // Make sure to assign the First created value of the subgraph output + // This will handle the case where the subgraph is empty. This helps + // ensure all tensors have valid lifetimes before those are used by the + // memory planner. + UpdateFirstCreated(current, allocation_scope_count_); + UpdateLastUsed(current, allocation_scope_count_); + } + return kTfLiteOk; +} + +// Get offline tensors allocation plan. See +// micro/docs/memory_management.md for more info. +TfLiteStatus AllocationInfoBuilder::GetOfflinePlannedOffsets( + const int32_t** offline_planner_offsets) { + if (model_->metadata()) { + for (size_t i = 0; i < model_->metadata()->size(); ++i) { + auto metadata = model_->metadata()->Get(i); + + if (metadata->name()) { + const size_t metadata_name_size = metadata->name()->size(); + + if ((strncmp(metadata->name()->c_str(), kOfflineMemAllocMetadata, + std::min(metadata_name_size, + strlen(kOfflineMemAllocMetadata))) == 0) && + metadata_name_size == strlen(kOfflineMemAllocMetadata)) { + const flatbuffers::Vector>* buffers = + model_->buffers(); + auto* buffer = (*buffers)[metadata->buffer()]; + auto* array = buffer->data(); + const uint32_t* metadata_buffer = + reinterpret_cast(array->data()); + const size_t nbr_tensors = static_cast(metadata_buffer[2]); + *offline_planner_offsets = + reinterpret_cast(&metadata_buffer[3]); + + if (info_.tensor_count != nbr_tensors) { + MicroPrintf( + "Nbr of offline buffer offsets (%d) in metadata " + "not equal nbr tensors (%d)\n", + nbr_tensors, info_.tensor_count); + return kTfLiteError; + } + } + } + } + } + return kTfLiteOk; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.h new file mode 100644 index 0000000..a02503e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.h @@ -0,0 +1,139 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_ALLOCATION_INFO_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_ALLOCATION_INFO_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h" + +namespace tflite { + +// Used to hold information used during allocation calculations. +struct AllocationInfo { + size_t bytes; + void** output_ptr; + int first_created; + int last_used; + int32_t offline_offset; + bool needs_allocating; +}; + +// Used to hold the allocation info list and related metadata for the entire +// graph (including subgraphs). Since all subgraphs are planned together, the +// allocation info list contains allocations for all subgraphs. Track the offset +// into this list for each subgraph then reserve space to track all allocations. +// +// The AllocationInfo list is a contiguous list of allocations across all +// subgraphs and scratch buffers. Each element here is marked as +// st. The following is a possible +// AllocationInfo list: +// [s0t0, s0t1, s1t0, s2t1, s1t2, s3t0, s3t1, scratch0, scratch1, scratch2] +// +// For this example, the subgraph offsets would be [0, 2, 5] and the scratch +// offset would be 7. +struct GraphAllocationInfo { + AllocationInfo* allocation_info; + size_t allocation_info_count; + size_t* subgraph_offsets; + size_t scratch_offset; + size_t tensor_count; + size_t scratch_buffer_count; +}; + +// A helper class to construct AllocationInfo array. This array contains the +// lifetime of tensors / scratch_buffer and will be used to calculate the memory +// plan. Methods need to be called in order from `Create`, Init`, `Add*`, to +// `Finish`. +class AllocationInfoBuilder { + public: + AllocationInfoBuilder(const Model* model, + INonPersistentBufferAllocator* non_persistent_allocator) + : model_(model), non_persistent_allocator_(non_persistent_allocator) {} + + // Check if model contains offline planned buffer offsets. + // - If there's no metadata available, offline_planner_offsets is not set + // - If there's metadata available, offline_planner_offsets will point to the + // first offset in the metadata buffer list. + TfLiteStatus GetOfflinePlannedOffsets( + const int32_t** offline_planner_offsets); + + // Allocate memory for the allocation info array as well as offsets into that + // array for each subgraph. + TfLiteStatus CreateAllocationInfo(int scratch_buffer_request_count); + + // Release memory used for the allocation info array. + TfLiteStatus FreeAllocationInfo(); + + // Initialize AllocationInfo for all tensors and scratch buffers in the graph. + TfLiteStatus InitializeAllocationInfo(const int32_t* offline_offsets, + SubgraphAllocations* allocations); + + // Mark the scope of each tensor and scratch buffer across the graph. Enter + // all possible subgraphs invoked by each control flow operator. This method + // marks the maximum lifetime of each buffer so that tensors are correctly + // planned for all valid invocation flows. + TfLiteStatus MarkAllocationLifetimes( + int subgraph_idx, internal::ScratchBufferRequest* scratch_buffer_request, + ScratchBufferHandle* scratch_buffer_handles, + SubgraphAllocations* allocations); + + // Identify control flow operators and recursively mark all subgraphs which + // that operator can invoke. The lifetime of all tensors within a subgraph + // can only be extended. The order of subgraph invocation does not matter + // since subgraphs within the same control flow operator are executed + // within their own allocation scope (planned buffers in a subgraph cannot + // persist beyond the end of that subgraph's invocation). + TfLiteStatus MarkSubgraphLifetimesIfNecessary( + const Operator* op, + internal::ScratchBufferRequest* scratch_buffer_requests, + ScratchBufferHandle* scratch_buffer_handles, + SubgraphAllocations* allocations); + + // Returns the number of allocations. + int AllocationCount() const { return info_.allocation_info_count; } + + // Returns a pointer to the built AllocationInfo array. + AllocationInfo* Finish() const { return info_.allocation_info; } + + private: + // Mark the given Allocation info as first created at the specified allocation + // scope count. Only the first creation must be recorded since the allocation + // scope count monotonically increases throughout the lifetime marking + // process. + void UpdateFirstCreated(AllocationInfo* current, int allocation_scope_count); + + // Mark the given AllocationInfo as last used at the specified allocation + // scope + // count. Update the last used marker every time, since the allocation scope + // count monotonically increases through the lifetime marking process. + void UpdateLastUsed(AllocationInfo* current, int allocation_scope_count); + + // Validate if a subgraph satisfies assumptions. + TfLiteStatus ValidateSubgraph(const SubGraph* subgraph, + TfLiteEvalTensor* eval_tensors); + + const tflite::Model* model_ = nullptr; + INonPersistentBufferAllocator* non_persistent_allocator_ = nullptr; + GraphAllocationInfo info_; + int allocation_scope_count_ = 0; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_ALLOCATION_INFO_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.cpp new file mode 100644 index 0000000..872cb06 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.cpp @@ -0,0 +1,941 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" + +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocation_info.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_arena_constants.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h" + +namespace tflite { + +namespace { + +// Maximum number of scratch buffer requests per operator. Operator kernels that +// request more than this value will receive an exception. +constexpr size_t kMaxScratchBuffersPerOp = 12; + +// Sentinel value used as a placeholder to mark a ScratchBufferRequest request +// needs a node id assignment. +constexpr int kUnassignedScratchBufferRequestIndex = -1; + +const TfLiteIntArray kZeroLengthIntArray = {}; + +class MicroBuiltinDataAllocator : public TfLiteBridgeBuiltinDataAllocator { + public: + explicit MicroBuiltinDataAllocator( + IPersistentBufferAllocator* persistent_allocator) + : persistent_allocator_(persistent_allocator) {} + + void* Allocate(size_t size, size_t alignment_hint) override { + return persistent_allocator_->AllocatePersistentBuffer(size, + alignment_hint); + } + void Deallocate(void* data) override { + // Do not deallocate, builtin data needs to be available for the life time + // of the model. + } + + TF_LITE_REMOVE_VIRTUAL_DELETE + + private: + IPersistentBufferAllocator* persistent_allocator_; +}; + +TfLiteStatus CreatePlan(MicroMemoryPlanner* planner, + const AllocationInfo* allocation_info, + size_t allocation_info_size) { + // Add the tensors to our allocation plan. + for (size_t i = 0; i < allocation_info_size; ++i) { + const AllocationInfo* current = &allocation_info[i]; + if (current->needs_allocating) { + size_t aligned_bytes_required = + AlignSizeUp(current->bytes, MicroArenaBufferAlignment()); + if (current->offline_offset == kOnlinePlannedBuffer) { + TF_LITE_ENSURE_STATUS(planner->AddBuffer(aligned_bytes_required, + current->first_created, + current->last_used)); + } else { + TF_LITE_ENSURE_STATUS( + planner->AddBuffer(aligned_bytes_required, current->first_created, + current->last_used, current->offline_offset)); + } + } + } + return kTfLiteOk; +} + +TfLiteStatus CommitPlan(MicroMemoryPlanner* planner, uint8_t* starting_point, + const AllocationInfo* allocation_info, + size_t allocation_info_size) { + // Figure out the actual memory addresses for each buffer, based on the plan. + int planner_index = 0; + for (size_t i = 0; i < allocation_info_size; ++i) { + const AllocationInfo* current = &allocation_info[i]; + if (current->needs_allocating) { + int offset = -1; + TF_LITE_ENSURE_STATUS( + planner->GetOffsetForBuffer(planner_index, &offset)); + *current->output_ptr = reinterpret_cast(starting_point + offset); + ++planner_index; + } + } + return kTfLiteOk; +} + +IPersistentBufferAllocator* CreatePersistentArenaAllocator(uint8_t* buffer_head, + size_t buffer_size) { + // Align the actually used area by the tail because persistent buffer grows + // from the bottom to top. + uint8_t* aligned_buffer_tail = + AlignPointerDown(buffer_head + buffer_size, MicroArenaBufferAlignment()); + size_t aligned_buffer_size = aligned_buffer_tail - buffer_head; + PersistentArenaBufferAllocator tmp = + PersistentArenaBufferAllocator(buffer_head, aligned_buffer_size); + + // Allocate enough bytes from the buffer to create a + // SingleArenaBufferAllocator. The new instance will use the current adjusted + // tail buffer from the tmp allocator instance. + uint8_t* allocator_buffer = + tmp.AllocatePersistentBuffer(sizeof(PersistentArenaBufferAllocator), + alignof(PersistentArenaBufferAllocator)); + // Use the default copy constructor to populate internal states. + return new (allocator_buffer) PersistentArenaBufferAllocator(tmp); +} + +// NonPersistentBufferAllocator instance is created in the persistent buffer +// because it has to be persistent to keep track of the non-persistent buffer +// information. +INonPersistentBufferAllocator* CreateNonPersistentArenaAllocator( + uint8_t* buffer_head, size_t buffer_size, + IPersistentBufferAllocator* persistent_buffer_allocator) { + uint8_t* allocator_buffer = + persistent_buffer_allocator->AllocatePersistentBuffer( + sizeof(NonPersistentArenaBufferAllocator), + alignof(NonPersistentArenaBufferAllocator)); + // Align the actually used area by the head because persistent buffer grows + // from the head to bottom. + uint8_t* aligned_buffer_head = + AlignPointerUp(buffer_head, MicroArenaBufferAlignment()); + size_t aligned_buffer_size = buffer_head + buffer_size - aligned_buffer_head; + + INonPersistentBufferAllocator* non_persistent_buffer_allocator = + new (allocator_buffer) NonPersistentArenaBufferAllocator( + aligned_buffer_head, aligned_buffer_size); + return non_persistent_buffer_allocator; +} + +} // namespace + +namespace internal { + +// Returns a pointer to any buffer associated with the flatbuffer tensor. Can +// return nullptr if no buffer is found. +void* GetFlatbufferTensorBuffer( + const tflite::Tensor& flatbuffer_tensor, + const flatbuffers::Vector>* buffers) { + // We need to figure out where the actual contents of this tensor are stored + // in memory. We'll check to see if there's a serialized buffer (pretty much + // the same as a constant op in TensorFlow) associated with this tensor first, + // and if there is update the runtime structure to point to its location in + // memory. + // First see if there's any buffer information in the serialized tensor. + // TODO(b/170379532): Add better unit tests to validate flatbuffer values. + void* out_buffer = nullptr; + if (auto* buffer = (*buffers)[flatbuffer_tensor.buffer()]) { + // If we've found a buffer, does it have any data? + if (auto* array = buffer->data()) { + // If it has any data, is the data size larger than zero? + if (array->size()) { + // We've found a buffer with valid data, so update the runtime tensor + // data structure to point to it. + out_buffer = const_cast(static_cast(array->data())); + } + } + // TODO(petewarden): It's not clear in what circumstances we could have a + // buffer in the serialized tensor, but it doesn't have any data in it. Is + // that a validly-generated file, and if so what does it mean, or is it an + // error condition? It would be good to tighten up the specification to make + // it less ambiguous. + } + return out_buffer; +} + +TfLiteStatus InitializeTfLiteTensorFromFlatbuffer( + IPersistentBufferAllocator* persistent_buffer_allocator, + INonPersistentBufferAllocator* non_persistent_buffer_allocator, + bool allocate_temp, const tflite::Tensor& flatbuffer_tensor, + const flatbuffers::Vector>* buffers, + TfLiteTensor* result) { + TFLITE_DCHECK(result != nullptr); + + *result = {}; + // Make sure the serialized type is one we know how to deal with, and convert + // it from a flatbuffer enum into a constant used by the kernel C API. + TF_LITE_ENSURE_STATUS( + tflite::ConvertTensorType(flatbuffer_tensor.type(), &result->type)); + // Make sure we remember if the serialized tensor is designated as a variable. + result->is_variable = flatbuffer_tensor.is_variable(); + + result->data.data = GetFlatbufferTensorBuffer(flatbuffer_tensor, buffers); + // this is useful for debugging +#if defined(EI_LOG_LEVEL) && (EI_LOG_LEVEL >= 4) + result->name = flatbuffer_tensor.name()->c_str(); +#endif + // TODO(petewarden): Some of these paths aren't getting enough testing + // coverage, so we should figure out some tests that exercise them. + if (result->data.data == nullptr) { + // The tensor contents haven't been set from a serialized buffer, so + // make a note that they will be allocated from memory. The actual + // allocation won't happen until later. + result->allocation_type = kTfLiteArenaRw; + } else { + // We set the data from a serialized buffer, so record tha. + result->allocation_type = kTfLiteMmapRo; + } + + // Figure out what the size in bytes of the buffer is and store it. + size_t type_size; + TF_LITE_ENSURE_STATUS( + BytesRequiredForTensor(flatbuffer_tensor, &result->bytes, &type_size)); + + if (flatbuffer_tensor.shape() == nullptr) { + // flatbuffer_tensor.shape() can return a nullptr in the case of a scalar + // tensor. + // TODO(b/188459715): figure out why const_cast is required here. + result->dims = const_cast(&kZeroLengthIntArray); + } else { + // TFLM doesn't allow reshaping the tensor which requires dynamic memory + // allocation so it is safe to drop the const qualifier. In the future, if + // we really want to update the tensor shape, we can always pass in a new + // TfLiteIntArray - especially we have to do so if the dimension is + result->dims = FlatBufferVectorToTfLiteTypeArray(flatbuffer_tensor.shape()); + } + + // Copy the quantization information from the serialized data. + const auto* src_quantization = flatbuffer_tensor.quantization(); + if (src_quantization && src_quantization->scale() && + (src_quantization->scale()->size() > 0) && + src_quantization->zero_point() && + (src_quantization->zero_point()->size() > 0)) { + // Always populate the TfLiteTensor.params field, even if there are + // per-channel quantization parameters. + result->params.scale = src_quantization->scale()->Get(0); + // Note that the zero_point field in the FlatBuffers schema is a 64-bit + // integer, but the zero_point field in the TfLiteQuantizationParams struct + // is a 32-bit integer. + result->params.zero_point = + static_cast(src_quantization->zero_point()->Get(0)); + + // Populate per-channel quantization params. + int channels = src_quantization->scale()->size(); + TfLiteAffineQuantization* quantization = + allocate_temp + ? reinterpret_cast( + non_persistent_buffer_allocator->AllocateTemp( + sizeof(TfLiteAffineQuantization), + alignof(TfLiteAffineQuantization))) + : reinterpret_cast( + persistent_buffer_allocator->AllocatePersistentBuffer( + sizeof(TfLiteAffineQuantization), + alignof(TfLiteAffineQuantization))); + if (quantization == nullptr) { + MicroPrintf("Unable to allocate TfLiteAffineQuantization.\n"); + return kTfLiteError; + } + + // TODO(b/153688719): Reduce tail allocation by using a global zero-point + // buffer. This value can not be reused from the flatbuffer since the + // zero_point is stored as a int64_t. + quantization->zero_point = + allocate_temp + ? reinterpret_cast( + non_persistent_buffer_allocator->AllocateTemp( + TfLiteIntArrayGetSizeInBytes(channels), + alignof(TfLiteIntArray))) + : reinterpret_cast( + persistent_buffer_allocator->AllocatePersistentBuffer( + TfLiteIntArrayGetSizeInBytes(channels), + alignof(TfLiteIntArray))); + if (quantization->zero_point == nullptr) { + MicroPrintf("Unable to allocate quantization->zero_point.\n"); + return kTfLiteError; + } + + quantization->scale = + FlatBufferVectorToTfLiteTypeArray(src_quantization->scale()); + + quantization->zero_point->size = channels; + int* zero_point_data = quantization->zero_point->data; + for (int i = 0; i < channels; i++) { + // As a space-saving optimization, zero point arrays for weights can be + // reduced to a single value, since all zero points for weights are 0. + zero_point_data[i] = src_quantization->zero_point()->size() == + src_quantization->scale()->size() + ? src_quantization->zero_point()->Get(i) + : src_quantization->zero_point()->Get(0); + } + // TODO(rocky): Need to add a micro_allocator test case that fails when + // this is not copied: + quantization->quantized_dimension = src_quantization->quantized_dimension(); + + result->quantization = {kTfLiteAffineQuantization, quantization}; + } + return kTfLiteOk; +} + +TfLiteStatus InitializeTfLiteEvalTensorFromFlatbuffer( + const tflite::Tensor& flatbuffer_tensor, + const flatbuffers::Vector>* buffers, + TfLiteEvalTensor* result) { + *result = {}; + // Make sure the serialized type is one we know how to deal with, and convert + // it from a flatbuffer enum into a constant used by the kernel C API. + TF_LITE_ENSURE_STATUS( + tflite::ConvertTensorType(flatbuffer_tensor.type(), &result->type)); + + result->data.data = GetFlatbufferTensorBuffer(flatbuffer_tensor, buffers); + + if (flatbuffer_tensor.shape() == nullptr) { + // flatbuffer_tensor.shape() can return a nullptr in the case of a scalar + // tensor. + result->dims = const_cast(&kZeroLengthIntArray); + } else { + result->dims = FlatBufferVectorToTfLiteTypeArray(flatbuffer_tensor.shape()); + } + return kTfLiteOk; +} + +} // namespace internal + +size_t MicroAllocator::GetDefaultTailUsage(bool is_memory_planner_given) { + size_t total_size = AlignSizeUp() + + AlignSizeUp() + + AlignSizeUp() + + AlignSizeUp(); + if (!is_memory_planner_given) { + total_size += AlignSizeUp(); + } + return total_size; +} + +MicroAllocator::MicroAllocator(SingleArenaBufferAllocator* memory_allocator, + MicroMemoryPlanner* memory_planner) + : non_persistent_buffer_allocator_(memory_allocator), + persistent_buffer_allocator_(memory_allocator), + memory_planner_(memory_planner), + model_is_allocating_(false) {} + +MicroAllocator::MicroAllocator( + IPersistentBufferAllocator* persistent_buffer_allocator, + INonPersistentBufferAllocator* non_persistent_buffer_allocator, + MicroMemoryPlanner* memory_planner) + : non_persistent_buffer_allocator_(non_persistent_buffer_allocator), + persistent_buffer_allocator_(persistent_buffer_allocator), + memory_planner_(memory_planner), + model_is_allocating_(false) {} + +MicroAllocator::~MicroAllocator() {} + +MicroAllocator* MicroAllocator::Create(uint8_t* tensor_arena, size_t arena_size, + MicroMemoryPlanner* memory_planner) { + uint8_t* aligned_arena = + AlignPointerUp(tensor_arena, MicroArenaBufferAlignment()); + size_t aligned_arena_size = tensor_arena + arena_size - aligned_arena; + SingleArenaBufferAllocator* memory_allocator = + SingleArenaBufferAllocator::Create(aligned_arena, aligned_arena_size); + + return Create(memory_allocator, memory_planner); +} + +MicroAllocator* MicroAllocator::Create(uint8_t* tensor_arena, + size_t arena_size) { + uint8_t* aligned_arena = + AlignPointerUp(tensor_arena, MicroArenaBufferAlignment()); + size_t aligned_arena_size = tensor_arena + arena_size - aligned_arena; + SingleArenaBufferAllocator* memory_allocator = + SingleArenaBufferAllocator::Create(aligned_arena, aligned_arena_size); + + // By default create GreedyMemoryPlanner. + // If a different MemoryPlanner is needed, use the other api. + uint8_t* memory_planner_buffer = memory_allocator->AllocatePersistentBuffer( + sizeof(GreedyMemoryPlanner), alignof(GreedyMemoryPlanner)); + GreedyMemoryPlanner* memory_planner = + new (memory_planner_buffer) GreedyMemoryPlanner(); + + return Create(memory_allocator, memory_planner); +} + +MicroAllocator* MicroAllocator::Create( + SingleArenaBufferAllocator* memory_allocator, + MicroMemoryPlanner* memory_planner) { + TFLITE_DCHECK(memory_allocator != nullptr); + TFLITE_DCHECK(memory_planner != nullptr); + + uint8_t* allocator_buffer = memory_allocator->AllocatePersistentBuffer( + sizeof(MicroAllocator), alignof(MicroAllocator)); + MicroAllocator* allocator = new (allocator_buffer) + MicroAllocator(memory_allocator, memory_allocator, memory_planner); + return allocator; +} + +MicroAllocator* MicroAllocator::Create(uint8_t* persistent_tensor_arena, + size_t persistent_arena_size, + uint8_t* non_persistent_tensor_arena, + size_t non_persistent_arena_size) { + TFLITE_DCHECK(persistent_tensor_arena != nullptr); + TFLITE_DCHECK(non_persistent_tensor_arena != nullptr); + TFLITE_DCHECK(persistent_tensor_arena != non_persistent_tensor_arena); + + IPersistentBufferAllocator* persistent_buffer_allocator = + CreatePersistentArenaAllocator(persistent_tensor_arena, + persistent_arena_size); + INonPersistentBufferAllocator* non_persistent_buffer_allocator = + CreateNonPersistentArenaAllocator(non_persistent_tensor_arena, + non_persistent_arena_size, + persistent_buffer_allocator); + + uint8_t* memory_planner_buffer = + persistent_buffer_allocator->AllocatePersistentBuffer( + sizeof(GreedyMemoryPlanner), alignof(GreedyMemoryPlanner)); + GreedyMemoryPlanner* memory_planner = + new (memory_planner_buffer) GreedyMemoryPlanner(); + + uint8_t* micro_allocator_buffer = + persistent_buffer_allocator->AllocatePersistentBuffer( + sizeof(MicroAllocator), alignof(MicroAllocator)); + MicroAllocator* allocator = new (micro_allocator_buffer) + MicroAllocator(persistent_buffer_allocator, + non_persistent_buffer_allocator, memory_planner); + return allocator; +} + +SubgraphAllocations* MicroAllocator::StartModelAllocation(const Model* model) { + TFLITE_DCHECK(model != nullptr); + + if (model_is_allocating_) { + MicroPrintf( + "MicroAllocator: Model allocation started before " + "finishing previously allocated model"); + return nullptr; + } + + model_is_allocating_ = true; + + uint8_t* data_allocator_buffer = + persistent_buffer_allocator_->AllocatePersistentBuffer( + sizeof(MicroBuiltinDataAllocator), + alignof(MicroBuiltinDataAllocator)); + builtin_data_allocator_ = new (data_allocator_buffer) + MicroBuiltinDataAllocator(persistent_buffer_allocator_); + + if (InitScratchBufferData() != kTfLiteOk) { + return nullptr; + } + + // Allocate struct to store eval tensors, nodes and registrations. + SubgraphAllocations* output = reinterpret_cast( + persistent_buffer_allocator_->AllocatePersistentBuffer( + sizeof(SubgraphAllocations) * model->subgraphs()->size(), + alignof(SubgraphAllocations))); + if (output == nullptr) { + MicroPrintf("Failed to allocate memory for model metadata."); + return nullptr; + } + + if (AllocateTfLiteEvalTensors(model, output) != kTfLiteOk || + AllocateNodeAndRegistrations(model, output) != kTfLiteOk) { + return nullptr; + } + return output; +} + +TfLiteStatus MicroAllocator::FinishModelAllocation( + const Model* model, SubgraphAllocations* subgraph_allocations, + ScratchBufferHandle** scratch_buffer_handles) { + if (!model_is_allocating_) { + MicroPrintf( + "MicroAllocator: Model allocation finished before " + "starting allocating model"); + return kTfLiteError; + } + + // Allocate scratch buffer metadata. + TF_LITE_ENSURE_STATUS(AllocateScratchBufferHandles( + scratch_buffer_handles, scratch_buffer_request_count_)); + + // Plan all subgraphs and scratch buffers together. + TF_LITE_ENSURE_STATUS(CommitStaticMemoryPlan(model, subgraph_allocations, + *scratch_buffer_handles)); + model_is_allocating_ = false; + return kTfLiteOk; +} + +void* MicroAllocator::AllocatePersistentBuffer(size_t bytes) { + return persistent_buffer_allocator_->AllocatePersistentBuffer( + bytes, MicroArenaBufferAlignment()); +} + +TfLiteStatus MicroAllocator::RequestScratchBufferInArena(size_t bytes, + int subgraph_idx, + int* buffer_idx) { + // All scratch buffer requests are stored in the head section of the arena + // when a model is in the prepare phase. First align a scratch buffer request + // pointer to the start of the head: + internal::ScratchBufferRequest* requests = GetScratchBufferRequests(); + + // Count the number of requested scratch buffers for the current node: + size_t current_node_request_count = 0; + for (size_t i = 0; i < scratch_buffer_request_count_; ++i) { + if (requests[i].node_idx == kUnassignedScratchBufferRequestIndex) { + ++current_node_request_count; + } + } + + // First, ensure that the per-kernel request has not exceeded the limit: + if (current_node_request_count >= kMaxScratchBuffersPerOp) { + MicroPrintf("Scratch buffer request exeeds limit per operator (%d)", + kMaxScratchBuffersPerOp); + return kTfLiteError; + } + + // Initialize and assign values for the request at the current index: + internal::ScratchBufferRequest* current_request = + &requests[scratch_buffer_request_count_]; + *current_request = {}; + // Assign -1 as a sentinel value that will be updated when the node finishes + // allocating: + current_request->bytes = bytes; + current_request->node_idx = kUnassignedScratchBufferRequestIndex; + current_request->subgraph_idx = subgraph_idx; + + // Assign the current request index to the out-param: + *buffer_idx = scratch_buffer_request_count_; + + // Bump the request count to prepare for the next request: + ++scratch_buffer_request_count_; + return kTfLiteOk; +} + +TfLiteStatus MicroAllocator::FinishPrepareNodeAllocations(int node_id) { + // When a node has finished preparing, all temp allocations performed by the + // kernel should be cleaned up: + TF_LITE_ENSURE_STATUS(ResetTempAllocations()); + + // Find and update any new scratch buffer requests for the current node: + internal::ScratchBufferRequest* requests = GetScratchBufferRequests(); + + for (size_t i = 0; i < scratch_buffer_request_count_; ++i) { + // A request with a node_idx of -1 is a sentinel value used to indicate this + // was a new request for the current node. The allocator finally knows the + // node index at this point. Assign the value and update the list of new + // requests so the head section can be adjusted to allow for the next kernel + // to allocate at most kMaxScratchBuffersPerOp requests: + if (requests[i].node_idx == kUnassignedScratchBufferRequestIndex) { + requests[i].node_idx = node_id; + } + } + + // Ensure that the head is re-adjusted to allow for another at-most + // kMaxScratchBuffersPerOp scratch buffer requests in the next operator: + TF_LITE_ENSURE_STATUS(non_persistent_buffer_allocator_->ResizeBuffer( + scratch_buffer_head_, + sizeof(internal::ScratchBufferRequest) * + (scratch_buffer_request_count_ + kMaxScratchBuffersPerOp), + alignof(internal::ScratchBufferRequest))); + + return kTfLiteOk; +} + +size_t MicroAllocator::used_bytes() const { + return non_persistent_buffer_allocator_->GetNonPersistentUsedBytes() + + persistent_buffer_allocator_->GetPersistentUsedBytes(); +} + +TfLiteStatus MicroAllocator::AllocateNodeAndRegistrations( + const Model* model, SubgraphAllocations* subgraph_allocations) { + TFLITE_DCHECK(subgraph_allocations != nullptr); + + for (size_t subgraph_idx = 0; subgraph_idx < model->subgraphs()->size(); + subgraph_idx++) { + const SubGraph* subgraph = model->subgraphs()->Get(subgraph_idx); + TFLITE_DCHECK(subgraph != nullptr); + + uint32_t operators_size = NumSubgraphOperators(subgraph); + + // Initialize NodeAndRegistrations for the subgraph. + NodeAndRegistration* output = reinterpret_cast( + persistent_buffer_allocator_->AllocatePersistentBuffer( + sizeof(NodeAndRegistration) * operators_size, + alignof(NodeAndRegistration))); + if (output == nullptr) { + MicroPrintf("Failed to allocate memory for node_and_registrations."); + return kTfLiteError; + } + subgraph_allocations[subgraph_idx].node_and_registrations = output; + } + return kTfLiteOk; +} + +TfLiteTensor* MicroAllocator::AllocatePersistentTfLiteTensor( + const Model* model, const SubgraphAllocations* subgraph_allocations, + int tensor_index, int subgraph_index) { + const SubGraph* subgraph = model->subgraphs()->Get(subgraph_index); + TFLITE_DCHECK(subgraph != nullptr); + + // This value is allocated from persistent arena space. It is guaranteed to be + // around for the lifetime of the application. + TfLiteTensor* tensor = AllocatePersistentTfLiteTensorInternal(); + + // Populate any fields from the flatbuffer, since this TfLiteTensor struct is + // allocated in the persistent section of the arena, ensure that additional + // allocations also take place in that section of the arena. + if (PopulateTfLiteTensorFromFlatbuffer( + model, tensor, tensor_index, subgraph_index, + /*allocate_temp=*/false) != kTfLiteOk) { + MicroPrintf( + "Failed to populate a persistent TfLiteTensor struct " + "from flatbuffer data!"); + return nullptr; + } + + if (subgraph_allocations != nullptr) { + // Tensor buffers that are allocated at runtime (e.g. non-weight buffers) + // and not located in the flatbuffer are stored on the pre-allocated list of + // TfLiteEvalTensors structs. These structs are the source of truth, simply + // point the corresponding buffer to the new TfLiteTensor data value. + tensor->data.data = + subgraph_allocations[subgraph_index].tensors[tensor_index].data.data; + // TfLiteEvalTensor structs must also be the source of truth for the + // TfLiteTensor dims. + tensor->dims = + subgraph_allocations[subgraph_index].tensors[tensor_index].dims; + } + return tensor; +} + +void MicroAllocator::DeallocateTempTfLiteTensor(TfLiteTensor* tensor) { + TFLITE_DCHECK(tensor != nullptr); + + if (tensor->quantization.type == kTfLiteAffineQuantization) { + TFLITE_DCHECK(tensor->quantization.params != nullptr); + TfLiteAffineQuantization* quantization = + reinterpret_cast( + tensor->quantization.params); + + non_persistent_buffer_allocator_->DeallocateTemp( + reinterpret_cast(quantization->zero_point)); + non_persistent_buffer_allocator_->DeallocateTemp( + reinterpret_cast(quantization)); + } + + // Clear the data in case someone still access tensor arena by mistake + tensor->quantization.type = kTfLiteNoQuantization; + tensor->quantization.params = nullptr; + tensor->data.data = nullptr; + tensor->dims = nullptr; + non_persistent_buffer_allocator_->DeallocateTemp( + reinterpret_cast(tensor)); +} + +TfLiteTensor* MicroAllocator::AllocateTempTfLiteTensor( + const Model* model, const SubgraphAllocations* subgraph_allocations, + int tensor_index, int subgraph_index) { + const SubGraph* subgraph = model->subgraphs()->Get(subgraph_index); + TFLITE_DCHECK(subgraph != nullptr); + + // This value is allocated from temporary arena space. It is guaranteed to be + // around for at least the scope of the calling function. Since this struct + // allocation takes place in temp space, no need to own or cleanup. + TfLiteTensor* tensor = reinterpret_cast( + non_persistent_buffer_allocator_->AllocateTemp(sizeof(TfLiteTensor), + alignof(TfLiteTensor))); + + // Populate any fields from the flatbuffer, since this TfLiteTensor struct is + // allocated in the temp section of the arena, ensure that additional + // allocations also take place in that section of the arena. + if (PopulateTfLiteTensorFromFlatbuffer(model, tensor, tensor_index, + subgraph_index, + /*allocate_temp=*/true) != kTfLiteOk) { + MicroPrintf( + "Failed to populate a temp TfLiteTensor struct from flatbuffer data!"); + return nullptr; + } + + if (subgraph_allocations != nullptr) { + // Tensor buffers that are allocated at runtime (e.g. non-weight buffers) + // and not located in the flatbuffer are stored on the pre-allocated list of + // TfLiteEvalTensors structs. These structs are the source of truth, simply + // point the corresponding buffer to the new TfLiteTensor data value. + tensor->data.data = + subgraph_allocations[subgraph_index].tensors[tensor_index].data.data; + // TfLiteEvalTensor structs must also be the source of truth for the + // TfLiteTensor dims. + tensor->dims = + subgraph_allocations[subgraph_index].tensors[tensor_index].dims; + } + return tensor; +} + +TfLiteStatus MicroAllocator::ResetTempAllocations() { + return non_persistent_buffer_allocator_->ResetTempAllocations(); +} + +bool MicroAllocator::IsAllTempDeallocated() { + return non_persistent_buffer_allocator_->IsAllTempDeallocated(); +} + +TfLiteStatus MicroAllocator::AllocateTfLiteEvalTensors( + const Model* model, SubgraphAllocations* subgraph_allocations) { + TFLITE_DCHECK(subgraph_allocations != nullptr); + + for (size_t subgraph_idx = 0; subgraph_idx < model->subgraphs()->size(); + subgraph_idx++) { + const SubGraph* subgraph = model->subgraphs()->Get(subgraph_idx); + TFLITE_DCHECK(subgraph != nullptr); + + size_t alloc_count = subgraph->tensors()->size(); + TfLiteEvalTensor* tensors = reinterpret_cast( + persistent_buffer_allocator_->AllocatePersistentBuffer( + sizeof(TfLiteEvalTensor) * alloc_count, alignof(TfLiteEvalTensor))); + if (tensors == nullptr) { + MicroPrintf( + "Failed to allocate memory for context->eval_tensors, " + "%d bytes required", + sizeof(TfLiteEvalTensor) * alloc_count); + return kTfLiteError; + } + + for (size_t i = 0; i < alloc_count; ++i) { + TfLiteStatus status = internal::InitializeTfLiteEvalTensorFromFlatbuffer( + *subgraph->tensors()->Get(i), model->buffers(), &tensors[i]); + if (status != kTfLiteOk) { + MicroPrintf("Failed to initialize tensor %d", i); + return kTfLiteError; + } + } + subgraph_allocations[subgraph_idx].tensors = tensors; + } + return kTfLiteOk; +} + +TfLiteStatus MicroAllocator::AllocateVariables( + const SubGraph* subgraph, TfLiteEvalTensor* eval_tensors, + const int32_t* offline_planner_offsets) { + for (size_t i = 0; i < subgraph->tensors()->size(); ++i) { + auto* tensor = subgraph->tensors()->Get(i); + if (tensor->is_variable()) { + if (offline_planner_offsets == nullptr || + offline_planner_offsets[i] == kOnlinePlannedBuffer) { + size_t buffer_size; + TF_LITE_ENSURE_STATUS( + TfLiteEvalTensorByteLength(&eval_tensors[i], &buffer_size)); + + eval_tensors[i].data.data = + persistent_buffer_allocator_->AllocatePersistentBuffer( + buffer_size, MicroArenaBufferAlignment()); + + if (eval_tensors[i].data.data == nullptr) { + MicroPrintf("Failed to allocate variable tensor of size %d", + buffer_size); + return kTfLiteError; + } + } + } + } + return kTfLiteOk; +} + +TfLiteTensor* MicroAllocator::AllocatePersistentTfLiteTensorInternal() { + return reinterpret_cast( + persistent_buffer_allocator_->AllocatePersistentBuffer( + sizeof(TfLiteTensor), alignof(TfLiteTensor))); +} + +TfLiteStatus MicroAllocator::PopulateTfLiteTensorFromFlatbuffer( + const Model* model, TfLiteTensor* tensor, int tensor_index, + int subgraph_idx, bool allocate_temp) { + // TODO(b/162311891): This method serves as a stub to ensure quantized + // allocations in the tail can be recorded. Once the interpreter has APIs for + // accessing buffers on TfLiteEvalTensor this method can be dropped. + return internal::InitializeTfLiteTensorFromFlatbuffer( + persistent_buffer_allocator_, non_persistent_buffer_allocator_, + allocate_temp, + *model->subgraphs()->Get(subgraph_idx)->tensors()->Get(tensor_index), + model->buffers(), tensor); +} + +TfLiteStatus MicroAllocator::CommitStaticMemoryPlan( + const Model* model, SubgraphAllocations* allocations, + ScratchBufferHandle* scratch_buffer_handles) { + size_t head_usage = 0; + // Create static memory plan + // 1. Calculate AllocationInfo to know the lifetime of each tensor/buffer. + // 2. Add them into the planner (such as the GreedyMemoryPlanner). + // 3. Static memory planning using the planner. + // 4. Set tensor/buffer pointers based on the offsets from the previous step. + // + // Note that AllocationInfo is only needed for creating the plan. It will be + // allocated from the temp section and cleaned up at the bottom of this + // function. + + // Use the AllocationInfoBuilder class to help determine where buffers are + // used in the subgraph. + AllocationInfoBuilder builder(model, non_persistent_buffer_allocator_); + TF_LITE_ENSURE_STATUS( + builder.CreateAllocationInfo(scratch_buffer_request_count_)); + + const int32_t* offline_planner_offsets = nullptr; + TF_LITE_ENSURE_STATUS( + builder.GetOfflinePlannedOffsets(&offline_planner_offsets)); + + // We allocate buffers for variable tensors here since the offline planner + // offsets are conviently available here. + for (size_t subgraph_idx = 0; subgraph_idx < model->subgraphs()->size(); + subgraph_idx++) { + const SubGraph* subgraph = model->subgraphs()->Get(subgraph_idx); + TFLITE_DCHECK(subgraph != nullptr); + TF_LITE_ENSURE_STATUS(AllocateVariables( + subgraph, allocations[subgraph_idx].tensors, offline_planner_offsets)); + } + + TF_LITE_ENSURE_STATUS( + builder.InitializeAllocationInfo(offline_planner_offsets, allocations)); + + internal::ScratchBufferRequest* scratch_buffer_requests = + GetScratchBufferRequests(); + TF_LITE_ENSURE_STATUS(builder.MarkAllocationLifetimes( + 0, scratch_buffer_requests, scratch_buffer_handles, allocations)); + int allocation_info_count = builder.AllocationCount(); + AllocationInfo* allocation_info = builder.Finish(); + + // Remaining arena size that memory planner can use for calculating offsets. + size_t remaining_arena_size = + non_persistent_buffer_allocator_->GetAvailableMemory( + MicroArenaBufferAlignment()); + uint8_t* planner_arena = non_persistent_buffer_allocator_->AllocateTemp( + remaining_arena_size, MicroArenaBufferAlignment()); + + if (planner_arena == nullptr) { + return kTfLiteError; + } + + memory_planner_->Init(planner_arena, remaining_arena_size); + TF_LITE_ENSURE_STATUS( + CreatePlan(memory_planner_, allocation_info, allocation_info_count)); + + // Commit the plan. + TF_LITE_ENSURE_STATUS( + CommitPlan(memory_planner_, + non_persistent_buffer_allocator_->GetOverlayMemoryAddress(), + allocation_info, allocation_info_count)); + + // Reset all temp allocations used above: + builder.FreeAllocationInfo(); + non_persistent_buffer_allocator_->DeallocateTemp(planner_arena); + TF_LITE_ENSURE_STATUS( + non_persistent_buffer_allocator_->ResetTempAllocations()); + TF_LITE_ENSURE_STATUS( + non_persistent_buffer_allocator_->DeallocateResizableBuffer( + scratch_buffer_head_)); + +#ifdef TF_LITE_SHOW_MEMORY_USE + memory_planner_->PrintMemoryPlan(); +#endif + head_usage = memory_planner_->GetMaximumMemorySize(); + + // The head is used to store memory plans for one model at a time during the + // model preparation stage, and is re-purposed to store scratch buffer handles + // during model invocation. The head must be as large as the greater of the + // largest model memory plan's size and the total space required for all + // scratch buffer handles. + if (max_head_buffer_usage_ < head_usage) { + max_head_buffer_usage_ = head_usage; + } + + // The head is used for storing scratch buffer allocations before finalizing a + // memory plan in this function. Ensure that the head is set to the largest + // memory plan sent through the allocator: + TF_LITE_ENSURE_STATUS( + non_persistent_buffer_allocator_->ReserveNonPersistentOverlayMemory( + max_head_buffer_usage_, MicroArenaBufferAlignment())); + return kTfLiteOk; +} + +TfLiteStatus MicroAllocator::AllocateScratchBufferHandles( + ScratchBufferHandle** scratch_buffer_handles, size_t handle_count) { + TFLITE_DCHECK(scratch_buffer_handles != nullptr); + + if (scratch_buffer_request_count_ == 0) { + // No scratch buffer requests were requested during model allocation. + return kTfLiteOk; + } + + // Allocate a consecutive block of memory store the scratch buffer handles. + // This alignment ensures quick lookup during inference time for the model: + *scratch_buffer_handles = reinterpret_cast( + persistent_buffer_allocator_->AllocatePersistentBuffer( + sizeof(ScratchBufferHandle) * handle_count, + alignof(ScratchBufferHandle))); + + return kTfLiteOk; +} + +TfLiteStatus MicroAllocator::InitScratchBufferData() { + // A model is preparing to allocate resources, ensure that scratch buffer + // request counter is cleared: + scratch_buffer_request_count_ = 0; + + // All requests will be stored in the head section. Each kernel is allowed at + // most kMaxScratchBuffersPerOp requests. Adjust the head to reserve at most + // that many requests to begin: + scratch_buffer_head_ = + non_persistent_buffer_allocator_->AllocateResizableBuffer( + sizeof(internal::ScratchBufferRequest) * kMaxScratchBuffersPerOp, + alignof(internal::ScratchBufferRequest)); + if (scratch_buffer_head_ == nullptr) { + return kTfLiteError; + } + + return kTfLiteOk; +} + +internal::ScratchBufferRequest* MicroAllocator::GetScratchBufferRequests() { + return reinterpret_cast(AlignPointerUp( + scratch_buffer_head_, alignof(internal::ScratchBufferRequest))); +} + +TfLiteBridgeBuiltinDataAllocator* MicroAllocator::GetBuiltinDataAllocator() { + return builtin_data_allocator_; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h new file mode 100644 index 0000000..ca2e27e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h @@ -0,0 +1,325 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_ALLOCATOR_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_ALLOCATOR_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/micro_memory_planner.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +// TODO(b/199402574): rename to tflite_internal or just remove internal +// namespace. +namespace internal { + +// Sets up all of the data structure members for a TfLiteTensor based on the +// contents of a serialized tensor in the flatbuffer. +// TODO(b/162311891): Drop this method when the interpreter has an API for +// returning buffers on TfLiteEvalTensor. +TfLiteStatus InitializeTfLiteTensorFromFlatbuffer( + IPersistentBufferAllocator* persistent_buffer_allocator, + INonPersistentBufferAllocator* non_persistent_buffer_allocator, + bool allocate_temp, const tflite::Tensor& flatbuffer_tensor, + const flatbuffers::Vector>* buffers, + TfLiteTensor* result); + +// Holds placeholder information for a scratch buffer request from a kernel. +// This struct is only used during the model prepare stage. Each request from a +// kernel is stored in the head section. During the prepare stage, the head +// section will at least hold kMaxScratchBuffersPerOp number of requests plus +// any requests from previous kernel requests. +// +// When the memory plan is finalized, these structs are no longer used in favor +// of a sequential, array of ScratchBufferHandle allocations in the tail +// section. These allocations are indexed by the request API defined in the +// TfLiteContext struct. +struct ScratchBufferRequest { + // Number of bytes required by the buffer. The actual allocated size might be + // greater than `bytes` due to buffer alignment. + size_t bytes; + // Node where the buffer is allocated for. This provides useful information to + // determine the lifetime of the buffer. In AllocationInfo, this buffer will + // have `before` = node_idx and `after` = node_idx. + int node_idx; + int subgraph_idx; +}; + +} // namespace internal + +struct NodeAndRegistration { + TfLiteNode node; + const TfLiteRegistration* registration; +}; + +// Holds a pointer to a buffer for a scratch buffer requested by a kernel during +// the model prepare stage. This struct is allocated in-place and allows for +// quick pointer-indexed lookup for speed during model inference. +struct ScratchBufferHandle { + // Pointer to location of the scratch buffer: + uint8_t* data; +}; + +// Stores all per-subgraph allocations. This includes the node and registration +// array, and tensor list for each subgraph. +struct SubgraphAllocations { + NodeAndRegistration* node_and_registrations; + TfLiteEvalTensor* tensors; +}; + +// Allocator responsible for allocating memory for all intermediate tensors +// necessary to invoke a model. +// +// The lifetime of the model, tensor arena and error reporter must be at +// least as long as that of the allocator object, since the allocator needs +// them to be accessible during its entire lifetime. +// +// The MicroAllocator simply plans out additional allocations that are required +// to standup a model for inference in TF Micro. This class currently relies on +// an additional allocator - SingleArenaBufferAllocator - for all allocations +// from an arena. These allocations are divided into head (non-persistent) and +// tail (persistent) regions: +// +// Memory layout to help understand how it works +// This information could change in the future version. +// ************** .memory_allocator->GetBuffer() +// Tensors/Scratch buffers (head) +// ************** .head_watermark +// unused memory +// ************** .memory_allocator->GetBuffer() + ->GetMaxBufferSize() +// - ->GetDataSize() +// persistent area (tail) +// ************** .memory_allocator->GetBuffer() + ->GetMaxBufferSize() +class MicroAllocator { + public: + // Creates a MicroAllocator instance from a given tensor arena. This arena + // will be managed by the created instance. The GreedyMemoryPlanner will + // by default be used and created on the arena. + // Note: Please use alignas(16) to make sure tensor_arena is 16 + // bytes aligned, otherwise some head room will be wasted. + // TODO(b/157615197): Cleanup constructor + factory usage. + static MicroAllocator* Create(uint8_t* tensor_arena, size_t arena_size); + + // Creates a MicroAllocator instance from a given tensor arena and a given + // MemoryPlanner. This arena will be managed by the created instance. Note: + // Please use alignas(16) to make sure tensor_arena is 16 bytes + // aligned, otherwise some head room will be wasted. + static MicroAllocator* Create(uint8_t* tensor_arena, size_t arena_size, + MicroMemoryPlanner* memory_planner); + + // Creates a MicroAllocator instance using the provided + // SingleArenaBufferAllocator instance and the MemoryPlanner. This allocator + // instance will use the SingleArenaBufferAllocator instance to manage + // allocations internally. + static MicroAllocator* Create(SingleArenaBufferAllocator* memory_allocator, + MicroMemoryPlanner* memory_planner); + + // Creates a MicroAllocator instance using the provided + // SingleArenaBufferAllocator instance and the MemoryPlanner. This allocator + // instance will use the SingleArenaBufferAllocator instance to manage + // allocations internally. + static MicroAllocator* Create(uint8_t* persistent_tensor_arena, + size_t persistent_arena_size, + uint8_t* non_persistent_tensor_arena, + size_t non_persistent_arena_size); + + // Returns the fixed amount of memory overhead of MicroAllocator. + static size_t GetDefaultTailUsage(bool is_memory_planner_given); + + // Allocates internal resources required for model inference for each subgraph + // from the arena. + // + // This method will run through the flatbuffer data supplied in the model to + // properly allocate tensor, node, and op registration data. This method is + // expected to be followed with a call to FinishModelAllocation() Returns a + // pointer to an array of SubgraphAllocations (also stored in the tail of the + // arena) where each index corresponds to a different subgraph in the model. + // Return value is nullptr if the allocations failed. + SubgraphAllocations* StartModelAllocation(const Model* model); + + // Finish allocating internal resources required for model inference. + // + // -Plan the memory for activation tensors and scratch buffers. + // -Update eval tensors for each subgraph based on planned offsets. + // -Allocate scratch buffer handles array and update based on planned offsets. + // + // This method should be called after assigning model resources + // in StartModelAllocation(). The subgraph_allocations pointer should be the + // value passed into this class during StartModelAllocation(). Scratch buffer + // handles are stored in the out-param `scratch_buffer_handles` array which is + // allocated in this method. This value will be used in `GetScratchBuffer` + // call to retrieve scratch buffers. + TfLiteStatus FinishModelAllocation( + const Model* model, SubgraphAllocations* subgraph_allocations, + ScratchBufferHandle** scratch_buffer_handles); + + // Allocates a TfLiteTensor struct and populates the returned value with + // properties from the model flatbuffer. This struct is allocated from + // persistent arena memory is only guaranteed for the lifetime of the + // application. The eval_tensors pointer should be the value passed into this + // class during StartModelAllocation() and contains the source-of-truth for + // buffers. + virtual TfLiteTensor* AllocatePersistentTfLiteTensor( + const Model* model, const SubgraphAllocations* subgraph_allocations, + int tensor_index, int subgraph_index); + + // Allocates a TfLiteTensor struct and populates the returned value with + // properties from the model flatbuffer. This struct is allocated from + // temporary arena memory is only guaranteed until a call is made to + // ResetTempAllocations(). Subgraph_allocaitons contains the array of + // TfLiteEvalTensors. If the newly allocated temp at the specified subgraph + // and tensor index is already present int the TfLiteEvalTensor array, its + // data buffer will be re-used. + virtual TfLiteTensor* AllocateTempTfLiteTensor( + const Model* model, const SubgraphAllocations* subgraph_allocations, + int tensor_index, int subgraph_index); + + virtual void DeallocateTempTfLiteTensor(TfLiteTensor*); + + // Resets all temporary allocations. This method should be called after a + // chain of temp allocations (e.g. chain of TfLiteTensor objects via + // AllocateTfLiteTensor()). + virtual TfLiteStatus ResetTempAllocations(); + + // Returns true if all temporary buffers including temp TfLiteTensor are + // already deallocated. + virtual bool IsAllTempDeallocated(); + + // Allocates persistent buffer which has the same life time as the allocator. + // The memory is immediately available and is allocated from the tail of the + // arena. + virtual void* AllocatePersistentBuffer(size_t bytes); + + // Register a scratch buffer of size `bytes` for Node with `node_id`. + // This method only requests a buffer with a given size to be used after a + // model has finished allocation via FinishModelAllocation(). All requested + // buffers will be accessible by the out-param in that method. + TfLiteStatus RequestScratchBufferInArena(size_t bytes, int subgraph_idx, + int* buffer_idx); + + // Finish allocating a specific NodeAndRegistration prepare block (kernel + // entry for a model) with a given node ID. This call ensures that any scratch + // buffer requests and temporary allocations are handled and ready for the + // next node prepare block. + TfLiteStatus FinishPrepareNodeAllocations(int node_id); + + // Returns the arena usage in bytes, only available after + // `FinishModelAllocation`. Otherwise, it will return 0. + size_t used_bytes() const; + + TfLiteBridgeBuiltinDataAllocator* GetBuiltinDataAllocator(); + + protected: + MicroAllocator(SingleArenaBufferAllocator* memory_allocator, + MicroMemoryPlanner* memory_planner); + MicroAllocator(IPersistentBufferAllocator* persistent_buffer_allocator, + INonPersistentBufferAllocator* non_persistent_buffer_allocator, + MicroMemoryPlanner* memory_planner); + virtual ~MicroAllocator(); + + // Allocates an array in the arena to hold pointers to the node and + // registration pointers required to represent the inference graph of the + // model. + virtual TfLiteStatus AllocateNodeAndRegistrations( + const Model* model, SubgraphAllocations* subgraph_allocations); + + // Allocates the list of persistent TfLiteEvalTensors that are used for the + // "eval" phase of model inference. These structs will be the source of truth + // for all tensor buffers. + virtual TfLiteStatus AllocateTfLiteEvalTensors( + const Model* model, SubgraphAllocations* subgraph_allocations); + + // Allocates persistent tensor buffers for variable tensors in the subgraph. + // Online and offline variable tensors are handled differently hence the + // offline_planner_offsets parameter is needed. + virtual TfLiteStatus AllocateVariables( + const SubGraph* subgraph, TfLiteEvalTensor* eval_tensors, + const int32_t* offline_planner_offsets); + + // Allocate and return a persistent TfLiteTensor. + // TODO(b/162311891): Drop this method when the interpreter has an API for + // accessing TfLiteEvalTensor structs. + virtual TfLiteTensor* AllocatePersistentTfLiteTensorInternal(); + + // Populates a TfLiteTensor struct with data from the model flatbuffer. Any + // quantization data is allocated from either the tail (persistent) or temp + // sections of the arena based on the allocation flag. + virtual TfLiteStatus PopulateTfLiteTensorFromFlatbuffer(const Model* model, + TfLiteTensor* tensor, + int tensor_index, + int subgraph_idx, + bool allocate_temp); + + private: + // Commits a memory plan for all non-persistent buffer allocations in the + // 'head' section of the memory arena. The eval_tensors pointer is the list of + // pre-allocated TfLiteEvalTensor structs that will point to the buffers that + // will be allocated into the head section in this function call. The + // scratch_buffer_handles pointer is the array of pre-allocated + // ScratchBufferHandle structs that will point to allocated buffers also in + // the head section. + virtual TfLiteStatus CommitStaticMemoryPlan( + const Model* model, SubgraphAllocations* allocations, + ScratchBufferHandle* scratch_buffer_handles); + + // Allocates an array of ScratchBufferHandle structs in the tail section for a + // given number of handles. + virtual TfLiteStatus AllocateScratchBufferHandles( + ScratchBufferHandle** scratch_buffer_handles, size_t handle_count); + + // Clears all internal scratch buffer request counts and resets the head to + // prepare for kernels to request scratch buffer data when a model is + // preparing. + TfLiteStatus InitScratchBufferData(); + + // Returns the pointer for the array of ScratchBufferRequest allocations in + // the head section. + internal::ScratchBufferRequest* GetScratchBufferRequests(); + + // A simple memory allocator that always allocate from the arena tail or head. + INonPersistentBufferAllocator* non_persistent_buffer_allocator_; + IPersistentBufferAllocator* persistent_buffer_allocator_; + + // Allocator used to allocate persistent builtin data. + TfLiteBridgeBuiltinDataAllocator* builtin_data_allocator_; + + // Activation buffer memory planner. + MicroMemoryPlanner* memory_planner_; + + bool model_is_allocating_; + + // Holds the number of ScratchBufferRequest instances stored in the head + // section when a model is allocating. + size_t scratch_buffer_request_count_ = 0; + + // Holds ScratchBufferRequest when a model is allocating + uint8_t* scratch_buffer_head_ = nullptr; + + // Holds the byte length of the memory plan with the largest head usage. Used + // to ensure that multi-tenant allocations can share the head for buffers. + size_t max_head_buffer_usage_ = 0; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite +#endif // TENSORFLOW_LITE_MICRO_MICRO_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_arena_constants.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_arena_constants.h new file mode 100644 index 0000000..8282817 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_arena_constants.h @@ -0,0 +1,28 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MICRO_ARENA_CONSTANTS_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_ARENA_CONSTANTS_H_ + +namespace tflite { + +// The default buffer alignment requirement. +// We align tensor buffers to 16-byte boundaries, since this is a common +// requirement for SIMD extensions. +constexpr int MicroArenaBufferAlignment() { return 16; } + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_ARENA_CONSTANTS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_context.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_context.cpp new file mode 100644 index 0000000..b0a4244 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_context.cpp @@ -0,0 +1,129 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { +MicroContext::MicroContext(MicroAllocator* allocator, const Model* model, + MicroGraph* graph) + : allocator_(*allocator), graph_(*graph), model_(model) {} + +MicroContext::~MicroContext() {} + +void* MicroContext::AllocatePersistentBuffer(size_t bytes) { + return allocator_.AllocatePersistentBuffer(bytes); +} + +TfLiteStatus MicroContext::RequestScratchBufferInArena(size_t bytes, + int* buffer_idx) { + return allocator_.RequestScratchBufferInArena( + bytes, graph_.GetCurrentSubgraphIndex(), buffer_idx); +} + +void* MicroContext::GetScratchBuffer(int buffer_idx) { + ScratchBufferHandle* handle = scratch_buffer_handles_ + buffer_idx; + return handle->data; +} + +TfLiteTensor* MicroContext::AllocateTempTfLiteTensor(int tensor_idx) { + return allocator_.AllocateTempTfLiteTensor(model_, graph_.GetAllocations(), + tensor_idx, + graph_.GetCurrentSubgraphIndex()); +} + +int MicroContext::GetTensorIndex(int index, int max_size, + const int* tensor_indices) { + if (index >= 0 && index < max_size) { + const int tensor_index = tensor_indices[index]; + if (tensor_index != kTfLiteOptionalTensor) { + return tensor_index; + } + } + return -1; +} + +TfLiteTensor* MicroContext::AllocateTempInputTensor(const TfLiteNode* node, + int index) { + const int tensor_index = + GetTensorIndex(index, node->inputs->size, node->inputs->data); + if (tensor_index < 0) { + return nullptr; + } + return AllocateTempTfLiteTensor(tensor_index); +} + +TfLiteTensor* MicroContext::AllocateTempOutputTensor(const TfLiteNode* node, + int index) { + const int tensor_index = + GetTensorIndex(index, node->outputs->size, node->outputs->data); + if (tensor_index < 0) { + return nullptr; + } + return AllocateTempTfLiteTensor(tensor_index); +} + +TfLiteTensor* MicroContext::AllocateTempIntermediateTensor( + const TfLiteNode* node, int index) { + const int tensor_index = GetTensorIndex(index, node->intermediates->size, + node->intermediates->data); + if (tensor_index < 0) { + return nullptr; + } + return AllocateTempTfLiteTensor(tensor_index); +} + +void MicroContext::DeallocateTempTfLiteTensor(TfLiteTensor* tensor) { + return allocator_.DeallocateTempTfLiteTensor(tensor); +} + +TfLiteEvalTensor* MicroContext::GetEvalTensor(int tensor_idx) { + return &graph_.GetAllocations()[graph_.GetCurrentSubgraphIndex()] + .tensors[tensor_idx]; +} + +void MicroContext::SetScratchBufferHandles( + ScratchBufferHandle* scratch_buffer_handles) { + scratch_buffer_handles_ = scratch_buffer_handles; +} + +TfLiteStatus MicroContext::set_external_context( + void* external_context_payload) { + if (external_context_payload == nullptr || + external_context_payload_ != nullptr) { + MicroPrintf( + "Attempting to set external context to %x but it was %x already", + external_context_payload, external_context_payload_); + return kTfLiteError; + } + + external_context_payload_ = external_context_payload; + return kTfLiteOk; +} + +void MicroContextReportOpError(struct TfLiteContext* context, + const char* format, ...) { + va_list args; + va_start(args, format); + Log(format, args); + va_end(args); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_context.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_context.h new file mode 100644 index 0000000..65a64b2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_context.h @@ -0,0 +1,161 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MICRO_CONTEXT_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_CONTEXT_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" + +namespace tflite { +// MicroContext is eventually going to become the API between TFLM and the +// kernels, replacing all the functions in TfLiteContext. The end state is code +// kernels to have code like: +// +// MicroContext* micro_context = GetMicroContext(context); +// micro_context-> +class MicroContext { + public: + // Does not take any ownership, and all pointers must refer to valid objects + // that outlive the one constructed. + explicit MicroContext(MicroAllocator* allocator, const Model* model, + MicroGraph* graph); + virtual ~MicroContext(); + + // Allocate persistent buffer which has the same life time as the interpreter. + // Returns nullptr on failure. + // The memory is allocated from the tail. + // This method is only available in Init or Prepare stage. + // Virtual so that it can be faked for kernel tests. + virtual void* AllocatePersistentBuffer(size_t bytes); + + // Request a scratch buffer in the arena through static memory planning. + // This method is only available in Prepare stage and the buffer is allocated + // by the interpreter between Prepare and Eval stage. In Eval stage, + // GetScratchBuffer API can be used to fetch the address. + // Virtual so that it can be faked for kernel tests. + virtual TfLiteStatus RequestScratchBufferInArena(size_t bytes, + int* buffer_idx); + + // Get the scratch buffer pointer. + // This method is only available in Eval stage. + // Virtual so that it can be faked for kernel tests. + virtual void* GetScratchBuffer(int buffer_idx); + + // Returns a temporary TfLiteTensor struct for a given index. + // Virtual so that it can be faked for kernel tests. + virtual TfLiteTensor* AllocateTempTfLiteTensor(int tensor_idx); + + // Returns a temporary TfLiteTensor struct for the specified input tensor of a + // given mode. This is the recommended API over the deprecated + // GetInput/GetInputSafe to get a temp input tensor. The returned tensor shall + // be freed via calling DeallocateTempTfLiteTensor. + virtual TfLiteTensor* AllocateTempInputTensor(const TfLiteNode* node, + int index); + + // Returns a temporary TfLiteTensor struct for the specified output tensor of + // a given mode. This is the recommended API over the deprecated + // GetOutput/GetOutputSafe to get a temp output tensor. The returned tensor + // shall be freed via calling DeallocateTempTfLiteTensor. + virtual TfLiteTensor* AllocateTempOutputTensor(const TfLiteNode* node, + int index); + + // Returns a temporary TfLiteTensor struct for the specified intermediate + // tensor of a given mode. This is the recommended API over the deprecated + // GetIntermediates/GetIntermediatesSafe to get a temp intermediate tensor. + // The returned tensor shall be freed via calling DeallocateTempTfLiteTensor. + virtual TfLiteTensor* AllocateTempIntermediateTensor(const TfLiteNode* node, + int index); + + // Deallocates a temp TfLiteTensor. + // Virtual so that it can be faked for kernel tests. + virtual void DeallocateTempTfLiteTensor(TfLiteTensor* tensor); + + // Returns a TfLiteEvalTensor struct for a given index. + // Virtual so that it can be faked for kernel tests. + virtual TfLiteEvalTensor* GetEvalTensor(int tensor_idx); + + // Does not take ownership of the pointer and the pointer must refer to valid + // an object that outlive this class instance. + // This can only be called once to set one external context. + TfLiteStatus set_external_context(void* external_context_payload); + + void* external_context() { return external_context_payload_; } + + MicroGraph& graph() { return graph_; } + + // Sets the pointer to a list of ScratchBufferHandle instances. + // Not API between TFLM and kernels. Primarily used by the framework for + // housekeeping in MicroContext. + void SetScratchBufferHandles(ScratchBufferHandle* scratch_buffer_handles); + + private: + // Return the tensor index as tensor_indices[index]. tensor_indices is of + // max_size. Return -1 if index is not in the valid range of tensor_indices. + int GetTensorIndex(int index, int max_size, const int* tensor_indices); + + MicroAllocator& allocator_; + MicroGraph& graph_; + const Model* model_; + + ScratchBufferHandle* scratch_buffer_handles_ = nullptr; + void* external_context_payload_ = nullptr; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +inline MicroContext* GetMicroContext(const struct TfLiteContext* context) { + return reinterpret_cast(context->impl_); +} + +// Deprecated API. Prefer to using the MicroContext API directly from the +// kernels. +// TODO(b/213010668): migrate all existing kernels to use MicroContext, delete +// these functions, and remove corresponding members from the TfLiteContext +// struct for TFLM. +inline void* MicroContextAllocatePersistentBuffer(TfLiteContext* ctx, + size_t bytes) { + return GetMicroContext(ctx)->AllocatePersistentBuffer(bytes); +} +inline TfLiteStatus MicroContextRequestScratchBufferInArena(TfLiteContext* ctx, + size_t bytes, + int* buffer_idx) { + return GetMicroContext(ctx)->RequestScratchBufferInArena(bytes, buffer_idx); +} +inline void* MicroContextGetScratchBuffer(TfLiteContext* ctx, int buffer_idx) { + return GetMicroContext(ctx)->GetScratchBuffer(buffer_idx); +} +inline TfLiteTensor* MicroContextGetTensor(const struct TfLiteContext* context, + int tensor_idx) { + return GetMicroContext(context)->AllocateTempTfLiteTensor(tensor_idx); +} +inline TfLiteEvalTensor* MicroContextGetEvalTensor( + const struct TfLiteContext* context, int tensor_idx) { + return GetMicroContext(context)->GetEvalTensor(tensor_idx); +} +inline TfLiteExternalContext* MicroContextGetExternalContext( + TfLiteContext* context, TfLiteExternalContextType unused) { + return reinterpret_cast( + GetMicroContext(context)->external_context()); +} + +// Requests that an error be reported with format string msg. +void MicroContextReportOpError(struct TfLiteContext* context, + const char* format, ...); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_CONTEXT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.cpp new file mode 100644 index 0000000..f15cfcc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.cpp @@ -0,0 +1,43 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace { +uint8_t micro_error_reporter_buffer[sizeof(tflite::MicroErrorReporter)]; +tflite::MicroErrorReporter* error_reporter_ = nullptr; + +} // namespace + +namespace tflite { +ErrorReporter* GetMicroErrorReporter() { + if (error_reporter_ == nullptr) { + error_reporter_ = new (micro_error_reporter_buffer) MicroErrorReporter(); + } + return error_reporter_; +} + +int MicroErrorReporter::Report(const char* format, va_list args) { + Log(format, args); + return 0; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.h new file mode 100644 index 0000000..20a2423 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.h @@ -0,0 +1,37 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_MICRO_ERROR_REPORTER_H_ +#define TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_MICRO_ERROR_REPORTER_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" + +namespace tflite { +// Get a pointer to a singleton global error reporter. +ErrorReporter* GetMicroErrorReporter(); +class MicroErrorReporter : public ErrorReporter { + public: + ~MicroErrorReporter() override {} + int Report(const char* format, va_list args) override; + + private: + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_MICRO_ERROR_REPORTER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_graph.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_graph.cpp new file mode 100644 index 0000000..fa43d6c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_graph.cpp @@ -0,0 +1,258 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { +namespace { + +const char* OpNameFromRegistration(const TfLiteRegistration* registration) { + if (registration->builtin_code == BuiltinOperator_CUSTOM) { + return registration->custom_name; + } else { + return EnumNameBuiltinOperator(BuiltinOperator(registration->builtin_code)); + } +} + +} // namespace + +MicroGraph::MicroGraph(TfLiteContext* context, const Model* model, + MicroAllocator* allocator, + MicroResourceVariables* resource_variables) + : context_(context), + model_(model), + allocator_(allocator), + current_subgraph_index_(0), + resource_variables_(resource_variables) { + if (model != nullptr) { + subgraphs_ = model->subgraphs(); + } +} + +MicroGraph::~MicroGraph() {} + +TfLiteStatus MicroGraph::InitSubgraphs() { + int previous_subgraph_idx = current_subgraph_index_; + + for (size_t subgraph_idx = 0; subgraph_idx < subgraphs_->size(); + subgraph_idx++) { + current_subgraph_index_ = subgraph_idx; + uint32_t operators_size = NumSubgraphOperators(model_, subgraph_idx); + for (size_t i = 0; i < operators_size; ++i) { + TfLiteNode* node = + &(subgraph_allocations_[subgraph_idx].node_and_registrations[i].node); + const TfLiteRegistration* registration = + subgraph_allocations_[subgraph_idx] + .node_and_registrations[i] + .registration; + size_t init_data_size; + const char* init_data; + if (registration->builtin_code == BuiltinOperator_CUSTOM) { + init_data = reinterpret_cast(node->custom_initial_data); + init_data_size = node->custom_initial_data_size; + } else { + init_data = reinterpret_cast(node->builtin_data); + init_data_size = 0; + } + if (registration->init) { + node->user_data = + registration->init(context_, init_data, init_data_size); + } + } + } + current_subgraph_index_ = previous_subgraph_idx; + + return kTfLiteOk; +} + +TfLiteStatus MicroGraph::PrepareSubgraphs(bool run_all_prep_ops) { + int previous_subgraph_idx = current_subgraph_index_; + bool all_prep_ops_ok = true; + + for (size_t subgraph_idx = 0; subgraph_idx < subgraphs_->size(); + subgraph_idx++) { + current_subgraph_index_ = subgraph_idx; + uint32_t operators_size = NumSubgraphOperators(model_, subgraph_idx); + for (size_t i = 0; i < operators_size; ++i) { + TfLiteNode* node = + &(subgraph_allocations_[subgraph_idx].node_and_registrations[i].node); + const TfLiteRegistration* registration = + subgraph_allocations_[subgraph_idx] + .node_and_registrations[i] + .registration; + if (registration->prepare != nullptr) { + TfLiteStatus prepare_status = registration->prepare(context_, node); + if (prepare_status != kTfLiteOk) { + MicroPrintf("Node %s (number %df) failed to prepare with status %d", + OpNameFromRegistration(registration), i, prepare_status); + + all_prep_ops_ok = false; + if (!run_all_prep_ops) { + return kTfLiteError; + } + } + } + allocator_->FinishPrepareNodeAllocations(/*node_id=*/i); + } + + if (!all_prep_ops_ok) { + return kTfLiteError; + } + + } + current_subgraph_index_ = previous_subgraph_idx; + + return kTfLiteOk; +} + +TfLiteStatus MicroGraph::FreeSubgraphs() { + int previous_subgraph_idx = current_subgraph_index_; + + for (size_t subgraph_idx = 0; subgraph_idx < subgraphs_->size(); + subgraph_idx++) { + current_subgraph_index_ = subgraph_idx; + uint32_t operators_size = NumSubgraphOperators(model_, subgraph_idx); + for (size_t i = 0; i < operators_size; ++i) { + TfLiteNode* node = + &(subgraph_allocations_[subgraph_idx].node_and_registrations[i].node); + const TfLiteRegistration* registration = + subgraph_allocations_[subgraph_idx] + .node_and_registrations[i] + .registration; + // registration is allocated outside the interpreter, so double check to + // make sure it's not nullptr; + if (registration != nullptr && registration->free != nullptr) { + registration->free(context_, node->user_data); + } + } + } + current_subgraph_index_ = previous_subgraph_idx; + + return kTfLiteOk; +} + +TfLiteStatus MicroGraph::InvokeSubgraph(int subgraph_idx) { + int previous_subgraph_idx = current_subgraph_index_; + current_subgraph_index_ = subgraph_idx; + + if (static_cast(subgraph_idx) >= subgraphs_->size()) { + MicroPrintf("Accessing subgraph %d but only %d subgraphs found", + subgraph_idx, subgraphs_->size()); + return kTfLiteError; + } + uint32_t operators_size = NumSubgraphOperators(model_, subgraph_idx); + for (size_t i = 0; i < operators_size; ++i) { + TfLiteNode* node = + &(subgraph_allocations_[subgraph_idx].node_and_registrations[i].node); + const TfLiteRegistration* registration = subgraph_allocations_[subgraph_idx] + .node_and_registrations[i] + .registration; + +// This ifdef is needed (even though ScopedMicroProfiler itself is a no-op with +// -DTF_LITE_STRIP_ERROR_STRINGS) because the function OpNameFromRegistration is +// only defined for builds with the error strings. +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) + ScopedMicroProfiler scoped_profiler( + OpNameFromRegistration(registration), + reinterpret_cast(context_->profiler)); +#endif + + TFLITE_DCHECK(registration->invoke); + TfLiteStatus invoke_status = registration->invoke(context_, node); + + // All TfLiteTensor structs used in the kernel are allocated from temp + // memory in the allocator. This creates a chain of allocations in the + // temp section. The call below resets the chain of allocations to + // prepare for the next call. + allocator_->ResetTempAllocations(); + + if (invoke_status == kTfLiteError) { + MicroPrintf("Node %s (number %d) failed to invoke with status %d", + OpNameFromRegistration(registration), i, invoke_status); + return kTfLiteError; + } else if (invoke_status != kTfLiteOk) { + return invoke_status; + } + } + current_subgraph_index_ = previous_subgraph_idx; + return kTfLiteOk; +} + +TfLiteStatus MicroGraph::ResetVariableTensors() { + for (size_t subgraph_idx = 0; subgraph_idx < subgraphs_->size(); + subgraph_idx++) { + const SubGraph* subgraph = (*subgraphs_)[subgraph_idx]; + for (size_t i = 0; i < subgraph->tensors()->size(); ++i) { + auto* tensor = subgraph->tensors()->Get(i); + if (tensor->is_variable()) { + size_t buffer_size; + TF_LITE_ENSURE_STATUS(TfLiteEvalTensorByteLength( + &subgraph_allocations_[subgraph_idx].tensors[i], &buffer_size)); + + int value = 0; + if (tensor->type() == tflite::TensorType_INT8) { + value = tensor->quantization()->zero_point()->Get(0); + } + memset(subgraph_allocations_[subgraph_idx].tensors[i].data.raw, value, + buffer_size); + } + } + } + if (resource_variables_ != nullptr) { + resource_variables_->ResetAll(); + } + + return kTfLiteOk; +} + +int MicroGraph::NumSubgraphs() { return model_->subgraphs()->size(); } + +void MicroGraph::SetSubgraphAllocations( + SubgraphAllocations* subgraph_allocations) { + subgraph_allocations_ = subgraph_allocations; +} + +size_t MicroGraph::NumSubgraphInputs(int subgraph_idx) { + return model_->subgraphs()->Get(subgraph_idx)->inputs()->size(); +} + +TfLiteEvalTensor* MicroGraph::GetSubgraphInput(int subgraph_idx, + int input_idx) { + int tensor_idx = + model_->subgraphs()->Get(subgraph_idx)->inputs()->Get(input_idx); + return &subgraph_allocations_[subgraph_idx].tensors[tensor_idx]; +} + +size_t MicroGraph::NumSubgraphOutputs(int subgraph_idx) { + return model_->subgraphs()->Get(subgraph_idx)->outputs()->size(); +} + +TfLiteEvalTensor* MicroGraph::GetSubgraphOutput(int subgraph_idx, + int output_idx) { + int tensor_idx = + model_->subgraphs()->Get(subgraph_idx)->outputs()->Get(output_idx); + return &subgraph_allocations_[subgraph_idx].tensors[tensor_idx]; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h new file mode 100644 index 0000000..0e096c7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h @@ -0,0 +1,110 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MICRO_GRAPH_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_GRAPH_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +// Abstracts the details of interacting with the tflite::Model. +// +// Provides methods to access, initialize, prepare, invoke and free any +// subgraph in the tflite::Graph. +class MicroGraph { + public: + // The lifetime of the context, model, allocator and resource_variables must + // be at least as long as that of the graph object, since the this class may + // need to access them at any time. If resource_variables is a nullptr, + // GetResourceVariables will return a nullptr. + MicroGraph(TfLiteContext* context, const Model* model, + MicroAllocator* allocator, + MicroResourceVariables* resource_variables); + virtual ~MicroGraph(); + + // Sets up builtin data and calls TfLiteRegistration->Init for every operator + // in every subgraph in the model. + virtual TfLiteStatus InitSubgraphs(); + + // Calls TfLiteRegistration->Prepare for every operator in every subgraph in + // the model. + virtual TfLiteStatus PrepareSubgraphs(bool run_all_prep_ops); + + // Calls TfLiteRegistration->Free for every operator in every subgraph in the + // model. + virtual TfLiteStatus FreeSubgraphs(); + + // Calls TfLiteRegistration->Invoke for every operator in a single subgraph in + // the model. + virtual TfLiteStatus InvokeSubgraph(int subgraph_idx); + + // Zeros out all variable tensors in all subgraphs in the model. + virtual TfLiteStatus ResetVariableTensors(); + + // Number of tensor inputs to a specified subgraph in the model. + virtual size_t NumSubgraphInputs(int subgraph_idx); + + // Get the specified input tensor of a specified subgraph in the model. + virtual TfLiteEvalTensor* GetSubgraphInput(int subgraph_idx, int input_idx); + + // Number of tensor outputs from a specified subgraph in the model. + virtual size_t NumSubgraphOutputs(int subgraph_idx); + + // Get the specified output tensor of a specified subgraph in the model. + virtual TfLiteEvalTensor* GetSubgraphOutput(int subgraph_idx, int output_idx); + + // Number of subgraphs in the model. + virtual int NumSubgraphs(); + + // Hook to pass in subgraph allocations tracked within the interpreter, + // allowing MicroGraph to init / prepare / invoke subgraphs in the model. + void SetSubgraphAllocations(SubgraphAllocations* subgraph_allocations); + + // Get the current subgraph index. Within an on operator, this is guaranteed + // to be the subgraph of that operator. + int GetCurrentSubgraphIndex() { return current_subgraph_index_; } + + // Set the current subgraph index. + void SetCurrentSubgraphIndex(int subgraph_idx) + { + current_subgraph_index_ = subgraph_idx; + } + + // Gets the list of alloctions for each subgraph. This is the source of truth + // for all per-subgraph allocation data. + SubgraphAllocations* GetAllocations() { return subgraph_allocations_; } + + // Get the resource variables for this TFLM graph. + MicroResourceVariables* GetResourceVariables() { return resource_variables_; } + + private: + TfLiteContext* context_; + const Model* model_; + MicroAllocator* allocator_; + SubgraphAllocations* subgraph_allocations_ = nullptr; + int current_subgraph_index_; + MicroResourceVariables* resource_variables_; + const flatbuffers::Vector>* subgraphs_; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_GRAPH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.cpp new file mode 100644 index 0000000..3c734fb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.cpp @@ -0,0 +1,347 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h" + +#include +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_op_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_profiler_interface.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h" + +namespace tflite { + +MicroInterpreter::MicroInterpreter(const Model* model, + const MicroOpResolver& op_resolver, + uint8_t* tensor_arena, + size_t tensor_arena_size, + MicroResourceVariables* resource_variables, + MicroProfilerInterface* profiler) + : model_(model), + op_resolver_(op_resolver), + allocator_(*MicroAllocator::Create(tensor_arena, tensor_arena_size)), + + graph_(&context_, model, &allocator_, resource_variables), + tensors_allocated_(false), + initialization_status_(kTfLiteError), + input_tensors_(nullptr), + output_tensors_(nullptr), + micro_context_(&allocator_, model_, &graph_) { + Init(profiler); +} + +MicroInterpreter::MicroInterpreter(const Model* model, + const MicroOpResolver& op_resolver, + MicroAllocator* allocator, + MicroResourceVariables* resource_variables, + MicroProfilerInterface* profiler) + : model_(model), + op_resolver_(op_resolver), + allocator_(*allocator), + graph_(&context_, model, allocator, resource_variables), + tensors_allocated_(false), + initialization_status_(kTfLiteError), + input_tensors_(nullptr), + output_tensors_(nullptr), + micro_context_(&allocator_, model_, &graph_) { + Init(profiler); +} + +MicroInterpreter::~MicroInterpreter() { + if (graph_.GetAllocations() != nullptr) { + graph_.FreeSubgraphs(); + } +#ifdef EON_COMPILER_RUN + if (node_and_registrations_ != nullptr) { + for (size_t i = 0; i < model_->subgraphs()->Get(0)->operators()->size(); ++i) { + TfLiteNode* node = &(node_and_registrations_[i].node); + const TfLiteRegistration* registration = + node_and_registrations_[i].registration; + // registration is allocated outside the interpreter, so double check to + // make sure it's not nullptr; + if (registration != nullptr && registration->free != nullptr) { + registration->free(&context_, node->user_data); + } + } + } +#endif +} + +void MicroInterpreter::Init(MicroProfilerInterface* profiler) { + context_.impl_ = static_cast(µ_context_); + context_.ReportError = MicroContextReportOpError; + context_.GetTensor = MicroContextGetTensor; + context_.GetEvalTensor = MicroContextGetEvalTensor; + context_.profiler = profiler; + + initialization_status_ = kTfLiteOk; +} + +TfLiteStatus MicroInterpreter::PrepareNodeAndRegistrationDataFromFlatbuffer() { + for (int subgraph_idx = 0; subgraph_idx < graph_.NumSubgraphs(); + subgraph_idx++) { + const SubGraph* subgraph = model_->subgraphs()->Get(subgraph_idx); + TFLITE_DCHECK(subgraph != nullptr); + + auto* opcodes = model_->operator_codes(); + TfLiteBridgeBuiltinDataAllocator* builtin_data_allocator = + allocator_.GetBuiltinDataAllocator(); + uint32_t operators_size = NumSubgraphOperators(subgraph); + for (size_t i = 0; i < operators_size; ++i) { + const auto* op = subgraph->operators()->Get(i); + const size_t index = op->opcode_index(); + if (index >= opcodes->size()) { + MicroPrintf("Missing registration for opcode_index %d\n", index); + return kTfLiteError; + } + const auto* opcode = opcodes->Get(index); + TfLiteStatus status = + GetRegistrationFromOpCode(opcode, op_resolver_, + &(graph_.GetAllocations()[subgraph_idx] + .node_and_registrations[i] + .registration)); + if (status != kTfLiteOk) { + MicroPrintf("Failed to get registration from op code %s\n ", + EnumNameBuiltinOperator(GetBuiltinCode(opcode))); + return status; + } + const auto* registration = graph_.GetAllocations()[subgraph_idx] + .node_and_registrations[i] + .registration; + if (registration == nullptr) { + MicroPrintf("Skipping op for opcode_index %d\n", index); + return kTfLiteError; + } + BuiltinOperator op_type = + static_cast(registration->builtin_code); + + const char* custom_data = nullptr; + size_t custom_data_size = 0; + unsigned char* builtin_data = nullptr; + + if (op_type == BuiltinOperator_CUSTOM) { + // Custom Ops may or may not have a non-null custom_options field. + if (op->custom_options() != nullptr) { + custom_data = + reinterpret_cast(op->custom_options()->data()); + custom_data_size = op->custom_options()->size(); + } + } else { + if (op->custom_options() != nullptr) { + MicroPrintf( + "Unsupported behavior: found builtin operator %s with custom " + "options.\n", + EnumNameBuiltinOperator(op_type)); + return kTfLiteError; + } + + TfLiteBridgeBuiltinParseFunction parser = + op_resolver_.GetOpDataParser(op_type); + if (parser == nullptr) { + MicroPrintf("Did not find a parser for %s", + EnumNameBuiltinOperator(op_type)); + + return kTfLiteError; + } + TF_LITE_ENSURE_STATUS(CallBuiltinParseFunction( + parser, op, builtin_data_allocator, (void**)(&builtin_data))); + } + + TfLiteIntArray* inputs_array = + FlatBufferVectorToTfLiteTypeArray(op->inputs()); + TfLiteIntArray* outputs_array = + FlatBufferVectorToTfLiteTypeArray(op->outputs()); + + TfLiteNode* node = &( + graph_.GetAllocations()[subgraph_idx].node_and_registrations[i].node); + *node = {}; + node->inputs = inputs_array; + node->outputs = outputs_array; + node->builtin_data = reinterpret_cast(builtin_data); + node->custom_initial_data = custom_data; + node->custom_initial_data_size = custom_data_size; + + if (op->intermediates() && (op->intermediates()->size() > 0)) { + node->intermediates = + FlatBufferVectorToTfLiteTypeArray(op->intermediates()); + } + } + } + return kTfLiteOk; +} + +TfLiteStatus MicroInterpreter::AllocateTensors(bool run_all_prep_ops) { + SubgraphAllocations* allocations = allocator_.StartModelAllocation(model_); + + if (allocations == nullptr) { + MicroPrintf("Failed starting model allocation.\n"); + initialization_status_ = kTfLiteError; + return kTfLiteError; + } + + graph_.SetSubgraphAllocations(allocations); + + TF_LITE_ENSURE_STATUS(PrepareNodeAndRegistrationDataFromFlatbuffer()); + + // Only allow AllocatePersistentBuffer in Init stage. + context_.AllocatePersistentBuffer = MicroContextAllocatePersistentBuffer; + context_.RequestScratchBufferInArena = nullptr; + context_.GetScratchBuffer = nullptr; + context_.GetExternalContext = nullptr; + TF_LITE_ENSURE_STATUS(graph_.InitSubgraphs()); + + // Both AllocatePersistentBuffer and RequestScratchBufferInArena is + // available in Prepare stage. + context_.RequestScratchBufferInArena = + MicroContextRequestScratchBufferInArena; + // external_context become available in Prepare stage. + context_.GetExternalContext = MicroContextGetExternalContext; + + TF_LITE_ENSURE_STATUS(graph_.PrepareSubgraphs(run_all_prep_ops)); + + // Prepare is done, we're ready for Invoke. Memory allocation is no longer + // allowed. Kernels can only fetch scratch buffers via GetScratchBuffer. + context_.AllocatePersistentBuffer = nullptr; + context_.RequestScratchBufferInArena = nullptr; + context_.GetScratchBuffer = MicroContextGetScratchBuffer; + + TF_LITE_ENSURE_OK(&context_, allocator_.FinishModelAllocation( + model_, graph_.GetAllocations(), + &scratch_buffer_handles_)); + + micro_context_.SetScratchBufferHandles(scratch_buffer_handles_); + + // TODO(b/162311891): Drop these allocations when the interpreter supports + // handling buffers from TfLiteEvalTensor. + input_tensors_ = + reinterpret_cast(allocator_.AllocatePersistentBuffer( + sizeof(TfLiteTensor*) * inputs_size())); + if (input_tensors_ == nullptr) { + MicroPrintf( + "Failed to allocate memory for context->input_tensors_, " + "%d bytes required", + sizeof(TfLiteTensor*) * inputs_size()); + return kTfLiteError; + } + + for (size_t i = 0; i < inputs_size(); ++i) { + input_tensors_[i] = allocator_.AllocatePersistentTfLiteTensor( + model_, graph_.GetAllocations(), inputs().Get(i), 0); + if (input_tensors_[i] == nullptr) { + MicroPrintf("Failed to initialize input tensor %d", i); + return kTfLiteError; + } + } + + // TODO(b/162311891): Drop these allocations when the interpreter supports + // handling buffers from TfLiteEvalTensor. + output_tensors_ = + reinterpret_cast(allocator_.AllocatePersistentBuffer( + sizeof(TfLiteTensor*) * outputs_size())); + if (output_tensors_ == nullptr) { + MicroPrintf( + "Failed to allocate memory for context->output_tensors_, " + "%d bytes required", + sizeof(TfLiteTensor*) * outputs_size()); + return kTfLiteError; + } + + for (size_t i = 0; i < outputs_size(); ++i) { + output_tensors_[i] = allocator_.AllocatePersistentTfLiteTensor( + model_, graph_.GetAllocations(), outputs().Get(i), 0); + if (output_tensors_[i] == nullptr) { + MicroPrintf("Failed to initialize output tensor %d", i); + return kTfLiteError; + } + } + + TF_LITE_ENSURE_STATUS(Reset()); + +#ifdef EON_COMPILER_RUN + node_and_registrations_ = allocations->node_and_registrations; +#endif + + tensors_allocated_ = true; + return kTfLiteOk; +} + +TfLiteStatus MicroInterpreter::Invoke() { + if (initialization_status_ != kTfLiteOk) { + MicroPrintf("Invoke() called after initialization failed\n"); + return kTfLiteError; + } + + // Ensure tensors are allocated before the interpreter is invoked to avoid + // difficult to debug segfaults. + if (!tensors_allocated_) { + TF_LITE_ENSURE_OK(&context_, AllocateTensors(true)); + } + return graph_.InvokeSubgraph(0); +} + +TfLiteTensor* MicroInterpreter::input(size_t index) { + const size_t length = inputs_size(); + if (index >= length) { + MicroPrintf("Input index %d out of range (length is %d)", index, length); + return nullptr; + } + return input_tensors_[index]; +} + +TfLiteTensor* MicroInterpreter::output(size_t index) { + const size_t length = outputs_size(); + if (index >= length) { + MicroPrintf("Output index %d out of range (length is %d)", index, length); + return nullptr; + } + return output_tensors_[index]; +} + +TfLiteTensor* MicroInterpreter::tensor(size_t index, size_t subgraph_idx) { + const size_t length = tensors_size(subgraph_idx); + if (index >= length) { + MicroPrintf("Tensor index %d out of range (length is %d)", index, length); + return nullptr; + } + return allocator_.AllocatePersistentTfLiteTensor(model_, graph_.GetAllocations(), index, subgraph_idx); +} + +// Repurposing free subgraphs to reset state for some ops for now +// will reset api is made. See b/220940833#comment25 for more context. +TfLiteStatus MicroInterpreter::Reset() { + TfLiteStatus status = graph_.FreeSubgraphs(); + if (status != kTfLiteOk) { + return status; + } + return graph_.ResetVariableTensors(); +} + +TfLiteStatus MicroInterpreter::SetMicroExternalContext( + void* external_context_payload) { + return micro_context_.set_external_context(external_context_payload); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h new file mode 100644 index 0000000..5901372 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h @@ -0,0 +1,200 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_INTERPRETER_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_INTERPRETER_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_context.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_op_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_profiler_interface.h" +#include "edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h" + +/// Copied from tensorflow/lite/version.h to avoid a dependency chain into +// tensorflow/core. +#define TFLITE_SCHEMA_VERSION (3) + +namespace tflite { + +class MicroInterpreter { + public: + // The lifetime of the model, op resolver, tensor arena, error reporter, + // resource variables, and profiler must be at least as long as that of the + // interpreter object, since the interpreter may need to access them at any + // time. This means that you should usually create them with the same scope as + // each other, for example having them all allocated on the stack as local + // variables through a top-level function. The interpreter doesn't do any + // deallocation of any of the pointed-to objects, ownership remains with the + // caller. + MicroInterpreter(const Model* model, const MicroOpResolver& op_resolver, + uint8_t* tensor_arena, size_t tensor_arena_size, + MicroResourceVariables* resource_variables = nullptr, + MicroProfilerInterface* profiler = nullptr); + + // Create an interpreter instance using an existing MicroAllocator instance. + // This constructor should be used when creating an allocator that needs to + // have allocation handled in more than one interpreter or for recording + // allocations inside the interpreter. The lifetime of the allocator must be + // as long as that of the interpreter object. + MicroInterpreter(const Model* model, const MicroOpResolver& op_resolver, + MicroAllocator* allocator, + MicroResourceVariables* resource_variables = nullptr, + MicroProfilerInterface* profiler = nullptr); + + ~MicroInterpreter(); + + // Runs through the model and allocates all necessary input, output and + // intermediate tensors. + TfLiteStatus AllocateTensors(bool run_all_prep_ops); + + // In order to support partial graph runs for strided models, this can return + // values other than kTfLiteOk and kTfLiteError. + // TODO(b/149795762): Add this to the TfLiteStatus enum. + TfLiteStatus Invoke(); + + // This is the recommended API for an application to pass an external payload + // pointer as an external context to kernels. The life time of the payload + // pointer should be at least as long as this interpreter. TFLM supports only + // one external context. + TfLiteStatus SetMicroExternalContext(void* external_context_payload); + + size_t tensors_size(size_t subgraph_idx = 0) const { return model_->subgraphs()->Get(subgraph_idx)->tensors()->size(); } + + TfLiteTensor* tensor(size_t tensor_index, size_t subgraph_idx = 0); + + template + T* typed_tensor(int tensor_index) { + if (TfLiteTensor* tensor_ptr = tensor(tensor_index)) { + if (tensor_ptr->type == typeToTfLiteType()) { + return GetTensorData(tensor_ptr); + } + } + return nullptr; + } + + TfLiteTensor* input(size_t index); + size_t inputs_size() const { + return model_->subgraphs()->Get(0)->inputs()->size(); + } + const flatbuffers::Vector& inputs() const { + return *model_->subgraphs()->Get(0)->inputs(); + } + TfLiteTensor* input_tensor(size_t index) { return input(index); } + template + T* typed_input_tensor(int tensor_index) { + if (TfLiteTensor* tensor_ptr = input_tensor(tensor_index)) { + if (tensor_ptr->type == typeToTfLiteType()) { + return GetTensorData(tensor_ptr); + } + } + return nullptr; + } + + TfLiteTensor* output(size_t index); + size_t outputs_size() const { + return model_->subgraphs()->Get(0)->outputs()->size(); + } + const flatbuffers::Vector& outputs() const { + return *model_->subgraphs()->Get(0)->outputs(); + } + TfLiteTensor* output_tensor(size_t index) { return output(index); } + template + T* typed_output_tensor(int tensor_index) { + if (TfLiteTensor* tensor_ptr = output_tensor(tensor_index)) { + if (tensor_ptr->type == typeToTfLiteType()) { + return GetTensorData(tensor_ptr); + } + } + return nullptr; + } + + // Reset the state to be what you would expect when the interpreter is first + // created. i.e. after Init and Prepare is called for the very first time. + TfLiteStatus Reset(); + + TfLiteStatus initialization_status() const { return initialization_status_; } + +#ifdef EON_COMPILER_RUN + NodeAndRegistration* node_and_registrations_ = nullptr; + + size_t operators_size(uint32_t subgraph_idx = 0) const + { + return model_->subgraphs()->Get(subgraph_idx)->operators()->size(); + } + + const NodeAndRegistration node_and_registration(int node_index, int sg) + { + return graph_.GetAllocations()[sg].node_and_registrations[node_index]; + } +#endif + + // Populates node and registration pointers representing the inference graph + // of the model from values inside the flatbuffer (loaded from the TfLiteModel + // instance). Persistent data (e.g. operator data) is allocated from the + // arena. + TfLiteStatus PrepareNodeAndRegistrationDataFromFlatbuffer(); + + // For debugging only. + // Returns the actual used arena in bytes. This method gives the optimal arena + // size. It's only available after `AllocateTensors` has been called. + // Note that normally `tensor_arena` requires 16 bytes alignment to fully + // utilize the space. If it's not the case, the optimial arena size would be + // arena_used_bytes() + 16. + size_t arena_used_bytes() const { return allocator_.used_bytes(); } + + protected: + const MicroAllocator& allocator() const { return allocator_; } + const TfLiteContext& context() const { return context_; } + + private: + // TODO(b/158263161): Consider switching to Create() function to enable better + // error reporting during initialization. + void Init(MicroProfilerInterface* profiler); + + // Gets the current subgraph index used from within context methods. + int get_subgraph_index() { return graph_.GetCurrentSubgraphIndex(); } + + const Model* model_; + const MicroOpResolver& op_resolver_; + TfLiteContext context_ = {}; + MicroAllocator& allocator_; + MicroGraph graph_; + bool tensors_allocated_; + + TfLiteStatus initialization_status_; + + ScratchBufferHandle* scratch_buffer_handles_ = nullptr; + + // TODO(b/162311891): Clean these pointers up when this class supports buffers + // from TfLiteEvalTensor. + TfLiteTensor** input_tensors_; + TfLiteTensor** output_tensors_; + + MicroContext micro_context_; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_INTERPRETER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_log.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_log.cpp new file mode 100644 index 0000000..26282ca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_log.cpp @@ -0,0 +1,47 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +#include +#include +#include + +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) +#include "edge-impulse-sdk/tensorflow/lite/micro/debug_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_string.h" +#endif + +void Log(const char* format, va_list args) { +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) + // Only pulling in the implementation of this function for builds where we + // expect to make use of it to be extra cautious about not increasing the code + // size. + static constexpr int kMaxLogLen = 256; + char log_buffer[kMaxLogLen]; + MicroVsnprintf(log_buffer, kMaxLogLen, format, args); + DebugLog(log_buffer); + DebugLog("\r\n"); +#endif +} + +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) +void MicroPrintf(const char* format, ...) { + va_list args; + va_start(args, format); + Log(format, args); + va_end(args); +} +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_log.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_log.h new file mode 100644 index 0000000..22cceb2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_log.h @@ -0,0 +1,49 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_LOG_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_LOG_H_ + +#include + +// do this by default except when running EON compiler +#ifndef EON_COMPILER_RUN +#define TF_LITE_STRIP_ERROR_STRINGS +#endif + +// This is a free function used to perform the actual logging. +// This function will be used by MicroPrintf and MicroErrorReporter::Report() +void Log(const char* format, va_list args); + +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) +// This function can be used independent of the MicroErrorReporter to get +// printf-like functionalitys and are common to all target platforms. +void MicroPrintf(const char* format, ...); +#else +// We use a #define to ensure that the strings are completely stripped, to +// prevent an unnecessary increase in the binary size. +#define MicroPrintf(...) tflite::Unused(__VA_ARGS__) +#endif + +namespace tflite { + +// From +// https://stackoverflow.com/questions/23235910/variadic-unused-function-macro +template +void Unused(Args&&... args) { + (void)(sizeof...(args)); +} +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_LOG_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_mutable_op_resolver.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_mutable_op_resolver.h new file mode 100644 index 0000000..798787a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_mutable_op_resolver.h @@ -0,0 +1,676 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_MUTABLE_OP_RESOLVER_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_MUTABLE_OP_RESOLVER_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/flatbuffer_conversions.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/add.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/conv.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/depthwise_conv.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/ethosu.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/tree_ensemble_classifier.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/fully_connected.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/pooling.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/reduce.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/softmax.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_op_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { +TfLiteRegistration* Register_DETECTION_POSTPROCESS(); + +template +class MicroMutableOpResolver : public MicroOpResolver { + public: + TF_LITE_REMOVE_VIRTUAL_DELETE + + explicit MicroMutableOpResolver() {} + + const TfLiteRegistration* FindOp(tflite::BuiltinOperator op) const override { + if (op == BuiltinOperator_CUSTOM) return nullptr; + + for (unsigned int i = 0; i < registrations_len_; ++i) { + const TfLiteRegistration& registration = registrations_[i]; + if (registration.builtin_code == op) { + return ®istration; + } + } + return nullptr; + } + + const TfLiteRegistration* FindOp(const char* op) const override { + for (unsigned int i = 0; i < registrations_len_; ++i) { + const TfLiteRegistration& registration = registrations_[i]; + if ((registration.builtin_code == BuiltinOperator_CUSTOM) && + (strcmp(registration.custom_name, op) == 0)) { + return ®istration; + } + } + return nullptr; + } + + TfLiteBridgeBuiltinParseFunction GetOpDataParser( + BuiltinOperator op) const override { + TFLITE_DCHECK(num_buitin_ops_ <= tOpCount); + for (unsigned int i = 0; i < num_buitin_ops_; ++i) { + if (builtin_codes_[i] == op) return builtin_parsers_[i]; + } + return nullptr; + } + + // Registers a Custom Operator with the MicroOpResolver. + // + // Only the first call for a given name will be successful. i.e. if this + // function is called again for a previously added Custom Operator, the + // MicroOpResolver will be unchanged and this function will return + // kTfLiteError. + TfLiteStatus AddCustom(const char* name, TfLiteRegistration* registration) { + if (registrations_len_ >= tOpCount) { + MicroPrintf( + "Couldn't register custom op '%s', resolver size is too" + "small (%d)", + name, tOpCount); + return kTfLiteError; + } + + if (FindOp(name) != nullptr) { + MicroPrintf("Calling AddCustom for the same op more than once "); + MicroPrintf("is not supported (Op: %s).", name); + return kTfLiteError; + } + + TfLiteRegistration* new_registration = ®istrations_[registrations_len_]; + registrations_len_ += 1; + + *new_registration = *registration; + new_registration->builtin_code = BuiltinOperator_CUSTOM; + new_registration->custom_name = name; + return kTfLiteOk; + } + + // The Add* functions below add the various Builtin operators to the + // MicroMutableOpResolver object. + + TfLiteStatus AddAbs() { + return AddBuiltin(BuiltinOperator_ABS, tflite::ops::micro::Register_ABS(), + ParseAbs); + } + + TfLiteStatus AddAdd(const TfLiteRegistration& registration = Register_ADD()) { + return AddBuiltin(BuiltinOperator_ADD, registration, ParseAdd); + } + + TfLiteStatus AddAddN() { + return AddBuiltin(BuiltinOperator_ADD_N, tflite::Register_ADD_N(), + ParseAddN); + } + + TfLiteStatus AddArgMax() { + return AddBuiltin(BuiltinOperator_ARG_MAX, Register_ARG_MAX(), ParseArgMax); + } + + TfLiteStatus AddArgMin() { + return AddBuiltin(BuiltinOperator_ARG_MIN, Register_ARG_MIN(), ParseArgMin); + } + + TfLiteStatus AddAssignVariable() { + return AddBuiltin(BuiltinOperator_ASSIGN_VARIABLE, + tflite::Register_ASSIGN_VARIABLE(), ParseAssignVariable); + } + + TfLiteStatus AddAveragePool2D( + const TfLiteRegistration& registration = Register_AVERAGE_POOL_2D()) { + return AddBuiltin(BuiltinOperator_AVERAGE_POOL_2D, registration, ParsePool); + } + + TfLiteStatus AddBatchMatMul() { + return AddBuiltin(BuiltinOperator_BATCH_MATMUL, + Register_BATCH_MATMUL(), ParseBatchMatMul); + } + + TfLiteStatus AddBatchToSpaceNd() { + return AddBuiltin(BuiltinOperator_BATCH_TO_SPACE_ND, + Register_BATCH_TO_SPACE_ND(), ParseBatchToSpaceNd); + } + + TfLiteStatus AddBroadcastArgs() { + return AddBuiltin(BuiltinOperator_BROADCAST_ARGS, Register_BROADCAST_ARGS(), + ParseBroadcastArgs); + } + + TfLiteStatus AddBroadcastTo() { + return AddBuiltin(BuiltinOperator_BROADCAST_TO, Register_BROADCAST_TO(), + ParseBroadcastTo); + } + + TfLiteStatus AddCallOnce() { + return AddBuiltin(BuiltinOperator_CALL_ONCE, Register_CALL_ONCE(), + ParseCallOnce); + } + + TfLiteStatus AddCast() { + return AddBuiltin(BuiltinOperator_CAST, Register_CAST(), ParseCast); + } + + TfLiteStatus AddCeil() { + return AddBuiltin(BuiltinOperator_CEIL, Register_CEIL(), ParseCeil); + } + + TfLiteStatus AddComplexAbs() { + return AddBuiltin(BuiltinOperator_COMPLEX_ABS, Register_COMPLEX_ABS(), + ParseComplexAbs); + } + + TfLiteStatus AddCircularBuffer() { + return AddCustom("CIRCULAR_BUFFER", tflite::Register_CIRCULAR_BUFFER()); + } + + TfLiteStatus AddConcatenation() { + return AddBuiltin(BuiltinOperator_CONCATENATION, Register_CONCATENATION(), + ParseConcatenation); + } + + TfLiteStatus AddConv2D( + const TfLiteRegistration& registration = Register_CONV_2D()) { + return AddBuiltin(BuiltinOperator_CONV_2D, registration, ParseConv2D); + } + + TfLiteStatus AddCos() { + return AddBuiltin(BuiltinOperator_COS, tflite::ops::micro::Register_COS(), + ParseCos); + } + + TfLiteStatus AddCumSum() { + return AddBuiltin(BuiltinOperator_CUMSUM, tflite::Register_CUMSUM(), + ParseCumsum); + } + + TfLiteStatus AddDepthToSpace() { + return AddBuiltin(BuiltinOperator_DEPTH_TO_SPACE, + tflite::Register_DEPTH_TO_SPACE(), ParseDepthToSpace); + } + + TfLiteStatus AddDepthwiseConv2D( + const TfLiteRegistration& registration = Register_DEPTHWISE_CONV_2D()) { + return AddBuiltin(BuiltinOperator_DEPTHWISE_CONV_2D, registration, + ParseDepthwiseConv2D); + } + + TfLiteStatus AddDequantize() { + return AddBuiltin(BuiltinOperator_DEQUANTIZE, tflite::Register_DEQUANTIZE(), + ParseDequantize); + } + + TfLiteStatus AddDetectionPostprocess() { + return AddCustom("TFLite_Detection_PostProcess", + tflite::Register_DETECTION_POSTPROCESS()); + } + + TfLiteStatus AddDiv() { + return AddBuiltin(BuiltinOperator_DIV, tflite::Register_DIV(), ParseDiv); + } + + TfLiteStatus AddElu() { + return AddBuiltin(BuiltinOperator_ELU, tflite::Register_ELU(), ParseElu); + } + + TfLiteStatus AddEqual() { + return AddBuiltin(BuiltinOperator_EQUAL, Register_EQUAL(), ParseEqual); + } + + TfLiteStatus AddEthosU() { + TfLiteRegistration* registration = tflite::Register_ETHOSU(); + if (registration) { + return AddCustom(tflite::GetString_ETHOSU(), registration); + } + return kTfLiteOk; + } + + TfLiteStatus AddExp() { + return AddBuiltin(BuiltinOperator_EXP, Register_EXP(), ParseExp); + } + + TfLiteStatus AddExpandDims() { + return AddBuiltin(BuiltinOperator_EXPAND_DIMS, Register_EXPAND_DIMS(), + ParseExpandDims); + } + + TfLiteStatus AddFill() { + return AddBuiltin(BuiltinOperator_FILL, tflite::Register_FILL(), ParseFill); + } + + TfLiteStatus AddFloor() { + return AddBuiltin(BuiltinOperator_FLOOR, Register_FLOOR(), ParseFloor); + } + + TfLiteStatus AddFloorDiv() { + return AddBuiltin(BuiltinOperator_FLOOR_DIV, tflite::Register_FLOOR_DIV(), + ParseFloorDiv); + } + + TfLiteStatus AddFloorMod() { + return AddBuiltin(BuiltinOperator_FLOOR_MOD, tflite::Register_FLOOR_MOD(), + ParseFloorMod); + } + + TfLiteStatus AddFullyConnected( + const TfLiteRegistration& registration = Register_FULLY_CONNECTED()) { + return AddBuiltin(BuiltinOperator_FULLY_CONNECTED, registration, + ParseFullyConnected); + } + +#ifndef TF_LITE_STATIC_MEMORY + TfLiteStatus AddGather() { + return AddBuiltin(BuiltinOperator_GATHER, tflite::Register_GATHER(), + ParseGather); + } +#endif + + TfLiteStatus AddGatherNd() { + return AddBuiltin(BuiltinOperator_GATHER_ND, tflite::Register_GATHER_ND(), + ParseGatherNd); + } + + TfLiteStatus AddGreater() { + return AddBuiltin(BuiltinOperator_GREATER, Register_GREATER(), + ParseGreater); + } + + TfLiteStatus AddGreaterEqual() { + return AddBuiltin(BuiltinOperator_GREATER_EQUAL, Register_GREATER_EQUAL(), + ParseGreaterEqual); + } + + TfLiteStatus AddHardSwish() { + return AddBuiltin(BuiltinOperator_HARD_SWISH, tflite::Register_HARD_SWISH(), + ParseHardSwish); + } + + TfLiteStatus AddImag() { + return AddBuiltin(BuiltinOperator_IMAG, Register_IMAG(), + ParseImag); + } + + TfLiteStatus AddIf() { + return AddBuiltin(BuiltinOperator_IF, tflite::Register_IF(), ParseIf); + } + + TfLiteStatus AddL2Normalization() { + return AddBuiltin(BuiltinOperator_L2_NORMALIZATION, + tflite::ops::micro::Register_L2_NORMALIZATION(), + ParseL2Normalization); + } + + TfLiteStatus AddL2Pool2D() { + return AddBuiltin(BuiltinOperator_L2_POOL_2D, tflite::Register_L2_POOL_2D(), + ParsePool); + } + + TfLiteStatus AddLeakyRelu() { + return AddBuiltin(BuiltinOperator_LEAKY_RELU, tflite::Register_LEAKY_RELU(), + ParseLeakyRelu); + } + + TfLiteStatus AddLess() { + return AddBuiltin(BuiltinOperator_LESS, Register_LESS(), ParseLess); + } + + TfLiteStatus AddLessEqual() { + return AddBuiltin(BuiltinOperator_LESS_EQUAL, Register_LESS_EQUAL(), + ParseLessEqual); + } + + TfLiteStatus AddLog() { + return AddBuiltin(BuiltinOperator_LOG, tflite::ops::micro::Register_LOG(), + ParseLog); + } + + TfLiteStatus AddLogicalAnd() { + return AddBuiltin(BuiltinOperator_LOGICAL_AND, + tflite::Register_LOGICAL_AND(), ParseLogicalAnd); + } + + TfLiteStatus AddLogicalNot() { + return AddBuiltin(BuiltinOperator_LOGICAL_NOT, + tflite::ops::micro::Register_LOGICAL_NOT(), + ParseLogicalNot); + } + + TfLiteStatus AddLogicalOr() { + return AddBuiltin(BuiltinOperator_LOGICAL_OR, tflite::Register_LOGICAL_OR(), + ParseLogicalOr); + } + + TfLiteStatus AddLogistic() { + return AddBuiltin(BuiltinOperator_LOGISTIC, tflite::Register_LOGISTIC(), + ParseLogistic); + } + + TfLiteStatus AddLogSoftmax() { + return AddBuiltin(BuiltinOperator_LOG_SOFTMAX, + tflite::Register_LOG_SOFTMAX(), ParseLogSoftmax); + } + + TfLiteStatus AddMaximum() { + return AddBuiltin(BuiltinOperator_MAXIMUM, Register_MAXIMUM(), + ParseMaximum); + } + + TfLiteStatus AddMaxPool2D( + const TfLiteRegistration& registration = Register_MAX_POOL_2D()) { + return AddBuiltin(BuiltinOperator_MAX_POOL_2D, registration, ParsePool); + } + + TfLiteStatus AddMirrorPad() { + return AddBuiltin(BuiltinOperator_MIRROR_PAD, tflite::Register_MIRROR_PAD(), + ParseMirrorPad); + } + + TfLiteStatus AddMean() { + return AddBuiltin(BuiltinOperator_MEAN, Register_MEAN(), ParseReducer); + } + + TfLiteStatus AddMinimum() { + return AddBuiltin(BuiltinOperator_MINIMUM, Register_MINIMUM(), + ParseMinimum); + } + + TfLiteStatus AddMul(const TfLiteRegistration& registration = Register_MUL()) { + return AddBuiltin(BuiltinOperator_MUL, registration, ParseMul); + } + + TfLiteStatus AddNeg() { + return AddBuiltin(BuiltinOperator_NEG, Register_NEG(), ParseNeg); + } + + TfLiteStatus AddNotEqual() { + return AddBuiltin(BuiltinOperator_NOT_EQUAL, Register_NOT_EQUAL(), + ParseNotEqual); + } + + TfLiteStatus AddPack() { + return AddBuiltin(BuiltinOperator_PACK, Register_PACK(), ParsePack); + } + + TfLiteStatus AddPad(const TfLiteRegistration& registration = Register_PAD()) { + return AddBuiltin(BuiltinOperator_PAD, registration, ParsePad); + } + + TfLiteStatus AddPadV2() { + return AddBuiltin(BuiltinOperator_PADV2, Register_PADV2(), ParsePadV2); + } + + TfLiteStatus AddPrelu() { + return AddBuiltin(BuiltinOperator_PRELU, tflite::Register_PRELU(), + ParsePrelu); + } + + TfLiteStatus AddQuantize() { + return AddBuiltin(BuiltinOperator_QUANTIZE, Register_QUANTIZE(), + ParseQuantize); + } + + TfLiteStatus AddReal() { + return AddBuiltin(BuiltinOperator_REAL, Register_REAL(), + ParseReal); + } + + TfLiteStatus AddReadVariable() { + return AddBuiltin(BuiltinOperator_READ_VARIABLE, + tflite::Register_READ_VARIABLE(), ParseReadVariable); + } + + TfLiteStatus AddReduceMax() { + return AddBuiltin(BuiltinOperator_REDUCE_MAX, Register_REDUCE_MAX(), + ParseReducer); + } + + TfLiteStatus AddReduceMin() { + return AddBuiltin(BuiltinOperator_REDUCE_MIN, Register_REDUCE_MIN(), + ParseReducer); + } + + TfLiteStatus AddRelu() { + return AddBuiltin(BuiltinOperator_RELU, tflite::Register_RELU(), ParseRelu); + } + + TfLiteStatus AddRelu6() { + return AddBuiltin(BuiltinOperator_RELU6, tflite::Register_RELU6(), + ParseRelu6); + } + + TfLiteStatus AddReshape() { + return AddBuiltin(BuiltinOperator_RESHAPE, + tflite::ops::micro::Register_RESHAPE(), ParseReshape); + } + + TfLiteStatus AddResizeBilinear() { + return AddBuiltin(BuiltinOperator_RESIZE_BILINEAR, + Register_RESIZE_BILINEAR(), ParseResizeBilinear); + } + + TfLiteStatus AddResizeNearestNeighbor() { + return AddBuiltin(BuiltinOperator_RESIZE_NEAREST_NEIGHBOR, + tflite::ops::micro::Register_RESIZE_NEAREST_NEIGHBOR(), + ParseResizeNearestNeighbor); + } + + TfLiteStatus AddRfft2D() { + return AddBuiltin(BuiltinOperator_RFFT2D, Register_RFFT2D(), + ParseRfft2D); + } + + TfLiteStatus AddRound() { + return AddBuiltin(BuiltinOperator_ROUND, + tflite::ops::micro::Register_ROUND(), ParseRound); + } + + TfLiteStatus AddRsqrt() { + return AddBuiltin(BuiltinOperator_RSQRT, + tflite::ops::micro::Register_RSQRT(), ParseRsqrt); + } + +#ifndef TF_LITE_STATIC_MEMORY + TfLiteStatus AddSelect() { + return AddBuiltin(BuiltinOperator_SELECT, Register_SELECT(), + ParseSelect); + } + + TfLiteStatus AddSelectV2() { + return AddBuiltin(BuiltinOperator_SELECT_V2, Register_SELECT_V2(), + ParseSelect); + } +#endif // TF_LITE_STATIC_MEMORY + + TfLiteStatus AddShape() { + return AddBuiltin(BuiltinOperator_SHAPE, Register_SHAPE(), ParseShape); + } + + TfLiteStatus AddSin() { + return AddBuiltin(BuiltinOperator_SIN, tflite::ops::micro::Register_SIN(), + ParseSin); + } + + TfLiteStatus AddSlice() { + return AddBuiltin(BuiltinOperator_SLICE, Register_SLICE(), ParseSlice); + } + + TfLiteStatus AddSoftmax( + const TfLiteRegistration& registration = Register_SOFTMAX()) { + return AddBuiltin(BuiltinOperator_SOFTMAX, registration, ParseSoftmax); + } + + TfLiteStatus AddSpaceToBatchNd() { + return AddBuiltin(BuiltinOperator_SPACE_TO_BATCH_ND, + Register_SPACE_TO_BATCH_ND(), ParseSpaceToBatchNd); + } + + TfLiteStatus AddSpaceToDepth() { + return AddBuiltin(BuiltinOperator_SPACE_TO_DEPTH, Register_SPACE_TO_DEPTH(), + ParseSpaceToDepth); + } + + TfLiteStatus AddSplit() { + return AddBuiltin(BuiltinOperator_SPLIT, + tflite::ops::micro::Register_SPLIT(), ParseSplit); + } + + TfLiteStatus AddSplitV() { + return AddBuiltin(BuiltinOperator_SPLIT_V, Register_SPLIT_V(), ParseSplitV); + } + + TfLiteStatus AddSqueeze() { + return AddBuiltin(BuiltinOperator_SQUEEZE, Register_SQUEEZE(), + ParseSqueeze); + } + + TfLiteStatus AddSqrt() { + return AddBuiltin(BuiltinOperator_SQRT, tflite::ops::micro::Register_SQRT(), + ParseSqrt); + } + + TfLiteStatus AddSquare() { + return AddBuiltin(BuiltinOperator_SQUARE, + tflite::ops::micro::Register_SQUARE(), ParseSquare); + } + + TfLiteStatus AddSquaredDifference() { + return AddBuiltin(BuiltinOperator_SQUARED_DIFFERENCE, + tflite::Register_SQUARED_DIFFERENCE(), + ParseSquaredDifference); + } + + TfLiteStatus AddStridedSlice() { + return AddBuiltin(BuiltinOperator_STRIDED_SLICE, Register_STRIDED_SLICE(), + ParseStridedSlice); + } + + TfLiteStatus AddSub() { + return AddBuiltin(BuiltinOperator_SUB, tflite::Register_SUB(), ParseSub); + } + + TfLiteStatus AddSum() { + return AddBuiltin(BuiltinOperator_SUM, Register_SUM(), ParseReducer); + } + + TfLiteStatus AddSvdf( + const TfLiteRegistration& registration = Register_SVDF()) { + return AddBuiltin(BuiltinOperator_SVDF, registration, ParseSvdf); + } + + TfLiteStatus AddTanh() { + return AddBuiltin(BuiltinOperator_TANH, tflite::ops::micro::Register_TANH(), + ParseTanh); + } + + TfLiteStatus AddTransposeConv() { + return AddBuiltin(BuiltinOperator_TRANSPOSE_CONV, + tflite::Register_TRANSPOSE_CONV(), ParseTransposeConv); + } + + TfLiteStatus AddTranspose() { + return AddBuiltin(BuiltinOperator_TRANSPOSE, Register_TRANSPOSE(), + ParseTranspose); + } + + TfLiteStatus AddTreeEnsembleClassifier() { + return AddCustom(tflite::GetString_TreeEnsembleClassifier(), + tflite::Register_TreeEnsembleClassifier()); + } + + TfLiteStatus AddUnpack() { + return AddBuiltin(BuiltinOperator_UNPACK, + tflite::ops::micro::Register_UNPACK(), ParseUnpack); + } + + TfLiteStatus AddUnidirectionalSequenceLstm() { + return AddBuiltin(BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM, + Register_UNIDIRECTIONAL_SEQUENCE_LSTM(), + ParseUnidirectionalSequenceLSTM); + } + + TfLiteStatus AddVarHandle() { + return AddBuiltin(BuiltinOperator_VAR_HANDLE, Register_VAR_HANDLE(), + ParseVarHandle); + } + + TfLiteStatus AddWhile() { + return AddBuiltin(BuiltinOperator_WHILE, Register_WHILE(), ParseWhile); + } + + TfLiteStatus AddZerosLike() { + return AddBuiltin(BuiltinOperator_ZEROS_LIKE, Register_ZEROS_LIKE(), + ParseZerosLike); + } + + unsigned int GetRegistrationLength() { return registrations_len_; } + + private: + TfLiteStatus AddBuiltin(tflite::BuiltinOperator op, + const TfLiteRegistration& registration, + TfLiteBridgeBuiltinParseFunction parser) { + if (op == BuiltinOperator_CUSTOM) { + MicroPrintf("Invalid parameter BuiltinOperator_CUSTOM to the "); + MicroPrintf("AddBuiltin function."); + return kTfLiteError; + } + + if (FindOp(op) != nullptr) { + MicroPrintf("Calling AddBuiltin with the same op more than "); + MicroPrintf("once is not supported (Op: #%d).", op); + return kTfLiteError; + } + + if (registrations_len_ >= tOpCount) { + MicroPrintf("Couldn't register builtin op #%d, resolver size ", op); + MicroPrintf("is too small (%d).", tOpCount); + return kTfLiteError; + } + + registrations_[registrations_len_] = registration; + // Strictly speaking, the builtin_code is not necessary for TFLM but filling + // it in regardless. + registrations_[registrations_len_].builtin_code = op; + registrations_len_++; + + builtin_codes_[num_buitin_ops_] = op; + builtin_parsers_[num_buitin_ops_] = parser; + num_buitin_ops_++; + + return kTfLiteOk; + } + + TfLiteRegistration registrations_[tOpCount]; + unsigned int registrations_len_ = 0; + + // Arrays (and counter) to store the builtin codes and their corresponding + // parse functions as these are registered with the Op Resolver. + BuiltinOperator builtin_codes_[tOpCount]; + TfLiteBridgeBuiltinParseFunction builtin_parsers_[tOpCount]; + unsigned int num_buitin_ops_ = 0; +}; + +}; // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_MUTABLE_OP_RESOLVER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_op_resolver.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_op_resolver.h new file mode 100644 index 0000000..1bd3f4b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_op_resolver.h @@ -0,0 +1,68 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_OP_RESOLVER_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_OP_RESOLVER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/flatbuffer_conversions_bridge.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +// This is an interface for the OpResolver for TFLiteMicro. The differences from +// the TFLite OpResolver base class are to: +// * explicitly remove support for Op versions +// * allow for finer grained registration of the Builtin Ops to reduce code +// size for TFLiteMicro. +// +// We need an interface class instead of directly using MicroMutableOpResolver +// because MicroMutableOpResolver is a class template with the number of +// registered Ops as the template parameter. +class MicroOpResolver : public TfLiteBridgeOpResolver { + public: + // Returns the Op registration struct corresponding to the enum code from the + // flatbuffer schema. Returns nullptr if the op is not found or if op == + // BuiltinOperator_CUSTOM. + virtual const TfLiteRegistration* FindOp(BuiltinOperator op) const = 0; + + // Returns the Op registration struct corresponding to the custom operator by + // name. + virtual const TfLiteRegistration* FindOp(const char* op) const = 0; + + // This implementation exists for compatibility with the OpResolver base class + // and disregards the version parameter. + const TfLiteRegistration* FindOp(BuiltinOperator op, + int version) const final { + return FindOp(op); + } + + // This implementation exists for compatibility with the OpResolver base class + // and disregards the version parameter. + const TfLiteRegistration* FindOp(const char* op, int version) const final { + return FindOp(op); + } + + // Returns the operator specific parsing function for the OpData for a + // BuiltinOperator (if registered), else nullptr. + virtual TfLiteBridgeBuiltinParseFunction GetOpDataParser( + BuiltinOperator op) const = 0; + + ~MicroOpResolver() override {} +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_OP_RESOLVER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.cpp new file mode 100644 index 0000000..63306ce --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.cpp @@ -0,0 +1,115 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_time.h" + +namespace tflite { + +uint32_t MicroProfiler::BeginEvent(const char* tag) { + if (num_events_ == kMaxEvents) { + num_events_ = 0; + } + + tags_[num_events_] = tag; + start_ticks_[num_events_] = GetCurrentTimeTicks(); + end_ticks_[num_events_] = start_ticks_[num_events_] - 1; + return num_events_++; +} + +void MicroProfiler::EndEvent(uint32_t event_handle) { + TFLITE_DCHECK(event_handle < kMaxEvents); + end_ticks_[event_handle] = GetCurrentTimeTicks(); +} + +uint32_t MicroProfiler::GetTotalTicks() const { + int32_t ticks = 0; + for (int i = 0; i < num_events_; ++i) { + ticks += end_ticks_[i] - start_ticks_[i]; + } + return ticks; +} + +void MicroProfiler::Log() const { +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) + for (int i = 0; i < num_events_; ++i) { + uint32_t ticks = end_ticks_[i] - start_ticks_[i]; + MicroPrintf("%s took %" PRIu32 " ticks (%d ms).", tags_[i], ticks, + TicksToMs(ticks)); + } +#endif +} + +void MicroProfiler::LogCsv() const { +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) + MicroPrintf("\"Event\",\"Tag\",\"Ticks\""); + for (int i = 0; i < num_events_; ++i) { + uint32_t ticks = end_ticks_[i] - start_ticks_[i]; + MicroPrintf("%d,%s,%" PRIu32, i, tags_[i], ticks); + } +#endif +} + +void MicroProfiler::LogTicksPerTagCsv() { +#if !defined(TF_LITE_STRIP_ERROR_STRINGS) + MicroPrintf( + "\"Unique Tag\",\"Total ticks across all events with that tag.\""); + int total_ticks = 0; + for (int i = 0; i < num_events_; ++i) { + uint32_t ticks = end_ticks_[i] - start_ticks_[i]; + TFLITE_DCHECK(tags_[i] != nullptr); + int position = FindExistingOrNextPosition(tags_[i]); + TFLITE_DCHECK(position >= 0); + total_ticks_per_tag[position].tag = tags_[i]; + total_ticks_per_tag[position].ticks = + total_ticks_per_tag[position].ticks + ticks; + total_ticks += ticks; + } + + for (int i = 0; i < num_events_; ++i) { + TicksPerTag each_tag_entry = total_ticks_per_tag[i]; + if (each_tag_entry.tag == nullptr) { + break; + } + MicroPrintf("%s, %d", each_tag_entry.tag, each_tag_entry.ticks); + } + MicroPrintf("total number of ticks, %d", total_ticks); +#endif +} + +// This method finds a particular array element in the total_ticks_per_tag array +// with the matching tag_name passed in the method. If it can find a +// matching array element that has the same tag_name, then it will return the +// position of the matching element. But if it unable to find a matching element +// with the given tag_name, it will return the next available empty position +// from the array. +int MicroProfiler::FindExistingOrNextPosition(const char* tag_name) { + int pos = 0; + for (; pos < num_events_; pos++) { + TicksPerTag each_tag_entry = total_ticks_per_tag[pos]; + if (each_tag_entry.tag == nullptr || + strcmp(each_tag_entry.tag, tag_name) == 0) { + return pos; + } + } + return pos < num_events_ ? pos : -1; +} +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.h new file mode 100644 index 0000000..d940398 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler.h @@ -0,0 +1,140 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MICRO_PROFILER_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_PROFILER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_profiler_interface.h" + +namespace tflite { + +// MicroProfiler creates a common way to gain fine-grained insight into runtime +// performance. Bottleck operators can be identified along with slow code +// sections. This can be used in conjunction with running the relevant micro +// benchmark to evaluate end-to-end performance. +class MicroProfiler : public MicroProfilerInterface { + public: + MicroProfiler() = default; + virtual ~MicroProfiler() = default; + + // Marks the start of a new event and returns an event handle that can be used + // to mark the end of the event via EndEvent. The lifetime of the tag + // parameter must exceed that of the MicroProfiler. + virtual uint32_t BeginEvent(const char* tag) override; + + // Marks the end of an event associated with event_handle. It is the + // responsibility of the caller to ensure than EndEvent is called once and + // only once per event_handle. + // + // If EndEvent is called more than once for the same event_handle, the last + // call will be used as the end of event marker.If EndEvent is called 0 times + // for a particular event_handle, the duration of that event will be 0 ticks. + virtual void EndEvent(uint32_t event_handle) override; + + // Clears all the events that have been currently profiled. + void ClearEvents() { num_events_ = 0; } + + // Returns the sum of the ticks taken across all the events. This number + // is only meaningful if all of the events are disjoint (the end time of + // event[i] <= start time of event[i+1]). + uint32_t GetTotalTicks() const; + + // Prints the profiling information of each of the events in human readable + // form. + void Log() const; + + // Prints the profiling information of each of the events in CSV (Comma + // Separated Value) form. + void LogCsv() const; + + // Prints total ticks for each unique tag in CSV format. + // Output will have one row for each unique tag along with the + // total ticks summed across all events with that particular tag. + void LogTicksPerTagCsv(); + + private: + // Maximum number of events that this class can keep track of. If we call + // AddEvent more than kMaxEvents number of times, then the oldest event's + // profiling information will be overwritten. + static constexpr int kMaxEvents = 1024; + + const char* tags_[kMaxEvents]; + uint32_t start_ticks_[kMaxEvents]; + uint32_t end_ticks_[kMaxEvents]; + int num_events_ = 0; + + struct TicksPerTag { + const char* tag; + uint32_t ticks; + }; + // In practice, the number of tags will be much lower than the number of + // events. But it is theoretically possible that each event to be unique and + // hence we allow total_ticks_per_tag to have kMaxEvents entries. + TicksPerTag total_ticks_per_tag[kMaxEvents] = {}; + + int FindExistingOrNextPosition(const char* tag_name); + + TF_LITE_REMOVE_VIRTUAL_DELETE; +}; + +#if defined(TF_LITE_STRIP_ERROR_STRINGS) +// For release builds, the ScopedMicroProfiler is a noop. +// +// This is done because the ScipedProfiler is used as part of the +// MicroInterpreter and we want to ensure zero overhead for the release builds. +class ScopedMicroProfiler { + public: + explicit ScopedMicroProfiler(const char* tag, + MicroProfilerInterface* profiler) {} +}; + +#else + +// This class can be used to add events to a MicroProfiler object that span the +// lifetime of the ScopedMicroProfiler object. +// Usage example: +// +// MicroProfiler profiler(); +// ... +// { +// ScopedMicroProfiler scoped_profiler("custom_tag", profiler); +// work_to_profile(); +// } +class ScopedMicroProfiler { + public: + explicit ScopedMicroProfiler(const char* tag, + MicroProfilerInterface* profiler) + : profiler_(profiler) { + if (profiler_ != nullptr) { + event_handle_ = profiler_->BeginEvent(tag); + } + } + + ~ScopedMicroProfiler() { + if (profiler_ != nullptr) { + profiler_->EndEvent(event_handle_); + } + } + + private: + uint32_t event_handle_ = 0; + MicroProfilerInterface* profiler_ = nullptr; +}; +#endif // !defined(TF_LITE_STRIP_ERROR_STRINGS) + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_PROFILER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler_interface.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler_interface.h new file mode 100644 index 0000000..f839a74 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_profiler_interface.h @@ -0,0 +1,38 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MICRO_PROFILER_INTERFACE_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_PROFILER_INTERFACE_H_ + +#include + +namespace tflite { + +// Interface class that the TFLM framework relies on for profiling. +class MicroProfilerInterface { + public: + virtual ~MicroProfilerInterface() {} + + // Marks the start of a new event and returns an event handle that can be used + // to mark the end of the event via EndEvent. + virtual uint32_t BeginEvent(const char* tag) = 0; + + // Marks the end of an event associated with event_handle. + virtual void EndEvent(uint32_t event_handle) = 0; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_PROFILER_INTERFACE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.cpp new file mode 100644 index 0000000..c07d111 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.cpp @@ -0,0 +1,148 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +namespace tflite { + +namespace {} // namespace + +MicroResourceVariables* MicroResourceVariables::Create( + MicroAllocator* allocator, int max_num_variables) { + TFLITE_DCHECK(allocator != nullptr); + + uint8_t* allocator_buffer = static_cast( + allocator->AllocatePersistentBuffer(sizeof(MicroResourceVariables))); + MicroResourceVariable* variable_array = + static_cast(allocator->AllocatePersistentBuffer( + sizeof(MicroResourceVariable) * max_num_variables)); + MicroResourceVariables* variables = new (allocator_buffer) + MicroResourceVariables(variable_array, max_num_variables); + return variables; +} + +int MicroResourceVariables::CreateIdIfNoneFound(const char* container, + const char* shared_name) { + int resource_id = FindId(container, shared_name); + if (resource_id >= 0) { + return resource_id; + } + + // no existing variable found for the given container and shared name pair. + if (num_resource_variables_ >= max_variable_count_) { + MicroPrintf( + "Failed to allocate resource variable. Maximum resource variable count " + "(%d) " + "reached.", + max_variable_count_); + return -1; + } + + resource_id = num_resource_variables_++; + resource_variables_[resource_id].container = container; + resource_variables_[resource_id].shared_name = shared_name; + resource_variables_[resource_id].resource_buffer = nullptr; + resource_variables_[resource_id].bytes = 0; + return resource_id; +} + +TfLiteStatus MicroResourceVariables::Read(int id, + const TfLiteEvalTensor* tensor) { + if (id < 0 || id >= num_resource_variables_) { + MicroPrintf("Attempting to read non-existent resource variable %d", id); + return kTfLiteError; + } + MicroResourceVariable variable = resource_variables_[id]; + TFLITE_DCHECK(EvalTensorBytes(tensor) == variable.bytes); + TFLITE_DCHECK(variable.resource_buffer != nullptr); + memcpy(tensor->data.raw, variable.resource_buffer, variable.bytes); + return kTfLiteOk; +} + +TfLiteStatus MicroResourceVariables::Allocate(int id, TfLiteContext* context, + const TfLiteTensor* tensor) { + if (id < 0 || id >= num_resource_variables_) { + MicroPrintf("Attempting to read non-existent resource variable %d", id); + return kTfLiteError; + } + + MicroResourceVariable& variable = resource_variables_[id]; + + if (variable.resource_buffer == nullptr) { + variable.bytes = tensor->bytes; + variable.resource_buffer = + context->AllocatePersistentBuffer(context, tensor->bytes); + if (variable.resource_buffer == nullptr) { + MicroPrintf("Failed to allocate resource buffer."); + return kTfLiteError; + } + // Zero out resource buffers by deafult. Buffers can be initialized to + // nonzero values using ASSIGN_VARIABLE. + memset(variable.resource_buffer, 0, variable.bytes); + } + + return kTfLiteOk; +} + +TfLiteStatus MicroResourceVariables::Assign(int id, + const TfLiteEvalTensor* tensor) { + if (id < 0 || id >= num_resource_variables_) { + MicroPrintf("Attempting to read non-existent resource variable %d", id); + return kTfLiteError; + } + MicroResourceVariable variable = resource_variables_[id]; + + if (variable.resource_buffer == nullptr) { + MicroPrintf( + "Attempting to assign from a TfLiteEvalTensor before the resource " + "buffer has been allocated. Make sure to call AssignResourceVariable " + "with a TfLiteTensor first."); + return kTfLiteError; + } + TFLITE_DCHECK(EvalTensorBytes(tensor) == variable.bytes); + memcpy(variable.resource_buffer, tensor->data.raw, variable.bytes); + return kTfLiteOk; +} + +TfLiteStatus MicroResourceVariables::ResetAll() { + for (int i = 0; i < num_resource_variables_; i++) { + MicroResourceVariable variable = resource_variables_[i]; + memset(variable.resource_buffer, 0, variable.bytes); + } + return kTfLiteOk; +} + +int MicroResourceVariables::FindId(const char* container, + const char* shared_name) { + for (int i = 0; i < num_resource_variables_; i++) { + // Some TFLite flatbuffers contain null container names to save space. + if ((container == nullptr || + !strcmp(container, resource_variables_[i].container)) && + !strcmp(shared_name, resource_variables_[i].shared_name)) { + return i; + } + } + return -1; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h new file mode 100644 index 0000000..d2ebb35 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_resource_variable.h @@ -0,0 +1,87 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TFLITE_MICRO_TENSORFLOW_LITE_MICRO_MICRO_RESOURCE_H_ +#define TFLITE_MICRO_TENSORFLOW_LITE_MICRO_MICRO_RESOURCE_H_ + +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" + +namespace tflite { + +class MicroResourceVariables { + public: + // Create + static MicroResourceVariables* Create(MicroAllocator* allocator, + int num_variables); + + // Creates a resource variable if none is available for the given container + // and shared name pair. Returns the resource ID corresponding to the + // container and shared name pair. If allocation fails, the returned resource + // ID will be negative. The the container and shared_name must outlive this + // class. + int CreateIdIfNoneFound(const char* container, const char* shared_name); + + // Read the resource buffer associated with the given ID into the given + // tensor. + TfLiteStatus Read(int id, const TfLiteEvalTensor* tensor); + + // Allocates the resource buffer if none has been allocated, based on the + // length of the input tensor. Copies input tensor contents to the resource + // buffer. + TfLiteStatus Allocate(int id, TfLiteContext* context, + const TfLiteTensor* tensor); + + // Copies input tensor contents to the resource buffer. + // AllocateResourceVariable with a TFLite tensor must have been called first + // in order to allocate the resource buffer. + TfLiteStatus Assign(int id, const TfLiteEvalTensor* tensor); + + // Zeros out all resource buffers. + TfLiteStatus ResetAll(); + + private: + int FindId(const char* container, const char* shared_name); + + // Micro resource contains the mapping between resource container/name strings + // and resouce IDs. Each resource ID corresponds to a resource buffer pointer. + // The resouce ID is created during the VAR_HANDLE operator preparation stage. + // The resource buffer pointer is created during ASSIGN_VARIABLE preparation + // stage based on the size of the TFLiteTensor being assigned. + struct MicroResourceVariable { + const char* container; + const char* shared_name; + void* resource_buffer; + + // This is only for verifying read size. + size_t bytes; + }; + + MicroResourceVariables(MicroResourceVariable* variables, + int max_variable_count) + : resource_variables_(variables), + max_variable_count_(max_variable_count), + num_resource_variables_(0) {} + + MicroResourceVariable* resource_variables_; + int max_variable_count_; + int num_resource_variables_; +}; + +} // namespace tflite + +#endif // TFLITE_MICRO_TENSORFLOW_LITE_MICRO_MICRO_RESOURCE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_string.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_string.cpp new file mode 100644 index 0000000..39746f9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_string.cpp @@ -0,0 +1,317 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// Implements debug logging for numbers by converting them into strings and then +// calling the main DebugLog(char*) function. These are separated into a +// different file so that platforms can just implement the string output version +// of DebugLog() and then get the numerical variations without requiring any +// more code. + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_string.h" + +#include +#include +#include + +namespace { + +// Int formats can need up to 10 bytes for the value plus a single byte for the +// sign. +constexpr int kMaxIntCharsNeeded = 10 + 1; +// Hex formats can need up to 8 bytes for the value plus two bytes for the "0x". +constexpr int kMaxHexCharsNeeded = 8 + 2; + +// Float formats can need up to 7 bytes for the fraction plus 3 bytes for "x2^" +// plus 3 bytes for the exponent and a single sign bit. +constexpr float kMaxFloatCharsNeeded = 7 + 3 + 3 + 1; + +// All input buffers to the number conversion functions must be this long. +const int kFastToBufferSize = 48; + +// Reverses a zero-terminated string in-place. +char* ReverseStringInPlace(char* start, char* end) { + char* p1 = start; + char* p2 = end - 1; + while (p1 < p2) { + char tmp = *p1; + *p1++ = *p2; + *p2-- = tmp; + } + return start; +} + +// Appends a string to a string, in-place. You need to pass in the maximum +// string length as the second argument. +char* StrCatStr(char* main, int main_max_length, const char* to_append) { + char* current = main; + while (*current != 0) { + ++current; + } + char* current_end = main + (main_max_length - 1); + while ((*to_append != 0) && (current < current_end)) { + *current = *to_append; + ++current; + ++to_append; + } + *current = 0; + return current; +} + +// Populates the provided buffer with an ASCII representation of the number. +char* FastUInt32ToBufferLeft(uint32_t i, char* buffer, int base) { + char* start = buffer; + do { + int32_t digit = i % base; + char character; + if (digit < 10) { + character = '0' + digit; + } else { + character = 'a' + (digit - 10); + } + *buffer++ = character; + i /= base; + } while (i > 0); + *buffer = 0; + ReverseStringInPlace(start, buffer); + return buffer; +} + +// Populates the provided buffer with an ASCII representation of the number. +char* FastInt32ToBufferLeft(int32_t i, char* buffer) { + uint32_t u = i; + if (i < 0) { + *buffer++ = '-'; + u = -u; + } + return FastUInt32ToBufferLeft(u, buffer, 10); +} + +// Converts a number to a string and appends it to another. +char* StrCatInt32(char* main, int main_max_length, int32_t number) { + char number_string[kFastToBufferSize]; + FastInt32ToBufferLeft(number, number_string); + return StrCatStr(main, main_max_length, number_string); +} + +// Converts a number to a string and appends it to another. +char* StrCatUInt32(char* main, int main_max_length, uint32_t number, int base) { + char number_string[kFastToBufferSize]; + FastUInt32ToBufferLeft(number, number_string, base); + return StrCatStr(main, main_max_length, number_string); +} + +// Populates the provided buffer with ASCII representation of the float number. +// Avoids the use of any floating point instructions (since these aren't +// supported on many microcontrollers) and as a consequence prints values with +// power-of-two exponents. +char* FastFloatToBufferLeft(float f, char* buffer) { + char* current = buffer; + char* current_end = buffer + (kFastToBufferSize - 1); + // Access the bit fields of the floating point value to avoid requiring any + // float instructions. These constants are derived from IEEE 754. + const uint32_t sign_mask = 0x80000000; + const uint32_t exponent_mask = 0x7f800000; + const int32_t exponent_shift = 23; + const int32_t exponent_bias = 127; + const uint32_t fraction_mask = 0x007fffff; + uint32_t u; + memcpy(&u, &f, sizeof(int32_t)); + const int32_t exponent = + ((u & exponent_mask) >> exponent_shift) - exponent_bias; + const uint32_t fraction = (u & fraction_mask); + // Expect ~0x2B1B9D3 for fraction. + if (u & sign_mask) { + *current = '-'; + current += 1; + } + *current = 0; + // These are special cases for infinities and not-a-numbers. + if (exponent == 128) { + if (fraction == 0) { + current = StrCatStr(current, (current_end - current), "Inf"); + return current; + } else { + current = StrCatStr(current, (current_end - current), "NaN"); + return current; + } + } + // 0x007fffff (8388607) represents 0.99... for the fraction, so to print the + // correct decimal digits we need to scale our value before passing it to the + // conversion function. This scale should be 10000000/8388608 = 1.1920928955. + // We can approximate this using multiply-adds and right-shifts using the + // values in this array. The 1. portion of the number string is printed out + // in a fixed way before the fraction, below. + const int32_t scale_shifts_size = 13; + const int8_t scale_shifts[13] = {3, 4, 8, 11, 13, 14, 17, + 18, 19, 20, 21, 22, 23}; + uint32_t scaled_fraction = fraction; + for (int i = 0; i < scale_shifts_size; ++i) { + scaled_fraction += (fraction >> scale_shifts[i]); + } + *current = '1'; + current += 1; + *current = '.'; + current += 1; + *current = 0; + + // Prepend leading zeros to fill in all 7 bytes of the fraction. Truncate + // zeros off the end of the fraction. Every fractional value takes 7 bytes. + // For example, 2500 would be written into the buffer as 0002500 since it + // represents .00025. + constexpr int kMaxFractionalDigits = 7; + + // Abort early if there is not enough space in the buffer. + if (current_end - current <= kMaxFractionalDigits) { + return current; + } + + // Pre-fill buffer with zeros to ensure zero-truncation works properly. + for (int i = 1; i < kMaxFractionalDigits; i++) { + *(current + i) = '0'; + } + + // Track how large the fraction is to add leading zeros. + char* previous = current; + current = StrCatUInt32(current, (current_end - current), scaled_fraction, 10); + int fraction_digits = current - previous; + int leading_zeros = kMaxFractionalDigits - fraction_digits; + + // Overwrite the null terminator from StrCatUInt32 to ensure zero-trunctaion + // works properly. + *current = '0'; + + // Shift fraction values and prepend zeros if necessary. + if (leading_zeros != 0) { + for (int i = 0; i < fraction_digits; i++) { + current--; + *(current + leading_zeros) = *current; + *current = '0'; + } + current += kMaxFractionalDigits; + } + + // Truncate trailing zeros for cleaner logs. Ensure we leave at least one + // fractional character for the case when scaled_fraction is 0. + while (*(current - 1) == '0' && (current - 1) > previous) { + current--; + } + *current = 0; + current = StrCatStr(current, (current_end - current), "*2^"); + current = StrCatInt32(current, (current_end - current), exponent); + return current; +} + +int FormatInt32(char* output, int32_t i) { + return static_cast(FastInt32ToBufferLeft(i, output) - output); +} + +int FormatUInt32(char* output, uint32_t i) { + return static_cast(FastUInt32ToBufferLeft(i, output, 10) - output); +} + +int FormatHex(char* output, uint32_t i) { + return static_cast(FastUInt32ToBufferLeft(i, output, 16) - output); +} + +int FormatFloat(char* output, float i) { + return static_cast(FastFloatToBufferLeft(i, output) - output); +} + +} // namespace + +extern "C" int MicroVsnprintf(char* output, int len, const char* format, + va_list args) { + int output_index = 0; + const char* current = format; + // One extra character must be left for the null terminator. + const int usable_length = len - 1; + while (*current != '\0' && output_index < usable_length) { + if (*current == '%') { + current++; + switch (*current) { + case 'd': + // Cut off log message if format could exceed log buffer length. + if (usable_length - output_index < kMaxIntCharsNeeded) { + output[output_index++] = '\0'; + return output_index; + } + output_index += + FormatInt32(&output[output_index], va_arg(args, int32_t)); + current++; + break; + case 'u': + if (usable_length - output_index < kMaxIntCharsNeeded) { + output[output_index++] = '\0'; + return output_index; + } + output_index += + FormatUInt32(&output[output_index], va_arg(args, uint32_t)); + current++; + break; + case 'x': + if (usable_length - output_index < kMaxHexCharsNeeded) { + output[output_index++] = '\0'; + return output_index; + } + output[output_index++] = '0'; + output[output_index++] = 'x'; + output_index += + FormatHex(&output[output_index], va_arg(args, uint32_t)); + current++; + break; + case 'f': + if (usable_length - output_index < kMaxFloatCharsNeeded) { + output[output_index++] = '\0'; + return output_index; + } + output_index += + FormatFloat(&output[output_index], va_arg(args, double)); + current++; + break; + case '%': + output[output_index++] = *current++; + break; + case 'c': + if (usable_length - output_index < 1) { + output[output_index++] = '\0'; + return output_index; + } + output[output_index++] = va_arg(args, int32_t); + current++; + break; + case 's': + char* string = va_arg(args, char*); + int string_idx = 0; + while (string_idx + output_index < usable_length && + string[string_idx] != '\0') { + output[output_index++] = string[string_idx++]; + } + current++; + } + } else { + output[output_index++] = *current++; + } + } + output[output_index++] = '\0'; + return output_index; +} + +extern "C" int MicroSnprintf(char* output, int len, const char* format, ...) { + va_list args; + va_start(args, format); + int bytes_written = MicroVsnprintf(output, len, format, args); + va_end(args); + return bytes_written; +} diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_string.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_string.h new file mode 100644 index 0000000..59303e8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_string.h @@ -0,0 +1,33 @@ +/* Copyright 2018 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_STRING_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_STRING_H_ + +#include + +// Implements simple string formatting for numeric types. Returns the number of +// bytes written to output. +extern "C" { +// Functionally equivalent to vsnprintf, trimmed down for TFLite Micro. +// MicroSnprintf() is implemented using MicroVsnprintf(). +int MicroVsnprintf(char* output, int len, const char* format, va_list args); +// Functionally equavalent to snprintf, trimmed down for TFLite Micro. +// For example, MicroSnprintf(buffer, 10, "int %d", 10) will put the string +// "int 10" in the buffer. +// Floating point values are logged in exponent notation (1.XXX*2^N). +int MicroSnprintf(char* output, int len, const char* format, ...); +} + +#endif // TENSORFLOW_LITE_MICRO_MICRO_STRING_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_time.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_time.cpp new file mode 100644 index 0000000..d418509 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_time.cpp @@ -0,0 +1,58 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// Reference implementation of timer functions. Platforms are not required to +// implement these timer methods, but they are required to enable profiling. + +// On platforms that have a POSIX stack or C library, it can be written using +// methods from or clock() from . + +// To add an equivalent function for your own platform, create your own +// implementation file, and place it in a subfolder with named after the OS +// you're targeting. For example, see the Cortex M bare metal version in +// tensorflow/lite/micro/bluepill/micro_time.cc + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_time.h" + +#if defined(TF_LITE_USE_CTIME) +#include +#endif + +namespace tflite { + +#if !defined(TF_LITE_USE_CTIME) + +// Reference implementation of the ticks_per_second() function that's required +// for a platform to support Tensorflow Lite for Microcontrollers profiling. +// This returns 0 by default because timing is an optional feature that builds +// without errors on platforms that do not need it. +uint32_t ticks_per_second() { return 0; } + +// Reference implementation of the GetCurrentTimeTicks() function that's +// required for a platform to support Tensorflow Lite for Microcontrollers +// profiling. This returns 0 by default because timing is an optional feature +// that builds without errors on platforms that do not need it. +uint32_t GetCurrentTimeTicks() { return 0; } + +#else // defined(TF_LITE_USE_CTIME) + +// For platforms that support ctime, we implment the micro_time interface in +// this central location. +uint32_t ticks_per_second() { return CLOCKS_PER_SEC; } + +uint32_t GetCurrentTimeTicks() { return clock(); } +#endif + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_time.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_time.h new file mode 100644 index 0000000..7a8ab45 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_time.h @@ -0,0 +1,36 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_MICRO_TIME_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_TIME_H_ + +#include + +namespace tflite { + +// These functions should be implemented by each target platform, and provide an +// accurate tick count along with how many ticks there are per second. +uint32_t ticks_per_second(); + +// Return time in ticks. The meaning of a tick varies per platform. +uint32_t GetCurrentTimeTicks(); + +inline uint32_t TicksToMs(int32_t ticks) { + return static_cast(1000.0f * static_cast(ticks) / + static_cast(ticks_per_second())); +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_TIME_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_utils.cpp new file mode 100644 index 0000000..4f7eba7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_utils.cpp @@ -0,0 +1,90 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +int ElementCount(const TfLiteIntArray& dims) { + int result = 1; + for (int i = 0; i < dims.size; ++i) { + result *= dims.data[i]; + } + return result; +} + +size_t EvalTensorBytes(const TfLiteEvalTensor* tensor) { + size_t bytes_per_element; + TFLITE_DCHECK(kTfLiteOk == + TfLiteTypeSizeOf(tensor->type, &bytes_per_element)); + return ElementCount(*tensor->dims) * bytes_per_element; +} + +void SignedSymmetricPerChannelQuantize( + const float* values, TfLiteIntArray* dims, int quantized_dimension, + int8_t* quantized_values, float* scaling_factors, TfLiteType type) { + int input_size = ElementCount(*dims); + int channel_count = dims->data[quantized_dimension]; + int per_channel_size = input_size / channel_count; + + int stride; + int channel_stride; + + int qmin = QMinFromTfLiteType(type); + int qmax = QMaxFromTfLiteType(type); + + if (quantized_dimension == 0) { + stride = 1; + channel_stride = per_channel_size; + } else if (quantized_dimension == 3) { + stride = channel_count; + channel_stride = 1; + } else { + MicroPrintf("quantized dimension must be 0 or 3"); + TFLITE_ABORT; + } + + // Calculate scales for each channel. + for (int channel = 0; channel < channel_count; channel++) { + float min = 0; + float max = 0; + + for (int i = 0; i < per_channel_size; i++) { + int idx = channel * channel_stride + i * stride; + min = fminf(min, values[idx]); + max = fmaxf(max, values[idx]); + } + scaling_factors[channel] = fmaxf(fabs(min), fabs(max)) / qmax; + for (int i = 0; i < per_channel_size; i++) { + int idx = channel * channel_stride + i * stride; + const int32_t quantized_value = + static_cast(roundf(values[idx] / scaling_factors[channel])); + // Clamp: just in case some odd numeric offset. + quantized_values[idx] = fminf(qmax, fmaxf(qmin + 1, quantized_value)); + } + } +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h new file mode 100644 index 0000000..0de899f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h @@ -0,0 +1,171 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MICRO_UTILS_H_ +#define TENSORFLOW_LITE_MICRO_MICRO_UTILS_H_ + +// Patched by Edge Impulse +// Arduino build defines abs as a macro here. That is invalid C++, and breaks +// libc++'s header, undefine it. +// TODO investigate if this belongs to global patch or Arduino lib one +#ifdef abs +#undef abs +#endif + +#include +#include +#include +#include "edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h" +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" + +namespace tflite { + +// Returns number of elements in the shape array. + +int ElementCount(const TfLiteIntArray& dims); + +size_t EvalTensorBytes(const TfLiteEvalTensor* tensor); + +// C++11 does not support constexpr max; hence, use ternary conditional to +// create our own constexpr Max function. +constexpr int Max(int a, int b) { return a >= b ? a : b; } + +// Converts a float value into a quantized value. Note that large values (close +// to max int and min int) may see significant error due to a lack of floating +// point granularity for large values. +template +T FloatToQuantizedType(const float value, const float scale, int zero_point) { + int32_t result = round(value / scale) + zero_point; + result = + std::max(static_cast(std::numeric_limits::min()), result); + result = + std::min(static_cast(std::numeric_limits::max()), result); + return result; +} + +template +T FloatToSymmetricQuantizedType(const float value, const float scale) { + // 64-bit values are required since 8x16 conv accumulates to int64, meaning + // an int64 bias is required. + std::int64_t result = round(value / scale); + result = std::max( + static_cast(std::numeric_limits::min() + 1), result); + result = std::min(static_cast(std::numeric_limits::max()), + result); + return result; +} + +// Helper methods to quantize arrays of floats to the desired format. +// +// There are several key flavors of quantization in TfLite: +// asymmetric symmetric per channel +// int8_t | X | X | X | +// uint8_t | X | X | | +// int16_t | X | | | +// int32_t | | X | X | +// +// The per-op quantization spec can be found here: +// https://www.tensorflow.org/lite/performance/quantization_spec +template +void Quantize(const float* input, T* output, int num_elements, float scale, + int zero_point) { + for (int i = 0; i < num_elements; i++) { + output[i] = FloatToQuantizedType(input[i], scale, zero_point); + } +} + +template +void SymmetricQuantize(const float* input, T* output, int num_elements, + float scale) { + for (int i = 0; i < num_elements; i++) { + output[i] = FloatToSymmetricQuantizedType(input[i], scale); + } +} + +template +void SymmetricPerChannelQuantize(const float* input, T* output, + int num_elements, int num_channels, + float* scales) { + int elements_per_channel = num_elements / num_channels; + for (int i = 0; i < num_channels; i++) { + for (int j = 0; j < elements_per_channel; j++) { + output[i * elements_per_channel + j] = FloatToSymmetricQuantizedType( + input[i * elements_per_channel + j], scales[i]); + } + } +} + +void SignedSymmetricPerChannelQuantize(const float* values, + TfLiteIntArray* dims, + int quantized_dimension, + int8_t* quantized_values, + float* scaling_factor, + TfLiteType type = kTfLiteNoType); + +// Quantizes inputs based on the values provided, choosing the smallest range +// which includes all input values. +template +void SymmetricQuantizeCalculateScales(const float* values, TfLiteIntArray* dims, + T* output, float* scale) { + int input_size = ElementCount(*dims); + + float min = 0; + float max = 0; + for (int i = 0; i < input_size; i++) { + min = fminf(min, values[i]); + max = fmaxf(max, values[i]); + } + *scale = fmaxf(std::abs(min), std::abs(max)) / std::numeric_limits::max(); + for (int i = 0; i < input_size; i++) { + const int32_t quantized_value = + static_cast(roundf(values[i] / *scale)); + // Clamp: just in case some odd numeric offset. + quantized_value = fminf(std::numeric_limits::max(), quantized_value); + quantized_value = fmaxf(std::numeric_limits::min() + 1, quantized_value); + output[i] = quantized_value; + } +} + +template +void Dequantize(const T* values, const int size, const float scale, + int zero_point, float* dequantized_values) { + for (int i = 0; i < size; ++i) { + dequantized_values[i] = (values[i] - zero_point) * scale; + } +} + +// based on TfLiteType passed in to these functions the corresponding max / min +// int for that type are returned +inline int QMinFromTfLiteType(TfLiteType type) { + if (type == kTfLiteInt4) { + return -8; + } else { + return std::numeric_limits::min(); + } +} + +inline int QMaxFromTfLiteType(TfLiteType type) { + if (type == kTfLiteInt4) { + return 7; + } else { + return std::numeric_limits::max(); + } +} + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MICRO_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.cpp new file mode 100644 index 0000000..8ad3864 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.cpp @@ -0,0 +1,66 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h" + +namespace tflite { + +MockMicroGraph::MockMicroGraph(SingleArenaBufferAllocator* allocator) + : MicroGraph(nullptr, nullptr, nullptr, nullptr), + allocator_(allocator), + init_count_(0), + prepare_count_(0), + free_count_(0) { + memset(invoke_counts_, 0, sizeof(invoke_counts_)); + mock_tensor_ = + reinterpret_cast(allocator_->AllocatePersistentBuffer( + sizeof(TfLiteEvalTensor), alignof(TfLiteEvalTensor))); + int* dims_array = reinterpret_cast( + allocator_->AllocatePersistentBuffer(3 * sizeof(int), alignof(int))); + float* data_array = reinterpret_cast( + allocator_->AllocatePersistentBuffer(2 * sizeof(float), alignof(float))); + int dims[] = {2, 1, 2}; + memcpy(dims_array, dims, 3 * sizeof(int)); + mock_tensor_->dims = testing::IntArrayFromInts(dims_array); + mock_tensor_->data.f = data_array; + mock_tensor_->type = kTfLiteFloat32; +} + +TfLiteStatus MockMicroGraph::InvokeSubgraph(int subgraph_idx) { + invoke_counts_[subgraph_idx]++; + return kTfLiteOk; +} + +TfLiteStatus MockMicroGraph::ResetVariableTensors() { return kTfLiteOk; } + +size_t MockMicroGraph::NumSubgraphInputs(int subgraph_idx) { return 1; } + +TfLiteEvalTensor* MockMicroGraph::GetSubgraphInput(int subgraph_idx, + int tensor_idx) { + return mock_tensor_; +} + +size_t MockMicroGraph::NumSubgraphOutputs(int subgraph_idx) { return 1; } + +TfLiteEvalTensor* MockMicroGraph::GetSubgraphOutput(int subgraph_idx, + int tensor_idx) { + return mock_tensor_; +} + +int MockMicroGraph::NumSubgraphs() { return kMaxSubgraphs; } + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.h new file mode 100644 index 0000000..b1aeb20 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/mock_micro_graph.h @@ -0,0 +1,60 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_MOCK_MICRO_GRAPH_H_ +#define TENSORFLOW_LITE_MICRO_MOCK_MICRO_GRAPH_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_graph.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +// MockMicroGraph stubs out all MicroGraph methods used during invoke. A count +// of the number of calls to invoke for each subgraph is maintained for +// validation of control flow operators. +class MockMicroGraph : public MicroGraph { + public: + explicit MockMicroGraph(SingleArenaBufferAllocator* allocator); + TfLiteStatus InvokeSubgraph(int subgraph_idx) override; + TfLiteStatus ResetVariableTensors() override; + size_t NumSubgraphInputs(int subgraph_idx) override; + TfLiteEvalTensor* GetSubgraphInput(int subgraph_idx, int tensor_idx) override; + size_t NumSubgraphOutputs(int subgraph_idx) override; + TfLiteEvalTensor* GetSubgraphOutput(int subgraph_idx, + int tensor_idx) override; + int NumSubgraphs() override; + int get_init_count() const { return init_count_; } + int get_prepare_count() const { return prepare_count_; } + int get_free_count() const { return free_count_; } + int get_invoke_count(int subgraph_idx) const { + return invoke_counts_[subgraph_idx]; + } + + private: + static constexpr int kMaxSubgraphs = 10; + SingleArenaBufferAllocator* allocator_; + TfLiteEvalTensor* mock_tensor_; + int init_count_; + int prepare_count_; + int free_count_; + int invoke_counts_[kMaxSubgraphs]; + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_MOCK_MICRO_GRAPH_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.cpp new file mode 100644 index 0000000..65515ff --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.cpp @@ -0,0 +1,170 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +NonPersistentArenaBufferAllocator::NonPersistentArenaBufferAllocator( + uint8_t* buffer, size_t buffer_size) + : buffer_head_(buffer), + buffer_tail_(buffer + buffer_size), + head_temp_(buffer), + next_temp_(buffer) {} + +NonPersistentArenaBufferAllocator::~NonPersistentArenaBufferAllocator() {} + +// Allocates a temporary buffer. This buffer is not resizable. +uint8_t* NonPersistentArenaBufferAllocator::AllocateTemp(size_t size, + size_t alignment) { + uint8_t* const aligned_result = AlignPointerUp(next_temp_, alignment); + const size_t available_memory = buffer_tail_ - aligned_result; + if (available_memory < size) { + MicroPrintf( + "Failed to allocate temp memory. Requested: %u, " + "available %u, missing: %u", + size, available_memory, size - available_memory); + return nullptr; + } + next_temp_ = aligned_result + size; + temp_buffer_ptr_check_sum_ ^= reinterpret_cast(aligned_result); + temp_buffer_count_++; + return aligned_result; +} + +// Signals that a temporary buffer is no longer needed. +void NonPersistentArenaBufferAllocator::DeallocateTemp(uint8_t* temp_buf) { + temp_buffer_ptr_check_sum_ ^= reinterpret_cast(temp_buf); + temp_buffer_count_--; +} + +// Returns true if all temporary buffers are already deallocated. +bool NonPersistentArenaBufferAllocator::IsAllTempDeallocated() { + if (temp_buffer_count_ != 0 || temp_buffer_ptr_check_sum_ != 0) { + MicroPrintf( + "Number of allocated temp buffers: %d. Checksum passing status: %d", + temp_buffer_count_, !temp_buffer_ptr_check_sum_); + return false; + } + return true; +} + +// Signals that all temporary allocations can be reclaimed. TFLM calls this +// API when it knows that all temporary buffers that it requested has been +// deallocated. The goal of API is to facilitate implementations of +// INonPersistentBufferAllocator can reuse buffer with some reasonable +// complexity. +TfLiteStatus NonPersistentArenaBufferAllocator::ResetTempAllocations() { + if (!IsAllTempDeallocated()) { + MicroPrintf( + "All temp buffers must be freed before calling ResetTempAllocations()"); + return kTfLiteError; + } + next_temp_ = head_temp_; + return kTfLiteOk; +} + +// Returns a buffer that is resizable viable ResizeBuffer(). +uint8_t* NonPersistentArenaBufferAllocator::AllocateResizableBuffer( + size_t size, size_t alignment) { + // Only supports one resizable buffer, which starts at the buffer head. + uint8_t* expected_resizable_buf = AlignPointerUp(buffer_head_, alignment); + + if (resizable_buffer_allocated_) { + MicroPrintf( + "Cannot allocate a new resizable buffer when one is already allocated"); + return nullptr; + } + + if (ResizeBuffer(expected_resizable_buf, size, alignment) == kTfLiteOk) { + resizable_buffer_allocated_ = true; + return expected_resizable_buf; + } + return nullptr; +} + +// Resizes a buffer that is previously returned by the AllocateResizableBuffer. +// Note that ResizeBuffer(old_resizable_buf, 0, 1) effectively deallocates +// a previous allocated resizable buffer. +TfLiteStatus NonPersistentArenaBufferAllocator::ResizeBuffer( + uint8_t* resizable_buf, size_t size, size_t alignment) { + // Only supports one resizable buffer, which starts at the buffer head. + uint8_t* expect_resizable_buf = AlignPointerUp(buffer_head_, alignment); + if (resizable_buf != expect_resizable_buf) { + MicroPrintf("Internal error: buffer is not resizable"); + return kTfLiteError; + } + if (head_temp_ != next_temp_) { + MicroPrintf("ResetTempAllocations() is not called before ResizeBuffer()."); + return kTfLiteError; + } + + const size_t available_memory = buffer_tail_ - expect_resizable_buf; + if (available_memory < size) { + MicroPrintf( + "Failed to resize buffer. Requested: %u, available %u, missing: %u", + size, available_memory, size - available_memory); + return kTfLiteError; + } + head_temp_ = expect_resizable_buf + size; + next_temp_ = head_temp_; + + return kTfLiteOk; +} + +// Frees up the memory occupied by the resizable buffer. +TfLiteStatus NonPersistentArenaBufferAllocator::DeallocateResizableBuffer( + uint8_t* resizable_buf) { + TfLiteStatus status = ResizeBuffer(resizable_buf, 0, 1); + if (status == kTfLiteOk) { + resizable_buffer_allocated_ = false; + } + return status; +} + +// Returns a pointer pointing to the start of the overlay memory, which is +// used for activation tensors and scratch buffers by kernels at Invoke stage. +uint8_t* NonPersistentArenaBufferAllocator::GetOverlayMemoryAddress() const { + return buffer_head_; +} + +// Reserves the size of the overlay memory. This overlay is reserved for the +// kernels at Invoke stage. This is referred to as the overlay because before +// Invoket state, the same memory can be used for temp buffers. The layout of +// the memory is planned by the memory planner separately at Invoke stage. +TfLiteStatus +NonPersistentArenaBufferAllocator::ReserveNonPersistentOverlayMemory( + size_t size, size_t alignment) { + uint8_t* expect_resizable_buf = AlignPointerUp(buffer_head_, alignment); + return ResizeBuffer(expect_resizable_buf, size, alignment); +} + +// Returns the size of non-persistent buffer in use. +size_t NonPersistentArenaBufferAllocator::GetNonPersistentUsedBytes() const { + return (next_temp_ - buffer_head_); +} + +// Returns the number of bytes available with a given alignment. This number +// takes in account any temporary allocations. +size_t NonPersistentArenaBufferAllocator::GetAvailableMemory( + size_t alignment) const { + uint8_t* const aligned_temp = AlignPointerUp(next_temp_, alignment); + uint8_t* const aligned_tail = AlignPointerDown(buffer_tail_, alignment); + return aligned_tail - aligned_temp; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.h new file mode 100644 index 0000000..2a3d639 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/non_persistent_arena_buffer_allocator.h @@ -0,0 +1,104 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_NON_PERSISTENT_ARENA_BUFFER_ALLOCATOR_H_ +#define TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_NON_PERSISTENT_ARENA_BUFFER_ALLOCATOR_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/ibuffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" + +namespace tflite { + +// Implement INonPersistentBufferAllocator on an arena that is dedicated for +// non-persistent buffers. +class NonPersistentArenaBufferAllocator : public INonPersistentBufferAllocator { + public: + NonPersistentArenaBufferAllocator(uint8_t* buffer, size_t buffer_size); + virtual ~NonPersistentArenaBufferAllocator(); + + // Allocates a temporary buffer. This buffer is not resizable. + uint8_t* AllocateTemp(size_t size, size_t alignment) override; + + // Signals that a temporary buffer is no longer needed. + void DeallocateTemp(uint8_t* buf) override; + + // Returns true if all temporary buffers are already deallocated. + bool IsAllTempDeallocated() override; + + // Signals that all temporary allocations can be reclaimed. TFLM calls this + // API when it knows that all temporary buffers that it requested has been + // deallocated. + TfLiteStatus ResetTempAllocations() override; + + // Returns a buffer that is resizable viable ResizeBuffer(). + uint8_t* AllocateResizableBuffer(size_t size, size_t alignment) override; + + // Resizes a buffer that is previously returned by the + // AllocateResizableBuffer. + TfLiteStatus ResizeBuffer(uint8_t* resizable_buf, size_t size, + size_t alignment) override; + + // Frees up the memory occupied by the resizable buffer. + TfLiteStatus DeallocateResizableBuffer(uint8_t* resizable_buf) override; + + // Returns a pointer pointing to the start of the overlay memory, which is + // used for activation tensors and scratch buffers by kernels at Invoke stage. + uint8_t* GetOverlayMemoryAddress() const override; + + // Reserves the size of the overlay memory. This overlay is reserved for the + // kernels at Invoke stage. This is referred to as the overlay because before + // Invoket state, the same memory can be used for temp buffers. The layout of + // the memory is planned by the memory planner separately at Invoke stage. + TfLiteStatus ReserveNonPersistentOverlayMemory(size_t size, + size_t alignment) override; + + // Returns the size of non-persistent buffer in use. + size_t GetNonPersistentUsedBytes() const override; + + // Returns the number of bytes available with a given alignment. This number + // takes in account any temporary allocations. + size_t GetAvailableMemory(size_t alignment) const override; + + TF_LITE_REMOVE_VIRTUAL_DELETE + + private: + // The memory arena that this allocator manages. + uint8_t* const buffer_head_; + uint8_t* const buffer_tail_; + + // The whole region is split into two parts: + // buffer_head_ to head_temp_ - 1 belongs to the only resizable buffer. + // head_temp_ to buffer_tail_ can be used for (non-resizable) temp buffers. + uint8_t* head_temp_; + + // next_temp_ points to the next available temp buffer allocation address and + // its range is between head_temp_ and buffer_tail_ + uint8_t* next_temp_; + + // XOR Check sum for outstanding temp buffers. + // If all temp buffers are deallocated OR no temp buffers are allocated, + // temp_buffer_ptr_check_sum_ == nullptr. + intptr_t temp_buffer_ptr_check_sum_ = 0; + // Count of outstanding temp buffers. + int temp_buffer_count_ = 0; + bool resizable_buffer_allocated_ = false; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_NON_PERSISTENT_ARENA_BUFFER_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.cpp new file mode 100644 index 0000000..a60b626 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.cpp @@ -0,0 +1,32 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.h" + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_error_reporter.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h" + +namespace tflite { + +TfLiteStatus GetRegistrationFromOpCode( + const OperatorCode* opcode, const OpResolver& op_resolver, + const TfLiteRegistration** registration) { + return GetRegistrationFromOpCode( + opcode, op_resolver, tflite::GetMicroErrorReporter(), registration); +} +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.h new file mode 100644 index 0000000..bf6a2db --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/op_resolver_bridge.h @@ -0,0 +1,38 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_OP_RESOLVER_BRIDGE_H_ +#define TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_OP_RESOLVER_BRIDGE_H_ + +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/core/api/op_resolver.h" // needed for the Using declarative + +namespace tflite { + +// Forward declaration of the classes and structs used here. +struct OperatorCode; + +using TfLiteBridgeOpResolver = OpResolver; + +// Handles the logic for converting between an OperatorCode structure extracted +// from a flatbuffer and information about a registered operator +// implementation. +TfLiteStatus GetRegistrationFromOpCode(const OperatorCode* opcode, + const OpResolver& op_resolver, + const TfLiteRegistration** registration); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_TFLITE_BRIDGE_OP_RESOLVER_BRIDGE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.cpp new file mode 100644 index 0000000..9237691 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.cpp @@ -0,0 +1,52 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.h" + +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +PersistentArenaBufferAllocator::PersistentArenaBufferAllocator( + uint8_t* buffer, size_t buffer_size) + : buffer_head_(buffer), + buffer_tail_(buffer + buffer_size), + tail_temp_(buffer_tail_) {} + +PersistentArenaBufferAllocator::~PersistentArenaBufferAllocator() {} + +uint8_t* PersistentArenaBufferAllocator::AllocatePersistentBuffer( + size_t size, size_t alignment) { + uint8_t* const aligned_result = + AlignPointerDown(tail_temp_ - size, alignment); + if (aligned_result < buffer_head_) { +#ifndef TF_LITE_STRIP_ERROR_STRINGS + const size_t missing_memory = buffer_head_ - aligned_result; + MicroPrintf( + "Failed to allocate tail memory. Requested: %u, " + "available %u, missing: %u", + size, size - missing_memory, missing_memory); +#endif + return nullptr; + } + tail_temp_ = aligned_result; + return aligned_result; +} + +size_t PersistentArenaBufferAllocator::GetPersistentUsedBytes() const { + return buffer_tail_ - tail_temp_; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.h new file mode 100644 index 0000000..911c486 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/persistent_arena_buffer_allocator.h @@ -0,0 +1,58 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_PERSISTENT_ARENA_BUFFER_ALLOCATOR_H_ +#define TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_PERSISTENT_ARENA_BUFFER_ALLOCATOR_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/ibuffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" + +namespace tflite { + +// PersistentArenaBufferAllocator is an implementatation of +// IPersistentBufferAllocator interface on an arena that is dedicated for +// persistent buffers. +class PersistentArenaBufferAllocator : public IPersistentBufferAllocator { + public: + PersistentArenaBufferAllocator(uint8_t* buffer, size_t buffer_size); + virtual ~PersistentArenaBufferAllocator(); + + // Allocates persistent memory. The persistent buffer is never freed. + // Returns nullptr if errors occured. + uint8_t* AllocatePersistentBuffer(size_t size, size_t alignment) override; + + // Returns the size of all persistent allocations in bytes. + size_t GetPersistentUsedBytes() const override; + + TF_LITE_REMOVE_VIRTUAL_DELETE + private: + // The memory arena that this allocator manages. + uint8_t* const buffer_head_; + uint8_t* const buffer_tail_; + + // The whole region is split into two parts: + // tail_temp_ to buffer_tail_ contains allocated buffers; + // buffer_head_ to tail_temp_ - 1 belongs to still available spaces. + // So in essence, the allocated region grows from the bottom and emulates + // SingleArenaBufferAllocator's persistent part. + uint8_t* tail_temp_; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_PERSISTENT_ARENA_BUFFER_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.cpp new file mode 100644 index 0000000..11e4d1b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.cpp @@ -0,0 +1,251 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.h" + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +size_t RecordingMicroAllocator::GetDefaultTailUsage() { + // RecordingMicroAllocator inherits from MicroAllocator and its tail usage is + // similar with MicroAllocator with SingleArenaBufferAllocator and + // MicroAllocator being replaced. + return MicroAllocator::GetDefaultTailUsage( + /*is_memory_planner_given=*/false) + + AlignSizeUp() - + AlignSizeUp() + + AlignSizeUp() - AlignSizeUp(); +} + +RecordingMicroAllocator::RecordingMicroAllocator( + RecordingSingleArenaBufferAllocator* recording_memory_allocator, + MicroMemoryPlanner* memory_planner) + : MicroAllocator(recording_memory_allocator, memory_planner), + recording_memory_allocator_(recording_memory_allocator) {} + +RecordingMicroAllocator* RecordingMicroAllocator::Create(uint8_t* tensor_arena, + size_t arena_size) { + RecordingSingleArenaBufferAllocator* simple_memory_allocator = + RecordingSingleArenaBufferAllocator::Create(tensor_arena, arena_size); + TFLITE_DCHECK(simple_memory_allocator != nullptr); + + uint8_t* memory_planner_buffer = + simple_memory_allocator->AllocatePersistentBuffer( + sizeof(GreedyMemoryPlanner), alignof(GreedyMemoryPlanner)); + GreedyMemoryPlanner* memory_planner = + new (memory_planner_buffer) GreedyMemoryPlanner(); + + uint8_t* allocator_buffer = simple_memory_allocator->AllocatePersistentBuffer( + sizeof(RecordingMicroAllocator), alignof(RecordingMicroAllocator)); + RecordingMicroAllocator* allocator = new (allocator_buffer) + RecordingMicroAllocator(simple_memory_allocator, memory_planner); + return allocator; +} + +RecordedAllocation RecordingMicroAllocator::GetRecordedAllocation( + RecordedAllocationType allocation_type) const { + switch (allocation_type) { + case RecordedAllocationType::kTfLiteEvalTensorData: + return recorded_tflite_eval_tensor_data_; + case RecordedAllocationType::kPersistentTfLiteTensorData: + return recorded_persistent_tflite_tensor_data_; + case RecordedAllocationType::kPersistentTfLiteTensorQuantizationData: + return recorded_persistent_tflite_tensor_quantization_data_; + case RecordedAllocationType::kPersistentBufferData: + return recorded_persistent_buffer_data_; + case RecordedAllocationType::kTfLiteTensorVariableBufferData: + return recorded_tflite_tensor_variable_buffer_data_; + case RecordedAllocationType::kNodeAndRegistrationArray: + return recorded_node_and_registration_array_data_; + case RecordedAllocationType::kOpData: + return recorded_op_data_; + } + MicroPrintf("Invalid allocation type supplied: %d", allocation_type); + return RecordedAllocation(); +} + +const RecordingSingleArenaBufferAllocator* +RecordingMicroAllocator::GetSimpleMemoryAllocator() const { + return recording_memory_allocator_; +} + +void RecordingMicroAllocator::PrintAllocations() const { + MicroPrintf("[RecordingMicroAllocator] Arena allocation total %d bytes", + recording_memory_allocator_->GetUsedBytes()); + MicroPrintf("[RecordingMicroAllocator] Arena allocation head %d bytes", + recording_memory_allocator_->GetNonPersistentUsedBytes()); + MicroPrintf("[RecordingMicroAllocator] Arena allocation tail %d bytes", + recording_memory_allocator_->GetPersistentUsedBytes()); + PrintRecordedAllocation(RecordedAllocationType::kTfLiteEvalTensorData, + "TfLiteEvalTensor data", "allocations"); + PrintRecordedAllocation(RecordedAllocationType::kPersistentTfLiteTensorData, + "Persistent TfLiteTensor data", "tensors"); + PrintRecordedAllocation( + RecordedAllocationType::kPersistentTfLiteTensorQuantizationData, + "Persistent TfLiteTensor quantization data", "allocations"); + PrintRecordedAllocation(RecordedAllocationType::kPersistentBufferData, + "Persistent buffer data", "allocations"); + PrintRecordedAllocation( + RecordedAllocationType::kTfLiteTensorVariableBufferData, + "TfLiteTensor variable buffer data", "allocations"); + PrintRecordedAllocation(RecordedAllocationType::kNodeAndRegistrationArray, + "NodeAndRegistration struct", + "NodeAndRegistration structs"); + PrintRecordedAllocation(RecordedAllocationType::kOpData, + "Operator runtime data", "OpData structs"); +} + +void* RecordingMicroAllocator::AllocatePersistentBuffer(size_t bytes) { + RecordedAllocation allocations = SnapshotAllocationUsage(); + void* buffer = MicroAllocator::AllocatePersistentBuffer(bytes); + RecordAllocationUsage(allocations, recorded_persistent_buffer_data_); + + return buffer; +} + +void RecordingMicroAllocator::PrintRecordedAllocation( + RecordedAllocationType allocation_type, const char* allocation_name, + const char* allocation_description) const { +#ifndef TF_LITE_STRIP_ERROR_STRINGS + RecordedAllocation allocation = GetRecordedAllocation(allocation_type); + if (allocation.used_bytes > 0 || allocation.requested_bytes > 0) { + MicroPrintf( + "[RecordingMicroAllocator] '%s' used %d bytes with alignment overhead " + "(requested %d bytes for %d %s)", + allocation_name, allocation.used_bytes, allocation.requested_bytes, + allocation.count, allocation_description); + } +#endif +} + +TfLiteStatus RecordingMicroAllocator::AllocateNodeAndRegistrations( + const Model* model, SubgraphAllocations* subgraph_allocations) { + RecordedAllocation allocations = SnapshotAllocationUsage(); + + TfLiteStatus status = + MicroAllocator::AllocateNodeAndRegistrations(model, subgraph_allocations); + + RecordAllocationUsage(allocations, + recorded_node_and_registration_array_data_); + + for (size_t subgraph_idx = 0; subgraph_idx < model->subgraphs()->size(); + subgraph_idx++) { + // The allocation count in SingleArenaBufferAllocator will only be 1. To + // provide better logging, decrement by 1 and add in the actual number of + // operators used in the graph: The allocation for this recording will + // always be 1. This is because the parent class mallocs one large + // allocation for the number of nodes in the graph (e.g. + // sizeof(NodeAndRegistration) * num_nodes). To prevent extra overhead and + // potential for fragmentation, manually adjust the accounting by + // decrementing by 1 and adding the actual number of nodes used in the + // graph: + if (model->subgraphs()->Get(subgraph_idx)->operators()) { + recorded_node_and_registration_array_data_.count += + model->subgraphs()->Get(subgraph_idx)->operators()->size() - 1; + } else { + recorded_node_and_registration_array_data_.count -= 1; + } + } + return status; +} + +TfLiteStatus RecordingMicroAllocator::AllocateTfLiteEvalTensors( + const Model* model, SubgraphAllocations* subgraph_allocations) { + RecordedAllocation allocations = SnapshotAllocationUsage(); + + TfLiteStatus status = + MicroAllocator::AllocateTfLiteEvalTensors(model, subgraph_allocations); + + RecordAllocationUsage(allocations, recorded_tflite_eval_tensor_data_); + + for (size_t subgraph_idx = 0; subgraph_idx < model->subgraphs()->size(); + subgraph_idx++) { + // The allocation for this recording will always be 1. This is because the + // parent class mallocs one large allocation for the number of tensors in + // the graph (e.g. sizeof(TfLiteEvalTensor) * num_tensors). To prevent extra + // overhead and potential for fragmentation, manually adjust the accounting + // by decrementing by 1 and adding the actual number of tensors used in the + // graph: + recorded_tflite_eval_tensor_data_.count += + model->subgraphs()->Get(subgraph_idx)->tensors()->size() - 1; + } + return status; +} + +TfLiteStatus RecordingMicroAllocator::AllocateVariables( + const SubGraph* subgraph, TfLiteEvalTensor* eval_tensors, + const int32_t* offline_planner_offsets) { + RecordedAllocation allocations = SnapshotAllocationUsage(); + + TfLiteStatus status = MicroAllocator::AllocateVariables( + subgraph, eval_tensors, offline_planner_offsets); + + RecordAllocationUsage(allocations, + recorded_tflite_tensor_variable_buffer_data_); + return status; +} + +TfLiteTensor* +RecordingMicroAllocator::AllocatePersistentTfLiteTensorInternal() { + RecordedAllocation allocations = SnapshotAllocationUsage(); + + TfLiteTensor* result = + MicroAllocator::AllocatePersistentTfLiteTensorInternal(); + + RecordAllocationUsage(allocations, recorded_persistent_tflite_tensor_data_); + return result; +} + +TfLiteStatus RecordingMicroAllocator::PopulateTfLiteTensorFromFlatbuffer( + const Model* model, TfLiteTensor* tensor, int tensor_index, + int subgraph_index, bool allocate_temp) { + RecordedAllocation allocations = SnapshotAllocationUsage(); + + TfLiteStatus status = MicroAllocator::PopulateTfLiteTensorFromFlatbuffer( + model, tensor, tensor_index, subgraph_index, allocate_temp); + + RecordAllocationUsage(allocations, + recorded_persistent_tflite_tensor_quantization_data_); + return status; +} + +RecordedAllocation RecordingMicroAllocator::SnapshotAllocationUsage() const { + return {/*requested_bytes=*/recording_memory_allocator_->GetRequestedBytes(), + /*used_bytes=*/recording_memory_allocator_->GetUsedBytes(), + /*count=*/recording_memory_allocator_->GetAllocatedCount()}; +} + +void RecordingMicroAllocator::RecordAllocationUsage( + const RecordedAllocation& snapshotted_allocation, + RecordedAllocation& recorded_allocation) { + recorded_allocation.requested_bytes += + recording_memory_allocator_->GetRequestedBytes() - + snapshotted_allocation.requested_bytes; + recorded_allocation.used_bytes += + recording_memory_allocator_->GetUsedBytes() - + snapshotted_allocation.used_bytes; + recorded_allocation.count += + recording_memory_allocator_->GetAllocatedCount() - + snapshotted_allocation.count; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.h new file mode 100644 index 0000000..9d694af --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.h @@ -0,0 +1,125 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_RECORDING_MICRO_ALLOCATOR_H_ +#define TENSORFLOW_LITE_MICRO_RECORDING_MICRO_ALLOCATOR_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_allocator.h" + +namespace tflite { + +// List of buckets currently recorded by this class. Each type keeps a list of +// allocated information during model initialization. +// TODO(b/169834511): Add tracking for scratch buffer allocations. +enum class RecordedAllocationType { + kTfLiteEvalTensorData, + kPersistentTfLiteTensorData, + kPersistentTfLiteTensorQuantizationData, + kPersistentBufferData, + kTfLiteTensorVariableBufferData, + kNodeAndRegistrationArray, + kOpData, +}; + +// Container for holding information about allocation recordings by a given +// type. Each recording contains the number of bytes requested, the actual bytes +// allocated (can defer from requested by alignment), and the number of items +// allocated. +struct RecordedAllocation { + size_t requested_bytes; + size_t used_bytes; + size_t count; +}; + +// Utility subclass of MicroAllocator that records all allocations +// inside the arena. A summary of allocations can be logged through the +// ErrorReporter by invoking LogAllocations(). This special allocator requires +// an instance of RecordingSingleArenaBufferAllocator to capture allocations in +// the head and tail. Arena allocation recording can be retrieved by type +// through the GetRecordedAllocation() function. This class should only be used +// for auditing memory usage or integration testing. +class RecordingMicroAllocator : public MicroAllocator { + public: + static RecordingMicroAllocator* Create(uint8_t* tensor_arena, + size_t arena_size); + + // Returns the fixed amount of memory overhead of RecordingMicroAllocator. + static size_t GetDefaultTailUsage(); + + // Returns the recorded allocations information for a given allocation type. + RecordedAllocation GetRecordedAllocation( + RecordedAllocationType allocation_type) const; + + const RecordingSingleArenaBufferAllocator* GetSimpleMemoryAllocator() const; + + // Logs out through the ErrorReporter all allocation recordings by type + // defined in RecordedAllocationType. + void PrintAllocations() const; + + void* AllocatePersistentBuffer(size_t bytes) override; + + protected: + TfLiteStatus AllocateNodeAndRegistrations( + const Model* model, SubgraphAllocations* subgraph_allocations) override; + TfLiteStatus AllocateTfLiteEvalTensors( + const Model* model, SubgraphAllocations* subgraph_allocations) override; + TfLiteStatus AllocateVariables( + const SubGraph* subgraph, TfLiteEvalTensor* eval_tensors, + const int32_t* offline_planner_offsets) override; + // TODO(b/162311891): Once all kernels have been updated to the new API drop + // this method. It is only used to record TfLiteTensor persistent allocations. + TfLiteTensor* AllocatePersistentTfLiteTensorInternal() override; + + // TODO(b/162311891): Once all kernels have been updated to the new API drop + // this function since all allocations for quantized data will take place in + // the temp section. + TfLiteStatus PopulateTfLiteTensorFromFlatbuffer(const Model* model, + TfLiteTensor* tensor, + int tensor_index, + int subgraph_index, + bool allocate_temp) override; + + private: + RecordingMicroAllocator(RecordingSingleArenaBufferAllocator* memory_allocator, + MicroMemoryPlanner* memory_planner); + + void PrintRecordedAllocation(RecordedAllocationType allocation_type, + const char* allocation_name, + const char* allocation_description) const; + + RecordedAllocation SnapshotAllocationUsage() const; + void RecordAllocationUsage(const RecordedAllocation& snapshotted_allocation, + RecordedAllocation& recorded_allocation); + + const RecordingSingleArenaBufferAllocator* recording_memory_allocator_; + + RecordedAllocation recorded_tflite_eval_tensor_data_ = {}; + RecordedAllocation recorded_persistent_tflite_tensor_data_ = {}; + RecordedAllocation recorded_persistent_tflite_tensor_quantization_data_ = {}; + RecordedAllocation recorded_persistent_buffer_data_ = {}; + RecordedAllocation recorded_tflite_tensor_variable_buffer_data_ = {}; + RecordedAllocation recorded_node_and_registration_array_data_ = {}; + + // TODO(b/187993291): Re-enable OpData allocating tracking. + RecordedAllocation recorded_op_data_ = {}; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_RECORDING_MICRO_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_interpreter.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_interpreter.h new file mode 100644 index 0000000..ce44fbd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_micro_interpreter.h @@ -0,0 +1,69 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_RECORDING_MICRO_INTERPRETER_H_ +#define TENSORFLOW_LITE_MICRO_RECORDING_MICRO_INTERPRETER_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_profiler_interface.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/recording_micro_allocator.h" + +namespace tflite { + +// Utility subclass that enables internal recordings of the MicroInterpreter. +// This class should be used to audit and analyze memory arena usage for a given +// model and interpreter. +// +// After construction and the first Invoke() or AllocateTensors() call - the +// memory usage is recorded and available through the GetMicroAllocator() +// function. See RecordingMicroAlloctor for more details on what is currently +// recorded from arena allocations. +// +// It is recommended for users to increase the tensor arena size by at least 1kb +// to ensure enough additional memory is available for internal recordings. +class RecordingMicroInterpreter : public MicroInterpreter { + public: + RecordingMicroInterpreter(const Model* model, + const MicroOpResolver& op_resolver, + uint8_t* tensor_arena, size_t tensor_arena_size, + MicroResourceVariables* resource_variable = nullptr, + MicroProfilerInterface* profiler = nullptr) + : MicroInterpreter( + model, op_resolver, + RecordingMicroAllocator::Create(tensor_arena, tensor_arena_size), + resource_variable, profiler), + recording_micro_allocator_( + static_cast(allocator())) {} + + RecordingMicroInterpreter(const Model* model, + const MicroOpResolver& op_resolver, + RecordingMicroAllocator* allocator, + MicroResourceVariables* resource_variable = nullptr, + MicroProfilerInterface* profiler = nullptr) + : MicroInterpreter(model, op_resolver, allocator, resource_variable, + profiler), + recording_micro_allocator_(*allocator) {} + + const RecordingMicroAllocator& GetMicroAllocator() const { + return recording_micro_allocator_; + } + + private: + const RecordingMicroAllocator& recording_micro_allocator_; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_RECORDING_MICRO_INTERPRETER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.cpp new file mode 100644 index 0000000..746561c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.cpp @@ -0,0 +1,85 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" + +namespace tflite { + +RecordingSingleArenaBufferAllocator::RecordingSingleArenaBufferAllocator( + uint8_t* buffer_head, size_t buffer_size) + : SingleArenaBufferAllocator(buffer_head, buffer_size), + requested_head_bytes_(0), + requested_tail_bytes_(0), + used_bytes_(0), + alloc_count_(0) {} + +RecordingSingleArenaBufferAllocator::~RecordingSingleArenaBufferAllocator() {} + +RecordingSingleArenaBufferAllocator* +RecordingSingleArenaBufferAllocator::Create(uint8_t* buffer_head, + size_t buffer_size) { + TFLITE_DCHECK(buffer_head != nullptr); + RecordingSingleArenaBufferAllocator tmp = + RecordingSingleArenaBufferAllocator(buffer_head, buffer_size); + + uint8_t* allocator_buffer = tmp.AllocatePersistentBuffer( + sizeof(RecordingSingleArenaBufferAllocator), + alignof(RecordingSingleArenaBufferAllocator)); + // Use the default copy constructor to populate internal states. + return new (allocator_buffer) RecordingSingleArenaBufferAllocator(tmp); +} + +size_t RecordingSingleArenaBufferAllocator::GetRequestedBytes() const { + return requested_head_bytes_ + requested_tail_bytes_; +} + +size_t RecordingSingleArenaBufferAllocator::GetUsedBytes() const { + return used_bytes_; +} + +size_t RecordingSingleArenaBufferAllocator::GetAllocatedCount() const { + return alloc_count_; +} + +TfLiteStatus RecordingSingleArenaBufferAllocator::ResizeBuffer( + uint8_t* resizable_buf, size_t size, size_t alignment) { + const uint8_t* previous_head = head(); + TfLiteStatus status = + SingleArenaBufferAllocator::ResizeBuffer(resizable_buf, size, alignment); + if (status == kTfLiteOk) { + used_bytes_ += head() - previous_head; + requested_head_bytes_ = size; + } + return status; +} + +uint8_t* RecordingSingleArenaBufferAllocator::AllocatePersistentBuffer( + size_t size, size_t alignment) { + const uint8_t* previous_tail = tail(); + uint8_t* result = + SingleArenaBufferAllocator::AllocatePersistentBuffer(size, alignment); + if (result != nullptr) { + used_bytes_ += previous_tail - tail(); + requested_tail_bytes_ += size; + alloc_count_++; + } + return result; +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.h new file mode 100644 index 0000000..cb58a8b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/recording_single_arena_buffer_allocator.h @@ -0,0 +1,63 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_RECORDING_SINGLE_ARENA_BUFFER_ALLOCATOR_H_ +#define TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_RECORDING_SINGLE_ARENA_BUFFER_ALLOCATOR_H_ + +#include "edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" + +namespace tflite { + +// Utility class used to log allocations of a SingleArenaBufferAllocator. Should +// only be used in debug/evaluation settings or unit tests to evaluate +// allocation usage. +class RecordingSingleArenaBufferAllocator : public SingleArenaBufferAllocator { + public: + RecordingSingleArenaBufferAllocator(uint8_t* buffer_head, size_t buffer_size); + // TODO(b/157615197): Cleanup constructors/destructor and use factory + // functions. + ~RecordingSingleArenaBufferAllocator() override; + + static RecordingSingleArenaBufferAllocator* Create(uint8_t* buffer_head, + size_t buffer_size); + + // Returns the number of bytes requested from the head or tail. + size_t GetRequestedBytes() const; + + // Returns the number of bytes actually allocated from the head or tail. This + // value will be >= to the number of requested bytes due to padding and + // alignment. + size_t GetUsedBytes() const; + + // Returns the number of alloc calls from the head or tail. + size_t GetAllocatedCount() const; + + TfLiteStatus ResizeBuffer(uint8_t* resizable_buf, size_t size, + size_t alignment) override; + uint8_t* AllocatePersistentBuffer(size_t size, size_t alignment) override; + + private: + size_t requested_head_bytes_; + size_t requested_tail_bytes_; + size_t used_bytes_; + size_t alloc_count_; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_RECORDING_SINGLE_ARENA_BUFFER_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/schema_utils.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/schema_utils.cpp new file mode 100644 index 0000000..7588028 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/schema_utils.cpp @@ -0,0 +1,62 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h" + +#include + +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" + +namespace tflite { + +// The following GetBuiltinCode methods are the utility methods for reading +// builtin operatore code, ensuring compatibility issues between v3 and v3a +// schema. Always the maximum value of the two fields always will be the correct +// value as follows: +// +// - Supporting schema version v3 models +// +// The `builtin_code` field is not available in the v3 models. Flatbuffer +// library will feed zero value, which is the default value in the v3a schema. +// The actual builtin operatore code value will exist in the +// `deprecated_builtin_code` field. At the same time, it implies that +// `deprecated_builtin_code` >= `builtin_code` and the maximum value of the two +// fields will be same with `deprecated_builtin_code'. +// +// - Supporting builtin operator codes beyonds 127 +// +// New builtin operators, whose operator code is larger than 127, can not be +// assigned to the `deprecated_builtin_code` field. In such cases, the +// value of the `builtin_code` field should be used for the builtin operator +// code. In the case, the maximum value of the two fields will be the value of +// the `builtin_code` as the right value. + +BuiltinOperator GetBuiltinCode(const OperatorCode* op_code) { + // Caller should guarantee that the given argument value is not a nullptr. + TFLITE_DCHECK(op_code != nullptr); + + return std::max( + op_code->builtin_code(), + static_cast(op_code->deprecated_builtin_code())); +} + +BuiltinOperator GetBuiltinCode(const OperatorCodeT* op_code) { + // Caller should guarantee that the given argument value is not a nullptr. + TFLITE_DCHECK(op_code != nullptr); + + return std::max(op_code->builtin_code, static_cast( + op_code->deprecated_builtin_code)); +} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.cpp new file mode 100644 index 0000000..1015b53 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.cpp @@ -0,0 +1,199 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h" + +#include +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/c_api_types.h" +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/op_macros.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_log.h" + +namespace tflite { + +SingleArenaBufferAllocator::SingleArenaBufferAllocator(uint8_t* buffer_head, + uint8_t* buffer_tail) + : buffer_head_(buffer_head), + buffer_tail_(buffer_tail), + head_(buffer_head), + tail_(buffer_tail), + temp_(buffer_head_) {} + +SingleArenaBufferAllocator::SingleArenaBufferAllocator(uint8_t* buffer, + size_t buffer_size) + : SingleArenaBufferAllocator(buffer, buffer + buffer_size) {} + +/* static */ +SingleArenaBufferAllocator* SingleArenaBufferAllocator::Create( + uint8_t* buffer_head, size_t buffer_size) { + TFLITE_DCHECK(buffer_head != nullptr); + SingleArenaBufferAllocator tmp = + SingleArenaBufferAllocator(buffer_head, buffer_size); + + // Allocate enough bytes from the buffer to create a + // SingleArenaBufferAllocator. The new instance will use the current adjusted + // tail buffer from the tmp allocator instance. + uint8_t* allocator_buffer = tmp.AllocatePersistentBuffer( + sizeof(SingleArenaBufferAllocator), alignof(SingleArenaBufferAllocator)); + // Use the default copy constructor to populate internal states. + return new (allocator_buffer) SingleArenaBufferAllocator(tmp); +} + +SingleArenaBufferAllocator::~SingleArenaBufferAllocator() {} + +uint8_t* SingleArenaBufferAllocator::AllocateResizableBuffer(size_t size, + size_t alignment) { + // Only supports one resizable buffer, which starts at the buffer head. + uint8_t* expect_resizable_buf = AlignPointerUp(buffer_head_, alignment); + if (ResizeBuffer(expect_resizable_buf, size, alignment) == kTfLiteOk) { + return expect_resizable_buf; + } + return nullptr; +} + +TfLiteStatus SingleArenaBufferAllocator::DeallocateResizableBuffer( + uint8_t* resizable_buf) { + return ResizeBuffer(resizable_buf, 0, 1); +} + +TfLiteStatus SingleArenaBufferAllocator::ReserveNonPersistentOverlayMemory( + size_t size, size_t alignment) { + uint8_t* expect_resizable_buf = AlignPointerUp(buffer_head_, alignment); + return ResizeBuffer(expect_resizable_buf, size, alignment); +} + +TfLiteStatus SingleArenaBufferAllocator::ResizeBuffer(uint8_t* resizable_buf, + size_t size, + size_t alignment) { + // Only supports one resizable buffer, which starts at the buffer head. + uint8_t* expect_resizable_buf = AlignPointerUp(buffer_head_, alignment); + if (head_ != temp_ || resizable_buf != expect_resizable_buf) { + MicroPrintf( + "Internal error: either buffer is not resizable or " + "ResetTempAllocations() is not called before ResizeBuffer()."); + return kTfLiteError; + } + + uint8_t* const aligned_result = AlignPointerUp(buffer_head_, alignment); + const size_t available_memory = tail_ - aligned_result; + if (available_memory < size) { + MicroPrintf( + "Failed to resize buffer. Requested: %u, available %u, missing: %u", + size, available_memory, size - available_memory); + return kTfLiteError; + } + head_ = aligned_result + size; + temp_ = head_; + + return kTfLiteOk; +} + +uint8_t* SingleArenaBufferAllocator::AllocatePersistentBuffer( + size_t size, size_t alignment) { + uint8_t* const aligned_result = AlignPointerDown(tail_ - size, alignment); + if (aligned_result < head_) { +#ifndef TF_LITE_STRIP_ERROR_STRINGS + const size_t missing_memory = head_ - aligned_result; + MicroPrintf( + "Failed to allocate tail memory. Requested: %u, " + "available %u, missing: %u", + size, size - missing_memory, missing_memory); +#endif + return nullptr; + } + tail_ = aligned_result; + return aligned_result; +} + +uint8_t* SingleArenaBufferAllocator::AllocateTemp(size_t size, + size_t alignment) { + uint8_t* const aligned_result = AlignPointerUp(temp_, alignment); + const size_t available_memory = tail_ - aligned_result; + if (available_memory < size) { + MicroPrintf( + "Failed to allocate temp memory. Requested: %u, " + "available %u, missing: %u", + size, available_memory, size - available_memory); + return nullptr; + } + temp_ = aligned_result + size; + temp_buffer_ptr_check_sum_ ^= (reinterpret_cast(aligned_result)); + temp_buffer_count_++; + return aligned_result; +} + +void SingleArenaBufferAllocator::DeallocateTemp(uint8_t* temp_buf) { + temp_buffer_ptr_check_sum_ ^= (reinterpret_cast(temp_buf)); + temp_buffer_count_--; +} + +bool SingleArenaBufferAllocator::IsAllTempDeallocated() { + if (temp_buffer_count_ != 0 || temp_buffer_ptr_check_sum_ != 0) { + MicroPrintf( + "Number of allocated temp buffers: %d. Checksum passing status: %d", + temp_buffer_count_, !temp_buffer_ptr_check_sum_); + return false; + } + return true; +} + +TfLiteStatus SingleArenaBufferAllocator::ResetTempAllocations() { + // TODO(b/209453859): enable error check based on IsAllTempDeallocated after + // all AllocateTemp have been paird with DeallocateTemp + if (!IsAllTempDeallocated()) { + MicroPrintf( + "All temp buffers must be freed before calling ResetTempAllocations()"); + return kTfLiteError; + } + temp_ = head_; + return kTfLiteOk; +} + +uint8_t* SingleArenaBufferAllocator::GetOverlayMemoryAddress() const { + return buffer_head_; +} + +size_t SingleArenaBufferAllocator::GetNonPersistentUsedBytes() const { + return std::max(head_ - buffer_head_, temp_ - buffer_head_); +} + +size_t SingleArenaBufferAllocator::GetPersistentUsedBytes() const { + return buffer_tail_ - tail_; +} + +size_t SingleArenaBufferAllocator::GetAvailableMemory(size_t alignment) const { + uint8_t* const aligned_temp = AlignPointerUp(temp_, alignment); + uint8_t* const aligned_tail = AlignPointerDown(tail_, alignment); + return aligned_tail - aligned_temp; +} + +size_t SingleArenaBufferAllocator::GetUsedBytes() const { + return GetPersistentUsedBytes() + GetNonPersistentUsedBytes(); +} + +size_t SingleArenaBufferAllocator::GetBufferSize() const { + return buffer_tail_ - buffer_head_; +} + +uint8_t* SingleArenaBufferAllocator::head() const { return head_; } + +uint8_t* SingleArenaBufferAllocator::tail() const { return tail_; } + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h new file mode 100644 index 0000000..730ee73 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/single_arena_buffer_allocator.h @@ -0,0 +1,144 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_SINGLE_ARENA_BUFFER_ALLOCATOR_H_ +#define TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_SINGLE_ARENA_BUFFER_ALLOCATOR_H_ + +#include +#include + +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/ibuffer_allocator.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/compatibility.h" + +namespace tflite { + +// TODO(petewarden): This allocator never frees up or reuses any memory, even +// though we have enough information about lifetimes of the tensors to do so. +// This makes it pretty wasteful, so we should use a more intelligent method. +class SingleArenaBufferAllocator : public INonPersistentBufferAllocator, + public IPersistentBufferAllocator { + public: + // TODO(b/157615197): Cleanup constructors/destructor and use factory + // functions. + SingleArenaBufferAllocator(uint8_t* buffer_head, uint8_t* buffer_tail); + SingleArenaBufferAllocator(uint8_t* buffer, size_t buffer_size); + virtual ~SingleArenaBufferAllocator(); + + // Creates a new SingleArenaBufferAllocator from a given buffer head and size. + static SingleArenaBufferAllocator* Create(uint8_t* buffer_head, + size_t buffer_size); + + // Resizes a buffer that is previously returned by the + // AllocateResizableBuffer. In current implementation, it Adjusts the head + // (lowest address and moving upwards) memory allocation to a given size. + // Calls to this method will also invalidate all temporary allocation values + // (it sets the location of temp space at the end of the head section). This + // call will fail if a chain of allocations through AllocateTemp() have not + // been cleaned up with a call to ResetTempAllocations(). + virtual TfLiteStatus ResizeBuffer(uint8_t* resizable_buf, size_t size, + size_t alignment) override; + + // Returns a buffer that is resizable viable ResizeBuffer(). Only one + // resizable buffer is currently supported. + virtual uint8_t* AllocateResizableBuffer(size_t size, + size_t alignment) override; + + // Frees up the memory occupied by the resizable buffer + virtual TfLiteStatus DeallocateResizableBuffer( + uint8_t* resizable_buf) override; + + // Reserves the non-persistent memory that is planned by the memory planner. + virtual TfLiteStatus ReserveNonPersistentOverlayMemory( + size_t size, size_t alignment) override; + + // Allocates persistent memory starting at the tail of the arena (highest + // address and moving downwards). + virtual uint8_t* AllocatePersistentBuffer(size_t size, + size_t alignment) override; + + // Allocates a temporary buffer from the head of the arena (lowest address and + // moving upwards) but does not update the actual head allocation size or + // position. The returned buffer is guaranteed until either + // ResetTempAllocations() is called or another call to AllocateFromHead(). + // Repeat calls to this function will create a chain of temp allocations. All + // calls to AllocateTemp() must end with a call to ResetTempAllocations(). If + // AllocateFromHead() is called before a call to ResetTempAllocations(), it + // will fail with an error message. + virtual uint8_t* AllocateTemp(size_t size, size_t alignment) override; + + // Signals that a temporary buffer is no longer needed. This is currently for + // book-keeping purpose and the memory region are not immediately available + // for re-use. The deallocated memory region are only reclaimed after + // ResetTempAllocations is called as it is right now. + virtual void DeallocateTemp(uint8_t* buf) override; + + // Returns true if all temporary buffers are already deallocated. + virtual bool IsAllTempDeallocated() override; + + // Resets a chain of temporary allocations back to the current head of the + // arena (lowest address). + virtual TfLiteStatus ResetTempAllocations() override; + + // Returns a pointer to the buffer currently assigned to the head section. + // This buffer is set by calling SetHeadSize(). + uint8_t* GetOverlayMemoryAddress() const override; + + // Returns the size of the head section in bytes. + size_t GetNonPersistentUsedBytes() const override; + + // Returns the size of all allocations in the tail section in bytes. + size_t GetPersistentUsedBytes() const override; + + // Returns the number of bytes available with a given alignment. This number + // takes in account any temporary allocations. + size_t GetAvailableMemory(size_t alignment) const override; + + // Returns the number of used bytes in the allocator. This number takes in + // account any temporary allocations. + size_t GetUsedBytes() const; + + TF_LITE_REMOVE_VIRTUAL_DELETE + + protected: + // Returns a pointer to the current end of the head buffer. + uint8_t* head() const; + + // Returns a pointer to the current end of the tail buffer. + uint8_t* tail() const; + + private: + size_t GetBufferSize() const; + uint8_t* buffer_head_; + uint8_t* buffer_tail_; + uint8_t* head_; + uint8_t* tail_; + uint8_t* temp_; + + // The combination of the checksum of outstanding temporary buffer pointers + // AND the count of outstanding temporary buffer provide a low cost mechanism + // to audit temporary buffers' allocation and deallocation. + // + // XOR Check sum for outstanding temp buffers. + // If all temp buffers are deallocated OR no temp buffers are allocated, + // temp_buffer_ptr_check_sum_ == nullptr. + intptr_t temp_buffer_ptr_check_sum_ = 0; + // Count of outstanding temp buffers. + int temp_buffer_count_ = 0; +}; + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_ARENA_ALLOCATOR_SINGLE_ARENA_BUFFER_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/system_setup.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/system_setup.cpp new file mode 100644 index 0000000..86815b9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/system_setup.cpp @@ -0,0 +1,25 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/system_setup.h" + +namespace tflite { + +// To add an equivalent function for your own platform, create your own +// implementation file, and place it in a subfolder named after the target. See +// tensorflow/lite/micro/debug_log.cc for a similar example. +void InitializeTarget() {} + +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/system_setup.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/system_setup.h new file mode 100644 index 0000000..71ab13a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/system_setup.h @@ -0,0 +1,27 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_MICRO_SYSTEM_SETUP_H_ +#define TENSORFLOW_LITE_MICRO_SYSTEM_SETUP_H_ + +namespace tflite { + +// This should called during initialization of TFLM binaries and tests. It can +// be specialized if there is a need for custom target-specific intialization. +// For more information, see tensorflow/lite/micro/system_setup.cc. +void InitializeTarget(); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_SYSTEM_SETUP_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.cpp new file mode 100644 index 0000000..fe4c836 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.cpp @@ -0,0 +1,112 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.h" + +#include +#include +#include +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +// TODO(b/170464050): Use TFLM test only version of schema_utils. + +namespace tflite { +namespace testing { + +const TfLiteRegistration* PackerOp::getRegistration() { + return GetMutableRegistration(); +} + +TfLiteRegistration* PackerOp::GetMutableRegistration() { + static TfLiteRegistration r; + r.init = Init; + r.prepare = Prepare; + r.invoke = Invoke; + r.free = Free; + return &r; +} + +void* PackerOp::Init(TfLiteContext* context, const char* buffer, + size_t length) { + freed_ = false; + // Do nothing. + return nullptr; +} + +void PackerOp::Free(TfLiteContext* context, void* buffer) { freed_ = true; } + +TfLiteStatus PackerOp::Prepare(TfLiteContext* context, TfLiteNode* node) { + return kTfLiteOk; +} + +TfLiteStatus PackerOp::Invoke(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, 0); + TF_LITE_ENSURE(context, input1 != nullptr); + const int32_t* input1_data = input1->data.i32; + TF_LITE_ENSURE_EQ(context, input1->dims->size, 1); + const int32_t input1_len = input1->dims->data[0]; + + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, 1); + TF_LITE_ENSURE(context, input2 != nullptr); + const int32_t* input2_data = input2->data.i32; + TF_LITE_ENSURE_EQ(context, input2->dims->size, 1); + const int32_t input2_len = input2->dims->data[0]; + + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE(context, output != nullptr); + int32_t* output_data = output->data.i32; + int32_t output_len = output->dims->data[0]; + + // Fill output with input: first with the first tensor, then with the second + // tensor up to the size of the output tensor. + int cnt = 0; + int i; + for (i = 0; i < input1_len && cnt < output_len; i++, cnt++) { + output_data[cnt] = input1_data[i]; + } + if (cnt >= output_len) { + return kTfLiteOk; + } + + for (i = 0; i < input2_len && cnt < output_len; i++, cnt++) { + output_data[cnt] = input2_data[i]; + } + if (cnt >= output_len) { + return kTfLiteOk; + } + + for (; cnt < output_len; cnt++) { + output_data[cnt] = 0; + } + return kTfLiteOk; +} + +bool PackerOp::freed_ = false; + +} // namespace testing +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.h new file mode 100644 index 0000000..cbbbcec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.h @@ -0,0 +1,50 @@ +/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_TEST_HELPER_CUSTOM_OPS_H_ +#define TENSORFLOW_LITE_MICRO_TEST_HELPER_CUSTOM_OPS_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { +namespace testing { + +class PackerOp { + public: + static const TfLiteRegistration* getRegistration(); + static TfLiteRegistration* GetMutableRegistration(); + static void* Init(TfLiteContext* context, const char* buffer, size_t length); + static void Free(TfLiteContext* context, void* buffer); + static TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node); + static TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node); + + private: + static bool freed_; +}; + +} // namespace testing +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_TEST_HELPER_CUSTOM_OPS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helpers.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helpers.cpp new file mode 100644 index 0000000..d97caca --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helpers.cpp @@ -0,0 +1,2035 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h" + +#include +#include +#include +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/kernel_util.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/memory_helpers.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_arena_constants.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/test_helper_custom_ops.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +// TODO(b/170464050): Use TFLM test only version of schema_utils. + +namespace tflite { +namespace testing { +namespace { + +class StackAllocator : public flatbuffers::Allocator { + public: + StackAllocator(size_t alignment) : data_size_(0) { + data_ = AlignPointerUp(data_backing_, alignment); + } + + uint8_t* allocate(size_t size) override { + TFLITE_DCHECK((data_size_ + size) <= kStackAllocatorSize); + uint8_t* result = data_; + data_ += size; + data_size_ += size; + return result; + } + + void deallocate(uint8_t* p, size_t) override {} + + static StackAllocator& instance(size_t alignment = 1) { + // Avoid using true dynamic memory allocation to be portable to bare metal. + static char inst_memory[sizeof(StackAllocator)]; + static StackAllocator* inst = new (inst_memory) StackAllocator(alignment); + return *inst; + } + + static constexpr size_t kStackAllocatorSize = 8192; + + private: + uint8_t data_backing_[kStackAllocatorSize]; + uint8_t* data_; + int data_size_; + + TF_LITE_REMOVE_VIRTUAL_DELETE +}; + +flatbuffers::FlatBufferBuilder* BuilderInstance() { + static char inst_memory[sizeof(flatbuffers::FlatBufferBuilder)]; + static flatbuffers::FlatBufferBuilder* inst = + new (inst_memory) flatbuffers::FlatBufferBuilder( + StackAllocator::kStackAllocatorSize, + &StackAllocator::instance(MicroArenaBufferAlignment())); + return inst; +} + +// A wrapper around FlatBuffer API to help build model easily. +class ModelBuilder { + public: + typedef int32_t Tensor; + typedef int Operator; + typedef int Node; + + // `builder` needs to be available until BuildModel is called. + explicit ModelBuilder(flatbuffers::FlatBufferBuilder* builder) + : builder_(builder) {} + + // Registers an operator that will be used in the model. + Operator RegisterOp(BuiltinOperator op, const char* custom_code); + + // Adds a tensor to the model. + Tensor AddTensor(TensorType type, std::initializer_list shape) { + return AddTensorImpl(type, /* is_variable */ false, shape); + } + + // Adds a variable tensor to the model. + Tensor AddVariableTensor(TensorType type, + std::initializer_list shape) { + return AddTensorImpl(type, /* is_variable */ true, shape); + } + + // Adds a node to the model with given input and output Tensors. + Node AddNode(Operator op, std::initializer_list inputs, + std::initializer_list outputs, + std::initializer_list intermediates = + std::initializer_list{}); + + void AddMetadata(const char* description_string, + const int32_t* metadata_buffer_data, size_t num_elements); + + // Constructs the flatbuffer model using `builder_` and return a pointer to + // it. The returned model has the same lifetime as `builder_`. + // Note the default value of 0 for num_subgraph_inputs means all tensor inputs + // are in subgraph input list. + const Model* BuildModel(std::initializer_list inputs, + std::initializer_list outputs, + size_t num_subgraph_inputs = 0); + + private: + // Adds a tensor to the model. + Tensor AddTensorImpl(TensorType type, bool is_variable, + std::initializer_list shape); + + flatbuffers::FlatBufferBuilder* builder_; + + static constexpr int kMaxOperatorCodes = 10; + flatbuffers::Offset operator_codes_[kMaxOperatorCodes]; + int next_operator_code_id_ = 0; + + static constexpr int kMaxOperators = 50; + flatbuffers::Offset operators_[kMaxOperators]; + int next_operator_id_ = 0; + + static constexpr int kMaxTensors = 50; + flatbuffers::Offset tensors_[kMaxTensors]; + + static constexpr int kMaxMetadataBuffers = 10; + + static constexpr int kMaxMetadatas = 10; + flatbuffers::Offset metadata_[kMaxMetadatas]; + + flatbuffers::Offset metadata_buffers_[kMaxMetadataBuffers]; + + int nbr_of_metadata_buffers_ = 0; + + int next_tensor_id_ = 0; +}; + +ModelBuilder::Operator ModelBuilder::RegisterOp(BuiltinOperator op, + const char* custom_code) { + TFLITE_DCHECK(next_operator_code_id_ <= kMaxOperatorCodes); + operator_codes_[next_operator_code_id_] = tflite::CreateOperatorCodeDirect( + *builder_, /*deprecated_builtin_code=*/0, custom_code, /*version=*/0, op); + next_operator_code_id_++; + return next_operator_code_id_ - 1; +} + +ModelBuilder::Node ModelBuilder::AddNode( + ModelBuilder::Operator op, + std::initializer_list inputs, + std::initializer_list outputs, + std::initializer_list intermediates) { + TFLITE_DCHECK(next_operator_id_ <= kMaxOperators); + operators_[next_operator_id_] = tflite::CreateOperator( + *builder_, op, builder_->CreateVector(inputs.begin(), inputs.size()), + builder_->CreateVector(outputs.begin(), outputs.size()), + BuiltinOptions_NONE, + /*builtin_options=*/0, + /*custom_options=*/0, tflite::CustomOptionsFormat_FLEXBUFFERS, + /*mutating_variable_inputs =*/0, + builder_->CreateVector(intermediates.begin(), intermediates.size())); + next_operator_id_++; + return next_operator_id_ - 1; +} + +void ModelBuilder::AddMetadata(const char* description_string, + const int32_t* metadata_buffer_data, + size_t num_elements) { + metadata_[ModelBuilder::nbr_of_metadata_buffers_] = + CreateMetadata(*builder_, builder_->CreateString(description_string), + 1 + ModelBuilder::nbr_of_metadata_buffers_); + + metadata_buffers_[nbr_of_metadata_buffers_] = tflite::CreateBuffer( + *builder_, builder_->CreateVector((uint8_t*)metadata_buffer_data, + sizeof(uint32_t) * num_elements)); + + ModelBuilder::nbr_of_metadata_buffers_++; +} + +const Model* ModelBuilder::BuildModel( + std::initializer_list inputs, + std::initializer_list outputs, + size_t num_subgraph_inputs) { + // Model schema requires an empty buffer at idx 0. + size_t buffer_size = 1 + ModelBuilder::nbr_of_metadata_buffers_; + flatbuffers::Offset buffers[kMaxMetadataBuffers]; + buffers[0] = tflite::CreateBuffer(*builder_); + + // Place the metadata buffers first in the buffer since the indices for them + // have already been set in AddMetadata() + for (int i = 1; i < ModelBuilder::nbr_of_metadata_buffers_ + 1; ++i) { + buffers[i] = metadata_buffers_[i - 1]; + } + + // Default to single subgraph model. + constexpr size_t subgraphs_size = 1; + + // Find out number of subgraph inputs. + if (num_subgraph_inputs == 0) { + // This is the default case. + num_subgraph_inputs = inputs.size(); + } else { + // A non-zero value of num_subgraph_inputs means that some of + // the operator input tensors are not subgraph inputs. + TFLITE_DCHECK(num_subgraph_inputs <= inputs.size()); + } + + const flatbuffers::Offset subgraphs[subgraphs_size] = { + tflite::CreateSubGraph( + *builder_, builder_->CreateVector(tensors_, next_tensor_id_), + builder_->CreateVector(inputs.begin(), num_subgraph_inputs), + builder_->CreateVector(outputs.begin(), outputs.size()), + builder_->CreateVector(operators_, next_operator_id_), + builder_->CreateString("test_subgraph"))}; + + flatbuffers::Offset model_offset; + if (ModelBuilder::nbr_of_metadata_buffers_ > 0) { + model_offset = tflite::CreateModel( + *builder_, 0, + builder_->CreateVector(operator_codes_, next_operator_code_id_), + builder_->CreateVector(subgraphs, subgraphs_size), + builder_->CreateString("teset_model"), + builder_->CreateVector(buffers, buffer_size), 0, + builder_->CreateVector(metadata_, + ModelBuilder::nbr_of_metadata_buffers_)); + } else { + model_offset = tflite::CreateModel( + *builder_, 0, + builder_->CreateVector(operator_codes_, next_operator_code_id_), + builder_->CreateVector(subgraphs, subgraphs_size), + builder_->CreateString("teset_model"), + builder_->CreateVector(buffers, buffer_size)); + } + + tflite::FinishModelBuffer(*builder_, model_offset); + void* model_pointer = builder_->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +ModelBuilder::Tensor ModelBuilder::AddTensorImpl( + TensorType type, bool is_variable, std::initializer_list shape) { + TFLITE_DCHECK(next_tensor_id_ <= kMaxTensors); + tensors_[next_tensor_id_] = tflite::CreateTensor( + *builder_, builder_->CreateVector(shape.begin(), shape.size()), type, + /* buffer */ 0, /* name */ 0, /* quantization */ 0, + /* is_variable */ is_variable, + /* sparsity */ 0); + next_tensor_id_++; + return next_tensor_id_ - 1; +} + +const Model* BuildSimpleStatefulModel() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* fb_builder = BuilderInstance(); + + ModelBuilder model_builder(fb_builder); + + const int op_id = + model_builder.RegisterOp(BuiltinOperator_CUSTOM, "simple_stateful_op"); + const int input_tensor = model_builder.AddTensor(TensorType_INT8, {3}); + const int median_tensor = model_builder.AddTensor(TensorType_INT8, {3}); + const int invoke_count_tensor = + model_builder.AddTensor(TensorType_INT32, {1}); + const int intermediate_tensor = + model_builder.AddTensor(TensorType_FLOAT32, {0}); + + model_builder.AddNode(op_id, {input_tensor}, + {median_tensor, invoke_count_tensor}, + {intermediate_tensor}); + return model_builder.BuildModel({input_tensor}, + {median_tensor, invoke_count_tensor}); +} + +const Model* BuildSimpleModelWithBranch() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* fb_builder = BuilderInstance(); + + ModelBuilder model_builder(fb_builder); + /* Model structure + | t0 + +------| + | v + | +---------+ + | | n0 | + | | | + | +---------+ + v + + | + +---------+ | t1 + | n1 | | + | | | + +---------+ | + | | + t2 | v + | +---------+ + +-->| n2 | + | | + +-------|-+ + |t3 + v + */ + const int op_id = + model_builder.RegisterOp(BuiltinOperator_CUSTOM, "mock_custom"); + const int t0 = model_builder.AddTensor(TensorType_FLOAT32, {2, 2, 3}); + const int t1 = model_builder.AddTensor(TensorType_FLOAT32, {2, 2, 3}); + const int t2 = model_builder.AddTensor(TensorType_FLOAT32, {2, 2, 3}); + const int t3 = model_builder.AddTensor(TensorType_FLOAT32, {2, 2, 3}); + model_builder.AddNode(op_id, {t0}, {t1}); // n0 + model_builder.AddNode(op_id, {t0}, {t2}); // n1 + model_builder.AddNode(op_id, {t1, t2}, {t3}); // n2 + return model_builder.BuildModel({t0}, {t3}); +} + +const Model* BuildModelWithOfflinePlanning(int number_of_tensors, + const int32_t* metadata_buffer, + NodeConnection* node_conn, + int num_conns, + int num_subgraph_inputs) { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* fb_builder = BuilderInstance(); + + ModelBuilder model_builder(fb_builder); + + const int op_id = + model_builder.RegisterOp(BuiltinOperator_CUSTOM, "mock_custom"); + + for (int i = 0; i < number_of_tensors; ++i) { + model_builder.AddTensor(TensorType_FLOAT32, {2, 2, 3}); + } + + for (int i = 0; i < num_conns; ++i) { + model_builder.AddNode(op_id, node_conn[i].input, node_conn[i].output); + } + + model_builder.AddMetadata( + "OfflineMemoryAllocation", metadata_buffer, + number_of_tensors + tflite::testing::kOfflinePlannerHeaderSize); + + return model_builder.BuildModel( + node_conn[0].input, node_conn[num_conns - 1].output, num_subgraph_inputs); +} + +const Model* BuildModelWithUnusedInputs() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = {CreateBuffer(*builder)}; + constexpr size_t tensor_shape_size = 2; + const int32_t tensor_shape[tensor_shape_size] = {1, 64}; + constexpr size_t tensors_size = 4; + const Offset tensors[tensors_size] = { + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 0, + builder->CreateString("test_input_tensor"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 0, + builder->CreateString("test_unused_input_tensor"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 0, + builder->CreateString("test_output_tensor"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 0, + builder->CreateString("test_unused_tensor"), 0, false), + }; + constexpr size_t inputs_size = 2; + const int32_t inputs[inputs_size] = {0, 1}; + constexpr size_t outputs_size = 1; + const int32_t outputs[outputs_size] = {2}; + constexpr size_t operator_inputs_size = 1; + const int32_t operator_inputs[operator_inputs_size] = {0}; + constexpr size_t operator_outputs_size = 1; + const int32_t operator_outputs[operator_outputs_size] = {2}; + constexpr size_t operators_size = 1; + const Offset operators[operators_size] = { + CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, operator_outputs_size), + BuiltinOptions_NONE), + }; + constexpr size_t subgraphs_size = 1; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(tensors, tensors_size), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(outputs, outputs_size), + builder->CreateVector(operators, operators_size), + builder->CreateString("test_subgraph"))}; + constexpr size_t operator_codes_size = 1; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "mock_custom", + /*version=*/0, BuiltinOperator_CUSTOM)}; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +const Model* BuildModelWithUnusedOperatorOutputs() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = {CreateBuffer(*builder)}; + constexpr size_t tensor_shape_size = 2; + const int32_t tensor_shape[tensor_shape_size] = {1, 64}; + constexpr size_t tensors_size = 2; + const Offset tensors[tensors_size] = { + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 0, + builder->CreateString("test_input_tensor"), 0, false), + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 0, + builder->CreateString("test_unused_output_tensor"), 0, false)}; + constexpr size_t inputs_size = 1; + const int32_t inputs[inputs_size] = {}; + constexpr size_t outputs_size = 1; + const int32_t outputs[outputs_size] = {0}; + constexpr size_t operator_inputs_size = 1; + const int32_t operator_inputs[operator_inputs_size] = {}; + constexpr size_t operator_outputs_size = 2; + const int32_t operator_outputs[operator_outputs_size] = {0, 1}; + constexpr size_t operators_size = 1; + const Offset operators[operators_size] = { + CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, operator_outputs_size), + BuiltinOptions_NONE), + }; + constexpr size_t subgraphs_size = 1; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(tensors, tensors_size), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(outputs, outputs_size), + builder->CreateVector(operators, operators_size), + builder->CreateString("test_subgraph"))}; + constexpr size_t operator_codes_size = 1; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "mock_custom", + /*version=*/0, BuiltinOperator_CUSTOM)}; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +const Model* BuildModelWith256x256Tensor() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* fb_builder = BuilderInstance(); + + ModelBuilder model_builder(fb_builder); + + const int op_id = + model_builder.RegisterOp(BuiltinOperator_CUSTOM, "mock_custom"); + const int input1_tensor = + model_builder.AddTensor(TensorType_INT8, {256, 256}); + const int input2_tensor = + model_builder.AddTensor(TensorType_INT8, {256, 256}); + const int output_tensor = + model_builder.AddTensor(TensorType_INT8, {256, 256}); + + model_builder.AddNode(op_id, {input1_tensor, input2_tensor}, {output_tensor}); + return model_builder.BuildModel({input1_tensor, input2_tensor}, + {output_tensor}); +} + +const Model* BuildSimpleMockModel() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffer_data_size = 1; + const uint8_t buffer_data[buffer_data_size] = {21}; + constexpr size_t buffers_size = 2; + const Offset buffers[buffers_size] = { + CreateBuffer(*builder), + CreateBuffer(*builder, + builder->CreateVector(buffer_data, buffer_data_size))}; + constexpr size_t tensor_shape_size = 1; + const int32_t tensor_shape[tensor_shape_size] = {1}; + constexpr size_t tensors_size = 4; + const Offset tensors[tensors_size] = { + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, + builder->CreateString("test_input_tensor"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 1, + builder->CreateString("test_weight_tensor"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, + builder->CreateString("test_output_tensor"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, + builder->CreateString("test_output2_tensor"), 0, false), + }; + constexpr size_t inputs_size = 1; + const int32_t inputs[inputs_size] = {0}; + constexpr size_t outputs_size = 2; + const int32_t outputs[outputs_size] = {2, 3}; + constexpr size_t operator_inputs_size = 2; + const int32_t operator_inputs[operator_inputs_size] = {0, 1}; + constexpr size_t operator_outputs_size = 1; + const int32_t operator_outputs[operator_outputs_size] = {2}; + const int32_t operator2_outputs[operator_outputs_size] = {3}; + constexpr size_t operators_size = 2; + const Offset operators[operators_size] = { + CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, operator_outputs_size), + BuiltinOptions_NONE), + CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator2_outputs, operator_outputs_size), + BuiltinOptions_NONE), + }; + constexpr size_t subgraphs_size = 1; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(tensors, tensors_size), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(outputs, outputs_size), + builder->CreateVector(operators, operators_size), + builder->CreateString("test_subgraph"))}; + constexpr size_t operator_codes_size = 1; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "mock_custom", + /*version=*/0, BuiltinOperator_CUSTOM)}; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +const Model* BuildComplexMockModel() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffer_data_size = 1; + const uint8_t buffer_data_1[buffer_data_size] = {21}; + const uint8_t buffer_data_2[buffer_data_size] = {21}; + const uint8_t buffer_data_3[buffer_data_size] = {21}; + constexpr size_t buffers_size = 7; + const Offset buffers[buffers_size] = { + // Op 1 buffers: + CreateBuffer(*builder), + CreateBuffer(*builder), + CreateBuffer(*builder, + builder->CreateVector(buffer_data_1, buffer_data_size)), + // Op 2 buffers: + CreateBuffer(*builder), + CreateBuffer(*builder, + builder->CreateVector(buffer_data_2, buffer_data_size)), + // Op 3 buffers: + CreateBuffer(*builder), + CreateBuffer(*builder, + builder->CreateVector(buffer_data_3, buffer_data_size)), + }; + constexpr size_t tensor_shape_size = 1; + const int32_t tensor_shape[tensor_shape_size] = {1}; + + constexpr size_t tensors_size = 10; + const Offset tensors[tensors_size] = { + // Op 1 inputs: + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, builder->CreateString("test_input_tensor_1"), 0, + false /* is_variable */), + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 1, builder->CreateString("test_variable_tensor_1"), + 0, true /* is_variable */), + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 2, builder->CreateString("test_weight_tensor_1"), 0, + false /* is_variable */), + // Op 1 output / Op 2 input: + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, builder->CreateString("test_output_tensor_1"), 0, + false /* is_variable */), + // Op 2 inputs: + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 1, builder->CreateString("test_variable_tensor_2"), + 0, true /* is_variable */), + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 2, builder->CreateString("test_weight_tensor_2"), 0, + false /* is_variable */), + // Op 2 output / Op 3 input: + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, builder->CreateString("test_output_tensor_2"), 0, + false /* is_variable */), + // Op 3 inputs: + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 1, builder->CreateString("test_variable_tensor_3"), + 0, true /* is_variable */), + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 2, builder->CreateString("test_weight_tensor_3"), 0, + false /* is_variable */), + // Op 3 output: + CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, builder->CreateString("test_output_tensor_3"), 0, + false /* is_variable */), + }; + + constexpr size_t operators_size = 3; + Offset operators[operators_size]; + { + // Set Op 1 attributes: + constexpr size_t operator_inputs_size = 3; + const int32_t operator_inputs[operator_inputs_size] = {0, 1, 2}; + constexpr size_t operator_outputs_size = 1; + const int32_t operator_outputs[operator_outputs_size] = {3}; + + operators[0] = {CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, operator_outputs_size), + BuiltinOptions_NONE)}; + } + + { + // Set Op 2 attributes + constexpr size_t operator_inputs_size = 3; + const int32_t operator_inputs[operator_inputs_size] = {3, 4, 5}; + constexpr size_t operator_outputs_size = 1; + const int32_t operator_outputs[operator_outputs_size] = {6}; + + operators[1] = {CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, operator_outputs_size), + BuiltinOptions_NONE)}; + } + + { + // Set Op 3 attributes + constexpr size_t operator_inputs_size = 3; + const int32_t operator_inputs[operator_inputs_size] = {6, 7, 8}; + constexpr size_t operator_outputs_size = 1; + const int32_t operator_outputs[operator_outputs_size] = {9}; + + operators[2] = {CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, operator_outputs_size), + BuiltinOptions_NONE)}; + } + + constexpr size_t inputs_size = 1; + const int32_t inputs[inputs_size] = {0}; + constexpr size_t outputs_size = 1; + const int32_t outputs[outputs_size] = {9}; + + constexpr size_t subgraphs_size = 1; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(tensors, tensors_size), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(outputs, outputs_size), + builder->CreateVector(operators, operators_size), + builder->CreateString("test_subgraph"))}; + + constexpr size_t operator_codes_size = 1; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "mock_custom", + /*version=*/0, BuiltinOperator_CUSTOM)}; + + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +const Model* BuildSimpleMultipleInputsModel() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = { + CreateBuffer(*builder), + }; + constexpr size_t tensor_shape_size = 1; + const int32_t tensor_shape[tensor_shape_size] = {1}; + constexpr size_t tensors_size = 4; + const Offset tensors[tensors_size] = { + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, + builder->CreateString("test_input_tensor1"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT8, 0, + builder->CreateString("test_input_tensor2"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, + builder->CreateString("test_input_tensor3"), 0, false), + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, + builder->CreateString("test_output_tensor"), 0, false), + }; + constexpr size_t inputs_size = 3; + const int32_t inputs[inputs_size] = {0, 1, 2}; + constexpr size_t outputs_size = 1; + const int32_t outputs[outputs_size] = {3}; + constexpr size_t operator_inputs_size = 3; + const int32_t operator_inputs[operator_inputs_size] = {0, 1, 2}; + constexpr size_t operator_outputs_size = 1; + const int32_t operator_outputs[operator_outputs_size] = {3}; + constexpr size_t operators_size = 1; + const Offset operators[operators_size] = { + CreateOperator( + *builder, 0, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, operator_outputs_size), + BuiltinOptions_NONE), + }; + constexpr size_t subgraphs_size = 1; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(tensors, tensors_size), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(outputs, outputs_size), + builder->CreateVector(operators, operators_size), + builder->CreateString("test_subgraph"))}; + constexpr size_t operator_codes_size = 1; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_CUSTOM)}; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +const Model* BuildSimpleModelWithSubgraphsAndIf() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = { + CreateBuffer(*builder), + }; + const int32_t condition_tensor_shape[] = {1}; + const int32_t data_tensor_shape[] = {1, 2}; + constexpr size_t tensors_size = 4; + const Offset subgraph1_tensors[tensors_size] = { + CreateTensor(*builder, builder->CreateVector(condition_tensor_shape, 1), + TensorType_BOOL, 0, + builder->CreateString("condition tensor"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor"), 0, false), + }; + const Offset subgraph2_tensors[tensors_size] = { + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor"), 0, false), + }; + const Offset subgraph3_tensors[tensors_size] = { + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor"), 0, false), + }; + + constexpr size_t if_inputs_size = 3; + const int32_t if_inputs[if_inputs_size] = {0, 1, 2}; + constexpr size_t outputs_size = 1; + const int32_t if_outputs[outputs_size] = {3}; + constexpr size_t operator_inputs_size = 2; + const int32_t operator_inputs[operator_inputs_size] = {0, 1}; + const int32_t operator_outputs[outputs_size] = {2}; + constexpr size_t operators_size = 1; + const Offset subgraph1_operators[operators_size] = { + CreateOperator( + *builder, 0, builder->CreateVector(if_inputs, if_inputs_size), + builder->CreateVector(if_outputs, outputs_size), + BuiltinOptions_IfOptions, CreateIfOptions(*builder, 1, 2).Union()), + }; + const Offset subgraph2_operators[operators_size] = { + CreateOperator( + *builder, 1, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, outputs_size), + BuiltinOptions_NONE), + }; + const Offset subgraph3_operators[operators_size] = { + CreateOperator( + *builder, 2, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, outputs_size), + BuiltinOptions_NONE), + }; + constexpr size_t subgraphs_size = 3; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(subgraph1_tensors, 4), + builder->CreateVector(if_inputs, if_inputs_size), + builder->CreateVector(if_outputs, outputs_size), + builder->CreateVector(subgraph1_operators, operators_size), + builder->CreateString("if_subgraph")), + CreateSubGraph( + *builder, builder->CreateVector(subgraph2_tensors, 3), + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, outputs_size), + builder->CreateVector(subgraph2_operators, operators_size), + builder->CreateString("then_subgraph")), + CreateSubGraph( + *builder, builder->CreateVector(subgraph3_tensors, 3), + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, outputs_size), + builder->CreateVector(subgraph3_operators, operators_size), + builder->CreateString("else_subgraph")), + }; + constexpr size_t operator_codes_size = 3; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_IF), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_ADD), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_MUL), + }; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +const Model* BuildSimpleModelWithIfAndEmptySubgraph() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = { + CreateBuffer(*builder), + }; + const int32_t condition_tensor_shape[] = {1}; + const int32_t data_tensor_shape[] = {1, 2}; + constexpr size_t tensors_size = 4; + const Offset subgraph1_tensors[tensors_size] = { + CreateTensor(*builder, builder->CreateVector(condition_tensor_shape, 1), + TensorType_BOOL, 0, + builder->CreateString("condition tensor"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor"), 0, false), + }; + const Offset subgraph2_tensors[tensors_size] = { + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor"), 0, false), + }; + const Offset subgraph3_tensors[tensors_size] = { + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 2), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor"), 0, false), + }; + + constexpr size_t if_inputs_size = 3; + const int32_t if_inputs[if_inputs_size] = {0, 1, 2}; + constexpr size_t outputs_size = 1; + const int32_t if_outputs[outputs_size] = {3}; + constexpr size_t operator_inputs_size = 2; + const int32_t operator_inputs[operator_inputs_size] = {0, 1}; + const int32_t operator_outputs[outputs_size] = {2}; + constexpr size_t operators_size = 1; + const Offset subgraph1_operators[operators_size] = { + CreateOperator( + *builder, 0, builder->CreateVector(if_inputs, if_inputs_size), + builder->CreateVector(if_outputs, outputs_size), + BuiltinOptions_IfOptions, CreateIfOptions(*builder, 1, 2).Union()), + }; + const Offset subgraph2_operators[operators_size] = { + CreateOperator( + *builder, 1, + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, outputs_size), + BuiltinOptions_NONE), + }; + constexpr size_t subgraphs_size = 3; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(subgraph1_tensors, 4), + builder->CreateVector(if_inputs, if_inputs_size), + builder->CreateVector(if_outputs, outputs_size), + builder->CreateVector(subgraph1_operators, operators_size), + builder->CreateString("if_subgraph")), + CreateSubGraph( + *builder, builder->CreateVector(subgraph2_tensors, 3), + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, outputs_size), + builder->CreateVector(subgraph2_operators, operators_size), + builder->CreateString("then_subgraph")), + CreateSubGraph( + *builder, builder->CreateVector(subgraph3_tensors, 3), + builder->CreateVector(operator_inputs, operator_inputs_size), + builder->CreateVector(operator_outputs, outputs_size), 0, + builder->CreateString("else_subgraph")), + }; + constexpr size_t operator_codes_size = 3; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_IF), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_ADD), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_MUL), + }; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +const Model* BuildSimpleModelWithSubgraphsAndWhile() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = { + CreateBuffer(*builder), + }; + const int32_t data_tensor_shape[] = {1, 1}; + constexpr size_t while_tensors_size = 4; + constexpr size_t op_tensors_size = 3; + const Offset subgraph0_tensors[while_tensors_size] = { + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor0"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor0"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor1"), 0, false), + }; + const Offset subgraph1_tensors[op_tensors_size] = { + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_BOOL, 0, + builder->CreateString("condition_tensor"), 0, false), + }; + const Offset subgraph2_tensors[op_tensors_size] = { + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor0"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(data_tensor_shape, 1), + TensorType_FLOAT32, 0, + builder->CreateString("output_tensor0"), 0, false), + }; + + constexpr size_t inputs_size = 2; + const int32_t inputs[inputs_size] = {0, 1}; + constexpr size_t while_outputs_size = 2; + const int32_t while_outputs[while_outputs_size] = {2, 3}; + constexpr size_t cond_outputs_size = 1; + const int32_t cond_outputs[cond_outputs_size] = {2}; + constexpr size_t add_outputs_size = 1; + const int32_t add_outputs[add_outputs_size] = {2}; + constexpr size_t add_subgraph_outputs_size = 2; + const int32_t add_subgraph_outputs[add_subgraph_outputs_size] = {2, 1}; + constexpr size_t operators_size = 1; + const Offset subgraph0_operators[operators_size] = { + CreateOperator(*builder, 0, builder->CreateVector(inputs, inputs_size), + builder->CreateVector(while_outputs, while_outputs_size), + BuiltinOptions_WhileOptions, + CreateWhileOptions(*builder, 1, 2).Union()), + }; + const Offset subgraph1_operators[operators_size] = { + CreateOperator(*builder, 1, builder->CreateVector(inputs, inputs_size), + builder->CreateVector(cond_outputs, cond_outputs_size), + BuiltinOptions_NONE), + }; + const Offset subgraph2_operators[operators_size] = { + CreateOperator(*builder, 2, builder->CreateVector(inputs, inputs_size), + builder->CreateVector(add_outputs, add_outputs_size), + BuiltinOptions_NONE), + }; + constexpr size_t subgraphs_size = 3; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph(*builder, builder->CreateVector(subgraph0_tensors, 4), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(while_outputs, while_outputs_size), + builder->CreateVector(subgraph0_operators, operators_size), + builder->CreateString("while_subgraph")), + CreateSubGraph(*builder, builder->CreateVector(subgraph1_tensors, 3), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(cond_outputs, cond_outputs_size), + builder->CreateVector(subgraph1_operators, operators_size), + builder->CreateString("cond_subgraph")), + CreateSubGraph(*builder, builder->CreateVector(subgraph2_tensors, 3), + builder->CreateVector(inputs, inputs_size), + builder->CreateVector(add_subgraph_outputs, + add_subgraph_outputs_size), + builder->CreateVector(subgraph2_operators, operators_size), + builder->CreateString("body_subgraph")), + }; + constexpr size_t operator_codes_size = 3; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_WHILE), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_LESS), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "multiple_inputs_op", + /*version=*/0, BuiltinOperator_ADD), + }; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +// Build a model with If and two subgraphs: two data tensors A1 of size 2, A2 of +// size 4 are first concatenated, then cut to a new tensor A3 of size 3; the new +// tensor A3 of size 3 is then concatenated with A2 tensor of size 4 to produce +// a final output tensor A4. This model is specially crafted to capture the +// corner case outlined in go/avoid-memory-corruption-in-if-operator. +// +// Subgraph0 +// A0(1) A2_0(4) A1_0(2) +// | | | ---+ +// v v v | +// +--------------+ | +// | IF | | +// +------+-------+ | +// | A3_0(3) | +// v | +// +--------------+ | +// | CUSTOM |<---+ +// +------+-------+ +// | +// v +// A4_0(8) +// +// Subgraph1/2 +// A1_1(2) A2_1(4) +// | | +// v v +// +---------------+ +// | CUSTOM | +// +-------+-------+ +// | +// v A3_1(3) +// +// And it leads to memory plan as below +// +// Subgraph0 Layout +// +// +// <------------A4_0 -------------> <----- A2_0-------> <----A3_0 ---> +// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ +// | | | | | | | | | 3 | 4 | 5 | 6 | | | | +// +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ +// +// +----+----+----+ +// | 1 | 2 | A0 | +// +----+----+----+ +// <---A1_0--> +// +// Subgraph 1 Layout +// +// +----+----+----+----+----+----+----+----+----+ +// | | | | | | | | | | +// +----+----+----+----+----+----+----+----+----+ +// +// +// <------A2_1 -------><----A3_1 ---><--A1_1---> +// +// +// A1_1 of subgraph 1 will overlap with A2_0 of subgraph 0. +// In a buggy implementation of IF, two overwrite may happen: +// 1. copying input from A1_0 to A1_1 overwrites A2_0 before A2_0 is copied to +// A2_1; thus subgraph 1 produce incorrect output. +// 2. copying output from A3_1 to A4_0 overwrites A1_0, which should remain +// intact so that it can be used by the OP after the IF operator in subgraph 0 +// + +const Model* BuildModelWithIfAndSubgraphInputTensorOverlap() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr TensorType kTensorType = TensorType_INT32; + constexpr int kBlockSize = + tflite::MicroArenaBufferAlignment() / sizeof(int32_t); + constexpr size_t kBuffersCount = 1; + const Offset buffers[kBuffersCount] = { + CreateBuffer(*builder), + }; + const int32_t kConditionTensorShape[] = {1}; + const int32_t kIfInput1TensorShape[] = {2 * kBlockSize}; + const int32_t kIfInput2TensorShape[] = {4 * kBlockSize}; + const int32_t kIfOutputTensorShape[] = {3 * kBlockSize}; + const int32_t kFinalOutputTensorShape[] = {8 * kBlockSize}; + constexpr size_t kSubgraph0TensorsCount = 5; + const Offset kSubgraph0Tensors[kSubgraph0TensorsCount] = { + CreateTensor(*builder, builder->CreateVector(kConditionTensorShape, 1), + TensorType_BOOL, 0, + builder->CreateString("condition tensor"), 0, false), + CreateTensor(*builder, builder->CreateVector(kIfInput1TensorShape, 1), + kTensorType, 0, builder->CreateString("if_input_tensor1"), 0, + false), + CreateTensor(*builder, builder->CreateVector(kIfInput2TensorShape, 1), + kTensorType, 0, builder->CreateString("if_input_tensor2"), 0, + false), + CreateTensor(*builder, builder->CreateVector(kIfOutputTensorShape, 1), + kTensorType, 0, builder->CreateString("if_output_tensor"), 0, + false), + CreateTensor(*builder, builder->CreateVector(kFinalOutputTensorShape, 1), + kTensorType, 0, builder->CreateString("final_output_tensor"), + 0, false), + }; + + // Subgraph 1 is the chosen path if condition tensor in IF is true. + constexpr size_t kSubgraph1TensorsCount = 3; + const Offset kSubgraph1Tensors[kSubgraph1TensorsCount] = { + CreateTensor(*builder, builder->CreateVector(kIfInput1TensorShape, 1), + kTensorType, 0, + builder->CreateString("subgraph1_input_tensor1"), 0, false), + CreateTensor(*builder, builder->CreateVector(kIfInput2TensorShape, 1), + kTensorType, 0, + builder->CreateString("subgraph1_input_tensor2"), 0, false), + CreateTensor(*builder, builder->CreateVector(kIfOutputTensorShape, 1), + kTensorType, 0, + builder->CreateString("subgraph1_output_tensor"), 0, false), + }; + + // Subgraph 2 is the chosen path if condition tensor in IF is false + constexpr size_t kSubgraph2TensorsCount = 3; + const Offset kSubgraph2Tensors[kSubgraph2TensorsCount] = { + CreateTensor(*builder, builder->CreateVector(kIfInput1TensorShape, 1), + kTensorType, 0, builder->CreateString("if_input_tensor1"), 0, + false), + CreateTensor(*builder, builder->CreateVector(kIfInput2TensorShape, 1), + kTensorType, 0, builder->CreateString("if_input_tensor2"), 0, + false), + CreateTensor(*builder, builder->CreateVector(kIfOutputTensorShape, 1), + kTensorType, 0, builder->CreateString("if_output_tensor"), 0, + false), + }; + + constexpr int kIfOpCodeIndex = 0; + constexpr int kCustomOpCodeIndex = 1; + + constexpr size_t kIfInputsCount = 3; + const int32_t kIfInputs[kIfInputsCount] = {0, 1, 2}; + constexpr size_t kOutputsCount = 1; + const int32_t kIfOutputs[kOutputsCount] = {3}; + constexpr size_t kOpAfterIfInputsCount = 2; + const int32_t kOpAfterIfInputs[kOpAfterIfInputsCount] = {3, 2}; + const int32_t kOpAfterIfOutputs[kOutputsCount] = {4}; + constexpr size_t kOperatorsCount = 2; + const Offset kSubgraph0Operators[kOperatorsCount] = { + CreateOperator(*builder, kIfOpCodeIndex, + builder->CreateVector(kIfInputs, kIfInputsCount), + builder->CreateVector(kIfOutputs, kOutputsCount), + BuiltinOptions_IfOptions, + CreateIfOptions(*builder, 1, 2).Union()), + CreateOperator( + *builder, kCustomOpCodeIndex, + builder->CreateVector(kOpAfterIfInputs, kOpAfterIfInputsCount), + builder->CreateVector(kOpAfterIfOutputs, kOutputsCount)), + }; + + constexpr size_t kSubgraph1InputsCount = 2; + const int32_t kSubgraph1Inputs[kSubgraph1InputsCount] = {0, 1}; + constexpr size_t kSubgraph1OutputsCount = 1; + const int32_t kSubgraph1Outputs[kSubgraph1OutputsCount] = {2}; + constexpr size_t kSubgraph1OperatorsCount = 1; + const Offset kSubgraph1Operators[kSubgraph1OperatorsCount] = { + CreateOperator( + *builder, kCustomOpCodeIndex, + builder->CreateVector(kSubgraph1Inputs, kSubgraph1InputsCount), + builder->CreateVector(kSubgraph1Outputs, kSubgraph1OutputsCount), + BuiltinOptions_NONE), + }; + + constexpr size_t kSubgraph2InputsCount = 2; + const int32_t kSubgraph2Inputs[kSubgraph2InputsCount] = {0, 1}; + constexpr size_t kSubgraph2OutputsCount = 1; + const int32_t kSubgraph2Outputs[kSubgraph2OutputsCount] = {2}; + constexpr size_t kSubgraph2OperatorsCount = 1; + const Offset kSubgraph2Operators[kSubgraph2OperatorsCount] = { + CreateOperator( + *builder, kCustomOpCodeIndex, + builder->CreateVector(kSubgraph2Inputs, kSubgraph2InputsCount), + builder->CreateVector(kSubgraph2Outputs, kSubgraph2OutputsCount), + BuiltinOptions_NONE), + }; + + constexpr size_t kSubgraphsCount = 3; + const Offset kSubgraphs[kSubgraphsCount] = { + CreateSubGraph( + *builder, + builder->CreateVector(kSubgraph0Tensors, kSubgraph0TensorsCount), + builder->CreateVector(kIfInputs, kIfInputsCount), + builder->CreateVector(kOpAfterIfOutputs, kOutputsCount), + builder->CreateVector(kSubgraph0Operators, kOperatorsCount), + builder->CreateString("if_subgraph")), + CreateSubGraph( + *builder, + builder->CreateVector(kSubgraph1Tensors, kSubgraph1TensorsCount), + builder->CreateVector(kSubgraph1Inputs, kSubgraph1InputsCount), + builder->CreateVector(kSubgraph1Outputs, kSubgraph1OutputsCount), + builder->CreateVector(kSubgraph1Operators, kSubgraph1OperatorsCount), + builder->CreateString("then_subgraph")), + CreateSubGraph( + *builder, + builder->CreateVector(kSubgraph2Tensors, kSubgraph2TensorsCount), + builder->CreateVector(kSubgraph2Inputs, kSubgraph2InputsCount), + builder->CreateVector(kSubgraph2Outputs, kSubgraph2OutputsCount), + builder->CreateVector(kSubgraph2Operators, kSubgraph2OperatorsCount), + builder->CreateString("else_subgraph")), + }; + + constexpr size_t kOperatorCodesCount = 2; + const Offset kOperatorCodes[kOperatorCodesCount] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, "if", + /*version=*/0, BuiltinOperator_IF), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "custom_packer_op", + /*version=*/0, BuiltinOperator_CUSTOM), + }; + const Offset kModelOffset = CreateModel( + *builder, 0, builder->CreateVector(kOperatorCodes, kOperatorCodesCount), + builder->CreateVector(kSubgraphs, kSubgraphsCount), + builder->CreateString("test_model"), + builder->CreateVector(buffers, kBuffersCount)); + FinishModelBuffer(*builder, kModelOffset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +// Mock model with one main subgraph containing a single CALL_ONCE op (with null +// inputs and outputs) which invokes a second subgraph which has null inputs and +// outputs. +const Model* BuildSimpleMockModelWithNullInputsOutputs() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = { + CreateBuffer(*builder), + }; + constexpr size_t tensor_shape_size = 1; + const int32_t tensor_shape[tensor_shape_size] = {0}; + constexpr size_t tensors_size = 1; + const Offset tensors[tensors_size] = { + CreateTensor(*builder, + builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, + builder->CreateString("test_input_tensor1"), 0, false), + }; + constexpr size_t subgraph0_inputs_size = 1; + const int32_t subgraph0_inputs[subgraph0_inputs_size] = {0}; + constexpr size_t subgraph0_outputs_size = 1; + const int32_t subgraph0_outputs[subgraph0_outputs_size] = {0}; + constexpr size_t operators_size = 1; + const Offset subgraph0_operators[operators_size] = { + CreateOperator(*builder, 0, {}, {}, BuiltinOptions_CallOnceOptions, + CreateCallOnceOptions(*builder, 1).Union()), + }; + const Offset subgraph1_operators[operators_size] = { + CreateOperator(*builder, 1, {}, {}, BuiltinOptions_NONE)}; + constexpr size_t subgraphs_size = 2; + const Offset subgraphs[subgraphs_size] = { + CreateSubGraph( + *builder, builder->CreateVector(tensors, tensors_size), + builder->CreateVector(subgraph0_inputs, subgraph0_inputs_size), + builder->CreateVector(subgraph0_outputs, subgraph0_outputs_size), + builder->CreateVector(subgraph0_operators, operators_size), + builder->CreateString("main_subgraph")), + CreateSubGraph(*builder, builder->CreateVector(tensors, tensors_size), {}, + {}, + builder->CreateVector(subgraph1_operators, operators_size), + builder->CreateString("secondary subgraph")), + }; + constexpr size_t operator_codes_size = 2; + const Offset operator_codes[operator_codes_size] = { + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, + "call_once_op", + /*version=*/0, BuiltinOperator_CALL_ONCE), + CreateOperatorCodeDirect(*builder, /*deprecated_builtin_code=*/0, "no_op", + /*version=*/0, BuiltinOperator_CUSTOM)}; + const Offset model_offset = CreateModel( + *builder, 0, builder->CreateVector(operator_codes, operator_codes_size), + builder->CreateVector(subgraphs, subgraphs_size), + builder->CreateString("test_model"), + builder->CreateVector(buffers, buffers_size)); + FinishModelBuffer(*builder, model_offset); + void* model_pointer = builder->GetBufferPointer(); + const Model* model = flatbuffers::GetRoot(model_pointer); + return model; +} + +} // namespace + +const TfLiteRegistration* SimpleStatefulOp::getRegistration() { + return GetMutableRegistration(); +} + +TfLiteRegistration* SimpleStatefulOp::GetMutableRegistration() { + static TfLiteRegistration r; + r.init = Init; + r.prepare = Prepare; + r.invoke = Invoke; + return &r; +} + +void* SimpleStatefulOp::Init(TfLiteContext* context, const char* buffer, + size_t length) { + TFLITE_DCHECK(context->AllocateBufferForEval == nullptr); + TFLITE_DCHECK(context->GetScratchBuffer == nullptr); + TFLITE_DCHECK(context->RequestScratchBufferInArena == nullptr); + + void* raw = context->AllocatePersistentBuffer(context, sizeof(OpData)); + OpData* data = reinterpret_cast(raw); + *data = {}; + return raw; +} + +TfLiteStatus SimpleStatefulOp::Prepare(TfLiteContext* context, + TfLiteNode* node) { + OpData* data = reinterpret_cast(node->user_data); + + // Make sure that the input is in uint8_t with at least 1 data entry. + MicroContext* micro_context = GetMicroContext(context); + TfLiteTensor* input = + micro_context->AllocateTempInputTensor(node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + + if (input->type != kTfLiteInt8) return kTfLiteError; + if (NumElements(input->dims) == 0) return kTfLiteError; + + // Allocate a temporary buffer with the same size of input for sorting. + TF_LITE_ENSURE_STATUS(context->RequestScratchBufferInArena( + context, sizeof(uint8_t) * NumElements(input->dims), + &data->sorting_buffer)); + // We can interleave scratch / persistent buffer allocation. + data->invoke_count = reinterpret_cast( + context->AllocatePersistentBuffer(context, sizeof(int))); + *data->invoke_count = 0; + + micro_context->DeallocateTempTfLiteTensor(input); + return kTfLiteOk; +} + +TfLiteStatus SimpleStatefulOp::Invoke(TfLiteContext* context, + TfLiteNode* node) { + OpData* data = reinterpret_cast(node->user_data); + *data->invoke_count += 1; + + const TfLiteEvalTensor* input = + tflite::micro::GetEvalInput(context, node, kInputTensor); + TF_LITE_ENSURE(context, input != nullptr); + const uint8_t* input_data = input->data.uint8; + int size = NumElements(input->dims); + + uint8_t* sorting_buffer = reinterpret_cast( + context->GetScratchBuffer(context, data->sorting_buffer)); + // Copy inputs data to the sorting buffer. We don't want to mutate the input + // tensor as it might be used by a another node. + for (int i = 0; i < size; i++) { + sorting_buffer[i] = input_data[i]; + } + + // In place insertion sort on `sorting_buffer`. + for (int i = 1; i < size; i++) { + for (int j = i; j > 0 && sorting_buffer[j] < sorting_buffer[j - 1]; j--) { + std::swap(sorting_buffer[j], sorting_buffer[j - 1]); + } + } + + TfLiteEvalTensor* median = + tflite::micro::GetEvalOutput(context, node, kMedianTensor); + TF_LITE_ENSURE(context, median != nullptr); + uint8_t* median_data = median->data.uint8; + TfLiteEvalTensor* invoke_count = + tflite::micro::GetEvalOutput(context, node, kInvokeCount); + TF_LITE_ENSURE(context, invoke_count != nullptr); + int32_t* invoke_count_data = invoke_count->data.i32; + + median_data[0] = sorting_buffer[size / 2]; + invoke_count_data[0] = *data->invoke_count; + return kTfLiteOk; +} + +const TfLiteRegistration* MockCustom::getRegistration() { + return GetMutableRegistration(); +} + +TfLiteRegistration* MockCustom::GetMutableRegistration() { + static TfLiteRegistration r; + r.init = Init; + r.prepare = Prepare; + r.invoke = Invoke; + r.free = Free; + return &r; +} + +void* MockCustom::Init(TfLiteContext* context, const char* buffer, + size_t length) { + // We don't support delegate in TFL micro. This is a weak check to test if + // context struct being zero-initialized. + TFLITE_DCHECK(context->ReplaceNodeSubsetsWithDelegateKernels == nullptr); + freed_ = false; + // Do nothing. + return nullptr; +} + +void MockCustom::Free(TfLiteContext* context, void* buffer) { freed_ = true; } + +TfLiteStatus MockCustom::Prepare(TfLiteContext* context, TfLiteNode* node) { + return kTfLiteOk; +} + +TfLiteStatus MockCustom::Invoke(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TF_LITE_ENSURE(context, input != nullptr); + const int32_t* input_data = input->data.i32; + const TfLiteEvalTensor* weight = + tflite::micro::GetEvalInput(context, node, 1); + TF_LITE_ENSURE(context, weight != nullptr); + const uint8_t* weight_data = weight->data.uint8; + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE(context, output != nullptr); + int32_t* output_data = output->data.i32; + output_data[0] = + 0; // Catch output tensor sharing memory with an input tensor + output_data[0] = input_data[0] + weight_data[0]; + return kTfLiteOk; +} + +bool MockCustom::freed_ = false; + +const TfLiteRegistration* MultipleInputs::getRegistration() { + return GetMutableRegistration(); +} + +TfLiteRegistration* MultipleInputs::GetMutableRegistration() { + static TfLiteRegistration r; + r.init = Init; + r.prepare = Prepare; + r.invoke = Invoke; + r.free = Free; + return &r; +} + +void* MultipleInputs::Init(TfLiteContext* context, const char* buffer, + size_t length) { + // We don't support delegate in TFL micro. This is a weak check to test if + // context struct being zero-initialized. + TFLITE_DCHECK(context->ReplaceNodeSubsetsWithDelegateKernels == nullptr); + freed_ = false; + // Do nothing. + return nullptr; +} + +void MultipleInputs::Free(TfLiteContext* context, void* buffer) { + freed_ = true; +} + +TfLiteStatus MultipleInputs::Prepare(TfLiteContext* context, TfLiteNode* node) { + return kTfLiteOk; +} + +TfLiteStatus MultipleInputs::Invoke(TfLiteContext* context, TfLiteNode* node) { + const TfLiteEvalTensor* input = tflite::micro::GetEvalInput(context, node, 0); + TF_LITE_ENSURE(context, input != nullptr); + const int32_t* input_data = input->data.i32; + const TfLiteEvalTensor* input1 = + tflite::micro::GetEvalInput(context, node, 1); + TF_LITE_ENSURE(context, input1 != nullptr); + const int32_t* input_data1 = input1->data.i32; + const TfLiteEvalTensor* input2 = + tflite::micro::GetEvalInput(context, node, 2); + TF_LITE_ENSURE(context, input2 != nullptr); + const int32_t* input_data2 = input2->data.i32; + + TfLiteEvalTensor* output = tflite::micro::GetEvalOutput(context, node, 0); + TF_LITE_ENSURE(context, output != nullptr); + int32_t* output_data = output->data.i32; + output_data[0] = + 0; // Catch output tensor sharing memory with an input tensor + output_data[0] = input_data[0] + input_data1[0] + input_data2[0]; + return kTfLiteOk; +} + +bool MultipleInputs::freed_ = false; + +const TfLiteRegistration* NoOp::getRegistration() { + return GetMutableRegistration(); +} + +TfLiteRegistration* NoOp::GetMutableRegistration() { + static TfLiteRegistration r; + r.init = Init; + r.prepare = Prepare; + r.invoke = Invoke; + r.free = Free; + return &r; +} + +void* NoOp::Init(TfLiteContext* context, const char* buffer, size_t length) { + // We don't support delegate in TFL micro. This is a weak check to test if + // context struct being zero-initialized. + TFLITE_DCHECK(context->ReplaceNodeSubsetsWithDelegateKernels == nullptr); + freed_ = false; + // Do nothing. + return nullptr; +} + +void NoOp::Free(TfLiteContext* context, void* buffer) { freed_ = true; } + +TfLiteStatus NoOp::Prepare(TfLiteContext* context, TfLiteNode* node) { + return kTfLiteOk; +} + +TfLiteStatus NoOp::Invoke(TfLiteContext* context, TfLiteNode* node) { + return kTfLiteOk; +} + +bool NoOp::freed_ = false; + +AllOpsResolver GetOpResolver() { + AllOpsResolver op_resolver; + op_resolver.AddCustom("mock_custom", MockCustom::GetMutableRegistration()); + op_resolver.AddCustom("simple_stateful_op", + SimpleStatefulOp::GetMutableRegistration()); + op_resolver.AddCustom("multiple_inputs_op", + MultipleInputs::GetMutableRegistration()); + op_resolver.AddCustom("no_op", NoOp::GetMutableRegistration()); + op_resolver.AddCustom("custom_packer_op", PackerOp::GetMutableRegistration()); + return op_resolver; +} + +const Model* GetModelWithUnusedInputs() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildModelWithUnusedInputs()); + } + return model; +} + +const Model* GetModelWithUnusedOperatorOutputs() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildModelWithUnusedOperatorOutputs()); + } + return model; +} + +const Model* GetModelWith256x256Tensor() { + static const Model* model = BuildModelWith256x256Tensor(); + return model; +} + +const Model* GetSimpleMockModel() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleMockModel()); + } + return model; +} + +const Model* GetSimpleMultipleInputsModel() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleMultipleInputsModel()); + } + return model; +} + +const Model* GetSimpleModelWithSubgraphsAndIf() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleModelWithSubgraphsAndIf()); + } + return model; +} + +const Model* GetSimpleModelWithIfAndEmptySubgraph() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleModelWithIfAndEmptySubgraph()); + } + return model; +} + +const Model* GetSimpleModelWithSubgraphsAndWhile() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleModelWithSubgraphsAndWhile()); + } + return model; +} + +const Model* GetModelWithIfAndSubgraphInputTensorOverlap() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildModelWithIfAndSubgraphInputTensorOverlap()); + } + return model; +} + +const Model* GetSimpleModelWithNullInputsAndOutputs() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleMockModelWithNullInputsOutputs()); + } + return model; +} + +const Model* GetComplexMockModel() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildComplexMockModel()); + } + return model; +} + +const Model* GetSimpleModelWithBranch() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleModelWithBranch()); + } + return model; +} + +const Model* GetModelWithOfflinePlanning(int num_tensors, + const int32_t* metadata_buffer, + NodeConnection* node_conn, + int num_conns, + int num_subgraph_inputs) { + const Model* model = BuildModelWithOfflinePlanning( + num_tensors, metadata_buffer, node_conn, num_conns, num_subgraph_inputs); + return model; +} + +const Model* GetSimpleStatefulModel() { + static Model* model = nullptr; + if (!model) { + model = const_cast(BuildSimpleStatefulModel()); + } + return model; +} + +const Tensor* Create1dFlatbufferTensor(int size, bool is_variable) { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + constexpr size_t tensor_shape_size = 1; + const int32_t tensor_shape[tensor_shape_size] = {size}; + const Offset tensor_offset = CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, builder->CreateString("test_tensor"), 0, + is_variable); + builder->Finish(tensor_offset); + void* tensor_pointer = builder->GetBufferPointer(); + const Tensor* tensor = flatbuffers::GetRoot(tensor_pointer); + return tensor; +} + +const Tensor* CreateQuantizedFlatbufferTensor(int size) { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + constexpr size_t quant_params_size = 1; + const float min_array[quant_params_size] = {0.1f}; + const float max_array[quant_params_size] = {0.2f}; + const float scale_array[quant_params_size] = {0.3f}; + const int64_t zero_point_array[quant_params_size] = {100ll}; + + const Offset quant_params = + CreateQuantizationParameters( + *builder, + /*min=*/builder->CreateVector(min_array, quant_params_size), + /*max=*/builder->CreateVector(max_array, quant_params_size), + /*scale=*/ + builder->CreateVector(scale_array, quant_params_size), + /*zero_point=*/ + builder->CreateVector(zero_point_array, quant_params_size)); + + constexpr size_t tensor_shape_size = 1; + const int32_t tensor_shape[tensor_shape_size] = {size}; + const Offset tensor_offset = CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, builder->CreateString("test_tensor"), quant_params, + false); + builder->Finish(tensor_offset); + void* tensor_pointer = builder->GetBufferPointer(); + const Tensor* tensor = flatbuffers::GetRoot(tensor_pointer); + return tensor; +} + +const Tensor* CreateMissingQuantizationFlatbufferTensor(int size) { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + const Offset quant_params = + CreateQuantizationParameters(*builder, 0, 0, 0, 0, + QuantizationDetails_NONE, 0, 0); + constexpr size_t tensor_shape_size = 1; + const int32_t tensor_shape[tensor_shape_size] = {size}; + const Offset tensor_offset = CreateTensor( + *builder, builder->CreateVector(tensor_shape, tensor_shape_size), + TensorType_INT32, 0, builder->CreateString("test_tensor"), quant_params, + false); + builder->Finish(tensor_offset); + void* tensor_pointer = builder->GetBufferPointer(); + const Tensor* tensor = flatbuffers::GetRoot(tensor_pointer); + return tensor; +} + +const flatbuffers::Vector>* +CreateFlatbufferBuffers() { + using flatbuffers::Offset; + flatbuffers::FlatBufferBuilder* builder = BuilderInstance(); + constexpr size_t buffers_size = 1; + const Offset buffers[buffers_size] = { + CreateBuffer(*builder), + }; + const flatbuffers::Offset>> + buffers_offset = builder->CreateVector(buffers, buffers_size); + builder->Finish(buffers_offset); + void* buffers_pointer = builder->GetBufferPointer(); + const flatbuffers::Vector>* result = + flatbuffers::GetRoot>>( + buffers_pointer); + return result; +} + +int TestStrcmp(const char* a, const char* b) { + if ((a == nullptr) || (b == nullptr)) { + return -1; + } + while ((*a != 0) && (*a == *b)) { + a++; + b++; + } + return *reinterpret_cast(a) - + *reinterpret_cast(b); +} + +// Create a TfLiteIntArray from an array of ints. The first element in the +// supplied array must be the size of the array expressed as an int. +TfLiteIntArray* IntArrayFromInts(int* int_array) { + return reinterpret_cast(int_array); +} + +// Create a TfLiteFloatArray from an array of floats. The first element in the +// supplied array must be the size of the array expressed as a float. +TfLiteFloatArray* FloatArrayFromFloats(const float* floats) { + static_assert(sizeof(float) == sizeof(int), + "assumes sizeof(float) == sizeof(int) to perform casting"); + int size = static_cast(floats[0]); + *reinterpret_cast(const_cast(floats)) = size; + return reinterpret_cast(const_cast(floats)); +} + +TfLiteTensor CreateQuantizedBiasTensor(const float* data, int16_t* quantized, + TfLiteIntArray* dims, float input_scale, + float weights_scale, bool is_variable) { + float bias_scale = input_scale * weights_scale; + tflite::SymmetricQuantize(data, quantized, ElementCount(*dims), bias_scale); + + // Quantized int16_t tensors always have a zero point of 0, since the range of + // int16_t values is large, and because zero point costs extra cycles during + // processing. + TfLiteTensor result = + CreateQuantizedTensor(quantized, dims, bias_scale, 0, is_variable); + return result; +} + +TfLiteTensor CreateQuantizedBiasTensor(const float* data, int32_t* quantized, + TfLiteIntArray* dims, float input_scale, + float weights_scale, bool is_variable) { + float bias_scale = input_scale * weights_scale; + tflite::SymmetricQuantize(data, quantized, ElementCount(*dims), bias_scale); + + // Quantized int32_t tensors always have a zero point of 0, since the range of + // int32_t values is large, and because zero point costs extra cycles during + // processing. + TfLiteTensor result = + CreateQuantizedTensor(quantized, dims, bias_scale, 0, is_variable); + return result; +} + +TfLiteTensor CreateQuantizedBiasTensor(const float* data, + std::int64_t* quantized, + TfLiteIntArray* dims, float input_scale, + float weights_scale, bool is_variable) { + float bias_scale = input_scale * weights_scale; + tflite::SymmetricQuantize(data, quantized, ElementCount(*dims), bias_scale); + + // Quantized int32_t tensors always have a zero point of 0, since the range of + // int32_t values is large, and because zero point costs extra cycles during + // processing. + TfLiteTensor result = + CreateQuantizedTensor(quantized, dims, bias_scale, 0, is_variable); + return result; +} + +// Quantizes int32_t bias tensor with per-channel weights determined by input +// scale multiplied by weight scale for each channel. +template +TfLiteTensor CreatePerChannelQuantizedBiasTensor( + const float* input, T* quantized, TfLiteIntArray* dims, float input_scale, + float* weight_scales, float* scales, int* zero_points, + TfLiteAffineQuantization* affine_quant, int quantized_dimension, + bool is_variable) { + int input_size = ElementCount(*dims); + int num_channels = dims->data[quantized_dimension]; + // First element is reserved for array length + zero_points[0] = num_channels; + scales[0] = static_cast(num_channels); + float* scales_array = &scales[1]; + for (int i = 0; i < num_channels; i++) { + scales_array[i] = input_scale * weight_scales[i]; + zero_points[i + 1] = 0; + } + + SymmetricPerChannelQuantize(input, quantized, input_size, num_channels, + scales_array); + + affine_quant->scale = FloatArrayFromFloats(scales); + affine_quant->zero_point = IntArrayFromInts(zero_points); + affine_quant->quantized_dimension = quantized_dimension; + + TfLiteTensor result = CreateTensor(quantized, dims, is_variable); + result.quantization = {kTfLiteAffineQuantization, affine_quant}; + return result; +} + +TfLiteTensor CreatePerChannelQuantizedBiasTensor( + const float* input, int32_t* quantized, TfLiteIntArray* dims, + float input_scale, float* weight_scales, float* scales, int* zero_points, + TfLiteAffineQuantization* affine_quant, int quantized_dimension, + bool is_variable) { + return CreatePerChannelQuantizedBiasTensor( + input, quantized, dims, input_scale, weight_scales, scales, zero_points, + affine_quant, quantized_dimension, is_variable); +} + +TfLiteTensor CreatePerChannelQuantizedBiasTensor( + const float* input, std::int64_t* quantized, TfLiteIntArray* dims, + float input_scale, float* weight_scales, float* scales, int* zero_points, + TfLiteAffineQuantization* affine_quant, int quantized_dimension, + bool is_variable) { + return CreatePerChannelQuantizedBiasTensor( + input, quantized, dims, input_scale, weight_scales, scales, zero_points, + affine_quant, quantized_dimension, is_variable); +} + +TfLiteTensor CreateSymmetricPerChannelQuantizedTensor( + const float* input, int8_t* quantized, TfLiteIntArray* dims, float* scales, + int* zero_points, TfLiteAffineQuantization* affine_quant, + int quantized_dimension, bool is_variable, TfLiteType tensor_weight_type) { + int channel_count = dims->data[quantized_dimension]; + + scales[0] = static_cast(channel_count); + zero_points[0] = channel_count; + + SignedSymmetricPerChannelQuantize(input, dims, quantized_dimension, quantized, + &scales[1], tensor_weight_type); + + for (int i = 0; i < channel_count; i++) { + zero_points[i + 1] = 0; + } + + affine_quant->scale = FloatArrayFromFloats(scales); + affine_quant->zero_point = IntArrayFromInts(zero_points); + affine_quant->quantized_dimension = quantized_dimension; + TfLiteTensor result = + CreateTensor(quantized, dims, is_variable, tensor_weight_type); + result.quantization = {kTfLiteAffineQuantization, affine_quant}; + return result; +} + +size_t GetModelTensorCount(const Model* model) { + auto* subgraphs = model->subgraphs(); + if (subgraphs) { + return (*subgraphs)[0]->tensors()->size(); + } + return 0; +} + +void PackInt4ValuesDenselyInPlace(uint8_t* src_buffer, int buffer_size) { + for (int i = 0; i < buffer_size; ++i) { + if (i % 2 == 0) { + src_buffer[i / 2] = src_buffer[i] & 0x0F; + } else { + src_buffer[i / 2] |= src_buffer[i] << 4; + } + } + // the rest of the buffer should be empty since half of it is packed with the + // values + memset(src_buffer + (buffer_size + 1) / 2, 0, buffer_size / 2); +} + +} // namespace testing +} // namespace tflite diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h new file mode 100644 index 0000000..544181d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/micro/test_helpers.h @@ -0,0 +1,319 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_TEST_HELPERS_H_ +#define TENSORFLOW_LITE_MICRO_TEST_HELPERS_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" // from @flatbuffers +#include "edge-impulse-sdk/tensorflow/lite/c/common.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/compatibility.h" +#include "edge-impulse-sdk/tensorflow/lite/kernels/internal/tensor_ctypes.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_utils.h" +#include "edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { +namespace testing { + +constexpr int kOfflinePlannerHeaderSize = 3; + +struct NodeConnection_ { + std::initializer_list input; + std::initializer_list output; +}; +typedef struct NodeConnection_ NodeConnection; + +// A simple operator that returns the median of the input with the number of +// times the kernel was invoked. The implementation below is deliberately +// complicated, just to demonstrate how kernel memory planning works. +class SimpleStatefulOp { + static constexpr int kBufferNotAllocated = 0; + // Inputs: + static constexpr int kInputTensor = 0; + // Outputs: + static constexpr int kMedianTensor = 0; + static constexpr int kInvokeCount = 1; + struct OpData { + int* invoke_count = nullptr; + int sorting_buffer = kBufferNotAllocated; + }; + + public: + static const TfLiteRegistration* getRegistration(); + static TfLiteRegistration* GetMutableRegistration(); + static void* Init(TfLiteContext* context, const char* buffer, size_t length); + static TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node); + static TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node); +}; + +class MockCustom { + public: + static const TfLiteRegistration* getRegistration(); + static TfLiteRegistration* GetMutableRegistration(); + static void* Init(TfLiteContext* context, const char* buffer, size_t length); + static void Free(TfLiteContext* context, void* buffer); + static TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node); + static TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node); + + static bool freed_; +}; + +// A simple operator with the purpose of testing multiple inputs. It returns +// the sum of the inputs. +class MultipleInputs { + public: + static const TfLiteRegistration* getRegistration(); + static TfLiteRegistration* GetMutableRegistration(); + static void* Init(TfLiteContext* context, const char* buffer, size_t length); + static void Free(TfLiteContext* context, void* buffer); + static TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node); + static TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node); + + static bool freed_; +}; + +// A simple no-op operator. +class NoOp { + public: + static const TfLiteRegistration* getRegistration(); + static TfLiteRegistration* GetMutableRegistration(); + static void* Init(TfLiteContext* context, const char* buffer, size_t length); + static void Free(TfLiteContext* context, void* buffer); + static TfLiteStatus Prepare(TfLiteContext* context, TfLiteNode* node); + static TfLiteStatus Invoke(TfLiteContext* context, TfLiteNode* node); + + static bool freed_; +}; + +// Returns an Op Resolver that can be used in the testing code. +AllOpsResolver GetOpResolver(); + +// Returns a simple example flatbuffer TensorFlow Lite model. Contains 1 input, +// 1 layer of weights, 1 output Tensor, and 1 operator. +const Model* GetSimpleMockModel(); + +// Returns a flatbuffer TensorFlow Lite model with more inputs, variable +// tensors, and operators. +const Model* GetComplexMockModel(); + +// Returns a simple example flatbuffer TensorFlow Lite model. Contains 1 input, +// 1 layer of weights, 1 output Tensor, and 1 operator. +// The size of all three tensors is 256 x 256, which is larger than what other +// models provide from this test helper. +const Model* GetModelWith256x256Tensor(); + +// Returns a simple flatbuffer model with two branches. +const Model* GetSimpleModelWithBranch(); + +// Returns a simple example flatbuffer TensorFlow Lite model. Contains 3 inputs, +// 1 output Tensor, and 1 operator. +const Model* GetSimpleMultipleInputsModel(); + +// Returns a simple flatbuffer model with offline planned tensors +// @param[in] num_tensors Number of tensors in the model. +// @param[in] metadata_buffer Metadata for offline planner. +// @param[in] node_con List of connections, i.e. operators +// in the model. +// @param[in] num_conns Number of connections. +// @param[in] num_subgraph_inputs How many of the input tensors are in +// the subgraph inputs. The default value +// of 0 means all of the input tensors +// are in the subgraph input list. There +// must be at least 1 input tensor in the +// subgraph input list. +const Model* GetModelWithOfflinePlanning(int num_tensors, + const int32_t* metadata_buffer, + NodeConnection* node_conn, + int num_conns, + int num_subgraph_inputs = 0); + +// Returns a flatbuffer with a single operator, two inputs (one unused) and one +// output. +const Model* GetModelWithUnusedInputs(); + +// Returns a flatbuffer with a single operator, zero inputs and two outputs +// (one unused). +const Model* GetModelWithUnusedOperatorOutputs(); + +// Returns a flatbuffer model with `simple_stateful_op` +const Model* GetSimpleStatefulModel(); + +// Returns a flatbuffer model with "if" and two subgraphs. +const Model* GetSimpleModelWithSubgraphsAndIf(); + +// Returns a flatbuffer model with "if" and two subgraphs one of which is empty. +const Model* GetSimpleModelWithIfAndEmptySubgraph(); + +// Returns a flatbuffer model with "while" and three subgraphs. +const Model* GetSimpleModelWithSubgraphsAndWhile(); + +// Returns a flatbuffer model with "if" and two subgraphs and the input tensor 1 +// of "if" subgraph overlaps with the input tensor 2 of subgraph 1. +const Model* GetModelWithIfAndSubgraphInputTensorOverlap(); + +// Returns a flatbuffer model with null subgraph/operator inputs and outputs. +const Model* GetSimpleModelWithNullInputsAndOutputs(); + +// Builds a one-dimensional flatbuffer tensor of the given size. +const Tensor* Create1dFlatbufferTensor(int size, bool is_variable = false); + +// Builds a one-dimensional flatbuffer tensor of the given size with +// quantization metadata. +const Tensor* CreateQuantizedFlatbufferTensor(int size); + +// Creates a one-dimensional tensor with no quantization metadata. +const Tensor* CreateMissingQuantizationFlatbufferTensor(int size); + +// Creates a vector of flatbuffer buffers. +const flatbuffers::Vector>* +CreateFlatbufferBuffers(); + +// Performs a simple string comparison without requiring standard C library. +int TestStrcmp(const char* a, const char* b); + +void PopulateContext(TfLiteTensor* tensors, int tensors_size, + TfLiteContext* context); + +// Create a TfLiteIntArray from an array of ints. The first element in the +// supplied array must be the size of the array expressed as an int. +TfLiteIntArray* IntArrayFromInts(int* int_array); + +// Create a TfLiteFloatArray from an array of floats. The first element in the +// supplied array must be the size of the array expressed as a float. +TfLiteFloatArray* FloatArrayFromFloats(const float* floats); + +// Assumes that `src_tensor` is a buffer where each element is a 4-bit value +// stored in 8-bit. +// Returns a new buffer that is packed densely with 2 4-bit values in a byte. +// The packing format is low-bits-first, i.e. the lower nibble of a byte is +// filled first, followed by the upper nibble. +void PackInt4ValuesDenselyInPlace(uint8_t* src_buffer, int buffer_size); + +template +TfLiteTensor CreateTensor(const T* data, TfLiteIntArray* dims, + const bool is_variable = false, + TfLiteType type = kTfLiteNoType) { + TfLiteTensor result; + result.dims = dims; + result.params = {}; + result.quantization = {kTfLiteNoQuantization, nullptr}; + result.is_variable = is_variable; + result.allocation_type = kTfLiteMemNone; + result.data.data = const_cast(data); + result.quantization = {kTfLiteAffineQuantization, nullptr}; + result.bytes = ElementCount(*dims) * sizeof(T); + result.data.data = const_cast(data); + + if (type == kTfLiteInt4) { + result.type = kTfLiteInt4; + PackInt4ValuesDenselyInPlace(tflite::GetTensorData(&result), + ElementCount(*dims)); + result.bytes = ((ElementCount(*dims) + 1) / 2); + } else { + // Const cast is used to allow passing in const and non-const arrays within + // a single CreateTensor method. A Const array should be used for immutable + // input tensors and non-const array should be used for mutable and output + // tensors. + result.type = typeToTfLiteType(); + } + return result; +} + +template +TfLiteTensor CreateQuantizedTensor(const T* data, TfLiteIntArray* dims, + const float scale, const int zero_point = 0, + const bool is_variable = false, + TfLiteType type = kTfLiteNoType) { + TfLiteTensor result = CreateTensor(data, dims, is_variable, type); + result.params = {scale, zero_point}; + result.quantization = {kTfLiteAffineQuantization, nullptr}; + return result; +} + +template +TfLiteTensor CreateQuantizedTensor(const float* input, T* quantized, + TfLiteIntArray* dims, float scale, + int zero_point, bool is_variable = false, + TfLiteType type = kTfLiteNoType) { + int input_size = ElementCount(*dims); + tflite::Quantize(input, quantized, input_size, scale, zero_point); + return CreateQuantizedTensor(quantized, dims, scale, zero_point, is_variable, + type); +} + +TfLiteTensor CreateQuantizedBiasTensor(const float* data, int16_t* quantized, + TfLiteIntArray* dims, float input_scale, + float weights_scale, + bool is_variable = false); + +TfLiteTensor CreateQuantizedBiasTensor(const float* data, int32_t* quantized, + TfLiteIntArray* dims, float input_scale, + float weights_scale, + bool is_variable = false); + +TfLiteTensor CreateQuantizedBiasTensor(const float* data, + std::int64_t* quantized, + TfLiteIntArray* dims, float input_scale, + float weights_scale, + bool is_variable = false); + +// Quantizes int32_t bias tensor with per-channel weights determined by input +// scale multiplied by weight scale for each channel. +TfLiteTensor CreatePerChannelQuantizedBiasTensor( + const float* input, int32_t* quantized, TfLiteIntArray* dims, + float input_scale, float* weight_scales, float* scales, int* zero_points, + TfLiteAffineQuantization* affine_quant, int quantized_dimension, + bool is_variable = false); + +// Quantizes int64_t bias tensor with per-channel weights determined by input +// scale multiplied by weight scale for each channel. +TfLiteTensor CreatePerChannelQuantizedBiasTensor( + const float* input, std::int64_t* quantized, TfLiteIntArray* dims, + float input_scale, float* weight_scales, float* scales, int* zero_points, + TfLiteAffineQuantization* affine_quant, int quantized_dimension, + bool is_variable = false); + +TfLiteTensor CreateSymmetricPerChannelQuantizedTensor( + const float* input, int8_t* quantized, TfLiteIntArray* dims, float* scales, + int* zero_points, TfLiteAffineQuantization* affine_quant, + int quantized_dimension, bool is_variable = false, + TfLiteType tensor_weight_type = kTfLiteNoType); + +// Returns the number of tensors in the default subgraph for a tflite::Model. +size_t GetModelTensorCount(const Model* model); + +// Derives the quantization scaling factor from a min and max range. +template +inline float ScaleFromMinMax(const float min, const float max) { + return (max - min) / + static_cast((std::numeric_limits::max() * 1.0) - + std::numeric_limits::min()); +} + +// Derives the quantization zero point from a min and max range. +template +inline int ZeroPointFromMinMax(const float min, const float max) { + return static_cast(std::numeric_limits::min()) + + static_cast(-min / ScaleFromMinMax(min, max) + 0.5f); +} + +} // namespace testing +} // namespace tflite + +#endif // TENSORFLOW_LITE_MICRO_TEST_HELPERS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h new file mode 100644 index 0000000..28d2bf8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/portable_type_to_tflitetype.h @@ -0,0 +1,75 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_PORTABLE_TYPE_TO_TFLITETYPE_H_ +#define TENSORFLOW_LITE_PORTABLE_TYPE_TO_TFLITETYPE_H_ + +// Most of the definitions have been moved to this subheader so that Micro +// can include it without relying on and , which isn't +// available on all platforms. + +// Arduino build defines abs as a macro here. That is invalid C++, and breaks +// libc++'s header, undefine it. +#ifdef abs +#undef abs +#endif + +#include + +#include "edge-impulse-sdk/tensorflow/lite/core/c/common.h" + +namespace tflite { + +// Map statically from a C++ type to a TfLiteType. Used in interpreter for +// safe casts. +// Example: +// typeToTfLiteType() -> kTfLiteBool +template +constexpr TfLiteType typeToTfLiteType() { + return kTfLiteNoType; +} +// Map from TfLiteType to the corresponding C++ type. +// Example: +// TfLiteTypeToType::Type -> bool +template +struct TfLiteTypeToType {}; // Specializations below + +// Template specialization for both typeToTfLiteType and TfLiteTypeToType. +#define MATCH_TYPE_AND_TFLITE_TYPE(CPP_TYPE, TFLITE_TYPE_ENUM) \ + template <> \ + constexpr TfLiteType typeToTfLiteType() { \ + return TFLITE_TYPE_ENUM; \ + } \ + template <> \ + struct TfLiteTypeToType { \ + using Type = CPP_TYPE; \ + } + +// No string mapping is included here, since the TF Lite packed representation +// doesn't correspond to a C++ type well. +MATCH_TYPE_AND_TFLITE_TYPE(int32_t, kTfLiteInt32); +MATCH_TYPE_AND_TFLITE_TYPE(uint32_t, kTfLiteUInt32); +MATCH_TYPE_AND_TFLITE_TYPE(int16_t, kTfLiteInt16); +MATCH_TYPE_AND_TFLITE_TYPE(uint16_t, kTfLiteUInt16); +MATCH_TYPE_AND_TFLITE_TYPE(int64_t, kTfLiteInt64); +MATCH_TYPE_AND_TFLITE_TYPE(float, kTfLiteFloat32); +MATCH_TYPE_AND_TFLITE_TYPE(unsigned char, kTfLiteUInt8); +MATCH_TYPE_AND_TFLITE_TYPE(int8_t, kTfLiteInt8); +MATCH_TYPE_AND_TFLITE_TYPE(bool, kTfLiteBool); +MATCH_TYPE_AND_TFLITE_TYPE(TfLiteFloat16, kTfLiteFloat16); +MATCH_TYPE_AND_TFLITE_TYPE(double, kTfLiteFloat64); +MATCH_TYPE_AND_TFLITE_TYPE(uint64_t, kTfLiteUInt64); + +} // namespace tflite +#endif // TENSORFLOW_LITE_PORTABLE_TYPE_TO_TFLITETYPE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h new file mode 100755 index 0000000..416029f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h @@ -0,0 +1,2587 @@ +#ifndef FLATBUFFERS_GENERATED_SCHEMA_SUPPL_TFLITE_H_ +#define FLATBUFFERS_GENERATED_SCHEMA_SUPPL_TFLITE_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" + +// Ensure the included flatbuffers.h is the same version as when this file was +// generated, otherwise it may not be compatible. +static_assert(FLATBUFFERS_VERSION_MAJOR == 2 && + FLATBUFFERS_VERSION_MINOR == 0 && + FLATBUFFERS_VERSION_REVISION == 6, + "Non-compatible flatbuffers version included"); + +namespace tflite { + +struct CustomQuantization; +struct CustomQuantizationBuilder; +struct CustomQuantizationT; + +struct QuantizationParameters; +struct QuantizationParametersBuilder; +struct QuantizationParametersT; + +struct Int32Vector; +struct Int32VectorBuilder; +struct Int32VectorT; + +struct Uint16Vector; +struct Uint16VectorBuilder; +struct Uint16VectorT; + +struct Uint8Vector; +struct Uint8VectorBuilder; +struct Uint8VectorT; + +struct DimensionMetadata; +struct DimensionMetadataBuilder; +struct DimensionMetadataT; + +struct SparsityParameters; +struct SparsityParametersBuilder; +struct SparsityParametersT; + +struct VariantSubType; +struct VariantSubTypeBuilder; +struct VariantSubTypeT; + +struct Tensor; +struct TensorBuilder; +struct TensorT; + +struct Conv2DOptions; +struct Conv2DOptionsBuilder; +struct Conv2DOptionsT; + +struct Conv3DOptions; +struct Conv3DOptionsBuilder; +struct Conv3DOptionsT; + +struct Pool2DOptions; +struct Pool2DOptionsBuilder; +struct Pool2DOptionsT; + +struct DepthwiseConv2DOptions; +struct DepthwiseConv2DOptionsBuilder; +struct DepthwiseConv2DOptionsT; + +struct ConcatEmbeddingsOptions; +struct ConcatEmbeddingsOptionsBuilder; +struct ConcatEmbeddingsOptionsT; + +struct LSHProjectionOptions; +struct LSHProjectionOptionsBuilder; +struct LSHProjectionOptionsT; + +struct SVDFOptions; +struct SVDFOptionsBuilder; +struct SVDFOptionsT; + +struct RNNOptions; +struct RNNOptionsBuilder; +struct RNNOptionsT; + +struct SequenceRNNOptions; +struct SequenceRNNOptionsBuilder; +struct SequenceRNNOptionsT; + +struct BidirectionalSequenceRNNOptions; +struct BidirectionalSequenceRNNOptionsBuilder; +struct BidirectionalSequenceRNNOptionsT; + +struct FullyConnectedOptions; +struct FullyConnectedOptionsBuilder; +struct FullyConnectedOptionsT; + +struct SoftmaxOptions; +struct SoftmaxOptionsBuilder; +struct SoftmaxOptionsT; + +struct ConcatenationOptions; +struct ConcatenationOptionsBuilder; +struct ConcatenationOptionsT; + +struct AddOptions; +struct AddOptionsBuilder; +struct AddOptionsT; + +struct MulOptions; +struct MulOptionsBuilder; +struct MulOptionsT; + +struct L2NormOptions; +struct L2NormOptionsBuilder; +struct L2NormOptionsT; + +struct LocalResponseNormalizationOptions; +struct LocalResponseNormalizationOptionsBuilder; +struct LocalResponseNormalizationOptionsT; + +struct LSTMOptions; +struct LSTMOptionsBuilder; +struct LSTMOptionsT; + +struct UnidirectionalSequenceLSTMOptions; +struct UnidirectionalSequenceLSTMOptionsBuilder; +struct UnidirectionalSequenceLSTMOptionsT; + +struct BidirectionalSequenceLSTMOptions; +struct BidirectionalSequenceLSTMOptionsBuilder; +struct BidirectionalSequenceLSTMOptionsT; + +struct ResizeBilinearOptions; +struct ResizeBilinearOptionsBuilder; +struct ResizeBilinearOptionsT; + +struct ResizeNearestNeighborOptions; +struct ResizeNearestNeighborOptionsBuilder; +struct ResizeNearestNeighborOptionsT; + +struct CallOptions; +struct CallOptionsBuilder; +struct CallOptionsT; + +struct PadOptions; +struct PadOptionsBuilder; +struct PadOptionsT; + +struct PadV2Options; +struct PadV2OptionsBuilder; +struct PadV2OptionsT; + +struct ReshapeOptions; +struct ReshapeOptionsBuilder; +struct ReshapeOptionsT; + +struct SpaceToBatchNDOptions; +struct SpaceToBatchNDOptionsBuilder; +struct SpaceToBatchNDOptionsT; + +struct BatchToSpaceNDOptions; +struct BatchToSpaceNDOptionsBuilder; +struct BatchToSpaceNDOptionsT; + +struct SkipGramOptions; +struct SkipGramOptionsBuilder; +struct SkipGramOptionsT; + +struct SpaceToDepthOptions; +struct SpaceToDepthOptionsBuilder; +struct SpaceToDepthOptionsT; + +struct DepthToSpaceOptions; +struct DepthToSpaceOptionsBuilder; +struct DepthToSpaceOptionsT; + +struct SubOptions; +struct SubOptionsBuilder; +struct SubOptionsT; + +struct DivOptions; +struct DivOptionsBuilder; +struct DivOptionsT; + +struct TopKV2Options; +struct TopKV2OptionsBuilder; +struct TopKV2OptionsT; + +struct EmbeddingLookupSparseOptions; +struct EmbeddingLookupSparseOptionsBuilder; +struct EmbeddingLookupSparseOptionsT; + +struct GatherOptions; +struct GatherOptionsBuilder; +struct GatherOptionsT; + +struct TransposeOptions; +struct TransposeOptionsBuilder; +struct TransposeOptionsT; + +struct ExpOptions; +struct ExpOptionsBuilder; +struct ExpOptionsT; + +struct CosOptions; +struct CosOptionsBuilder; +struct CosOptionsT; + +struct ReducerOptions; +struct ReducerOptionsBuilder; +struct ReducerOptionsT; + +struct SqueezeOptions; +struct SqueezeOptionsBuilder; +struct SqueezeOptionsT; + +struct SplitOptions; +struct SplitOptionsBuilder; +struct SplitOptionsT; + +struct SplitVOptions; +struct SplitVOptionsBuilder; +struct SplitVOptionsT; + +struct StridedSliceOptions; +struct StridedSliceOptionsBuilder; +struct StridedSliceOptionsT; + +struct LogSoftmaxOptions; +struct LogSoftmaxOptionsBuilder; +struct LogSoftmaxOptionsT; + +struct CastOptions; +struct CastOptionsBuilder; +struct CastOptionsT; + +struct DequantizeOptions; +struct DequantizeOptionsBuilder; +struct DequantizeOptionsT; + +struct MaximumMinimumOptions; +struct MaximumMinimumOptionsBuilder; +struct MaximumMinimumOptionsT; + +struct TileOptions; +struct TileOptionsBuilder; +struct TileOptionsT; + +struct ArgMaxOptions; +struct ArgMaxOptionsBuilder; +struct ArgMaxOptionsT; + +struct ArgMinOptions; +struct ArgMinOptionsBuilder; +struct ArgMinOptionsT; + +struct GreaterOptions; +struct GreaterOptionsBuilder; +struct GreaterOptionsT; + +struct GreaterEqualOptions; +struct GreaterEqualOptionsBuilder; +struct GreaterEqualOptionsT; + +struct LessOptions; +struct LessOptionsBuilder; +struct LessOptionsT; + +struct LessEqualOptions; +struct LessEqualOptionsBuilder; +struct LessEqualOptionsT; + +struct NegOptions; +struct NegOptionsBuilder; +struct NegOptionsT; + +struct SelectOptions; +struct SelectOptionsBuilder; +struct SelectOptionsT; + +struct SliceOptions; +struct SliceOptionsBuilder; +struct SliceOptionsT; + +struct TransposeConvOptions; +struct TransposeConvOptionsBuilder; +struct TransposeConvOptionsT; + +struct ExpandDimsOptions; +struct ExpandDimsOptionsBuilder; +struct ExpandDimsOptionsT; + +struct SparseToDenseOptions; +struct SparseToDenseOptionsBuilder; +struct SparseToDenseOptionsT; + +struct EqualOptions; +struct EqualOptionsBuilder; +struct EqualOptionsT; + +struct NotEqualOptions; +struct NotEqualOptionsBuilder; +struct NotEqualOptionsT; + +struct ShapeOptions; +struct ShapeOptionsBuilder; +struct ShapeOptionsT; + +struct RankOptions; +struct RankOptionsBuilder; +struct RankOptionsT; + +struct PowOptions; +struct PowOptionsBuilder; +struct PowOptionsT; + +struct FakeQuantOptions; +struct FakeQuantOptionsBuilder; +struct FakeQuantOptionsT; + +struct PackOptions; +struct PackOptionsBuilder; +struct PackOptionsT; + +struct LogicalOrOptions; +struct LogicalOrOptionsBuilder; +struct LogicalOrOptionsT; + +struct OneHotOptions; +struct OneHotOptionsBuilder; +struct OneHotOptionsT; + +struct AbsOptions; +struct AbsOptionsBuilder; +struct AbsOptionsT; + +struct HardSwishOptions; +struct HardSwishOptionsBuilder; +struct HardSwishOptionsT; + +struct LogicalAndOptions; +struct LogicalAndOptionsBuilder; +struct LogicalAndOptionsT; + +struct LogicalNotOptions; +struct LogicalNotOptionsBuilder; +struct LogicalNotOptionsT; + +struct UnpackOptions; +struct UnpackOptionsBuilder; +struct UnpackOptionsT; + +struct FloorDivOptions; +struct FloorDivOptionsBuilder; +struct FloorDivOptionsT; + +struct SquareOptions; +struct SquareOptionsBuilder; +struct SquareOptionsT; + +struct ZerosLikeOptions; +struct ZerosLikeOptionsBuilder; +struct ZerosLikeOptionsT; + +struct FillOptions; +struct FillOptionsBuilder; +struct FillOptionsT; + +struct FloorModOptions; +struct FloorModOptionsBuilder; +struct FloorModOptionsT; + +struct RangeOptions; +struct RangeOptionsBuilder; +struct RangeOptionsT; + +struct LeakyReluOptions; +struct LeakyReluOptionsBuilder; +struct LeakyReluOptionsT; + +struct SquaredDifferenceOptions; +struct SquaredDifferenceOptionsBuilder; +struct SquaredDifferenceOptionsT; + +struct MirrorPadOptions; +struct MirrorPadOptionsBuilder; +struct MirrorPadOptionsT; + +struct UniqueOptions; +struct UniqueOptionsBuilder; +struct UniqueOptionsT; + +struct ReverseV2Options; +struct ReverseV2OptionsBuilder; +struct ReverseV2OptionsT; + +struct AddNOptions; +struct AddNOptionsBuilder; +struct AddNOptionsT; + +struct GatherNdOptions; +struct GatherNdOptionsBuilder; +struct GatherNdOptionsT; + +struct WhereOptions; +struct WhereOptionsBuilder; +struct WhereOptionsT; + +struct ReverseSequenceOptions; +struct ReverseSequenceOptionsBuilder; +struct ReverseSequenceOptionsT; + +struct MatrixDiagOptions; +struct MatrixDiagOptionsBuilder; +struct MatrixDiagOptionsT; + +struct QuantizeOptions; +struct QuantizeOptionsBuilder; +struct QuantizeOptionsT; + +struct MatrixSetDiagOptions; +struct MatrixSetDiagOptionsBuilder; +struct MatrixSetDiagOptionsT; + +struct IfOptions; +struct IfOptionsBuilder; +struct IfOptionsT; + +struct CallOnceOptions; +struct CallOnceOptionsBuilder; +struct CallOnceOptionsT; + +struct WhileOptions; +struct WhileOptionsBuilder; +struct WhileOptionsT; + +struct NonMaxSuppressionV4Options; +struct NonMaxSuppressionV4OptionsBuilder; +struct NonMaxSuppressionV4OptionsT; + +struct NonMaxSuppressionV5Options; +struct NonMaxSuppressionV5OptionsBuilder; +struct NonMaxSuppressionV5OptionsT; + +struct ScatterNdOptions; +struct ScatterNdOptionsBuilder; +struct ScatterNdOptionsT; + +struct SelectV2Options; +struct SelectV2OptionsBuilder; +struct SelectV2OptionsT; + +struct DensifyOptions; +struct DensifyOptionsBuilder; +struct DensifyOptionsT; + +struct SegmentSumOptions; +struct SegmentSumOptionsBuilder; +struct SegmentSumOptionsT; + +struct BatchMatMulOptions; +struct BatchMatMulOptionsBuilder; +struct BatchMatMulOptionsT; + +struct CumsumOptions; +struct CumsumOptionsBuilder; +struct CumsumOptionsT; + +struct BroadcastToOptions; +struct BroadcastToOptionsBuilder; +struct BroadcastToOptionsT; + +struct Rfft2dOptions; +struct Rfft2dOptionsBuilder; +struct Rfft2dOptionsT; + +struct HashtableOptions; +struct HashtableOptionsBuilder; +struct HashtableOptionsT; + +struct HashtableFindOptions; +struct HashtableFindOptionsBuilder; +struct HashtableFindOptionsT; + +struct HashtableImportOptions; +struct HashtableImportOptionsBuilder; +struct HashtableImportOptionsT; + +struct HashtableSizeOptions; +struct HashtableSizeOptionsBuilder; +struct HashtableSizeOptionsT; + +struct VarHandleOptions; +struct VarHandleOptionsBuilder; +struct VarHandleOptionsT; + +struct ReadVariableOptions; +struct ReadVariableOptionsBuilder; +struct ReadVariableOptionsT; + +struct AssignVariableOptions; +struct AssignVariableOptionsBuilder; +struct AssignVariableOptionsT; + +struct RandomOptions; +struct RandomOptionsBuilder; +struct RandomOptionsT; + +struct BucketizeOptions; +struct BucketizeOptionsBuilder; +struct BucketizeOptionsT; + +struct GeluOptions; +struct GeluOptionsBuilder; +struct GeluOptionsT; + +struct DynamicUpdateSliceOptions; +struct DynamicUpdateSliceOptionsBuilder; +struct DynamicUpdateSliceOptionsT; + +struct UnsortedSegmentProdOptions; +struct UnsortedSegmentProdOptionsBuilder; +struct UnsortedSegmentProdOptionsT; + +struct UnsortedSegmentMaxOptions; +struct UnsortedSegmentMaxOptionsBuilder; +struct UnsortedSegmentMaxOptionsT; + +struct UnsortedSegmentSumOptions; +struct UnsortedSegmentSumOptionsBuilder; +struct UnsortedSegmentSumOptionsT; + +struct ATan2Options; +struct ATan2OptionsBuilder; +struct ATan2OptionsT; + +struct UnsortedSegmentMinOptions; +struct UnsortedSegmentMinOptionsBuilder; +struct UnsortedSegmentMinOptionsT; + +struct SignOptions; +struct SignOptionsBuilder; +struct SignOptionsT; + +struct OperatorCode; +struct OperatorCodeBuilder; +struct OperatorCodeT; + +struct Operator; +struct OperatorBuilder; +struct OperatorT; + +struct SubGraph; +struct SubGraphBuilder; +struct SubGraphT; + +struct Buffer; +struct BufferBuilder; +struct BufferT; + +struct Metadata; +struct MetadataBuilder; +struct MetadataT; + +struct TensorMap; +struct TensorMapBuilder; +struct TensorMapT; + +struct SignatureDef; +struct SignatureDefBuilder; +struct SignatureDefT; + +struct Model; +struct ModelBuilder; +struct ModelT; + +enum TensorType : int8_t { + TensorType_FLOAT32 = 0, + TensorType_FLOAT16 = 1, + TensorType_INT32 = 2, + TensorType_UINT8 = 3, + TensorType_INT64 = 4, + TensorType_STRING = 5, + TensorType_BOOL = 6, + TensorType_INT16 = 7, + TensorType_COMPLEX64 = 8, + TensorType_INT8 = 9, + TensorType_FLOAT64 = 10, + TensorType_COMPLEX128 = 11, + TensorType_UINT64 = 12, + TensorType_RESOURCE = 13, + TensorType_VARIANT = 14, + TensorType_UINT32 = 15, + TensorType_UINT16 = 16, + TensorType_INT4 = 17, + TensorType_MIN = TensorType_FLOAT32, + TensorType_MAX = TensorType_INT4 +}; + +inline const TensorType (&EnumValuesTensorType())[18] { + static const TensorType values[] = { + TensorType_FLOAT32, + TensorType_FLOAT16, + TensorType_INT32, + TensorType_UINT8, + TensorType_INT64, + TensorType_STRING, + TensorType_BOOL, + TensorType_INT16, + TensorType_COMPLEX64, + TensorType_INT8, + TensorType_FLOAT64, + TensorType_COMPLEX128, + TensorType_UINT64, + TensorType_RESOURCE, + TensorType_VARIANT, + TensorType_UINT32, + TensorType_UINT16, + TensorType_INT4 + }; + return values; +} + +inline const char * const *EnumNamesTensorType() { + static const char * const names[19] = { + "FLOAT32", + "FLOAT16", + "INT32", + "UINT8", + "INT64", + "STRING", + "BOOL", + "INT16", + "COMPLEX64", + "INT8", + "FLOAT64", + "COMPLEX128", + "UINT64", + "RESOURCE", + "VARIANT", + "UINT32", + "UINT16", + "INT4", + nullptr + }; + return names; +} + +inline const char *EnumNameTensorType(TensorType e) { + if (flatbuffers::IsOutRange(e, TensorType_FLOAT32, TensorType_INT4)) return ""; + const size_t index = static_cast(e); + return EnumNamesTensorType()[index]; +} + + +enum BuiltinOperator : int32_t { + BuiltinOperator_ADD = 0, + BuiltinOperator_AVERAGE_POOL_2D = 1, + BuiltinOperator_CONCATENATION = 2, + BuiltinOperator_CONV_2D = 3, + BuiltinOperator_DEPTHWISE_CONV_2D = 4, + BuiltinOperator_DEPTH_TO_SPACE = 5, + BuiltinOperator_DEQUANTIZE = 6, + BuiltinOperator_EMBEDDING_LOOKUP = 7, + BuiltinOperator_FLOOR = 8, + BuiltinOperator_FULLY_CONNECTED = 9, + BuiltinOperator_HASHTABLE_LOOKUP = 10, + BuiltinOperator_L2_NORMALIZATION = 11, + BuiltinOperator_L2_POOL_2D = 12, + BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION = 13, + BuiltinOperator_LOGISTIC = 14, + BuiltinOperator_LSH_PROJECTION = 15, + BuiltinOperator_LSTM = 16, + BuiltinOperator_MAX_POOL_2D = 17, + BuiltinOperator_MUL = 18, + BuiltinOperator_RELU = 19, + BuiltinOperator_RELU_N1_TO_1 = 20, + BuiltinOperator_RELU6 = 21, + BuiltinOperator_RESHAPE = 22, + BuiltinOperator_RESIZE_BILINEAR = 23, + BuiltinOperator_RNN = 24, + BuiltinOperator_SOFTMAX = 25, + BuiltinOperator_SPACE_TO_DEPTH = 26, + BuiltinOperator_SVDF = 27, + BuiltinOperator_TANH = 28, + BuiltinOperator_CONCAT_EMBEDDINGS = 29, + BuiltinOperator_SKIP_GRAM = 30, + BuiltinOperator_CALL = 31, + BuiltinOperator_CUSTOM = 32, + BuiltinOperator_EMBEDDING_LOOKUP_SPARSE = 33, + BuiltinOperator_PAD = 34, + BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN = 35, + BuiltinOperator_GATHER = 36, + BuiltinOperator_BATCH_TO_SPACE_ND = 37, + BuiltinOperator_SPACE_TO_BATCH_ND = 38, + BuiltinOperator_TRANSPOSE = 39, + BuiltinOperator_MEAN = 40, + BuiltinOperator_SUB = 41, + BuiltinOperator_DIV = 42, + BuiltinOperator_SQUEEZE = 43, + BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM = 44, + BuiltinOperator_STRIDED_SLICE = 45, + BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN = 46, + BuiltinOperator_EXP = 47, + BuiltinOperator_TOPK_V2 = 48, + BuiltinOperator_SPLIT = 49, + BuiltinOperator_LOG_SOFTMAX = 50, + BuiltinOperator_DELEGATE = 51, + BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM = 52, + BuiltinOperator_CAST = 53, + BuiltinOperator_PRELU = 54, + BuiltinOperator_MAXIMUM = 55, + BuiltinOperator_ARG_MAX = 56, + BuiltinOperator_MINIMUM = 57, + BuiltinOperator_LESS = 58, + BuiltinOperator_NEG = 59, + BuiltinOperator_PADV2 = 60, + BuiltinOperator_GREATER = 61, + BuiltinOperator_GREATER_EQUAL = 62, + BuiltinOperator_LESS_EQUAL = 63, + BuiltinOperator_SELECT = 64, + BuiltinOperator_SLICE = 65, + BuiltinOperator_SIN = 66, + BuiltinOperator_TRANSPOSE_CONV = 67, + BuiltinOperator_SPARSE_TO_DENSE = 68, + BuiltinOperator_TILE = 69, + BuiltinOperator_EXPAND_DIMS = 70, + BuiltinOperator_EQUAL = 71, + BuiltinOperator_NOT_EQUAL = 72, + BuiltinOperator_LOG = 73, + BuiltinOperator_SUM = 74, + BuiltinOperator_SQRT = 75, + BuiltinOperator_RSQRT = 76, + BuiltinOperator_SHAPE = 77, + BuiltinOperator_POW = 78, + BuiltinOperator_ARG_MIN = 79, + BuiltinOperator_FAKE_QUANT = 80, + BuiltinOperator_REDUCE_PROD = 81, + BuiltinOperator_REDUCE_MAX = 82, + BuiltinOperator_PACK = 83, + BuiltinOperator_LOGICAL_OR = 84, + BuiltinOperator_ONE_HOT = 85, + BuiltinOperator_LOGICAL_AND = 86, + BuiltinOperator_LOGICAL_NOT = 87, + BuiltinOperator_UNPACK = 88, + BuiltinOperator_REDUCE_MIN = 89, + BuiltinOperator_FLOOR_DIV = 90, + BuiltinOperator_REDUCE_ANY = 91, + BuiltinOperator_SQUARE = 92, + BuiltinOperator_ZEROS_LIKE = 93, + BuiltinOperator_FILL = 94, + BuiltinOperator_FLOOR_MOD = 95, + BuiltinOperator_RANGE = 96, + BuiltinOperator_RESIZE_NEAREST_NEIGHBOR = 97, + BuiltinOperator_LEAKY_RELU = 98, + BuiltinOperator_SQUARED_DIFFERENCE = 99, + BuiltinOperator_MIRROR_PAD = 100, + BuiltinOperator_ABS = 101, + BuiltinOperator_SPLIT_V = 102, + BuiltinOperator_UNIQUE = 103, + BuiltinOperator_CEIL = 104, + BuiltinOperator_REVERSE_V2 = 105, + BuiltinOperator_ADD_N = 106, + BuiltinOperator_GATHER_ND = 107, + BuiltinOperator_COS = 108, + BuiltinOperator_WHERE = 109, + BuiltinOperator_RANK = 110, + BuiltinOperator_ELU = 111, + BuiltinOperator_REVERSE_SEQUENCE = 112, + BuiltinOperator_MATRIX_DIAG = 113, + BuiltinOperator_QUANTIZE = 114, + BuiltinOperator_MATRIX_SET_DIAG = 115, + BuiltinOperator_ROUND = 116, + BuiltinOperator_HARD_SWISH = 117, + BuiltinOperator_IF = 118, + BuiltinOperator_WHILE = 119, + BuiltinOperator_NON_MAX_SUPPRESSION_V4 = 120, + BuiltinOperator_NON_MAX_SUPPRESSION_V5 = 121, + BuiltinOperator_SCATTER_ND = 122, + BuiltinOperator_SELECT_V2 = 123, + BuiltinOperator_DENSIFY = 124, + BuiltinOperator_SEGMENT_SUM = 125, + BuiltinOperator_BATCH_MATMUL = 126, + BuiltinOperator_PLACEHOLDER_FOR_GREATER_OP_CODES = 127, + BuiltinOperator_CUMSUM = 128, + BuiltinOperator_CALL_ONCE = 129, + BuiltinOperator_BROADCAST_TO = 130, + BuiltinOperator_RFFT2D = 131, + BuiltinOperator_CONV_3D = 132, + BuiltinOperator_IMAG = 133, + BuiltinOperator_REAL = 134, + BuiltinOperator_COMPLEX_ABS = 135, + BuiltinOperator_HASHTABLE = 136, + BuiltinOperator_HASHTABLE_FIND = 137, + BuiltinOperator_HASHTABLE_IMPORT = 138, + BuiltinOperator_HASHTABLE_SIZE = 139, + BuiltinOperator_REDUCE_ALL = 140, + BuiltinOperator_CONV_3D_TRANSPOSE = 141, + BuiltinOperator_VAR_HANDLE = 142, + BuiltinOperator_READ_VARIABLE = 143, + BuiltinOperator_ASSIGN_VARIABLE = 144, + BuiltinOperator_BROADCAST_ARGS = 145, + BuiltinOperator_RANDOM_STANDARD_NORMAL = 146, + BuiltinOperator_BUCKETIZE = 147, + BuiltinOperator_RANDOM_UNIFORM = 148, + BuiltinOperator_MULTINOMIAL = 149, + BuiltinOperator_GELU = 150, + BuiltinOperator_DYNAMIC_UPDATE_SLICE = 151, + BuiltinOperator_RELU_0_TO_1 = 152, + BuiltinOperator_UNSORTED_SEGMENT_PROD = 153, + BuiltinOperator_UNSORTED_SEGMENT_MAX = 154, + BuiltinOperator_UNSORTED_SEGMENT_SUM = 155, + BuiltinOperator_ATAN2 = 156, + BuiltinOperator_UNSORTED_SEGMENT_MIN = 157, + BuiltinOperator_SIGN = 158, + BuiltinOperator_MIN = BuiltinOperator_ADD, + BuiltinOperator_MAX = BuiltinOperator_SIGN +}; + +inline const BuiltinOperator (&EnumValuesBuiltinOperator())[159] { + static const BuiltinOperator values[] = { + BuiltinOperator_ADD, + BuiltinOperator_AVERAGE_POOL_2D, + BuiltinOperator_CONCATENATION, + BuiltinOperator_CONV_2D, + BuiltinOperator_DEPTHWISE_CONV_2D, + BuiltinOperator_DEPTH_TO_SPACE, + BuiltinOperator_DEQUANTIZE, + BuiltinOperator_EMBEDDING_LOOKUP, + BuiltinOperator_FLOOR, + BuiltinOperator_FULLY_CONNECTED, + BuiltinOperator_HASHTABLE_LOOKUP, + BuiltinOperator_L2_NORMALIZATION, + BuiltinOperator_L2_POOL_2D, + BuiltinOperator_LOCAL_RESPONSE_NORMALIZATION, + BuiltinOperator_LOGISTIC, + BuiltinOperator_LSH_PROJECTION, + BuiltinOperator_LSTM, + BuiltinOperator_MAX_POOL_2D, + BuiltinOperator_MUL, + BuiltinOperator_RELU, + BuiltinOperator_RELU_N1_TO_1, + BuiltinOperator_RELU6, + BuiltinOperator_RESHAPE, + BuiltinOperator_RESIZE_BILINEAR, + BuiltinOperator_RNN, + BuiltinOperator_SOFTMAX, + BuiltinOperator_SPACE_TO_DEPTH, + BuiltinOperator_SVDF, + BuiltinOperator_TANH, + BuiltinOperator_CONCAT_EMBEDDINGS, + BuiltinOperator_SKIP_GRAM, + BuiltinOperator_CALL, + BuiltinOperator_CUSTOM, + BuiltinOperator_EMBEDDING_LOOKUP_SPARSE, + BuiltinOperator_PAD, + BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_RNN, + BuiltinOperator_GATHER, + BuiltinOperator_BATCH_TO_SPACE_ND, + BuiltinOperator_SPACE_TO_BATCH_ND, + BuiltinOperator_TRANSPOSE, + BuiltinOperator_MEAN, + BuiltinOperator_SUB, + BuiltinOperator_DIV, + BuiltinOperator_SQUEEZE, + BuiltinOperator_UNIDIRECTIONAL_SEQUENCE_LSTM, + BuiltinOperator_STRIDED_SLICE, + BuiltinOperator_BIDIRECTIONAL_SEQUENCE_RNN, + BuiltinOperator_EXP, + BuiltinOperator_TOPK_V2, + BuiltinOperator_SPLIT, + BuiltinOperator_LOG_SOFTMAX, + BuiltinOperator_DELEGATE, + BuiltinOperator_BIDIRECTIONAL_SEQUENCE_LSTM, + BuiltinOperator_CAST, + BuiltinOperator_PRELU, + BuiltinOperator_MAXIMUM, + BuiltinOperator_ARG_MAX, + BuiltinOperator_MINIMUM, + BuiltinOperator_LESS, + BuiltinOperator_NEG, + BuiltinOperator_PADV2, + BuiltinOperator_GREATER, + BuiltinOperator_GREATER_EQUAL, + BuiltinOperator_LESS_EQUAL, + BuiltinOperator_SELECT, + BuiltinOperator_SLICE, + BuiltinOperator_SIN, + BuiltinOperator_TRANSPOSE_CONV, + BuiltinOperator_SPARSE_TO_DENSE, + BuiltinOperator_TILE, + BuiltinOperator_EXPAND_DIMS, + BuiltinOperator_EQUAL, + BuiltinOperator_NOT_EQUAL, + BuiltinOperator_LOG, + BuiltinOperator_SUM, + BuiltinOperator_SQRT, + BuiltinOperator_RSQRT, + BuiltinOperator_SHAPE, + BuiltinOperator_POW, + BuiltinOperator_ARG_MIN, + BuiltinOperator_FAKE_QUANT, + BuiltinOperator_REDUCE_PROD, + BuiltinOperator_REDUCE_MAX, + BuiltinOperator_PACK, + BuiltinOperator_LOGICAL_OR, + BuiltinOperator_ONE_HOT, + BuiltinOperator_LOGICAL_AND, + BuiltinOperator_LOGICAL_NOT, + BuiltinOperator_UNPACK, + BuiltinOperator_REDUCE_MIN, + BuiltinOperator_FLOOR_DIV, + BuiltinOperator_REDUCE_ANY, + BuiltinOperator_SQUARE, + BuiltinOperator_ZEROS_LIKE, + BuiltinOperator_FILL, + BuiltinOperator_FLOOR_MOD, + BuiltinOperator_RANGE, + BuiltinOperator_RESIZE_NEAREST_NEIGHBOR, + BuiltinOperator_LEAKY_RELU, + BuiltinOperator_SQUARED_DIFFERENCE, + BuiltinOperator_MIRROR_PAD, + BuiltinOperator_ABS, + BuiltinOperator_SPLIT_V, + BuiltinOperator_UNIQUE, + BuiltinOperator_CEIL, + BuiltinOperator_REVERSE_V2, + BuiltinOperator_ADD_N, + BuiltinOperator_GATHER_ND, + BuiltinOperator_COS, + BuiltinOperator_WHERE, + BuiltinOperator_RANK, + BuiltinOperator_ELU, + BuiltinOperator_REVERSE_SEQUENCE, + BuiltinOperator_MATRIX_DIAG, + BuiltinOperator_QUANTIZE, + BuiltinOperator_MATRIX_SET_DIAG, + BuiltinOperator_ROUND, + BuiltinOperator_HARD_SWISH, + BuiltinOperator_IF, + BuiltinOperator_WHILE, + BuiltinOperator_NON_MAX_SUPPRESSION_V4, + BuiltinOperator_NON_MAX_SUPPRESSION_V5, + BuiltinOperator_SCATTER_ND, + BuiltinOperator_SELECT_V2, + BuiltinOperator_DENSIFY, + BuiltinOperator_SEGMENT_SUM, + BuiltinOperator_BATCH_MATMUL, + BuiltinOperator_PLACEHOLDER_FOR_GREATER_OP_CODES, + BuiltinOperator_CUMSUM, + BuiltinOperator_CALL_ONCE, + BuiltinOperator_BROADCAST_TO, + BuiltinOperator_RFFT2D, + BuiltinOperator_CONV_3D, + BuiltinOperator_IMAG, + BuiltinOperator_REAL, + BuiltinOperator_COMPLEX_ABS, + BuiltinOperator_HASHTABLE, + BuiltinOperator_HASHTABLE_FIND, + BuiltinOperator_HASHTABLE_IMPORT, + BuiltinOperator_HASHTABLE_SIZE, + BuiltinOperator_REDUCE_ALL, + BuiltinOperator_CONV_3D_TRANSPOSE, + BuiltinOperator_VAR_HANDLE, + BuiltinOperator_READ_VARIABLE, + BuiltinOperator_ASSIGN_VARIABLE, + BuiltinOperator_BROADCAST_ARGS, + BuiltinOperator_RANDOM_STANDARD_NORMAL, + BuiltinOperator_BUCKETIZE, + BuiltinOperator_RANDOM_UNIFORM, + BuiltinOperator_MULTINOMIAL, + BuiltinOperator_GELU, + BuiltinOperator_DYNAMIC_UPDATE_SLICE, + BuiltinOperator_RELU_0_TO_1, + BuiltinOperator_UNSORTED_SEGMENT_PROD, + BuiltinOperator_UNSORTED_SEGMENT_MAX, + BuiltinOperator_UNSORTED_SEGMENT_SUM, + BuiltinOperator_ATAN2, + BuiltinOperator_UNSORTED_SEGMENT_MIN, + BuiltinOperator_SIGN + }; + return values; +} + +inline const char * const *EnumNamesBuiltinOperator() { + static const char * const names[160] = { + "ADD", + "AVERAGE_POOL_2D", + "CONCATENATION", + "CONV_2D", + "DEPTHWISE_CONV_2D", + "DEPTH_TO_SPACE", + "DEQUANTIZE", + "EMBEDDING_LOOKUP", + "FLOOR", + "FULLY_CONNECTED", + "HASHTABLE_LOOKUP", + "L2_NORMALIZATION", + "L2_POOL_2D", + "LOCAL_RESPONSE_NORMALIZATION", + "LOGISTIC", + "LSH_PROJECTION", + "LSTM", + "MAX_POOL_2D", + "MUL", + "RELU", + "RELU_N1_TO_1", + "RELU6", + "RESHAPE", + "RESIZE_BILINEAR", + "RNN", + "SOFTMAX", + "SPACE_TO_DEPTH", + "SVDF", + "TANH", + "CONCAT_EMBEDDINGS", + "SKIP_GRAM", + "CALL", + "CUSTOM", + "EMBEDDING_LOOKUP_SPARSE", + "PAD", + "UNIDIRECTIONAL_SEQUENCE_RNN", + "GATHER", + "BATCH_TO_SPACE_ND", + "SPACE_TO_BATCH_ND", + "TRANSPOSE", + "MEAN", + "SUB", + "DIV", + "SQUEEZE", + "UNIDIRECTIONAL_SEQUENCE_LSTM", + "STRIDED_SLICE", + "BIDIRECTIONAL_SEQUENCE_RNN", + "EXP", + "TOPK_V2", + "SPLIT", + "LOG_SOFTMAX", + "DELEGATE", + "BIDIRECTIONAL_SEQUENCE_LSTM", + "CAST", + "PRELU", + "MAXIMUM", + "ARG_MAX", + "MINIMUM", + "LESS", + "NEG", + "PADV2", + "GREATER", + "GREATER_EQUAL", + "LESS_EQUAL", + "SELECT", + "SLICE", + "SIN", + "TRANSPOSE_CONV", + "SPARSE_TO_DENSE", + "TILE", + "EXPAND_DIMS", + "EQUAL", + "NOT_EQUAL", + "LOG", + "SUM", + "SQRT", + "RSQRT", + "SHAPE", + "POW", + "ARG_MIN", + "FAKE_QUANT", + "REDUCE_PROD", + "REDUCE_MAX", + "PACK", + "LOGICAL_OR", + "ONE_HOT", + "LOGICAL_AND", + "LOGICAL_NOT", + "UNPACK", + "REDUCE_MIN", + "FLOOR_DIV", + "REDUCE_ANY", + "SQUARE", + "ZEROS_LIKE", + "FILL", + "FLOOR_MOD", + "RANGE", + "RESIZE_NEAREST_NEIGHBOR", + "LEAKY_RELU", + "SQUARED_DIFFERENCE", + "MIRROR_PAD", + "ABS", + "SPLIT_V", + "UNIQUE", + "CEIL", + "REVERSE_V2", + "ADD_N", + "GATHER_ND", + "COS", + "WHERE", + "RANK", + "ELU", + "REVERSE_SEQUENCE", + "MATRIX_DIAG", + "QUANTIZE", + "MATRIX_SET_DIAG", + "ROUND", + "HARD_SWISH", + "IF", + "WHILE", + "NON_MAX_SUPPRESSION_V4", + "NON_MAX_SUPPRESSION_V5", + "SCATTER_ND", + "SELECT_V2", + "DENSIFY", + "SEGMENT_SUM", + "BATCH_MATMUL", + "PLACEHOLDER_FOR_GREATER_OP_CODES", + "CUMSUM", + "CALL_ONCE", + "BROADCAST_TO", + "RFFT2D", + "CONV_3D", + "IMAG", + "REAL", + "COMPLEX_ABS", + "HASHTABLE", + "HASHTABLE_FIND", + "HASHTABLE_IMPORT", + "HASHTABLE_SIZE", + "REDUCE_ALL", + "CONV_3D_TRANSPOSE", + "VAR_HANDLE", + "READ_VARIABLE", + "ASSIGN_VARIABLE", + "BROADCAST_ARGS", + "RANDOM_STANDARD_NORMAL", + "BUCKETIZE", + "RANDOM_UNIFORM", + "MULTINOMIAL", + "GELU", + "DYNAMIC_UPDATE_SLICE", + "RELU_0_TO_1", + "UNSORTED_SEGMENT_PROD", + "UNSORTED_SEGMENT_MAX", + "UNSORTED_SEGMENT_SUM", + "ATAN2", + "UNSORTED_SEGMENT_MIN", + "SIGN", + nullptr + }; + return names; +} + +inline const char *EnumNameBuiltinOperator(BuiltinOperator e) { + if (flatbuffers::IsOutRange(e, BuiltinOperator_ADD, BuiltinOperator_SIGN)) return ""; + const size_t index = static_cast(e); + return EnumNamesBuiltinOperator()[index]; +} + +enum BuiltinOptions : uint8_t { + BuiltinOptions_NONE = 0, + BuiltinOptions_Conv2DOptions = 1, + BuiltinOptions_DepthwiseConv2DOptions = 2, + BuiltinOptions_ConcatEmbeddingsOptions = 3, + BuiltinOptions_LSHProjectionOptions = 4, + BuiltinOptions_Pool2DOptions = 5, + BuiltinOptions_SVDFOptions = 6, + BuiltinOptions_RNNOptions = 7, + BuiltinOptions_FullyConnectedOptions = 8, + BuiltinOptions_SoftmaxOptions = 9, + BuiltinOptions_ConcatenationOptions = 10, + BuiltinOptions_AddOptions = 11, + BuiltinOptions_L2NormOptions = 12, + BuiltinOptions_LocalResponseNormalizationOptions = 13, + BuiltinOptions_LSTMOptions = 14, + BuiltinOptions_ResizeBilinearOptions = 15, + BuiltinOptions_CallOptions = 16, + BuiltinOptions_ReshapeOptions = 17, + BuiltinOptions_SkipGramOptions = 18, + BuiltinOptions_SpaceToDepthOptions = 19, + BuiltinOptions_EmbeddingLookupSparseOptions = 20, + BuiltinOptions_MulOptions = 21, + BuiltinOptions_PadOptions = 22, + BuiltinOptions_GatherOptions = 23, + BuiltinOptions_BatchToSpaceNDOptions = 24, + BuiltinOptions_SpaceToBatchNDOptions = 25, + BuiltinOptions_TransposeOptions = 26, + BuiltinOptions_ReducerOptions = 27, + BuiltinOptions_SubOptions = 28, + BuiltinOptions_DivOptions = 29, + BuiltinOptions_SqueezeOptions = 30, + BuiltinOptions_SequenceRNNOptions = 31, + BuiltinOptions_StridedSliceOptions = 32, + BuiltinOptions_ExpOptions = 33, + BuiltinOptions_TopKV2Options = 34, + BuiltinOptions_SplitOptions = 35, + BuiltinOptions_LogSoftmaxOptions = 36, + BuiltinOptions_CastOptions = 37, + BuiltinOptions_DequantizeOptions = 38, + BuiltinOptions_MaximumMinimumOptions = 39, + BuiltinOptions_ArgMaxOptions = 40, + BuiltinOptions_LessOptions = 41, + BuiltinOptions_NegOptions = 42, + BuiltinOptions_PadV2Options = 43, + BuiltinOptions_GreaterOptions = 44, + BuiltinOptions_GreaterEqualOptions = 45, + BuiltinOptions_LessEqualOptions = 46, + BuiltinOptions_SelectOptions = 47, + BuiltinOptions_SliceOptions = 48, + BuiltinOptions_TransposeConvOptions = 49, + BuiltinOptions_SparseToDenseOptions = 50, + BuiltinOptions_TileOptions = 51, + BuiltinOptions_ExpandDimsOptions = 52, + BuiltinOptions_EqualOptions = 53, + BuiltinOptions_NotEqualOptions = 54, + BuiltinOptions_ShapeOptions = 55, + BuiltinOptions_PowOptions = 56, + BuiltinOptions_ArgMinOptions = 57, + BuiltinOptions_FakeQuantOptions = 58, + BuiltinOptions_PackOptions = 59, + BuiltinOptions_LogicalOrOptions = 60, + BuiltinOptions_OneHotOptions = 61, + BuiltinOptions_LogicalAndOptions = 62, + BuiltinOptions_LogicalNotOptions = 63, + BuiltinOptions_UnpackOptions = 64, + BuiltinOptions_FloorDivOptions = 65, + BuiltinOptions_SquareOptions = 66, + BuiltinOptions_ZerosLikeOptions = 67, + BuiltinOptions_FillOptions = 68, + BuiltinOptions_BidirectionalSequenceLSTMOptions = 69, + BuiltinOptions_BidirectionalSequenceRNNOptions = 70, + BuiltinOptions_UnidirectionalSequenceLSTMOptions = 71, + BuiltinOptions_FloorModOptions = 72, + BuiltinOptions_RangeOptions = 73, + BuiltinOptions_ResizeNearestNeighborOptions = 74, + BuiltinOptions_LeakyReluOptions = 75, + BuiltinOptions_SquaredDifferenceOptions = 76, + BuiltinOptions_MirrorPadOptions = 77, + BuiltinOptions_AbsOptions = 78, + BuiltinOptions_SplitVOptions = 79, + BuiltinOptions_UniqueOptions = 80, + BuiltinOptions_ReverseV2Options = 81, + BuiltinOptions_AddNOptions = 82, + BuiltinOptions_GatherNdOptions = 83, + BuiltinOptions_CosOptions = 84, + BuiltinOptions_WhereOptions = 85, + BuiltinOptions_RankOptions = 86, + BuiltinOptions_ReverseSequenceOptions = 87, + BuiltinOptions_MatrixDiagOptions = 88, + BuiltinOptions_QuantizeOptions = 89, + BuiltinOptions_MatrixSetDiagOptions = 90, + BuiltinOptions_HardSwishOptions = 91, + BuiltinOptions_IfOptions = 92, + BuiltinOptions_WhileOptions = 93, + BuiltinOptions_DepthToSpaceOptions = 94, + BuiltinOptions_NonMaxSuppressionV4Options = 95, + BuiltinOptions_NonMaxSuppressionV5Options = 96, + BuiltinOptions_ScatterNdOptions = 97, + BuiltinOptions_SelectV2Options = 98, + BuiltinOptions_DensifyOptions = 99, + BuiltinOptions_SegmentSumOptions = 100, + BuiltinOptions_BatchMatMulOptions = 101, + BuiltinOptions_CumsumOptions = 102, + BuiltinOptions_CallOnceOptions = 103, + BuiltinOptions_BroadcastToOptions = 104, + BuiltinOptions_Rfft2dOptions = 105, + BuiltinOptions_Conv3DOptions = 106, + BuiltinOptions_HashtableOptions = 107, + BuiltinOptions_HashtableFindOptions = 108, + BuiltinOptions_HashtableImportOptions = 109, + BuiltinOptions_HashtableSizeOptions = 110, + BuiltinOptions_VarHandleOptions = 111, + BuiltinOptions_ReadVariableOptions = 112, + BuiltinOptions_AssignVariableOptions = 113, + BuiltinOptions_RandomOptions = 114, + BuiltinOptions_BucketizeOptions = 115, + BuiltinOptions_GeluOptions = 116, + BuiltinOptions_DynamicUpdateSliceOptions = 117, + BuiltinOptions_UnsortedSegmentProdOptions = 118, + BuiltinOptions_UnsortedSegmentMaxOptions = 119, + BuiltinOptions_UnsortedSegmentMinOptions = 120, + BuiltinOptions_UnsortedSegmentSumOptions = 121, + BuiltinOptions_ATan2Options = 122, + BuiltinOptions_SignOptions = 123, + BuiltinOptions_MIN = BuiltinOptions_NONE, + BuiltinOptions_MAX = BuiltinOptions_SignOptions +}; + +inline const BuiltinOptions (&EnumValuesBuiltinOptions())[124] { + static const BuiltinOptions values[] = { + BuiltinOptions_NONE, + BuiltinOptions_Conv2DOptions, + BuiltinOptions_DepthwiseConv2DOptions, + BuiltinOptions_ConcatEmbeddingsOptions, + BuiltinOptions_LSHProjectionOptions, + BuiltinOptions_Pool2DOptions, + BuiltinOptions_SVDFOptions, + BuiltinOptions_RNNOptions, + BuiltinOptions_FullyConnectedOptions, + BuiltinOptions_SoftmaxOptions, + BuiltinOptions_ConcatenationOptions, + BuiltinOptions_AddOptions, + BuiltinOptions_L2NormOptions, + BuiltinOptions_LocalResponseNormalizationOptions, + BuiltinOptions_LSTMOptions, + BuiltinOptions_ResizeBilinearOptions, + BuiltinOptions_CallOptions, + BuiltinOptions_ReshapeOptions, + BuiltinOptions_SkipGramOptions, + BuiltinOptions_SpaceToDepthOptions, + BuiltinOptions_EmbeddingLookupSparseOptions, + BuiltinOptions_MulOptions, + BuiltinOptions_PadOptions, + BuiltinOptions_GatherOptions, + BuiltinOptions_BatchToSpaceNDOptions, + BuiltinOptions_SpaceToBatchNDOptions, + BuiltinOptions_TransposeOptions, + BuiltinOptions_ReducerOptions, + BuiltinOptions_SubOptions, + BuiltinOptions_DivOptions, + BuiltinOptions_SqueezeOptions, + BuiltinOptions_SequenceRNNOptions, + BuiltinOptions_StridedSliceOptions, + BuiltinOptions_ExpOptions, + BuiltinOptions_TopKV2Options, + BuiltinOptions_SplitOptions, + BuiltinOptions_LogSoftmaxOptions, + BuiltinOptions_CastOptions, + BuiltinOptions_DequantizeOptions, + BuiltinOptions_MaximumMinimumOptions, + BuiltinOptions_ArgMaxOptions, + BuiltinOptions_LessOptions, + BuiltinOptions_NegOptions, + BuiltinOptions_PadV2Options, + BuiltinOptions_GreaterOptions, + BuiltinOptions_GreaterEqualOptions, + BuiltinOptions_LessEqualOptions, + BuiltinOptions_SelectOptions, + BuiltinOptions_SliceOptions, + BuiltinOptions_TransposeConvOptions, + BuiltinOptions_SparseToDenseOptions, + BuiltinOptions_TileOptions, + BuiltinOptions_ExpandDimsOptions, + BuiltinOptions_EqualOptions, + BuiltinOptions_NotEqualOptions, + BuiltinOptions_ShapeOptions, + BuiltinOptions_PowOptions, + BuiltinOptions_ArgMinOptions, + BuiltinOptions_FakeQuantOptions, + BuiltinOptions_PackOptions, + BuiltinOptions_LogicalOrOptions, + BuiltinOptions_OneHotOptions, + BuiltinOptions_LogicalAndOptions, + BuiltinOptions_LogicalNotOptions, + BuiltinOptions_UnpackOptions, + BuiltinOptions_FloorDivOptions, + BuiltinOptions_SquareOptions, + BuiltinOptions_ZerosLikeOptions, + BuiltinOptions_FillOptions, + BuiltinOptions_BidirectionalSequenceLSTMOptions, + BuiltinOptions_BidirectionalSequenceRNNOptions, + BuiltinOptions_UnidirectionalSequenceLSTMOptions, + BuiltinOptions_FloorModOptions, + BuiltinOptions_RangeOptions, + BuiltinOptions_ResizeNearestNeighborOptions, + BuiltinOptions_LeakyReluOptions, + BuiltinOptions_SquaredDifferenceOptions, + BuiltinOptions_MirrorPadOptions, + BuiltinOptions_AbsOptions, + BuiltinOptions_SplitVOptions, + BuiltinOptions_UniqueOptions, + BuiltinOptions_ReverseV2Options, + BuiltinOptions_AddNOptions, + BuiltinOptions_GatherNdOptions, + BuiltinOptions_CosOptions, + BuiltinOptions_WhereOptions, + BuiltinOptions_RankOptions, + BuiltinOptions_ReverseSequenceOptions, + BuiltinOptions_MatrixDiagOptions, + BuiltinOptions_QuantizeOptions, + BuiltinOptions_MatrixSetDiagOptions, + BuiltinOptions_HardSwishOptions, + BuiltinOptions_IfOptions, + BuiltinOptions_WhileOptions, + BuiltinOptions_DepthToSpaceOptions, + BuiltinOptions_NonMaxSuppressionV4Options, + BuiltinOptions_NonMaxSuppressionV5Options, + BuiltinOptions_ScatterNdOptions, + BuiltinOptions_SelectV2Options, + BuiltinOptions_DensifyOptions, + BuiltinOptions_SegmentSumOptions, + BuiltinOptions_BatchMatMulOptions, + BuiltinOptions_CumsumOptions, + BuiltinOptions_CallOnceOptions, + BuiltinOptions_BroadcastToOptions, + BuiltinOptions_Rfft2dOptions, + BuiltinOptions_Conv3DOptions, + BuiltinOptions_HashtableOptions, + BuiltinOptions_HashtableFindOptions, + BuiltinOptions_HashtableImportOptions, + BuiltinOptions_HashtableSizeOptions, + BuiltinOptions_VarHandleOptions, + BuiltinOptions_ReadVariableOptions, + BuiltinOptions_AssignVariableOptions, + BuiltinOptions_RandomOptions, + BuiltinOptions_BucketizeOptions, + BuiltinOptions_GeluOptions, + BuiltinOptions_DynamicUpdateSliceOptions, + BuiltinOptions_UnsortedSegmentProdOptions, + BuiltinOptions_UnsortedSegmentMaxOptions, + BuiltinOptions_UnsortedSegmentMinOptions, + BuiltinOptions_UnsortedSegmentSumOptions, + BuiltinOptions_ATan2Options, + BuiltinOptions_SignOptions + }; + return values; +} + +inline const char * const *EnumNamesBuiltinOptions() { + static const char * const names[125] = { + "NONE", + "Conv2DOptions", + "DepthwiseConv2DOptions", + "ConcatEmbeddingsOptions", + "LSHProjectionOptions", + "Pool2DOptions", + "SVDFOptions", + "RNNOptions", + "FullyConnectedOptions", + "SoftmaxOptions", + "ConcatenationOptions", + "AddOptions", + "L2NormOptions", + "LocalResponseNormalizationOptions", + "LSTMOptions", + "ResizeBilinearOptions", + "CallOptions", + "ReshapeOptions", + "SkipGramOptions", + "SpaceToDepthOptions", + "EmbeddingLookupSparseOptions", + "MulOptions", + "PadOptions", + "GatherOptions", + "BatchToSpaceNDOptions", + "SpaceToBatchNDOptions", + "TransposeOptions", + "ReducerOptions", + "SubOptions", + "DivOptions", + "SqueezeOptions", + "SequenceRNNOptions", + "StridedSliceOptions", + "ExpOptions", + "TopKV2Options", + "SplitOptions", + "LogSoftmaxOptions", + "CastOptions", + "DequantizeOptions", + "MaximumMinimumOptions", + "ArgMaxOptions", + "LessOptions", + "NegOptions", + "PadV2Options", + "GreaterOptions", + "GreaterEqualOptions", + "LessEqualOptions", + "SelectOptions", + "SliceOptions", + "TransposeConvOptions", + "SparseToDenseOptions", + "TileOptions", + "ExpandDimsOptions", + "EqualOptions", + "NotEqualOptions", + "ShapeOptions", + "PowOptions", + "ArgMinOptions", + "FakeQuantOptions", + "PackOptions", + "LogicalOrOptions", + "OneHotOptions", + "LogicalAndOptions", + "LogicalNotOptions", + "UnpackOptions", + "FloorDivOptions", + "SquareOptions", + "ZerosLikeOptions", + "FillOptions", + "BidirectionalSequenceLSTMOptions", + "BidirectionalSequenceRNNOptions", + "UnidirectionalSequenceLSTMOptions", + "FloorModOptions", + "RangeOptions", + "ResizeNearestNeighborOptions", + "LeakyReluOptions", + "SquaredDifferenceOptions", + "MirrorPadOptions", + "AbsOptions", + "SplitVOptions", + "UniqueOptions", + "ReverseV2Options", + "AddNOptions", + "GatherNdOptions", + "CosOptions", + "WhereOptions", + "RankOptions", + "ReverseSequenceOptions", + "MatrixDiagOptions", + "QuantizeOptions", + "MatrixSetDiagOptions", + "HardSwishOptions", + "IfOptions", + "WhileOptions", + "DepthToSpaceOptions", + "NonMaxSuppressionV4Options", + "NonMaxSuppressionV5Options", + "ScatterNdOptions", + "SelectV2Options", + "DensifyOptions", + "SegmentSumOptions", + "BatchMatMulOptions", + "CumsumOptions", + "CallOnceOptions", + "BroadcastToOptions", + "Rfft2dOptions", + "Conv3DOptions", + "HashtableOptions", + "HashtableFindOptions", + "HashtableImportOptions", + "HashtableSizeOptions", + "VarHandleOptions", + "ReadVariableOptions", + "AssignVariableOptions", + "RandomOptions", + "BucketizeOptions", + "GeluOptions", + "DynamicUpdateSliceOptions", + "UnsortedSegmentProdOptions", + "UnsortedSegmentMaxOptions", + "UnsortedSegmentMinOptions", + "UnsortedSegmentSumOptions", + "ATan2Options", + "SignOptions", + nullptr + }; + return names; +} + +inline const char *EnumNameBuiltinOptions(BuiltinOptions e) { + if (flatbuffers::IsOutRange(e, BuiltinOptions_NONE, BuiltinOptions_SignOptions)) return ""; + const size_t index = static_cast(e); + return EnumNamesBuiltinOptions()[index]; +} + +template struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NONE; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Conv2DOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DepthwiseConv2DOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ConcatEmbeddingsOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LSHProjectionOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Pool2DOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SVDFOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RNNOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FullyConnectedOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SoftmaxOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ConcatenationOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AddOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_L2NormOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LocalResponseNormalizationOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LSTMOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ResizeBilinearOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CallOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReshapeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SkipGramOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SpaceToDepthOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_EmbeddingLookupSparseOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MulOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PadOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GatherOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BatchToSpaceNDOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SpaceToBatchNDOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TransposeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReducerOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SubOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DivOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SqueezeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SequenceRNNOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_StridedSliceOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ExpOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TopKV2Options; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SplitOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogSoftmaxOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CastOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DequantizeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MaximumMinimumOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ArgMaxOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LessOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NegOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PadV2Options; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GreaterOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GreaterEqualOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LessEqualOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SelectOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SliceOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TransposeConvOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SparseToDenseOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TileOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ExpandDimsOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_EqualOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NotEqualOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ShapeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PowOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ArgMinOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FakeQuantOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PackOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogicalOrOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_OneHotOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogicalAndOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogicalNotOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnpackOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FloorDivOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SquareOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ZerosLikeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FillOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceLSTMOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceRNNOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnidirectionalSequenceLSTMOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FloorModOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RangeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ResizeNearestNeighborOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LeakyReluOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SquaredDifferenceOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MirrorPadOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AbsOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SplitVOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UniqueOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReverseV2Options; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AddNOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GatherNdOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CosOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_WhereOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RankOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReverseSequenceOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MatrixDiagOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_QuantizeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MatrixSetDiagOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HardSwishOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_IfOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_WhileOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DepthToSpaceOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NonMaxSuppressionV4Options; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NonMaxSuppressionV5Options; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ScatterNdOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SelectV2Options; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DensifyOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SegmentSumOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BatchMatMulOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CumsumOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CallOnceOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BroadcastToOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Rfft2dOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Conv3DOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableFindOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableImportOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableSizeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_VarHandleOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReadVariableOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AssignVariableOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RandomOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BucketizeOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GeluOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DynamicUpdateSliceOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentProdOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentMaxOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentMinOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentSumOptions; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ATan2Options; +}; + +template<> struct BuiltinOptionsTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SignOptions; +}; + +template struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NONE; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Conv2DOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DepthwiseConv2DOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ConcatEmbeddingsOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LSHProjectionOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Pool2DOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SVDFOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RNNOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FullyConnectedOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SoftmaxOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ConcatenationOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AddOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_L2NormOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LocalResponseNormalizationOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LSTMOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ResizeBilinearOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CallOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReshapeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SkipGramOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SpaceToDepthOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_EmbeddingLookupSparseOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MulOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PadOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GatherOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BatchToSpaceNDOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SpaceToBatchNDOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TransposeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReducerOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SubOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DivOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SqueezeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SequenceRNNOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_StridedSliceOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ExpOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TopKV2Options; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SplitOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogSoftmaxOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CastOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DequantizeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MaximumMinimumOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ArgMaxOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LessOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NegOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PadV2Options; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GreaterOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GreaterEqualOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LessEqualOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SelectOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SliceOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TransposeConvOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SparseToDenseOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_TileOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ExpandDimsOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_EqualOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NotEqualOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ShapeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PowOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ArgMinOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FakeQuantOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_PackOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogicalOrOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_OneHotOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogicalAndOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LogicalNotOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnpackOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FloorDivOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SquareOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ZerosLikeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FillOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceLSTMOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BidirectionalSequenceRNNOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnidirectionalSequenceLSTMOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_FloorModOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RangeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ResizeNearestNeighborOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_LeakyReluOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SquaredDifferenceOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MirrorPadOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AbsOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SplitVOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UniqueOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReverseV2Options; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AddNOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GatherNdOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CosOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_WhereOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RankOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReverseSequenceOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MatrixDiagOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_QuantizeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_MatrixSetDiagOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HardSwishOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_IfOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_WhileOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DepthToSpaceOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NonMaxSuppressionV4Options; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_NonMaxSuppressionV5Options; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ScatterNdOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SelectV2Options; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DensifyOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SegmentSumOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BatchMatMulOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CumsumOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_CallOnceOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BroadcastToOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Rfft2dOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_Conv3DOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableFindOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableImportOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_HashtableSizeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_VarHandleOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ReadVariableOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_AssignVariableOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_RandomOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_BucketizeOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_GeluOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_DynamicUpdateSliceOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentProdOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentMaxOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentMinOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_UnsortedSegmentSumOptions; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_ATan2Options; +}; + +template<> struct BuiltinOptionsUnionTraits { + static const BuiltinOptions enum_value = BuiltinOptions_SignOptions; +}; + +struct OperatorCodeT : public flatbuffers::NativeTable { + typedef OperatorCode TableType; + int8_t deprecated_builtin_code = 0; + std::string custom_code{}; + int32_t version = 1; + tflite::BuiltinOperator builtin_code = tflite::BuiltinOperator_ADD; +}; + +struct OperatorCode FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef OperatorCodeT NativeTableType; + typedef OperatorCodeBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_DEPRECATED_BUILTIN_CODE = 4, + VT_CUSTOM_CODE = 6, + VT_VERSION = 8, + VT_BUILTIN_CODE = 10 + }; + int8_t deprecated_builtin_code() const { + return GetField(VT_DEPRECATED_BUILTIN_CODE, 0); + } + const flatbuffers::String *custom_code() const { + return GetPointer(VT_CUSTOM_CODE); + } + int32_t version() const { + return GetField(VT_VERSION, 1); + } + tflite::BuiltinOperator builtin_code() const { + return static_cast(GetField(VT_BUILTIN_CODE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_DEPRECATED_BUILTIN_CODE, 1) && + VerifyOffset(verifier, VT_CUSTOM_CODE) && + verifier.VerifyString(custom_code()) && + VerifyField(verifier, VT_VERSION, 4) && + VerifyField(verifier, VT_BUILTIN_CODE, 4) && + verifier.EndTable(); + } + OperatorCodeT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(OperatorCodeT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const OperatorCodeT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +} +#endif // FLATBUFFERS_GENERATED_SCHEMA_SUPPL_TFLITE_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h new file mode 100755 index 0000000..aaa2252 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_generated_full.h @@ -0,0 +1,17601 @@ +// automatically generated by the FlatBuffers compiler, do not modify + + +#ifndef FLATBUFFERS_GENERATED_SCHEMA_TFLITE_H_ +#define FLATBUFFERS_GENERATED_SCHEMA_TFLITE_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" + +// Ensure the included flatbuffers.h is the same version as when this file was +// generated, otherwise it may not be compatible. +static_assert(FLATBUFFERS_VERSION_MAJOR == 2 && + FLATBUFFERS_VERSION_MINOR == 0 && + FLATBUFFERS_VERSION_REVISION == 6, + "Non-compatible flatbuffers version included"); + +namespace tflite { + +enum QuantizationDetails : uint8_t { + QuantizationDetails_NONE = 0, + QuantizationDetails_CustomQuantization = 1, + QuantizationDetails_MIN = QuantizationDetails_NONE, + QuantizationDetails_MAX = QuantizationDetails_CustomQuantization +}; + +inline const QuantizationDetails (&EnumValuesQuantizationDetails())[2] { + static const QuantizationDetails values[] = { + QuantizationDetails_NONE, + QuantizationDetails_CustomQuantization + }; + return values; +} + +inline const char * const *EnumNamesQuantizationDetails() { + static const char * const names[3] = { + "NONE", + "CustomQuantization", + nullptr + }; + return names; +} + +inline const char *EnumNameQuantizationDetails(QuantizationDetails e) { + if (flatbuffers::IsOutRange(e, QuantizationDetails_NONE, QuantizationDetails_CustomQuantization)) return ""; + const size_t index = static_cast(e); + return EnumNamesQuantizationDetails()[index]; +} + +template struct QuantizationDetailsTraits { + static const QuantizationDetails enum_value = QuantizationDetails_NONE; +}; + +template<> struct QuantizationDetailsTraits { + static const QuantizationDetails enum_value = QuantizationDetails_CustomQuantization; +}; + +template struct QuantizationDetailsUnionTraits { + static const QuantizationDetails enum_value = QuantizationDetails_NONE; +}; + +template<> struct QuantizationDetailsUnionTraits { + static const QuantizationDetails enum_value = QuantizationDetails_CustomQuantization; +}; + +struct QuantizationDetailsUnion { + QuantizationDetails type; + void *value; + + QuantizationDetailsUnion() : type(QuantizationDetails_NONE), value(nullptr) {} + QuantizationDetailsUnion(QuantizationDetailsUnion&& u) FLATBUFFERS_NOEXCEPT : + type(QuantizationDetails_NONE), value(nullptr) + { std::swap(type, u.type); std::swap(value, u.value); } + QuantizationDetailsUnion(const QuantizationDetailsUnion &); + QuantizationDetailsUnion &operator=(const QuantizationDetailsUnion &u) + { QuantizationDetailsUnion t(u); std::swap(type, t.type); std::swap(value, t.value); return *this; } + QuantizationDetailsUnion &operator=(QuantizationDetailsUnion &&u) FLATBUFFERS_NOEXCEPT + { std::swap(type, u.type); std::swap(value, u.value); return *this; } + ~QuantizationDetailsUnion() { Reset(); } + + void Reset(); + + template + void Set(T&& val) { + typedef typename std::remove_reference::type RT; + Reset(); + type = QuantizationDetailsUnionTraits::enum_value; + if (type != QuantizationDetails_NONE) { + value = new RT(std::forward(val)); + } + } + + static void *UnPack(const void *obj, QuantizationDetails type, const flatbuffers::resolver_function_t *resolver); + flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const flatbuffers::rehasher_function_t *_rehasher = nullptr) const; + + tflite::CustomQuantizationT *AsCustomQuantization() { + return type == QuantizationDetails_CustomQuantization ? + reinterpret_cast(value) : nullptr; + } + const tflite::CustomQuantizationT *AsCustomQuantization() const { + return type == QuantizationDetails_CustomQuantization ? + reinterpret_cast(value) : nullptr; + } +}; + +bool VerifyQuantizationDetails(flatbuffers::Verifier &verifier, const void *obj, QuantizationDetails type); +bool VerifyQuantizationDetailsVector(flatbuffers::Verifier &verifier, const flatbuffers::Vector> *values, const flatbuffers::Vector *types); + +enum DimensionType : int8_t { + DimensionType_DENSE = 0, + DimensionType_SPARSE_CSR = 1, + DimensionType_MIN = DimensionType_DENSE, + DimensionType_MAX = DimensionType_SPARSE_CSR +}; + +inline const DimensionType (&EnumValuesDimensionType())[2] { + static const DimensionType values[] = { + DimensionType_DENSE, + DimensionType_SPARSE_CSR + }; + return values; +} + +inline const char * const *EnumNamesDimensionType() { + static const char * const names[3] = { + "DENSE", + "SPARSE_CSR", + nullptr + }; + return names; +} + +inline const char *EnumNameDimensionType(DimensionType e) { + if (flatbuffers::IsOutRange(e, DimensionType_DENSE, DimensionType_SPARSE_CSR)) return ""; + const size_t index = static_cast(e); + return EnumNamesDimensionType()[index]; +} + +enum SparseIndexVector : uint8_t { + SparseIndexVector_NONE = 0, + SparseIndexVector_Int32Vector = 1, + SparseIndexVector_Uint16Vector = 2, + SparseIndexVector_Uint8Vector = 3, + SparseIndexVector_MIN = SparseIndexVector_NONE, + SparseIndexVector_MAX = SparseIndexVector_Uint8Vector +}; + +inline const SparseIndexVector (&EnumValuesSparseIndexVector())[4] { + static const SparseIndexVector values[] = { + SparseIndexVector_NONE, + SparseIndexVector_Int32Vector, + SparseIndexVector_Uint16Vector, + SparseIndexVector_Uint8Vector + }; + return values; +} + +inline const char * const *EnumNamesSparseIndexVector() { + static const char * const names[5] = { + "NONE", + "Int32Vector", + "Uint16Vector", + "Uint8Vector", + nullptr + }; + return names; +} + +inline const char *EnumNameSparseIndexVector(SparseIndexVector e) { + if (flatbuffers::IsOutRange(e, SparseIndexVector_NONE, SparseIndexVector_Uint8Vector)) return ""; + const size_t index = static_cast(e); + return EnumNamesSparseIndexVector()[index]; +} + +template struct SparseIndexVectorTraits { + static const SparseIndexVector enum_value = SparseIndexVector_NONE; +}; + +template<> struct SparseIndexVectorTraits { + static const SparseIndexVector enum_value = SparseIndexVector_Int32Vector; +}; + +template<> struct SparseIndexVectorTraits { + static const SparseIndexVector enum_value = SparseIndexVector_Uint16Vector; +}; + +template<> struct SparseIndexVectorTraits { + static const SparseIndexVector enum_value = SparseIndexVector_Uint8Vector; +}; + +template struct SparseIndexVectorUnionTraits { + static const SparseIndexVector enum_value = SparseIndexVector_NONE; +}; + +template<> struct SparseIndexVectorUnionTraits { + static const SparseIndexVector enum_value = SparseIndexVector_Int32Vector; +}; + +template<> struct SparseIndexVectorUnionTraits { + static const SparseIndexVector enum_value = SparseIndexVector_Uint16Vector; +}; + +template<> struct SparseIndexVectorUnionTraits { + static const SparseIndexVector enum_value = SparseIndexVector_Uint8Vector; +}; + +struct SparseIndexVectorUnion { + SparseIndexVector type; + void *value; + + SparseIndexVectorUnion() : type(SparseIndexVector_NONE), value(nullptr) {} + SparseIndexVectorUnion(SparseIndexVectorUnion&& u) FLATBUFFERS_NOEXCEPT : + type(SparseIndexVector_NONE), value(nullptr) + { std::swap(type, u.type); std::swap(value, u.value); } + SparseIndexVectorUnion(const SparseIndexVectorUnion &); + SparseIndexVectorUnion &operator=(const SparseIndexVectorUnion &u) + { SparseIndexVectorUnion t(u); std::swap(type, t.type); std::swap(value, t.value); return *this; } + SparseIndexVectorUnion &operator=(SparseIndexVectorUnion &&u) FLATBUFFERS_NOEXCEPT + { std::swap(type, u.type); std::swap(value, u.value); return *this; } + ~SparseIndexVectorUnion() { Reset(); } + + void Reset(); + + template + void Set(T&& val) { + typedef typename std::remove_reference::type RT; + Reset(); + type = SparseIndexVectorUnionTraits::enum_value; + if (type != SparseIndexVector_NONE) { + value = new RT(std::forward(val)); + } + } + + static void *UnPack(const void *obj, SparseIndexVector type, const flatbuffers::resolver_function_t *resolver); + flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const flatbuffers::rehasher_function_t *_rehasher = nullptr) const; + + tflite::Int32VectorT *AsInt32Vector() { + return type == SparseIndexVector_Int32Vector ? + reinterpret_cast(value) : nullptr; + } + const tflite::Int32VectorT *AsInt32Vector() const { + return type == SparseIndexVector_Int32Vector ? + reinterpret_cast(value) : nullptr; + } + tflite::Uint16VectorT *AsUint16Vector() { + return type == SparseIndexVector_Uint16Vector ? + reinterpret_cast(value) : nullptr; + } + const tflite::Uint16VectorT *AsUint16Vector() const { + return type == SparseIndexVector_Uint16Vector ? + reinterpret_cast(value) : nullptr; + } + tflite::Uint8VectorT *AsUint8Vector() { + return type == SparseIndexVector_Uint8Vector ? + reinterpret_cast(value) : nullptr; + } + const tflite::Uint8VectorT *AsUint8Vector() const { + return type == SparseIndexVector_Uint8Vector ? + reinterpret_cast(value) : nullptr; + } +}; + +bool VerifySparseIndexVector(flatbuffers::Verifier &verifier, const void *obj, SparseIndexVector type); +bool VerifySparseIndexVectorVector(flatbuffers::Verifier &verifier, const flatbuffers::Vector> *values, const flatbuffers::Vector *types); + +struct BuiltinOptionsUnion { + BuiltinOptions type; + void *value; + + BuiltinOptionsUnion() : type(BuiltinOptions_NONE), value(nullptr) {} + BuiltinOptionsUnion(BuiltinOptionsUnion&& u) FLATBUFFERS_NOEXCEPT : + type(BuiltinOptions_NONE), value(nullptr) + { std::swap(type, u.type); std::swap(value, u.value); } + BuiltinOptionsUnion(const BuiltinOptionsUnion &); + BuiltinOptionsUnion &operator=(const BuiltinOptionsUnion &u) + { BuiltinOptionsUnion t(u); std::swap(type, t.type); std::swap(value, t.value); return *this; } + BuiltinOptionsUnion &operator=(BuiltinOptionsUnion &&u) FLATBUFFERS_NOEXCEPT + { std::swap(type, u.type); std::swap(value, u.value); return *this; } + ~BuiltinOptionsUnion() { Reset(); } + + void Reset(); + + template + void Set(T&& val) { + typedef typename std::remove_reference::type RT; + Reset(); + type = BuiltinOptionsUnionTraits::enum_value; + if (type != BuiltinOptions_NONE) { + value = new RT(std::forward(val)); + } + } + + static void *UnPack(const void *obj, BuiltinOptions type, const flatbuffers::resolver_function_t *resolver); + flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const flatbuffers::rehasher_function_t *_rehasher = nullptr) const; + + tflite::Conv2DOptionsT *AsConv2DOptions() { + return type == BuiltinOptions_Conv2DOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::Conv2DOptionsT *AsConv2DOptions() const { + return type == BuiltinOptions_Conv2DOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::DepthwiseConv2DOptionsT *AsDepthwiseConv2DOptions() { + return type == BuiltinOptions_DepthwiseConv2DOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::DepthwiseConv2DOptionsT *AsDepthwiseConv2DOptions() const { + return type == BuiltinOptions_DepthwiseConv2DOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ConcatEmbeddingsOptionsT *AsConcatEmbeddingsOptions() { + return type == BuiltinOptions_ConcatEmbeddingsOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ConcatEmbeddingsOptionsT *AsConcatEmbeddingsOptions() const { + return type == BuiltinOptions_ConcatEmbeddingsOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LSHProjectionOptionsT *AsLSHProjectionOptions() { + return type == BuiltinOptions_LSHProjectionOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LSHProjectionOptionsT *AsLSHProjectionOptions() const { + return type == BuiltinOptions_LSHProjectionOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::Pool2DOptionsT *AsPool2DOptions() { + return type == BuiltinOptions_Pool2DOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::Pool2DOptionsT *AsPool2DOptions() const { + return type == BuiltinOptions_Pool2DOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SVDFOptionsT *AsSVDFOptions() { + return type == BuiltinOptions_SVDFOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SVDFOptionsT *AsSVDFOptions() const { + return type == BuiltinOptions_SVDFOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::RNNOptionsT *AsRNNOptions() { + return type == BuiltinOptions_RNNOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::RNNOptionsT *AsRNNOptions() const { + return type == BuiltinOptions_RNNOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::FullyConnectedOptionsT *AsFullyConnectedOptions() { + return type == BuiltinOptions_FullyConnectedOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::FullyConnectedOptionsT *AsFullyConnectedOptions() const { + return type == BuiltinOptions_FullyConnectedOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SoftmaxOptionsT *AsSoftmaxOptions() { + return type == BuiltinOptions_SoftmaxOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SoftmaxOptionsT *AsSoftmaxOptions() const { + return type == BuiltinOptions_SoftmaxOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ConcatenationOptionsT *AsConcatenationOptions() { + return type == BuiltinOptions_ConcatenationOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ConcatenationOptionsT *AsConcatenationOptions() const { + return type == BuiltinOptions_ConcatenationOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::AddOptionsT *AsAddOptions() { + return type == BuiltinOptions_AddOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::AddOptionsT *AsAddOptions() const { + return type == BuiltinOptions_AddOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::L2NormOptionsT *AsL2NormOptions() { + return type == BuiltinOptions_L2NormOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::L2NormOptionsT *AsL2NormOptions() const { + return type == BuiltinOptions_L2NormOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LocalResponseNormalizationOptionsT *AsLocalResponseNormalizationOptions() { + return type == BuiltinOptions_LocalResponseNormalizationOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LocalResponseNormalizationOptionsT *AsLocalResponseNormalizationOptions() const { + return type == BuiltinOptions_LocalResponseNormalizationOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LSTMOptionsT *AsLSTMOptions() { + return type == BuiltinOptions_LSTMOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LSTMOptionsT *AsLSTMOptions() const { + return type == BuiltinOptions_LSTMOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ResizeBilinearOptionsT *AsResizeBilinearOptions() { + return type == BuiltinOptions_ResizeBilinearOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ResizeBilinearOptionsT *AsResizeBilinearOptions() const { + return type == BuiltinOptions_ResizeBilinearOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::CallOptionsT *AsCallOptions() { + return type == BuiltinOptions_CallOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::CallOptionsT *AsCallOptions() const { + return type == BuiltinOptions_CallOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ReshapeOptionsT *AsReshapeOptions() { + return type == BuiltinOptions_ReshapeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ReshapeOptionsT *AsReshapeOptions() const { + return type == BuiltinOptions_ReshapeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SkipGramOptionsT *AsSkipGramOptions() { + return type == BuiltinOptions_SkipGramOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SkipGramOptionsT *AsSkipGramOptions() const { + return type == BuiltinOptions_SkipGramOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SpaceToDepthOptionsT *AsSpaceToDepthOptions() { + return type == BuiltinOptions_SpaceToDepthOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SpaceToDepthOptionsT *AsSpaceToDepthOptions() const { + return type == BuiltinOptions_SpaceToDepthOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::EmbeddingLookupSparseOptionsT *AsEmbeddingLookupSparseOptions() { + return type == BuiltinOptions_EmbeddingLookupSparseOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::EmbeddingLookupSparseOptionsT *AsEmbeddingLookupSparseOptions() const { + return type == BuiltinOptions_EmbeddingLookupSparseOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::MulOptionsT *AsMulOptions() { + return type == BuiltinOptions_MulOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::MulOptionsT *AsMulOptions() const { + return type == BuiltinOptions_MulOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::PadOptionsT *AsPadOptions() { + return type == BuiltinOptions_PadOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::PadOptionsT *AsPadOptions() const { + return type == BuiltinOptions_PadOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::GatherOptionsT *AsGatherOptions() { + return type == BuiltinOptions_GatherOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::GatherOptionsT *AsGatherOptions() const { + return type == BuiltinOptions_GatherOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::BatchToSpaceNDOptionsT *AsBatchToSpaceNDOptions() { + return type == BuiltinOptions_BatchToSpaceNDOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::BatchToSpaceNDOptionsT *AsBatchToSpaceNDOptions() const { + return type == BuiltinOptions_BatchToSpaceNDOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SpaceToBatchNDOptionsT *AsSpaceToBatchNDOptions() { + return type == BuiltinOptions_SpaceToBatchNDOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SpaceToBatchNDOptionsT *AsSpaceToBatchNDOptions() const { + return type == BuiltinOptions_SpaceToBatchNDOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::TransposeOptionsT *AsTransposeOptions() { + return type == BuiltinOptions_TransposeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::TransposeOptionsT *AsTransposeOptions() const { + return type == BuiltinOptions_TransposeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ReducerOptionsT *AsReducerOptions() { + return type == BuiltinOptions_ReducerOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ReducerOptionsT *AsReducerOptions() const { + return type == BuiltinOptions_ReducerOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SubOptionsT *AsSubOptions() { + return type == BuiltinOptions_SubOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SubOptionsT *AsSubOptions() const { + return type == BuiltinOptions_SubOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::DivOptionsT *AsDivOptions() { + return type == BuiltinOptions_DivOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::DivOptionsT *AsDivOptions() const { + return type == BuiltinOptions_DivOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SqueezeOptionsT *AsSqueezeOptions() { + return type == BuiltinOptions_SqueezeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SqueezeOptionsT *AsSqueezeOptions() const { + return type == BuiltinOptions_SqueezeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SequenceRNNOptionsT *AsSequenceRNNOptions() { + return type == BuiltinOptions_SequenceRNNOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SequenceRNNOptionsT *AsSequenceRNNOptions() const { + return type == BuiltinOptions_SequenceRNNOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::StridedSliceOptionsT *AsStridedSliceOptions() { + return type == BuiltinOptions_StridedSliceOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::StridedSliceOptionsT *AsStridedSliceOptions() const { + return type == BuiltinOptions_StridedSliceOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ExpOptionsT *AsExpOptions() { + return type == BuiltinOptions_ExpOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ExpOptionsT *AsExpOptions() const { + return type == BuiltinOptions_ExpOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::TopKV2OptionsT *AsTopKV2Options() { + return type == BuiltinOptions_TopKV2Options ? + reinterpret_cast(value) : nullptr; + } + const tflite::TopKV2OptionsT *AsTopKV2Options() const { + return type == BuiltinOptions_TopKV2Options ? + reinterpret_cast(value) : nullptr; + } + tflite::SplitOptionsT *AsSplitOptions() { + return type == BuiltinOptions_SplitOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SplitOptionsT *AsSplitOptions() const { + return type == BuiltinOptions_SplitOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LogSoftmaxOptionsT *AsLogSoftmaxOptions() { + return type == BuiltinOptions_LogSoftmaxOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LogSoftmaxOptionsT *AsLogSoftmaxOptions() const { + return type == BuiltinOptions_LogSoftmaxOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::CastOptionsT *AsCastOptions() { + return type == BuiltinOptions_CastOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::CastOptionsT *AsCastOptions() const { + return type == BuiltinOptions_CastOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::DequantizeOptionsT *AsDequantizeOptions() { + return type == BuiltinOptions_DequantizeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::DequantizeOptionsT *AsDequantizeOptions() const { + return type == BuiltinOptions_DequantizeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::MaximumMinimumOptionsT *AsMaximumMinimumOptions() { + return type == BuiltinOptions_MaximumMinimumOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::MaximumMinimumOptionsT *AsMaximumMinimumOptions() const { + return type == BuiltinOptions_MaximumMinimumOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ArgMaxOptionsT *AsArgMaxOptions() { + return type == BuiltinOptions_ArgMaxOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ArgMaxOptionsT *AsArgMaxOptions() const { + return type == BuiltinOptions_ArgMaxOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LessOptionsT *AsLessOptions() { + return type == BuiltinOptions_LessOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LessOptionsT *AsLessOptions() const { + return type == BuiltinOptions_LessOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::NegOptionsT *AsNegOptions() { + return type == BuiltinOptions_NegOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::NegOptionsT *AsNegOptions() const { + return type == BuiltinOptions_NegOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::PadV2OptionsT *AsPadV2Options() { + return type == BuiltinOptions_PadV2Options ? + reinterpret_cast(value) : nullptr; + } + const tflite::PadV2OptionsT *AsPadV2Options() const { + return type == BuiltinOptions_PadV2Options ? + reinterpret_cast(value) : nullptr; + } + tflite::GreaterOptionsT *AsGreaterOptions() { + return type == BuiltinOptions_GreaterOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::GreaterOptionsT *AsGreaterOptions() const { + return type == BuiltinOptions_GreaterOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::GreaterEqualOptionsT *AsGreaterEqualOptions() { + return type == BuiltinOptions_GreaterEqualOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::GreaterEqualOptionsT *AsGreaterEqualOptions() const { + return type == BuiltinOptions_GreaterEqualOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LessEqualOptionsT *AsLessEqualOptions() { + return type == BuiltinOptions_LessEqualOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LessEqualOptionsT *AsLessEqualOptions() const { + return type == BuiltinOptions_LessEqualOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SelectOptionsT *AsSelectOptions() { + return type == BuiltinOptions_SelectOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SelectOptionsT *AsSelectOptions() const { + return type == BuiltinOptions_SelectOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SliceOptionsT *AsSliceOptions() { + return type == BuiltinOptions_SliceOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SliceOptionsT *AsSliceOptions() const { + return type == BuiltinOptions_SliceOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::TransposeConvOptionsT *AsTransposeConvOptions() { + return type == BuiltinOptions_TransposeConvOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::TransposeConvOptionsT *AsTransposeConvOptions() const { + return type == BuiltinOptions_TransposeConvOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SparseToDenseOptionsT *AsSparseToDenseOptions() { + return type == BuiltinOptions_SparseToDenseOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SparseToDenseOptionsT *AsSparseToDenseOptions() const { + return type == BuiltinOptions_SparseToDenseOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::TileOptionsT *AsTileOptions() { + return type == BuiltinOptions_TileOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::TileOptionsT *AsTileOptions() const { + return type == BuiltinOptions_TileOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ExpandDimsOptionsT *AsExpandDimsOptions() { + return type == BuiltinOptions_ExpandDimsOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ExpandDimsOptionsT *AsExpandDimsOptions() const { + return type == BuiltinOptions_ExpandDimsOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::EqualOptionsT *AsEqualOptions() { + return type == BuiltinOptions_EqualOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::EqualOptionsT *AsEqualOptions() const { + return type == BuiltinOptions_EqualOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::NotEqualOptionsT *AsNotEqualOptions() { + return type == BuiltinOptions_NotEqualOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::NotEqualOptionsT *AsNotEqualOptions() const { + return type == BuiltinOptions_NotEqualOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ShapeOptionsT *AsShapeOptions() { + return type == BuiltinOptions_ShapeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ShapeOptionsT *AsShapeOptions() const { + return type == BuiltinOptions_ShapeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::PowOptionsT *AsPowOptions() { + return type == BuiltinOptions_PowOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::PowOptionsT *AsPowOptions() const { + return type == BuiltinOptions_PowOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ArgMinOptionsT *AsArgMinOptions() { + return type == BuiltinOptions_ArgMinOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ArgMinOptionsT *AsArgMinOptions() const { + return type == BuiltinOptions_ArgMinOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::FakeQuantOptionsT *AsFakeQuantOptions() { + return type == BuiltinOptions_FakeQuantOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::FakeQuantOptionsT *AsFakeQuantOptions() const { + return type == BuiltinOptions_FakeQuantOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::PackOptionsT *AsPackOptions() { + return type == BuiltinOptions_PackOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::PackOptionsT *AsPackOptions() const { + return type == BuiltinOptions_PackOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LogicalOrOptionsT *AsLogicalOrOptions() { + return type == BuiltinOptions_LogicalOrOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LogicalOrOptionsT *AsLogicalOrOptions() const { + return type == BuiltinOptions_LogicalOrOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::OneHotOptionsT *AsOneHotOptions() { + return type == BuiltinOptions_OneHotOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::OneHotOptionsT *AsOneHotOptions() const { + return type == BuiltinOptions_OneHotOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LogicalAndOptionsT *AsLogicalAndOptions() { + return type == BuiltinOptions_LogicalAndOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LogicalAndOptionsT *AsLogicalAndOptions() const { + return type == BuiltinOptions_LogicalAndOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LogicalNotOptionsT *AsLogicalNotOptions() { + return type == BuiltinOptions_LogicalNotOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LogicalNotOptionsT *AsLogicalNotOptions() const { + return type == BuiltinOptions_LogicalNotOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::UnpackOptionsT *AsUnpackOptions() { + return type == BuiltinOptions_UnpackOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::UnpackOptionsT *AsUnpackOptions() const { + return type == BuiltinOptions_UnpackOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::FloorDivOptionsT *AsFloorDivOptions() { + return type == BuiltinOptions_FloorDivOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::FloorDivOptionsT *AsFloorDivOptions() const { + return type == BuiltinOptions_FloorDivOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SquareOptionsT *AsSquareOptions() { + return type == BuiltinOptions_SquareOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SquareOptionsT *AsSquareOptions() const { + return type == BuiltinOptions_SquareOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ZerosLikeOptionsT *AsZerosLikeOptions() { + return type == BuiltinOptions_ZerosLikeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ZerosLikeOptionsT *AsZerosLikeOptions() const { + return type == BuiltinOptions_ZerosLikeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::FillOptionsT *AsFillOptions() { + return type == BuiltinOptions_FillOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::FillOptionsT *AsFillOptions() const { + return type == BuiltinOptions_FillOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::BidirectionalSequenceLSTMOptionsT *AsBidirectionalSequenceLSTMOptions() { + return type == BuiltinOptions_BidirectionalSequenceLSTMOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::BidirectionalSequenceLSTMOptionsT *AsBidirectionalSequenceLSTMOptions() const { + return type == BuiltinOptions_BidirectionalSequenceLSTMOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::BidirectionalSequenceRNNOptionsT *AsBidirectionalSequenceRNNOptions() { + return type == BuiltinOptions_BidirectionalSequenceRNNOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::BidirectionalSequenceRNNOptionsT *AsBidirectionalSequenceRNNOptions() const { + return type == BuiltinOptions_BidirectionalSequenceRNNOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::UnidirectionalSequenceLSTMOptionsT *AsUnidirectionalSequenceLSTMOptions() { + return type == BuiltinOptions_UnidirectionalSequenceLSTMOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::UnidirectionalSequenceLSTMOptionsT *AsUnidirectionalSequenceLSTMOptions() const { + return type == BuiltinOptions_UnidirectionalSequenceLSTMOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::FloorModOptionsT *AsFloorModOptions() { + return type == BuiltinOptions_FloorModOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::FloorModOptionsT *AsFloorModOptions() const { + return type == BuiltinOptions_FloorModOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::RangeOptionsT *AsRangeOptions() { + return type == BuiltinOptions_RangeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::RangeOptionsT *AsRangeOptions() const { + return type == BuiltinOptions_RangeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ResizeNearestNeighborOptionsT *AsResizeNearestNeighborOptions() { + return type == BuiltinOptions_ResizeNearestNeighborOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ResizeNearestNeighborOptionsT *AsResizeNearestNeighborOptions() const { + return type == BuiltinOptions_ResizeNearestNeighborOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::LeakyReluOptionsT *AsLeakyReluOptions() { + return type == BuiltinOptions_LeakyReluOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::LeakyReluOptionsT *AsLeakyReluOptions() const { + return type == BuiltinOptions_LeakyReluOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SquaredDifferenceOptionsT *AsSquaredDifferenceOptions() { + return type == BuiltinOptions_SquaredDifferenceOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SquaredDifferenceOptionsT *AsSquaredDifferenceOptions() const { + return type == BuiltinOptions_SquaredDifferenceOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::MirrorPadOptionsT *AsMirrorPadOptions() { + return type == BuiltinOptions_MirrorPadOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::MirrorPadOptionsT *AsMirrorPadOptions() const { + return type == BuiltinOptions_MirrorPadOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::AbsOptionsT *AsAbsOptions() { + return type == BuiltinOptions_AbsOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::AbsOptionsT *AsAbsOptions() const { + return type == BuiltinOptions_AbsOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SplitVOptionsT *AsSplitVOptions() { + return type == BuiltinOptions_SplitVOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SplitVOptionsT *AsSplitVOptions() const { + return type == BuiltinOptions_SplitVOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::UniqueOptionsT *AsUniqueOptions() { + return type == BuiltinOptions_UniqueOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::UniqueOptionsT *AsUniqueOptions() const { + return type == BuiltinOptions_UniqueOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ReverseV2OptionsT *AsReverseV2Options() { + return type == BuiltinOptions_ReverseV2Options ? + reinterpret_cast(value) : nullptr; + } + const tflite::ReverseV2OptionsT *AsReverseV2Options() const { + return type == BuiltinOptions_ReverseV2Options ? + reinterpret_cast(value) : nullptr; + } + tflite::AddNOptionsT *AsAddNOptions() { + return type == BuiltinOptions_AddNOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::AddNOptionsT *AsAddNOptions() const { + return type == BuiltinOptions_AddNOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::GatherNdOptionsT *AsGatherNdOptions() { + return type == BuiltinOptions_GatherNdOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::GatherNdOptionsT *AsGatherNdOptions() const { + return type == BuiltinOptions_GatherNdOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::CosOptionsT *AsCosOptions() { + return type == BuiltinOptions_CosOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::CosOptionsT *AsCosOptions() const { + return type == BuiltinOptions_CosOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::WhereOptionsT *AsWhereOptions() { + return type == BuiltinOptions_WhereOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::WhereOptionsT *AsWhereOptions() const { + return type == BuiltinOptions_WhereOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::RankOptionsT *AsRankOptions() { + return type == BuiltinOptions_RankOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::RankOptionsT *AsRankOptions() const { + return type == BuiltinOptions_RankOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ReverseSequenceOptionsT *AsReverseSequenceOptions() { + return type == BuiltinOptions_ReverseSequenceOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ReverseSequenceOptionsT *AsReverseSequenceOptions() const { + return type == BuiltinOptions_ReverseSequenceOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::MatrixDiagOptionsT *AsMatrixDiagOptions() { + return type == BuiltinOptions_MatrixDiagOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::MatrixDiagOptionsT *AsMatrixDiagOptions() const { + return type == BuiltinOptions_MatrixDiagOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::QuantizeOptionsT *AsQuantizeOptions() { + return type == BuiltinOptions_QuantizeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::QuantizeOptionsT *AsQuantizeOptions() const { + return type == BuiltinOptions_QuantizeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::MatrixSetDiagOptionsT *AsMatrixSetDiagOptions() { + return type == BuiltinOptions_MatrixSetDiagOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::MatrixSetDiagOptionsT *AsMatrixSetDiagOptions() const { + return type == BuiltinOptions_MatrixSetDiagOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::HardSwishOptionsT *AsHardSwishOptions() { + return type == BuiltinOptions_HardSwishOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::HardSwishOptionsT *AsHardSwishOptions() const { + return type == BuiltinOptions_HardSwishOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::IfOptionsT *AsIfOptions() { + return type == BuiltinOptions_IfOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::IfOptionsT *AsIfOptions() const { + return type == BuiltinOptions_IfOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::WhileOptionsT *AsWhileOptions() { + return type == BuiltinOptions_WhileOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::WhileOptionsT *AsWhileOptions() const { + return type == BuiltinOptions_WhileOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::DepthToSpaceOptionsT *AsDepthToSpaceOptions() { + return type == BuiltinOptions_DepthToSpaceOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::DepthToSpaceOptionsT *AsDepthToSpaceOptions() const { + return type == BuiltinOptions_DepthToSpaceOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::NonMaxSuppressionV4OptionsT *AsNonMaxSuppressionV4Options() { + return type == BuiltinOptions_NonMaxSuppressionV4Options ? + reinterpret_cast(value) : nullptr; + } + const tflite::NonMaxSuppressionV4OptionsT *AsNonMaxSuppressionV4Options() const { + return type == BuiltinOptions_NonMaxSuppressionV4Options ? + reinterpret_cast(value) : nullptr; + } + tflite::NonMaxSuppressionV5OptionsT *AsNonMaxSuppressionV5Options() { + return type == BuiltinOptions_NonMaxSuppressionV5Options ? + reinterpret_cast(value) : nullptr; + } + const tflite::NonMaxSuppressionV5OptionsT *AsNonMaxSuppressionV5Options() const { + return type == BuiltinOptions_NonMaxSuppressionV5Options ? + reinterpret_cast(value) : nullptr; + } + tflite::ScatterNdOptionsT *AsScatterNdOptions() { + return type == BuiltinOptions_ScatterNdOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ScatterNdOptionsT *AsScatterNdOptions() const { + return type == BuiltinOptions_ScatterNdOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SelectV2OptionsT *AsSelectV2Options() { + return type == BuiltinOptions_SelectV2Options ? + reinterpret_cast(value) : nullptr; + } + const tflite::SelectV2OptionsT *AsSelectV2Options() const { + return type == BuiltinOptions_SelectV2Options ? + reinterpret_cast(value) : nullptr; + } + tflite::DensifyOptionsT *AsDensifyOptions() { + return type == BuiltinOptions_DensifyOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::DensifyOptionsT *AsDensifyOptions() const { + return type == BuiltinOptions_DensifyOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::SegmentSumOptionsT *AsSegmentSumOptions() { + return type == BuiltinOptions_SegmentSumOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SegmentSumOptionsT *AsSegmentSumOptions() const { + return type == BuiltinOptions_SegmentSumOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::BatchMatMulOptionsT *AsBatchMatMulOptions() { + return type == BuiltinOptions_BatchMatMulOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::BatchMatMulOptionsT *AsBatchMatMulOptions() const { + return type == BuiltinOptions_BatchMatMulOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::CumsumOptionsT *AsCumsumOptions() { + return type == BuiltinOptions_CumsumOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::CumsumOptionsT *AsCumsumOptions() const { + return type == BuiltinOptions_CumsumOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::CallOnceOptionsT *AsCallOnceOptions() { + return type == BuiltinOptions_CallOnceOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::CallOnceOptionsT *AsCallOnceOptions() const { + return type == BuiltinOptions_CallOnceOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::BroadcastToOptionsT *AsBroadcastToOptions() { + return type == BuiltinOptions_BroadcastToOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::BroadcastToOptionsT *AsBroadcastToOptions() const { + return type == BuiltinOptions_BroadcastToOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::Rfft2dOptionsT *AsRfft2dOptions() { + return type == BuiltinOptions_Rfft2dOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::Rfft2dOptionsT *AsRfft2dOptions() const { + return type == BuiltinOptions_Rfft2dOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::Conv3DOptionsT *AsConv3DOptions() { + return type == BuiltinOptions_Conv3DOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::Conv3DOptionsT *AsConv3DOptions() const { + return type == BuiltinOptions_Conv3DOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::HashtableOptionsT *AsHashtableOptions() { + return type == BuiltinOptions_HashtableOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::HashtableOptionsT *AsHashtableOptions() const { + return type == BuiltinOptions_HashtableOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::HashtableFindOptionsT *AsHashtableFindOptions() { + return type == BuiltinOptions_HashtableFindOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::HashtableFindOptionsT *AsHashtableFindOptions() const { + return type == BuiltinOptions_HashtableFindOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::HashtableImportOptionsT *AsHashtableImportOptions() { + return type == BuiltinOptions_HashtableImportOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::HashtableImportOptionsT *AsHashtableImportOptions() const { + return type == BuiltinOptions_HashtableImportOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::HashtableSizeOptionsT *AsHashtableSizeOptions() { + return type == BuiltinOptions_HashtableSizeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::HashtableSizeOptionsT *AsHashtableSizeOptions() const { + return type == BuiltinOptions_HashtableSizeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::VarHandleOptionsT *AsVarHandleOptions() { + return type == BuiltinOptions_VarHandleOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::VarHandleOptionsT *AsVarHandleOptions() const { + return type == BuiltinOptions_VarHandleOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ReadVariableOptionsT *AsReadVariableOptions() { + return type == BuiltinOptions_ReadVariableOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::ReadVariableOptionsT *AsReadVariableOptions() const { + return type == BuiltinOptions_ReadVariableOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::AssignVariableOptionsT *AsAssignVariableOptions() { + return type == BuiltinOptions_AssignVariableOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::AssignVariableOptionsT *AsAssignVariableOptions() const { + return type == BuiltinOptions_AssignVariableOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::RandomOptionsT *AsRandomOptions() { + return type == BuiltinOptions_RandomOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::RandomOptionsT *AsRandomOptions() const { + return type == BuiltinOptions_RandomOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::BucketizeOptionsT *AsBucketizeOptions() { + return type == BuiltinOptions_BucketizeOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::BucketizeOptionsT *AsBucketizeOptions() const { + return type == BuiltinOptions_BucketizeOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::GeluOptionsT *AsGeluOptions() { + return type == BuiltinOptions_GeluOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::GeluOptionsT *AsGeluOptions() const { + return type == BuiltinOptions_GeluOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::DynamicUpdateSliceOptionsT *AsDynamicUpdateSliceOptions() { + return type == BuiltinOptions_DynamicUpdateSliceOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::DynamicUpdateSliceOptionsT *AsDynamicUpdateSliceOptions() const { + return type == BuiltinOptions_DynamicUpdateSliceOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::UnsortedSegmentProdOptionsT *AsUnsortedSegmentProdOptions() { + return type == BuiltinOptions_UnsortedSegmentProdOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::UnsortedSegmentProdOptionsT *AsUnsortedSegmentProdOptions() const { + return type == BuiltinOptions_UnsortedSegmentProdOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::UnsortedSegmentMaxOptionsT *AsUnsortedSegmentMaxOptions() { + return type == BuiltinOptions_UnsortedSegmentMaxOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::UnsortedSegmentMaxOptionsT *AsUnsortedSegmentMaxOptions() const { + return type == BuiltinOptions_UnsortedSegmentMaxOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::UnsortedSegmentMinOptionsT *AsUnsortedSegmentMinOptions() { + return type == BuiltinOptions_UnsortedSegmentMinOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::UnsortedSegmentMinOptionsT *AsUnsortedSegmentMinOptions() const { + return type == BuiltinOptions_UnsortedSegmentMinOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::UnsortedSegmentSumOptionsT *AsUnsortedSegmentSumOptions() { + return type == BuiltinOptions_UnsortedSegmentSumOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::UnsortedSegmentSumOptionsT *AsUnsortedSegmentSumOptions() const { + return type == BuiltinOptions_UnsortedSegmentSumOptions ? + reinterpret_cast(value) : nullptr; + } + tflite::ATan2OptionsT *AsATan2Options() { + return type == BuiltinOptions_ATan2Options ? + reinterpret_cast(value) : nullptr; + } + const tflite::ATan2OptionsT *AsATan2Options() const { + return type == BuiltinOptions_ATan2Options ? + reinterpret_cast(value) : nullptr; + } + tflite::SignOptionsT *AsSignOptions() { + return type == BuiltinOptions_SignOptions ? + reinterpret_cast(value) : nullptr; + } + const tflite::SignOptionsT *AsSignOptions() const { + return type == BuiltinOptions_SignOptions ? + reinterpret_cast(value) : nullptr; + } +}; + +bool VerifyBuiltinOptions(flatbuffers::Verifier &verifier, const void *obj, BuiltinOptions type); +bool VerifyBuiltinOptionsVector(flatbuffers::Verifier &verifier, const flatbuffers::Vector> *values, const flatbuffers::Vector *types); + +enum Padding : int8_t { + Padding_SAME = 0, + Padding_VALID = 1, + Padding_MIN = Padding_SAME, + Padding_MAX = Padding_VALID +}; + +inline const Padding (&EnumValuesPadding())[2] { + static const Padding values[] = { + Padding_SAME, + Padding_VALID + }; + return values; +} + +inline const char * const *EnumNamesPadding() { + static const char * const names[3] = { + "SAME", + "VALID", + nullptr + }; + return names; +} + +inline const char *EnumNamePadding(Padding e) { + if (flatbuffers::IsOutRange(e, Padding_SAME, Padding_VALID)) return ""; + const size_t index = static_cast(e); + return EnumNamesPadding()[index]; +} + +enum ActivationFunctionType : int8_t { + ActivationFunctionType_NONE = 0, + ActivationFunctionType_RELU = 1, + ActivationFunctionType_RELU_N1_TO_1 = 2, + ActivationFunctionType_RELU6 = 3, + ActivationFunctionType_TANH = 4, + ActivationFunctionType_SIGN_BIT = 5, + ActivationFunctionType_MIN = ActivationFunctionType_NONE, + ActivationFunctionType_MAX = ActivationFunctionType_SIGN_BIT +}; + +inline const ActivationFunctionType (&EnumValuesActivationFunctionType())[6] { + static const ActivationFunctionType values[] = { + ActivationFunctionType_NONE, + ActivationFunctionType_RELU, + ActivationFunctionType_RELU_N1_TO_1, + ActivationFunctionType_RELU6, + ActivationFunctionType_TANH, + ActivationFunctionType_SIGN_BIT + }; + return values; +} + +inline const char * const *EnumNamesActivationFunctionType() { + static const char * const names[7] = { + "NONE", + "RELU", + "RELU_N1_TO_1", + "RELU6", + "TANH", + "SIGN_BIT", + nullptr + }; + return names; +} + +inline const char *EnumNameActivationFunctionType(ActivationFunctionType e) { + if (flatbuffers::IsOutRange(e, ActivationFunctionType_NONE, ActivationFunctionType_SIGN_BIT)) return ""; + const size_t index = static_cast(e); + return EnumNamesActivationFunctionType()[index]; +} + +enum LSHProjectionType : int8_t { + LSHProjectionType_UNKNOWN = 0, + LSHProjectionType_SPARSE = 1, + LSHProjectionType_DENSE = 2, + LSHProjectionType_MIN = LSHProjectionType_UNKNOWN, + LSHProjectionType_MAX = LSHProjectionType_DENSE +}; + +inline const LSHProjectionType (&EnumValuesLSHProjectionType())[3] { + static const LSHProjectionType values[] = { + LSHProjectionType_UNKNOWN, + LSHProjectionType_SPARSE, + LSHProjectionType_DENSE + }; + return values; +} + +inline const char * const *EnumNamesLSHProjectionType() { + static const char * const names[4] = { + "UNKNOWN", + "SPARSE", + "DENSE", + nullptr + }; + return names; +} + +inline const char *EnumNameLSHProjectionType(LSHProjectionType e) { + if (flatbuffers::IsOutRange(e, LSHProjectionType_UNKNOWN, LSHProjectionType_DENSE)) return ""; + const size_t index = static_cast(e); + return EnumNamesLSHProjectionType()[index]; +} + +enum FullyConnectedOptionsWeightsFormat : int8_t { + FullyConnectedOptionsWeightsFormat_DEFAULT = 0, + FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8 = 1, + FullyConnectedOptionsWeightsFormat_MIN = FullyConnectedOptionsWeightsFormat_DEFAULT, + FullyConnectedOptionsWeightsFormat_MAX = FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8 +}; + +inline const FullyConnectedOptionsWeightsFormat (&EnumValuesFullyConnectedOptionsWeightsFormat())[2] { + static const FullyConnectedOptionsWeightsFormat values[] = { + FullyConnectedOptionsWeightsFormat_DEFAULT, + FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8 + }; + return values; +} + +inline const char * const *EnumNamesFullyConnectedOptionsWeightsFormat() { + static const char * const names[3] = { + "DEFAULT", + "SHUFFLED4x16INT8", + nullptr + }; + return names; +} + +inline const char *EnumNameFullyConnectedOptionsWeightsFormat(FullyConnectedOptionsWeightsFormat e) { + if (flatbuffers::IsOutRange(e, FullyConnectedOptionsWeightsFormat_DEFAULT, FullyConnectedOptionsWeightsFormat_SHUFFLED4x16INT8)) return ""; + const size_t index = static_cast(e); + return EnumNamesFullyConnectedOptionsWeightsFormat()[index]; +} + +enum LSTMKernelType : int8_t { + LSTMKernelType_FULL = 0, + LSTMKernelType_BASIC = 1, + LSTMKernelType_MIN = LSTMKernelType_FULL, + LSTMKernelType_MAX = LSTMKernelType_BASIC +}; + +inline const LSTMKernelType (&EnumValuesLSTMKernelType())[2] { + static const LSTMKernelType values[] = { + LSTMKernelType_FULL, + LSTMKernelType_BASIC + }; + return values; +} + +inline const char * const *EnumNamesLSTMKernelType() { + static const char * const names[3] = { + "FULL", + "BASIC", + nullptr + }; + return names; +} + +inline const char *EnumNameLSTMKernelType(LSTMKernelType e) { + if (flatbuffers::IsOutRange(e, LSTMKernelType_FULL, LSTMKernelType_BASIC)) return ""; + const size_t index = static_cast(e); + return EnumNamesLSTMKernelType()[index]; +} + +enum CombinerType : int8_t { + CombinerType_SUM = 0, + CombinerType_MEAN = 1, + CombinerType_SQRTN = 2, + CombinerType_MIN = CombinerType_SUM, + CombinerType_MAX = CombinerType_SQRTN +}; + +inline const CombinerType (&EnumValuesCombinerType())[3] { + static const CombinerType values[] = { + CombinerType_SUM, + CombinerType_MEAN, + CombinerType_SQRTN + }; + return values; +} + +inline const char * const *EnumNamesCombinerType() { + static const char * const names[4] = { + "SUM", + "MEAN", + "SQRTN", + nullptr + }; + return names; +} + +inline const char *EnumNameCombinerType(CombinerType e) { + if (flatbuffers::IsOutRange(e, CombinerType_SUM, CombinerType_SQRTN)) return ""; + const size_t index = static_cast(e); + return EnumNamesCombinerType()[index]; +} + +enum MirrorPadMode : int8_t { + MirrorPadMode_REFLECT = 0, + MirrorPadMode_SYMMETRIC = 1, + MirrorPadMode_MIN = MirrorPadMode_REFLECT, + MirrorPadMode_MAX = MirrorPadMode_SYMMETRIC +}; + +inline const MirrorPadMode (&EnumValuesMirrorPadMode())[2] { + static const MirrorPadMode values[] = { + MirrorPadMode_REFLECT, + MirrorPadMode_SYMMETRIC + }; + return values; +} + +inline const char * const *EnumNamesMirrorPadMode() { + static const char * const names[3] = { + "REFLECT", + "SYMMETRIC", + nullptr + }; + return names; +} + +inline const char *EnumNameMirrorPadMode(MirrorPadMode e) { + if (flatbuffers::IsOutRange(e, MirrorPadMode_REFLECT, MirrorPadMode_SYMMETRIC)) return ""; + const size_t index = static_cast(e); + return EnumNamesMirrorPadMode()[index]; +} + +enum CustomOptionsFormat : int8_t { + CustomOptionsFormat_FLEXBUFFERS = 0, + CustomOptionsFormat_MIN = CustomOptionsFormat_FLEXBUFFERS, + CustomOptionsFormat_MAX = CustomOptionsFormat_FLEXBUFFERS +}; + +inline const CustomOptionsFormat (&EnumValuesCustomOptionsFormat())[1] { + static const CustomOptionsFormat values[] = { + CustomOptionsFormat_FLEXBUFFERS + }; + return values; +} + +inline const char * const *EnumNamesCustomOptionsFormat() { + static const char * const names[2] = { + "FLEXBUFFERS", + nullptr + }; + return names; +} + +inline const char *EnumNameCustomOptionsFormat(CustomOptionsFormat e) { + if (flatbuffers::IsOutRange(e, CustomOptionsFormat_FLEXBUFFERS, CustomOptionsFormat_FLEXBUFFERS)) return ""; + const size_t index = static_cast(e); + return EnumNamesCustomOptionsFormat()[index]; +} + +struct CustomQuantizationT : public flatbuffers::NativeTable { + typedef CustomQuantization TableType; + std::vector custom{}; +}; + +struct CustomQuantization FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef CustomQuantizationT NativeTableType; + typedef CustomQuantizationBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_CUSTOM = 4 + }; + const flatbuffers::Vector *custom() const { + return GetPointer *>(VT_CUSTOM); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_CUSTOM) && + verifier.VerifyVector(custom()) && + verifier.EndTable(); + } + CustomQuantizationT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(CustomQuantizationT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const CustomQuantizationT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct CustomQuantizationBuilder { + typedef CustomQuantization Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_custom(flatbuffers::Offset> custom) { + fbb_.AddOffset(CustomQuantization::VT_CUSTOM, custom); + } + explicit CustomQuantizationBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateCustomQuantization( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> custom = 0) { + CustomQuantizationBuilder builder_(_fbb); + builder_.add_custom(custom); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateCustomQuantizationDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *custom = nullptr) { + if (custom) { _fbb.ForceVectorAlignment(custom->size(), sizeof(uint8_t), 16); } + auto custom__ = custom ? _fbb.CreateVector(*custom) : 0; + return tflite::CreateCustomQuantization( + _fbb, + custom__); +} + +flatbuffers::Offset CreateCustomQuantization(flatbuffers::FlatBufferBuilder &_fbb, const CustomQuantizationT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct QuantizationParametersT : public flatbuffers::NativeTable { + typedef QuantizationParameters TableType; + std::vector min{}; + std::vector max{}; + std::vector scale{}; + std::vector zero_point{}; + tflite::QuantizationDetailsUnion details{}; + int32_t quantized_dimension = 0; +}; + +struct QuantizationParameters FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef QuantizationParametersT NativeTableType; + typedef QuantizationParametersBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_MIN = 4, + VT_MAX = 6, + VT_SCALE = 8, + VT_ZERO_POINT = 10, + VT_DETAILS_TYPE = 12, + VT_DETAILS = 14, + VT_QUANTIZED_DIMENSION = 16 + }; + const flatbuffers::Vector *min() const { + return GetPointer *>(VT_MIN); + } + const flatbuffers::Vector *max() const { + return GetPointer *>(VT_MAX); + } + const flatbuffers::Vector *scale() const { + return GetPointer *>(VT_SCALE); + } + const flatbuffers::Vector *zero_point() const { + return GetPointer *>(VT_ZERO_POINT); + } + tflite::QuantizationDetails details_type() const { + return static_cast(GetField(VT_DETAILS_TYPE, 0)); + } + const void *details() const { + return GetPointer(VT_DETAILS); + } + template const T *details_as() const; + const tflite::CustomQuantization *details_as_CustomQuantization() const { + return details_type() == tflite::QuantizationDetails_CustomQuantization ? static_cast(details()) : nullptr; + } + int32_t quantized_dimension() const { + return GetField(VT_QUANTIZED_DIMENSION, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_MIN) && + verifier.VerifyVector(min()) && + VerifyOffset(verifier, VT_MAX) && + verifier.VerifyVector(max()) && + VerifyOffset(verifier, VT_SCALE) && + verifier.VerifyVector(scale()) && + VerifyOffset(verifier, VT_ZERO_POINT) && + verifier.VerifyVector(zero_point()) && + VerifyField(verifier, VT_DETAILS_TYPE, 1) && + VerifyOffset(verifier, VT_DETAILS) && + VerifyQuantizationDetails(verifier, details(), details_type()) && + VerifyField(verifier, VT_QUANTIZED_DIMENSION, 4) && + verifier.EndTable(); + } + QuantizationParametersT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(QuantizationParametersT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const QuantizationParametersT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +template<> inline const tflite::CustomQuantization *QuantizationParameters::details_as() const { + return details_as_CustomQuantization(); +} + +struct QuantizationParametersBuilder { + typedef QuantizationParameters Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_min(flatbuffers::Offset> min) { + fbb_.AddOffset(QuantizationParameters::VT_MIN, min); + } + void add_max(flatbuffers::Offset> max) { + fbb_.AddOffset(QuantizationParameters::VT_MAX, max); + } + void add_scale(flatbuffers::Offset> scale) { + fbb_.AddOffset(QuantizationParameters::VT_SCALE, scale); + } + void add_zero_point(flatbuffers::Offset> zero_point) { + fbb_.AddOffset(QuantizationParameters::VT_ZERO_POINT, zero_point); + } + void add_details_type(tflite::QuantizationDetails details_type) { + fbb_.AddElement(QuantizationParameters::VT_DETAILS_TYPE, static_cast(details_type), 0); + } + void add_details(flatbuffers::Offset details) { + fbb_.AddOffset(QuantizationParameters::VT_DETAILS, details); + } + void add_quantized_dimension(int32_t quantized_dimension) { + fbb_.AddElement(QuantizationParameters::VT_QUANTIZED_DIMENSION, quantized_dimension, 0); + } + explicit QuantizationParametersBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateQuantizationParameters( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> min = 0, + flatbuffers::Offset> max = 0, + flatbuffers::Offset> scale = 0, + flatbuffers::Offset> zero_point = 0, + tflite::QuantizationDetails details_type = tflite::QuantizationDetails_NONE, + flatbuffers::Offset details = 0, + int32_t quantized_dimension = 0) { + QuantizationParametersBuilder builder_(_fbb); + builder_.add_quantized_dimension(quantized_dimension); + builder_.add_details(details); + builder_.add_zero_point(zero_point); + builder_.add_scale(scale); + builder_.add_max(max); + builder_.add_min(min); + builder_.add_details_type(details_type); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateQuantizationParametersDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *min = nullptr, + const std::vector *max = nullptr, + const std::vector *scale = nullptr, + const std::vector *zero_point = nullptr, + tflite::QuantizationDetails details_type = tflite::QuantizationDetails_NONE, + flatbuffers::Offset details = 0, + int32_t quantized_dimension = 0) { + auto min__ = min ? _fbb.CreateVector(*min) : 0; + auto max__ = max ? _fbb.CreateVector(*max) : 0; + auto scale__ = scale ? _fbb.CreateVector(*scale) : 0; + auto zero_point__ = zero_point ? _fbb.CreateVector(*zero_point) : 0; + return tflite::CreateQuantizationParameters( + _fbb, + min__, + max__, + scale__, + zero_point__, + details_type, + details, + quantized_dimension); +} + +flatbuffers::Offset CreateQuantizationParameters(flatbuffers::FlatBufferBuilder &_fbb, const QuantizationParametersT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct Int32VectorT : public flatbuffers::NativeTable { + typedef Int32Vector TableType; + std::vector values{}; +}; + +struct Int32Vector FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef Int32VectorT NativeTableType; + typedef Int32VectorBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_VALUES = 4 + }; + const flatbuffers::Vector *values() const { + return GetPointer *>(VT_VALUES); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_VALUES) && + verifier.VerifyVector(values()) && + verifier.EndTable(); + } + Int32VectorT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(Int32VectorT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const Int32VectorT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct Int32VectorBuilder { + typedef Int32Vector Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_values(flatbuffers::Offset> values) { + fbb_.AddOffset(Int32Vector::VT_VALUES, values); + } + explicit Int32VectorBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateInt32Vector( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> values = 0) { + Int32VectorBuilder builder_(_fbb); + builder_.add_values(values); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateInt32VectorDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *values = nullptr) { + auto values__ = values ? _fbb.CreateVector(*values) : 0; + return tflite::CreateInt32Vector( + _fbb, + values__); +} + +flatbuffers::Offset CreateInt32Vector(flatbuffers::FlatBufferBuilder &_fbb, const Int32VectorT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct Uint16VectorT : public flatbuffers::NativeTable { + typedef Uint16Vector TableType; + std::vector values{}; +}; + +struct Uint16Vector FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef Uint16VectorT NativeTableType; + typedef Uint16VectorBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_VALUES = 4 + }; + const flatbuffers::Vector *values() const { + return GetPointer *>(VT_VALUES); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_VALUES) && + verifier.VerifyVector(values()) && + verifier.EndTable(); + } + Uint16VectorT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(Uint16VectorT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const Uint16VectorT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct Uint16VectorBuilder { + typedef Uint16Vector Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_values(flatbuffers::Offset> values) { + fbb_.AddOffset(Uint16Vector::VT_VALUES, values); + } + explicit Uint16VectorBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUint16Vector( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> values = 0) { + Uint16VectorBuilder builder_(_fbb); + builder_.add_values(values); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateUint16VectorDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *values = nullptr) { + if (values) { _fbb.ForceVectorAlignment(values->size(), sizeof(uint16_t), 4); } + auto values__ = values ? _fbb.CreateVector(*values) : 0; + return tflite::CreateUint16Vector( + _fbb, + values__); +} + +flatbuffers::Offset CreateUint16Vector(flatbuffers::FlatBufferBuilder &_fbb, const Uint16VectorT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct Uint8VectorT : public flatbuffers::NativeTable { + typedef Uint8Vector TableType; + std::vector values{}; +}; + +struct Uint8Vector FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef Uint8VectorT NativeTableType; + typedef Uint8VectorBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_VALUES = 4 + }; + const flatbuffers::Vector *values() const { + return GetPointer *>(VT_VALUES); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_VALUES) && + verifier.VerifyVector(values()) && + verifier.EndTable(); + } + Uint8VectorT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(Uint8VectorT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const Uint8VectorT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct Uint8VectorBuilder { + typedef Uint8Vector Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_values(flatbuffers::Offset> values) { + fbb_.AddOffset(Uint8Vector::VT_VALUES, values); + } + explicit Uint8VectorBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUint8Vector( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> values = 0) { + Uint8VectorBuilder builder_(_fbb); + builder_.add_values(values); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateUint8VectorDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *values = nullptr) { + if (values) { _fbb.ForceVectorAlignment(values->size(), sizeof(uint8_t), 4); } + auto values__ = values ? _fbb.CreateVector(*values) : 0; + return tflite::CreateUint8Vector( + _fbb, + values__); +} + +flatbuffers::Offset CreateUint8Vector(flatbuffers::FlatBufferBuilder &_fbb, const Uint8VectorT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct DimensionMetadataT : public flatbuffers::NativeTable { + typedef DimensionMetadata TableType; + tflite::DimensionType format = tflite::DimensionType_DENSE; + int32_t dense_size = 0; + tflite::SparseIndexVectorUnion array_segments{}; + tflite::SparseIndexVectorUnion array_indices{}; +}; + +struct DimensionMetadata FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef DimensionMetadataT NativeTableType; + typedef DimensionMetadataBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FORMAT = 4, + VT_DENSE_SIZE = 6, + VT_ARRAY_SEGMENTS_TYPE = 8, + VT_ARRAY_SEGMENTS = 10, + VT_ARRAY_INDICES_TYPE = 12, + VT_ARRAY_INDICES = 14 + }; + tflite::DimensionType format() const { + return static_cast(GetField(VT_FORMAT, 0)); + } + int32_t dense_size() const { + return GetField(VT_DENSE_SIZE, 0); + } + tflite::SparseIndexVector array_segments_type() const { + return static_cast(GetField(VT_ARRAY_SEGMENTS_TYPE, 0)); + } + const void *array_segments() const { + return GetPointer(VT_ARRAY_SEGMENTS); + } + template const T *array_segments_as() const; + const tflite::Int32Vector *array_segments_as_Int32Vector() const { + return array_segments_type() == tflite::SparseIndexVector_Int32Vector ? static_cast(array_segments()) : nullptr; + } + const tflite::Uint16Vector *array_segments_as_Uint16Vector() const { + return array_segments_type() == tflite::SparseIndexVector_Uint16Vector ? static_cast(array_segments()) : nullptr; + } + const tflite::Uint8Vector *array_segments_as_Uint8Vector() const { + return array_segments_type() == tflite::SparseIndexVector_Uint8Vector ? static_cast(array_segments()) : nullptr; + } + tflite::SparseIndexVector array_indices_type() const { + return static_cast(GetField(VT_ARRAY_INDICES_TYPE, 0)); + } + const void *array_indices() const { + return GetPointer(VT_ARRAY_INDICES); + } + template const T *array_indices_as() const; + const tflite::Int32Vector *array_indices_as_Int32Vector() const { + return array_indices_type() == tflite::SparseIndexVector_Int32Vector ? static_cast(array_indices()) : nullptr; + } + const tflite::Uint16Vector *array_indices_as_Uint16Vector() const { + return array_indices_type() == tflite::SparseIndexVector_Uint16Vector ? static_cast(array_indices()) : nullptr; + } + const tflite::Uint8Vector *array_indices_as_Uint8Vector() const { + return array_indices_type() == tflite::SparseIndexVector_Uint8Vector ? static_cast(array_indices()) : nullptr; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FORMAT, 1) && + VerifyField(verifier, VT_DENSE_SIZE, 4) && + VerifyField(verifier, VT_ARRAY_SEGMENTS_TYPE, 1) && + VerifyOffset(verifier, VT_ARRAY_SEGMENTS) && + VerifySparseIndexVector(verifier, array_segments(), array_segments_type()) && + VerifyField(verifier, VT_ARRAY_INDICES_TYPE, 1) && + VerifyOffset(verifier, VT_ARRAY_INDICES) && + VerifySparseIndexVector(verifier, array_indices(), array_indices_type()) && + verifier.EndTable(); + } + DimensionMetadataT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(DimensionMetadataT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const DimensionMetadataT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +template<> inline const tflite::Int32Vector *DimensionMetadata::array_segments_as() const { + return array_segments_as_Int32Vector(); +} + +template<> inline const tflite::Uint16Vector *DimensionMetadata::array_segments_as() const { + return array_segments_as_Uint16Vector(); +} + +template<> inline const tflite::Uint8Vector *DimensionMetadata::array_segments_as() const { + return array_segments_as_Uint8Vector(); +} + +template<> inline const tflite::Int32Vector *DimensionMetadata::array_indices_as() const { + return array_indices_as_Int32Vector(); +} + +template<> inline const tflite::Uint16Vector *DimensionMetadata::array_indices_as() const { + return array_indices_as_Uint16Vector(); +} + +template<> inline const tflite::Uint8Vector *DimensionMetadata::array_indices_as() const { + return array_indices_as_Uint8Vector(); +} + +struct DimensionMetadataBuilder { + typedef DimensionMetadata Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_format(tflite::DimensionType format) { + fbb_.AddElement(DimensionMetadata::VT_FORMAT, static_cast(format), 0); + } + void add_dense_size(int32_t dense_size) { + fbb_.AddElement(DimensionMetadata::VT_DENSE_SIZE, dense_size, 0); + } + void add_array_segments_type(tflite::SparseIndexVector array_segments_type) { + fbb_.AddElement(DimensionMetadata::VT_ARRAY_SEGMENTS_TYPE, static_cast(array_segments_type), 0); + } + void add_array_segments(flatbuffers::Offset array_segments) { + fbb_.AddOffset(DimensionMetadata::VT_ARRAY_SEGMENTS, array_segments); + } + void add_array_indices_type(tflite::SparseIndexVector array_indices_type) { + fbb_.AddElement(DimensionMetadata::VT_ARRAY_INDICES_TYPE, static_cast(array_indices_type), 0); + } + void add_array_indices(flatbuffers::Offset array_indices) { + fbb_.AddOffset(DimensionMetadata::VT_ARRAY_INDICES, array_indices); + } + explicit DimensionMetadataBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateDimensionMetadata( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::DimensionType format = tflite::DimensionType_DENSE, + int32_t dense_size = 0, + tflite::SparseIndexVector array_segments_type = tflite::SparseIndexVector_NONE, + flatbuffers::Offset array_segments = 0, + tflite::SparseIndexVector array_indices_type = tflite::SparseIndexVector_NONE, + flatbuffers::Offset array_indices = 0) { + DimensionMetadataBuilder builder_(_fbb); + builder_.add_array_indices(array_indices); + builder_.add_array_segments(array_segments); + builder_.add_dense_size(dense_size); + builder_.add_array_indices_type(array_indices_type); + builder_.add_array_segments_type(array_segments_type); + builder_.add_format(format); + return builder_.Finish(); +} + +flatbuffers::Offset CreateDimensionMetadata(flatbuffers::FlatBufferBuilder &_fbb, const DimensionMetadataT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SparsityParametersT : public flatbuffers::NativeTable { + typedef SparsityParameters TableType; + std::vector traversal_order{}; + std::vector block_map{}; + std::vector> dim_metadata{}; + SparsityParametersT() = default; + SparsityParametersT(const SparsityParametersT &o); + SparsityParametersT(SparsityParametersT&&) FLATBUFFERS_NOEXCEPT = default; + SparsityParametersT &operator=(SparsityParametersT o) FLATBUFFERS_NOEXCEPT; +}; + +struct SparsityParameters FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SparsityParametersT NativeTableType; + typedef SparsityParametersBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_TRAVERSAL_ORDER = 4, + VT_BLOCK_MAP = 6, + VT_DIM_METADATA = 8 + }; + const flatbuffers::Vector *traversal_order() const { + return GetPointer *>(VT_TRAVERSAL_ORDER); + } + const flatbuffers::Vector *block_map() const { + return GetPointer *>(VT_BLOCK_MAP); + } + const flatbuffers::Vector> *dim_metadata() const { + return GetPointer> *>(VT_DIM_METADATA); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_TRAVERSAL_ORDER) && + verifier.VerifyVector(traversal_order()) && + VerifyOffset(verifier, VT_BLOCK_MAP) && + verifier.VerifyVector(block_map()) && + VerifyOffset(verifier, VT_DIM_METADATA) && + verifier.VerifyVector(dim_metadata()) && + verifier.VerifyVectorOfTables(dim_metadata()) && + verifier.EndTable(); + } + SparsityParametersT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SparsityParametersT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SparsityParametersT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SparsityParametersBuilder { + typedef SparsityParameters Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_traversal_order(flatbuffers::Offset> traversal_order) { + fbb_.AddOffset(SparsityParameters::VT_TRAVERSAL_ORDER, traversal_order); + } + void add_block_map(flatbuffers::Offset> block_map) { + fbb_.AddOffset(SparsityParameters::VT_BLOCK_MAP, block_map); + } + void add_dim_metadata(flatbuffers::Offset>> dim_metadata) { + fbb_.AddOffset(SparsityParameters::VT_DIM_METADATA, dim_metadata); + } + explicit SparsityParametersBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSparsityParameters( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> traversal_order = 0, + flatbuffers::Offset> block_map = 0, + flatbuffers::Offset>> dim_metadata = 0) { + SparsityParametersBuilder builder_(_fbb); + builder_.add_dim_metadata(dim_metadata); + builder_.add_block_map(block_map); + builder_.add_traversal_order(traversal_order); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateSparsityParametersDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *traversal_order = nullptr, + const std::vector *block_map = nullptr, + const std::vector> *dim_metadata = nullptr) { + auto traversal_order__ = traversal_order ? _fbb.CreateVector(*traversal_order) : 0; + auto block_map__ = block_map ? _fbb.CreateVector(*block_map) : 0; + auto dim_metadata__ = dim_metadata ? _fbb.CreateVector>(*dim_metadata) : 0; + return tflite::CreateSparsityParameters( + _fbb, + traversal_order__, + block_map__, + dim_metadata__); +} + +flatbuffers::Offset CreateSparsityParameters(flatbuffers::FlatBufferBuilder &_fbb, const SparsityParametersT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct VariantSubTypeT : public flatbuffers::NativeTable { + typedef VariantSubType TableType; + std::vector shape{}; + tflite::TensorType type = tflite::TensorType_FLOAT32; + bool has_rank = false; +}; + +struct VariantSubType FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef VariantSubTypeT NativeTableType; + typedef VariantSubTypeBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_SHAPE = 4, + VT_TYPE = 6, + VT_HAS_RANK = 8 + }; + const flatbuffers::Vector *shape() const { + return GetPointer *>(VT_SHAPE); + } + tflite::TensorType type() const { + return static_cast(GetField(VT_TYPE, 0)); + } + bool has_rank() const { + return GetField(VT_HAS_RANK, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_SHAPE) && + verifier.VerifyVector(shape()) && + VerifyField(verifier, VT_TYPE, 1) && + VerifyField(verifier, VT_HAS_RANK, 1) && + verifier.EndTable(); + } + VariantSubTypeT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(VariantSubTypeT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const VariantSubTypeT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct VariantSubTypeBuilder { + typedef VariantSubType Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_shape(flatbuffers::Offset> shape) { + fbb_.AddOffset(VariantSubType::VT_SHAPE, shape); + } + void add_type(tflite::TensorType type) { + fbb_.AddElement(VariantSubType::VT_TYPE, static_cast(type), 0); + } + void add_has_rank(bool has_rank) { + fbb_.AddElement(VariantSubType::VT_HAS_RANK, static_cast(has_rank), 0); + } + explicit VariantSubTypeBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateVariantSubType( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> shape = 0, + tflite::TensorType type = tflite::TensorType_FLOAT32, + bool has_rank = false) { + VariantSubTypeBuilder builder_(_fbb); + builder_.add_shape(shape); + builder_.add_has_rank(has_rank); + builder_.add_type(type); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateVariantSubTypeDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *shape = nullptr, + tflite::TensorType type = tflite::TensorType_FLOAT32, + bool has_rank = false) { + auto shape__ = shape ? _fbb.CreateVector(*shape) : 0; + return tflite::CreateVariantSubType( + _fbb, + shape__, + type, + has_rank); +} + +flatbuffers::Offset CreateVariantSubType(flatbuffers::FlatBufferBuilder &_fbb, const VariantSubTypeT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct TensorT : public flatbuffers::NativeTable { + typedef Tensor TableType; + std::vector shape{}; + tflite::TensorType type = tflite::TensorType_FLOAT32; + uint32_t buffer = 0; + std::string name{}; + std::unique_ptr quantization{}; + bool is_variable = false; + std::unique_ptr sparsity{}; + std::vector shape_signature{}; + bool has_rank = false; + std::vector> variant_tensors{}; + TensorT() = default; + TensorT(const TensorT &o); + TensorT(TensorT&&) FLATBUFFERS_NOEXCEPT = default; + TensorT &operator=(TensorT o) FLATBUFFERS_NOEXCEPT; +}; + +struct Tensor FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef TensorT NativeTableType; + typedef TensorBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_SHAPE = 4, + VT_TYPE = 6, + VT_BUFFER = 8, + VT_NAME = 10, + VT_QUANTIZATION = 12, + VT_IS_VARIABLE = 14, + VT_SPARSITY = 16, + VT_SHAPE_SIGNATURE = 18, + VT_HAS_RANK = 20, + VT_VARIANT_TENSORS = 22 + }; + const flatbuffers::Vector *shape() const { + return GetPointer *>(VT_SHAPE); + } + tflite::TensorType type() const { + return static_cast(GetField(VT_TYPE, 0)); + } + uint32_t buffer() const { + return GetField(VT_BUFFER, 0); + } + const flatbuffers::String *name() const { + return GetPointer(VT_NAME); + } + const tflite::QuantizationParameters *quantization() const { + return GetPointer(VT_QUANTIZATION); + } + bool is_variable() const { + return GetField(VT_IS_VARIABLE, 0) != 0; + } + const tflite::SparsityParameters *sparsity() const { + return GetPointer(VT_SPARSITY); + } + const flatbuffers::Vector *shape_signature() const { + return GetPointer *>(VT_SHAPE_SIGNATURE); + } + bool has_rank() const { + return GetField(VT_HAS_RANK, 0) != 0; + } + const flatbuffers::Vector> *variant_tensors() const { + return GetPointer> *>(VT_VARIANT_TENSORS); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_SHAPE) && + verifier.VerifyVector(shape()) && + VerifyField(verifier, VT_TYPE, 1) && + VerifyField(verifier, VT_BUFFER, 4) && + VerifyOffset(verifier, VT_NAME) && + verifier.VerifyString(name()) && + VerifyOffset(verifier, VT_QUANTIZATION) && + verifier.VerifyTable(quantization()) && + VerifyField(verifier, VT_IS_VARIABLE, 1) && + VerifyOffset(verifier, VT_SPARSITY) && + verifier.VerifyTable(sparsity()) && + VerifyOffset(verifier, VT_SHAPE_SIGNATURE) && + verifier.VerifyVector(shape_signature()) && + VerifyField(verifier, VT_HAS_RANK, 1) && + VerifyOffset(verifier, VT_VARIANT_TENSORS) && + verifier.VerifyVector(variant_tensors()) && + verifier.VerifyVectorOfTables(variant_tensors()) && + verifier.EndTable(); + } + TensorT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(TensorT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const TensorT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct TensorBuilder { + typedef Tensor Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_shape(flatbuffers::Offset> shape) { + fbb_.AddOffset(Tensor::VT_SHAPE, shape); + } + void add_type(tflite::TensorType type) { + fbb_.AddElement(Tensor::VT_TYPE, static_cast(type), 0); + } + void add_buffer(uint32_t buffer) { + fbb_.AddElement(Tensor::VT_BUFFER, buffer, 0); + } + void add_name(flatbuffers::Offset name) { + fbb_.AddOffset(Tensor::VT_NAME, name); + } + void add_quantization(flatbuffers::Offset quantization) { + fbb_.AddOffset(Tensor::VT_QUANTIZATION, quantization); + } + void add_is_variable(bool is_variable) { + fbb_.AddElement(Tensor::VT_IS_VARIABLE, static_cast(is_variable), 0); + } + void add_sparsity(flatbuffers::Offset sparsity) { + fbb_.AddOffset(Tensor::VT_SPARSITY, sparsity); + } + void add_shape_signature(flatbuffers::Offset> shape_signature) { + fbb_.AddOffset(Tensor::VT_SHAPE_SIGNATURE, shape_signature); + } + void add_has_rank(bool has_rank) { + fbb_.AddElement(Tensor::VT_HAS_RANK, static_cast(has_rank), 0); + } + void add_variant_tensors(flatbuffers::Offset>> variant_tensors) { + fbb_.AddOffset(Tensor::VT_VARIANT_TENSORS, variant_tensors); + } + explicit TensorBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateTensor( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> shape = 0, + tflite::TensorType type = tflite::TensorType_FLOAT32, + uint32_t buffer = 0, + flatbuffers::Offset name = 0, + flatbuffers::Offset quantization = 0, + bool is_variable = false, + flatbuffers::Offset sparsity = 0, + flatbuffers::Offset> shape_signature = 0, + bool has_rank = false, + flatbuffers::Offset>> variant_tensors = 0) { + TensorBuilder builder_(_fbb); + builder_.add_variant_tensors(variant_tensors); + builder_.add_shape_signature(shape_signature); + builder_.add_sparsity(sparsity); + builder_.add_quantization(quantization); + builder_.add_name(name); + builder_.add_buffer(buffer); + builder_.add_shape(shape); + builder_.add_has_rank(has_rank); + builder_.add_is_variable(is_variable); + builder_.add_type(type); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateTensorDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *shape = nullptr, + tflite::TensorType type = tflite::TensorType_FLOAT32, + uint32_t buffer = 0, + const char *name = nullptr, + flatbuffers::Offset quantization = 0, + bool is_variable = false, + flatbuffers::Offset sparsity = 0, + const std::vector *shape_signature = nullptr, + bool has_rank = false, + const std::vector> *variant_tensors = nullptr) { + auto shape__ = shape ? _fbb.CreateVector(*shape) : 0; + auto name__ = name ? _fbb.CreateString(name) : 0; + auto shape_signature__ = shape_signature ? _fbb.CreateVector(*shape_signature) : 0; + auto variant_tensors__ = variant_tensors ? _fbb.CreateVector>(*variant_tensors) : 0; + return tflite::CreateTensor( + _fbb, + shape__, + type, + buffer, + name__, + quantization, + is_variable, + sparsity, + shape_signature__, + has_rank, + variant_tensors__); +} + +flatbuffers::Offset CreateTensor(flatbuffers::FlatBufferBuilder &_fbb, const TensorT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct Conv2DOptionsT : public flatbuffers::NativeTable { + typedef Conv2DOptions TableType; + tflite::Padding padding = tflite::Padding_SAME; + int32_t stride_w = 0; + int32_t stride_h = 0; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + int32_t dilation_w_factor = 1; + int32_t dilation_h_factor = 1; +}; + +struct Conv2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef Conv2DOptionsT NativeTableType; + typedef Conv2DOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_PADDING = 4, + VT_STRIDE_W = 6, + VT_STRIDE_H = 8, + VT_FUSED_ACTIVATION_FUNCTION = 10, + VT_DILATION_W_FACTOR = 12, + VT_DILATION_H_FACTOR = 14 + }; + tflite::Padding padding() const { + return static_cast(GetField(VT_PADDING, 0)); + } + int32_t stride_w() const { + return GetField(VT_STRIDE_W, 0); + } + int32_t stride_h() const { + return GetField(VT_STRIDE_H, 0); + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + int32_t dilation_w_factor() const { + return GetField(VT_DILATION_W_FACTOR, 1); + } + int32_t dilation_h_factor() const { + return GetField(VT_DILATION_H_FACTOR, 1); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_PADDING, 1) && + VerifyField(verifier, VT_STRIDE_W, 4) && + VerifyField(verifier, VT_STRIDE_H, 4) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_DILATION_W_FACTOR, 4) && + VerifyField(verifier, VT_DILATION_H_FACTOR, 4) && + verifier.EndTable(); + } + Conv2DOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(Conv2DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const Conv2DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct Conv2DOptionsBuilder { + typedef Conv2DOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_padding(tflite::Padding padding) { + fbb_.AddElement(Conv2DOptions::VT_PADDING, static_cast(padding), 0); + } + void add_stride_w(int32_t stride_w) { + fbb_.AddElement(Conv2DOptions::VT_STRIDE_W, stride_w, 0); + } + void add_stride_h(int32_t stride_h) { + fbb_.AddElement(Conv2DOptions::VT_STRIDE_H, stride_h, 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(Conv2DOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_dilation_w_factor(int32_t dilation_w_factor) { + fbb_.AddElement(Conv2DOptions::VT_DILATION_W_FACTOR, dilation_w_factor, 1); + } + void add_dilation_h_factor(int32_t dilation_h_factor) { + fbb_.AddElement(Conv2DOptions::VT_DILATION_H_FACTOR, dilation_h_factor, 1); + } + explicit Conv2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateConv2DOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::Padding padding = tflite::Padding_SAME, + int32_t stride_w = 0, + int32_t stride_h = 0, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + int32_t dilation_w_factor = 1, + int32_t dilation_h_factor = 1) { + Conv2DOptionsBuilder builder_(_fbb); + builder_.add_dilation_h_factor(dilation_h_factor); + builder_.add_dilation_w_factor(dilation_w_factor); + builder_.add_stride_h(stride_h); + builder_.add_stride_w(stride_w); + builder_.add_fused_activation_function(fused_activation_function); + builder_.add_padding(padding); + return builder_.Finish(); +} + +flatbuffers::Offset CreateConv2DOptions(flatbuffers::FlatBufferBuilder &_fbb, const Conv2DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct Conv3DOptionsT : public flatbuffers::NativeTable { + typedef Conv3DOptions TableType; + tflite::Padding padding = tflite::Padding_SAME; + int32_t stride_d = 0; + int32_t stride_w = 0; + int32_t stride_h = 0; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + int32_t dilation_d_factor = 1; + int32_t dilation_w_factor = 1; + int32_t dilation_h_factor = 1; +}; + +struct Conv3DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef Conv3DOptionsT NativeTableType; + typedef Conv3DOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_PADDING = 4, + VT_STRIDE_D = 6, + VT_STRIDE_W = 8, + VT_STRIDE_H = 10, + VT_FUSED_ACTIVATION_FUNCTION = 12, + VT_DILATION_D_FACTOR = 14, + VT_DILATION_W_FACTOR = 16, + VT_DILATION_H_FACTOR = 18 + }; + tflite::Padding padding() const { + return static_cast(GetField(VT_PADDING, 0)); + } + int32_t stride_d() const { + return GetField(VT_STRIDE_D, 0); + } + int32_t stride_w() const { + return GetField(VT_STRIDE_W, 0); + } + int32_t stride_h() const { + return GetField(VT_STRIDE_H, 0); + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + int32_t dilation_d_factor() const { + return GetField(VT_DILATION_D_FACTOR, 1); + } + int32_t dilation_w_factor() const { + return GetField(VT_DILATION_W_FACTOR, 1); + } + int32_t dilation_h_factor() const { + return GetField(VT_DILATION_H_FACTOR, 1); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_PADDING, 1) && + VerifyField(verifier, VT_STRIDE_D, 4) && + VerifyField(verifier, VT_STRIDE_W, 4) && + VerifyField(verifier, VT_STRIDE_H, 4) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_DILATION_D_FACTOR, 4) && + VerifyField(verifier, VT_DILATION_W_FACTOR, 4) && + VerifyField(verifier, VT_DILATION_H_FACTOR, 4) && + verifier.EndTable(); + } + Conv3DOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(Conv3DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const Conv3DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct Conv3DOptionsBuilder { + typedef Conv3DOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_padding(tflite::Padding padding) { + fbb_.AddElement(Conv3DOptions::VT_PADDING, static_cast(padding), 0); + } + void add_stride_d(int32_t stride_d) { + fbb_.AddElement(Conv3DOptions::VT_STRIDE_D, stride_d, 0); + } + void add_stride_w(int32_t stride_w) { + fbb_.AddElement(Conv3DOptions::VT_STRIDE_W, stride_w, 0); + } + void add_stride_h(int32_t stride_h) { + fbb_.AddElement(Conv3DOptions::VT_STRIDE_H, stride_h, 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(Conv3DOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_dilation_d_factor(int32_t dilation_d_factor) { + fbb_.AddElement(Conv3DOptions::VT_DILATION_D_FACTOR, dilation_d_factor, 1); + } + void add_dilation_w_factor(int32_t dilation_w_factor) { + fbb_.AddElement(Conv3DOptions::VT_DILATION_W_FACTOR, dilation_w_factor, 1); + } + void add_dilation_h_factor(int32_t dilation_h_factor) { + fbb_.AddElement(Conv3DOptions::VT_DILATION_H_FACTOR, dilation_h_factor, 1); + } + explicit Conv3DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateConv3DOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::Padding padding = tflite::Padding_SAME, + int32_t stride_d = 0, + int32_t stride_w = 0, + int32_t stride_h = 0, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + int32_t dilation_d_factor = 1, + int32_t dilation_w_factor = 1, + int32_t dilation_h_factor = 1) { + Conv3DOptionsBuilder builder_(_fbb); + builder_.add_dilation_h_factor(dilation_h_factor); + builder_.add_dilation_w_factor(dilation_w_factor); + builder_.add_dilation_d_factor(dilation_d_factor); + builder_.add_stride_h(stride_h); + builder_.add_stride_w(stride_w); + builder_.add_stride_d(stride_d); + builder_.add_fused_activation_function(fused_activation_function); + builder_.add_padding(padding); + return builder_.Finish(); +} + +flatbuffers::Offset CreateConv3DOptions(flatbuffers::FlatBufferBuilder &_fbb, const Conv3DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct Pool2DOptionsT : public flatbuffers::NativeTable { + typedef Pool2DOptions TableType; + tflite::Padding padding = tflite::Padding_SAME; + int32_t stride_w = 0; + int32_t stride_h = 0; + int32_t filter_width = 0; + int32_t filter_height = 0; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; +}; + +struct Pool2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef Pool2DOptionsT NativeTableType; + typedef Pool2DOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_PADDING = 4, + VT_STRIDE_W = 6, + VT_STRIDE_H = 8, + VT_FILTER_WIDTH = 10, + VT_FILTER_HEIGHT = 12, + VT_FUSED_ACTIVATION_FUNCTION = 14 + }; + tflite::Padding padding() const { + return static_cast(GetField(VT_PADDING, 0)); + } + int32_t stride_w() const { + return GetField(VT_STRIDE_W, 0); + } + int32_t stride_h() const { + return GetField(VT_STRIDE_H, 0); + } + int32_t filter_width() const { + return GetField(VT_FILTER_WIDTH, 0); + } + int32_t filter_height() const { + return GetField(VT_FILTER_HEIGHT, 0); + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_PADDING, 1) && + VerifyField(verifier, VT_STRIDE_W, 4) && + VerifyField(verifier, VT_STRIDE_H, 4) && + VerifyField(verifier, VT_FILTER_WIDTH, 4) && + VerifyField(verifier, VT_FILTER_HEIGHT, 4) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + verifier.EndTable(); + } + Pool2DOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(Pool2DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const Pool2DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct Pool2DOptionsBuilder { + typedef Pool2DOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_padding(tflite::Padding padding) { + fbb_.AddElement(Pool2DOptions::VT_PADDING, static_cast(padding), 0); + } + void add_stride_w(int32_t stride_w) { + fbb_.AddElement(Pool2DOptions::VT_STRIDE_W, stride_w, 0); + } + void add_stride_h(int32_t stride_h) { + fbb_.AddElement(Pool2DOptions::VT_STRIDE_H, stride_h, 0); + } + void add_filter_width(int32_t filter_width) { + fbb_.AddElement(Pool2DOptions::VT_FILTER_WIDTH, filter_width, 0); + } + void add_filter_height(int32_t filter_height) { + fbb_.AddElement(Pool2DOptions::VT_FILTER_HEIGHT, filter_height, 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(Pool2DOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + explicit Pool2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreatePool2DOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::Padding padding = tflite::Padding_SAME, + int32_t stride_w = 0, + int32_t stride_h = 0, + int32_t filter_width = 0, + int32_t filter_height = 0, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE) { + Pool2DOptionsBuilder builder_(_fbb); + builder_.add_filter_height(filter_height); + builder_.add_filter_width(filter_width); + builder_.add_stride_h(stride_h); + builder_.add_stride_w(stride_w); + builder_.add_fused_activation_function(fused_activation_function); + builder_.add_padding(padding); + return builder_.Finish(); +} + +flatbuffers::Offset CreatePool2DOptions(flatbuffers::FlatBufferBuilder &_fbb, const Pool2DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct DepthwiseConv2DOptionsT : public flatbuffers::NativeTable { + typedef DepthwiseConv2DOptions TableType; + tflite::Padding padding = tflite::Padding_SAME; + int32_t stride_w = 0; + int32_t stride_h = 0; + int32_t depth_multiplier = 0; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + int32_t dilation_w_factor = 1; + int32_t dilation_h_factor = 1; +}; + +struct DepthwiseConv2DOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef DepthwiseConv2DOptionsT NativeTableType; + typedef DepthwiseConv2DOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_PADDING = 4, + VT_STRIDE_W = 6, + VT_STRIDE_H = 8, + VT_DEPTH_MULTIPLIER = 10, + VT_FUSED_ACTIVATION_FUNCTION = 12, + VT_DILATION_W_FACTOR = 14, + VT_DILATION_H_FACTOR = 16 + }; + tflite::Padding padding() const { + return static_cast(GetField(VT_PADDING, 0)); + } + int32_t stride_w() const { + return GetField(VT_STRIDE_W, 0); + } + int32_t stride_h() const { + return GetField(VT_STRIDE_H, 0); + } + int32_t depth_multiplier() const { + return GetField(VT_DEPTH_MULTIPLIER, 0); + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + int32_t dilation_w_factor() const { + return GetField(VT_DILATION_W_FACTOR, 1); + } + int32_t dilation_h_factor() const { + return GetField(VT_DILATION_H_FACTOR, 1); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_PADDING, 1) && + VerifyField(verifier, VT_STRIDE_W, 4) && + VerifyField(verifier, VT_STRIDE_H, 4) && + VerifyField(verifier, VT_DEPTH_MULTIPLIER, 4) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_DILATION_W_FACTOR, 4) && + VerifyField(verifier, VT_DILATION_H_FACTOR, 4) && + verifier.EndTable(); + } + DepthwiseConv2DOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(DepthwiseConv2DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const DepthwiseConv2DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct DepthwiseConv2DOptionsBuilder { + typedef DepthwiseConv2DOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_padding(tflite::Padding padding) { + fbb_.AddElement(DepthwiseConv2DOptions::VT_PADDING, static_cast(padding), 0); + } + void add_stride_w(int32_t stride_w) { + fbb_.AddElement(DepthwiseConv2DOptions::VT_STRIDE_W, stride_w, 0); + } + void add_stride_h(int32_t stride_h) { + fbb_.AddElement(DepthwiseConv2DOptions::VT_STRIDE_H, stride_h, 0); + } + void add_depth_multiplier(int32_t depth_multiplier) { + fbb_.AddElement(DepthwiseConv2DOptions::VT_DEPTH_MULTIPLIER, depth_multiplier, 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(DepthwiseConv2DOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_dilation_w_factor(int32_t dilation_w_factor) { + fbb_.AddElement(DepthwiseConv2DOptions::VT_DILATION_W_FACTOR, dilation_w_factor, 1); + } + void add_dilation_h_factor(int32_t dilation_h_factor) { + fbb_.AddElement(DepthwiseConv2DOptions::VT_DILATION_H_FACTOR, dilation_h_factor, 1); + } + explicit DepthwiseConv2DOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateDepthwiseConv2DOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::Padding padding = tflite::Padding_SAME, + int32_t stride_w = 0, + int32_t stride_h = 0, + int32_t depth_multiplier = 0, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + int32_t dilation_w_factor = 1, + int32_t dilation_h_factor = 1) { + DepthwiseConv2DOptionsBuilder builder_(_fbb); + builder_.add_dilation_h_factor(dilation_h_factor); + builder_.add_dilation_w_factor(dilation_w_factor); + builder_.add_depth_multiplier(depth_multiplier); + builder_.add_stride_h(stride_h); + builder_.add_stride_w(stride_w); + builder_.add_fused_activation_function(fused_activation_function); + builder_.add_padding(padding); + return builder_.Finish(); +} + +flatbuffers::Offset CreateDepthwiseConv2DOptions(flatbuffers::FlatBufferBuilder &_fbb, const DepthwiseConv2DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ConcatEmbeddingsOptionsT : public flatbuffers::NativeTable { + typedef ConcatEmbeddingsOptions TableType; + int32_t num_channels = 0; + std::vector num_columns_per_channel{}; + std::vector embedding_dim_per_channel{}; +}; + +struct ConcatEmbeddingsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ConcatEmbeddingsOptionsT NativeTableType; + typedef ConcatEmbeddingsOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NUM_CHANNELS = 4, + VT_NUM_COLUMNS_PER_CHANNEL = 6, + VT_EMBEDDING_DIM_PER_CHANNEL = 8 + }; + int32_t num_channels() const { + return GetField(VT_NUM_CHANNELS, 0); + } + const flatbuffers::Vector *num_columns_per_channel() const { + return GetPointer *>(VT_NUM_COLUMNS_PER_CHANNEL); + } + const flatbuffers::Vector *embedding_dim_per_channel() const { + return GetPointer *>(VT_EMBEDDING_DIM_PER_CHANNEL); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_NUM_CHANNELS, 4) && + VerifyOffset(verifier, VT_NUM_COLUMNS_PER_CHANNEL) && + verifier.VerifyVector(num_columns_per_channel()) && + VerifyOffset(verifier, VT_EMBEDDING_DIM_PER_CHANNEL) && + verifier.VerifyVector(embedding_dim_per_channel()) && + verifier.EndTable(); + } + ConcatEmbeddingsOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ConcatEmbeddingsOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ConcatEmbeddingsOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ConcatEmbeddingsOptionsBuilder { + typedef ConcatEmbeddingsOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_num_channels(int32_t num_channels) { + fbb_.AddElement(ConcatEmbeddingsOptions::VT_NUM_CHANNELS, num_channels, 0); + } + void add_num_columns_per_channel(flatbuffers::Offset> num_columns_per_channel) { + fbb_.AddOffset(ConcatEmbeddingsOptions::VT_NUM_COLUMNS_PER_CHANNEL, num_columns_per_channel); + } + void add_embedding_dim_per_channel(flatbuffers::Offset> embedding_dim_per_channel) { + fbb_.AddOffset(ConcatEmbeddingsOptions::VT_EMBEDDING_DIM_PER_CHANNEL, embedding_dim_per_channel); + } + explicit ConcatEmbeddingsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateConcatEmbeddingsOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t num_channels = 0, + flatbuffers::Offset> num_columns_per_channel = 0, + flatbuffers::Offset> embedding_dim_per_channel = 0) { + ConcatEmbeddingsOptionsBuilder builder_(_fbb); + builder_.add_embedding_dim_per_channel(embedding_dim_per_channel); + builder_.add_num_columns_per_channel(num_columns_per_channel); + builder_.add_num_channels(num_channels); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateConcatEmbeddingsOptionsDirect( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t num_channels = 0, + const std::vector *num_columns_per_channel = nullptr, + const std::vector *embedding_dim_per_channel = nullptr) { + auto num_columns_per_channel__ = num_columns_per_channel ? _fbb.CreateVector(*num_columns_per_channel) : 0; + auto embedding_dim_per_channel__ = embedding_dim_per_channel ? _fbb.CreateVector(*embedding_dim_per_channel) : 0; + return tflite::CreateConcatEmbeddingsOptions( + _fbb, + num_channels, + num_columns_per_channel__, + embedding_dim_per_channel__); +} + +flatbuffers::Offset CreateConcatEmbeddingsOptions(flatbuffers::FlatBufferBuilder &_fbb, const ConcatEmbeddingsOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LSHProjectionOptionsT : public flatbuffers::NativeTable { + typedef LSHProjectionOptions TableType; + tflite::LSHProjectionType type = tflite::LSHProjectionType_UNKNOWN; +}; + +struct LSHProjectionOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LSHProjectionOptionsT NativeTableType; + typedef LSHProjectionOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_TYPE = 4 + }; + tflite::LSHProjectionType type() const { + return static_cast(GetField(VT_TYPE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_TYPE, 1) && + verifier.EndTable(); + } + LSHProjectionOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LSHProjectionOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LSHProjectionOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LSHProjectionOptionsBuilder { + typedef LSHProjectionOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_type(tflite::LSHProjectionType type) { + fbb_.AddElement(LSHProjectionOptions::VT_TYPE, static_cast(type), 0); + } + explicit LSHProjectionOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLSHProjectionOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::LSHProjectionType type = tflite::LSHProjectionType_UNKNOWN) { + LSHProjectionOptionsBuilder builder_(_fbb); + builder_.add_type(type); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLSHProjectionOptions(flatbuffers::FlatBufferBuilder &_fbb, const LSHProjectionOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SVDFOptionsT : public flatbuffers::NativeTable { + typedef SVDFOptions TableType; + int32_t rank = 0; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + bool asymmetric_quantize_inputs = false; +}; + +struct SVDFOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SVDFOptionsT NativeTableType; + typedef SVDFOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_RANK = 4, + VT_FUSED_ACTIVATION_FUNCTION = 6, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 8 + }; + int32_t rank() const { + return GetField(VT_RANK, 0); + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_RANK, 4) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + SVDFOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SVDFOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SVDFOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SVDFOptionsBuilder { + typedef SVDFOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_rank(int32_t rank) { + fbb_.AddElement(SVDFOptions::VT_RANK, rank, 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(SVDFOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(SVDFOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit SVDFOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSVDFOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t rank = 0, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + bool asymmetric_quantize_inputs = false) { + SVDFOptionsBuilder builder_(_fbb); + builder_.add_rank(rank); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSVDFOptions(flatbuffers::FlatBufferBuilder &_fbb, const SVDFOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct RNNOptionsT : public flatbuffers::NativeTable { + typedef RNNOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + bool asymmetric_quantize_inputs = false; +}; + +struct RNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef RNNOptionsT NativeTableType; + typedef RNNOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 6 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + RNNOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(RNNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const RNNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct RNNOptionsBuilder { + typedef RNNOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(RNNOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(RNNOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit RNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateRNNOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + bool asymmetric_quantize_inputs = false) { + RNNOptionsBuilder builder_(_fbb); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateRNNOptions(flatbuffers::FlatBufferBuilder &_fbb, const RNNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SequenceRNNOptionsT : public flatbuffers::NativeTable { + typedef SequenceRNNOptions TableType; + bool time_major = false; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + bool asymmetric_quantize_inputs = false; +}; + +struct SequenceRNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SequenceRNNOptionsT NativeTableType; + typedef SequenceRNNOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_TIME_MAJOR = 4, + VT_FUSED_ACTIVATION_FUNCTION = 6, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 8 + }; + bool time_major() const { + return GetField(VT_TIME_MAJOR, 0) != 0; + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_TIME_MAJOR, 1) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + SequenceRNNOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SequenceRNNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SequenceRNNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SequenceRNNOptionsBuilder { + typedef SequenceRNNOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_time_major(bool time_major) { + fbb_.AddElement(SequenceRNNOptions::VT_TIME_MAJOR, static_cast(time_major), 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(SequenceRNNOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(SequenceRNNOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit SequenceRNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSequenceRNNOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool time_major = false, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + bool asymmetric_quantize_inputs = false) { + SequenceRNNOptionsBuilder builder_(_fbb); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_fused_activation_function(fused_activation_function); + builder_.add_time_major(time_major); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSequenceRNNOptions(flatbuffers::FlatBufferBuilder &_fbb, const SequenceRNNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct BidirectionalSequenceRNNOptionsT : public flatbuffers::NativeTable { + typedef BidirectionalSequenceRNNOptions TableType; + bool time_major = false; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + bool merge_outputs = false; + bool asymmetric_quantize_inputs = false; +}; + +struct BidirectionalSequenceRNNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef BidirectionalSequenceRNNOptionsT NativeTableType; + typedef BidirectionalSequenceRNNOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_TIME_MAJOR = 4, + VT_FUSED_ACTIVATION_FUNCTION = 6, + VT_MERGE_OUTPUTS = 8, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 10 + }; + bool time_major() const { + return GetField(VT_TIME_MAJOR, 0) != 0; + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool merge_outputs() const { + return GetField(VT_MERGE_OUTPUTS, 0) != 0; + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_TIME_MAJOR, 1) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_MERGE_OUTPUTS, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + BidirectionalSequenceRNNOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(BidirectionalSequenceRNNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceRNNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct BidirectionalSequenceRNNOptionsBuilder { + typedef BidirectionalSequenceRNNOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_time_major(bool time_major) { + fbb_.AddElement(BidirectionalSequenceRNNOptions::VT_TIME_MAJOR, static_cast(time_major), 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(BidirectionalSequenceRNNOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_merge_outputs(bool merge_outputs) { + fbb_.AddElement(BidirectionalSequenceRNNOptions::VT_MERGE_OUTPUTS, static_cast(merge_outputs), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(BidirectionalSequenceRNNOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit BidirectionalSequenceRNNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateBidirectionalSequenceRNNOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool time_major = false, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + bool merge_outputs = false, + bool asymmetric_quantize_inputs = false) { + BidirectionalSequenceRNNOptionsBuilder builder_(_fbb); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_merge_outputs(merge_outputs); + builder_.add_fused_activation_function(fused_activation_function); + builder_.add_time_major(time_major); + return builder_.Finish(); +} + +flatbuffers::Offset CreateBidirectionalSequenceRNNOptions(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceRNNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct FullyConnectedOptionsT : public flatbuffers::NativeTable { + typedef FullyConnectedOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + tflite::FullyConnectedOptionsWeightsFormat weights_format = tflite::FullyConnectedOptionsWeightsFormat_DEFAULT; + bool keep_num_dims = false; + bool asymmetric_quantize_inputs = false; +}; + +struct FullyConnectedOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef FullyConnectedOptionsT NativeTableType; + typedef FullyConnectedOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4, + VT_WEIGHTS_FORMAT = 6, + VT_KEEP_NUM_DIMS = 8, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 10 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + tflite::FullyConnectedOptionsWeightsFormat weights_format() const { + return static_cast(GetField(VT_WEIGHTS_FORMAT, 0)); + } + bool keep_num_dims() const { + return GetField(VT_KEEP_NUM_DIMS, 0) != 0; + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_WEIGHTS_FORMAT, 1) && + VerifyField(verifier, VT_KEEP_NUM_DIMS, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + FullyConnectedOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(FullyConnectedOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const FullyConnectedOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct FullyConnectedOptionsBuilder { + typedef FullyConnectedOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(FullyConnectedOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_weights_format(tflite::FullyConnectedOptionsWeightsFormat weights_format) { + fbb_.AddElement(FullyConnectedOptions::VT_WEIGHTS_FORMAT, static_cast(weights_format), 0); + } + void add_keep_num_dims(bool keep_num_dims) { + fbb_.AddElement(FullyConnectedOptions::VT_KEEP_NUM_DIMS, static_cast(keep_num_dims), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(FullyConnectedOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit FullyConnectedOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateFullyConnectedOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + tflite::FullyConnectedOptionsWeightsFormat weights_format = tflite::FullyConnectedOptionsWeightsFormat_DEFAULT, + bool keep_num_dims = false, + bool asymmetric_quantize_inputs = false) { + FullyConnectedOptionsBuilder builder_(_fbb); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_keep_num_dims(keep_num_dims); + builder_.add_weights_format(weights_format); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateFullyConnectedOptions(flatbuffers::FlatBufferBuilder &_fbb, const FullyConnectedOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SoftmaxOptionsT : public flatbuffers::NativeTable { + typedef SoftmaxOptions TableType; + float beta = 0.0f; +}; + +struct SoftmaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SoftmaxOptionsT NativeTableType; + typedef SoftmaxOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_BETA = 4 + }; + float beta() const { + return GetField(VT_BETA, 0.0f); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_BETA, 4) && + verifier.EndTable(); + } + SoftmaxOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SoftmaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SoftmaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SoftmaxOptionsBuilder { + typedef SoftmaxOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_beta(float beta) { + fbb_.AddElement(SoftmaxOptions::VT_BETA, beta, 0.0f); + } + explicit SoftmaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSoftmaxOptions( + flatbuffers::FlatBufferBuilder &_fbb, + float beta = 0.0f) { + SoftmaxOptionsBuilder builder_(_fbb); + builder_.add_beta(beta); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const SoftmaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ConcatenationOptionsT : public flatbuffers::NativeTable { + typedef ConcatenationOptions TableType; + int32_t axis = 0; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; +}; + +struct ConcatenationOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ConcatenationOptionsT NativeTableType; + typedef ConcatenationOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_AXIS = 4, + VT_FUSED_ACTIVATION_FUNCTION = 6 + }; + int32_t axis() const { + return GetField(VT_AXIS, 0); + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_AXIS, 4) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + verifier.EndTable(); + } + ConcatenationOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ConcatenationOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ConcatenationOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ConcatenationOptionsBuilder { + typedef ConcatenationOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_axis(int32_t axis) { + fbb_.AddElement(ConcatenationOptions::VT_AXIS, axis, 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(ConcatenationOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + explicit ConcatenationOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateConcatenationOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t axis = 0, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE) { + ConcatenationOptionsBuilder builder_(_fbb); + builder_.add_axis(axis); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateConcatenationOptions(flatbuffers::FlatBufferBuilder &_fbb, const ConcatenationOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct AddOptionsT : public flatbuffers::NativeTable { + typedef AddOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + bool pot_scale_int16 = true; +}; + +struct AddOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef AddOptionsT NativeTableType; + typedef AddOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4, + VT_POT_SCALE_INT16 = 6 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool pot_scale_int16() const { + return GetField(VT_POT_SCALE_INT16, 1) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_POT_SCALE_INT16, 1) && + verifier.EndTable(); + } + AddOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(AddOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const AddOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct AddOptionsBuilder { + typedef AddOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(AddOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_pot_scale_int16(bool pot_scale_int16) { + fbb_.AddElement(AddOptions::VT_POT_SCALE_INT16, static_cast(pot_scale_int16), 1); + } + explicit AddOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateAddOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + bool pot_scale_int16 = true) { + AddOptionsBuilder builder_(_fbb); + builder_.add_pot_scale_int16(pot_scale_int16); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateAddOptions(flatbuffers::FlatBufferBuilder &_fbb, const AddOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct MulOptionsT : public flatbuffers::NativeTable { + typedef MulOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; +}; + +struct MulOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef MulOptionsT NativeTableType; + typedef MulOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + verifier.EndTable(); + } + MulOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(MulOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const MulOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct MulOptionsBuilder { + typedef MulOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(MulOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + explicit MulOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateMulOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE) { + MulOptionsBuilder builder_(_fbb); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateMulOptions(flatbuffers::FlatBufferBuilder &_fbb, const MulOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct L2NormOptionsT : public flatbuffers::NativeTable { + typedef L2NormOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; +}; + +struct L2NormOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef L2NormOptionsT NativeTableType; + typedef L2NormOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + verifier.EndTable(); + } + L2NormOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(L2NormOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const L2NormOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct L2NormOptionsBuilder { + typedef L2NormOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(L2NormOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + explicit L2NormOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateL2NormOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE) { + L2NormOptionsBuilder builder_(_fbb); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateL2NormOptions(flatbuffers::FlatBufferBuilder &_fbb, const L2NormOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LocalResponseNormalizationOptionsT : public flatbuffers::NativeTable { + typedef LocalResponseNormalizationOptions TableType; + int32_t radius = 0; + float bias = 0.0f; + float alpha = 0.0f; + float beta = 0.0f; +}; + +struct LocalResponseNormalizationOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LocalResponseNormalizationOptionsT NativeTableType; + typedef LocalResponseNormalizationOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_RADIUS = 4, + VT_BIAS = 6, + VT_ALPHA = 8, + VT_BETA = 10 + }; + int32_t radius() const { + return GetField(VT_RADIUS, 0); + } + float bias() const { + return GetField(VT_BIAS, 0.0f); + } + float alpha() const { + return GetField(VT_ALPHA, 0.0f); + } + float beta() const { + return GetField(VT_BETA, 0.0f); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_RADIUS, 4) && + VerifyField(verifier, VT_BIAS, 4) && + VerifyField(verifier, VT_ALPHA, 4) && + VerifyField(verifier, VT_BETA, 4) && + verifier.EndTable(); + } + LocalResponseNormalizationOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LocalResponseNormalizationOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LocalResponseNormalizationOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LocalResponseNormalizationOptionsBuilder { + typedef LocalResponseNormalizationOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_radius(int32_t radius) { + fbb_.AddElement(LocalResponseNormalizationOptions::VT_RADIUS, radius, 0); + } + void add_bias(float bias) { + fbb_.AddElement(LocalResponseNormalizationOptions::VT_BIAS, bias, 0.0f); + } + void add_alpha(float alpha) { + fbb_.AddElement(LocalResponseNormalizationOptions::VT_ALPHA, alpha, 0.0f); + } + void add_beta(float beta) { + fbb_.AddElement(LocalResponseNormalizationOptions::VT_BETA, beta, 0.0f); + } + explicit LocalResponseNormalizationOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLocalResponseNormalizationOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t radius = 0, + float bias = 0.0f, + float alpha = 0.0f, + float beta = 0.0f) { + LocalResponseNormalizationOptionsBuilder builder_(_fbb); + builder_.add_beta(beta); + builder_.add_alpha(alpha); + builder_.add_bias(bias); + builder_.add_radius(radius); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLocalResponseNormalizationOptions(flatbuffers::FlatBufferBuilder &_fbb, const LocalResponseNormalizationOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LSTMOptionsT : public flatbuffers::NativeTable { + typedef LSTMOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + float cell_clip = 0.0f; + float proj_clip = 0.0f; + tflite::LSTMKernelType kernel_type = tflite::LSTMKernelType_FULL; + bool asymmetric_quantize_inputs = false; +}; + +struct LSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LSTMOptionsT NativeTableType; + typedef LSTMOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4, + VT_CELL_CLIP = 6, + VT_PROJ_CLIP = 8, + VT_KERNEL_TYPE = 10, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 12 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + float cell_clip() const { + return GetField(VT_CELL_CLIP, 0.0f); + } + float proj_clip() const { + return GetField(VT_PROJ_CLIP, 0.0f); + } + tflite::LSTMKernelType kernel_type() const { + return static_cast(GetField(VT_KERNEL_TYPE, 0)); + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_CELL_CLIP, 4) && + VerifyField(verifier, VT_PROJ_CLIP, 4) && + VerifyField(verifier, VT_KERNEL_TYPE, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + LSTMOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LSTMOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LSTMOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LSTMOptionsBuilder { + typedef LSTMOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(LSTMOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_cell_clip(float cell_clip) { + fbb_.AddElement(LSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f); + } + void add_proj_clip(float proj_clip) { + fbb_.AddElement(LSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f); + } + void add_kernel_type(tflite::LSTMKernelType kernel_type) { + fbb_.AddElement(LSTMOptions::VT_KERNEL_TYPE, static_cast(kernel_type), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(LSTMOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit LSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLSTMOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + float cell_clip = 0.0f, + float proj_clip = 0.0f, + tflite::LSTMKernelType kernel_type = tflite::LSTMKernelType_FULL, + bool asymmetric_quantize_inputs = false) { + LSTMOptionsBuilder builder_(_fbb); + builder_.add_proj_clip(proj_clip); + builder_.add_cell_clip(cell_clip); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_kernel_type(kernel_type); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb, const LSTMOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct UnidirectionalSequenceLSTMOptionsT : public flatbuffers::NativeTable { + typedef UnidirectionalSequenceLSTMOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + float cell_clip = 0.0f; + float proj_clip = 0.0f; + bool time_major = false; + bool asymmetric_quantize_inputs = false; + bool diagonal_recurrent_tensors = false; +}; + +struct UnidirectionalSequenceLSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef UnidirectionalSequenceLSTMOptionsT NativeTableType; + typedef UnidirectionalSequenceLSTMOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4, + VT_CELL_CLIP = 6, + VT_PROJ_CLIP = 8, + VT_TIME_MAJOR = 10, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 12, + VT_DIAGONAL_RECURRENT_TENSORS = 14 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + float cell_clip() const { + return GetField(VT_CELL_CLIP, 0.0f); + } + float proj_clip() const { + return GetField(VT_PROJ_CLIP, 0.0f); + } + bool time_major() const { + return GetField(VT_TIME_MAJOR, 0) != 0; + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool diagonal_recurrent_tensors() const { + return GetField(VT_DIAGONAL_RECURRENT_TENSORS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_CELL_CLIP, 4) && + VerifyField(verifier, VT_PROJ_CLIP, 4) && + VerifyField(verifier, VT_TIME_MAJOR, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + VerifyField(verifier, VT_DIAGONAL_RECURRENT_TENSORS, 1) && + verifier.EndTable(); + } + UnidirectionalSequenceLSTMOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(UnidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnidirectionalSequenceLSTMOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct UnidirectionalSequenceLSTMOptionsBuilder { + typedef UnidirectionalSequenceLSTMOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(UnidirectionalSequenceLSTMOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_cell_clip(float cell_clip) { + fbb_.AddElement(UnidirectionalSequenceLSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f); + } + void add_proj_clip(float proj_clip) { + fbb_.AddElement(UnidirectionalSequenceLSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f); + } + void add_time_major(bool time_major) { + fbb_.AddElement(UnidirectionalSequenceLSTMOptions::VT_TIME_MAJOR, static_cast(time_major), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(UnidirectionalSequenceLSTMOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + void add_diagonal_recurrent_tensors(bool diagonal_recurrent_tensors) { + fbb_.AddElement(UnidirectionalSequenceLSTMOptions::VT_DIAGONAL_RECURRENT_TENSORS, static_cast(diagonal_recurrent_tensors), 0); + } + explicit UnidirectionalSequenceLSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUnidirectionalSequenceLSTMOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + float cell_clip = 0.0f, + float proj_clip = 0.0f, + bool time_major = false, + bool asymmetric_quantize_inputs = false, + bool diagonal_recurrent_tensors = false) { + UnidirectionalSequenceLSTMOptionsBuilder builder_(_fbb); + builder_.add_proj_clip(proj_clip); + builder_.add_cell_clip(cell_clip); + builder_.add_diagonal_recurrent_tensors(diagonal_recurrent_tensors); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_time_major(time_major); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateUnidirectionalSequenceLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct BidirectionalSequenceLSTMOptionsT : public flatbuffers::NativeTable { + typedef BidirectionalSequenceLSTMOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + float cell_clip = 0.0f; + float proj_clip = 0.0f; + bool merge_outputs = false; + bool time_major = true; + bool asymmetric_quantize_inputs = false; +}; + +struct BidirectionalSequenceLSTMOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef BidirectionalSequenceLSTMOptionsT NativeTableType; + typedef BidirectionalSequenceLSTMOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4, + VT_CELL_CLIP = 6, + VT_PROJ_CLIP = 8, + VT_MERGE_OUTPUTS = 10, + VT_TIME_MAJOR = 12, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 14 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + float cell_clip() const { + return GetField(VT_CELL_CLIP, 0.0f); + } + float proj_clip() const { + return GetField(VT_PROJ_CLIP, 0.0f); + } + bool merge_outputs() const { + return GetField(VT_MERGE_OUTPUTS, 0) != 0; + } + bool time_major() const { + return GetField(VT_TIME_MAJOR, 1) != 0; + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_CELL_CLIP, 4) && + VerifyField(verifier, VT_PROJ_CLIP, 4) && + VerifyField(verifier, VT_MERGE_OUTPUTS, 1) && + VerifyField(verifier, VT_TIME_MAJOR, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + BidirectionalSequenceLSTMOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(BidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceLSTMOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct BidirectionalSequenceLSTMOptionsBuilder { + typedef BidirectionalSequenceLSTMOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(BidirectionalSequenceLSTMOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_cell_clip(float cell_clip) { + fbb_.AddElement(BidirectionalSequenceLSTMOptions::VT_CELL_CLIP, cell_clip, 0.0f); + } + void add_proj_clip(float proj_clip) { + fbb_.AddElement(BidirectionalSequenceLSTMOptions::VT_PROJ_CLIP, proj_clip, 0.0f); + } + void add_merge_outputs(bool merge_outputs) { + fbb_.AddElement(BidirectionalSequenceLSTMOptions::VT_MERGE_OUTPUTS, static_cast(merge_outputs), 0); + } + void add_time_major(bool time_major) { + fbb_.AddElement(BidirectionalSequenceLSTMOptions::VT_TIME_MAJOR, static_cast(time_major), 1); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(BidirectionalSequenceLSTMOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit BidirectionalSequenceLSTMOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateBidirectionalSequenceLSTMOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + float cell_clip = 0.0f, + float proj_clip = 0.0f, + bool merge_outputs = false, + bool time_major = true, + bool asymmetric_quantize_inputs = false) { + BidirectionalSequenceLSTMOptionsBuilder builder_(_fbb); + builder_.add_proj_clip(proj_clip); + builder_.add_cell_clip(cell_clip); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_time_major(time_major); + builder_.add_merge_outputs(merge_outputs); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateBidirectionalSequenceLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ResizeBilinearOptionsT : public flatbuffers::NativeTable { + typedef ResizeBilinearOptions TableType; + bool align_corners = false; + bool half_pixel_centers = false; +}; + +struct ResizeBilinearOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ResizeBilinearOptionsT NativeTableType; + typedef ResizeBilinearOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_ALIGN_CORNERS = 8, + VT_HALF_PIXEL_CENTERS = 10 + }; + bool align_corners() const { + return GetField(VT_ALIGN_CORNERS, 0) != 0; + } + bool half_pixel_centers() const { + return GetField(VT_HALF_PIXEL_CENTERS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_ALIGN_CORNERS, 1) && + VerifyField(verifier, VT_HALF_PIXEL_CENTERS, 1) && + verifier.EndTable(); + } + ResizeBilinearOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ResizeBilinearOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ResizeBilinearOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ResizeBilinearOptionsBuilder { + typedef ResizeBilinearOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_align_corners(bool align_corners) { + fbb_.AddElement(ResizeBilinearOptions::VT_ALIGN_CORNERS, static_cast(align_corners), 0); + } + void add_half_pixel_centers(bool half_pixel_centers) { + fbb_.AddElement(ResizeBilinearOptions::VT_HALF_PIXEL_CENTERS, static_cast(half_pixel_centers), 0); + } + explicit ResizeBilinearOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateResizeBilinearOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool align_corners = false, + bool half_pixel_centers = false) { + ResizeBilinearOptionsBuilder builder_(_fbb); + builder_.add_half_pixel_centers(half_pixel_centers); + builder_.add_align_corners(align_corners); + return builder_.Finish(); +} + +flatbuffers::Offset CreateResizeBilinearOptions(flatbuffers::FlatBufferBuilder &_fbb, const ResizeBilinearOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ResizeNearestNeighborOptionsT : public flatbuffers::NativeTable { + typedef ResizeNearestNeighborOptions TableType; + bool align_corners = false; + bool half_pixel_centers = false; +}; + +struct ResizeNearestNeighborOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ResizeNearestNeighborOptionsT NativeTableType; + typedef ResizeNearestNeighborOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_ALIGN_CORNERS = 4, + VT_HALF_PIXEL_CENTERS = 6 + }; + bool align_corners() const { + return GetField(VT_ALIGN_CORNERS, 0) != 0; + } + bool half_pixel_centers() const { + return GetField(VT_HALF_PIXEL_CENTERS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_ALIGN_CORNERS, 1) && + VerifyField(verifier, VT_HALF_PIXEL_CENTERS, 1) && + verifier.EndTable(); + } + ResizeNearestNeighborOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ResizeNearestNeighborOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ResizeNearestNeighborOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ResizeNearestNeighborOptionsBuilder { + typedef ResizeNearestNeighborOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_align_corners(bool align_corners) { + fbb_.AddElement(ResizeNearestNeighborOptions::VT_ALIGN_CORNERS, static_cast(align_corners), 0); + } + void add_half_pixel_centers(bool half_pixel_centers) { + fbb_.AddElement(ResizeNearestNeighborOptions::VT_HALF_PIXEL_CENTERS, static_cast(half_pixel_centers), 0); + } + explicit ResizeNearestNeighborOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateResizeNearestNeighborOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool align_corners = false, + bool half_pixel_centers = false) { + ResizeNearestNeighborOptionsBuilder builder_(_fbb); + builder_.add_half_pixel_centers(half_pixel_centers); + builder_.add_align_corners(align_corners); + return builder_.Finish(); +} + +flatbuffers::Offset CreateResizeNearestNeighborOptions(flatbuffers::FlatBufferBuilder &_fbb, const ResizeNearestNeighborOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct CallOptionsT : public flatbuffers::NativeTable { + typedef CallOptions TableType; + uint32_t subgraph = 0; +}; + +struct CallOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef CallOptionsT NativeTableType; + typedef CallOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_SUBGRAPH = 4 + }; + uint32_t subgraph() const { + return GetField(VT_SUBGRAPH, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_SUBGRAPH, 4) && + verifier.EndTable(); + } + CallOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(CallOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const CallOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct CallOptionsBuilder { + typedef CallOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_subgraph(uint32_t subgraph) { + fbb_.AddElement(CallOptions::VT_SUBGRAPH, subgraph, 0); + } + explicit CallOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateCallOptions( + flatbuffers::FlatBufferBuilder &_fbb, + uint32_t subgraph = 0) { + CallOptionsBuilder builder_(_fbb); + builder_.add_subgraph(subgraph); + return builder_.Finish(); +} + +flatbuffers::Offset CreateCallOptions(flatbuffers::FlatBufferBuilder &_fbb, const CallOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct PadOptionsT : public flatbuffers::NativeTable { + typedef PadOptions TableType; +}; + +struct PadOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef PadOptionsT NativeTableType; + typedef PadOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + PadOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(PadOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const PadOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct PadOptionsBuilder { + typedef PadOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit PadOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreatePadOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + PadOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreatePadOptions(flatbuffers::FlatBufferBuilder &_fbb, const PadOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct PadV2OptionsT : public flatbuffers::NativeTable { + typedef PadV2Options TableType; +}; + +struct PadV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef PadV2OptionsT NativeTableType; + typedef PadV2OptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + PadV2OptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(PadV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const PadV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct PadV2OptionsBuilder { + typedef PadV2Options Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit PadV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreatePadV2Options( + flatbuffers::FlatBufferBuilder &_fbb) { + PadV2OptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreatePadV2Options(flatbuffers::FlatBufferBuilder &_fbb, const PadV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ReshapeOptionsT : public flatbuffers::NativeTable { + typedef ReshapeOptions TableType; + std::vector new_shape{}; +}; + +struct ReshapeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ReshapeOptionsT NativeTableType; + typedef ReshapeOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NEW_SHAPE = 4 + }; + const flatbuffers::Vector *new_shape() const { + return GetPointer *>(VT_NEW_SHAPE); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_NEW_SHAPE) && + verifier.VerifyVector(new_shape()) && + verifier.EndTable(); + } + ReshapeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ReshapeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReshapeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ReshapeOptionsBuilder { + typedef ReshapeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_new_shape(flatbuffers::Offset> new_shape) { + fbb_.AddOffset(ReshapeOptions::VT_NEW_SHAPE, new_shape); + } + explicit ReshapeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateReshapeOptions( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> new_shape = 0) { + ReshapeOptionsBuilder builder_(_fbb); + builder_.add_new_shape(new_shape); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateReshapeOptionsDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *new_shape = nullptr) { + auto new_shape__ = new_shape ? _fbb.CreateVector(*new_shape) : 0; + return tflite::CreateReshapeOptions( + _fbb, + new_shape__); +} + +flatbuffers::Offset CreateReshapeOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReshapeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SpaceToBatchNDOptionsT : public flatbuffers::NativeTable { + typedef SpaceToBatchNDOptions TableType; +}; + +struct SpaceToBatchNDOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SpaceToBatchNDOptionsT NativeTableType; + typedef SpaceToBatchNDOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SpaceToBatchNDOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SpaceToBatchNDOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToBatchNDOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SpaceToBatchNDOptionsBuilder { + typedef SpaceToBatchNDOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SpaceToBatchNDOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSpaceToBatchNDOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + SpaceToBatchNDOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSpaceToBatchNDOptions(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToBatchNDOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct BatchToSpaceNDOptionsT : public flatbuffers::NativeTable { + typedef BatchToSpaceNDOptions TableType; +}; + +struct BatchToSpaceNDOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef BatchToSpaceNDOptionsT NativeTableType; + typedef BatchToSpaceNDOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + BatchToSpaceNDOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(BatchToSpaceNDOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const BatchToSpaceNDOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct BatchToSpaceNDOptionsBuilder { + typedef BatchToSpaceNDOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit BatchToSpaceNDOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateBatchToSpaceNDOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + BatchToSpaceNDOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateBatchToSpaceNDOptions(flatbuffers::FlatBufferBuilder &_fbb, const BatchToSpaceNDOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SkipGramOptionsT : public flatbuffers::NativeTable { + typedef SkipGramOptions TableType; + int32_t ngram_size = 0; + int32_t max_skip_size = 0; + bool include_all_ngrams = false; +}; + +struct SkipGramOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SkipGramOptionsT NativeTableType; + typedef SkipGramOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NGRAM_SIZE = 4, + VT_MAX_SKIP_SIZE = 6, + VT_INCLUDE_ALL_NGRAMS = 8 + }; + int32_t ngram_size() const { + return GetField(VT_NGRAM_SIZE, 0); + } + int32_t max_skip_size() const { + return GetField(VT_MAX_SKIP_SIZE, 0); + } + bool include_all_ngrams() const { + return GetField(VT_INCLUDE_ALL_NGRAMS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_NGRAM_SIZE, 4) && + VerifyField(verifier, VT_MAX_SKIP_SIZE, 4) && + VerifyField(verifier, VT_INCLUDE_ALL_NGRAMS, 1) && + verifier.EndTable(); + } + SkipGramOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SkipGramOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SkipGramOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SkipGramOptionsBuilder { + typedef SkipGramOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_ngram_size(int32_t ngram_size) { + fbb_.AddElement(SkipGramOptions::VT_NGRAM_SIZE, ngram_size, 0); + } + void add_max_skip_size(int32_t max_skip_size) { + fbb_.AddElement(SkipGramOptions::VT_MAX_SKIP_SIZE, max_skip_size, 0); + } + void add_include_all_ngrams(bool include_all_ngrams) { + fbb_.AddElement(SkipGramOptions::VT_INCLUDE_ALL_NGRAMS, static_cast(include_all_ngrams), 0); + } + explicit SkipGramOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSkipGramOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t ngram_size = 0, + int32_t max_skip_size = 0, + bool include_all_ngrams = false) { + SkipGramOptionsBuilder builder_(_fbb); + builder_.add_max_skip_size(max_skip_size); + builder_.add_ngram_size(ngram_size); + builder_.add_include_all_ngrams(include_all_ngrams); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSkipGramOptions(flatbuffers::FlatBufferBuilder &_fbb, const SkipGramOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SpaceToDepthOptionsT : public flatbuffers::NativeTable { + typedef SpaceToDepthOptions TableType; + int32_t block_size = 0; +}; + +struct SpaceToDepthOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SpaceToDepthOptionsT NativeTableType; + typedef SpaceToDepthOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_BLOCK_SIZE = 4 + }; + int32_t block_size() const { + return GetField(VT_BLOCK_SIZE, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_BLOCK_SIZE, 4) && + verifier.EndTable(); + } + SpaceToDepthOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SpaceToDepthOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToDepthOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SpaceToDepthOptionsBuilder { + typedef SpaceToDepthOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_block_size(int32_t block_size) { + fbb_.AddElement(SpaceToDepthOptions::VT_BLOCK_SIZE, block_size, 0); + } + explicit SpaceToDepthOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSpaceToDepthOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t block_size = 0) { + SpaceToDepthOptionsBuilder builder_(_fbb); + builder_.add_block_size(block_size); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSpaceToDepthOptions(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToDepthOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct DepthToSpaceOptionsT : public flatbuffers::NativeTable { + typedef DepthToSpaceOptions TableType; + int32_t block_size = 0; +}; + +struct DepthToSpaceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef DepthToSpaceOptionsT NativeTableType; + typedef DepthToSpaceOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_BLOCK_SIZE = 4 + }; + int32_t block_size() const { + return GetField(VT_BLOCK_SIZE, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_BLOCK_SIZE, 4) && + verifier.EndTable(); + } + DepthToSpaceOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(DepthToSpaceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const DepthToSpaceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct DepthToSpaceOptionsBuilder { + typedef DepthToSpaceOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_block_size(int32_t block_size) { + fbb_.AddElement(DepthToSpaceOptions::VT_BLOCK_SIZE, block_size, 0); + } + explicit DepthToSpaceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateDepthToSpaceOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t block_size = 0) { + DepthToSpaceOptionsBuilder builder_(_fbb); + builder_.add_block_size(block_size); + return builder_.Finish(); +} + +flatbuffers::Offset CreateDepthToSpaceOptions(flatbuffers::FlatBufferBuilder &_fbb, const DepthToSpaceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SubOptionsT : public flatbuffers::NativeTable { + typedef SubOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; + bool pot_scale_int16 = true; +}; + +struct SubOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SubOptionsT NativeTableType; + typedef SubOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4, + VT_POT_SCALE_INT16 = 6 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool pot_scale_int16() const { + return GetField(VT_POT_SCALE_INT16, 1) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + VerifyField(verifier, VT_POT_SCALE_INT16, 1) && + verifier.EndTable(); + } + SubOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SubOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SubOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SubOptionsBuilder { + typedef SubOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(SubOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + void add_pot_scale_int16(bool pot_scale_int16) { + fbb_.AddElement(SubOptions::VT_POT_SCALE_INT16, static_cast(pot_scale_int16), 1); + } + explicit SubOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSubOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE, + bool pot_scale_int16 = true) { + SubOptionsBuilder builder_(_fbb); + builder_.add_pot_scale_int16(pot_scale_int16); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSubOptions(flatbuffers::FlatBufferBuilder &_fbb, const SubOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct DivOptionsT : public flatbuffers::NativeTable { + typedef DivOptions TableType; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; +}; + +struct DivOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef DivOptionsT NativeTableType; + typedef DivOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_FUSED_ACTIVATION_FUNCTION = 4 + }; + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + verifier.EndTable(); + } + DivOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(DivOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const DivOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct DivOptionsBuilder { + typedef DivOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(DivOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + explicit DivOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateDivOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE) { + DivOptionsBuilder builder_(_fbb); + builder_.add_fused_activation_function(fused_activation_function); + return builder_.Finish(); +} + +flatbuffers::Offset CreateDivOptions(flatbuffers::FlatBufferBuilder &_fbb, const DivOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct TopKV2OptionsT : public flatbuffers::NativeTable { + typedef TopKV2Options TableType; +}; + +struct TopKV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef TopKV2OptionsT NativeTableType; + typedef TopKV2OptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + TopKV2OptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(TopKV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const TopKV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct TopKV2OptionsBuilder { + typedef TopKV2Options Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit TopKV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateTopKV2Options( + flatbuffers::FlatBufferBuilder &_fbb) { + TopKV2OptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateTopKV2Options(flatbuffers::FlatBufferBuilder &_fbb, const TopKV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct EmbeddingLookupSparseOptionsT : public flatbuffers::NativeTable { + typedef EmbeddingLookupSparseOptions TableType; + tflite::CombinerType combiner = tflite::CombinerType_SUM; +}; + +struct EmbeddingLookupSparseOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef EmbeddingLookupSparseOptionsT NativeTableType; + typedef EmbeddingLookupSparseOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_COMBINER = 4 + }; + tflite::CombinerType combiner() const { + return static_cast(GetField(VT_COMBINER, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_COMBINER, 1) && + verifier.EndTable(); + } + EmbeddingLookupSparseOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(EmbeddingLookupSparseOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const EmbeddingLookupSparseOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct EmbeddingLookupSparseOptionsBuilder { + typedef EmbeddingLookupSparseOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_combiner(tflite::CombinerType combiner) { + fbb_.AddElement(EmbeddingLookupSparseOptions::VT_COMBINER, static_cast(combiner), 0); + } + explicit EmbeddingLookupSparseOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateEmbeddingLookupSparseOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::CombinerType combiner = tflite::CombinerType_SUM) { + EmbeddingLookupSparseOptionsBuilder builder_(_fbb); + builder_.add_combiner(combiner); + return builder_.Finish(); +} + +flatbuffers::Offset CreateEmbeddingLookupSparseOptions(flatbuffers::FlatBufferBuilder &_fbb, const EmbeddingLookupSparseOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct GatherOptionsT : public flatbuffers::NativeTable { + typedef GatherOptions TableType; + int32_t axis = 0; + int32_t batch_dims = 0; +}; + +struct GatherOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef GatherOptionsT NativeTableType; + typedef GatherOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_AXIS = 4, + VT_BATCH_DIMS = 6 + }; + int32_t axis() const { + return GetField(VT_AXIS, 0); + } + int32_t batch_dims() const { + return GetField(VT_BATCH_DIMS, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_AXIS, 4) && + VerifyField(verifier, VT_BATCH_DIMS, 4) && + verifier.EndTable(); + } + GatherOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(GatherOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const GatherOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct GatherOptionsBuilder { + typedef GatherOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_axis(int32_t axis) { + fbb_.AddElement(GatherOptions::VT_AXIS, axis, 0); + } + void add_batch_dims(int32_t batch_dims) { + fbb_.AddElement(GatherOptions::VT_BATCH_DIMS, batch_dims, 0); + } + explicit GatherOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateGatherOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t axis = 0, + int32_t batch_dims = 0) { + GatherOptionsBuilder builder_(_fbb); + builder_.add_batch_dims(batch_dims); + builder_.add_axis(axis); + return builder_.Finish(); +} + +flatbuffers::Offset CreateGatherOptions(flatbuffers::FlatBufferBuilder &_fbb, const GatherOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct TransposeOptionsT : public flatbuffers::NativeTable { + typedef TransposeOptions TableType; +}; + +struct TransposeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef TransposeOptionsT NativeTableType; + typedef TransposeOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + TransposeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(TransposeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const TransposeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct TransposeOptionsBuilder { + typedef TransposeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit TransposeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateTransposeOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + TransposeOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateTransposeOptions(flatbuffers::FlatBufferBuilder &_fbb, const TransposeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ExpOptionsT : public flatbuffers::NativeTable { + typedef ExpOptions TableType; +}; + +struct ExpOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ExpOptionsT NativeTableType; + typedef ExpOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + ExpOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ExpOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ExpOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ExpOptionsBuilder { + typedef ExpOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit ExpOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateExpOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + ExpOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateExpOptions(flatbuffers::FlatBufferBuilder &_fbb, const ExpOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct CosOptionsT : public flatbuffers::NativeTable { + typedef CosOptions TableType; +}; + +struct CosOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef CosOptionsT NativeTableType; + typedef CosOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + CosOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(CosOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const CosOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct CosOptionsBuilder { + typedef CosOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit CosOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateCosOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + CosOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateCosOptions(flatbuffers::FlatBufferBuilder &_fbb, const CosOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ReducerOptionsT : public flatbuffers::NativeTable { + typedef ReducerOptions TableType; + bool keep_dims = false; +}; + +struct ReducerOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ReducerOptionsT NativeTableType; + typedef ReducerOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_KEEP_DIMS = 4 + }; + bool keep_dims() const { + return GetField(VT_KEEP_DIMS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_KEEP_DIMS, 1) && + verifier.EndTable(); + } + ReducerOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ReducerOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReducerOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ReducerOptionsBuilder { + typedef ReducerOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_keep_dims(bool keep_dims) { + fbb_.AddElement(ReducerOptions::VT_KEEP_DIMS, static_cast(keep_dims), 0); + } + explicit ReducerOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateReducerOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool keep_dims = false) { + ReducerOptionsBuilder builder_(_fbb); + builder_.add_keep_dims(keep_dims); + return builder_.Finish(); +} + +flatbuffers::Offset CreateReducerOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReducerOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SqueezeOptionsT : public flatbuffers::NativeTable { + typedef SqueezeOptions TableType; + std::vector squeeze_dims{}; +}; + +struct SqueezeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SqueezeOptionsT NativeTableType; + typedef SqueezeOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_SQUEEZE_DIMS = 4 + }; + const flatbuffers::Vector *squeeze_dims() const { + return GetPointer *>(VT_SQUEEZE_DIMS); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_SQUEEZE_DIMS) && + verifier.VerifyVector(squeeze_dims()) && + verifier.EndTable(); + } + SqueezeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SqueezeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SqueezeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SqueezeOptionsBuilder { + typedef SqueezeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_squeeze_dims(flatbuffers::Offset> squeeze_dims) { + fbb_.AddOffset(SqueezeOptions::VT_SQUEEZE_DIMS, squeeze_dims); + } + explicit SqueezeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSqueezeOptions( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> squeeze_dims = 0) { + SqueezeOptionsBuilder builder_(_fbb); + builder_.add_squeeze_dims(squeeze_dims); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateSqueezeOptionsDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *squeeze_dims = nullptr) { + auto squeeze_dims__ = squeeze_dims ? _fbb.CreateVector(*squeeze_dims) : 0; + return tflite::CreateSqueezeOptions( + _fbb, + squeeze_dims__); +} + +flatbuffers::Offset CreateSqueezeOptions(flatbuffers::FlatBufferBuilder &_fbb, const SqueezeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SplitOptionsT : public flatbuffers::NativeTable { + typedef SplitOptions TableType; + int32_t num_splits = 0; +}; + +struct SplitOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SplitOptionsT NativeTableType; + typedef SplitOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NUM_SPLITS = 4 + }; + int32_t num_splits() const { + return GetField(VT_NUM_SPLITS, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_NUM_SPLITS, 4) && + verifier.EndTable(); + } + SplitOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SplitOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SplitOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SplitOptionsBuilder { + typedef SplitOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_num_splits(int32_t num_splits) { + fbb_.AddElement(SplitOptions::VT_NUM_SPLITS, num_splits, 0); + } + explicit SplitOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSplitOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t num_splits = 0) { + SplitOptionsBuilder builder_(_fbb); + builder_.add_num_splits(num_splits); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSplitOptions(flatbuffers::FlatBufferBuilder &_fbb, const SplitOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SplitVOptionsT : public flatbuffers::NativeTable { + typedef SplitVOptions TableType; + int32_t num_splits = 0; +}; + +struct SplitVOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SplitVOptionsT NativeTableType; + typedef SplitVOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NUM_SPLITS = 4 + }; + int32_t num_splits() const { + return GetField(VT_NUM_SPLITS, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_NUM_SPLITS, 4) && + verifier.EndTable(); + } + SplitVOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SplitVOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SplitVOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SplitVOptionsBuilder { + typedef SplitVOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_num_splits(int32_t num_splits) { + fbb_.AddElement(SplitVOptions::VT_NUM_SPLITS, num_splits, 0); + } + explicit SplitVOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSplitVOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t num_splits = 0) { + SplitVOptionsBuilder builder_(_fbb); + builder_.add_num_splits(num_splits); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSplitVOptions(flatbuffers::FlatBufferBuilder &_fbb, const SplitVOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct StridedSliceOptionsT : public flatbuffers::NativeTable { + typedef StridedSliceOptions TableType; + int32_t begin_mask = 0; + int32_t end_mask = 0; + int32_t ellipsis_mask = 0; + int32_t new_axis_mask = 0; + int32_t shrink_axis_mask = 0; +}; + +struct StridedSliceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef StridedSliceOptionsT NativeTableType; + typedef StridedSliceOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_BEGIN_MASK = 4, + VT_END_MASK = 6, + VT_ELLIPSIS_MASK = 8, + VT_NEW_AXIS_MASK = 10, + VT_SHRINK_AXIS_MASK = 12 + }; + int32_t begin_mask() const { + return GetField(VT_BEGIN_MASK, 0); + } + int32_t end_mask() const { + return GetField(VT_END_MASK, 0); + } + int32_t ellipsis_mask() const { + return GetField(VT_ELLIPSIS_MASK, 0); + } + int32_t new_axis_mask() const { + return GetField(VT_NEW_AXIS_MASK, 0); + } + int32_t shrink_axis_mask() const { + return GetField(VT_SHRINK_AXIS_MASK, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_BEGIN_MASK, 4) && + VerifyField(verifier, VT_END_MASK, 4) && + VerifyField(verifier, VT_ELLIPSIS_MASK, 4) && + VerifyField(verifier, VT_NEW_AXIS_MASK, 4) && + VerifyField(verifier, VT_SHRINK_AXIS_MASK, 4) && + verifier.EndTable(); + } + StridedSliceOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(StridedSliceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const StridedSliceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct StridedSliceOptionsBuilder { + typedef StridedSliceOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_begin_mask(int32_t begin_mask) { + fbb_.AddElement(StridedSliceOptions::VT_BEGIN_MASK, begin_mask, 0); + } + void add_end_mask(int32_t end_mask) { + fbb_.AddElement(StridedSliceOptions::VT_END_MASK, end_mask, 0); + } + void add_ellipsis_mask(int32_t ellipsis_mask) { + fbb_.AddElement(StridedSliceOptions::VT_ELLIPSIS_MASK, ellipsis_mask, 0); + } + void add_new_axis_mask(int32_t new_axis_mask) { + fbb_.AddElement(StridedSliceOptions::VT_NEW_AXIS_MASK, new_axis_mask, 0); + } + void add_shrink_axis_mask(int32_t shrink_axis_mask) { + fbb_.AddElement(StridedSliceOptions::VT_SHRINK_AXIS_MASK, shrink_axis_mask, 0); + } + explicit StridedSliceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateStridedSliceOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t begin_mask = 0, + int32_t end_mask = 0, + int32_t ellipsis_mask = 0, + int32_t new_axis_mask = 0, + int32_t shrink_axis_mask = 0) { + StridedSliceOptionsBuilder builder_(_fbb); + builder_.add_shrink_axis_mask(shrink_axis_mask); + builder_.add_new_axis_mask(new_axis_mask); + builder_.add_ellipsis_mask(ellipsis_mask); + builder_.add_end_mask(end_mask); + builder_.add_begin_mask(begin_mask); + return builder_.Finish(); +} + +flatbuffers::Offset CreateStridedSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, const StridedSliceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LogSoftmaxOptionsT : public flatbuffers::NativeTable { + typedef LogSoftmaxOptions TableType; +}; + +struct LogSoftmaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LogSoftmaxOptionsT NativeTableType; + typedef LogSoftmaxOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + LogSoftmaxOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LogSoftmaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogSoftmaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LogSoftmaxOptionsBuilder { + typedef LogSoftmaxOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit LogSoftmaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLogSoftmaxOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + LogSoftmaxOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLogSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogSoftmaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct CastOptionsT : public flatbuffers::NativeTable { + typedef CastOptions TableType; + tflite::TensorType in_data_type = tflite::TensorType_FLOAT32; + tflite::TensorType out_data_type = tflite::TensorType_FLOAT32; +}; + +struct CastOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef CastOptionsT NativeTableType; + typedef CastOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_IN_DATA_TYPE = 4, + VT_OUT_DATA_TYPE = 6 + }; + tflite::TensorType in_data_type() const { + return static_cast(GetField(VT_IN_DATA_TYPE, 0)); + } + tflite::TensorType out_data_type() const { + return static_cast(GetField(VT_OUT_DATA_TYPE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_IN_DATA_TYPE, 1) && + VerifyField(verifier, VT_OUT_DATA_TYPE, 1) && + verifier.EndTable(); + } + CastOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(CastOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const CastOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct CastOptionsBuilder { + typedef CastOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_in_data_type(tflite::TensorType in_data_type) { + fbb_.AddElement(CastOptions::VT_IN_DATA_TYPE, static_cast(in_data_type), 0); + } + void add_out_data_type(tflite::TensorType out_data_type) { + fbb_.AddElement(CastOptions::VT_OUT_DATA_TYPE, static_cast(out_data_type), 0); + } + explicit CastOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateCastOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::TensorType in_data_type = tflite::TensorType_FLOAT32, + tflite::TensorType out_data_type = tflite::TensorType_FLOAT32) { + CastOptionsBuilder builder_(_fbb); + builder_.add_out_data_type(out_data_type); + builder_.add_in_data_type(in_data_type); + return builder_.Finish(); +} + +flatbuffers::Offset CreateCastOptions(flatbuffers::FlatBufferBuilder &_fbb, const CastOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct DequantizeOptionsT : public flatbuffers::NativeTable { + typedef DequantizeOptions TableType; +}; + +struct DequantizeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef DequantizeOptionsT NativeTableType; + typedef DequantizeOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + DequantizeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(DequantizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const DequantizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct DequantizeOptionsBuilder { + typedef DequantizeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit DequantizeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateDequantizeOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + DequantizeOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateDequantizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const DequantizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct MaximumMinimumOptionsT : public flatbuffers::NativeTable { + typedef MaximumMinimumOptions TableType; +}; + +struct MaximumMinimumOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef MaximumMinimumOptionsT NativeTableType; + typedef MaximumMinimumOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + MaximumMinimumOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(MaximumMinimumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const MaximumMinimumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct MaximumMinimumOptionsBuilder { + typedef MaximumMinimumOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit MaximumMinimumOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateMaximumMinimumOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + MaximumMinimumOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateMaximumMinimumOptions(flatbuffers::FlatBufferBuilder &_fbb, const MaximumMinimumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct TileOptionsT : public flatbuffers::NativeTable { + typedef TileOptions TableType; +}; + +struct TileOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef TileOptionsT NativeTableType; + typedef TileOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + TileOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(TileOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const TileOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct TileOptionsBuilder { + typedef TileOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit TileOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateTileOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + TileOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateTileOptions(flatbuffers::FlatBufferBuilder &_fbb, const TileOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ArgMaxOptionsT : public flatbuffers::NativeTable { + typedef ArgMaxOptions TableType; + tflite::TensorType output_type = tflite::TensorType_FLOAT32; +}; + +struct ArgMaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ArgMaxOptionsT NativeTableType; + typedef ArgMaxOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_OUTPUT_TYPE = 4 + }; + tflite::TensorType output_type() const { + return static_cast(GetField(VT_OUTPUT_TYPE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_OUTPUT_TYPE, 1) && + verifier.EndTable(); + } + ArgMaxOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ArgMaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ArgMaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ArgMaxOptionsBuilder { + typedef ArgMaxOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_output_type(tflite::TensorType output_type) { + fbb_.AddElement(ArgMaxOptions::VT_OUTPUT_TYPE, static_cast(output_type), 0); + } + explicit ArgMaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateArgMaxOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::TensorType output_type = tflite::TensorType_FLOAT32) { + ArgMaxOptionsBuilder builder_(_fbb); + builder_.add_output_type(output_type); + return builder_.Finish(); +} + +flatbuffers::Offset CreateArgMaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const ArgMaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ArgMinOptionsT : public flatbuffers::NativeTable { + typedef ArgMinOptions TableType; + tflite::TensorType output_type = tflite::TensorType_FLOAT32; +}; + +struct ArgMinOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ArgMinOptionsT NativeTableType; + typedef ArgMinOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_OUTPUT_TYPE = 4 + }; + tflite::TensorType output_type() const { + return static_cast(GetField(VT_OUTPUT_TYPE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_OUTPUT_TYPE, 1) && + verifier.EndTable(); + } + ArgMinOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ArgMinOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ArgMinOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ArgMinOptionsBuilder { + typedef ArgMinOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_output_type(tflite::TensorType output_type) { + fbb_.AddElement(ArgMinOptions::VT_OUTPUT_TYPE, static_cast(output_type), 0); + } + explicit ArgMinOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateArgMinOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::TensorType output_type = tflite::TensorType_FLOAT32) { + ArgMinOptionsBuilder builder_(_fbb); + builder_.add_output_type(output_type); + return builder_.Finish(); +} + +flatbuffers::Offset CreateArgMinOptions(flatbuffers::FlatBufferBuilder &_fbb, const ArgMinOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct GreaterOptionsT : public flatbuffers::NativeTable { + typedef GreaterOptions TableType; +}; + +struct GreaterOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef GreaterOptionsT NativeTableType; + typedef GreaterOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + GreaterOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(GreaterOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const GreaterOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct GreaterOptionsBuilder { + typedef GreaterOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit GreaterOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateGreaterOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + GreaterOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateGreaterOptions(flatbuffers::FlatBufferBuilder &_fbb, const GreaterOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct GreaterEqualOptionsT : public flatbuffers::NativeTable { + typedef GreaterEqualOptions TableType; +}; + +struct GreaterEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef GreaterEqualOptionsT NativeTableType; + typedef GreaterEqualOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + GreaterEqualOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(GreaterEqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const GreaterEqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct GreaterEqualOptionsBuilder { + typedef GreaterEqualOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit GreaterEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateGreaterEqualOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + GreaterEqualOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateGreaterEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const GreaterEqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LessOptionsT : public flatbuffers::NativeTable { + typedef LessOptions TableType; +}; + +struct LessOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LessOptionsT NativeTableType; + typedef LessOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + LessOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LessOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LessOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LessOptionsBuilder { + typedef LessOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit LessOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLessOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + LessOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLessOptions(flatbuffers::FlatBufferBuilder &_fbb, const LessOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LessEqualOptionsT : public flatbuffers::NativeTable { + typedef LessEqualOptions TableType; +}; + +struct LessEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LessEqualOptionsT NativeTableType; + typedef LessEqualOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + LessEqualOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LessEqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LessEqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LessEqualOptionsBuilder { + typedef LessEqualOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit LessEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLessEqualOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + LessEqualOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLessEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const LessEqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct NegOptionsT : public flatbuffers::NativeTable { + typedef NegOptions TableType; +}; + +struct NegOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef NegOptionsT NativeTableType; + typedef NegOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + NegOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(NegOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const NegOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct NegOptionsBuilder { + typedef NegOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit NegOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateNegOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + NegOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateNegOptions(flatbuffers::FlatBufferBuilder &_fbb, const NegOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SelectOptionsT : public flatbuffers::NativeTable { + typedef SelectOptions TableType; +}; + +struct SelectOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SelectOptionsT NativeTableType; + typedef SelectOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SelectOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SelectOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SelectOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SelectOptionsBuilder { + typedef SelectOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SelectOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSelectOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + SelectOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSelectOptions(flatbuffers::FlatBufferBuilder &_fbb, const SelectOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SliceOptionsT : public flatbuffers::NativeTable { + typedef SliceOptions TableType; +}; + +struct SliceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SliceOptionsT NativeTableType; + typedef SliceOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SliceOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SliceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SliceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SliceOptionsBuilder { + typedef SliceOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SliceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSliceOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + SliceOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, const SliceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct TransposeConvOptionsT : public flatbuffers::NativeTable { + typedef TransposeConvOptions TableType; + tflite::Padding padding = tflite::Padding_SAME; + int32_t stride_w = 0; + int32_t stride_h = 0; + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE; +}; + +struct TransposeConvOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef TransposeConvOptionsT NativeTableType; + typedef TransposeConvOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_PADDING = 4, + VT_STRIDE_W = 6, + VT_STRIDE_H = 8, + VT_FUSED_ACTIVATION_FUNCTION = 10 + }; + tflite::Padding padding() const { + return static_cast(GetField(VT_PADDING, 0)); + } + int32_t stride_w() const { + return GetField(VT_STRIDE_W, 0); + } + int32_t stride_h() const { + return GetField(VT_STRIDE_H, 0); + } + tflite::ActivationFunctionType fused_activation_function() const { + return static_cast(GetField(VT_FUSED_ACTIVATION_FUNCTION, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_PADDING, 1) && + VerifyField(verifier, VT_STRIDE_W, 4) && + VerifyField(verifier, VT_STRIDE_H, 4) && + VerifyField(verifier, VT_FUSED_ACTIVATION_FUNCTION, 1) && + verifier.EndTable(); + } + TransposeConvOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(TransposeConvOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const TransposeConvOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct TransposeConvOptionsBuilder { + typedef TransposeConvOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_padding(tflite::Padding padding) { + fbb_.AddElement(TransposeConvOptions::VT_PADDING, static_cast(padding), 0); + } + void add_stride_w(int32_t stride_w) { + fbb_.AddElement(TransposeConvOptions::VT_STRIDE_W, stride_w, 0); + } + void add_stride_h(int32_t stride_h) { + fbb_.AddElement(TransposeConvOptions::VT_STRIDE_H, stride_h, 0); + } + void add_fused_activation_function(tflite::ActivationFunctionType fused_activation_function) { + fbb_.AddElement(TransposeConvOptions::VT_FUSED_ACTIVATION_FUNCTION, static_cast(fused_activation_function), 0); + } + explicit TransposeConvOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateTransposeConvOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::Padding padding = tflite::Padding_SAME, + int32_t stride_w = 0, + int32_t stride_h = 0, + tflite::ActivationFunctionType fused_activation_function = tflite::ActivationFunctionType_NONE) { + TransposeConvOptionsBuilder builder_(_fbb); + builder_.add_stride_h(stride_h); + builder_.add_stride_w(stride_w); + builder_.add_fused_activation_function(fused_activation_function); + builder_.add_padding(padding); + return builder_.Finish(); +} + +flatbuffers::Offset CreateTransposeConvOptions(flatbuffers::FlatBufferBuilder &_fbb, const TransposeConvOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ExpandDimsOptionsT : public flatbuffers::NativeTable { + typedef ExpandDimsOptions TableType; +}; + +struct ExpandDimsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ExpandDimsOptionsT NativeTableType; + typedef ExpandDimsOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + ExpandDimsOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ExpandDimsOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ExpandDimsOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ExpandDimsOptionsBuilder { + typedef ExpandDimsOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit ExpandDimsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateExpandDimsOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + ExpandDimsOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateExpandDimsOptions(flatbuffers::FlatBufferBuilder &_fbb, const ExpandDimsOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SparseToDenseOptionsT : public flatbuffers::NativeTable { + typedef SparseToDenseOptions TableType; + bool validate_indices = false; +}; + +struct SparseToDenseOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SparseToDenseOptionsT NativeTableType; + typedef SparseToDenseOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_VALIDATE_INDICES = 4 + }; + bool validate_indices() const { + return GetField(VT_VALIDATE_INDICES, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_VALIDATE_INDICES, 1) && + verifier.EndTable(); + } + SparseToDenseOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SparseToDenseOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SparseToDenseOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SparseToDenseOptionsBuilder { + typedef SparseToDenseOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_validate_indices(bool validate_indices) { + fbb_.AddElement(SparseToDenseOptions::VT_VALIDATE_INDICES, static_cast(validate_indices), 0); + } + explicit SparseToDenseOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSparseToDenseOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool validate_indices = false) { + SparseToDenseOptionsBuilder builder_(_fbb); + builder_.add_validate_indices(validate_indices); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSparseToDenseOptions(flatbuffers::FlatBufferBuilder &_fbb, const SparseToDenseOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct EqualOptionsT : public flatbuffers::NativeTable { + typedef EqualOptions TableType; +}; + +struct EqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef EqualOptionsT NativeTableType; + typedef EqualOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + EqualOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(EqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const EqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct EqualOptionsBuilder { + typedef EqualOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit EqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateEqualOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + EqualOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const EqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct NotEqualOptionsT : public flatbuffers::NativeTable { + typedef NotEqualOptions TableType; +}; + +struct NotEqualOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef NotEqualOptionsT NativeTableType; + typedef NotEqualOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + NotEqualOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(NotEqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const NotEqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct NotEqualOptionsBuilder { + typedef NotEqualOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit NotEqualOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateNotEqualOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + NotEqualOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateNotEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const NotEqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ShapeOptionsT : public flatbuffers::NativeTable { + typedef ShapeOptions TableType; + tflite::TensorType out_type = tflite::TensorType_FLOAT32; +}; + +struct ShapeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ShapeOptionsT NativeTableType; + typedef ShapeOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_OUT_TYPE = 4 + }; + tflite::TensorType out_type() const { + return static_cast(GetField(VT_OUT_TYPE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_OUT_TYPE, 1) && + verifier.EndTable(); + } + ShapeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ShapeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ShapeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ShapeOptionsBuilder { + typedef ShapeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_out_type(tflite::TensorType out_type) { + fbb_.AddElement(ShapeOptions::VT_OUT_TYPE, static_cast(out_type), 0); + } + explicit ShapeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateShapeOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::TensorType out_type = tflite::TensorType_FLOAT32) { + ShapeOptionsBuilder builder_(_fbb); + builder_.add_out_type(out_type); + return builder_.Finish(); +} + +flatbuffers::Offset CreateShapeOptions(flatbuffers::FlatBufferBuilder &_fbb, const ShapeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct RankOptionsT : public flatbuffers::NativeTable { + typedef RankOptions TableType; +}; + +struct RankOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef RankOptionsT NativeTableType; + typedef RankOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + RankOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(RankOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const RankOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct RankOptionsBuilder { + typedef RankOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit RankOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateRankOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + RankOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateRankOptions(flatbuffers::FlatBufferBuilder &_fbb, const RankOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct PowOptionsT : public flatbuffers::NativeTable { + typedef PowOptions TableType; +}; + +struct PowOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef PowOptionsT NativeTableType; + typedef PowOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + PowOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(PowOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const PowOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct PowOptionsBuilder { + typedef PowOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit PowOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreatePowOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + PowOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreatePowOptions(flatbuffers::FlatBufferBuilder &_fbb, const PowOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct FakeQuantOptionsT : public flatbuffers::NativeTable { + typedef FakeQuantOptions TableType; + float min = 0.0f; + float max = 0.0f; + int32_t num_bits = 0; + bool narrow_range = false; +}; + +struct FakeQuantOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef FakeQuantOptionsT NativeTableType; + typedef FakeQuantOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_MIN = 4, + VT_MAX = 6, + VT_NUM_BITS = 8, + VT_NARROW_RANGE = 10 + }; + float min() const { + return GetField(VT_MIN, 0.0f); + } + float max() const { + return GetField(VT_MAX, 0.0f); + } + int32_t num_bits() const { + return GetField(VT_NUM_BITS, 0); + } + bool narrow_range() const { + return GetField(VT_NARROW_RANGE, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_MIN, 4) && + VerifyField(verifier, VT_MAX, 4) && + VerifyField(verifier, VT_NUM_BITS, 4) && + VerifyField(verifier, VT_NARROW_RANGE, 1) && + verifier.EndTable(); + } + FakeQuantOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(FakeQuantOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const FakeQuantOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct FakeQuantOptionsBuilder { + typedef FakeQuantOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_min(float min) { + fbb_.AddElement(FakeQuantOptions::VT_MIN, min, 0.0f); + } + void add_max(float max) { + fbb_.AddElement(FakeQuantOptions::VT_MAX, max, 0.0f); + } + void add_num_bits(int32_t num_bits) { + fbb_.AddElement(FakeQuantOptions::VT_NUM_BITS, num_bits, 0); + } + void add_narrow_range(bool narrow_range) { + fbb_.AddElement(FakeQuantOptions::VT_NARROW_RANGE, static_cast(narrow_range), 0); + } + explicit FakeQuantOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateFakeQuantOptions( + flatbuffers::FlatBufferBuilder &_fbb, + float min = 0.0f, + float max = 0.0f, + int32_t num_bits = 0, + bool narrow_range = false) { + FakeQuantOptionsBuilder builder_(_fbb); + builder_.add_num_bits(num_bits); + builder_.add_max(max); + builder_.add_min(min); + builder_.add_narrow_range(narrow_range); + return builder_.Finish(); +} + +flatbuffers::Offset CreateFakeQuantOptions(flatbuffers::FlatBufferBuilder &_fbb, const FakeQuantOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct PackOptionsT : public flatbuffers::NativeTable { + typedef PackOptions TableType; + int32_t values_count = 0; + int32_t axis = 0; +}; + +struct PackOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef PackOptionsT NativeTableType; + typedef PackOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_VALUES_COUNT = 4, + VT_AXIS = 6 + }; + int32_t values_count() const { + return GetField(VT_VALUES_COUNT, 0); + } + int32_t axis() const { + return GetField(VT_AXIS, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_VALUES_COUNT, 4) && + VerifyField(verifier, VT_AXIS, 4) && + verifier.EndTable(); + } + PackOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(PackOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const PackOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct PackOptionsBuilder { + typedef PackOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_values_count(int32_t values_count) { + fbb_.AddElement(PackOptions::VT_VALUES_COUNT, values_count, 0); + } + void add_axis(int32_t axis) { + fbb_.AddElement(PackOptions::VT_AXIS, axis, 0); + } + explicit PackOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreatePackOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t values_count = 0, + int32_t axis = 0) { + PackOptionsBuilder builder_(_fbb); + builder_.add_axis(axis); + builder_.add_values_count(values_count); + return builder_.Finish(); +} + +flatbuffers::Offset CreatePackOptions(flatbuffers::FlatBufferBuilder &_fbb, const PackOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LogicalOrOptionsT : public flatbuffers::NativeTable { + typedef LogicalOrOptions TableType; +}; + +struct LogicalOrOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LogicalOrOptionsT NativeTableType; + typedef LogicalOrOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + LogicalOrOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LogicalOrOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogicalOrOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LogicalOrOptionsBuilder { + typedef LogicalOrOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit LogicalOrOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLogicalOrOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + LogicalOrOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLogicalOrOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogicalOrOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct OneHotOptionsT : public flatbuffers::NativeTable { + typedef OneHotOptions TableType; + int32_t axis = 0; +}; + +struct OneHotOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef OneHotOptionsT NativeTableType; + typedef OneHotOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_AXIS = 4 + }; + int32_t axis() const { + return GetField(VT_AXIS, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_AXIS, 4) && + verifier.EndTable(); + } + OneHotOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(OneHotOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const OneHotOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct OneHotOptionsBuilder { + typedef OneHotOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_axis(int32_t axis) { + fbb_.AddElement(OneHotOptions::VT_AXIS, axis, 0); + } + explicit OneHotOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateOneHotOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t axis = 0) { + OneHotOptionsBuilder builder_(_fbb); + builder_.add_axis(axis); + return builder_.Finish(); +} + +flatbuffers::Offset CreateOneHotOptions(flatbuffers::FlatBufferBuilder &_fbb, const OneHotOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct AbsOptionsT : public flatbuffers::NativeTable { + typedef AbsOptions TableType; +}; + +struct AbsOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef AbsOptionsT NativeTableType; + typedef AbsOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + AbsOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(AbsOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const AbsOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct AbsOptionsBuilder { + typedef AbsOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit AbsOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateAbsOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + AbsOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateAbsOptions(flatbuffers::FlatBufferBuilder &_fbb, const AbsOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct HardSwishOptionsT : public flatbuffers::NativeTable { + typedef HardSwishOptions TableType; +}; + +struct HardSwishOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef HardSwishOptionsT NativeTableType; + typedef HardSwishOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + HardSwishOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(HardSwishOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const HardSwishOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct HardSwishOptionsBuilder { + typedef HardSwishOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit HardSwishOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateHardSwishOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + HardSwishOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateHardSwishOptions(flatbuffers::FlatBufferBuilder &_fbb, const HardSwishOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LogicalAndOptionsT : public flatbuffers::NativeTable { + typedef LogicalAndOptions TableType; +}; + +struct LogicalAndOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LogicalAndOptionsT NativeTableType; + typedef LogicalAndOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + LogicalAndOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LogicalAndOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogicalAndOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LogicalAndOptionsBuilder { + typedef LogicalAndOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit LogicalAndOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLogicalAndOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + LogicalAndOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLogicalAndOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogicalAndOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LogicalNotOptionsT : public flatbuffers::NativeTable { + typedef LogicalNotOptions TableType; +}; + +struct LogicalNotOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LogicalNotOptionsT NativeTableType; + typedef LogicalNotOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + LogicalNotOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LogicalNotOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogicalNotOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LogicalNotOptionsBuilder { + typedef LogicalNotOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit LogicalNotOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLogicalNotOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + LogicalNotOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLogicalNotOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogicalNotOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct UnpackOptionsT : public flatbuffers::NativeTable { + typedef UnpackOptions TableType; + int32_t num = 0; + int32_t axis = 0; +}; + +struct UnpackOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef UnpackOptionsT NativeTableType; + typedef UnpackOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NUM = 4, + VT_AXIS = 6 + }; + int32_t num() const { + return GetField(VT_NUM, 0); + } + int32_t axis() const { + return GetField(VT_AXIS, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_NUM, 4) && + VerifyField(verifier, VT_AXIS, 4) && + verifier.EndTable(); + } + UnpackOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(UnpackOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnpackOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct UnpackOptionsBuilder { + typedef UnpackOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_num(int32_t num) { + fbb_.AddElement(UnpackOptions::VT_NUM, num, 0); + } + void add_axis(int32_t axis) { + fbb_.AddElement(UnpackOptions::VT_AXIS, axis, 0); + } + explicit UnpackOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUnpackOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t num = 0, + int32_t axis = 0) { + UnpackOptionsBuilder builder_(_fbb); + builder_.add_axis(axis); + builder_.add_num(num); + return builder_.Finish(); +} + +flatbuffers::Offset CreateUnpackOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnpackOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct FloorDivOptionsT : public flatbuffers::NativeTable { + typedef FloorDivOptions TableType; +}; + +struct FloorDivOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef FloorDivOptionsT NativeTableType; + typedef FloorDivOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + FloorDivOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(FloorDivOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const FloorDivOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct FloorDivOptionsBuilder { + typedef FloorDivOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit FloorDivOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateFloorDivOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + FloorDivOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateFloorDivOptions(flatbuffers::FlatBufferBuilder &_fbb, const FloorDivOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SquareOptionsT : public flatbuffers::NativeTable { + typedef SquareOptions TableType; +}; + +struct SquareOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SquareOptionsT NativeTableType; + typedef SquareOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SquareOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SquareOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SquareOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SquareOptionsBuilder { + typedef SquareOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SquareOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSquareOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + SquareOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSquareOptions(flatbuffers::FlatBufferBuilder &_fbb, const SquareOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ZerosLikeOptionsT : public flatbuffers::NativeTable { + typedef ZerosLikeOptions TableType; +}; + +struct ZerosLikeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ZerosLikeOptionsT NativeTableType; + typedef ZerosLikeOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + ZerosLikeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ZerosLikeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ZerosLikeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ZerosLikeOptionsBuilder { + typedef ZerosLikeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit ZerosLikeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateZerosLikeOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + ZerosLikeOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateZerosLikeOptions(flatbuffers::FlatBufferBuilder &_fbb, const ZerosLikeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct FillOptionsT : public flatbuffers::NativeTable { + typedef FillOptions TableType; +}; + +struct FillOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef FillOptionsT NativeTableType; + typedef FillOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + FillOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(FillOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const FillOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct FillOptionsBuilder { + typedef FillOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit FillOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateFillOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + FillOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateFillOptions(flatbuffers::FlatBufferBuilder &_fbb, const FillOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct FloorModOptionsT : public flatbuffers::NativeTable { + typedef FloorModOptions TableType; +}; + +struct FloorModOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef FloorModOptionsT NativeTableType; + typedef FloorModOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + FloorModOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(FloorModOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const FloorModOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct FloorModOptionsBuilder { + typedef FloorModOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit FloorModOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateFloorModOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + FloorModOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateFloorModOptions(flatbuffers::FlatBufferBuilder &_fbb, const FloorModOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct RangeOptionsT : public flatbuffers::NativeTable { + typedef RangeOptions TableType; +}; + +struct RangeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef RangeOptionsT NativeTableType; + typedef RangeOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + RangeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(RangeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const RangeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct RangeOptionsBuilder { + typedef RangeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit RangeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateRangeOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + RangeOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateRangeOptions(flatbuffers::FlatBufferBuilder &_fbb, const RangeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct LeakyReluOptionsT : public flatbuffers::NativeTable { + typedef LeakyReluOptions TableType; + float alpha = 0.0f; +}; + +struct LeakyReluOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef LeakyReluOptionsT NativeTableType; + typedef LeakyReluOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_ALPHA = 4 + }; + float alpha() const { + return GetField(VT_ALPHA, 0.0f); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_ALPHA, 4) && + verifier.EndTable(); + } + LeakyReluOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(LeakyReluOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const LeakyReluOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct LeakyReluOptionsBuilder { + typedef LeakyReluOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_alpha(float alpha) { + fbb_.AddElement(LeakyReluOptions::VT_ALPHA, alpha, 0.0f); + } + explicit LeakyReluOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateLeakyReluOptions( + flatbuffers::FlatBufferBuilder &_fbb, + float alpha = 0.0f) { + LeakyReluOptionsBuilder builder_(_fbb); + builder_.add_alpha(alpha); + return builder_.Finish(); +} + +flatbuffers::Offset CreateLeakyReluOptions(flatbuffers::FlatBufferBuilder &_fbb, const LeakyReluOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SquaredDifferenceOptionsT : public flatbuffers::NativeTable { + typedef SquaredDifferenceOptions TableType; +}; + +struct SquaredDifferenceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SquaredDifferenceOptionsT NativeTableType; + typedef SquaredDifferenceOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SquaredDifferenceOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SquaredDifferenceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SquaredDifferenceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SquaredDifferenceOptionsBuilder { + typedef SquaredDifferenceOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SquaredDifferenceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSquaredDifferenceOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + SquaredDifferenceOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSquaredDifferenceOptions(flatbuffers::FlatBufferBuilder &_fbb, const SquaredDifferenceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct MirrorPadOptionsT : public flatbuffers::NativeTable { + typedef MirrorPadOptions TableType; + tflite::MirrorPadMode mode = tflite::MirrorPadMode_REFLECT; +}; + +struct MirrorPadOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef MirrorPadOptionsT NativeTableType; + typedef MirrorPadOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_MODE = 4 + }; + tflite::MirrorPadMode mode() const { + return static_cast(GetField(VT_MODE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_MODE, 1) && + verifier.EndTable(); + } + MirrorPadOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(MirrorPadOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const MirrorPadOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct MirrorPadOptionsBuilder { + typedef MirrorPadOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_mode(tflite::MirrorPadMode mode) { + fbb_.AddElement(MirrorPadOptions::VT_MODE, static_cast(mode), 0); + } + explicit MirrorPadOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateMirrorPadOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::MirrorPadMode mode = tflite::MirrorPadMode_REFLECT) { + MirrorPadOptionsBuilder builder_(_fbb); + builder_.add_mode(mode); + return builder_.Finish(); +} + +flatbuffers::Offset CreateMirrorPadOptions(flatbuffers::FlatBufferBuilder &_fbb, const MirrorPadOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct UniqueOptionsT : public flatbuffers::NativeTable { + typedef UniqueOptions TableType; + tflite::TensorType idx_out_type = tflite::TensorType_INT32; +}; + +struct UniqueOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef UniqueOptionsT NativeTableType; + typedef UniqueOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_IDX_OUT_TYPE = 4 + }; + tflite::TensorType idx_out_type() const { + return static_cast(GetField(VT_IDX_OUT_TYPE, 2)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_IDX_OUT_TYPE, 1) && + verifier.EndTable(); + } + UniqueOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(UniqueOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const UniqueOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct UniqueOptionsBuilder { + typedef UniqueOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_idx_out_type(tflite::TensorType idx_out_type) { + fbb_.AddElement(UniqueOptions::VT_IDX_OUT_TYPE, static_cast(idx_out_type), 2); + } + explicit UniqueOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUniqueOptions( + flatbuffers::FlatBufferBuilder &_fbb, + tflite::TensorType idx_out_type = tflite::TensorType_INT32) { + UniqueOptionsBuilder builder_(_fbb); + builder_.add_idx_out_type(idx_out_type); + return builder_.Finish(); +} + +flatbuffers::Offset CreateUniqueOptions(flatbuffers::FlatBufferBuilder &_fbb, const UniqueOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ReverseV2OptionsT : public flatbuffers::NativeTable { + typedef ReverseV2Options TableType; +}; + +struct ReverseV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ReverseV2OptionsT NativeTableType; + typedef ReverseV2OptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + ReverseV2OptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ReverseV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReverseV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ReverseV2OptionsBuilder { + typedef ReverseV2Options Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit ReverseV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateReverseV2Options( + flatbuffers::FlatBufferBuilder &_fbb) { + ReverseV2OptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateReverseV2Options(flatbuffers::FlatBufferBuilder &_fbb, const ReverseV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct AddNOptionsT : public flatbuffers::NativeTable { + typedef AddNOptions TableType; +}; + +struct AddNOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef AddNOptionsT NativeTableType; + typedef AddNOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + AddNOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(AddNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const AddNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct AddNOptionsBuilder { + typedef AddNOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit AddNOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateAddNOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + AddNOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateAddNOptions(flatbuffers::FlatBufferBuilder &_fbb, const AddNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct GatherNdOptionsT : public flatbuffers::NativeTable { + typedef GatherNdOptions TableType; +}; + +struct GatherNdOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef GatherNdOptionsT NativeTableType; + typedef GatherNdOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + GatherNdOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(GatherNdOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const GatherNdOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct GatherNdOptionsBuilder { + typedef GatherNdOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit GatherNdOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateGatherNdOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + GatherNdOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateGatherNdOptions(flatbuffers::FlatBufferBuilder &_fbb, const GatherNdOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct WhereOptionsT : public flatbuffers::NativeTable { + typedef WhereOptions TableType; +}; + +struct WhereOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef WhereOptionsT NativeTableType; + typedef WhereOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + WhereOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(WhereOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const WhereOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct WhereOptionsBuilder { + typedef WhereOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit WhereOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateWhereOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + WhereOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateWhereOptions(flatbuffers::FlatBufferBuilder &_fbb, const WhereOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ReverseSequenceOptionsT : public flatbuffers::NativeTable { + typedef ReverseSequenceOptions TableType; + int32_t seq_dim = 0; + int32_t batch_dim = 0; +}; + +struct ReverseSequenceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ReverseSequenceOptionsT NativeTableType; + typedef ReverseSequenceOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_SEQ_DIM = 4, + VT_BATCH_DIM = 6 + }; + int32_t seq_dim() const { + return GetField(VT_SEQ_DIM, 0); + } + int32_t batch_dim() const { + return GetField(VT_BATCH_DIM, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_SEQ_DIM, 4) && + VerifyField(verifier, VT_BATCH_DIM, 4) && + verifier.EndTable(); + } + ReverseSequenceOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ReverseSequenceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReverseSequenceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ReverseSequenceOptionsBuilder { + typedef ReverseSequenceOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_seq_dim(int32_t seq_dim) { + fbb_.AddElement(ReverseSequenceOptions::VT_SEQ_DIM, seq_dim, 0); + } + void add_batch_dim(int32_t batch_dim) { + fbb_.AddElement(ReverseSequenceOptions::VT_BATCH_DIM, batch_dim, 0); + } + explicit ReverseSequenceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateReverseSequenceOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t seq_dim = 0, + int32_t batch_dim = 0) { + ReverseSequenceOptionsBuilder builder_(_fbb); + builder_.add_batch_dim(batch_dim); + builder_.add_seq_dim(seq_dim); + return builder_.Finish(); +} + +flatbuffers::Offset CreateReverseSequenceOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReverseSequenceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct MatrixDiagOptionsT : public flatbuffers::NativeTable { + typedef MatrixDiagOptions TableType; +}; + +struct MatrixDiagOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef MatrixDiagOptionsT NativeTableType; + typedef MatrixDiagOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + MatrixDiagOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(MatrixDiagOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const MatrixDiagOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct MatrixDiagOptionsBuilder { + typedef MatrixDiagOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit MatrixDiagOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateMatrixDiagOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + MatrixDiagOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateMatrixDiagOptions(flatbuffers::FlatBufferBuilder &_fbb, const MatrixDiagOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct QuantizeOptionsT : public flatbuffers::NativeTable { + typedef QuantizeOptions TableType; +}; + +struct QuantizeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef QuantizeOptionsT NativeTableType; + typedef QuantizeOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + QuantizeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(QuantizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const QuantizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct QuantizeOptionsBuilder { + typedef QuantizeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit QuantizeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateQuantizeOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + QuantizeOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateQuantizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const QuantizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct MatrixSetDiagOptionsT : public flatbuffers::NativeTable { + typedef MatrixSetDiagOptions TableType; +}; + +struct MatrixSetDiagOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef MatrixSetDiagOptionsT NativeTableType; + typedef MatrixSetDiagOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + MatrixSetDiagOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(MatrixSetDiagOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const MatrixSetDiagOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct MatrixSetDiagOptionsBuilder { + typedef MatrixSetDiagOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit MatrixSetDiagOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateMatrixSetDiagOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + MatrixSetDiagOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateMatrixSetDiagOptions(flatbuffers::FlatBufferBuilder &_fbb, const MatrixSetDiagOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct IfOptionsT : public flatbuffers::NativeTable { + typedef IfOptions TableType; + int32_t then_subgraph_index = 0; + int32_t else_subgraph_index = 0; +}; + +struct IfOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef IfOptionsT NativeTableType; + typedef IfOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_THEN_SUBGRAPH_INDEX = 4, + VT_ELSE_SUBGRAPH_INDEX = 6 + }; + int32_t then_subgraph_index() const { + return GetField(VT_THEN_SUBGRAPH_INDEX, 0); + } + int32_t else_subgraph_index() const { + return GetField(VT_ELSE_SUBGRAPH_INDEX, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_THEN_SUBGRAPH_INDEX, 4) && + VerifyField(verifier, VT_ELSE_SUBGRAPH_INDEX, 4) && + verifier.EndTable(); + } + IfOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(IfOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const IfOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct IfOptionsBuilder { + typedef IfOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_then_subgraph_index(int32_t then_subgraph_index) { + fbb_.AddElement(IfOptions::VT_THEN_SUBGRAPH_INDEX, then_subgraph_index, 0); + } + void add_else_subgraph_index(int32_t else_subgraph_index) { + fbb_.AddElement(IfOptions::VT_ELSE_SUBGRAPH_INDEX, else_subgraph_index, 0); + } + explicit IfOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateIfOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t then_subgraph_index = 0, + int32_t else_subgraph_index = 0) { + IfOptionsBuilder builder_(_fbb); + builder_.add_else_subgraph_index(else_subgraph_index); + builder_.add_then_subgraph_index(then_subgraph_index); + return builder_.Finish(); +} + +flatbuffers::Offset CreateIfOptions(flatbuffers::FlatBufferBuilder &_fbb, const IfOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct CallOnceOptionsT : public flatbuffers::NativeTable { + typedef CallOnceOptions TableType; + int32_t init_subgraph_index = 0; +}; + +struct CallOnceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef CallOnceOptionsT NativeTableType; + typedef CallOnceOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_INIT_SUBGRAPH_INDEX = 4 + }; + int32_t init_subgraph_index() const { + return GetField(VT_INIT_SUBGRAPH_INDEX, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_INIT_SUBGRAPH_INDEX, 4) && + verifier.EndTable(); + } + CallOnceOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(CallOnceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const CallOnceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct CallOnceOptionsBuilder { + typedef CallOnceOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_init_subgraph_index(int32_t init_subgraph_index) { + fbb_.AddElement(CallOnceOptions::VT_INIT_SUBGRAPH_INDEX, init_subgraph_index, 0); + } + explicit CallOnceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateCallOnceOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t init_subgraph_index = 0) { + CallOnceOptionsBuilder builder_(_fbb); + builder_.add_init_subgraph_index(init_subgraph_index); + return builder_.Finish(); +} + +flatbuffers::Offset CreateCallOnceOptions(flatbuffers::FlatBufferBuilder &_fbb, const CallOnceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct WhileOptionsT : public flatbuffers::NativeTable { + typedef WhileOptions TableType; + int32_t cond_subgraph_index = 0; + int32_t body_subgraph_index = 0; +}; + +struct WhileOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef WhileOptionsT NativeTableType; + typedef WhileOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_COND_SUBGRAPH_INDEX = 4, + VT_BODY_SUBGRAPH_INDEX = 6 + }; + int32_t cond_subgraph_index() const { + return GetField(VT_COND_SUBGRAPH_INDEX, 0); + } + int32_t body_subgraph_index() const { + return GetField(VT_BODY_SUBGRAPH_INDEX, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_COND_SUBGRAPH_INDEX, 4) && + VerifyField(verifier, VT_BODY_SUBGRAPH_INDEX, 4) && + verifier.EndTable(); + } + WhileOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(WhileOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const WhileOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct WhileOptionsBuilder { + typedef WhileOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_cond_subgraph_index(int32_t cond_subgraph_index) { + fbb_.AddElement(WhileOptions::VT_COND_SUBGRAPH_INDEX, cond_subgraph_index, 0); + } + void add_body_subgraph_index(int32_t body_subgraph_index) { + fbb_.AddElement(WhileOptions::VT_BODY_SUBGRAPH_INDEX, body_subgraph_index, 0); + } + explicit WhileOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateWhileOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t cond_subgraph_index = 0, + int32_t body_subgraph_index = 0) { + WhileOptionsBuilder builder_(_fbb); + builder_.add_body_subgraph_index(body_subgraph_index); + builder_.add_cond_subgraph_index(cond_subgraph_index); + return builder_.Finish(); +} + +flatbuffers::Offset CreateWhileOptions(flatbuffers::FlatBufferBuilder &_fbb, const WhileOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct NonMaxSuppressionV4OptionsT : public flatbuffers::NativeTable { + typedef NonMaxSuppressionV4Options TableType; +}; + +struct NonMaxSuppressionV4Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef NonMaxSuppressionV4OptionsT NativeTableType; + typedef NonMaxSuppressionV4OptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + NonMaxSuppressionV4OptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(NonMaxSuppressionV4OptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV4OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct NonMaxSuppressionV4OptionsBuilder { + typedef NonMaxSuppressionV4Options Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit NonMaxSuppressionV4OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateNonMaxSuppressionV4Options( + flatbuffers::FlatBufferBuilder &_fbb) { + NonMaxSuppressionV4OptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateNonMaxSuppressionV4Options(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV4OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct NonMaxSuppressionV5OptionsT : public flatbuffers::NativeTable { + typedef NonMaxSuppressionV5Options TableType; +}; + +struct NonMaxSuppressionV5Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef NonMaxSuppressionV5OptionsT NativeTableType; + typedef NonMaxSuppressionV5OptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + NonMaxSuppressionV5OptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(NonMaxSuppressionV5OptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV5OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct NonMaxSuppressionV5OptionsBuilder { + typedef NonMaxSuppressionV5Options Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit NonMaxSuppressionV5OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateNonMaxSuppressionV5Options( + flatbuffers::FlatBufferBuilder &_fbb) { + NonMaxSuppressionV5OptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateNonMaxSuppressionV5Options(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV5OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ScatterNdOptionsT : public flatbuffers::NativeTable { + typedef ScatterNdOptions TableType; +}; + +struct ScatterNdOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ScatterNdOptionsT NativeTableType; + typedef ScatterNdOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + ScatterNdOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ScatterNdOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ScatterNdOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ScatterNdOptionsBuilder { + typedef ScatterNdOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit ScatterNdOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateScatterNdOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + ScatterNdOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateScatterNdOptions(flatbuffers::FlatBufferBuilder &_fbb, const ScatterNdOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SelectV2OptionsT : public flatbuffers::NativeTable { + typedef SelectV2Options TableType; +}; + +struct SelectV2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SelectV2OptionsT NativeTableType; + typedef SelectV2OptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SelectV2OptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SelectV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SelectV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SelectV2OptionsBuilder { + typedef SelectV2Options Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SelectV2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSelectV2Options( + flatbuffers::FlatBufferBuilder &_fbb) { + SelectV2OptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSelectV2Options(flatbuffers::FlatBufferBuilder &_fbb, const SelectV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct DensifyOptionsT : public flatbuffers::NativeTable { + typedef DensifyOptions TableType; +}; + +struct DensifyOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef DensifyOptionsT NativeTableType; + typedef DensifyOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + DensifyOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(DensifyOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const DensifyOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct DensifyOptionsBuilder { + typedef DensifyOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit DensifyOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateDensifyOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + DensifyOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateDensifyOptions(flatbuffers::FlatBufferBuilder &_fbb, const DensifyOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SegmentSumOptionsT : public flatbuffers::NativeTable { + typedef SegmentSumOptions TableType; +}; + +struct SegmentSumOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SegmentSumOptionsT NativeTableType; + typedef SegmentSumOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SegmentSumOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SegmentSumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SegmentSumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SegmentSumOptionsBuilder { + typedef SegmentSumOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SegmentSumOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSegmentSumOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + SegmentSumOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSegmentSumOptions(flatbuffers::FlatBufferBuilder &_fbb, const SegmentSumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct BatchMatMulOptionsT : public flatbuffers::NativeTable { + typedef BatchMatMulOptions TableType; + bool adj_x = false; + bool adj_y = false; + bool asymmetric_quantize_inputs = false; +}; + +struct BatchMatMulOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef BatchMatMulOptionsT NativeTableType; + typedef BatchMatMulOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_ADJ_X = 4, + VT_ADJ_Y = 6, + VT_ASYMMETRIC_QUANTIZE_INPUTS = 8 + }; + bool adj_x() const { + return GetField(VT_ADJ_X, 0) != 0; + } + bool adj_y() const { + return GetField(VT_ADJ_Y, 0) != 0; + } + bool asymmetric_quantize_inputs() const { + return GetField(VT_ASYMMETRIC_QUANTIZE_INPUTS, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_ADJ_X, 1) && + VerifyField(verifier, VT_ADJ_Y, 1) && + VerifyField(verifier, VT_ASYMMETRIC_QUANTIZE_INPUTS, 1) && + verifier.EndTable(); + } + BatchMatMulOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(BatchMatMulOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const BatchMatMulOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct BatchMatMulOptionsBuilder { + typedef BatchMatMulOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_adj_x(bool adj_x) { + fbb_.AddElement(BatchMatMulOptions::VT_ADJ_X, static_cast(adj_x), 0); + } + void add_adj_y(bool adj_y) { + fbb_.AddElement(BatchMatMulOptions::VT_ADJ_Y, static_cast(adj_y), 0); + } + void add_asymmetric_quantize_inputs(bool asymmetric_quantize_inputs) { + fbb_.AddElement(BatchMatMulOptions::VT_ASYMMETRIC_QUANTIZE_INPUTS, static_cast(asymmetric_quantize_inputs), 0); + } + explicit BatchMatMulOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateBatchMatMulOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool adj_x = false, + bool adj_y = false, + bool asymmetric_quantize_inputs = false) { + BatchMatMulOptionsBuilder builder_(_fbb); + builder_.add_asymmetric_quantize_inputs(asymmetric_quantize_inputs); + builder_.add_adj_y(adj_y); + builder_.add_adj_x(adj_x); + return builder_.Finish(); +} + +flatbuffers::Offset CreateBatchMatMulOptions(flatbuffers::FlatBufferBuilder &_fbb, const BatchMatMulOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct CumsumOptionsT : public flatbuffers::NativeTable { + typedef CumsumOptions TableType; + bool exclusive = false; + bool reverse = false; +}; + +struct CumsumOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef CumsumOptionsT NativeTableType; + typedef CumsumOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_EXCLUSIVE = 4, + VT_REVERSE = 6 + }; + bool exclusive() const { + return GetField(VT_EXCLUSIVE, 0) != 0; + } + bool reverse() const { + return GetField(VT_REVERSE, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_EXCLUSIVE, 1) && + VerifyField(verifier, VT_REVERSE, 1) && + verifier.EndTable(); + } + CumsumOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(CumsumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const CumsumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct CumsumOptionsBuilder { + typedef CumsumOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_exclusive(bool exclusive) { + fbb_.AddElement(CumsumOptions::VT_EXCLUSIVE, static_cast(exclusive), 0); + } + void add_reverse(bool reverse) { + fbb_.AddElement(CumsumOptions::VT_REVERSE, static_cast(reverse), 0); + } + explicit CumsumOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateCumsumOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool exclusive = false, + bool reverse = false) { + CumsumOptionsBuilder builder_(_fbb); + builder_.add_reverse(reverse); + builder_.add_exclusive(exclusive); + return builder_.Finish(); +} + +flatbuffers::Offset CreateCumsumOptions(flatbuffers::FlatBufferBuilder &_fbb, const CumsumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct BroadcastToOptionsT : public flatbuffers::NativeTable { + typedef BroadcastToOptions TableType; +}; + +struct BroadcastToOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef BroadcastToOptionsT NativeTableType; + typedef BroadcastToOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + BroadcastToOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(BroadcastToOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const BroadcastToOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct BroadcastToOptionsBuilder { + typedef BroadcastToOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit BroadcastToOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateBroadcastToOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + BroadcastToOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateBroadcastToOptions(flatbuffers::FlatBufferBuilder &_fbb, const BroadcastToOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct Rfft2dOptionsT : public flatbuffers::NativeTable { + typedef Rfft2dOptions TableType; +}; + +struct Rfft2dOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef Rfft2dOptionsT NativeTableType; + typedef Rfft2dOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + Rfft2dOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(Rfft2dOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const Rfft2dOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct Rfft2dOptionsBuilder { + typedef Rfft2dOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit Rfft2dOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateRfft2dOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + Rfft2dOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateRfft2dOptions(flatbuffers::FlatBufferBuilder &_fbb, const Rfft2dOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct HashtableOptionsT : public flatbuffers::NativeTable { + typedef HashtableOptions TableType; + int32_t table_id = 0; + tflite::TensorType key_dtype = tflite::TensorType_FLOAT32; + tflite::TensorType value_dtype = tflite::TensorType_FLOAT32; +}; + +struct HashtableOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef HashtableOptionsT NativeTableType; + typedef HashtableOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_TABLE_ID = 4, + VT_KEY_DTYPE = 6, + VT_VALUE_DTYPE = 8 + }; + int32_t table_id() const { + return GetField(VT_TABLE_ID, 0); + } + tflite::TensorType key_dtype() const { + return static_cast(GetField(VT_KEY_DTYPE, 0)); + } + tflite::TensorType value_dtype() const { + return static_cast(GetField(VT_VALUE_DTYPE, 0)); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_TABLE_ID, 4) && + VerifyField(verifier, VT_KEY_DTYPE, 1) && + VerifyField(verifier, VT_VALUE_DTYPE, 1) && + verifier.EndTable(); + } + HashtableOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(HashtableOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct HashtableOptionsBuilder { + typedef HashtableOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_table_id(int32_t table_id) { + fbb_.AddElement(HashtableOptions::VT_TABLE_ID, table_id, 0); + } + void add_key_dtype(tflite::TensorType key_dtype) { + fbb_.AddElement(HashtableOptions::VT_KEY_DTYPE, static_cast(key_dtype), 0); + } + void add_value_dtype(tflite::TensorType value_dtype) { + fbb_.AddElement(HashtableOptions::VT_VALUE_DTYPE, static_cast(value_dtype), 0); + } + explicit HashtableOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateHashtableOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int32_t table_id = 0, + tflite::TensorType key_dtype = tflite::TensorType_FLOAT32, + tflite::TensorType value_dtype = tflite::TensorType_FLOAT32) { + HashtableOptionsBuilder builder_(_fbb); + builder_.add_table_id(table_id); + builder_.add_value_dtype(value_dtype); + builder_.add_key_dtype(key_dtype); + return builder_.Finish(); +} + +flatbuffers::Offset CreateHashtableOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct HashtableFindOptionsT : public flatbuffers::NativeTable { + typedef HashtableFindOptions TableType; +}; + +struct HashtableFindOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef HashtableFindOptionsT NativeTableType; + typedef HashtableFindOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + HashtableFindOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(HashtableFindOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableFindOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct HashtableFindOptionsBuilder { + typedef HashtableFindOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit HashtableFindOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateHashtableFindOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + HashtableFindOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateHashtableFindOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableFindOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct HashtableImportOptionsT : public flatbuffers::NativeTable { + typedef HashtableImportOptions TableType; +}; + +struct HashtableImportOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef HashtableImportOptionsT NativeTableType; + typedef HashtableImportOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + HashtableImportOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(HashtableImportOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableImportOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct HashtableImportOptionsBuilder { + typedef HashtableImportOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit HashtableImportOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateHashtableImportOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + HashtableImportOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateHashtableImportOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableImportOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct HashtableSizeOptionsT : public flatbuffers::NativeTable { + typedef HashtableSizeOptions TableType; +}; + +struct HashtableSizeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef HashtableSizeOptionsT NativeTableType; + typedef HashtableSizeOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + HashtableSizeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(HashtableSizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableSizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct HashtableSizeOptionsBuilder { + typedef HashtableSizeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit HashtableSizeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateHashtableSizeOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + HashtableSizeOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateHashtableSizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableSizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct VarHandleOptionsT : public flatbuffers::NativeTable { + typedef VarHandleOptions TableType; + std::string container{}; + std::string shared_name{}; +}; + +struct VarHandleOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef VarHandleOptionsT NativeTableType; + typedef VarHandleOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_CONTAINER = 4, + VT_SHARED_NAME = 6 + }; + const flatbuffers::String *container() const { + return GetPointer(VT_CONTAINER); + } + const flatbuffers::String *shared_name() const { + return GetPointer(VT_SHARED_NAME); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_CONTAINER) && + verifier.VerifyString(container()) && + VerifyOffset(verifier, VT_SHARED_NAME) && + verifier.VerifyString(shared_name()) && + verifier.EndTable(); + } + VarHandleOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(VarHandleOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const VarHandleOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct VarHandleOptionsBuilder { + typedef VarHandleOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_container(flatbuffers::Offset container) { + fbb_.AddOffset(VarHandleOptions::VT_CONTAINER, container); + } + void add_shared_name(flatbuffers::Offset shared_name) { + fbb_.AddOffset(VarHandleOptions::VT_SHARED_NAME, shared_name); + } + explicit VarHandleOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateVarHandleOptions( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset container = 0, + flatbuffers::Offset shared_name = 0) { + VarHandleOptionsBuilder builder_(_fbb); + builder_.add_shared_name(shared_name); + builder_.add_container(container); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateVarHandleOptionsDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const char *container = nullptr, + const char *shared_name = nullptr) { + auto container__ = container ? _fbb.CreateString(container) : 0; + auto shared_name__ = shared_name ? _fbb.CreateString(shared_name) : 0; + return tflite::CreateVarHandleOptions( + _fbb, + container__, + shared_name__); +} + +flatbuffers::Offset CreateVarHandleOptions(flatbuffers::FlatBufferBuilder &_fbb, const VarHandleOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ReadVariableOptionsT : public flatbuffers::NativeTable { + typedef ReadVariableOptions TableType; +}; + +struct ReadVariableOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ReadVariableOptionsT NativeTableType; + typedef ReadVariableOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + ReadVariableOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ReadVariableOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReadVariableOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ReadVariableOptionsBuilder { + typedef ReadVariableOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit ReadVariableOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateReadVariableOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + ReadVariableOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateReadVariableOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReadVariableOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct AssignVariableOptionsT : public flatbuffers::NativeTable { + typedef AssignVariableOptions TableType; +}; + +struct AssignVariableOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef AssignVariableOptionsT NativeTableType; + typedef AssignVariableOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + AssignVariableOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(AssignVariableOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const AssignVariableOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct AssignVariableOptionsBuilder { + typedef AssignVariableOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit AssignVariableOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateAssignVariableOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + AssignVariableOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateAssignVariableOptions(flatbuffers::FlatBufferBuilder &_fbb, const AssignVariableOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct RandomOptionsT : public flatbuffers::NativeTable { + typedef RandomOptions TableType; + int64_t seed = 0; + int64_t seed2 = 0; +}; + +struct RandomOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef RandomOptionsT NativeTableType; + typedef RandomOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_SEED = 4, + VT_SEED2 = 6 + }; + int64_t seed() const { + return GetField(VT_SEED, 0); + } + int64_t seed2() const { + return GetField(VT_SEED2, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_SEED, 8) && + VerifyField(verifier, VT_SEED2, 8) && + verifier.EndTable(); + } + RandomOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(RandomOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const RandomOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct RandomOptionsBuilder { + typedef RandomOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_seed(int64_t seed) { + fbb_.AddElement(RandomOptions::VT_SEED, seed, 0); + } + void add_seed2(int64_t seed2) { + fbb_.AddElement(RandomOptions::VT_SEED2, seed2, 0); + } + explicit RandomOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateRandomOptions( + flatbuffers::FlatBufferBuilder &_fbb, + int64_t seed = 0, + int64_t seed2 = 0) { + RandomOptionsBuilder builder_(_fbb); + builder_.add_seed2(seed2); + builder_.add_seed(seed); + return builder_.Finish(); +} + +flatbuffers::Offset CreateRandomOptions(flatbuffers::FlatBufferBuilder &_fbb, const RandomOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct BucketizeOptionsT : public flatbuffers::NativeTable { + typedef BucketizeOptions TableType; + std::vector boundaries{}; +}; + +struct BucketizeOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef BucketizeOptionsT NativeTableType; + typedef BucketizeOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_BOUNDARIES = 4 + }; + const flatbuffers::Vector *boundaries() const { + return GetPointer *>(VT_BOUNDARIES); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_BOUNDARIES) && + verifier.VerifyVector(boundaries()) && + verifier.EndTable(); + } + BucketizeOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(BucketizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const BucketizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct BucketizeOptionsBuilder { + typedef BucketizeOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_boundaries(flatbuffers::Offset> boundaries) { + fbb_.AddOffset(BucketizeOptions::VT_BOUNDARIES, boundaries); + } + explicit BucketizeOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateBucketizeOptions( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> boundaries = 0) { + BucketizeOptionsBuilder builder_(_fbb); + builder_.add_boundaries(boundaries); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateBucketizeOptionsDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *boundaries = nullptr) { + auto boundaries__ = boundaries ? _fbb.CreateVector(*boundaries) : 0; + return tflite::CreateBucketizeOptions( + _fbb, + boundaries__); +} + +flatbuffers::Offset CreateBucketizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const BucketizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct GeluOptionsT : public flatbuffers::NativeTable { + typedef GeluOptions TableType; + bool approximate = false; +}; + +struct GeluOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef GeluOptionsT NativeTableType; + typedef GeluOptionsBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_APPROXIMATE = 4 + }; + bool approximate() const { + return GetField(VT_APPROXIMATE, 0) != 0; + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_APPROXIMATE, 1) && + verifier.EndTable(); + } + GeluOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(GeluOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const GeluOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct GeluOptionsBuilder { + typedef GeluOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_approximate(bool approximate) { + fbb_.AddElement(GeluOptions::VT_APPROXIMATE, static_cast(approximate), 0); + } + explicit GeluOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateGeluOptions( + flatbuffers::FlatBufferBuilder &_fbb, + bool approximate = false) { + GeluOptionsBuilder builder_(_fbb); + builder_.add_approximate(approximate); + return builder_.Finish(); +} + +flatbuffers::Offset CreateGeluOptions(flatbuffers::FlatBufferBuilder &_fbb, const GeluOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct DynamicUpdateSliceOptionsT : public flatbuffers::NativeTable { + typedef DynamicUpdateSliceOptions TableType; +}; + +struct DynamicUpdateSliceOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef DynamicUpdateSliceOptionsT NativeTableType; + typedef DynamicUpdateSliceOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + DynamicUpdateSliceOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(DynamicUpdateSliceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const DynamicUpdateSliceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct DynamicUpdateSliceOptionsBuilder { + typedef DynamicUpdateSliceOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit DynamicUpdateSliceOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateDynamicUpdateSliceOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + DynamicUpdateSliceOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateDynamicUpdateSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, const DynamicUpdateSliceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct UnsortedSegmentProdOptionsT : public flatbuffers::NativeTable { + typedef UnsortedSegmentProdOptions TableType; +}; + +struct UnsortedSegmentProdOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef UnsortedSegmentProdOptionsT NativeTableType; + typedef UnsortedSegmentProdOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + UnsortedSegmentProdOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(UnsortedSegmentProdOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentProdOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct UnsortedSegmentProdOptionsBuilder { + typedef UnsortedSegmentProdOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit UnsortedSegmentProdOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUnsortedSegmentProdOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + UnsortedSegmentProdOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateUnsortedSegmentProdOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentProdOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct UnsortedSegmentMaxOptionsT : public flatbuffers::NativeTable { + typedef UnsortedSegmentMaxOptions TableType; +}; + +struct UnsortedSegmentMaxOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef UnsortedSegmentMaxOptionsT NativeTableType; + typedef UnsortedSegmentMaxOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + UnsortedSegmentMaxOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(UnsortedSegmentMaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct UnsortedSegmentMaxOptionsBuilder { + typedef UnsortedSegmentMaxOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit UnsortedSegmentMaxOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUnsortedSegmentMaxOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + UnsortedSegmentMaxOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateUnsortedSegmentMaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct UnsortedSegmentSumOptionsT : public flatbuffers::NativeTable { + typedef UnsortedSegmentSumOptions TableType; +}; + +struct UnsortedSegmentSumOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef UnsortedSegmentSumOptionsT NativeTableType; + typedef UnsortedSegmentSumOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + UnsortedSegmentSumOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(UnsortedSegmentSumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentSumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct UnsortedSegmentSumOptionsBuilder { + typedef UnsortedSegmentSumOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit UnsortedSegmentSumOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUnsortedSegmentSumOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + UnsortedSegmentSumOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateUnsortedSegmentSumOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentSumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ATan2OptionsT : public flatbuffers::NativeTable { + typedef ATan2Options TableType; +}; + +struct ATan2Options FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ATan2OptionsT NativeTableType; + typedef ATan2OptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + ATan2OptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ATan2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ATan2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ATan2OptionsBuilder { + typedef ATan2Options Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit ATan2OptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateATan2Options( + flatbuffers::FlatBufferBuilder &_fbb) { + ATan2OptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateATan2Options(flatbuffers::FlatBufferBuilder &_fbb, const ATan2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct UnsortedSegmentMinOptionsT : public flatbuffers::NativeTable { + typedef UnsortedSegmentMinOptions TableType; +}; + +struct UnsortedSegmentMinOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef UnsortedSegmentMinOptionsT NativeTableType; + typedef UnsortedSegmentMinOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + UnsortedSegmentMinOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(UnsortedSegmentMinOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMinOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct UnsortedSegmentMinOptionsBuilder { + typedef UnsortedSegmentMinOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit UnsortedSegmentMinOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateUnsortedSegmentMinOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + UnsortedSegmentMinOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateUnsortedSegmentMinOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMinOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SignOptionsT : public flatbuffers::NativeTable { + typedef SignOptions TableType; +}; + +struct SignOptions FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SignOptionsT NativeTableType; + typedef SignOptionsBuilder Builder; + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + verifier.EndTable(); + } + SignOptionsT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SignOptionsT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SignOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SignOptionsBuilder { + typedef SignOptions Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + explicit SignOptionsBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSignOptions( + flatbuffers::FlatBufferBuilder &_fbb) { + SignOptionsBuilder builder_(_fbb); + return builder_.Finish(); +} + +flatbuffers::Offset CreateSignOptions(flatbuffers::FlatBufferBuilder &_fbb, const SignOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + + + + + +struct OperatorCodeBuilder { + typedef OperatorCode Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_deprecated_builtin_code(int8_t deprecated_builtin_code) { + fbb_.AddElement(OperatorCode::VT_DEPRECATED_BUILTIN_CODE, deprecated_builtin_code, 0); + } + void add_custom_code(flatbuffers::Offset custom_code) { + fbb_.AddOffset(OperatorCode::VT_CUSTOM_CODE, custom_code); + } + void add_version(int32_t version) { + fbb_.AddElement(OperatorCode::VT_VERSION, version, 1); + } + void add_builtin_code(tflite::BuiltinOperator builtin_code) { + fbb_.AddElement(OperatorCode::VT_BUILTIN_CODE, static_cast(builtin_code), 0); + } + explicit OperatorCodeBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateOperatorCode( + flatbuffers::FlatBufferBuilder &_fbb, + int8_t deprecated_builtin_code = 0, + flatbuffers::Offset custom_code = 0, + int32_t version = 1, + tflite::BuiltinOperator builtin_code = tflite::BuiltinOperator_ADD) { + OperatorCodeBuilder builder_(_fbb); + builder_.add_builtin_code(builtin_code); + builder_.add_version(version); + builder_.add_custom_code(custom_code); + builder_.add_deprecated_builtin_code(deprecated_builtin_code); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateOperatorCodeDirect( + flatbuffers::FlatBufferBuilder &_fbb, + int8_t deprecated_builtin_code = 0, + const char *custom_code = nullptr, + int32_t version = 1, + tflite::BuiltinOperator builtin_code = tflite::BuiltinOperator_ADD) { + auto custom_code__ = custom_code ? _fbb.CreateString(custom_code) : 0; + return tflite::CreateOperatorCode( + _fbb, + deprecated_builtin_code, + custom_code__, + version, + builtin_code); +} + +flatbuffers::Offset CreateOperatorCode(flatbuffers::FlatBufferBuilder &_fbb, const OperatorCodeT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct OperatorT : public flatbuffers::NativeTable { + typedef Operator TableType; + uint32_t opcode_index = 0; + std::vector inputs{}; + std::vector outputs{}; + tflite::BuiltinOptionsUnion builtin_options{}; + std::vector custom_options{}; + tflite::CustomOptionsFormat custom_options_format = tflite::CustomOptionsFormat_FLEXBUFFERS; + std::vector mutating_variable_inputs{}; + std::vector intermediates{}; +}; + +struct Operator FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef OperatorT NativeTableType; + typedef OperatorBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_OPCODE_INDEX = 4, + VT_INPUTS = 6, + VT_OUTPUTS = 8, + VT_BUILTIN_OPTIONS_TYPE = 10, + VT_BUILTIN_OPTIONS = 12, + VT_CUSTOM_OPTIONS = 14, + VT_CUSTOM_OPTIONS_FORMAT = 16, + VT_MUTATING_VARIABLE_INPUTS = 18, + VT_INTERMEDIATES = 20 + }; + uint32_t opcode_index() const { + return GetField(VT_OPCODE_INDEX, 0); + } + const flatbuffers::Vector *inputs() const { + return GetPointer *>(VT_INPUTS); + } + const flatbuffers::Vector *outputs() const { + return GetPointer *>(VT_OUTPUTS); + } + tflite::BuiltinOptions builtin_options_type() const { + return static_cast(GetField(VT_BUILTIN_OPTIONS_TYPE, 0)); + } + const void *builtin_options() const { + return GetPointer(VT_BUILTIN_OPTIONS); + } + template const T *builtin_options_as() const; + const tflite::Conv2DOptions *builtin_options_as_Conv2DOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_Conv2DOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::DepthwiseConv2DOptions *builtin_options_as_DepthwiseConv2DOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_DepthwiseConv2DOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ConcatEmbeddingsOptions *builtin_options_as_ConcatEmbeddingsOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ConcatEmbeddingsOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LSHProjectionOptions *builtin_options_as_LSHProjectionOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LSHProjectionOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::Pool2DOptions *builtin_options_as_Pool2DOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_Pool2DOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SVDFOptions *builtin_options_as_SVDFOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SVDFOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::RNNOptions *builtin_options_as_RNNOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_RNNOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::FullyConnectedOptions *builtin_options_as_FullyConnectedOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_FullyConnectedOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SoftmaxOptions *builtin_options_as_SoftmaxOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SoftmaxOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ConcatenationOptions *builtin_options_as_ConcatenationOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ConcatenationOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::AddOptions *builtin_options_as_AddOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_AddOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::L2NormOptions *builtin_options_as_L2NormOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_L2NormOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LocalResponseNormalizationOptions *builtin_options_as_LocalResponseNormalizationOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LocalResponseNormalizationOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LSTMOptions *builtin_options_as_LSTMOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LSTMOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ResizeBilinearOptions *builtin_options_as_ResizeBilinearOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ResizeBilinearOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::CallOptions *builtin_options_as_CallOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_CallOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ReshapeOptions *builtin_options_as_ReshapeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ReshapeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SkipGramOptions *builtin_options_as_SkipGramOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SkipGramOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SpaceToDepthOptions *builtin_options_as_SpaceToDepthOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SpaceToDepthOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::EmbeddingLookupSparseOptions *builtin_options_as_EmbeddingLookupSparseOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_EmbeddingLookupSparseOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::MulOptions *builtin_options_as_MulOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_MulOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::PadOptions *builtin_options_as_PadOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_PadOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::GatherOptions *builtin_options_as_GatherOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_GatherOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::BatchToSpaceNDOptions *builtin_options_as_BatchToSpaceNDOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_BatchToSpaceNDOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SpaceToBatchNDOptions *builtin_options_as_SpaceToBatchNDOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SpaceToBatchNDOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::TransposeOptions *builtin_options_as_TransposeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_TransposeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ReducerOptions *builtin_options_as_ReducerOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ReducerOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SubOptions *builtin_options_as_SubOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SubOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::DivOptions *builtin_options_as_DivOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_DivOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SqueezeOptions *builtin_options_as_SqueezeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SqueezeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SequenceRNNOptions *builtin_options_as_SequenceRNNOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SequenceRNNOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::StridedSliceOptions *builtin_options_as_StridedSliceOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_StridedSliceOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ExpOptions *builtin_options_as_ExpOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ExpOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::TopKV2Options *builtin_options_as_TopKV2Options() const { + return builtin_options_type() == tflite::BuiltinOptions_TopKV2Options ? static_cast(builtin_options()) : nullptr; + } + const tflite::SplitOptions *builtin_options_as_SplitOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SplitOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LogSoftmaxOptions *builtin_options_as_LogSoftmaxOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LogSoftmaxOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::CastOptions *builtin_options_as_CastOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_CastOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::DequantizeOptions *builtin_options_as_DequantizeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_DequantizeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::MaximumMinimumOptions *builtin_options_as_MaximumMinimumOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_MaximumMinimumOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ArgMaxOptions *builtin_options_as_ArgMaxOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ArgMaxOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LessOptions *builtin_options_as_LessOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LessOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::NegOptions *builtin_options_as_NegOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_NegOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::PadV2Options *builtin_options_as_PadV2Options() const { + return builtin_options_type() == tflite::BuiltinOptions_PadV2Options ? static_cast(builtin_options()) : nullptr; + } + const tflite::GreaterOptions *builtin_options_as_GreaterOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_GreaterOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::GreaterEqualOptions *builtin_options_as_GreaterEqualOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_GreaterEqualOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LessEqualOptions *builtin_options_as_LessEqualOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LessEqualOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SelectOptions *builtin_options_as_SelectOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SelectOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SliceOptions *builtin_options_as_SliceOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SliceOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::TransposeConvOptions *builtin_options_as_TransposeConvOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_TransposeConvOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SparseToDenseOptions *builtin_options_as_SparseToDenseOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SparseToDenseOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::TileOptions *builtin_options_as_TileOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_TileOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ExpandDimsOptions *builtin_options_as_ExpandDimsOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ExpandDimsOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::EqualOptions *builtin_options_as_EqualOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_EqualOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::NotEqualOptions *builtin_options_as_NotEqualOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_NotEqualOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ShapeOptions *builtin_options_as_ShapeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ShapeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::PowOptions *builtin_options_as_PowOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_PowOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ArgMinOptions *builtin_options_as_ArgMinOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ArgMinOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::FakeQuantOptions *builtin_options_as_FakeQuantOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_FakeQuantOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::PackOptions *builtin_options_as_PackOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_PackOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LogicalOrOptions *builtin_options_as_LogicalOrOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LogicalOrOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::OneHotOptions *builtin_options_as_OneHotOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_OneHotOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LogicalAndOptions *builtin_options_as_LogicalAndOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LogicalAndOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LogicalNotOptions *builtin_options_as_LogicalNotOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LogicalNotOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::UnpackOptions *builtin_options_as_UnpackOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_UnpackOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::FloorDivOptions *builtin_options_as_FloorDivOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_FloorDivOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SquareOptions *builtin_options_as_SquareOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SquareOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ZerosLikeOptions *builtin_options_as_ZerosLikeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ZerosLikeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::FillOptions *builtin_options_as_FillOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_FillOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::BidirectionalSequenceLSTMOptions *builtin_options_as_BidirectionalSequenceLSTMOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_BidirectionalSequenceLSTMOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::BidirectionalSequenceRNNOptions *builtin_options_as_BidirectionalSequenceRNNOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_BidirectionalSequenceRNNOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::UnidirectionalSequenceLSTMOptions *builtin_options_as_UnidirectionalSequenceLSTMOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_UnidirectionalSequenceLSTMOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::FloorModOptions *builtin_options_as_FloorModOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_FloorModOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::RangeOptions *builtin_options_as_RangeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_RangeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ResizeNearestNeighborOptions *builtin_options_as_ResizeNearestNeighborOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ResizeNearestNeighborOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::LeakyReluOptions *builtin_options_as_LeakyReluOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_LeakyReluOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SquaredDifferenceOptions *builtin_options_as_SquaredDifferenceOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SquaredDifferenceOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::MirrorPadOptions *builtin_options_as_MirrorPadOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_MirrorPadOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::AbsOptions *builtin_options_as_AbsOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_AbsOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SplitVOptions *builtin_options_as_SplitVOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SplitVOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::UniqueOptions *builtin_options_as_UniqueOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_UniqueOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ReverseV2Options *builtin_options_as_ReverseV2Options() const { + return builtin_options_type() == tflite::BuiltinOptions_ReverseV2Options ? static_cast(builtin_options()) : nullptr; + } + const tflite::AddNOptions *builtin_options_as_AddNOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_AddNOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::GatherNdOptions *builtin_options_as_GatherNdOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_GatherNdOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::CosOptions *builtin_options_as_CosOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_CosOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::WhereOptions *builtin_options_as_WhereOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_WhereOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::RankOptions *builtin_options_as_RankOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_RankOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ReverseSequenceOptions *builtin_options_as_ReverseSequenceOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ReverseSequenceOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::MatrixDiagOptions *builtin_options_as_MatrixDiagOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_MatrixDiagOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::QuantizeOptions *builtin_options_as_QuantizeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_QuantizeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::MatrixSetDiagOptions *builtin_options_as_MatrixSetDiagOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_MatrixSetDiagOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::HardSwishOptions *builtin_options_as_HardSwishOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_HardSwishOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::IfOptions *builtin_options_as_IfOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_IfOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::WhileOptions *builtin_options_as_WhileOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_WhileOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::DepthToSpaceOptions *builtin_options_as_DepthToSpaceOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_DepthToSpaceOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::NonMaxSuppressionV4Options *builtin_options_as_NonMaxSuppressionV4Options() const { + return builtin_options_type() == tflite::BuiltinOptions_NonMaxSuppressionV4Options ? static_cast(builtin_options()) : nullptr; + } + const tflite::NonMaxSuppressionV5Options *builtin_options_as_NonMaxSuppressionV5Options() const { + return builtin_options_type() == tflite::BuiltinOptions_NonMaxSuppressionV5Options ? static_cast(builtin_options()) : nullptr; + } + const tflite::ScatterNdOptions *builtin_options_as_ScatterNdOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ScatterNdOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SelectV2Options *builtin_options_as_SelectV2Options() const { + return builtin_options_type() == tflite::BuiltinOptions_SelectV2Options ? static_cast(builtin_options()) : nullptr; + } + const tflite::DensifyOptions *builtin_options_as_DensifyOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_DensifyOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::SegmentSumOptions *builtin_options_as_SegmentSumOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SegmentSumOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::BatchMatMulOptions *builtin_options_as_BatchMatMulOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_BatchMatMulOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::CumsumOptions *builtin_options_as_CumsumOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_CumsumOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::CallOnceOptions *builtin_options_as_CallOnceOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_CallOnceOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::BroadcastToOptions *builtin_options_as_BroadcastToOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_BroadcastToOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::Rfft2dOptions *builtin_options_as_Rfft2dOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_Rfft2dOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::Conv3DOptions *builtin_options_as_Conv3DOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_Conv3DOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::HashtableOptions *builtin_options_as_HashtableOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_HashtableOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::HashtableFindOptions *builtin_options_as_HashtableFindOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_HashtableFindOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::HashtableImportOptions *builtin_options_as_HashtableImportOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_HashtableImportOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::HashtableSizeOptions *builtin_options_as_HashtableSizeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_HashtableSizeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::VarHandleOptions *builtin_options_as_VarHandleOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_VarHandleOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ReadVariableOptions *builtin_options_as_ReadVariableOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_ReadVariableOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::AssignVariableOptions *builtin_options_as_AssignVariableOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_AssignVariableOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::RandomOptions *builtin_options_as_RandomOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_RandomOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::BucketizeOptions *builtin_options_as_BucketizeOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_BucketizeOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::GeluOptions *builtin_options_as_GeluOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_GeluOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::DynamicUpdateSliceOptions *builtin_options_as_DynamicUpdateSliceOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_DynamicUpdateSliceOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::UnsortedSegmentProdOptions *builtin_options_as_UnsortedSegmentProdOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_UnsortedSegmentProdOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::UnsortedSegmentMaxOptions *builtin_options_as_UnsortedSegmentMaxOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_UnsortedSegmentMaxOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::UnsortedSegmentMinOptions *builtin_options_as_UnsortedSegmentMinOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_UnsortedSegmentMinOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::UnsortedSegmentSumOptions *builtin_options_as_UnsortedSegmentSumOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_UnsortedSegmentSumOptions ? static_cast(builtin_options()) : nullptr; + } + const tflite::ATan2Options *builtin_options_as_ATan2Options() const { + return builtin_options_type() == tflite::BuiltinOptions_ATan2Options ? static_cast(builtin_options()) : nullptr; + } + const tflite::SignOptions *builtin_options_as_SignOptions() const { + return builtin_options_type() == tflite::BuiltinOptions_SignOptions ? static_cast(builtin_options()) : nullptr; + } + const flatbuffers::Vector *custom_options() const { + return GetPointer *>(VT_CUSTOM_OPTIONS); + } + tflite::CustomOptionsFormat custom_options_format() const { + return static_cast(GetField(VT_CUSTOM_OPTIONS_FORMAT, 0)); + } + const flatbuffers::Vector *mutating_variable_inputs() const { + return GetPointer *>(VT_MUTATING_VARIABLE_INPUTS); + } + const flatbuffers::Vector *intermediates() const { + return GetPointer *>(VT_INTERMEDIATES); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_OPCODE_INDEX, 4) && + VerifyOffset(verifier, VT_INPUTS) && + verifier.VerifyVector(inputs()) && + VerifyOffset(verifier, VT_OUTPUTS) && + verifier.VerifyVector(outputs()) && + VerifyField(verifier, VT_BUILTIN_OPTIONS_TYPE, 1) && + VerifyOffset(verifier, VT_BUILTIN_OPTIONS) && + VerifyBuiltinOptions(verifier, builtin_options(), builtin_options_type()) && + VerifyOffset(verifier, VT_CUSTOM_OPTIONS) && + verifier.VerifyVector(custom_options()) && + VerifyField(verifier, VT_CUSTOM_OPTIONS_FORMAT, 1) && + VerifyOffset(verifier, VT_MUTATING_VARIABLE_INPUTS) && + verifier.VerifyVector(mutating_variable_inputs()) && + VerifyOffset(verifier, VT_INTERMEDIATES) && + verifier.VerifyVector(intermediates()) && + verifier.EndTable(); + } + OperatorT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(OperatorT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const OperatorT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +template<> inline const tflite::Conv2DOptions *Operator::builtin_options_as() const { + return builtin_options_as_Conv2DOptions(); +} + +template<> inline const tflite::DepthwiseConv2DOptions *Operator::builtin_options_as() const { + return builtin_options_as_DepthwiseConv2DOptions(); +} + +template<> inline const tflite::ConcatEmbeddingsOptions *Operator::builtin_options_as() const { + return builtin_options_as_ConcatEmbeddingsOptions(); +} + +template<> inline const tflite::LSHProjectionOptions *Operator::builtin_options_as() const { + return builtin_options_as_LSHProjectionOptions(); +} + +template<> inline const tflite::Pool2DOptions *Operator::builtin_options_as() const { + return builtin_options_as_Pool2DOptions(); +} + +template<> inline const tflite::SVDFOptions *Operator::builtin_options_as() const { + return builtin_options_as_SVDFOptions(); +} + +template<> inline const tflite::RNNOptions *Operator::builtin_options_as() const { + return builtin_options_as_RNNOptions(); +} + +template<> inline const tflite::FullyConnectedOptions *Operator::builtin_options_as() const { + return builtin_options_as_FullyConnectedOptions(); +} + +template<> inline const tflite::SoftmaxOptions *Operator::builtin_options_as() const { + return builtin_options_as_SoftmaxOptions(); +} + +template<> inline const tflite::ConcatenationOptions *Operator::builtin_options_as() const { + return builtin_options_as_ConcatenationOptions(); +} + +template<> inline const tflite::AddOptions *Operator::builtin_options_as() const { + return builtin_options_as_AddOptions(); +} + +template<> inline const tflite::L2NormOptions *Operator::builtin_options_as() const { + return builtin_options_as_L2NormOptions(); +} + +template<> inline const tflite::LocalResponseNormalizationOptions *Operator::builtin_options_as() const { + return builtin_options_as_LocalResponseNormalizationOptions(); +} + +template<> inline const tflite::LSTMOptions *Operator::builtin_options_as() const { + return builtin_options_as_LSTMOptions(); +} + +template<> inline const tflite::ResizeBilinearOptions *Operator::builtin_options_as() const { + return builtin_options_as_ResizeBilinearOptions(); +} + +template<> inline const tflite::CallOptions *Operator::builtin_options_as() const { + return builtin_options_as_CallOptions(); +} + +template<> inline const tflite::ReshapeOptions *Operator::builtin_options_as() const { + return builtin_options_as_ReshapeOptions(); +} + +template<> inline const tflite::SkipGramOptions *Operator::builtin_options_as() const { + return builtin_options_as_SkipGramOptions(); +} + +template<> inline const tflite::SpaceToDepthOptions *Operator::builtin_options_as() const { + return builtin_options_as_SpaceToDepthOptions(); +} + +template<> inline const tflite::EmbeddingLookupSparseOptions *Operator::builtin_options_as() const { + return builtin_options_as_EmbeddingLookupSparseOptions(); +} + +template<> inline const tflite::MulOptions *Operator::builtin_options_as() const { + return builtin_options_as_MulOptions(); +} + +template<> inline const tflite::PadOptions *Operator::builtin_options_as() const { + return builtin_options_as_PadOptions(); +} + +template<> inline const tflite::GatherOptions *Operator::builtin_options_as() const { + return builtin_options_as_GatherOptions(); +} + +template<> inline const tflite::BatchToSpaceNDOptions *Operator::builtin_options_as() const { + return builtin_options_as_BatchToSpaceNDOptions(); +} + +template<> inline const tflite::SpaceToBatchNDOptions *Operator::builtin_options_as() const { + return builtin_options_as_SpaceToBatchNDOptions(); +} + +template<> inline const tflite::TransposeOptions *Operator::builtin_options_as() const { + return builtin_options_as_TransposeOptions(); +} + +template<> inline const tflite::ReducerOptions *Operator::builtin_options_as() const { + return builtin_options_as_ReducerOptions(); +} + +template<> inline const tflite::SubOptions *Operator::builtin_options_as() const { + return builtin_options_as_SubOptions(); +} + +template<> inline const tflite::DivOptions *Operator::builtin_options_as() const { + return builtin_options_as_DivOptions(); +} + +template<> inline const tflite::SqueezeOptions *Operator::builtin_options_as() const { + return builtin_options_as_SqueezeOptions(); +} + +template<> inline const tflite::SequenceRNNOptions *Operator::builtin_options_as() const { + return builtin_options_as_SequenceRNNOptions(); +} + +template<> inline const tflite::StridedSliceOptions *Operator::builtin_options_as() const { + return builtin_options_as_StridedSliceOptions(); +} + +template<> inline const tflite::ExpOptions *Operator::builtin_options_as() const { + return builtin_options_as_ExpOptions(); +} + +template<> inline const tflite::TopKV2Options *Operator::builtin_options_as() const { + return builtin_options_as_TopKV2Options(); +} + +template<> inline const tflite::SplitOptions *Operator::builtin_options_as() const { + return builtin_options_as_SplitOptions(); +} + +template<> inline const tflite::LogSoftmaxOptions *Operator::builtin_options_as() const { + return builtin_options_as_LogSoftmaxOptions(); +} + +template<> inline const tflite::CastOptions *Operator::builtin_options_as() const { + return builtin_options_as_CastOptions(); +} + +template<> inline const tflite::DequantizeOptions *Operator::builtin_options_as() const { + return builtin_options_as_DequantizeOptions(); +} + +template<> inline const tflite::MaximumMinimumOptions *Operator::builtin_options_as() const { + return builtin_options_as_MaximumMinimumOptions(); +} + +template<> inline const tflite::ArgMaxOptions *Operator::builtin_options_as() const { + return builtin_options_as_ArgMaxOptions(); +} + +template<> inline const tflite::LessOptions *Operator::builtin_options_as() const { + return builtin_options_as_LessOptions(); +} + +template<> inline const tflite::NegOptions *Operator::builtin_options_as() const { + return builtin_options_as_NegOptions(); +} + +template<> inline const tflite::PadV2Options *Operator::builtin_options_as() const { + return builtin_options_as_PadV2Options(); +} + +template<> inline const tflite::GreaterOptions *Operator::builtin_options_as() const { + return builtin_options_as_GreaterOptions(); +} + +template<> inline const tflite::GreaterEqualOptions *Operator::builtin_options_as() const { + return builtin_options_as_GreaterEqualOptions(); +} + +template<> inline const tflite::LessEqualOptions *Operator::builtin_options_as() const { + return builtin_options_as_LessEqualOptions(); +} + +template<> inline const tflite::SelectOptions *Operator::builtin_options_as() const { + return builtin_options_as_SelectOptions(); +} + +template<> inline const tflite::SliceOptions *Operator::builtin_options_as() const { + return builtin_options_as_SliceOptions(); +} + +template<> inline const tflite::TransposeConvOptions *Operator::builtin_options_as() const { + return builtin_options_as_TransposeConvOptions(); +} + +template<> inline const tflite::SparseToDenseOptions *Operator::builtin_options_as() const { + return builtin_options_as_SparseToDenseOptions(); +} + +template<> inline const tflite::TileOptions *Operator::builtin_options_as() const { + return builtin_options_as_TileOptions(); +} + +template<> inline const tflite::ExpandDimsOptions *Operator::builtin_options_as() const { + return builtin_options_as_ExpandDimsOptions(); +} + +template<> inline const tflite::EqualOptions *Operator::builtin_options_as() const { + return builtin_options_as_EqualOptions(); +} + +template<> inline const tflite::NotEqualOptions *Operator::builtin_options_as() const { + return builtin_options_as_NotEqualOptions(); +} + +template<> inline const tflite::ShapeOptions *Operator::builtin_options_as() const { + return builtin_options_as_ShapeOptions(); +} + +template<> inline const tflite::PowOptions *Operator::builtin_options_as() const { + return builtin_options_as_PowOptions(); +} + +template<> inline const tflite::ArgMinOptions *Operator::builtin_options_as() const { + return builtin_options_as_ArgMinOptions(); +} + +template<> inline const tflite::FakeQuantOptions *Operator::builtin_options_as() const { + return builtin_options_as_FakeQuantOptions(); +} + +template<> inline const tflite::PackOptions *Operator::builtin_options_as() const { + return builtin_options_as_PackOptions(); +} + +template<> inline const tflite::LogicalOrOptions *Operator::builtin_options_as() const { + return builtin_options_as_LogicalOrOptions(); +} + +template<> inline const tflite::OneHotOptions *Operator::builtin_options_as() const { + return builtin_options_as_OneHotOptions(); +} + +template<> inline const tflite::LogicalAndOptions *Operator::builtin_options_as() const { + return builtin_options_as_LogicalAndOptions(); +} + +template<> inline const tflite::LogicalNotOptions *Operator::builtin_options_as() const { + return builtin_options_as_LogicalNotOptions(); +} + +template<> inline const tflite::UnpackOptions *Operator::builtin_options_as() const { + return builtin_options_as_UnpackOptions(); +} + +template<> inline const tflite::FloorDivOptions *Operator::builtin_options_as() const { + return builtin_options_as_FloorDivOptions(); +} + +template<> inline const tflite::SquareOptions *Operator::builtin_options_as() const { + return builtin_options_as_SquareOptions(); +} + +template<> inline const tflite::ZerosLikeOptions *Operator::builtin_options_as() const { + return builtin_options_as_ZerosLikeOptions(); +} + +template<> inline const tflite::FillOptions *Operator::builtin_options_as() const { + return builtin_options_as_FillOptions(); +} + +template<> inline const tflite::BidirectionalSequenceLSTMOptions *Operator::builtin_options_as() const { + return builtin_options_as_BidirectionalSequenceLSTMOptions(); +} + +template<> inline const tflite::BidirectionalSequenceRNNOptions *Operator::builtin_options_as() const { + return builtin_options_as_BidirectionalSequenceRNNOptions(); +} + +template<> inline const tflite::UnidirectionalSequenceLSTMOptions *Operator::builtin_options_as() const { + return builtin_options_as_UnidirectionalSequenceLSTMOptions(); +} + +template<> inline const tflite::FloorModOptions *Operator::builtin_options_as() const { + return builtin_options_as_FloorModOptions(); +} + +template<> inline const tflite::RangeOptions *Operator::builtin_options_as() const { + return builtin_options_as_RangeOptions(); +} + +template<> inline const tflite::ResizeNearestNeighborOptions *Operator::builtin_options_as() const { + return builtin_options_as_ResizeNearestNeighborOptions(); +} + +template<> inline const tflite::LeakyReluOptions *Operator::builtin_options_as() const { + return builtin_options_as_LeakyReluOptions(); +} + +template<> inline const tflite::SquaredDifferenceOptions *Operator::builtin_options_as() const { + return builtin_options_as_SquaredDifferenceOptions(); +} + +template<> inline const tflite::MirrorPadOptions *Operator::builtin_options_as() const { + return builtin_options_as_MirrorPadOptions(); +} + +template<> inline const tflite::AbsOptions *Operator::builtin_options_as() const { + return builtin_options_as_AbsOptions(); +} + +template<> inline const tflite::SplitVOptions *Operator::builtin_options_as() const { + return builtin_options_as_SplitVOptions(); +} + +template<> inline const tflite::UniqueOptions *Operator::builtin_options_as() const { + return builtin_options_as_UniqueOptions(); +} + +template<> inline const tflite::ReverseV2Options *Operator::builtin_options_as() const { + return builtin_options_as_ReverseV2Options(); +} + +template<> inline const tflite::AddNOptions *Operator::builtin_options_as() const { + return builtin_options_as_AddNOptions(); +} + +template<> inline const tflite::GatherNdOptions *Operator::builtin_options_as() const { + return builtin_options_as_GatherNdOptions(); +} + +template<> inline const tflite::CosOptions *Operator::builtin_options_as() const { + return builtin_options_as_CosOptions(); +} + +template<> inline const tflite::WhereOptions *Operator::builtin_options_as() const { + return builtin_options_as_WhereOptions(); +} + +template<> inline const tflite::RankOptions *Operator::builtin_options_as() const { + return builtin_options_as_RankOptions(); +} + +template<> inline const tflite::ReverseSequenceOptions *Operator::builtin_options_as() const { + return builtin_options_as_ReverseSequenceOptions(); +} + +template<> inline const tflite::MatrixDiagOptions *Operator::builtin_options_as() const { + return builtin_options_as_MatrixDiagOptions(); +} + +template<> inline const tflite::QuantizeOptions *Operator::builtin_options_as() const { + return builtin_options_as_QuantizeOptions(); +} + +template<> inline const tflite::MatrixSetDiagOptions *Operator::builtin_options_as() const { + return builtin_options_as_MatrixSetDiagOptions(); +} + +template<> inline const tflite::HardSwishOptions *Operator::builtin_options_as() const { + return builtin_options_as_HardSwishOptions(); +} + +template<> inline const tflite::IfOptions *Operator::builtin_options_as() const { + return builtin_options_as_IfOptions(); +} + +template<> inline const tflite::WhileOptions *Operator::builtin_options_as() const { + return builtin_options_as_WhileOptions(); +} + +template<> inline const tflite::DepthToSpaceOptions *Operator::builtin_options_as() const { + return builtin_options_as_DepthToSpaceOptions(); +} + +template<> inline const tflite::NonMaxSuppressionV4Options *Operator::builtin_options_as() const { + return builtin_options_as_NonMaxSuppressionV4Options(); +} + +template<> inline const tflite::NonMaxSuppressionV5Options *Operator::builtin_options_as() const { + return builtin_options_as_NonMaxSuppressionV5Options(); +} + +template<> inline const tflite::ScatterNdOptions *Operator::builtin_options_as() const { + return builtin_options_as_ScatterNdOptions(); +} + +template<> inline const tflite::SelectV2Options *Operator::builtin_options_as() const { + return builtin_options_as_SelectV2Options(); +} + +template<> inline const tflite::DensifyOptions *Operator::builtin_options_as() const { + return builtin_options_as_DensifyOptions(); +} + +template<> inline const tflite::SegmentSumOptions *Operator::builtin_options_as() const { + return builtin_options_as_SegmentSumOptions(); +} + +template<> inline const tflite::BatchMatMulOptions *Operator::builtin_options_as() const { + return builtin_options_as_BatchMatMulOptions(); +} + +template<> inline const tflite::CumsumOptions *Operator::builtin_options_as() const { + return builtin_options_as_CumsumOptions(); +} + +template<> inline const tflite::CallOnceOptions *Operator::builtin_options_as() const { + return builtin_options_as_CallOnceOptions(); +} + +template<> inline const tflite::BroadcastToOptions *Operator::builtin_options_as() const { + return builtin_options_as_BroadcastToOptions(); +} + +template<> inline const tflite::Rfft2dOptions *Operator::builtin_options_as() const { + return builtin_options_as_Rfft2dOptions(); +} + +template<> inline const tflite::Conv3DOptions *Operator::builtin_options_as() const { + return builtin_options_as_Conv3DOptions(); +} + +template<> inline const tflite::HashtableOptions *Operator::builtin_options_as() const { + return builtin_options_as_HashtableOptions(); +} + +template<> inline const tflite::HashtableFindOptions *Operator::builtin_options_as() const { + return builtin_options_as_HashtableFindOptions(); +} + +template<> inline const tflite::HashtableImportOptions *Operator::builtin_options_as() const { + return builtin_options_as_HashtableImportOptions(); +} + +template<> inline const tflite::HashtableSizeOptions *Operator::builtin_options_as() const { + return builtin_options_as_HashtableSizeOptions(); +} + +template<> inline const tflite::VarHandleOptions *Operator::builtin_options_as() const { + return builtin_options_as_VarHandleOptions(); +} + +template<> inline const tflite::ReadVariableOptions *Operator::builtin_options_as() const { + return builtin_options_as_ReadVariableOptions(); +} + +template<> inline const tflite::AssignVariableOptions *Operator::builtin_options_as() const { + return builtin_options_as_AssignVariableOptions(); +} + +template<> inline const tflite::RandomOptions *Operator::builtin_options_as() const { + return builtin_options_as_RandomOptions(); +} + +template<> inline const tflite::BucketizeOptions *Operator::builtin_options_as() const { + return builtin_options_as_BucketizeOptions(); +} + +template<> inline const tflite::GeluOptions *Operator::builtin_options_as() const { + return builtin_options_as_GeluOptions(); +} + +template<> inline const tflite::DynamicUpdateSliceOptions *Operator::builtin_options_as() const { + return builtin_options_as_DynamicUpdateSliceOptions(); +} + +template<> inline const tflite::UnsortedSegmentProdOptions *Operator::builtin_options_as() const { + return builtin_options_as_UnsortedSegmentProdOptions(); +} + +template<> inline const tflite::UnsortedSegmentMaxOptions *Operator::builtin_options_as() const { + return builtin_options_as_UnsortedSegmentMaxOptions(); +} + +template<> inline const tflite::UnsortedSegmentMinOptions *Operator::builtin_options_as() const { + return builtin_options_as_UnsortedSegmentMinOptions(); +} + +template<> inline const tflite::UnsortedSegmentSumOptions *Operator::builtin_options_as() const { + return builtin_options_as_UnsortedSegmentSumOptions(); +} + +template<> inline const tflite::ATan2Options *Operator::builtin_options_as() const { + return builtin_options_as_ATan2Options(); +} + +template<> inline const tflite::SignOptions *Operator::builtin_options_as() const { + return builtin_options_as_SignOptions(); +} + +struct OperatorBuilder { + typedef Operator Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_opcode_index(uint32_t opcode_index) { + fbb_.AddElement(Operator::VT_OPCODE_INDEX, opcode_index, 0); + } + void add_inputs(flatbuffers::Offset> inputs) { + fbb_.AddOffset(Operator::VT_INPUTS, inputs); + } + void add_outputs(flatbuffers::Offset> outputs) { + fbb_.AddOffset(Operator::VT_OUTPUTS, outputs); + } + void add_builtin_options_type(tflite::BuiltinOptions builtin_options_type) { + fbb_.AddElement(Operator::VT_BUILTIN_OPTIONS_TYPE, static_cast(builtin_options_type), 0); + } + void add_builtin_options(flatbuffers::Offset builtin_options) { + fbb_.AddOffset(Operator::VT_BUILTIN_OPTIONS, builtin_options); + } + void add_custom_options(flatbuffers::Offset> custom_options) { + fbb_.AddOffset(Operator::VT_CUSTOM_OPTIONS, custom_options); + } + void add_custom_options_format(tflite::CustomOptionsFormat custom_options_format) { + fbb_.AddElement(Operator::VT_CUSTOM_OPTIONS_FORMAT, static_cast(custom_options_format), 0); + } + void add_mutating_variable_inputs(flatbuffers::Offset> mutating_variable_inputs) { + fbb_.AddOffset(Operator::VT_MUTATING_VARIABLE_INPUTS, mutating_variable_inputs); + } + void add_intermediates(flatbuffers::Offset> intermediates) { + fbb_.AddOffset(Operator::VT_INTERMEDIATES, intermediates); + } + explicit OperatorBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateOperator( + flatbuffers::FlatBufferBuilder &_fbb, + uint32_t opcode_index = 0, + flatbuffers::Offset> inputs = 0, + flatbuffers::Offset> outputs = 0, + tflite::BuiltinOptions builtin_options_type = tflite::BuiltinOptions_NONE, + flatbuffers::Offset builtin_options = 0, + flatbuffers::Offset> custom_options = 0, + tflite::CustomOptionsFormat custom_options_format = tflite::CustomOptionsFormat_FLEXBUFFERS, + flatbuffers::Offset> mutating_variable_inputs = 0, + flatbuffers::Offset> intermediates = 0) { + OperatorBuilder builder_(_fbb); + builder_.add_intermediates(intermediates); + builder_.add_mutating_variable_inputs(mutating_variable_inputs); + builder_.add_custom_options(custom_options); + builder_.add_builtin_options(builtin_options); + builder_.add_outputs(outputs); + builder_.add_inputs(inputs); + builder_.add_opcode_index(opcode_index); + builder_.add_custom_options_format(custom_options_format); + builder_.add_builtin_options_type(builtin_options_type); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateOperatorDirect( + flatbuffers::FlatBufferBuilder &_fbb, + uint32_t opcode_index = 0, + const std::vector *inputs = nullptr, + const std::vector *outputs = nullptr, + tflite::BuiltinOptions builtin_options_type = tflite::BuiltinOptions_NONE, + flatbuffers::Offset builtin_options = 0, + const std::vector *custom_options = nullptr, + tflite::CustomOptionsFormat custom_options_format = tflite::CustomOptionsFormat_FLEXBUFFERS, + const std::vector *mutating_variable_inputs = nullptr, + const std::vector *intermediates = nullptr) { + auto inputs__ = inputs ? _fbb.CreateVector(*inputs) : 0; + auto outputs__ = outputs ? _fbb.CreateVector(*outputs) : 0; + auto custom_options__ = custom_options ? _fbb.CreateVector(*custom_options) : 0; + auto mutating_variable_inputs__ = mutating_variable_inputs ? _fbb.CreateVector(*mutating_variable_inputs) : 0; + auto intermediates__ = intermediates ? _fbb.CreateVector(*intermediates) : 0; + return tflite::CreateOperator( + _fbb, + opcode_index, + inputs__, + outputs__, + builtin_options_type, + builtin_options, + custom_options__, + custom_options_format, + mutating_variable_inputs__, + intermediates__); +} + +flatbuffers::Offset CreateOperator(flatbuffers::FlatBufferBuilder &_fbb, const OperatorT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SubGraphT : public flatbuffers::NativeTable { + typedef SubGraph TableType; + std::vector> tensors{}; + std::vector inputs{}; + std::vector outputs{}; + std::vector> operators{}; + std::string name{}; + SubGraphT() = default; + SubGraphT(const SubGraphT &o); + SubGraphT(SubGraphT&&) FLATBUFFERS_NOEXCEPT = default; + SubGraphT &operator=(SubGraphT o) FLATBUFFERS_NOEXCEPT; +}; + +struct SubGraph FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SubGraphT NativeTableType; + typedef SubGraphBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_TENSORS = 4, + VT_INPUTS = 6, + VT_OUTPUTS = 8, + VT_OPERATORS = 10, + VT_NAME = 12 + }; + const flatbuffers::Vector> *tensors() const { + return GetPointer> *>(VT_TENSORS); + } + const flatbuffers::Vector *inputs() const { + return GetPointer *>(VT_INPUTS); + } + const flatbuffers::Vector *outputs() const { + return GetPointer *>(VT_OUTPUTS); + } + const flatbuffers::Vector> *operators() const { + return GetPointer> *>(VT_OPERATORS); + } + const flatbuffers::String *name() const { + return GetPointer(VT_NAME); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_TENSORS) && + verifier.VerifyVector(tensors()) && + verifier.VerifyVectorOfTables(tensors()) && + VerifyOffset(verifier, VT_INPUTS) && + verifier.VerifyVector(inputs()) && + VerifyOffset(verifier, VT_OUTPUTS) && + verifier.VerifyVector(outputs()) && + VerifyOffset(verifier, VT_OPERATORS) && + verifier.VerifyVector(operators()) && + verifier.VerifyVectorOfTables(operators()) && + VerifyOffset(verifier, VT_NAME) && + verifier.VerifyString(name()) && + verifier.EndTable(); + } + SubGraphT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SubGraphT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SubGraphT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SubGraphBuilder { + typedef SubGraph Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_tensors(flatbuffers::Offset>> tensors) { + fbb_.AddOffset(SubGraph::VT_TENSORS, tensors); + } + void add_inputs(flatbuffers::Offset> inputs) { + fbb_.AddOffset(SubGraph::VT_INPUTS, inputs); + } + void add_outputs(flatbuffers::Offset> outputs) { + fbb_.AddOffset(SubGraph::VT_OUTPUTS, outputs); + } + void add_operators(flatbuffers::Offset>> operators) { + fbb_.AddOffset(SubGraph::VT_OPERATORS, operators); + } + void add_name(flatbuffers::Offset name) { + fbb_.AddOffset(SubGraph::VT_NAME, name); + } + explicit SubGraphBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSubGraph( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset>> tensors = 0, + flatbuffers::Offset> inputs = 0, + flatbuffers::Offset> outputs = 0, + flatbuffers::Offset>> operators = 0, + flatbuffers::Offset name = 0) { + SubGraphBuilder builder_(_fbb); + builder_.add_name(name); + builder_.add_operators(operators); + builder_.add_outputs(outputs); + builder_.add_inputs(inputs); + builder_.add_tensors(tensors); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateSubGraphDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector> *tensors = nullptr, + const std::vector *inputs = nullptr, + const std::vector *outputs = nullptr, + const std::vector> *operators = nullptr, + const char *name = nullptr) { + auto tensors__ = tensors ? _fbb.CreateVector>(*tensors) : 0; + auto inputs__ = inputs ? _fbb.CreateVector(*inputs) : 0; + auto outputs__ = outputs ? _fbb.CreateVector(*outputs) : 0; + auto operators__ = operators ? _fbb.CreateVector>(*operators) : 0; + auto name__ = name ? _fbb.CreateString(name) : 0; + return tflite::CreateSubGraph( + _fbb, + tensors__, + inputs__, + outputs__, + operators__, + name__); +} + +flatbuffers::Offset CreateSubGraph(flatbuffers::FlatBufferBuilder &_fbb, const SubGraphT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct BufferT : public flatbuffers::NativeTable { + typedef Buffer TableType; + std::vector data{}; +}; + +struct Buffer FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef BufferT NativeTableType; + typedef BufferBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_DATA = 4 + }; + const flatbuffers::Vector *data() const { + return GetPointer *>(VT_DATA); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_DATA) && + verifier.VerifyVector(data()) && + verifier.EndTable(); + } + BufferT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(BufferT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const BufferT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct BufferBuilder { + typedef Buffer Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_data(flatbuffers::Offset> data) { + fbb_.AddOffset(Buffer::VT_DATA, data); + } + explicit BufferBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateBuffer( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset> data = 0) { + BufferBuilder builder_(_fbb); + builder_.add_data(data); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateBufferDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector *data = nullptr) { + if (data) { _fbb.ForceVectorAlignment(data->size(), sizeof(uint8_t), 16); } + auto data__ = data ? _fbb.CreateVector(*data) : 0; + return tflite::CreateBuffer( + _fbb, + data__); +} + +flatbuffers::Offset CreateBuffer(flatbuffers::FlatBufferBuilder &_fbb, const BufferT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct MetadataT : public flatbuffers::NativeTable { + typedef Metadata TableType; + std::string name{}; + uint32_t buffer = 0; +}; + +struct Metadata FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef MetadataT NativeTableType; + typedef MetadataBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NAME = 4, + VT_BUFFER = 6 + }; + const flatbuffers::String *name() const { + return GetPointer(VT_NAME); + } + uint32_t buffer() const { + return GetField(VT_BUFFER, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_NAME) && + verifier.VerifyString(name()) && + VerifyField(verifier, VT_BUFFER, 4) && + verifier.EndTable(); + } + MetadataT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(MetadataT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const MetadataT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct MetadataBuilder { + typedef Metadata Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_name(flatbuffers::Offset name) { + fbb_.AddOffset(Metadata::VT_NAME, name); + } + void add_buffer(uint32_t buffer) { + fbb_.AddElement(Metadata::VT_BUFFER, buffer, 0); + } + explicit MetadataBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateMetadata( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset name = 0, + uint32_t buffer = 0) { + MetadataBuilder builder_(_fbb); + builder_.add_buffer(buffer); + builder_.add_name(name); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateMetadataDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const char *name = nullptr, + uint32_t buffer = 0) { + auto name__ = name ? _fbb.CreateString(name) : 0; + return tflite::CreateMetadata( + _fbb, + name__, + buffer); +} + +flatbuffers::Offset CreateMetadata(flatbuffers::FlatBufferBuilder &_fbb, const MetadataT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct TensorMapT : public flatbuffers::NativeTable { + typedef TensorMap TableType; + std::string name{}; + uint32_t tensor_index = 0; +}; + +struct TensorMap FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef TensorMapT NativeTableType; + typedef TensorMapBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_NAME = 4, + VT_TENSOR_INDEX = 6 + }; + const flatbuffers::String *name() const { + return GetPointer(VT_NAME); + } + uint32_t tensor_index() const { + return GetField(VT_TENSOR_INDEX, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_NAME) && + verifier.VerifyString(name()) && + VerifyField(verifier, VT_TENSOR_INDEX, 4) && + verifier.EndTable(); + } + TensorMapT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(TensorMapT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const TensorMapT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct TensorMapBuilder { + typedef TensorMap Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_name(flatbuffers::Offset name) { + fbb_.AddOffset(TensorMap::VT_NAME, name); + } + void add_tensor_index(uint32_t tensor_index) { + fbb_.AddElement(TensorMap::VT_TENSOR_INDEX, tensor_index, 0); + } + explicit TensorMapBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateTensorMap( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset name = 0, + uint32_t tensor_index = 0) { + TensorMapBuilder builder_(_fbb); + builder_.add_tensor_index(tensor_index); + builder_.add_name(name); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateTensorMapDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const char *name = nullptr, + uint32_t tensor_index = 0) { + auto name__ = name ? _fbb.CreateString(name) : 0; + return tflite::CreateTensorMap( + _fbb, + name__, + tensor_index); +} + +flatbuffers::Offset CreateTensorMap(flatbuffers::FlatBufferBuilder &_fbb, const TensorMapT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct SignatureDefT : public flatbuffers::NativeTable { + typedef SignatureDef TableType; + std::vector> inputs{}; + std::vector> outputs{}; + std::string signature_key{}; + uint32_t subgraph_index = 0; + SignatureDefT() = default; + SignatureDefT(const SignatureDefT &o); + SignatureDefT(SignatureDefT&&) FLATBUFFERS_NOEXCEPT = default; + SignatureDefT &operator=(SignatureDefT o) FLATBUFFERS_NOEXCEPT; +}; + +struct SignatureDef FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef SignatureDefT NativeTableType; + typedef SignatureDefBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_INPUTS = 4, + VT_OUTPUTS = 6, + VT_SIGNATURE_KEY = 8, + VT_SUBGRAPH_INDEX = 12 + }; + const flatbuffers::Vector> *inputs() const { + return GetPointer> *>(VT_INPUTS); + } + const flatbuffers::Vector> *outputs() const { + return GetPointer> *>(VT_OUTPUTS); + } + const flatbuffers::String *signature_key() const { + return GetPointer(VT_SIGNATURE_KEY); + } + uint32_t subgraph_index() const { + return GetField(VT_SUBGRAPH_INDEX, 0); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyOffset(verifier, VT_INPUTS) && + verifier.VerifyVector(inputs()) && + verifier.VerifyVectorOfTables(inputs()) && + VerifyOffset(verifier, VT_OUTPUTS) && + verifier.VerifyVector(outputs()) && + verifier.VerifyVectorOfTables(outputs()) && + VerifyOffset(verifier, VT_SIGNATURE_KEY) && + verifier.VerifyString(signature_key()) && + VerifyField(verifier, VT_SUBGRAPH_INDEX, 4) && + verifier.EndTable(); + } + SignatureDefT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(SignatureDefT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const SignatureDefT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct SignatureDefBuilder { + typedef SignatureDef Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_inputs(flatbuffers::Offset>> inputs) { + fbb_.AddOffset(SignatureDef::VT_INPUTS, inputs); + } + void add_outputs(flatbuffers::Offset>> outputs) { + fbb_.AddOffset(SignatureDef::VT_OUTPUTS, outputs); + } + void add_signature_key(flatbuffers::Offset signature_key) { + fbb_.AddOffset(SignatureDef::VT_SIGNATURE_KEY, signature_key); + } + void add_subgraph_index(uint32_t subgraph_index) { + fbb_.AddElement(SignatureDef::VT_SUBGRAPH_INDEX, subgraph_index, 0); + } + explicit SignatureDefBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateSignatureDef( + flatbuffers::FlatBufferBuilder &_fbb, + flatbuffers::Offset>> inputs = 0, + flatbuffers::Offset>> outputs = 0, + flatbuffers::Offset signature_key = 0, + uint32_t subgraph_index = 0) { + SignatureDefBuilder builder_(_fbb); + builder_.add_subgraph_index(subgraph_index); + builder_.add_signature_key(signature_key); + builder_.add_outputs(outputs); + builder_.add_inputs(inputs); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateSignatureDefDirect( + flatbuffers::FlatBufferBuilder &_fbb, + const std::vector> *inputs = nullptr, + const std::vector> *outputs = nullptr, + const char *signature_key = nullptr, + uint32_t subgraph_index = 0) { + auto inputs__ = inputs ? _fbb.CreateVector>(*inputs) : 0; + auto outputs__ = outputs ? _fbb.CreateVector>(*outputs) : 0; + auto signature_key__ = signature_key ? _fbb.CreateString(signature_key) : 0; + return tflite::CreateSignatureDef( + _fbb, + inputs__, + outputs__, + signature_key__, + subgraph_index); +} + +flatbuffers::Offset CreateSignatureDef(flatbuffers::FlatBufferBuilder &_fbb, const SignatureDefT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +struct ModelT : public flatbuffers::NativeTable { + typedef Model TableType; + uint32_t version = 0; + std::vector> operator_codes{}; + std::vector> subgraphs{}; + std::string description{}; + std::vector> buffers{}; + std::vector metadata_buffer{}; + std::vector> metadata{}; + std::vector> signature_defs{}; + ModelT() = default; + ModelT(const ModelT &o); + ModelT(ModelT&&) FLATBUFFERS_NOEXCEPT = default; + ModelT &operator=(ModelT o) FLATBUFFERS_NOEXCEPT; +}; + +struct Model FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { + typedef ModelT NativeTableType; + typedef ModelBuilder Builder; + enum FlatBuffersVTableOffset FLATBUFFERS_VTABLE_UNDERLYING_TYPE { + VT_VERSION = 4, + VT_OPERATOR_CODES = 6, + VT_SUBGRAPHS = 8, + VT_DESCRIPTION = 10, + VT_BUFFERS = 12, + VT_METADATA_BUFFER = 14, + VT_METADATA = 16, + VT_SIGNATURE_DEFS = 18 + }; + uint32_t version() const { + return GetField(VT_VERSION, 0); + } + const flatbuffers::Vector> *operator_codes() const { + return GetPointer> *>(VT_OPERATOR_CODES); + } + const flatbuffers::Vector> *subgraphs() const { + return GetPointer> *>(VT_SUBGRAPHS); + } + const flatbuffers::String *description() const { + return GetPointer(VT_DESCRIPTION); + } + const flatbuffers::Vector> *buffers() const { + return GetPointer> *>(VT_BUFFERS); + } + const flatbuffers::Vector *metadata_buffer() const { + return GetPointer *>(VT_METADATA_BUFFER); + } + const flatbuffers::Vector> *metadata() const { + return GetPointer> *>(VT_METADATA); + } + const flatbuffers::Vector> *signature_defs() const { + return GetPointer> *>(VT_SIGNATURE_DEFS); + } + bool Verify(flatbuffers::Verifier &verifier) const { + return VerifyTableStart(verifier) && + VerifyField(verifier, VT_VERSION, 4) && + VerifyOffset(verifier, VT_OPERATOR_CODES) && + verifier.VerifyVector(operator_codes()) && + verifier.VerifyVectorOfTables(operator_codes()) && + VerifyOffset(verifier, VT_SUBGRAPHS) && + verifier.VerifyVector(subgraphs()) && + verifier.VerifyVectorOfTables(subgraphs()) && + VerifyOffset(verifier, VT_DESCRIPTION) && + verifier.VerifyString(description()) && + VerifyOffset(verifier, VT_BUFFERS) && + verifier.VerifyVector(buffers()) && + verifier.VerifyVectorOfTables(buffers()) && + VerifyOffset(verifier, VT_METADATA_BUFFER) && + verifier.VerifyVector(metadata_buffer()) && + VerifyOffset(verifier, VT_METADATA) && + verifier.VerifyVector(metadata()) && + verifier.VerifyVectorOfTables(metadata()) && + VerifyOffset(verifier, VT_SIGNATURE_DEFS) && + verifier.VerifyVector(signature_defs()) && + verifier.VerifyVectorOfTables(signature_defs()) && + verifier.EndTable(); + } + ModelT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; + void UnPackTo(ModelT *_o, const flatbuffers::resolver_function_t *_resolver = nullptr) const; + static flatbuffers::Offset Pack(flatbuffers::FlatBufferBuilder &_fbb, const ModelT* _o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); +}; + +struct ModelBuilder { + typedef Model Table; + flatbuffers::FlatBufferBuilder &fbb_; + flatbuffers::uoffset_t start_; + void add_version(uint32_t version) { + fbb_.AddElement(Model::VT_VERSION, version, 0); + } + void add_operator_codes(flatbuffers::Offset>> operator_codes) { + fbb_.AddOffset(Model::VT_OPERATOR_CODES, operator_codes); + } + void add_subgraphs(flatbuffers::Offset>> subgraphs) { + fbb_.AddOffset(Model::VT_SUBGRAPHS, subgraphs); + } + void add_description(flatbuffers::Offset description) { + fbb_.AddOffset(Model::VT_DESCRIPTION, description); + } + void add_buffers(flatbuffers::Offset>> buffers) { + fbb_.AddOffset(Model::VT_BUFFERS, buffers); + } + void add_metadata_buffer(flatbuffers::Offset> metadata_buffer) { + fbb_.AddOffset(Model::VT_METADATA_BUFFER, metadata_buffer); + } + void add_metadata(flatbuffers::Offset>> metadata) { + fbb_.AddOffset(Model::VT_METADATA, metadata); + } + void add_signature_defs(flatbuffers::Offset>> signature_defs) { + fbb_.AddOffset(Model::VT_SIGNATURE_DEFS, signature_defs); + } + explicit ModelBuilder(flatbuffers::FlatBufferBuilder &_fbb) + : fbb_(_fbb) { + start_ = fbb_.StartTable(); + } + flatbuffers::Offset Finish() { + const auto end = fbb_.EndTable(start_); + auto o = flatbuffers::Offset(end); + return o; + } +}; + +inline flatbuffers::Offset CreateModel( + flatbuffers::FlatBufferBuilder &_fbb, + uint32_t version = 0, + flatbuffers::Offset>> operator_codes = 0, + flatbuffers::Offset>> subgraphs = 0, + flatbuffers::Offset description = 0, + flatbuffers::Offset>> buffers = 0, + flatbuffers::Offset> metadata_buffer = 0, + flatbuffers::Offset>> metadata = 0, + flatbuffers::Offset>> signature_defs = 0) { + ModelBuilder builder_(_fbb); + builder_.add_signature_defs(signature_defs); + builder_.add_metadata(metadata); + builder_.add_metadata_buffer(metadata_buffer); + builder_.add_buffers(buffers); + builder_.add_description(description); + builder_.add_subgraphs(subgraphs); + builder_.add_operator_codes(operator_codes); + builder_.add_version(version); + return builder_.Finish(); +} + +inline flatbuffers::Offset CreateModelDirect( + flatbuffers::FlatBufferBuilder &_fbb, + uint32_t version = 0, + const std::vector> *operator_codes = nullptr, + const std::vector> *subgraphs = nullptr, + const char *description = nullptr, + const std::vector> *buffers = nullptr, + const std::vector *metadata_buffer = nullptr, + const std::vector> *metadata = nullptr, + const std::vector> *signature_defs = nullptr) { + auto operator_codes__ = operator_codes ? _fbb.CreateVector>(*operator_codes) : 0; + auto subgraphs__ = subgraphs ? _fbb.CreateVector>(*subgraphs) : 0; + auto description__ = description ? _fbb.CreateString(description) : 0; + auto buffers__ = buffers ? _fbb.CreateVector>(*buffers) : 0; + auto metadata_buffer__ = metadata_buffer ? _fbb.CreateVector(*metadata_buffer) : 0; + auto metadata__ = metadata ? _fbb.CreateVector>(*metadata) : 0; + auto signature_defs__ = signature_defs ? _fbb.CreateVector>(*signature_defs) : 0; + return tflite::CreateModel( + _fbb, + version, + operator_codes__, + subgraphs__, + description__, + buffers__, + metadata_buffer__, + metadata__, + signature_defs__); +} + +flatbuffers::Offset CreateModel(flatbuffers::FlatBufferBuilder &_fbb, const ModelT *_o, const flatbuffers::rehasher_function_t *_rehasher = nullptr); + +inline CustomQuantizationT *CustomQuantization::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new CustomQuantizationT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void CustomQuantization::UnPackTo(CustomQuantizationT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = custom(); if (_e) { _o->custom.resize(_e->size()); std::copy(_e->begin(), _e->end(), _o->custom.begin()); } } +} + +inline flatbuffers::Offset CustomQuantization::Pack(flatbuffers::FlatBufferBuilder &_fbb, const CustomQuantizationT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateCustomQuantization(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateCustomQuantization(flatbuffers::FlatBufferBuilder &_fbb, const CustomQuantizationT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const CustomQuantizationT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + _fbb.ForceVectorAlignment(_o->custom.size(), sizeof(uint8_t), 16); + auto _custom = _o->custom.size() ? _fbb.CreateVector(_o->custom) : 0; + return tflite::CreateCustomQuantization( + _fbb, + _custom); +} + +inline QuantizationParametersT *QuantizationParameters::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new QuantizationParametersT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void QuantizationParameters::UnPackTo(QuantizationParametersT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = min(); if (_e) { _o->min.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->min[_i] = _e->Get(_i); } } } + { auto _e = max(); if (_e) { _o->max.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->max[_i] = _e->Get(_i); } } } + { auto _e = scale(); if (_e) { _o->scale.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->scale[_i] = _e->Get(_i); } } } + { auto _e = zero_point(); if (_e) { _o->zero_point.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->zero_point[_i] = _e->Get(_i); } } } + { auto _e = details_type(); _o->details.type = _e; } + { auto _e = details(); if (_e) _o->details.value = tflite::QuantizationDetailsUnion::UnPack(_e, details_type(), _resolver); } + { auto _e = quantized_dimension(); _o->quantized_dimension = _e; } +} + +inline flatbuffers::Offset QuantizationParameters::Pack(flatbuffers::FlatBufferBuilder &_fbb, const QuantizationParametersT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateQuantizationParameters(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateQuantizationParameters(flatbuffers::FlatBufferBuilder &_fbb, const QuantizationParametersT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const QuantizationParametersT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _min = _o->min.size() ? _fbb.CreateVector(_o->min) : 0; + auto _max = _o->max.size() ? _fbb.CreateVector(_o->max) : 0; + auto _scale = _o->scale.size() ? _fbb.CreateVector(_o->scale) : 0; + auto _zero_point = _o->zero_point.size() ? _fbb.CreateVector(_o->zero_point) : 0; + auto _details_type = _o->details.type; + auto _details = _o->details.Pack(_fbb); + auto _quantized_dimension = _o->quantized_dimension; + return tflite::CreateQuantizationParameters( + _fbb, + _min, + _max, + _scale, + _zero_point, + _details_type, + _details, + _quantized_dimension); +} + +inline Int32VectorT *Int32Vector::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new Int32VectorT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Int32Vector::UnPackTo(Int32VectorT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = values(); if (_e) { _o->values.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->values[_i] = _e->Get(_i); } } } +} + +inline flatbuffers::Offset Int32Vector::Pack(flatbuffers::FlatBufferBuilder &_fbb, const Int32VectorT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateInt32Vector(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateInt32Vector(flatbuffers::FlatBufferBuilder &_fbb, const Int32VectorT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const Int32VectorT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _values = _o->values.size() ? _fbb.CreateVector(_o->values) : 0; + return tflite::CreateInt32Vector( + _fbb, + _values); +} + +inline Uint16VectorT *Uint16Vector::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new Uint16VectorT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Uint16Vector::UnPackTo(Uint16VectorT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = values(); if (_e) { _o->values.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->values[_i] = _e->Get(_i); } } } +} + +inline flatbuffers::Offset Uint16Vector::Pack(flatbuffers::FlatBufferBuilder &_fbb, const Uint16VectorT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUint16Vector(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUint16Vector(flatbuffers::FlatBufferBuilder &_fbb, const Uint16VectorT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const Uint16VectorT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + _fbb.ForceVectorAlignment(_o->values.size(), sizeof(uint16_t), 4); + auto _values = _o->values.size() ? _fbb.CreateVector(_o->values) : 0; + return tflite::CreateUint16Vector( + _fbb, + _values); +} + +inline Uint8VectorT *Uint8Vector::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new Uint8VectorT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Uint8Vector::UnPackTo(Uint8VectorT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = values(); if (_e) { _o->values.resize(_e->size()); std::copy(_e->begin(), _e->end(), _o->values.begin()); } } +} + +inline flatbuffers::Offset Uint8Vector::Pack(flatbuffers::FlatBufferBuilder &_fbb, const Uint8VectorT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUint8Vector(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUint8Vector(flatbuffers::FlatBufferBuilder &_fbb, const Uint8VectorT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const Uint8VectorT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + _fbb.ForceVectorAlignment(_o->values.size(), sizeof(uint8_t), 4); + auto _values = _o->values.size() ? _fbb.CreateVector(_o->values) : 0; + return tflite::CreateUint8Vector( + _fbb, + _values); +} + +inline DimensionMetadataT *DimensionMetadata::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new DimensionMetadataT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void DimensionMetadata::UnPackTo(DimensionMetadataT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = format(); _o->format = _e; } + { auto _e = dense_size(); _o->dense_size = _e; } + { auto _e = array_segments_type(); _o->array_segments.type = _e; } + { auto _e = array_segments(); if (_e) _o->array_segments.value = tflite::SparseIndexVectorUnion::UnPack(_e, array_segments_type(), _resolver); } + { auto _e = array_indices_type(); _o->array_indices.type = _e; } + { auto _e = array_indices(); if (_e) _o->array_indices.value = tflite::SparseIndexVectorUnion::UnPack(_e, array_indices_type(), _resolver); } +} + +inline flatbuffers::Offset DimensionMetadata::Pack(flatbuffers::FlatBufferBuilder &_fbb, const DimensionMetadataT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateDimensionMetadata(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateDimensionMetadata(flatbuffers::FlatBufferBuilder &_fbb, const DimensionMetadataT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const DimensionMetadataT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _format = _o->format; + auto _dense_size = _o->dense_size; + auto _array_segments_type = _o->array_segments.type; + auto _array_segments = _o->array_segments.Pack(_fbb); + auto _array_indices_type = _o->array_indices.type; + auto _array_indices = _o->array_indices.Pack(_fbb); + return tflite::CreateDimensionMetadata( + _fbb, + _format, + _dense_size, + _array_segments_type, + _array_segments, + _array_indices_type, + _array_indices); +} + +inline SparsityParametersT::SparsityParametersT(const SparsityParametersT &o) + : traversal_order(o.traversal_order), + block_map(o.block_map) { + dim_metadata.reserve(o.dim_metadata.size()); + for (const auto &dim_metadata_ : o.dim_metadata) { dim_metadata.emplace_back((dim_metadata_) ? new tflite::DimensionMetadataT(*dim_metadata_) : nullptr); } +} + +inline SparsityParametersT &SparsityParametersT::operator=(SparsityParametersT o) FLATBUFFERS_NOEXCEPT { + std::swap(traversal_order, o.traversal_order); + std::swap(block_map, o.block_map); + std::swap(dim_metadata, o.dim_metadata); + return *this; +} + +inline SparsityParametersT *SparsityParameters::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SparsityParametersT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SparsityParameters::UnPackTo(SparsityParametersT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = traversal_order(); if (_e) { _o->traversal_order.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->traversal_order[_i] = _e->Get(_i); } } } + { auto _e = block_map(); if (_e) { _o->block_map.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->block_map[_i] = _e->Get(_i); } } } + { auto _e = dim_metadata(); if (_e) { _o->dim_metadata.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->dim_metadata[_i]) { _e->Get(_i)->UnPackTo(_o->dim_metadata[_i].get(), _resolver); } else { _o->dim_metadata[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } +} + +inline flatbuffers::Offset SparsityParameters::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SparsityParametersT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSparsityParameters(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSparsityParameters(flatbuffers::FlatBufferBuilder &_fbb, const SparsityParametersT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SparsityParametersT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _traversal_order = _o->traversal_order.size() ? _fbb.CreateVector(_o->traversal_order) : 0; + auto _block_map = _o->block_map.size() ? _fbb.CreateVector(_o->block_map) : 0; + auto _dim_metadata = _o->dim_metadata.size() ? _fbb.CreateVector> (_o->dim_metadata.size(), [](size_t i, _VectorArgs *__va) { return CreateDimensionMetadata(*__va->__fbb, __va->__o->dim_metadata[i].get(), __va->__rehasher); }, &_va ) : 0; + return tflite::CreateSparsityParameters( + _fbb, + _traversal_order, + _block_map, + _dim_metadata); +} + +inline VariantSubTypeT *VariantSubType::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new VariantSubTypeT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void VariantSubType::UnPackTo(VariantSubTypeT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = shape(); if (_e) { _o->shape.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->shape[_i] = _e->Get(_i); } } } + { auto _e = type(); _o->type = _e; } + { auto _e = has_rank(); _o->has_rank = _e; } +} + +inline flatbuffers::Offset VariantSubType::Pack(flatbuffers::FlatBufferBuilder &_fbb, const VariantSubTypeT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateVariantSubType(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateVariantSubType(flatbuffers::FlatBufferBuilder &_fbb, const VariantSubTypeT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const VariantSubTypeT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _shape = _o->shape.size() ? _fbb.CreateVector(_o->shape) : 0; + auto _type = _o->type; + auto _has_rank = _o->has_rank; + return tflite::CreateVariantSubType( + _fbb, + _shape, + _type, + _has_rank); +} + +inline TensorT::TensorT(const TensorT &o) + : shape(o.shape), + type(o.type), + buffer(o.buffer), + name(o.name), + quantization((o.quantization) ? new tflite::QuantizationParametersT(*o.quantization) : nullptr), + is_variable(o.is_variable), + sparsity((o.sparsity) ? new tflite::SparsityParametersT(*o.sparsity) : nullptr), + shape_signature(o.shape_signature), + has_rank(o.has_rank) { + variant_tensors.reserve(o.variant_tensors.size()); + for (const auto &variant_tensors_ : o.variant_tensors) { variant_tensors.emplace_back((variant_tensors_) ? new tflite::VariantSubTypeT(*variant_tensors_) : nullptr); } +} + +inline TensorT &TensorT::operator=(TensorT o) FLATBUFFERS_NOEXCEPT { + std::swap(shape, o.shape); + std::swap(type, o.type); + std::swap(buffer, o.buffer); + std::swap(name, o.name); + std::swap(quantization, o.quantization); + std::swap(is_variable, o.is_variable); + std::swap(sparsity, o.sparsity); + std::swap(shape_signature, o.shape_signature); + std::swap(has_rank, o.has_rank); + std::swap(variant_tensors, o.variant_tensors); + return *this; +} + +inline TensorT *Tensor::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new TensorT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Tensor::UnPackTo(TensorT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = shape(); if (_e) { _o->shape.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->shape[_i] = _e->Get(_i); } } } + { auto _e = type(); _o->type = _e; } + { auto _e = buffer(); _o->buffer = _e; } + { auto _e = name(); if (_e) _o->name = _e->str(); } + { auto _e = quantization(); if (_e) { if(_o->quantization) { _e->UnPackTo(_o->quantization.get(), _resolver); } else { _o->quantization = std::unique_ptr(_e->UnPack(_resolver)); } } } + { auto _e = is_variable(); _o->is_variable = _e; } + { auto _e = sparsity(); if (_e) { if(_o->sparsity) { _e->UnPackTo(_o->sparsity.get(), _resolver); } else { _o->sparsity = std::unique_ptr(_e->UnPack(_resolver)); } } } + { auto _e = shape_signature(); if (_e) { _o->shape_signature.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->shape_signature[_i] = _e->Get(_i); } } } + { auto _e = has_rank(); _o->has_rank = _e; } + { auto _e = variant_tensors(); if (_e) { _o->variant_tensors.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->variant_tensors[_i]) { _e->Get(_i)->UnPackTo(_o->variant_tensors[_i].get(), _resolver); } else { _o->variant_tensors[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } +} + +inline flatbuffers::Offset Tensor::Pack(flatbuffers::FlatBufferBuilder &_fbb, const TensorT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateTensor(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateTensor(flatbuffers::FlatBufferBuilder &_fbb, const TensorT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const TensorT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _shape = _o->shape.size() ? _fbb.CreateVector(_o->shape) : 0; + auto _type = _o->type; + auto _buffer = _o->buffer; + auto _name = _o->name.empty() ? 0 : _fbb.CreateString(_o->name); + auto _quantization = _o->quantization ? CreateQuantizationParameters(_fbb, _o->quantization.get(), _rehasher) : 0; + auto _is_variable = _o->is_variable; + auto _sparsity = _o->sparsity ? CreateSparsityParameters(_fbb, _o->sparsity.get(), _rehasher) : 0; + auto _shape_signature = _o->shape_signature.size() ? _fbb.CreateVector(_o->shape_signature) : 0; + auto _has_rank = _o->has_rank; + auto _variant_tensors = _o->variant_tensors.size() ? _fbb.CreateVector> (_o->variant_tensors.size(), [](size_t i, _VectorArgs *__va) { return CreateVariantSubType(*__va->__fbb, __va->__o->variant_tensors[i].get(), __va->__rehasher); }, &_va ) : 0; + return tflite::CreateTensor( + _fbb, + _shape, + _type, + _buffer, + _name, + _quantization, + _is_variable, + _sparsity, + _shape_signature, + _has_rank, + _variant_tensors); +} + +inline Conv2DOptionsT *Conv2DOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new Conv2DOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Conv2DOptions::UnPackTo(Conv2DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = padding(); _o->padding = _e; } + { auto _e = stride_w(); _o->stride_w = _e; } + { auto _e = stride_h(); _o->stride_h = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = dilation_w_factor(); _o->dilation_w_factor = _e; } + { auto _e = dilation_h_factor(); _o->dilation_h_factor = _e; } +} + +inline flatbuffers::Offset Conv2DOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const Conv2DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateConv2DOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateConv2DOptions(flatbuffers::FlatBufferBuilder &_fbb, const Conv2DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const Conv2DOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _padding = _o->padding; + auto _stride_w = _o->stride_w; + auto _stride_h = _o->stride_h; + auto _fused_activation_function = _o->fused_activation_function; + auto _dilation_w_factor = _o->dilation_w_factor; + auto _dilation_h_factor = _o->dilation_h_factor; + return tflite::CreateConv2DOptions( + _fbb, + _padding, + _stride_w, + _stride_h, + _fused_activation_function, + _dilation_w_factor, + _dilation_h_factor); +} + +inline Conv3DOptionsT *Conv3DOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new Conv3DOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Conv3DOptions::UnPackTo(Conv3DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = padding(); _o->padding = _e; } + { auto _e = stride_d(); _o->stride_d = _e; } + { auto _e = stride_w(); _o->stride_w = _e; } + { auto _e = stride_h(); _o->stride_h = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = dilation_d_factor(); _o->dilation_d_factor = _e; } + { auto _e = dilation_w_factor(); _o->dilation_w_factor = _e; } + { auto _e = dilation_h_factor(); _o->dilation_h_factor = _e; } +} + +inline flatbuffers::Offset Conv3DOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const Conv3DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateConv3DOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateConv3DOptions(flatbuffers::FlatBufferBuilder &_fbb, const Conv3DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const Conv3DOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _padding = _o->padding; + auto _stride_d = _o->stride_d; + auto _stride_w = _o->stride_w; + auto _stride_h = _o->stride_h; + auto _fused_activation_function = _o->fused_activation_function; + auto _dilation_d_factor = _o->dilation_d_factor; + auto _dilation_w_factor = _o->dilation_w_factor; + auto _dilation_h_factor = _o->dilation_h_factor; + return tflite::CreateConv3DOptions( + _fbb, + _padding, + _stride_d, + _stride_w, + _stride_h, + _fused_activation_function, + _dilation_d_factor, + _dilation_w_factor, + _dilation_h_factor); +} + +inline Pool2DOptionsT *Pool2DOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new Pool2DOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Pool2DOptions::UnPackTo(Pool2DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = padding(); _o->padding = _e; } + { auto _e = stride_w(); _o->stride_w = _e; } + { auto _e = stride_h(); _o->stride_h = _e; } + { auto _e = filter_width(); _o->filter_width = _e; } + { auto _e = filter_height(); _o->filter_height = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } +} + +inline flatbuffers::Offset Pool2DOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const Pool2DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreatePool2DOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreatePool2DOptions(flatbuffers::FlatBufferBuilder &_fbb, const Pool2DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const Pool2DOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _padding = _o->padding; + auto _stride_w = _o->stride_w; + auto _stride_h = _o->stride_h; + auto _filter_width = _o->filter_width; + auto _filter_height = _o->filter_height; + auto _fused_activation_function = _o->fused_activation_function; + return tflite::CreatePool2DOptions( + _fbb, + _padding, + _stride_w, + _stride_h, + _filter_width, + _filter_height, + _fused_activation_function); +} + +inline DepthwiseConv2DOptionsT *DepthwiseConv2DOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new DepthwiseConv2DOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void DepthwiseConv2DOptions::UnPackTo(DepthwiseConv2DOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = padding(); _o->padding = _e; } + { auto _e = stride_w(); _o->stride_w = _e; } + { auto _e = stride_h(); _o->stride_h = _e; } + { auto _e = depth_multiplier(); _o->depth_multiplier = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = dilation_w_factor(); _o->dilation_w_factor = _e; } + { auto _e = dilation_h_factor(); _o->dilation_h_factor = _e; } +} + +inline flatbuffers::Offset DepthwiseConv2DOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const DepthwiseConv2DOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateDepthwiseConv2DOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateDepthwiseConv2DOptions(flatbuffers::FlatBufferBuilder &_fbb, const DepthwiseConv2DOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const DepthwiseConv2DOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _padding = _o->padding; + auto _stride_w = _o->stride_w; + auto _stride_h = _o->stride_h; + auto _depth_multiplier = _o->depth_multiplier; + auto _fused_activation_function = _o->fused_activation_function; + auto _dilation_w_factor = _o->dilation_w_factor; + auto _dilation_h_factor = _o->dilation_h_factor; + return tflite::CreateDepthwiseConv2DOptions( + _fbb, + _padding, + _stride_w, + _stride_h, + _depth_multiplier, + _fused_activation_function, + _dilation_w_factor, + _dilation_h_factor); +} + +inline ConcatEmbeddingsOptionsT *ConcatEmbeddingsOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ConcatEmbeddingsOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ConcatEmbeddingsOptions::UnPackTo(ConcatEmbeddingsOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = num_channels(); _o->num_channels = _e; } + { auto _e = num_columns_per_channel(); if (_e) { _o->num_columns_per_channel.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->num_columns_per_channel[_i] = _e->Get(_i); } } } + { auto _e = embedding_dim_per_channel(); if (_e) { _o->embedding_dim_per_channel.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->embedding_dim_per_channel[_i] = _e->Get(_i); } } } +} + +inline flatbuffers::Offset ConcatEmbeddingsOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ConcatEmbeddingsOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateConcatEmbeddingsOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateConcatEmbeddingsOptions(flatbuffers::FlatBufferBuilder &_fbb, const ConcatEmbeddingsOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ConcatEmbeddingsOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _num_channels = _o->num_channels; + auto _num_columns_per_channel = _o->num_columns_per_channel.size() ? _fbb.CreateVector(_o->num_columns_per_channel) : 0; + auto _embedding_dim_per_channel = _o->embedding_dim_per_channel.size() ? _fbb.CreateVector(_o->embedding_dim_per_channel) : 0; + return tflite::CreateConcatEmbeddingsOptions( + _fbb, + _num_channels, + _num_columns_per_channel, + _embedding_dim_per_channel); +} + +inline LSHProjectionOptionsT *LSHProjectionOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LSHProjectionOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LSHProjectionOptions::UnPackTo(LSHProjectionOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = type(); _o->type = _e; } +} + +inline flatbuffers::Offset LSHProjectionOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LSHProjectionOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLSHProjectionOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLSHProjectionOptions(flatbuffers::FlatBufferBuilder &_fbb, const LSHProjectionOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LSHProjectionOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _type = _o->type; + return tflite::CreateLSHProjectionOptions( + _fbb, + _type); +} + +inline SVDFOptionsT *SVDFOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SVDFOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SVDFOptions::UnPackTo(SVDFOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = rank(); _o->rank = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset SVDFOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SVDFOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSVDFOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSVDFOptions(flatbuffers::FlatBufferBuilder &_fbb, const SVDFOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SVDFOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _rank = _o->rank; + auto _fused_activation_function = _o->fused_activation_function; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateSVDFOptions( + _fbb, + _rank, + _fused_activation_function, + _asymmetric_quantize_inputs); +} + +inline RNNOptionsT *RNNOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new RNNOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void RNNOptions::UnPackTo(RNNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset RNNOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const RNNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateRNNOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateRNNOptions(flatbuffers::FlatBufferBuilder &_fbb, const RNNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const RNNOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateRNNOptions( + _fbb, + _fused_activation_function, + _asymmetric_quantize_inputs); +} + +inline SequenceRNNOptionsT *SequenceRNNOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SequenceRNNOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SequenceRNNOptions::UnPackTo(SequenceRNNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = time_major(); _o->time_major = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset SequenceRNNOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SequenceRNNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSequenceRNNOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSequenceRNNOptions(flatbuffers::FlatBufferBuilder &_fbb, const SequenceRNNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SequenceRNNOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _time_major = _o->time_major; + auto _fused_activation_function = _o->fused_activation_function; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateSequenceRNNOptions( + _fbb, + _time_major, + _fused_activation_function, + _asymmetric_quantize_inputs); +} + +inline BidirectionalSequenceRNNOptionsT *BidirectionalSequenceRNNOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new BidirectionalSequenceRNNOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void BidirectionalSequenceRNNOptions::UnPackTo(BidirectionalSequenceRNNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = time_major(); _o->time_major = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = merge_outputs(); _o->merge_outputs = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset BidirectionalSequenceRNNOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceRNNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateBidirectionalSequenceRNNOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateBidirectionalSequenceRNNOptions(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceRNNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BidirectionalSequenceRNNOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _time_major = _o->time_major; + auto _fused_activation_function = _o->fused_activation_function; + auto _merge_outputs = _o->merge_outputs; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateBidirectionalSequenceRNNOptions( + _fbb, + _time_major, + _fused_activation_function, + _merge_outputs, + _asymmetric_quantize_inputs); +} + +inline FullyConnectedOptionsT *FullyConnectedOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new FullyConnectedOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void FullyConnectedOptions::UnPackTo(FullyConnectedOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = weights_format(); _o->weights_format = _e; } + { auto _e = keep_num_dims(); _o->keep_num_dims = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset FullyConnectedOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const FullyConnectedOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateFullyConnectedOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateFullyConnectedOptions(flatbuffers::FlatBufferBuilder &_fbb, const FullyConnectedOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const FullyConnectedOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + auto _weights_format = _o->weights_format; + auto _keep_num_dims = _o->keep_num_dims; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateFullyConnectedOptions( + _fbb, + _fused_activation_function, + _weights_format, + _keep_num_dims, + _asymmetric_quantize_inputs); +} + +inline SoftmaxOptionsT *SoftmaxOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SoftmaxOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SoftmaxOptions::UnPackTo(SoftmaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = beta(); _o->beta = _e; } +} + +inline flatbuffers::Offset SoftmaxOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SoftmaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSoftmaxOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const SoftmaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SoftmaxOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _beta = _o->beta; + return tflite::CreateSoftmaxOptions( + _fbb, + _beta); +} + +inline ConcatenationOptionsT *ConcatenationOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ConcatenationOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ConcatenationOptions::UnPackTo(ConcatenationOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = axis(); _o->axis = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } +} + +inline flatbuffers::Offset ConcatenationOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ConcatenationOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateConcatenationOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateConcatenationOptions(flatbuffers::FlatBufferBuilder &_fbb, const ConcatenationOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ConcatenationOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _axis = _o->axis; + auto _fused_activation_function = _o->fused_activation_function; + return tflite::CreateConcatenationOptions( + _fbb, + _axis, + _fused_activation_function); +} + +inline AddOptionsT *AddOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new AddOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void AddOptions::UnPackTo(AddOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = pot_scale_int16(); _o->pot_scale_int16 = _e; } +} + +inline flatbuffers::Offset AddOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const AddOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateAddOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateAddOptions(flatbuffers::FlatBufferBuilder &_fbb, const AddOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const AddOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + auto _pot_scale_int16 = _o->pot_scale_int16; + return tflite::CreateAddOptions( + _fbb, + _fused_activation_function, + _pot_scale_int16); +} + +inline MulOptionsT *MulOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new MulOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void MulOptions::UnPackTo(MulOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } +} + +inline flatbuffers::Offset MulOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const MulOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateMulOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateMulOptions(flatbuffers::FlatBufferBuilder &_fbb, const MulOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const MulOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + return tflite::CreateMulOptions( + _fbb, + _fused_activation_function); +} + +inline L2NormOptionsT *L2NormOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new L2NormOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void L2NormOptions::UnPackTo(L2NormOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } +} + +inline flatbuffers::Offset L2NormOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const L2NormOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateL2NormOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateL2NormOptions(flatbuffers::FlatBufferBuilder &_fbb, const L2NormOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const L2NormOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + return tflite::CreateL2NormOptions( + _fbb, + _fused_activation_function); +} + +inline LocalResponseNormalizationOptionsT *LocalResponseNormalizationOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LocalResponseNormalizationOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LocalResponseNormalizationOptions::UnPackTo(LocalResponseNormalizationOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = radius(); _o->radius = _e; } + { auto _e = bias(); _o->bias = _e; } + { auto _e = alpha(); _o->alpha = _e; } + { auto _e = beta(); _o->beta = _e; } +} + +inline flatbuffers::Offset LocalResponseNormalizationOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LocalResponseNormalizationOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLocalResponseNormalizationOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLocalResponseNormalizationOptions(flatbuffers::FlatBufferBuilder &_fbb, const LocalResponseNormalizationOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LocalResponseNormalizationOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _radius = _o->radius; + auto _bias = _o->bias; + auto _alpha = _o->alpha; + auto _beta = _o->beta; + return tflite::CreateLocalResponseNormalizationOptions( + _fbb, + _radius, + _bias, + _alpha, + _beta); +} + +inline LSTMOptionsT *LSTMOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LSTMOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LSTMOptions::UnPackTo(LSTMOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = cell_clip(); _o->cell_clip = _e; } + { auto _e = proj_clip(); _o->proj_clip = _e; } + { auto _e = kernel_type(); _o->kernel_type = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset LSTMOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LSTMOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLSTMOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb, const LSTMOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LSTMOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + auto _cell_clip = _o->cell_clip; + auto _proj_clip = _o->proj_clip; + auto _kernel_type = _o->kernel_type; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateLSTMOptions( + _fbb, + _fused_activation_function, + _cell_clip, + _proj_clip, + _kernel_type, + _asymmetric_quantize_inputs); +} + +inline UnidirectionalSequenceLSTMOptionsT *UnidirectionalSequenceLSTMOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new UnidirectionalSequenceLSTMOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void UnidirectionalSequenceLSTMOptions::UnPackTo(UnidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = cell_clip(); _o->cell_clip = _e; } + { auto _e = proj_clip(); _o->proj_clip = _e; } + { auto _e = time_major(); _o->time_major = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } + { auto _e = diagonal_recurrent_tensors(); _o->diagonal_recurrent_tensors = _e; } +} + +inline flatbuffers::Offset UnidirectionalSequenceLSTMOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnidirectionalSequenceLSTMOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUnidirectionalSequenceLSTMOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUnidirectionalSequenceLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const UnidirectionalSequenceLSTMOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + auto _cell_clip = _o->cell_clip; + auto _proj_clip = _o->proj_clip; + auto _time_major = _o->time_major; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + auto _diagonal_recurrent_tensors = _o->diagonal_recurrent_tensors; + return tflite::CreateUnidirectionalSequenceLSTMOptions( + _fbb, + _fused_activation_function, + _cell_clip, + _proj_clip, + _time_major, + _asymmetric_quantize_inputs, + _diagonal_recurrent_tensors); +} + +inline BidirectionalSequenceLSTMOptionsT *BidirectionalSequenceLSTMOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new BidirectionalSequenceLSTMOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void BidirectionalSequenceLSTMOptions::UnPackTo(BidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = cell_clip(); _o->cell_clip = _e; } + { auto _e = proj_clip(); _o->proj_clip = _e; } + { auto _e = merge_outputs(); _o->merge_outputs = _e; } + { auto _e = time_major(); _o->time_major = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset BidirectionalSequenceLSTMOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceLSTMOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateBidirectionalSequenceLSTMOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateBidirectionalSequenceLSTMOptions(flatbuffers::FlatBufferBuilder &_fbb, const BidirectionalSequenceLSTMOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BidirectionalSequenceLSTMOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + auto _cell_clip = _o->cell_clip; + auto _proj_clip = _o->proj_clip; + auto _merge_outputs = _o->merge_outputs; + auto _time_major = _o->time_major; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateBidirectionalSequenceLSTMOptions( + _fbb, + _fused_activation_function, + _cell_clip, + _proj_clip, + _merge_outputs, + _time_major, + _asymmetric_quantize_inputs); +} + +inline ResizeBilinearOptionsT *ResizeBilinearOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ResizeBilinearOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ResizeBilinearOptions::UnPackTo(ResizeBilinearOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = align_corners(); _o->align_corners = _e; } + { auto _e = half_pixel_centers(); _o->half_pixel_centers = _e; } +} + +inline flatbuffers::Offset ResizeBilinearOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ResizeBilinearOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateResizeBilinearOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateResizeBilinearOptions(flatbuffers::FlatBufferBuilder &_fbb, const ResizeBilinearOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ResizeBilinearOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _align_corners = _o->align_corners; + auto _half_pixel_centers = _o->half_pixel_centers; + return tflite::CreateResizeBilinearOptions( + _fbb, + _align_corners, + _half_pixel_centers); +} + +inline ResizeNearestNeighborOptionsT *ResizeNearestNeighborOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ResizeNearestNeighborOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ResizeNearestNeighborOptions::UnPackTo(ResizeNearestNeighborOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = align_corners(); _o->align_corners = _e; } + { auto _e = half_pixel_centers(); _o->half_pixel_centers = _e; } +} + +inline flatbuffers::Offset ResizeNearestNeighborOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ResizeNearestNeighborOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateResizeNearestNeighborOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateResizeNearestNeighborOptions(flatbuffers::FlatBufferBuilder &_fbb, const ResizeNearestNeighborOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ResizeNearestNeighborOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _align_corners = _o->align_corners; + auto _half_pixel_centers = _o->half_pixel_centers; + return tflite::CreateResizeNearestNeighborOptions( + _fbb, + _align_corners, + _half_pixel_centers); +} + +inline CallOptionsT *CallOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new CallOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void CallOptions::UnPackTo(CallOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = subgraph(); _o->subgraph = _e; } +} + +inline flatbuffers::Offset CallOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const CallOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateCallOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateCallOptions(flatbuffers::FlatBufferBuilder &_fbb, const CallOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const CallOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _subgraph = _o->subgraph; + return tflite::CreateCallOptions( + _fbb, + _subgraph); +} + +inline PadOptionsT *PadOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new PadOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void PadOptions::UnPackTo(PadOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset PadOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const PadOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreatePadOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreatePadOptions(flatbuffers::FlatBufferBuilder &_fbb, const PadOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const PadOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreatePadOptions( + _fbb); +} + +inline PadV2OptionsT *PadV2Options::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new PadV2OptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void PadV2Options::UnPackTo(PadV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset PadV2Options::Pack(flatbuffers::FlatBufferBuilder &_fbb, const PadV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreatePadV2Options(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreatePadV2Options(flatbuffers::FlatBufferBuilder &_fbb, const PadV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const PadV2OptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreatePadV2Options( + _fbb); +} + +inline ReshapeOptionsT *ReshapeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ReshapeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ReshapeOptions::UnPackTo(ReshapeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = new_shape(); if (_e) { _o->new_shape.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->new_shape[_i] = _e->Get(_i); } } } +} + +inline flatbuffers::Offset ReshapeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReshapeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateReshapeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateReshapeOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReshapeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ReshapeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _new_shape = _o->new_shape.size() ? _fbb.CreateVector(_o->new_shape) : 0; + return tflite::CreateReshapeOptions( + _fbb, + _new_shape); +} + +inline SpaceToBatchNDOptionsT *SpaceToBatchNDOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SpaceToBatchNDOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SpaceToBatchNDOptions::UnPackTo(SpaceToBatchNDOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SpaceToBatchNDOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToBatchNDOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSpaceToBatchNDOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSpaceToBatchNDOptions(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToBatchNDOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SpaceToBatchNDOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSpaceToBatchNDOptions( + _fbb); +} + +inline BatchToSpaceNDOptionsT *BatchToSpaceNDOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new BatchToSpaceNDOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void BatchToSpaceNDOptions::UnPackTo(BatchToSpaceNDOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset BatchToSpaceNDOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BatchToSpaceNDOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateBatchToSpaceNDOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateBatchToSpaceNDOptions(flatbuffers::FlatBufferBuilder &_fbb, const BatchToSpaceNDOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BatchToSpaceNDOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateBatchToSpaceNDOptions( + _fbb); +} + +inline SkipGramOptionsT *SkipGramOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SkipGramOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SkipGramOptions::UnPackTo(SkipGramOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = ngram_size(); _o->ngram_size = _e; } + { auto _e = max_skip_size(); _o->max_skip_size = _e; } + { auto _e = include_all_ngrams(); _o->include_all_ngrams = _e; } +} + +inline flatbuffers::Offset SkipGramOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SkipGramOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSkipGramOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSkipGramOptions(flatbuffers::FlatBufferBuilder &_fbb, const SkipGramOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SkipGramOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _ngram_size = _o->ngram_size; + auto _max_skip_size = _o->max_skip_size; + auto _include_all_ngrams = _o->include_all_ngrams; + return tflite::CreateSkipGramOptions( + _fbb, + _ngram_size, + _max_skip_size, + _include_all_ngrams); +} + +inline SpaceToDepthOptionsT *SpaceToDepthOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SpaceToDepthOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SpaceToDepthOptions::UnPackTo(SpaceToDepthOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = block_size(); _o->block_size = _e; } +} + +inline flatbuffers::Offset SpaceToDepthOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToDepthOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSpaceToDepthOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSpaceToDepthOptions(flatbuffers::FlatBufferBuilder &_fbb, const SpaceToDepthOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SpaceToDepthOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _block_size = _o->block_size; + return tflite::CreateSpaceToDepthOptions( + _fbb, + _block_size); +} + +inline DepthToSpaceOptionsT *DepthToSpaceOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new DepthToSpaceOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void DepthToSpaceOptions::UnPackTo(DepthToSpaceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = block_size(); _o->block_size = _e; } +} + +inline flatbuffers::Offset DepthToSpaceOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const DepthToSpaceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateDepthToSpaceOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateDepthToSpaceOptions(flatbuffers::FlatBufferBuilder &_fbb, const DepthToSpaceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const DepthToSpaceOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _block_size = _o->block_size; + return tflite::CreateDepthToSpaceOptions( + _fbb, + _block_size); +} + +inline SubOptionsT *SubOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SubOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SubOptions::UnPackTo(SubOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } + { auto _e = pot_scale_int16(); _o->pot_scale_int16 = _e; } +} + +inline flatbuffers::Offset SubOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SubOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSubOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSubOptions(flatbuffers::FlatBufferBuilder &_fbb, const SubOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SubOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + auto _pot_scale_int16 = _o->pot_scale_int16; + return tflite::CreateSubOptions( + _fbb, + _fused_activation_function, + _pot_scale_int16); +} + +inline DivOptionsT *DivOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new DivOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void DivOptions::UnPackTo(DivOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } +} + +inline flatbuffers::Offset DivOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const DivOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateDivOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateDivOptions(flatbuffers::FlatBufferBuilder &_fbb, const DivOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const DivOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _fused_activation_function = _o->fused_activation_function; + return tflite::CreateDivOptions( + _fbb, + _fused_activation_function); +} + +inline TopKV2OptionsT *TopKV2Options::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new TopKV2OptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void TopKV2Options::UnPackTo(TopKV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset TopKV2Options::Pack(flatbuffers::FlatBufferBuilder &_fbb, const TopKV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateTopKV2Options(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateTopKV2Options(flatbuffers::FlatBufferBuilder &_fbb, const TopKV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const TopKV2OptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateTopKV2Options( + _fbb); +} + +inline EmbeddingLookupSparseOptionsT *EmbeddingLookupSparseOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new EmbeddingLookupSparseOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void EmbeddingLookupSparseOptions::UnPackTo(EmbeddingLookupSparseOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = combiner(); _o->combiner = _e; } +} + +inline flatbuffers::Offset EmbeddingLookupSparseOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const EmbeddingLookupSparseOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateEmbeddingLookupSparseOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateEmbeddingLookupSparseOptions(flatbuffers::FlatBufferBuilder &_fbb, const EmbeddingLookupSparseOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const EmbeddingLookupSparseOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _combiner = _o->combiner; + return tflite::CreateEmbeddingLookupSparseOptions( + _fbb, + _combiner); +} + +inline GatherOptionsT *GatherOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new GatherOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void GatherOptions::UnPackTo(GatherOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = axis(); _o->axis = _e; } + { auto _e = batch_dims(); _o->batch_dims = _e; } +} + +inline flatbuffers::Offset GatherOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const GatherOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateGatherOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateGatherOptions(flatbuffers::FlatBufferBuilder &_fbb, const GatherOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const GatherOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _axis = _o->axis; + auto _batch_dims = _o->batch_dims; + return tflite::CreateGatherOptions( + _fbb, + _axis, + _batch_dims); +} + +inline TransposeOptionsT *TransposeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new TransposeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void TransposeOptions::UnPackTo(TransposeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset TransposeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const TransposeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateTransposeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateTransposeOptions(flatbuffers::FlatBufferBuilder &_fbb, const TransposeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const TransposeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateTransposeOptions( + _fbb); +} + +inline ExpOptionsT *ExpOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ExpOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ExpOptions::UnPackTo(ExpOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset ExpOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ExpOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateExpOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateExpOptions(flatbuffers::FlatBufferBuilder &_fbb, const ExpOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ExpOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateExpOptions( + _fbb); +} + +inline CosOptionsT *CosOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new CosOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void CosOptions::UnPackTo(CosOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset CosOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const CosOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateCosOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateCosOptions(flatbuffers::FlatBufferBuilder &_fbb, const CosOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const CosOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateCosOptions( + _fbb); +} + +inline ReducerOptionsT *ReducerOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ReducerOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ReducerOptions::UnPackTo(ReducerOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = keep_dims(); _o->keep_dims = _e; } +} + +inline flatbuffers::Offset ReducerOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReducerOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateReducerOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateReducerOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReducerOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ReducerOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _keep_dims = _o->keep_dims; + return tflite::CreateReducerOptions( + _fbb, + _keep_dims); +} + +inline SqueezeOptionsT *SqueezeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SqueezeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SqueezeOptions::UnPackTo(SqueezeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = squeeze_dims(); if (_e) { _o->squeeze_dims.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->squeeze_dims[_i] = _e->Get(_i); } } } +} + +inline flatbuffers::Offset SqueezeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SqueezeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSqueezeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSqueezeOptions(flatbuffers::FlatBufferBuilder &_fbb, const SqueezeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SqueezeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _squeeze_dims = _o->squeeze_dims.size() ? _fbb.CreateVector(_o->squeeze_dims) : 0; + return tflite::CreateSqueezeOptions( + _fbb, + _squeeze_dims); +} + +inline SplitOptionsT *SplitOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SplitOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SplitOptions::UnPackTo(SplitOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = num_splits(); _o->num_splits = _e; } +} + +inline flatbuffers::Offset SplitOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SplitOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSplitOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSplitOptions(flatbuffers::FlatBufferBuilder &_fbb, const SplitOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SplitOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _num_splits = _o->num_splits; + return tflite::CreateSplitOptions( + _fbb, + _num_splits); +} + +inline SplitVOptionsT *SplitVOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SplitVOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SplitVOptions::UnPackTo(SplitVOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = num_splits(); _o->num_splits = _e; } +} + +inline flatbuffers::Offset SplitVOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SplitVOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSplitVOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSplitVOptions(flatbuffers::FlatBufferBuilder &_fbb, const SplitVOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SplitVOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _num_splits = _o->num_splits; + return tflite::CreateSplitVOptions( + _fbb, + _num_splits); +} + +inline StridedSliceOptionsT *StridedSliceOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new StridedSliceOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void StridedSliceOptions::UnPackTo(StridedSliceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = begin_mask(); _o->begin_mask = _e; } + { auto _e = end_mask(); _o->end_mask = _e; } + { auto _e = ellipsis_mask(); _o->ellipsis_mask = _e; } + { auto _e = new_axis_mask(); _o->new_axis_mask = _e; } + { auto _e = shrink_axis_mask(); _o->shrink_axis_mask = _e; } +} + +inline flatbuffers::Offset StridedSliceOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const StridedSliceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateStridedSliceOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateStridedSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, const StridedSliceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const StridedSliceOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _begin_mask = _o->begin_mask; + auto _end_mask = _o->end_mask; + auto _ellipsis_mask = _o->ellipsis_mask; + auto _new_axis_mask = _o->new_axis_mask; + auto _shrink_axis_mask = _o->shrink_axis_mask; + return tflite::CreateStridedSliceOptions( + _fbb, + _begin_mask, + _end_mask, + _ellipsis_mask, + _new_axis_mask, + _shrink_axis_mask); +} + +inline LogSoftmaxOptionsT *LogSoftmaxOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LogSoftmaxOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LogSoftmaxOptions::UnPackTo(LogSoftmaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset LogSoftmaxOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogSoftmaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLogSoftmaxOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLogSoftmaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogSoftmaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LogSoftmaxOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateLogSoftmaxOptions( + _fbb); +} + +inline CastOptionsT *CastOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new CastOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void CastOptions::UnPackTo(CastOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = in_data_type(); _o->in_data_type = _e; } + { auto _e = out_data_type(); _o->out_data_type = _e; } +} + +inline flatbuffers::Offset CastOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const CastOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateCastOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateCastOptions(flatbuffers::FlatBufferBuilder &_fbb, const CastOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const CastOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _in_data_type = _o->in_data_type; + auto _out_data_type = _o->out_data_type; + return tflite::CreateCastOptions( + _fbb, + _in_data_type, + _out_data_type); +} + +inline DequantizeOptionsT *DequantizeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new DequantizeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void DequantizeOptions::UnPackTo(DequantizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset DequantizeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const DequantizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateDequantizeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateDequantizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const DequantizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const DequantizeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateDequantizeOptions( + _fbb); +} + +inline MaximumMinimumOptionsT *MaximumMinimumOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new MaximumMinimumOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void MaximumMinimumOptions::UnPackTo(MaximumMinimumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset MaximumMinimumOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const MaximumMinimumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateMaximumMinimumOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateMaximumMinimumOptions(flatbuffers::FlatBufferBuilder &_fbb, const MaximumMinimumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const MaximumMinimumOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateMaximumMinimumOptions( + _fbb); +} + +inline TileOptionsT *TileOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new TileOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void TileOptions::UnPackTo(TileOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset TileOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const TileOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateTileOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateTileOptions(flatbuffers::FlatBufferBuilder &_fbb, const TileOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const TileOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateTileOptions( + _fbb); +} + +inline ArgMaxOptionsT *ArgMaxOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ArgMaxOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ArgMaxOptions::UnPackTo(ArgMaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = output_type(); _o->output_type = _e; } +} + +inline flatbuffers::Offset ArgMaxOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ArgMaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateArgMaxOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateArgMaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const ArgMaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ArgMaxOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _output_type = _o->output_type; + return tflite::CreateArgMaxOptions( + _fbb, + _output_type); +} + +inline ArgMinOptionsT *ArgMinOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ArgMinOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ArgMinOptions::UnPackTo(ArgMinOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = output_type(); _o->output_type = _e; } +} + +inline flatbuffers::Offset ArgMinOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ArgMinOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateArgMinOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateArgMinOptions(flatbuffers::FlatBufferBuilder &_fbb, const ArgMinOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ArgMinOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _output_type = _o->output_type; + return tflite::CreateArgMinOptions( + _fbb, + _output_type); +} + +inline GreaterOptionsT *GreaterOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new GreaterOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void GreaterOptions::UnPackTo(GreaterOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset GreaterOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const GreaterOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateGreaterOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateGreaterOptions(flatbuffers::FlatBufferBuilder &_fbb, const GreaterOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const GreaterOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateGreaterOptions( + _fbb); +} + +inline GreaterEqualOptionsT *GreaterEqualOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new GreaterEqualOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void GreaterEqualOptions::UnPackTo(GreaterEqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset GreaterEqualOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const GreaterEqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateGreaterEqualOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateGreaterEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const GreaterEqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const GreaterEqualOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateGreaterEqualOptions( + _fbb); +} + +inline LessOptionsT *LessOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LessOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LessOptions::UnPackTo(LessOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset LessOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LessOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLessOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLessOptions(flatbuffers::FlatBufferBuilder &_fbb, const LessOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LessOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateLessOptions( + _fbb); +} + +inline LessEqualOptionsT *LessEqualOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LessEqualOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LessEqualOptions::UnPackTo(LessEqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset LessEqualOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LessEqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLessEqualOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLessEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const LessEqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LessEqualOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateLessEqualOptions( + _fbb); +} + +inline NegOptionsT *NegOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new NegOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void NegOptions::UnPackTo(NegOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset NegOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const NegOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateNegOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateNegOptions(flatbuffers::FlatBufferBuilder &_fbb, const NegOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const NegOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateNegOptions( + _fbb); +} + +inline SelectOptionsT *SelectOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SelectOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SelectOptions::UnPackTo(SelectOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SelectOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SelectOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSelectOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSelectOptions(flatbuffers::FlatBufferBuilder &_fbb, const SelectOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SelectOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSelectOptions( + _fbb); +} + +inline SliceOptionsT *SliceOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SliceOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SliceOptions::UnPackTo(SliceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SliceOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SliceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSliceOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, const SliceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SliceOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSliceOptions( + _fbb); +} + +inline TransposeConvOptionsT *TransposeConvOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new TransposeConvOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void TransposeConvOptions::UnPackTo(TransposeConvOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = padding(); _o->padding = _e; } + { auto _e = stride_w(); _o->stride_w = _e; } + { auto _e = stride_h(); _o->stride_h = _e; } + { auto _e = fused_activation_function(); _o->fused_activation_function = _e; } +} + +inline flatbuffers::Offset TransposeConvOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const TransposeConvOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateTransposeConvOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateTransposeConvOptions(flatbuffers::FlatBufferBuilder &_fbb, const TransposeConvOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const TransposeConvOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _padding = _o->padding; + auto _stride_w = _o->stride_w; + auto _stride_h = _o->stride_h; + auto _fused_activation_function = _o->fused_activation_function; + return tflite::CreateTransposeConvOptions( + _fbb, + _padding, + _stride_w, + _stride_h, + _fused_activation_function); +} + +inline ExpandDimsOptionsT *ExpandDimsOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ExpandDimsOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ExpandDimsOptions::UnPackTo(ExpandDimsOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset ExpandDimsOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ExpandDimsOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateExpandDimsOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateExpandDimsOptions(flatbuffers::FlatBufferBuilder &_fbb, const ExpandDimsOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ExpandDimsOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateExpandDimsOptions( + _fbb); +} + +inline SparseToDenseOptionsT *SparseToDenseOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SparseToDenseOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SparseToDenseOptions::UnPackTo(SparseToDenseOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = validate_indices(); _o->validate_indices = _e; } +} + +inline flatbuffers::Offset SparseToDenseOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SparseToDenseOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSparseToDenseOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSparseToDenseOptions(flatbuffers::FlatBufferBuilder &_fbb, const SparseToDenseOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SparseToDenseOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _validate_indices = _o->validate_indices; + return tflite::CreateSparseToDenseOptions( + _fbb, + _validate_indices); +} + +inline EqualOptionsT *EqualOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new EqualOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void EqualOptions::UnPackTo(EqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset EqualOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const EqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateEqualOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const EqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const EqualOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateEqualOptions( + _fbb); +} + +inline NotEqualOptionsT *NotEqualOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new NotEqualOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void NotEqualOptions::UnPackTo(NotEqualOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset NotEqualOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const NotEqualOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateNotEqualOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateNotEqualOptions(flatbuffers::FlatBufferBuilder &_fbb, const NotEqualOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const NotEqualOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateNotEqualOptions( + _fbb); +} + +inline ShapeOptionsT *ShapeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ShapeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ShapeOptions::UnPackTo(ShapeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = out_type(); _o->out_type = _e; } +} + +inline flatbuffers::Offset ShapeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ShapeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateShapeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateShapeOptions(flatbuffers::FlatBufferBuilder &_fbb, const ShapeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ShapeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _out_type = _o->out_type; + return tflite::CreateShapeOptions( + _fbb, + _out_type); +} + +inline RankOptionsT *RankOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new RankOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void RankOptions::UnPackTo(RankOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset RankOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const RankOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateRankOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateRankOptions(flatbuffers::FlatBufferBuilder &_fbb, const RankOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const RankOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateRankOptions( + _fbb); +} + +inline PowOptionsT *PowOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new PowOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void PowOptions::UnPackTo(PowOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset PowOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const PowOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreatePowOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreatePowOptions(flatbuffers::FlatBufferBuilder &_fbb, const PowOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const PowOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreatePowOptions( + _fbb); +} + +inline FakeQuantOptionsT *FakeQuantOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new FakeQuantOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void FakeQuantOptions::UnPackTo(FakeQuantOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = min(); _o->min = _e; } + { auto _e = max(); _o->max = _e; } + { auto _e = num_bits(); _o->num_bits = _e; } + { auto _e = narrow_range(); _o->narrow_range = _e; } +} + +inline flatbuffers::Offset FakeQuantOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const FakeQuantOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateFakeQuantOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateFakeQuantOptions(flatbuffers::FlatBufferBuilder &_fbb, const FakeQuantOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const FakeQuantOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _min = _o->min; + auto _max = _o->max; + auto _num_bits = _o->num_bits; + auto _narrow_range = _o->narrow_range; + return tflite::CreateFakeQuantOptions( + _fbb, + _min, + _max, + _num_bits, + _narrow_range); +} + +inline PackOptionsT *PackOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new PackOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void PackOptions::UnPackTo(PackOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = values_count(); _o->values_count = _e; } + { auto _e = axis(); _o->axis = _e; } +} + +inline flatbuffers::Offset PackOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const PackOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreatePackOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreatePackOptions(flatbuffers::FlatBufferBuilder &_fbb, const PackOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const PackOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _values_count = _o->values_count; + auto _axis = _o->axis; + return tflite::CreatePackOptions( + _fbb, + _values_count, + _axis); +} + +inline LogicalOrOptionsT *LogicalOrOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LogicalOrOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LogicalOrOptions::UnPackTo(LogicalOrOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset LogicalOrOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogicalOrOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLogicalOrOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLogicalOrOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogicalOrOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LogicalOrOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateLogicalOrOptions( + _fbb); +} + +inline OneHotOptionsT *OneHotOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new OneHotOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void OneHotOptions::UnPackTo(OneHotOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = axis(); _o->axis = _e; } +} + +inline flatbuffers::Offset OneHotOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const OneHotOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateOneHotOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateOneHotOptions(flatbuffers::FlatBufferBuilder &_fbb, const OneHotOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const OneHotOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _axis = _o->axis; + return tflite::CreateOneHotOptions( + _fbb, + _axis); +} + +inline AbsOptionsT *AbsOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new AbsOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void AbsOptions::UnPackTo(AbsOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset AbsOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const AbsOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateAbsOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateAbsOptions(flatbuffers::FlatBufferBuilder &_fbb, const AbsOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const AbsOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateAbsOptions( + _fbb); +} + +inline HardSwishOptionsT *HardSwishOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new HardSwishOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void HardSwishOptions::UnPackTo(HardSwishOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset HardSwishOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const HardSwishOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateHardSwishOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateHardSwishOptions(flatbuffers::FlatBufferBuilder &_fbb, const HardSwishOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const HardSwishOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateHardSwishOptions( + _fbb); +} + +inline LogicalAndOptionsT *LogicalAndOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LogicalAndOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LogicalAndOptions::UnPackTo(LogicalAndOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset LogicalAndOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogicalAndOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLogicalAndOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLogicalAndOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogicalAndOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LogicalAndOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateLogicalAndOptions( + _fbb); +} + +inline LogicalNotOptionsT *LogicalNotOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LogicalNotOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LogicalNotOptions::UnPackTo(LogicalNotOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset LogicalNotOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LogicalNotOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLogicalNotOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLogicalNotOptions(flatbuffers::FlatBufferBuilder &_fbb, const LogicalNotOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LogicalNotOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateLogicalNotOptions( + _fbb); +} + +inline UnpackOptionsT *UnpackOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new UnpackOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void UnpackOptions::UnPackTo(UnpackOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = num(); _o->num = _e; } + { auto _e = axis(); _o->axis = _e; } +} + +inline flatbuffers::Offset UnpackOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnpackOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUnpackOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUnpackOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnpackOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const UnpackOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _num = _o->num; + auto _axis = _o->axis; + return tflite::CreateUnpackOptions( + _fbb, + _num, + _axis); +} + +inline FloorDivOptionsT *FloorDivOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new FloorDivOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void FloorDivOptions::UnPackTo(FloorDivOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset FloorDivOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const FloorDivOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateFloorDivOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateFloorDivOptions(flatbuffers::FlatBufferBuilder &_fbb, const FloorDivOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const FloorDivOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateFloorDivOptions( + _fbb); +} + +inline SquareOptionsT *SquareOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SquareOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SquareOptions::UnPackTo(SquareOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SquareOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SquareOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSquareOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSquareOptions(flatbuffers::FlatBufferBuilder &_fbb, const SquareOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SquareOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSquareOptions( + _fbb); +} + +inline ZerosLikeOptionsT *ZerosLikeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ZerosLikeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ZerosLikeOptions::UnPackTo(ZerosLikeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset ZerosLikeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ZerosLikeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateZerosLikeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateZerosLikeOptions(flatbuffers::FlatBufferBuilder &_fbb, const ZerosLikeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ZerosLikeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateZerosLikeOptions( + _fbb); +} + +inline FillOptionsT *FillOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new FillOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void FillOptions::UnPackTo(FillOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset FillOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const FillOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateFillOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateFillOptions(flatbuffers::FlatBufferBuilder &_fbb, const FillOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const FillOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateFillOptions( + _fbb); +} + +inline FloorModOptionsT *FloorModOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new FloorModOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void FloorModOptions::UnPackTo(FloorModOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset FloorModOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const FloorModOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateFloorModOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateFloorModOptions(flatbuffers::FlatBufferBuilder &_fbb, const FloorModOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const FloorModOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateFloorModOptions( + _fbb); +} + +inline RangeOptionsT *RangeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new RangeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void RangeOptions::UnPackTo(RangeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset RangeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const RangeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateRangeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateRangeOptions(flatbuffers::FlatBufferBuilder &_fbb, const RangeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const RangeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateRangeOptions( + _fbb); +} + +inline LeakyReluOptionsT *LeakyReluOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new LeakyReluOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void LeakyReluOptions::UnPackTo(LeakyReluOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = alpha(); _o->alpha = _e; } +} + +inline flatbuffers::Offset LeakyReluOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const LeakyReluOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateLeakyReluOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateLeakyReluOptions(flatbuffers::FlatBufferBuilder &_fbb, const LeakyReluOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const LeakyReluOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _alpha = _o->alpha; + return tflite::CreateLeakyReluOptions( + _fbb, + _alpha); +} + +inline SquaredDifferenceOptionsT *SquaredDifferenceOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SquaredDifferenceOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SquaredDifferenceOptions::UnPackTo(SquaredDifferenceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SquaredDifferenceOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SquaredDifferenceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSquaredDifferenceOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSquaredDifferenceOptions(flatbuffers::FlatBufferBuilder &_fbb, const SquaredDifferenceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SquaredDifferenceOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSquaredDifferenceOptions( + _fbb); +} + +inline MirrorPadOptionsT *MirrorPadOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new MirrorPadOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void MirrorPadOptions::UnPackTo(MirrorPadOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = mode(); _o->mode = _e; } +} + +inline flatbuffers::Offset MirrorPadOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const MirrorPadOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateMirrorPadOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateMirrorPadOptions(flatbuffers::FlatBufferBuilder &_fbb, const MirrorPadOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const MirrorPadOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _mode = _o->mode; + return tflite::CreateMirrorPadOptions( + _fbb, + _mode); +} + +inline UniqueOptionsT *UniqueOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new UniqueOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void UniqueOptions::UnPackTo(UniqueOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = idx_out_type(); _o->idx_out_type = _e; } +} + +inline flatbuffers::Offset UniqueOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const UniqueOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUniqueOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUniqueOptions(flatbuffers::FlatBufferBuilder &_fbb, const UniqueOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const UniqueOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _idx_out_type = _o->idx_out_type; + return tflite::CreateUniqueOptions( + _fbb, + _idx_out_type); +} + +inline ReverseV2OptionsT *ReverseV2Options::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ReverseV2OptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ReverseV2Options::UnPackTo(ReverseV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset ReverseV2Options::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReverseV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateReverseV2Options(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateReverseV2Options(flatbuffers::FlatBufferBuilder &_fbb, const ReverseV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ReverseV2OptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateReverseV2Options( + _fbb); +} + +inline AddNOptionsT *AddNOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new AddNOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void AddNOptions::UnPackTo(AddNOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset AddNOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const AddNOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateAddNOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateAddNOptions(flatbuffers::FlatBufferBuilder &_fbb, const AddNOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const AddNOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateAddNOptions( + _fbb); +} + +inline GatherNdOptionsT *GatherNdOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new GatherNdOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void GatherNdOptions::UnPackTo(GatherNdOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset GatherNdOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const GatherNdOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateGatherNdOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateGatherNdOptions(flatbuffers::FlatBufferBuilder &_fbb, const GatherNdOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const GatherNdOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateGatherNdOptions( + _fbb); +} + +inline WhereOptionsT *WhereOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new WhereOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void WhereOptions::UnPackTo(WhereOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset WhereOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const WhereOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateWhereOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateWhereOptions(flatbuffers::FlatBufferBuilder &_fbb, const WhereOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const WhereOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateWhereOptions( + _fbb); +} + +inline ReverseSequenceOptionsT *ReverseSequenceOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ReverseSequenceOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ReverseSequenceOptions::UnPackTo(ReverseSequenceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = seq_dim(); _o->seq_dim = _e; } + { auto _e = batch_dim(); _o->batch_dim = _e; } +} + +inline flatbuffers::Offset ReverseSequenceOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReverseSequenceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateReverseSequenceOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateReverseSequenceOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReverseSequenceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ReverseSequenceOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _seq_dim = _o->seq_dim; + auto _batch_dim = _o->batch_dim; + return tflite::CreateReverseSequenceOptions( + _fbb, + _seq_dim, + _batch_dim); +} + +inline MatrixDiagOptionsT *MatrixDiagOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new MatrixDiagOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void MatrixDiagOptions::UnPackTo(MatrixDiagOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset MatrixDiagOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const MatrixDiagOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateMatrixDiagOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateMatrixDiagOptions(flatbuffers::FlatBufferBuilder &_fbb, const MatrixDiagOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const MatrixDiagOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateMatrixDiagOptions( + _fbb); +} + +inline QuantizeOptionsT *QuantizeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new QuantizeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void QuantizeOptions::UnPackTo(QuantizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset QuantizeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const QuantizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateQuantizeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateQuantizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const QuantizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const QuantizeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateQuantizeOptions( + _fbb); +} + +inline MatrixSetDiagOptionsT *MatrixSetDiagOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new MatrixSetDiagOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void MatrixSetDiagOptions::UnPackTo(MatrixSetDiagOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset MatrixSetDiagOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const MatrixSetDiagOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateMatrixSetDiagOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateMatrixSetDiagOptions(flatbuffers::FlatBufferBuilder &_fbb, const MatrixSetDiagOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const MatrixSetDiagOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateMatrixSetDiagOptions( + _fbb); +} + +inline IfOptionsT *IfOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new IfOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void IfOptions::UnPackTo(IfOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = then_subgraph_index(); _o->then_subgraph_index = _e; } + { auto _e = else_subgraph_index(); _o->else_subgraph_index = _e; } +} + +inline flatbuffers::Offset IfOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const IfOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateIfOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateIfOptions(flatbuffers::FlatBufferBuilder &_fbb, const IfOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const IfOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _then_subgraph_index = _o->then_subgraph_index; + auto _else_subgraph_index = _o->else_subgraph_index; + return tflite::CreateIfOptions( + _fbb, + _then_subgraph_index, + _else_subgraph_index); +} + +inline CallOnceOptionsT *CallOnceOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new CallOnceOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void CallOnceOptions::UnPackTo(CallOnceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = init_subgraph_index(); _o->init_subgraph_index = _e; } +} + +inline flatbuffers::Offset CallOnceOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const CallOnceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateCallOnceOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateCallOnceOptions(flatbuffers::FlatBufferBuilder &_fbb, const CallOnceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const CallOnceOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _init_subgraph_index = _o->init_subgraph_index; + return tflite::CreateCallOnceOptions( + _fbb, + _init_subgraph_index); +} + +inline WhileOptionsT *WhileOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new WhileOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void WhileOptions::UnPackTo(WhileOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = cond_subgraph_index(); _o->cond_subgraph_index = _e; } + { auto _e = body_subgraph_index(); _o->body_subgraph_index = _e; } +} + +inline flatbuffers::Offset WhileOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const WhileOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateWhileOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateWhileOptions(flatbuffers::FlatBufferBuilder &_fbb, const WhileOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const WhileOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _cond_subgraph_index = _o->cond_subgraph_index; + auto _body_subgraph_index = _o->body_subgraph_index; + return tflite::CreateWhileOptions( + _fbb, + _cond_subgraph_index, + _body_subgraph_index); +} + +inline NonMaxSuppressionV4OptionsT *NonMaxSuppressionV4Options::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new NonMaxSuppressionV4OptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void NonMaxSuppressionV4Options::UnPackTo(NonMaxSuppressionV4OptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset NonMaxSuppressionV4Options::Pack(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV4OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateNonMaxSuppressionV4Options(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateNonMaxSuppressionV4Options(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV4OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const NonMaxSuppressionV4OptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateNonMaxSuppressionV4Options( + _fbb); +} + +inline NonMaxSuppressionV5OptionsT *NonMaxSuppressionV5Options::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new NonMaxSuppressionV5OptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void NonMaxSuppressionV5Options::UnPackTo(NonMaxSuppressionV5OptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset NonMaxSuppressionV5Options::Pack(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV5OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateNonMaxSuppressionV5Options(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateNonMaxSuppressionV5Options(flatbuffers::FlatBufferBuilder &_fbb, const NonMaxSuppressionV5OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const NonMaxSuppressionV5OptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateNonMaxSuppressionV5Options( + _fbb); +} + +inline ScatterNdOptionsT *ScatterNdOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ScatterNdOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ScatterNdOptions::UnPackTo(ScatterNdOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset ScatterNdOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ScatterNdOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateScatterNdOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateScatterNdOptions(flatbuffers::FlatBufferBuilder &_fbb, const ScatterNdOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ScatterNdOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateScatterNdOptions( + _fbb); +} + +inline SelectV2OptionsT *SelectV2Options::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SelectV2OptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SelectV2Options::UnPackTo(SelectV2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SelectV2Options::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SelectV2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSelectV2Options(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSelectV2Options(flatbuffers::FlatBufferBuilder &_fbb, const SelectV2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SelectV2OptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSelectV2Options( + _fbb); +} + +inline DensifyOptionsT *DensifyOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new DensifyOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void DensifyOptions::UnPackTo(DensifyOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset DensifyOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const DensifyOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateDensifyOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateDensifyOptions(flatbuffers::FlatBufferBuilder &_fbb, const DensifyOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const DensifyOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateDensifyOptions( + _fbb); +} + +inline SegmentSumOptionsT *SegmentSumOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SegmentSumOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SegmentSumOptions::UnPackTo(SegmentSumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SegmentSumOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SegmentSumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSegmentSumOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSegmentSumOptions(flatbuffers::FlatBufferBuilder &_fbb, const SegmentSumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SegmentSumOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSegmentSumOptions( + _fbb); +} + +inline BatchMatMulOptionsT *BatchMatMulOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new BatchMatMulOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void BatchMatMulOptions::UnPackTo(BatchMatMulOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = adj_x(); _o->adj_x = _e; } + { auto _e = adj_y(); _o->adj_y = _e; } + { auto _e = asymmetric_quantize_inputs(); _o->asymmetric_quantize_inputs = _e; } +} + +inline flatbuffers::Offset BatchMatMulOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BatchMatMulOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateBatchMatMulOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateBatchMatMulOptions(flatbuffers::FlatBufferBuilder &_fbb, const BatchMatMulOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BatchMatMulOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _adj_x = _o->adj_x; + auto _adj_y = _o->adj_y; + auto _asymmetric_quantize_inputs = _o->asymmetric_quantize_inputs; + return tflite::CreateBatchMatMulOptions( + _fbb, + _adj_x, + _adj_y, + _asymmetric_quantize_inputs); +} + +inline CumsumOptionsT *CumsumOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new CumsumOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void CumsumOptions::UnPackTo(CumsumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = exclusive(); _o->exclusive = _e; } + { auto _e = reverse(); _o->reverse = _e; } +} + +inline flatbuffers::Offset CumsumOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const CumsumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateCumsumOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateCumsumOptions(flatbuffers::FlatBufferBuilder &_fbb, const CumsumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const CumsumOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _exclusive = _o->exclusive; + auto _reverse = _o->reverse; + return tflite::CreateCumsumOptions( + _fbb, + _exclusive, + _reverse); +} + +inline BroadcastToOptionsT *BroadcastToOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new BroadcastToOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void BroadcastToOptions::UnPackTo(BroadcastToOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset BroadcastToOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BroadcastToOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateBroadcastToOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateBroadcastToOptions(flatbuffers::FlatBufferBuilder &_fbb, const BroadcastToOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BroadcastToOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateBroadcastToOptions( + _fbb); +} + +inline Rfft2dOptionsT *Rfft2dOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new Rfft2dOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Rfft2dOptions::UnPackTo(Rfft2dOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset Rfft2dOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const Rfft2dOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateRfft2dOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateRfft2dOptions(flatbuffers::FlatBufferBuilder &_fbb, const Rfft2dOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const Rfft2dOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateRfft2dOptions( + _fbb); +} + +inline HashtableOptionsT *HashtableOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new HashtableOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void HashtableOptions::UnPackTo(HashtableOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = table_id(); _o->table_id = _e; } + { auto _e = key_dtype(); _o->key_dtype = _e; } + { auto _e = value_dtype(); _o->value_dtype = _e; } +} + +inline flatbuffers::Offset HashtableOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateHashtableOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateHashtableOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const HashtableOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _table_id = _o->table_id; + auto _key_dtype = _o->key_dtype; + auto _value_dtype = _o->value_dtype; + return tflite::CreateHashtableOptions( + _fbb, + _table_id, + _key_dtype, + _value_dtype); +} + +inline HashtableFindOptionsT *HashtableFindOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new HashtableFindOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void HashtableFindOptions::UnPackTo(HashtableFindOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset HashtableFindOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableFindOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateHashtableFindOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateHashtableFindOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableFindOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const HashtableFindOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateHashtableFindOptions( + _fbb); +} + +inline HashtableImportOptionsT *HashtableImportOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new HashtableImportOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void HashtableImportOptions::UnPackTo(HashtableImportOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset HashtableImportOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableImportOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateHashtableImportOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateHashtableImportOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableImportOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const HashtableImportOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateHashtableImportOptions( + _fbb); +} + +inline HashtableSizeOptionsT *HashtableSizeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new HashtableSizeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void HashtableSizeOptions::UnPackTo(HashtableSizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset HashtableSizeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const HashtableSizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateHashtableSizeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateHashtableSizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const HashtableSizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const HashtableSizeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateHashtableSizeOptions( + _fbb); +} + +inline VarHandleOptionsT *VarHandleOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new VarHandleOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void VarHandleOptions::UnPackTo(VarHandleOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = container(); if (_e) _o->container = _e->str(); } + { auto _e = shared_name(); if (_e) _o->shared_name = _e->str(); } +} + +inline flatbuffers::Offset VarHandleOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const VarHandleOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateVarHandleOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateVarHandleOptions(flatbuffers::FlatBufferBuilder &_fbb, const VarHandleOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const VarHandleOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _container = _o->container.empty() ? 0 : _fbb.CreateString(_o->container); + auto _shared_name = _o->shared_name.empty() ? 0 : _fbb.CreateString(_o->shared_name); + return tflite::CreateVarHandleOptions( + _fbb, + _container, + _shared_name); +} + +inline ReadVariableOptionsT *ReadVariableOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ReadVariableOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ReadVariableOptions::UnPackTo(ReadVariableOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset ReadVariableOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ReadVariableOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateReadVariableOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateReadVariableOptions(flatbuffers::FlatBufferBuilder &_fbb, const ReadVariableOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ReadVariableOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateReadVariableOptions( + _fbb); +} + +inline AssignVariableOptionsT *AssignVariableOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new AssignVariableOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void AssignVariableOptions::UnPackTo(AssignVariableOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset AssignVariableOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const AssignVariableOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateAssignVariableOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateAssignVariableOptions(flatbuffers::FlatBufferBuilder &_fbb, const AssignVariableOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const AssignVariableOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateAssignVariableOptions( + _fbb); +} + +inline RandomOptionsT *RandomOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new RandomOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void RandomOptions::UnPackTo(RandomOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = seed(); _o->seed = _e; } + { auto _e = seed2(); _o->seed2 = _e; } +} + +inline flatbuffers::Offset RandomOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const RandomOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateRandomOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateRandomOptions(flatbuffers::FlatBufferBuilder &_fbb, const RandomOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const RandomOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _seed = _o->seed; + auto _seed2 = _o->seed2; + return tflite::CreateRandomOptions( + _fbb, + _seed, + _seed2); +} + +inline BucketizeOptionsT *BucketizeOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new BucketizeOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void BucketizeOptions::UnPackTo(BucketizeOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = boundaries(); if (_e) { _o->boundaries.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->boundaries[_i] = _e->Get(_i); } } } +} + +inline flatbuffers::Offset BucketizeOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BucketizeOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateBucketizeOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateBucketizeOptions(flatbuffers::FlatBufferBuilder &_fbb, const BucketizeOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BucketizeOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _boundaries = _o->boundaries.size() ? _fbb.CreateVector(_o->boundaries) : 0; + return tflite::CreateBucketizeOptions( + _fbb, + _boundaries); +} + +inline GeluOptionsT *GeluOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new GeluOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void GeluOptions::UnPackTo(GeluOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = approximate(); _o->approximate = _e; } +} + +inline flatbuffers::Offset GeluOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const GeluOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateGeluOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateGeluOptions(flatbuffers::FlatBufferBuilder &_fbb, const GeluOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const GeluOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _approximate = _o->approximate; + return tflite::CreateGeluOptions( + _fbb, + _approximate); +} + +inline DynamicUpdateSliceOptionsT *DynamicUpdateSliceOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new DynamicUpdateSliceOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void DynamicUpdateSliceOptions::UnPackTo(DynamicUpdateSliceOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset DynamicUpdateSliceOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const DynamicUpdateSliceOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateDynamicUpdateSliceOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateDynamicUpdateSliceOptions(flatbuffers::FlatBufferBuilder &_fbb, const DynamicUpdateSliceOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const DynamicUpdateSliceOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateDynamicUpdateSliceOptions( + _fbb); +} + +inline UnsortedSegmentProdOptionsT *UnsortedSegmentProdOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new UnsortedSegmentProdOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void UnsortedSegmentProdOptions::UnPackTo(UnsortedSegmentProdOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset UnsortedSegmentProdOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentProdOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUnsortedSegmentProdOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUnsortedSegmentProdOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentProdOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const UnsortedSegmentProdOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateUnsortedSegmentProdOptions( + _fbb); +} + +inline UnsortedSegmentMaxOptionsT *UnsortedSegmentMaxOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new UnsortedSegmentMaxOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void UnsortedSegmentMaxOptions::UnPackTo(UnsortedSegmentMaxOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset UnsortedSegmentMaxOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMaxOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUnsortedSegmentMaxOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUnsortedSegmentMaxOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMaxOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const UnsortedSegmentMaxOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateUnsortedSegmentMaxOptions( + _fbb); +} + +inline UnsortedSegmentSumOptionsT *UnsortedSegmentSumOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new UnsortedSegmentSumOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void UnsortedSegmentSumOptions::UnPackTo(UnsortedSegmentSumOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset UnsortedSegmentSumOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentSumOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUnsortedSegmentSumOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUnsortedSegmentSumOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentSumOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const UnsortedSegmentSumOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateUnsortedSegmentSumOptions( + _fbb); +} + +inline ATan2OptionsT *ATan2Options::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ATan2OptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void ATan2Options::UnPackTo(ATan2OptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset ATan2Options::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ATan2OptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateATan2Options(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateATan2Options(flatbuffers::FlatBufferBuilder &_fbb, const ATan2OptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ATan2OptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateATan2Options( + _fbb); +} + +inline UnsortedSegmentMinOptionsT *UnsortedSegmentMinOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new UnsortedSegmentMinOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void UnsortedSegmentMinOptions::UnPackTo(UnsortedSegmentMinOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset UnsortedSegmentMinOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMinOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateUnsortedSegmentMinOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateUnsortedSegmentMinOptions(flatbuffers::FlatBufferBuilder &_fbb, const UnsortedSegmentMinOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const UnsortedSegmentMinOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateUnsortedSegmentMinOptions( + _fbb); +} + +inline SignOptionsT *SignOptions::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SignOptionsT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SignOptions::UnPackTo(SignOptionsT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; +} + +inline flatbuffers::Offset SignOptions::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SignOptionsT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSignOptions(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSignOptions(flatbuffers::FlatBufferBuilder &_fbb, const SignOptionsT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SignOptionsT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + return tflite::CreateSignOptions( + _fbb); +} + +inline OperatorCodeT *OperatorCode::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new OperatorCodeT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void OperatorCode::UnPackTo(OperatorCodeT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = deprecated_builtin_code(); _o->deprecated_builtin_code = _e; } + { auto _e = custom_code(); if (_e) _o->custom_code = _e->str(); } + { auto _e = version(); _o->version = _e; } + { auto _e = builtin_code(); _o->builtin_code = _e; } +} + +inline flatbuffers::Offset OperatorCode::Pack(flatbuffers::FlatBufferBuilder &_fbb, const OperatorCodeT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateOperatorCode(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateOperatorCode(flatbuffers::FlatBufferBuilder &_fbb, const OperatorCodeT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const OperatorCodeT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _deprecated_builtin_code = _o->deprecated_builtin_code; + auto _custom_code = _o->custom_code.empty() ? 0 : _fbb.CreateString(_o->custom_code); + auto _version = _o->version; + auto _builtin_code = _o->builtin_code; + return tflite::CreateOperatorCode( + _fbb, + _deprecated_builtin_code, + _custom_code, + _version, + _builtin_code); +} + +inline OperatorT *Operator::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new OperatorT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Operator::UnPackTo(OperatorT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = opcode_index(); _o->opcode_index = _e; } + { auto _e = inputs(); if (_e) { _o->inputs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->inputs[_i] = _e->Get(_i); } } } + { auto _e = outputs(); if (_e) { _o->outputs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->outputs[_i] = _e->Get(_i); } } } + { auto _e = builtin_options_type(); _o->builtin_options.type = _e; } + { auto _e = builtin_options(); if (_e) _o->builtin_options.value = tflite::BuiltinOptionsUnion::UnPack(_e, builtin_options_type(), _resolver); } + { auto _e = custom_options(); if (_e) { _o->custom_options.resize(_e->size()); std::copy(_e->begin(), _e->end(), _o->custom_options.begin()); } } + { auto _e = custom_options_format(); _o->custom_options_format = _e; } + { auto _e = mutating_variable_inputs(); if (_e) { _o->mutating_variable_inputs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->mutating_variable_inputs[_i] = _e->Get(_i) != 0; } } } + { auto _e = intermediates(); if (_e) { _o->intermediates.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->intermediates[_i] = _e->Get(_i); } } } +} + +inline flatbuffers::Offset Operator::Pack(flatbuffers::FlatBufferBuilder &_fbb, const OperatorT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateOperator(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateOperator(flatbuffers::FlatBufferBuilder &_fbb, const OperatorT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const OperatorT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _opcode_index = _o->opcode_index; + auto _inputs = _o->inputs.size() ? _fbb.CreateVector(_o->inputs) : 0; + auto _outputs = _o->outputs.size() ? _fbb.CreateVector(_o->outputs) : 0; + auto _builtin_options_type = _o->builtin_options.type; + auto _builtin_options = _o->builtin_options.Pack(_fbb); + auto _custom_options = _o->custom_options.size() ? _fbb.CreateVector(_o->custom_options) : 0; + auto _custom_options_format = _o->custom_options_format; + auto _mutating_variable_inputs = _o->mutating_variable_inputs.size() ? _fbb.CreateVector(_o->mutating_variable_inputs) : 0; + auto _intermediates = _o->intermediates.size() ? _fbb.CreateVector(_o->intermediates) : 0; + return tflite::CreateOperator( + _fbb, + _opcode_index, + _inputs, + _outputs, + _builtin_options_type, + _builtin_options, + _custom_options, + _custom_options_format, + _mutating_variable_inputs, + _intermediates); +} + +inline SubGraphT::SubGraphT(const SubGraphT &o) + : inputs(o.inputs), + outputs(o.outputs), + name(o.name) { + tensors.reserve(o.tensors.size()); + for (const auto &tensors_ : o.tensors) { tensors.emplace_back((tensors_) ? new tflite::TensorT(*tensors_) : nullptr); } + operators.reserve(o.operators.size()); + for (const auto &operators_ : o.operators) { operators.emplace_back((operators_) ? new tflite::OperatorT(*operators_) : nullptr); } +} + +inline SubGraphT &SubGraphT::operator=(SubGraphT o) FLATBUFFERS_NOEXCEPT { + std::swap(tensors, o.tensors); + std::swap(inputs, o.inputs); + std::swap(outputs, o.outputs); + std::swap(operators, o.operators); + std::swap(name, o.name); + return *this; +} + +inline SubGraphT *SubGraph::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SubGraphT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SubGraph::UnPackTo(SubGraphT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = tensors(); if (_e) { _o->tensors.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->tensors[_i]) { _e->Get(_i)->UnPackTo(_o->tensors[_i].get(), _resolver); } else { _o->tensors[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = inputs(); if (_e) { _o->inputs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->inputs[_i] = _e->Get(_i); } } } + { auto _e = outputs(); if (_e) { _o->outputs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->outputs[_i] = _e->Get(_i); } } } + { auto _e = operators(); if (_e) { _o->operators.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->operators[_i]) { _e->Get(_i)->UnPackTo(_o->operators[_i].get(), _resolver); } else { _o->operators[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = name(); if (_e) _o->name = _e->str(); } +} + +inline flatbuffers::Offset SubGraph::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SubGraphT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSubGraph(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSubGraph(flatbuffers::FlatBufferBuilder &_fbb, const SubGraphT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SubGraphT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _tensors = _o->tensors.size() ? _fbb.CreateVector> (_o->tensors.size(), [](size_t i, _VectorArgs *__va) { return CreateTensor(*__va->__fbb, __va->__o->tensors[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _inputs = _o->inputs.size() ? _fbb.CreateVector(_o->inputs) : 0; + auto _outputs = _o->outputs.size() ? _fbb.CreateVector(_o->outputs) : 0; + auto _operators = _o->operators.size() ? _fbb.CreateVector> (_o->operators.size(), [](size_t i, _VectorArgs *__va) { return CreateOperator(*__va->__fbb, __va->__o->operators[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _name = _o->name.empty() ? 0 : _fbb.CreateString(_o->name); + return tflite::CreateSubGraph( + _fbb, + _tensors, + _inputs, + _outputs, + _operators, + _name); +} + +inline BufferT *Buffer::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new BufferT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Buffer::UnPackTo(BufferT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = data(); if (_e) { _o->data.resize(_e->size()); std::copy(_e->begin(), _e->end(), _o->data.begin()); } } +} + +inline flatbuffers::Offset Buffer::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BufferT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateBuffer(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateBuffer(flatbuffers::FlatBufferBuilder &_fbb, const BufferT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BufferT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + _fbb.ForceVectorAlignment(_o->data.size(), sizeof(uint8_t), 16); + auto _data = _o->data.size() ? _fbb.CreateVector(_o->data) : 0; + return tflite::CreateBuffer( + _fbb, + _data); +} + +inline MetadataT *Metadata::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new MetadataT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Metadata::UnPackTo(MetadataT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = name(); if (_e) _o->name = _e->str(); } + { auto _e = buffer(); _o->buffer = _e; } +} + +inline flatbuffers::Offset Metadata::Pack(flatbuffers::FlatBufferBuilder &_fbb, const MetadataT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateMetadata(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateMetadata(flatbuffers::FlatBufferBuilder &_fbb, const MetadataT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const MetadataT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _name = _o->name.empty() ? 0 : _fbb.CreateString(_o->name); + auto _buffer = _o->buffer; + return tflite::CreateMetadata( + _fbb, + _name, + _buffer); +} + +inline TensorMapT *TensorMap::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new TensorMapT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void TensorMap::UnPackTo(TensorMapT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = name(); if (_e) _o->name = _e->str(); } + { auto _e = tensor_index(); _o->tensor_index = _e; } +} + +inline flatbuffers::Offset TensorMap::Pack(flatbuffers::FlatBufferBuilder &_fbb, const TensorMapT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateTensorMap(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateTensorMap(flatbuffers::FlatBufferBuilder &_fbb, const TensorMapT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const TensorMapT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _name = _o->name.empty() ? 0 : _fbb.CreateString(_o->name); + auto _tensor_index = _o->tensor_index; + return tflite::CreateTensorMap( + _fbb, + _name, + _tensor_index); +} + +inline SignatureDefT::SignatureDefT(const SignatureDefT &o) + : signature_key(o.signature_key), + subgraph_index(o.subgraph_index) { + inputs.reserve(o.inputs.size()); + for (const auto &inputs_ : o.inputs) { inputs.emplace_back((inputs_) ? new tflite::TensorMapT(*inputs_) : nullptr); } + outputs.reserve(o.outputs.size()); + for (const auto &outputs_ : o.outputs) { outputs.emplace_back((outputs_) ? new tflite::TensorMapT(*outputs_) : nullptr); } +} + +inline SignatureDefT &SignatureDefT::operator=(SignatureDefT o) FLATBUFFERS_NOEXCEPT { + std::swap(inputs, o.inputs); + std::swap(outputs, o.outputs); + std::swap(signature_key, o.signature_key); + std::swap(subgraph_index, o.subgraph_index); + return *this; +} + +inline SignatureDefT *SignatureDef::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new SignatureDefT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void SignatureDef::UnPackTo(SignatureDefT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = inputs(); if (_e) { _o->inputs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->inputs[_i]) { _e->Get(_i)->UnPackTo(_o->inputs[_i].get(), _resolver); } else { _o->inputs[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = outputs(); if (_e) { _o->outputs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->outputs[_i]) { _e->Get(_i)->UnPackTo(_o->outputs[_i].get(), _resolver); } else { _o->outputs[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = signature_key(); if (_e) _o->signature_key = _e->str(); } + { auto _e = subgraph_index(); _o->subgraph_index = _e; } +} + +inline flatbuffers::Offset SignatureDef::Pack(flatbuffers::FlatBufferBuilder &_fbb, const SignatureDefT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateSignatureDef(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateSignatureDef(flatbuffers::FlatBufferBuilder &_fbb, const SignatureDefT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const SignatureDefT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _inputs = _o->inputs.size() ? _fbb.CreateVector> (_o->inputs.size(), [](size_t i, _VectorArgs *__va) { return CreateTensorMap(*__va->__fbb, __va->__o->inputs[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _outputs = _o->outputs.size() ? _fbb.CreateVector> (_o->outputs.size(), [](size_t i, _VectorArgs *__va) { return CreateTensorMap(*__va->__fbb, __va->__o->outputs[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _signature_key = _o->signature_key.empty() ? 0 : _fbb.CreateString(_o->signature_key); + auto _subgraph_index = _o->subgraph_index; + return tflite::CreateSignatureDef( + _fbb, + _inputs, + _outputs, + _signature_key, + _subgraph_index); +} + +inline ModelT::ModelT(const ModelT &o) + : version(o.version), + description(o.description), + metadata_buffer(o.metadata_buffer) { + operator_codes.reserve(o.operator_codes.size()); + for (const auto &operator_codes_ : o.operator_codes) { operator_codes.emplace_back((operator_codes_) ? new tflite::OperatorCodeT(*operator_codes_) : nullptr); } + subgraphs.reserve(o.subgraphs.size()); + for (const auto &subgraphs_ : o.subgraphs) { subgraphs.emplace_back((subgraphs_) ? new tflite::SubGraphT(*subgraphs_) : nullptr); } + buffers.reserve(o.buffers.size()); + for (const auto &buffers_ : o.buffers) { buffers.emplace_back((buffers_) ? new tflite::BufferT(*buffers_) : nullptr); } + metadata.reserve(o.metadata.size()); + for (const auto &metadata_ : o.metadata) { metadata.emplace_back((metadata_) ? new tflite::MetadataT(*metadata_) : nullptr); } + signature_defs.reserve(o.signature_defs.size()); + for (const auto &signature_defs_ : o.signature_defs) { signature_defs.emplace_back((signature_defs_) ? new tflite::SignatureDefT(*signature_defs_) : nullptr); } +} + +inline ModelT &ModelT::operator=(ModelT o) FLATBUFFERS_NOEXCEPT { + std::swap(version, o.version); + std::swap(operator_codes, o.operator_codes); + std::swap(subgraphs, o.subgraphs); + std::swap(description, o.description); + std::swap(buffers, o.buffers); + std::swap(metadata_buffer, o.metadata_buffer); + std::swap(metadata, o.metadata); + std::swap(signature_defs, o.signature_defs); + return *this; +} + +inline ModelT *Model::UnPack(const flatbuffers::resolver_function_t *_resolver) const { + auto _o = std::unique_ptr(new ModelT()); + UnPackTo(_o.get(), _resolver); + return _o.release(); +} + +inline void Model::UnPackTo(ModelT *_o, const flatbuffers::resolver_function_t *_resolver) const { + (void)_o; + (void)_resolver; + { auto _e = version(); _o->version = _e; } + { auto _e = operator_codes(); if (_e) { _o->operator_codes.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->operator_codes[_i]) { _e->Get(_i)->UnPackTo(_o->operator_codes[_i].get(), _resolver); } else { _o->operator_codes[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = subgraphs(); if (_e) { _o->subgraphs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->subgraphs[_i]) { _e->Get(_i)->UnPackTo(_o->subgraphs[_i].get(), _resolver); } else { _o->subgraphs[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = description(); if (_e) _o->description = _e->str(); } + { auto _e = buffers(); if (_e) { _o->buffers.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->buffers[_i]) { _e->Get(_i)->UnPackTo(_o->buffers[_i].get(), _resolver); } else { _o->buffers[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = metadata_buffer(); if (_e) { _o->metadata_buffer.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { _o->metadata_buffer[_i] = _e->Get(_i); } } } + { auto _e = metadata(); if (_e) { _o->metadata.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->metadata[_i]) { _e->Get(_i)->UnPackTo(_o->metadata[_i].get(), _resolver); } else { _o->metadata[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } + { auto _e = signature_defs(); if (_e) { _o->signature_defs.resize(_e->size()); for (flatbuffers::uoffset_t _i = 0; _i < _e->size(); _i++) { if(_o->signature_defs[_i]) { _e->Get(_i)->UnPackTo(_o->signature_defs[_i].get(), _resolver); } else { _o->signature_defs[_i] = std::unique_ptr(_e->Get(_i)->UnPack(_resolver)); }; } } } +} + +inline flatbuffers::Offset Model::Pack(flatbuffers::FlatBufferBuilder &_fbb, const ModelT* _o, const flatbuffers::rehasher_function_t *_rehasher) { + return CreateModel(_fbb, _o, _rehasher); +} + +inline flatbuffers::Offset CreateModel(flatbuffers::FlatBufferBuilder &_fbb, const ModelT *_o, const flatbuffers::rehasher_function_t *_rehasher) { + (void)_rehasher; + (void)_o; + struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const ModelT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; + auto _version = _o->version; + auto _operator_codes = _o->operator_codes.size() ? _fbb.CreateVector> (_o->operator_codes.size(), [](size_t i, _VectorArgs *__va) { return CreateOperatorCode(*__va->__fbb, __va->__o->operator_codes[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _subgraphs = _o->subgraphs.size() ? _fbb.CreateVector> (_o->subgraphs.size(), [](size_t i, _VectorArgs *__va) { return CreateSubGraph(*__va->__fbb, __va->__o->subgraphs[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _description = _o->description.empty() ? 0 : _fbb.CreateString(_o->description); + auto _buffers = _o->buffers.size() ? _fbb.CreateVector> (_o->buffers.size(), [](size_t i, _VectorArgs *__va) { return CreateBuffer(*__va->__fbb, __va->__o->buffers[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _metadata_buffer = _o->metadata_buffer.size() ? _fbb.CreateVector(_o->metadata_buffer) : 0; + auto _metadata = _o->metadata.size() ? _fbb.CreateVector> (_o->metadata.size(), [](size_t i, _VectorArgs *__va) { return CreateMetadata(*__va->__fbb, __va->__o->metadata[i].get(), __va->__rehasher); }, &_va ) : 0; + auto _signature_defs = _o->signature_defs.size() ? _fbb.CreateVector> (_o->signature_defs.size(), [](size_t i, _VectorArgs *__va) { return CreateSignatureDef(*__va->__fbb, __va->__o->signature_defs[i].get(), __va->__rehasher); }, &_va ) : 0; + return tflite::CreateModel( + _fbb, + _version, + _operator_codes, + _subgraphs, + _description, + _buffers, + _metadata_buffer, + _metadata, + _signature_defs); +} + +inline bool VerifyQuantizationDetails(flatbuffers::Verifier &verifier, const void *obj, QuantizationDetails type) { + switch (type) { + case QuantizationDetails_NONE: { + return true; + } + case QuantizationDetails_CustomQuantization: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + default: return true; + } +} + +inline bool VerifyQuantizationDetailsVector(flatbuffers::Verifier &verifier, const flatbuffers::Vector> *values, const flatbuffers::Vector *types) { + if (!values || !types) return !values && !types; + if (values->size() != types->size()) return false; + for (flatbuffers::uoffset_t i = 0; i < values->size(); ++i) { + if (!VerifyQuantizationDetails( + verifier, values->Get(i), types->GetEnum(i))) { + return false; + } + } + return true; +} + +inline void *QuantizationDetailsUnion::UnPack(const void *obj, QuantizationDetails type, const flatbuffers::resolver_function_t *resolver) { + (void)resolver; + switch (type) { + case QuantizationDetails_CustomQuantization: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + default: return nullptr; + } +} + +inline flatbuffers::Offset QuantizationDetailsUnion::Pack(flatbuffers::FlatBufferBuilder &_fbb, const flatbuffers::rehasher_function_t *_rehasher) const { + (void)_rehasher; + switch (type) { + case QuantizationDetails_CustomQuantization: { + auto ptr = reinterpret_cast(value); + return CreateCustomQuantization(_fbb, ptr, _rehasher).Union(); + } + default: return 0; + } +} + +inline QuantizationDetailsUnion::QuantizationDetailsUnion(const QuantizationDetailsUnion &u) : type(u.type), value(nullptr) { + switch (type) { + case QuantizationDetails_CustomQuantization: { + value = new tflite::CustomQuantizationT(*reinterpret_cast(u.value)); + break; + } + default: + break; + } +} + +inline void QuantizationDetailsUnion::Reset() { + switch (type) { + case QuantizationDetails_CustomQuantization: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + default: break; + } + value = nullptr; + type = QuantizationDetails_NONE; +} + +inline bool VerifySparseIndexVector(flatbuffers::Verifier &verifier, const void *obj, SparseIndexVector type) { + switch (type) { + case SparseIndexVector_NONE: { + return true; + } + case SparseIndexVector_Int32Vector: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case SparseIndexVector_Uint16Vector: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case SparseIndexVector_Uint8Vector: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + default: return true; + } +} + +inline bool VerifySparseIndexVectorVector(flatbuffers::Verifier &verifier, const flatbuffers::Vector> *values, const flatbuffers::Vector *types) { + if (!values || !types) return !values && !types; + if (values->size() != types->size()) return false; + for (flatbuffers::uoffset_t i = 0; i < values->size(); ++i) { + if (!VerifySparseIndexVector( + verifier, values->Get(i), types->GetEnum(i))) { + return false; + } + } + return true; +} + +inline void *SparseIndexVectorUnion::UnPack(const void *obj, SparseIndexVector type, const flatbuffers::resolver_function_t *resolver) { + (void)resolver; + switch (type) { + case SparseIndexVector_Int32Vector: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case SparseIndexVector_Uint16Vector: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case SparseIndexVector_Uint8Vector: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + default: return nullptr; + } +} + +inline flatbuffers::Offset SparseIndexVectorUnion::Pack(flatbuffers::FlatBufferBuilder &_fbb, const flatbuffers::rehasher_function_t *_rehasher) const { + (void)_rehasher; + switch (type) { + case SparseIndexVector_Int32Vector: { + auto ptr = reinterpret_cast(value); + return CreateInt32Vector(_fbb, ptr, _rehasher).Union(); + } + case SparseIndexVector_Uint16Vector: { + auto ptr = reinterpret_cast(value); + return CreateUint16Vector(_fbb, ptr, _rehasher).Union(); + } + case SparseIndexVector_Uint8Vector: { + auto ptr = reinterpret_cast(value); + return CreateUint8Vector(_fbb, ptr, _rehasher).Union(); + } + default: return 0; + } +} + +inline SparseIndexVectorUnion::SparseIndexVectorUnion(const SparseIndexVectorUnion &u) : type(u.type), value(nullptr) { + switch (type) { + case SparseIndexVector_Int32Vector: { + value = new tflite::Int32VectorT(*reinterpret_cast(u.value)); + break; + } + case SparseIndexVector_Uint16Vector: { + value = new tflite::Uint16VectorT(*reinterpret_cast(u.value)); + break; + } + case SparseIndexVector_Uint8Vector: { + value = new tflite::Uint8VectorT(*reinterpret_cast(u.value)); + break; + } + default: + break; + } +} + +inline void SparseIndexVectorUnion::Reset() { + switch (type) { + case SparseIndexVector_Int32Vector: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case SparseIndexVector_Uint16Vector: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case SparseIndexVector_Uint8Vector: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + default: break; + } + value = nullptr; + type = SparseIndexVector_NONE; +} + +inline bool VerifyBuiltinOptions(flatbuffers::Verifier &verifier, const void *obj, BuiltinOptions type) { + switch (type) { + case BuiltinOptions_NONE: { + return true; + } + case BuiltinOptions_Conv2DOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_DepthwiseConv2DOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ConcatEmbeddingsOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LSHProjectionOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_Pool2DOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SVDFOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_RNNOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_FullyConnectedOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SoftmaxOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ConcatenationOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_AddOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_L2NormOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LocalResponseNormalizationOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LSTMOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ResizeBilinearOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_CallOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ReshapeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SkipGramOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SpaceToDepthOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_EmbeddingLookupSparseOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_MulOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_PadOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_GatherOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_BatchToSpaceNDOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SpaceToBatchNDOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_TransposeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ReducerOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SubOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_DivOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SqueezeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SequenceRNNOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_StridedSliceOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ExpOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_TopKV2Options: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SplitOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LogSoftmaxOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_CastOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_DequantizeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_MaximumMinimumOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ArgMaxOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LessOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_NegOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_PadV2Options: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_GreaterOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_GreaterEqualOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LessEqualOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SelectOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SliceOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_TransposeConvOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SparseToDenseOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_TileOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ExpandDimsOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_EqualOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_NotEqualOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ShapeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_PowOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ArgMinOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_FakeQuantOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_PackOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LogicalOrOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_OneHotOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LogicalAndOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LogicalNotOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_UnpackOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_FloorDivOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SquareOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ZerosLikeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_FillOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_BidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_BidirectionalSequenceRNNOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_UnidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_FloorModOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_RangeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ResizeNearestNeighborOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_LeakyReluOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SquaredDifferenceOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_MirrorPadOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_AbsOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SplitVOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_UniqueOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ReverseV2Options: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_AddNOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_GatherNdOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_CosOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_WhereOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_RankOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ReverseSequenceOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_MatrixDiagOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_QuantizeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_MatrixSetDiagOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_HardSwishOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_IfOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_WhileOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_DepthToSpaceOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_NonMaxSuppressionV4Options: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_NonMaxSuppressionV5Options: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ScatterNdOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SelectV2Options: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_DensifyOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SegmentSumOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_BatchMatMulOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_CumsumOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_CallOnceOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_BroadcastToOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_Rfft2dOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_Conv3DOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_HashtableOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_HashtableFindOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_HashtableImportOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_HashtableSizeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_VarHandleOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ReadVariableOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_AssignVariableOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_RandomOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_BucketizeOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_GeluOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_DynamicUpdateSliceOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_UnsortedSegmentProdOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_UnsortedSegmentMaxOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_UnsortedSegmentMinOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_UnsortedSegmentSumOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_ATan2Options: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + case BuiltinOptions_SignOptions: { + auto ptr = reinterpret_cast(obj); + return verifier.VerifyTable(ptr); + } + default: return true; + } +} + +inline bool VerifyBuiltinOptionsVector(flatbuffers::Verifier &verifier, const flatbuffers::Vector> *values, const flatbuffers::Vector *types) { + if (!values || !types) return !values && !types; + if (values->size() != types->size()) return false; + for (flatbuffers::uoffset_t i = 0; i < values->size(); ++i) { + if (!VerifyBuiltinOptions( + verifier, values->Get(i), types->GetEnum(i))) { + return false; + } + } + return true; +} + +inline void *BuiltinOptionsUnion::UnPack(const void *obj, BuiltinOptions type, const flatbuffers::resolver_function_t *resolver) { + (void)resolver; + switch (type) { + case BuiltinOptions_Conv2DOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_DepthwiseConv2DOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ConcatEmbeddingsOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LSHProjectionOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_Pool2DOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SVDFOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_RNNOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_FullyConnectedOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SoftmaxOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ConcatenationOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_AddOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_L2NormOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LocalResponseNormalizationOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LSTMOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ResizeBilinearOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_CallOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ReshapeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SkipGramOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SpaceToDepthOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_EmbeddingLookupSparseOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_MulOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_PadOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_GatherOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_BatchToSpaceNDOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SpaceToBatchNDOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_TransposeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ReducerOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SubOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_DivOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SqueezeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SequenceRNNOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_StridedSliceOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ExpOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_TopKV2Options: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SplitOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LogSoftmaxOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_CastOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_DequantizeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_MaximumMinimumOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ArgMaxOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LessOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_NegOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_PadV2Options: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_GreaterOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_GreaterEqualOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LessEqualOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SelectOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SliceOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_TransposeConvOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SparseToDenseOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_TileOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ExpandDimsOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_EqualOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_NotEqualOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ShapeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_PowOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ArgMinOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_FakeQuantOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_PackOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LogicalOrOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_OneHotOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LogicalAndOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LogicalNotOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_UnpackOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_FloorDivOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SquareOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ZerosLikeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_FillOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_BidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_BidirectionalSequenceRNNOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_UnidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_FloorModOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_RangeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ResizeNearestNeighborOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_LeakyReluOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SquaredDifferenceOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_MirrorPadOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_AbsOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SplitVOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_UniqueOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ReverseV2Options: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_AddNOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_GatherNdOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_CosOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_WhereOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_RankOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ReverseSequenceOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_MatrixDiagOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_QuantizeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_MatrixSetDiagOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_HardSwishOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_IfOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_WhileOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_DepthToSpaceOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_NonMaxSuppressionV4Options: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_NonMaxSuppressionV5Options: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ScatterNdOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SelectV2Options: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_DensifyOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SegmentSumOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_BatchMatMulOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_CumsumOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_CallOnceOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_BroadcastToOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_Rfft2dOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_Conv3DOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_HashtableOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_HashtableFindOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_HashtableImportOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_HashtableSizeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_VarHandleOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ReadVariableOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_AssignVariableOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_RandomOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_BucketizeOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_GeluOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_DynamicUpdateSliceOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_UnsortedSegmentProdOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_UnsortedSegmentMaxOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_UnsortedSegmentMinOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_UnsortedSegmentSumOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_ATan2Options: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + case BuiltinOptions_SignOptions: { + auto ptr = reinterpret_cast(obj); + return ptr->UnPack(resolver); + } + default: return nullptr; + } +} + +inline flatbuffers::Offset BuiltinOptionsUnion::Pack(flatbuffers::FlatBufferBuilder &_fbb, const flatbuffers::rehasher_function_t *_rehasher) const { + (void)_rehasher; + switch (type) { + case BuiltinOptions_Conv2DOptions: { + auto ptr = reinterpret_cast(value); + return CreateConv2DOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_DepthwiseConv2DOptions: { + auto ptr = reinterpret_cast(value); + return CreateDepthwiseConv2DOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ConcatEmbeddingsOptions: { + auto ptr = reinterpret_cast(value); + return CreateConcatEmbeddingsOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LSHProjectionOptions: { + auto ptr = reinterpret_cast(value); + return CreateLSHProjectionOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_Pool2DOptions: { + auto ptr = reinterpret_cast(value); + return CreatePool2DOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SVDFOptions: { + auto ptr = reinterpret_cast(value); + return CreateSVDFOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_RNNOptions: { + auto ptr = reinterpret_cast(value); + return CreateRNNOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_FullyConnectedOptions: { + auto ptr = reinterpret_cast(value); + return CreateFullyConnectedOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SoftmaxOptions: { + auto ptr = reinterpret_cast(value); + return CreateSoftmaxOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ConcatenationOptions: { + auto ptr = reinterpret_cast(value); + return CreateConcatenationOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_AddOptions: { + auto ptr = reinterpret_cast(value); + return CreateAddOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_L2NormOptions: { + auto ptr = reinterpret_cast(value); + return CreateL2NormOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LocalResponseNormalizationOptions: { + auto ptr = reinterpret_cast(value); + return CreateLocalResponseNormalizationOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LSTMOptions: { + auto ptr = reinterpret_cast(value); + return CreateLSTMOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ResizeBilinearOptions: { + auto ptr = reinterpret_cast(value); + return CreateResizeBilinearOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_CallOptions: { + auto ptr = reinterpret_cast(value); + return CreateCallOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ReshapeOptions: { + auto ptr = reinterpret_cast(value); + return CreateReshapeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SkipGramOptions: { + auto ptr = reinterpret_cast(value); + return CreateSkipGramOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SpaceToDepthOptions: { + auto ptr = reinterpret_cast(value); + return CreateSpaceToDepthOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_EmbeddingLookupSparseOptions: { + auto ptr = reinterpret_cast(value); + return CreateEmbeddingLookupSparseOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_MulOptions: { + auto ptr = reinterpret_cast(value); + return CreateMulOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_PadOptions: { + auto ptr = reinterpret_cast(value); + return CreatePadOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_GatherOptions: { + auto ptr = reinterpret_cast(value); + return CreateGatherOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_BatchToSpaceNDOptions: { + auto ptr = reinterpret_cast(value); + return CreateBatchToSpaceNDOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SpaceToBatchNDOptions: { + auto ptr = reinterpret_cast(value); + return CreateSpaceToBatchNDOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_TransposeOptions: { + auto ptr = reinterpret_cast(value); + return CreateTransposeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ReducerOptions: { + auto ptr = reinterpret_cast(value); + return CreateReducerOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SubOptions: { + auto ptr = reinterpret_cast(value); + return CreateSubOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_DivOptions: { + auto ptr = reinterpret_cast(value); + return CreateDivOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SqueezeOptions: { + auto ptr = reinterpret_cast(value); + return CreateSqueezeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SequenceRNNOptions: { + auto ptr = reinterpret_cast(value); + return CreateSequenceRNNOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_StridedSliceOptions: { + auto ptr = reinterpret_cast(value); + return CreateStridedSliceOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ExpOptions: { + auto ptr = reinterpret_cast(value); + return CreateExpOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_TopKV2Options: { + auto ptr = reinterpret_cast(value); + return CreateTopKV2Options(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SplitOptions: { + auto ptr = reinterpret_cast(value); + return CreateSplitOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LogSoftmaxOptions: { + auto ptr = reinterpret_cast(value); + return CreateLogSoftmaxOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_CastOptions: { + auto ptr = reinterpret_cast(value); + return CreateCastOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_DequantizeOptions: { + auto ptr = reinterpret_cast(value); + return CreateDequantizeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_MaximumMinimumOptions: { + auto ptr = reinterpret_cast(value); + return CreateMaximumMinimumOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ArgMaxOptions: { + auto ptr = reinterpret_cast(value); + return CreateArgMaxOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LessOptions: { + auto ptr = reinterpret_cast(value); + return CreateLessOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_NegOptions: { + auto ptr = reinterpret_cast(value); + return CreateNegOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_PadV2Options: { + auto ptr = reinterpret_cast(value); + return CreatePadV2Options(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_GreaterOptions: { + auto ptr = reinterpret_cast(value); + return CreateGreaterOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_GreaterEqualOptions: { + auto ptr = reinterpret_cast(value); + return CreateGreaterEqualOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LessEqualOptions: { + auto ptr = reinterpret_cast(value); + return CreateLessEqualOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SelectOptions: { + auto ptr = reinterpret_cast(value); + return CreateSelectOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SliceOptions: { + auto ptr = reinterpret_cast(value); + return CreateSliceOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_TransposeConvOptions: { + auto ptr = reinterpret_cast(value); + return CreateTransposeConvOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SparseToDenseOptions: { + auto ptr = reinterpret_cast(value); + return CreateSparseToDenseOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_TileOptions: { + auto ptr = reinterpret_cast(value); + return CreateTileOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ExpandDimsOptions: { + auto ptr = reinterpret_cast(value); + return CreateExpandDimsOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_EqualOptions: { + auto ptr = reinterpret_cast(value); + return CreateEqualOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_NotEqualOptions: { + auto ptr = reinterpret_cast(value); + return CreateNotEqualOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ShapeOptions: { + auto ptr = reinterpret_cast(value); + return CreateShapeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_PowOptions: { + auto ptr = reinterpret_cast(value); + return CreatePowOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ArgMinOptions: { + auto ptr = reinterpret_cast(value); + return CreateArgMinOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_FakeQuantOptions: { + auto ptr = reinterpret_cast(value); + return CreateFakeQuantOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_PackOptions: { + auto ptr = reinterpret_cast(value); + return CreatePackOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LogicalOrOptions: { + auto ptr = reinterpret_cast(value); + return CreateLogicalOrOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_OneHotOptions: { + auto ptr = reinterpret_cast(value); + return CreateOneHotOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LogicalAndOptions: { + auto ptr = reinterpret_cast(value); + return CreateLogicalAndOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LogicalNotOptions: { + auto ptr = reinterpret_cast(value); + return CreateLogicalNotOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_UnpackOptions: { + auto ptr = reinterpret_cast(value); + return CreateUnpackOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_FloorDivOptions: { + auto ptr = reinterpret_cast(value); + return CreateFloorDivOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SquareOptions: { + auto ptr = reinterpret_cast(value); + return CreateSquareOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ZerosLikeOptions: { + auto ptr = reinterpret_cast(value); + return CreateZerosLikeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_FillOptions: { + auto ptr = reinterpret_cast(value); + return CreateFillOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_BidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(value); + return CreateBidirectionalSequenceLSTMOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_BidirectionalSequenceRNNOptions: { + auto ptr = reinterpret_cast(value); + return CreateBidirectionalSequenceRNNOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_UnidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(value); + return CreateUnidirectionalSequenceLSTMOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_FloorModOptions: { + auto ptr = reinterpret_cast(value); + return CreateFloorModOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_RangeOptions: { + auto ptr = reinterpret_cast(value); + return CreateRangeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ResizeNearestNeighborOptions: { + auto ptr = reinterpret_cast(value); + return CreateResizeNearestNeighborOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_LeakyReluOptions: { + auto ptr = reinterpret_cast(value); + return CreateLeakyReluOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SquaredDifferenceOptions: { + auto ptr = reinterpret_cast(value); + return CreateSquaredDifferenceOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_MirrorPadOptions: { + auto ptr = reinterpret_cast(value); + return CreateMirrorPadOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_AbsOptions: { + auto ptr = reinterpret_cast(value); + return CreateAbsOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SplitVOptions: { + auto ptr = reinterpret_cast(value); + return CreateSplitVOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_UniqueOptions: { + auto ptr = reinterpret_cast(value); + return CreateUniqueOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ReverseV2Options: { + auto ptr = reinterpret_cast(value); + return CreateReverseV2Options(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_AddNOptions: { + auto ptr = reinterpret_cast(value); + return CreateAddNOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_GatherNdOptions: { + auto ptr = reinterpret_cast(value); + return CreateGatherNdOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_CosOptions: { + auto ptr = reinterpret_cast(value); + return CreateCosOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_WhereOptions: { + auto ptr = reinterpret_cast(value); + return CreateWhereOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_RankOptions: { + auto ptr = reinterpret_cast(value); + return CreateRankOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ReverseSequenceOptions: { + auto ptr = reinterpret_cast(value); + return CreateReverseSequenceOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_MatrixDiagOptions: { + auto ptr = reinterpret_cast(value); + return CreateMatrixDiagOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_QuantizeOptions: { + auto ptr = reinterpret_cast(value); + return CreateQuantizeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_MatrixSetDiagOptions: { + auto ptr = reinterpret_cast(value); + return CreateMatrixSetDiagOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_HardSwishOptions: { + auto ptr = reinterpret_cast(value); + return CreateHardSwishOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_IfOptions: { + auto ptr = reinterpret_cast(value); + return CreateIfOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_WhileOptions: { + auto ptr = reinterpret_cast(value); + return CreateWhileOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_DepthToSpaceOptions: { + auto ptr = reinterpret_cast(value); + return CreateDepthToSpaceOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_NonMaxSuppressionV4Options: { + auto ptr = reinterpret_cast(value); + return CreateNonMaxSuppressionV4Options(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_NonMaxSuppressionV5Options: { + auto ptr = reinterpret_cast(value); + return CreateNonMaxSuppressionV5Options(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ScatterNdOptions: { + auto ptr = reinterpret_cast(value); + return CreateScatterNdOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SelectV2Options: { + auto ptr = reinterpret_cast(value); + return CreateSelectV2Options(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_DensifyOptions: { + auto ptr = reinterpret_cast(value); + return CreateDensifyOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SegmentSumOptions: { + auto ptr = reinterpret_cast(value); + return CreateSegmentSumOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_BatchMatMulOptions: { + auto ptr = reinterpret_cast(value); + return CreateBatchMatMulOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_CumsumOptions: { + auto ptr = reinterpret_cast(value); + return CreateCumsumOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_CallOnceOptions: { + auto ptr = reinterpret_cast(value); + return CreateCallOnceOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_BroadcastToOptions: { + auto ptr = reinterpret_cast(value); + return CreateBroadcastToOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_Rfft2dOptions: { + auto ptr = reinterpret_cast(value); + return CreateRfft2dOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_Conv3DOptions: { + auto ptr = reinterpret_cast(value); + return CreateConv3DOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_HashtableOptions: { + auto ptr = reinterpret_cast(value); + return CreateHashtableOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_HashtableFindOptions: { + auto ptr = reinterpret_cast(value); + return CreateHashtableFindOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_HashtableImportOptions: { + auto ptr = reinterpret_cast(value); + return CreateHashtableImportOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_HashtableSizeOptions: { + auto ptr = reinterpret_cast(value); + return CreateHashtableSizeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_VarHandleOptions: { + auto ptr = reinterpret_cast(value); + return CreateVarHandleOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ReadVariableOptions: { + auto ptr = reinterpret_cast(value); + return CreateReadVariableOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_AssignVariableOptions: { + auto ptr = reinterpret_cast(value); + return CreateAssignVariableOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_RandomOptions: { + auto ptr = reinterpret_cast(value); + return CreateRandomOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_BucketizeOptions: { + auto ptr = reinterpret_cast(value); + return CreateBucketizeOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_GeluOptions: { + auto ptr = reinterpret_cast(value); + return CreateGeluOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_DynamicUpdateSliceOptions: { + auto ptr = reinterpret_cast(value); + return CreateDynamicUpdateSliceOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_UnsortedSegmentProdOptions: { + auto ptr = reinterpret_cast(value); + return CreateUnsortedSegmentProdOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_UnsortedSegmentMaxOptions: { + auto ptr = reinterpret_cast(value); + return CreateUnsortedSegmentMaxOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_UnsortedSegmentMinOptions: { + auto ptr = reinterpret_cast(value); + return CreateUnsortedSegmentMinOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_UnsortedSegmentSumOptions: { + auto ptr = reinterpret_cast(value); + return CreateUnsortedSegmentSumOptions(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_ATan2Options: { + auto ptr = reinterpret_cast(value); + return CreateATan2Options(_fbb, ptr, _rehasher).Union(); + } + case BuiltinOptions_SignOptions: { + auto ptr = reinterpret_cast(value); + return CreateSignOptions(_fbb, ptr, _rehasher).Union(); + } + default: return 0; + } +} + +inline BuiltinOptionsUnion::BuiltinOptionsUnion(const BuiltinOptionsUnion &u) : type(u.type), value(nullptr) { + switch (type) { + case BuiltinOptions_Conv2DOptions: { + value = new tflite::Conv2DOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_DepthwiseConv2DOptions: { + value = new tflite::DepthwiseConv2DOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ConcatEmbeddingsOptions: { + value = new tflite::ConcatEmbeddingsOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LSHProjectionOptions: { + value = new tflite::LSHProjectionOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_Pool2DOptions: { + value = new tflite::Pool2DOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SVDFOptions: { + value = new tflite::SVDFOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_RNNOptions: { + value = new tflite::RNNOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_FullyConnectedOptions: { + value = new tflite::FullyConnectedOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SoftmaxOptions: { + value = new tflite::SoftmaxOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ConcatenationOptions: { + value = new tflite::ConcatenationOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_AddOptions: { + value = new tflite::AddOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_L2NormOptions: { + value = new tflite::L2NormOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LocalResponseNormalizationOptions: { + value = new tflite::LocalResponseNormalizationOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LSTMOptions: { + value = new tflite::LSTMOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ResizeBilinearOptions: { + value = new tflite::ResizeBilinearOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_CallOptions: { + value = new tflite::CallOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ReshapeOptions: { + value = new tflite::ReshapeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SkipGramOptions: { + value = new tflite::SkipGramOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SpaceToDepthOptions: { + value = new tflite::SpaceToDepthOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_EmbeddingLookupSparseOptions: { + value = new tflite::EmbeddingLookupSparseOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_MulOptions: { + value = new tflite::MulOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_PadOptions: { + value = new tflite::PadOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_GatherOptions: { + value = new tflite::GatherOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_BatchToSpaceNDOptions: { + value = new tflite::BatchToSpaceNDOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SpaceToBatchNDOptions: { + value = new tflite::SpaceToBatchNDOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_TransposeOptions: { + value = new tflite::TransposeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ReducerOptions: { + value = new tflite::ReducerOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SubOptions: { + value = new tflite::SubOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_DivOptions: { + value = new tflite::DivOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SqueezeOptions: { + value = new tflite::SqueezeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SequenceRNNOptions: { + value = new tflite::SequenceRNNOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_StridedSliceOptions: { + value = new tflite::StridedSliceOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ExpOptions: { + value = new tflite::ExpOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_TopKV2Options: { + value = new tflite::TopKV2OptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SplitOptions: { + value = new tflite::SplitOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LogSoftmaxOptions: { + value = new tflite::LogSoftmaxOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_CastOptions: { + value = new tflite::CastOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_DequantizeOptions: { + value = new tflite::DequantizeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_MaximumMinimumOptions: { + value = new tflite::MaximumMinimumOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ArgMaxOptions: { + value = new tflite::ArgMaxOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LessOptions: { + value = new tflite::LessOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_NegOptions: { + value = new tflite::NegOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_PadV2Options: { + value = new tflite::PadV2OptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_GreaterOptions: { + value = new tflite::GreaterOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_GreaterEqualOptions: { + value = new tflite::GreaterEqualOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LessEqualOptions: { + value = new tflite::LessEqualOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SelectOptions: { + value = new tflite::SelectOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SliceOptions: { + value = new tflite::SliceOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_TransposeConvOptions: { + value = new tflite::TransposeConvOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SparseToDenseOptions: { + value = new tflite::SparseToDenseOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_TileOptions: { + value = new tflite::TileOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ExpandDimsOptions: { + value = new tflite::ExpandDimsOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_EqualOptions: { + value = new tflite::EqualOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_NotEqualOptions: { + value = new tflite::NotEqualOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ShapeOptions: { + value = new tflite::ShapeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_PowOptions: { + value = new tflite::PowOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ArgMinOptions: { + value = new tflite::ArgMinOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_FakeQuantOptions: { + value = new tflite::FakeQuantOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_PackOptions: { + value = new tflite::PackOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LogicalOrOptions: { + value = new tflite::LogicalOrOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_OneHotOptions: { + value = new tflite::OneHotOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LogicalAndOptions: { + value = new tflite::LogicalAndOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LogicalNotOptions: { + value = new tflite::LogicalNotOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_UnpackOptions: { + value = new tflite::UnpackOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_FloorDivOptions: { + value = new tflite::FloorDivOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SquareOptions: { + value = new tflite::SquareOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ZerosLikeOptions: { + value = new tflite::ZerosLikeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_FillOptions: { + value = new tflite::FillOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_BidirectionalSequenceLSTMOptions: { + value = new tflite::BidirectionalSequenceLSTMOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_BidirectionalSequenceRNNOptions: { + value = new tflite::BidirectionalSequenceRNNOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_UnidirectionalSequenceLSTMOptions: { + value = new tflite::UnidirectionalSequenceLSTMOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_FloorModOptions: { + value = new tflite::FloorModOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_RangeOptions: { + value = new tflite::RangeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ResizeNearestNeighborOptions: { + value = new tflite::ResizeNearestNeighborOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_LeakyReluOptions: { + value = new tflite::LeakyReluOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SquaredDifferenceOptions: { + value = new tflite::SquaredDifferenceOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_MirrorPadOptions: { + value = new tflite::MirrorPadOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_AbsOptions: { + value = new tflite::AbsOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SplitVOptions: { + value = new tflite::SplitVOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_UniqueOptions: { + value = new tflite::UniqueOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ReverseV2Options: { + value = new tflite::ReverseV2OptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_AddNOptions: { + value = new tflite::AddNOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_GatherNdOptions: { + value = new tflite::GatherNdOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_CosOptions: { + value = new tflite::CosOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_WhereOptions: { + value = new tflite::WhereOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_RankOptions: { + value = new tflite::RankOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ReverseSequenceOptions: { + value = new tflite::ReverseSequenceOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_MatrixDiagOptions: { + value = new tflite::MatrixDiagOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_QuantizeOptions: { + value = new tflite::QuantizeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_MatrixSetDiagOptions: { + value = new tflite::MatrixSetDiagOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_HardSwishOptions: { + value = new tflite::HardSwishOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_IfOptions: { + value = new tflite::IfOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_WhileOptions: { + value = new tflite::WhileOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_DepthToSpaceOptions: { + value = new tflite::DepthToSpaceOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_NonMaxSuppressionV4Options: { + value = new tflite::NonMaxSuppressionV4OptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_NonMaxSuppressionV5Options: { + value = new tflite::NonMaxSuppressionV5OptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ScatterNdOptions: { + value = new tflite::ScatterNdOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SelectV2Options: { + value = new tflite::SelectV2OptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_DensifyOptions: { + value = new tflite::DensifyOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SegmentSumOptions: { + value = new tflite::SegmentSumOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_BatchMatMulOptions: { + value = new tflite::BatchMatMulOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_CumsumOptions: { + value = new tflite::CumsumOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_CallOnceOptions: { + value = new tflite::CallOnceOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_BroadcastToOptions: { + value = new tflite::BroadcastToOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_Rfft2dOptions: { + value = new tflite::Rfft2dOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_Conv3DOptions: { + value = new tflite::Conv3DOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_HashtableOptions: { + value = new tflite::HashtableOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_HashtableFindOptions: { + value = new tflite::HashtableFindOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_HashtableImportOptions: { + value = new tflite::HashtableImportOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_HashtableSizeOptions: { + value = new tflite::HashtableSizeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_VarHandleOptions: { + value = new tflite::VarHandleOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ReadVariableOptions: { + value = new tflite::ReadVariableOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_AssignVariableOptions: { + value = new tflite::AssignVariableOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_RandomOptions: { + value = new tflite::RandomOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_BucketizeOptions: { + value = new tflite::BucketizeOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_GeluOptions: { + value = new tflite::GeluOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_DynamicUpdateSliceOptions: { + value = new tflite::DynamicUpdateSliceOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_UnsortedSegmentProdOptions: { + value = new tflite::UnsortedSegmentProdOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_UnsortedSegmentMaxOptions: { + value = new tflite::UnsortedSegmentMaxOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_UnsortedSegmentMinOptions: { + value = new tflite::UnsortedSegmentMinOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_UnsortedSegmentSumOptions: { + value = new tflite::UnsortedSegmentSumOptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_ATan2Options: { + value = new tflite::ATan2OptionsT(*reinterpret_cast(u.value)); + break; + } + case BuiltinOptions_SignOptions: { + value = new tflite::SignOptionsT(*reinterpret_cast(u.value)); + break; + } + default: + break; + } +} + +inline void BuiltinOptionsUnion::Reset() { + switch (type) { + case BuiltinOptions_Conv2DOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_DepthwiseConv2DOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ConcatEmbeddingsOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LSHProjectionOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_Pool2DOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SVDFOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_RNNOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_FullyConnectedOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SoftmaxOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ConcatenationOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_AddOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_L2NormOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LocalResponseNormalizationOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LSTMOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ResizeBilinearOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_CallOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ReshapeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SkipGramOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SpaceToDepthOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_EmbeddingLookupSparseOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_MulOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_PadOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_GatherOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_BatchToSpaceNDOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SpaceToBatchNDOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_TransposeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ReducerOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SubOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_DivOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SqueezeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SequenceRNNOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_StridedSliceOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ExpOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_TopKV2Options: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SplitOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LogSoftmaxOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_CastOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_DequantizeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_MaximumMinimumOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ArgMaxOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LessOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_NegOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_PadV2Options: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_GreaterOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_GreaterEqualOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LessEqualOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SelectOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SliceOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_TransposeConvOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SparseToDenseOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_TileOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ExpandDimsOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_EqualOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_NotEqualOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ShapeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_PowOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ArgMinOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_FakeQuantOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_PackOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LogicalOrOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_OneHotOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LogicalAndOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LogicalNotOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_UnpackOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_FloorDivOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SquareOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ZerosLikeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_FillOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_BidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_BidirectionalSequenceRNNOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_UnidirectionalSequenceLSTMOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_FloorModOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_RangeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ResizeNearestNeighborOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_LeakyReluOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SquaredDifferenceOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_MirrorPadOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_AbsOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SplitVOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_UniqueOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ReverseV2Options: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_AddNOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_GatherNdOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_CosOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_WhereOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_RankOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ReverseSequenceOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_MatrixDiagOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_QuantizeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_MatrixSetDiagOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_HardSwishOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_IfOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_WhileOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_DepthToSpaceOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_NonMaxSuppressionV4Options: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_NonMaxSuppressionV5Options: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ScatterNdOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SelectV2Options: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_DensifyOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SegmentSumOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_BatchMatMulOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_CumsumOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_CallOnceOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_BroadcastToOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_Rfft2dOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_Conv3DOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_HashtableOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_HashtableFindOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_HashtableImportOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_HashtableSizeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_VarHandleOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ReadVariableOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_AssignVariableOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_RandomOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_BucketizeOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_GeluOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_DynamicUpdateSliceOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_UnsortedSegmentProdOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_UnsortedSegmentMaxOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_UnsortedSegmentMinOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_UnsortedSegmentSumOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_ATan2Options: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + case BuiltinOptions_SignOptions: { + auto ptr = reinterpret_cast(value); + delete ptr; + break; + } + default: break; + } + value = nullptr; + type = BuiltinOptions_NONE; +} + +inline const tflite::Model *GetModel(const void *buf) { + return flatbuffers::GetRoot(buf); +} + +inline const tflite::Model *GetSizePrefixedModel(const void *buf) { + return flatbuffers::GetSizePrefixedRoot(buf); +} + +inline const char *ModelIdentifier() { + return "TFL3"; +} + +inline bool ModelBufferHasIdentifier(const void *buf) { + return flatbuffers::BufferHasIdentifier( + buf, ModelIdentifier()); +} + +inline bool SizePrefixedModelBufferHasIdentifier(const void *buf) { + return flatbuffers::BufferHasIdentifier( + buf, ModelIdentifier(), true); +} + +inline bool VerifyModelBuffer( + flatbuffers::Verifier &verifier) { + return verifier.VerifyBuffer(ModelIdentifier()); +} + +inline bool VerifySizePrefixedModelBuffer( + flatbuffers::Verifier &verifier) { + return verifier.VerifySizePrefixedBuffer(ModelIdentifier()); +} + +inline const char *ModelExtension() { + return "tflite"; +} + +inline void FinishModelBuffer( + flatbuffers::FlatBufferBuilder &fbb, + flatbuffers::Offset root) { + fbb.Finish(root, ModelIdentifier()); +} + +inline void FinishSizePrefixedModelBuffer( + flatbuffers::FlatBufferBuilder &fbb, + flatbuffers::Offset root) { + fbb.FinishSizePrefixed(root, ModelIdentifier()); +} + +inline std::unique_ptr UnPackModel( + const void *buf, + const flatbuffers::resolver_function_t *res = nullptr) { + return std::unique_ptr(GetModel(buf)->UnPack(res)); +} + +inline std::unique_ptr UnPackSizePrefixedModel( + const void *buf, + const flatbuffers::resolver_function_t *res = nullptr) { + return std::unique_ptr(GetSizePrefixedModel(buf)->UnPack(res)); +} + +} // namespace tflite + +#endif // FLATBUFFERS_GENERATED_SCHEMA_TFLITE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h new file mode 100644 index 0000000..d810c4e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/tensorflow/lite/schema/schema_utils.h @@ -0,0 +1,33 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ +#ifndef TENSORFLOW_LITE_SCHEMA_SCHEMA_UTILS_H_ +#define TENSORFLOW_LITE_SCHEMA_SCHEMA_UTILS_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" + +namespace tflite { + +// The following methods are introduced to resolve op builtin code shortage +// problem. The new builtin operator will be assigned to the extended builtin +// code field in the flatbuffer schema. Those methods helps to hide builtin code +// details. +BuiltinOperator GetBuiltinCode(const OperatorCode *op_code); + +BuiltinOperator GetBuiltinCode(const OperatorCodeT *op_code); + +} // namespace tflite + +#endif // TENSORFLOW_LITE_SCHEMA_SCHEMA_UTILS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/LICENSE.txt b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/LICENSE.txt new file mode 100644 index 0000000..d645695 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/LICENSE.txt @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_allocator.h new file mode 100644 index 0000000..9274c98 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_allocator.h @@ -0,0 +1,68 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_ALLOCATOR_H_ +#define FLATBUFFERS_ALLOCATOR_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" + +namespace flatbuffers { + +// Allocator interface. This is flatbuffers-specific and meant only for +// `vector_downward` usage. +class Allocator { + public: + virtual ~Allocator() {} + + // Allocate `size` bytes of memory. + virtual uint8_t *allocate(size_t size) = 0; + + // Deallocate `size` bytes of memory at `p` allocated by this allocator. + virtual void deallocate(uint8_t *p, size_t size) = 0; + + // Reallocate `new_size` bytes of memory, replacing the old region of size + // `old_size` at `p`. In contrast to a normal realloc, this grows downwards, + // and is intended specifcally for `vector_downward` use. + // `in_use_back` and `in_use_front` indicate how much of `old_size` is + // actually in use at each end, and needs to be copied. + virtual uint8_t *reallocate_downward(uint8_t *old_p, size_t old_size, + size_t new_size, size_t in_use_back, + size_t in_use_front) { + FLATBUFFERS_ASSERT(new_size > old_size); // vector_downward only grows + uint8_t *new_p = allocate(new_size); + memcpy_downward(old_p, old_size, new_p, new_size, in_use_back, + in_use_front); + deallocate(old_p, old_size); + return new_p; + } + + protected: + // Called by `reallocate_downward` to copy memory from `old_p` of `old_size` + // to `new_p` of `new_size`. Only memory of size `in_use_front` and + // `in_use_back` will be copied from the front and back of the old memory + // allocation. + void memcpy_downward(uint8_t *old_p, size_t old_size, uint8_t *new_p, + size_t new_size, size_t in_use_back, + size_t in_use_front) { + memcpy(new_p + new_size - in_use_back, old_p + old_size - in_use_back, + in_use_back); + memcpy(new_p, old_p, in_use_front); + } +}; + +} // namespace flatbuffers + +#endif // FLATBUFFERS_ALLOCATOR_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_array.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_array.h new file mode 100644 index 0000000..286db9d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_array.h @@ -0,0 +1,243 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_ARRAY_H_ +#define FLATBUFFERS_ARRAY_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h" + +namespace flatbuffers { + +// This is used as a helper type for accessing arrays. +template class Array { + // Array can carry only POD data types (scalars or structs). + typedef typename flatbuffers::bool_constant::value> + scalar_tag; + typedef + typename flatbuffers::conditional::type + IndirectHelperType; + + public: + typedef uint16_t size_type; + typedef typename IndirectHelper::return_type return_type; + typedef VectorIterator const_iterator; + typedef VectorReverseIterator const_reverse_iterator; + + // If T is a LE-scalar or a struct (!scalar_tag::value). + static FLATBUFFERS_CONSTEXPR bool is_span_observable = + (scalar_tag::value && (FLATBUFFERS_LITTLEENDIAN || sizeof(T) == 1)) || + !scalar_tag::value; + + FLATBUFFERS_CONSTEXPR uint16_t size() const { return length; } + + return_type Get(uoffset_t i) const { + FLATBUFFERS_ASSERT(i < size()); + return IndirectHelper::Read(Data(), i); + } + + return_type operator[](uoffset_t i) const { return Get(i); } + + // If this is a Vector of enums, T will be its storage type, not the enum + // type. This function makes it convenient to retrieve value with enum + // type E. + template E GetEnum(uoffset_t i) const { + return static_cast(Get(i)); + } + + const_iterator begin() const { return const_iterator(Data(), 0); } + const_iterator end() const { return const_iterator(Data(), size()); } + + const_reverse_iterator rbegin() const { + return const_reverse_iterator(end()); + } + const_reverse_iterator rend() const { + return const_reverse_iterator(begin()); + } + + const_iterator cbegin() const { return begin(); } + const_iterator cend() const { return end(); } + + const_reverse_iterator crbegin() const { return rbegin(); } + const_reverse_iterator crend() const { return rend(); } + + // Get a mutable pointer to elements inside this array. + // This method used to mutate arrays of structs followed by a @p Mutate + // operation. For primitive types use @p Mutate directly. + // @warning Assignments and reads to/from the dereferenced pointer are not + // automatically converted to the correct endianness. + typename flatbuffers::conditional::type + GetMutablePointer(uoffset_t i) const { + FLATBUFFERS_ASSERT(i < size()); + return const_cast(&data()[i]); + } + + // Change elements if you have a non-const pointer to this object. + void Mutate(uoffset_t i, const T &val) { MutateImpl(scalar_tag(), i, val); } + + // The raw data in little endian format. Use with care. + const uint8_t *Data() const { return data_; } + + uint8_t *Data() { return data_; } + + // Similarly, but typed, much like std::vector::data + const T *data() const { return reinterpret_cast(Data()); } + T *data() { return reinterpret_cast(Data()); } + + // Copy data from a span with endian conversion. + // If this Array and the span overlap, the behavior is undefined. + void CopyFromSpan(flatbuffers::span src) { + const auto p1 = reinterpret_cast(src.data()); + const auto p2 = Data(); + FLATBUFFERS_ASSERT(!(p1 >= p2 && p1 < (p2 + length)) && + !(p2 >= p1 && p2 < (p1 + length))); + (void)p1; + (void)p2; + CopyFromSpanImpl(flatbuffers::bool_constant(), src); + } + + protected: + void MutateImpl(flatbuffers::true_type, uoffset_t i, const T &val) { + FLATBUFFERS_ASSERT(i < size()); + WriteScalar(data() + i, val); + } + + void MutateImpl(flatbuffers::false_type, uoffset_t i, const T &val) { + *(GetMutablePointer(i)) = val; + } + + void CopyFromSpanImpl(flatbuffers::true_type, + flatbuffers::span src) { + // Use std::memcpy() instead of std::copy() to avoid performance degradation + // due to aliasing if T is char or unsigned char. + // The size is known at compile time, so memcpy would be inlined. + std::memcpy(data(), src.data(), length * sizeof(T)); + } + + // Copy data from flatbuffers::span with endian conversion. + void CopyFromSpanImpl(flatbuffers::false_type, + flatbuffers::span src) { + for (size_type k = 0; k < length; k++) { Mutate(k, src[k]); } + } + + // This class is only used to access pre-existing data. Don't ever + // try to construct these manually. + // 'constexpr' allows us to use 'size()' at compile time. + // @note Must not use 'FLATBUFFERS_CONSTEXPR' here, as const is not allowed on + // a constructor. +#if defined(__cpp_constexpr) + constexpr Array(); +#else + Array(); +#endif + + uint8_t data_[length * sizeof(T)]; + + private: + // This class is a pointer. Copying will therefore create an invalid object. + // Private and unimplemented copy constructor. + Array(const Array &); + Array &operator=(const Array &); +}; + +// Specialization for Array[struct] with access using Offset pointer. +// This specialization used by idl_gen_text.cpp. +template class Array, length> { + static_assert(flatbuffers::is_same::value, "unexpected type T"); + + public: + typedef const void *return_type; + + const uint8_t *Data() const { return data_; } + + // Make idl_gen_text.cpp::PrintContainer happy. + return_type operator[](uoffset_t) const { + FLATBUFFERS_ASSERT(false); + return nullptr; + } + + private: + // This class is only used to access pre-existing data. + Array(); + Array(const Array &); + Array &operator=(const Array &); + + uint8_t data_[1]; +}; + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_span(Array &arr) + FLATBUFFERS_NOEXCEPT { + static_assert( + Array::is_span_observable, + "wrong type U, only plain struct, LE-scalar, or byte types are allowed"); + return span(arr.data(), N); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_span( + const Array &arr) FLATBUFFERS_NOEXCEPT { + static_assert( + Array::is_span_observable, + "wrong type U, only plain struct, LE-scalar, or byte types are allowed"); + return span(arr.data(), N); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span +make_bytes_span(Array &arr) FLATBUFFERS_NOEXCEPT { + static_assert(Array::is_span_observable, + "internal error, Array might hold only scalars or structs"); + return span(arr.Data(), sizeof(U) * N); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span +make_bytes_span(const Array &arr) FLATBUFFERS_NOEXCEPT { + static_assert(Array::is_span_observable, + "internal error, Array might hold only scalars or structs"); + return span(arr.Data(), sizeof(U) * N); +} + +// Cast a raw T[length] to a raw flatbuffers::Array +// without endian conversion. Use with care. +// TODO: move these Cast-methods to `internal` namespace. +template +Array &CastToArray(T (&arr)[length]) { + return *reinterpret_cast *>(arr); +} + +template +const Array &CastToArray(const T (&arr)[length]) { + return *reinterpret_cast *>(arr); +} + +template +Array &CastToArrayOfEnum(T (&arr)[length]) { + static_assert(sizeof(E) == sizeof(T), "invalid enum type E"); + return *reinterpret_cast *>(arr); +} + +template +const Array &CastToArrayOfEnum(const T (&arr)[length]) { + static_assert(sizeof(E) == sizeof(T), "invalid enum type E"); + return *reinterpret_cast *>(arr); +} + +} // namespace flatbuffers + +#endif // FLATBUFFERS_ARRAY_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h new file mode 100644 index 0000000..525a8e5 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h @@ -0,0 +1,496 @@ +#ifndef FLATBUFFERS_BASE_H_ +#define FLATBUFFERS_BASE_H_ + +// For TFLM, we always want FLATBUFFERS_LOCALE_INDEPENDENT to be defined as 0. +// We could achieve this by adding -DFLATBUFFERS_LOCALE_INDEPENDENT=0 to the +// TFLM Makefile. However, for (at least) the Arduino, adding additional build +// flags during the compilation can be a bit awkward. As such, we have instead +// made a decision to change the default to be FLATBUFFERS_LOCALE_INDEPENDENT=0 +// for TFLM to make it easier for external IDE integration. +#ifndef FLATBUFFERS_LOCALE_INDEPENDENT +#define FLATBUFFERS_LOCALE_INDEPENDENT 0 +#endif + +// clang-format off + +// If activate should be declared and included first. +#if defined(FLATBUFFERS_MEMORY_LEAK_TRACKING) && \ + defined(_MSC_VER) && defined(_DEBUG) + // The _CRTDBG_MAP_ALLOC inside will replace + // calloc/free (etc) to its debug version using #define directives. + #define _CRTDBG_MAP_ALLOC + #include + #include + // Replace operator new by trace-enabled version. + #define DEBUG_NEW new(_NORMAL_BLOCK, __FILE__, __LINE__) + #define new DEBUG_NEW +#endif + +#if !defined(FLATBUFFERS_ASSERT) +#include +#define FLATBUFFERS_ASSERT assert +#elif defined(FLATBUFFERS_ASSERT_INCLUDE) +// Include file with forward declaration +#include FLATBUFFERS_ASSERT_INCLUDE +#endif + +#ifndef ARDUINO +#include +#endif + +#include +#include +#include + +#if defined(ARDUINO) && !defined(ARDUINOSTL_M_H) + #include +#else + #include +#endif + +#include +#include +#include +#include +#include +#include +#include + +#if defined(__unix__) && !defined(FLATBUFFERS_LOCALE_INDEPENDENT) + #include +#endif + +#ifdef __ANDROID__ + #include +#endif + +#if defined(__ICCARM__) +#include +#endif + +// Note the __clang__ check is needed, because clang presents itself +// as an older GNUC compiler (4.2). +// Clang 3.3 and later implement all of the ISO C++ 2011 standard. +// Clang 3.4 and later implement all of the ISO C++ 2014 standard. +// http://clang.llvm.org/cxx_status.html + +// Note the MSVC value '__cplusplus' may be incorrect: +// The '__cplusplus' predefined macro in the MSVC stuck at the value 199711L, +// indicating (erroneously!) that the compiler conformed to the C++98 Standard. +// This value should be correct starting from MSVC2017-15.7-Preview-3. +// The '__cplusplus' will be valid only if MSVC2017-15.7-P3 and the `/Zc:__cplusplus` switch is set. +// Workaround (for details see MSDN): +// Use the _MSC_VER and _MSVC_LANG definition instead of the __cplusplus for compatibility. +// The _MSVC_LANG macro reports the Standard version regardless of the '/Zc:__cplusplus' switch. + +#if defined(__GNUC__) && !defined(__clang__) + #define FLATBUFFERS_GCC (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) +#else + #define FLATBUFFERS_GCC 0 +#endif + +#if defined(__clang__) + #define FLATBUFFERS_CLANG (__clang_major__ * 10000 + __clang_minor__ * 100 + __clang_patchlevel__) +#else + #define FLATBUFFERS_CLANG 0 +#endif + +/// @cond FLATBUFFERS_INTERNAL +#if __cplusplus <= 199711L && \ + (!defined(_MSC_VER) || _MSC_VER < 1600) && \ + (!defined(__GNUC__) || \ + (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ < 40400)) + #error A C++11 compatible compiler with support for the auto typing is \ + required for FlatBuffers. + #error __cplusplus _MSC_VER __GNUC__ __GNUC_MINOR__ __GNUC_PATCHLEVEL__ +#endif + +#if !defined(__clang__) && \ + defined(__GNUC__) && \ + (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ < 40600) + // Backwards compatibility for g++ 4.4, and 4.5 which don't have the nullptr + // and constexpr keywords. Note the __clang__ check is needed, because clang + // presents itself as an older GNUC compiler. + #ifndef nullptr_t + const class nullptr_t { + public: + template inline operator T*() const { return 0; } + private: + void operator&() const; + } nullptr = {}; + #endif + #ifndef constexpr + #define constexpr const + #endif +#endif + +// The wire format uses a little endian encoding (since that's efficient for +// the common platforms). +#if defined(__s390x__) + #define FLATBUFFERS_LITTLEENDIAN 0 +#endif // __s390x__ +#if !defined(FLATBUFFERS_LITTLEENDIAN) + #if defined(__GNUC__) || defined(__clang__) || defined(__ICCARM__) + #if (defined(__BIG_ENDIAN__) || \ + (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)) + #define FLATBUFFERS_LITTLEENDIAN 0 + #else + #define FLATBUFFERS_LITTLEENDIAN 1 + #endif // __BIG_ENDIAN__ + #elif defined(_MSC_VER) + #if defined(_M_PPC) + #define FLATBUFFERS_LITTLEENDIAN 0 + #else + #define FLATBUFFERS_LITTLEENDIAN 1 + #endif + #else + #error Unable to determine endianness, define FLATBUFFERS_LITTLEENDIAN. + #endif +#endif // !defined(FLATBUFFERS_LITTLEENDIAN) + +#define FLATBUFFERS_VERSION_MAJOR 2 +#define FLATBUFFERS_VERSION_MINOR 0 +#define FLATBUFFERS_VERSION_REVISION 6 +#define FLATBUFFERS_STRING_EXPAND(X) #X +#define FLATBUFFERS_STRING(X) FLATBUFFERS_STRING_EXPAND(X) +namespace flatbuffers { + // Returns version as string "MAJOR.MINOR.REVISION". + const char* FLATBUFFERS_VERSION(); +} + +#if (!defined(_MSC_VER) || _MSC_VER > 1600) && \ + (!defined(__GNUC__) || (__GNUC__ * 100 + __GNUC_MINOR__ >= 407)) || \ + defined(__clang__) + #define FLATBUFFERS_FINAL_CLASS final + #define FLATBUFFERS_OVERRIDE override + #define FLATBUFFERS_EXPLICIT_CPP11 explicit + #define FLATBUFFERS_VTABLE_UNDERLYING_TYPE : flatbuffers::voffset_t +#else + #define FLATBUFFERS_FINAL_CLASS + #define FLATBUFFERS_OVERRIDE + #define FLATBUFFERS_EXPLICIT_CPP11 + #define FLATBUFFERS_VTABLE_UNDERLYING_TYPE +#endif + +#if (!defined(_MSC_VER) || _MSC_VER >= 1900) && \ + (!defined(__GNUC__) || (__GNUC__ * 100 + __GNUC_MINOR__ >= 406)) || \ + (defined(__cpp_constexpr) && __cpp_constexpr >= 200704) + #define FLATBUFFERS_CONSTEXPR constexpr + #define FLATBUFFERS_CONSTEXPR_CPP11 constexpr + #define FLATBUFFERS_CONSTEXPR_DEFINED +#else + #define FLATBUFFERS_CONSTEXPR const + #define FLATBUFFERS_CONSTEXPR_CPP11 +#endif + +#if (defined(__cplusplus) && __cplusplus >= 201402L) || \ + (defined(__cpp_constexpr) && __cpp_constexpr >= 201304) + #define FLATBUFFERS_CONSTEXPR_CPP14 FLATBUFFERS_CONSTEXPR_CPP11 +#else + #define FLATBUFFERS_CONSTEXPR_CPP14 +#endif + +#if (defined(__GXX_EXPERIMENTAL_CXX0X__) && (__GNUC__ * 100 + __GNUC_MINOR__ >= 406)) || \ + (defined(_MSC_FULL_VER) && (_MSC_FULL_VER >= 190023026)) || \ + defined(__clang__) + #define FLATBUFFERS_NOEXCEPT noexcept +#else + #define FLATBUFFERS_NOEXCEPT +#endif + +// NOTE: the FLATBUFFERS_DELETE_FUNC macro may change the access mode to +// private, so be sure to put it at the end or reset access mode explicitly. +#if (!defined(_MSC_VER) || _MSC_FULL_VER >= 180020827) && \ + (!defined(__GNUC__) || (__GNUC__ * 100 + __GNUC_MINOR__ >= 404)) || \ + defined(__clang__) + #define FLATBUFFERS_DELETE_FUNC(func) func = delete +#else + #define FLATBUFFERS_DELETE_FUNC(func) private: func +#endif + +#if (!defined(_MSC_VER) || _MSC_VER >= 1900) && \ + (!defined(__GNUC__) || (__GNUC__ * 100 + __GNUC_MINOR__ >= 409)) || \ + defined(__clang__) + #define FLATBUFFERS_DEFAULT_DECLARATION +#endif + +// Check if we can use template aliases +// Not possible if Microsoft Compiler before 2012 +// Possible is the language feature __cpp_alias_templates is defined well +// Or possible if the C++ std is C+11 or newer +#if (defined(_MSC_VER) && _MSC_VER > 1700 /* MSVC2012 */) \ + || (defined(__cpp_alias_templates) && __cpp_alias_templates >= 200704) \ + || (defined(__cplusplus) && __cplusplus >= 201103L) + #define FLATBUFFERS_TEMPLATES_ALIASES +#endif + +#ifndef FLATBUFFERS_HAS_STRING_VIEW + // Only provide flatbuffers::string_view if __has_include can be used + // to detect a header that provides an implementation + #if defined(__has_include) + // Check for std::string_view (in c++17) + #if __has_include() && (__cplusplus >= 201606 || (defined(_HAS_CXX17) && _HAS_CXX17)) + #include + namespace flatbuffers { + typedef std::string_view string_view; + } + #define FLATBUFFERS_HAS_STRING_VIEW 1 + // Check for std::experimental::string_view (in c++14, compiler-dependent) + #elif __has_include() && (__cplusplus >= 201411) + #include + namespace flatbuffers { + typedef std::experimental::string_view string_view; + } + #define FLATBUFFERS_HAS_STRING_VIEW 1 + // Check for absl::string_view + #elif __has_include("absl/strings/string_view.h") + #include "absl/strings/string_view.h" + namespace flatbuffers { + typedef absl::string_view string_view; + } + #define FLATBUFFERS_HAS_STRING_VIEW 1 + #endif + #endif // __has_include +#endif // !FLATBUFFERS_HAS_STRING_VIEW + +#ifndef FLATBUFFERS_GENERAL_HEAP_ALLOC_OK + // Allow heap allocations to be used + #define FLATBUFFERS_GENERAL_HEAP_ALLOC_OK 1 +#endif // !FLATBUFFERS_GENERAL_HEAP_ALLOC_OK + +#ifndef FLATBUFFERS_HAS_NEW_STRTOD + // Modern (C++11) strtod and strtof functions are available for use. + // 1) nan/inf strings as argument of strtod; + // 2) hex-float as argument of strtod/strtof. + #if (defined(_MSC_VER) && _MSC_VER >= 1900) || \ + (defined(__GNUC__) && (__GNUC__ * 100 + __GNUC_MINOR__ >= 409)) || \ + (defined(__clang__)) + #define FLATBUFFERS_HAS_NEW_STRTOD 1 + #endif +#endif // !FLATBUFFERS_HAS_NEW_STRTOD + +#ifndef FLATBUFFERS_LOCALE_INDEPENDENT + // Enable locale independent functions {strtof_l, strtod_l,strtoll_l, + // strtoull_l}. + #if (defined(_MSC_VER) && _MSC_VER >= 1800) || \ + (defined(__ANDROID_API__) && __ANDROID_API__>= 21) || \ + (defined(_XOPEN_VERSION) && (_XOPEN_VERSION >= 700)) && \ + (!defined(__Fuchsia__) && !defined(__ANDROID_API__)) + #define FLATBUFFERS_LOCALE_INDEPENDENT 1 + #else + #define FLATBUFFERS_LOCALE_INDEPENDENT 0 + #endif +#endif // !FLATBUFFERS_LOCALE_INDEPENDENT + +// Suppress Undefined Behavior Sanitizer (recoverable only). Usage: +// - __supress_ubsan__("undefined") +// - __supress_ubsan__("signed-integer-overflow") +#if defined(__clang__) && (__clang_major__ > 3 || (__clang_major__ == 3 && __clang_minor__ >=7)) + #define __supress_ubsan__(type) __attribute__((no_sanitize(type))) +#elif defined(__GNUC__) && (__GNUC__ * 100 + __GNUC_MINOR__ >= 409) + #define __supress_ubsan__(type) __attribute__((no_sanitize_undefined)) +#else + #define __supress_ubsan__(type) +#endif + +// This is constexpr function used for checking compile-time constants. +// Avoid `#pragma warning(disable: 4127) // C4127: expression is constant`. +template FLATBUFFERS_CONSTEXPR inline bool IsConstTrue(T t) { + return !!t; +} + +// Enable C++ attribute [[]] if std:c++17 or higher. +#if ((__cplusplus >= 201703L) \ + || (defined(_MSVC_LANG) && (_MSVC_LANG >= 201703L))) + // All attributes unknown to an implementation are ignored without causing an error. + #define FLATBUFFERS_ATTRIBUTE(attr) attr + + #define FLATBUFFERS_FALLTHROUGH() [[fallthrough]] +#else + #define FLATBUFFERS_ATTRIBUTE(attr) + + #if FLATBUFFERS_CLANG >= 30800 + #define FLATBUFFERS_FALLTHROUGH() [[clang::fallthrough]] + #elif FLATBUFFERS_GCC >= 70300 + #define FLATBUFFERS_FALLTHROUGH() [[gnu::fallthrough]] + #else + #define FLATBUFFERS_FALLTHROUGH() + #endif +#endif + +/// @endcond + +/// @file +namespace flatbuffers { + +/// @cond FLATBUFFERS_INTERNAL +// Our default offset / size type, 32bit on purpose on 64bit systems. +// Also, using a consistent offset type maintains compatibility of serialized +// offset values between 32bit and 64bit systems. +typedef uint32_t uoffset_t; + +// Signed offsets for references that can go in both directions. +typedef int32_t soffset_t; + +// Offset/index used in v-tables, can be changed to uint8_t in +// format forks to save a bit of space if desired. +typedef uint16_t voffset_t; + +typedef uintmax_t largest_scalar_t; + +// In 32bits, this evaluates to 2GB - 1 +#define FLATBUFFERS_MAX_BUFFER_SIZE ((1ULL << (sizeof(::flatbuffers::soffset_t) * 8 - 1)) - 1) + +// The minimum size buffer that can be a valid flatbuffer. +// Includes the offset to the root table (uoffset_t), the offset to the vtable +// of the root table (soffset_t), the size of the vtable (uint16_t), and the +// size of the referring table (uint16_t). +#define FLATBUFFERS_MIN_BUFFER_SIZE sizeof(uoffset_t) + sizeof(soffset_t) + \ + sizeof(uint16_t) + sizeof(uint16_t) + +// We support aligning the contents of buffers up to this size. +#ifndef FLATBUFFERS_MAX_ALIGNMENT + #define FLATBUFFERS_MAX_ALIGNMENT 32 +#endif + +/// @brief The length of a FlatBuffer file header. +static const size_t kFileIdentifierLength = 4; + +inline bool VerifyAlignmentRequirements(size_t align, size_t min_align = 1) { + return (min_align <= align) && (align <= (FLATBUFFERS_MAX_ALIGNMENT)) && + (align & (align - 1)) == 0; // must be power of 2 +} + +#if defined(_MSC_VER) + #pragma warning(disable: 4351) // C4351: new behavior: elements of array ... will be default initialized + #pragma warning(push) + #pragma warning(disable: 4127) // C4127: conditional expression is constant +#endif + +template T EndianSwap(T t) { + #if defined(_MSC_VER) + #define FLATBUFFERS_BYTESWAP16 _byteswap_ushort + #define FLATBUFFERS_BYTESWAP32 _byteswap_ulong + #define FLATBUFFERS_BYTESWAP64 _byteswap_uint64 + #elif defined(__ICCARM__) + #define FLATBUFFERS_BYTESWAP16 __REV16 + #define FLATBUFFERS_BYTESWAP32 __REV + #define FLATBUFFERS_BYTESWAP64(x) \ + ((__REV(static_cast(x >> 32U))) | (static_cast(__REV(static_cast(x)))) << 32U) + #else + #if defined(__GNUC__) && __GNUC__ * 100 + __GNUC_MINOR__ < 408 && !defined(__clang__) + // __builtin_bswap16 was missing prior to GCC 4.8. + #define FLATBUFFERS_BYTESWAP16(x) \ + static_cast(__builtin_bswap32(static_cast(x) << 16)) + #else + #define FLATBUFFERS_BYTESWAP16 __builtin_bswap16 + #endif + #define FLATBUFFERS_BYTESWAP32 __builtin_bswap32 + #define FLATBUFFERS_BYTESWAP64 __builtin_bswap64 + #endif + if (sizeof(T) == 1) { // Compile-time if-then's. + return t; + } else if (sizeof(T) == 2) { + union { T t; uint16_t i; } u = { t }; + u.i = FLATBUFFERS_BYTESWAP16(u.i); + return u.t; + } else if (sizeof(T) == 4) { + union { T t; uint32_t i; } u = { t }; + u.i = FLATBUFFERS_BYTESWAP32(u.i); + return u.t; + } else if (sizeof(T) == 8) { + union { T t; uint64_t i; } u = { t }; + u.i = FLATBUFFERS_BYTESWAP64(u.i); + return u.t; + } else { + FLATBUFFERS_ASSERT(0); + return t; + } +} + +#if defined(_MSC_VER) + #pragma warning(pop) +#endif + + +template T EndianScalar(T t) { + #if FLATBUFFERS_LITTLEENDIAN + return t; + #else + return EndianSwap(t); + #endif +} + +template +// UBSAN: C++ aliasing type rules, see std::bit_cast<> for details. +__supress_ubsan__("alignment") +T ReadScalar(const void *p) { + return EndianScalar(*reinterpret_cast(p)); +} + +// See https://github.com/google/flatbuffers/issues/5950 + +#if (FLATBUFFERS_GCC >= 100000) && (FLATBUFFERS_GCC < 110000) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wstringop-overflow" +#endif + +template +// UBSAN: C++ aliasing type rules, see std::bit_cast<> for details. +__supress_ubsan__("alignment") +void WriteScalar(void *p, T t) { + *reinterpret_cast(p) = EndianScalar(t); +} + +template struct Offset; +template __supress_ubsan__("alignment") void WriteScalar(void *p, Offset t) { + *reinterpret_cast(p) = EndianScalar(t.o); +} + +#if (FLATBUFFERS_GCC >= 100000) && (FLATBUFFERS_GCC < 110000) + #pragma GCC diagnostic pop +#endif + +// Computes how many bytes you'd have to pad to be able to write an +// "scalar_size" scalar if the buffer had grown to "buf_size" (downwards in +// memory). +__supress_ubsan__("unsigned-integer-overflow") +inline size_t PaddingBytes(size_t buf_size, size_t scalar_size) { + return ((~buf_size) + 1) & (scalar_size - 1); +} + +// Generic 'operator==' with conditional specialisations. +// T e - new value of a scalar field. +// T def - default of scalar (is known at compile-time). +template inline bool IsTheSameAs(T e, T def) { return e == def; } + +#if defined(FLATBUFFERS_NAN_DEFAULTS) && \ + defined(FLATBUFFERS_HAS_NEW_STRTOD) && (FLATBUFFERS_HAS_NEW_STRTOD > 0) +// Like `operator==(e, def)` with weak NaN if T=(float|double). +template inline bool IsFloatTheSameAs(T e, T def) { + return (e == def) || ((def != def) && (e != e)); +} +template<> inline bool IsTheSameAs(float e, float def) { + return IsFloatTheSameAs(e, def); +} +template<> inline bool IsTheSameAs(double e, double def) { + return IsFloatTheSameAs(e, def); +} +#endif + +// Check 'v' is out of closed range [low; high]. +// Workaround for GCC warning [-Werror=type-limits]: +// comparison is always true due to limited range of data type. +template +inline bool IsOutRange(const T &v, const T &low, const T &high) { + return (v < low) || (high < v); +} + +// Check 'v' is in closed range [low; high]. +template +inline bool IsInRange(const T &v, const T &low, const T &high) { + return !IsOutRange(v, low, high); +} + +} // namespace flatbuffers +#endif // FLATBUFFERS_BASE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer.h new file mode 100644 index 0000000..fba7de2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer.h @@ -0,0 +1,142 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_BUFFER_H_ +#define FLATBUFFERS_BUFFER_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" + +namespace flatbuffers { + +// Wrapper for uoffset_t to allow safe template specialization. +// Value is allowed to be 0 to indicate a null object (see e.g. AddOffset). +template struct Offset { + uoffset_t o; + Offset() : o(0) {} + Offset(uoffset_t _o) : o(_o) {} + Offset Union() const { return Offset(o); } + bool IsNull() const { return !o; } +}; + +inline void EndianCheck() { + int endiantest = 1; + // If this fails, see FLATBUFFERS_LITTLEENDIAN above. + FLATBUFFERS_ASSERT(*reinterpret_cast(&endiantest) == + FLATBUFFERS_LITTLEENDIAN); + (void)endiantest; +} + +template FLATBUFFERS_CONSTEXPR size_t AlignOf() { + // clang-format off + #ifdef _MSC_VER + return __alignof(T); + #else + #ifndef alignof + return __alignof__(T); + #else + return alignof(T); + #endif + #endif + // clang-format on +} + +// Lexicographically compare two strings (possibly containing nulls), and +// return true if the first is less than the second. +static inline bool StringLessThan(const char *a_data, uoffset_t a_size, + const char *b_data, uoffset_t b_size) { + const auto cmp = memcmp(a_data, b_data, (std::min)(a_size, b_size)); + return cmp == 0 ? a_size < b_size : cmp < 0; +} + +// When we read serialized data from memory, in the case of most scalars, +// we want to just read T, but in the case of Offset, we want to actually +// perform the indirection and return a pointer. +// The template specialization below does just that. +// It is wrapped in a struct since function templates can't overload on the +// return type like this. +// The typedef is for the convenience of callers of this function +// (avoiding the need for a trailing return decltype) +template struct IndirectHelper { + typedef T return_type; + typedef T mutable_return_type; + static const size_t element_stride = sizeof(T); + static return_type Read(const uint8_t *p, uoffset_t i) { + return EndianScalar((reinterpret_cast(p))[i]); + } +}; +template struct IndirectHelper> { + typedef const T *return_type; + typedef T *mutable_return_type; + static const size_t element_stride = sizeof(uoffset_t); + static return_type Read(const uint8_t *p, uoffset_t i) { + p += i * sizeof(uoffset_t); + return reinterpret_cast(p + ReadScalar(p)); + } +}; +template struct IndirectHelper { + typedef const T *return_type; + typedef T *mutable_return_type; + static const size_t element_stride = sizeof(T); + static return_type Read(const uint8_t *p, uoffset_t i) { + return reinterpret_cast(p + i * sizeof(T)); + } +}; + +/// @brief Get a pointer to the the file_identifier section of the buffer. +/// @return Returns a const char pointer to the start of the file_identifier +/// characters in the buffer. The returned char * has length +/// 'flatbuffers::FlatBufferBuilder::kFileIdentifierLength'. +/// This function is UNDEFINED for FlatBuffers whose schema does not include +/// a file_identifier (likely points at padding or the start of a the root +/// vtable). +inline const char *GetBufferIdentifier(const void *buf, + bool size_prefixed = false) { + return reinterpret_cast(buf) + + ((size_prefixed) ? 2 * sizeof(uoffset_t) : sizeof(uoffset_t)); +} + +// Helper to see if the identifier in a buffer has the expected value. +inline bool BufferHasIdentifier(const void *buf, const char *identifier, + bool size_prefixed = false) { + return strncmp(GetBufferIdentifier(buf, size_prefixed), identifier, + flatbuffers::kFileIdentifierLength) == 0; +} + +/// @cond FLATBUFFERS_INTERNAL +// Helpers to get a typed pointer to the root object contained in the buffer. +template T *GetMutableRoot(void *buf) { + EndianCheck(); + return reinterpret_cast( + reinterpret_cast(buf) + + EndianScalar(*reinterpret_cast(buf))); +} + +template T *GetMutableSizePrefixedRoot(void *buf) { + return GetMutableRoot(reinterpret_cast(buf) + + sizeof(uoffset_t)); +} + +template const T *GetRoot(const void *buf) { + return GetMutableRoot(const_cast(buf)); +} + +template const T *GetSizePrefixedRoot(const void *buf) { + return GetRoot(reinterpret_cast(buf) + sizeof(uoffset_t)); +} + +} // namespace flatbuffers + +#endif // FLATBUFFERS_BUFFER_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer_ref.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer_ref.h new file mode 100644 index 0000000..56eb281 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer_ref.h @@ -0,0 +1,53 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_BUFFER_REF_H_ +#define FLATBUFFERS_BUFFER_REF_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h" + +namespace flatbuffers { + +// Convenient way to bundle a buffer and its length, to pass it around +// typed by its root. +// A BufferRef does not own its buffer. +struct BufferRefBase {}; // for std::is_base_of + +template struct BufferRef : BufferRefBase { + BufferRef() : buf(nullptr), len(0), must_free(false) {} + BufferRef(uint8_t *_buf, uoffset_t _len) + : buf(_buf), len(_len), must_free(false) {} + + ~BufferRef() { + if (must_free) free(buf); + } + + const T *GetRoot() const { return flatbuffers::GetRoot(buf); } + + bool Verify() { + Verifier verifier(buf, len); + return verifier.VerifyBuffer(nullptr); + } + + uint8_t *buf; + uoffset_t len; + bool must_free; +}; + +} // namespace flatbuffers + +#endif // FLATBUFFERS_BUFFER_REF_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_default_allocator.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_default_allocator.h new file mode 100644 index 0000000..fff5db7 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_default_allocator.h @@ -0,0 +1,58 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_DEFAULT_ALLOCATOR_H_ +#define FLATBUFFERS_DEFAULT_ALLOCATOR_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_allocator.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" + +namespace flatbuffers { + +// DefaultAllocator uses new/delete to allocate memory regions +class DefaultAllocator : public Allocator { + public: + uint8_t *allocate(size_t size) FLATBUFFERS_OVERRIDE { + return new uint8_t[size]; + } + + void deallocate(uint8_t *p, size_t) FLATBUFFERS_OVERRIDE { delete[] p; } + + static void dealloc(void *p, size_t) { delete[] static_cast(p); } +}; + +// These functions allow for a null allocator to mean use the default allocator, +// as used by DetachedBuffer and vector_downward below. +// This is to avoid having a statically or dynamically allocated default +// allocator, or having to move it between the classes that may own it. +inline uint8_t *Allocate(Allocator *allocator, size_t size) { + return allocator->allocate(size); +} + +inline void Deallocate(Allocator *allocator, uint8_t *p, size_t size) { + allocator->deallocate(p, size); +} + +inline uint8_t *ReallocateDownward(Allocator *allocator, uint8_t *old_p, + size_t old_size, size_t new_size, + size_t in_use_back, size_t in_use_front) { + return allocator->reallocate_downward(old_p, old_size, new_size, in_use_back, + in_use_front); +} + +} // namespace flatbuffers + +#endif // FLATBUFFERS_DEFAULT_ALLOCATOR_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_detached_buffer.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_detached_buffer.h new file mode 100644 index 0000000..2d8ebac --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_detached_buffer.h @@ -0,0 +1,114 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_DETACHED_BUFFER_H_ +#define FLATBUFFERS_DETACHED_BUFFER_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_allocator.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_default_allocator.h" + +namespace flatbuffers { + +// DetachedBuffer is a finished flatbuffer memory region, detached from its +// builder. The original memory region and allocator are also stored so that +// the DetachedBuffer can manage the memory lifetime. +class DetachedBuffer { + public: + DetachedBuffer() + : allocator_(nullptr), + own_allocator_(false), + buf_(nullptr), + reserved_(0), + cur_(nullptr), + size_(0) {} + + DetachedBuffer(Allocator *allocator, bool own_allocator, uint8_t *buf, + size_t reserved, uint8_t *cur, size_t sz) + : allocator_(allocator), + own_allocator_(own_allocator), + buf_(buf), + reserved_(reserved), + cur_(cur), + size_(sz) {} + + DetachedBuffer(DetachedBuffer &&other) + : allocator_(other.allocator_), + own_allocator_(other.own_allocator_), + buf_(other.buf_), + reserved_(other.reserved_), + cur_(other.cur_), + size_(other.size_) { + other.reset(); + } + + DetachedBuffer &operator=(DetachedBuffer &&other) { + if (this == &other) return *this; + + destroy(); + + allocator_ = other.allocator_; + own_allocator_ = other.own_allocator_; + buf_ = other.buf_; + reserved_ = other.reserved_; + cur_ = other.cur_; + size_ = other.size_; + + other.reset(); + + return *this; + } + + ~DetachedBuffer() { destroy(); } + + const uint8_t *data() const { return cur_; } + + uint8_t *data() { return cur_; } + + size_t size() const { return size_; } + + // These may change access mode, leave these at end of public section + FLATBUFFERS_DELETE_FUNC(DetachedBuffer(const DetachedBuffer &other)); + FLATBUFFERS_DELETE_FUNC( + DetachedBuffer &operator=(const DetachedBuffer &other)); + + protected: + Allocator *allocator_; + bool own_allocator_; + uint8_t *buf_; + size_t reserved_; + uint8_t *cur_; + size_t size_; + + inline void destroy() { + if (buf_) Deallocate(allocator_, buf_, reserved_); + if (own_allocator_ && allocator_) { delete allocator_; } + reset(); + } + + inline void reset() { + allocator_ = nullptr; + own_allocator_ = false; + buf_ = nullptr; + reserved_ = 0; + cur_ = nullptr; + size_ = 0; + } +}; + +} // namespace flatbuffers + +#endif // FLATBUFFERS_DETACHED_BUFFER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_flatbuffer_builder.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_flatbuffer_builder.h new file mode 100644 index 0000000..9aedf7b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_flatbuffer_builder.h @@ -0,0 +1,1214 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_FLATBUFFER_BUILDER_H_ +#define FLATBUFFERS_FLATBUFFER_BUILDER_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_allocator.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_array.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer_ref.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_default_allocator.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_detached_buffer.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_string.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_struct.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_table.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector_downward.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h" + +namespace flatbuffers { + +// Converts a Field ID to a virtual table offset. +inline voffset_t FieldIndexToOffset(voffset_t field_id) { + // Should correspond to what EndTable() below builds up. + const int fixed_fields = 2; // Vtable size and Object Size. + return static_cast((field_id + fixed_fields) * sizeof(voffset_t)); +} + +template> +const T *data(const std::vector &v) { + // Eventually the returned pointer gets passed down to memcpy, so + // we need it to be non-null to avoid undefined behavior. + static uint8_t t; + return v.empty() ? reinterpret_cast(&t) : &v.front(); +} +template> +T *data(std::vector &v) { + // Eventually the returned pointer gets passed down to memcpy, so + // we need it to be non-null to avoid undefined behavior. + static uint8_t t; + return v.empty() ? reinterpret_cast(&t) : &v.front(); +} + +/// @addtogroup flatbuffers_cpp_api +/// @{ +/// @class FlatBufferBuilder +/// @brief Helper class to hold data needed in creation of a FlatBuffer. +/// To serialize data, you typically call one of the `Create*()` functions in +/// the generated code, which in turn call a sequence of `StartTable`/ +/// `PushElement`/`AddElement`/`EndTable`, or the builtin `CreateString`/ +/// `CreateVector` functions. Do this is depth-first order to build up a tree to +/// the root. `Finish()` wraps up the buffer ready for transport. +class FlatBufferBuilder { + public: + /// @brief Default constructor for FlatBufferBuilder. + /// @param[in] initial_size The initial size of the buffer, in bytes. Defaults + /// to `1024`. + /// @param[in] allocator An `Allocator` to use. If null will use + /// `DefaultAllocator`. + /// @param[in] own_allocator Whether the builder/vector should own the + /// allocator. Defaults to / `false`. + /// @param[in] buffer_minalign Force the buffer to be aligned to the given + /// minimum alignment upon reallocation. Only needed if you intend to store + /// types with custom alignment AND you wish to read the buffer in-place + /// directly after creation. + explicit FlatBufferBuilder( + size_t initial_size = 1024, Allocator *allocator = nullptr, + bool own_allocator = false, + size_t buffer_minalign = AlignOf()) + : buf_(initial_size, allocator, own_allocator, buffer_minalign), + num_field_loc(0), + max_voffset_(0), + nested(false), + finished(false), + minalign_(1), + force_defaults_(false), + dedup_vtables_(true), + string_pool(nullptr) { + EndianCheck(); + } + + /// @brief Move constructor for FlatBufferBuilder. + FlatBufferBuilder(FlatBufferBuilder &&other) + : buf_(1024, nullptr, false, AlignOf()), + num_field_loc(0), + max_voffset_(0), + nested(false), + finished(false), + minalign_(1), + force_defaults_(false), + dedup_vtables_(true), + string_pool(nullptr) { + EndianCheck(); + // Default construct and swap idiom. + // Lack of delegating constructors in vs2010 makes it more verbose than + // needed. + Swap(other); + } + + /// @brief Move assignment operator for FlatBufferBuilder. + FlatBufferBuilder &operator=(FlatBufferBuilder &&other) { + // Move construct a temporary and swap idiom + FlatBufferBuilder temp(std::move(other)); + Swap(temp); + return *this; + } + + void Swap(FlatBufferBuilder &other) { + using std::swap; + buf_.swap(other.buf_); + swap(num_field_loc, other.num_field_loc); + swap(max_voffset_, other.max_voffset_); + swap(nested, other.nested); + swap(finished, other.finished); + swap(minalign_, other.minalign_); + swap(force_defaults_, other.force_defaults_); + swap(dedup_vtables_, other.dedup_vtables_); + swap(string_pool, other.string_pool); + } + + ~FlatBufferBuilder() { + if (string_pool) delete string_pool; + } + + void Reset() { + Clear(); // clear builder state + buf_.reset(); // deallocate buffer + } + + /// @brief Reset all the state in this FlatBufferBuilder so it can be reused + /// to construct another buffer. + void Clear() { + ClearOffsets(); + buf_.clear(); + nested = false; + finished = false; + minalign_ = 1; + if (string_pool) string_pool->clear(); + } + + /// @brief The current size of the serialized buffer, counting from the end. + /// @return Returns an `uoffset_t` with the current size of the buffer. + uoffset_t GetSize() const { return buf_.size(); } + + /// @brief Get the serialized buffer (after you call `Finish()`). + /// @return Returns an `uint8_t` pointer to the FlatBuffer data inside the + /// buffer. + uint8_t *GetBufferPointer() const { + Finished(); + return buf_.data(); + } + + /// @brief Get the serialized buffer (after you call `Finish()`) as a span. + /// @return Returns a constructed flatbuffers::span that is a view over the + /// FlatBuffer data inside the buffer. + flatbuffers::span GetBufferSpan() const { + Finished(); + return flatbuffers::span(buf_.data(), buf_.size()); + } + + /// @brief Get a pointer to an unfinished buffer. + /// @return Returns a `uint8_t` pointer to the unfinished buffer. + uint8_t *GetCurrentBufferPointer() const { return buf_.data(); } + + /// @brief Get the released pointer to the serialized buffer. + /// @warning Do NOT attempt to use this FlatBufferBuilder afterwards! + /// @return A `FlatBuffer` that owns the buffer and its allocator and + /// behaves similar to a `unique_ptr` with a deleter. + FLATBUFFERS_ATTRIBUTE([[deprecated("use Release() instead")]]) + DetachedBuffer ReleaseBufferPointer() { + Finished(); + return buf_.release(); + } + + /// @brief Get the released DetachedBuffer. + /// @return A `DetachedBuffer` that owns the buffer and its allocator. + DetachedBuffer Release() { + Finished(); + return buf_.release(); + } + + /// @brief Get the released pointer to the serialized buffer. + /// @param size The size of the memory block containing + /// the serialized `FlatBuffer`. + /// @param offset The offset from the released pointer where the finished + /// `FlatBuffer` starts. + /// @return A raw pointer to the start of the memory block containing + /// the serialized `FlatBuffer`. + /// @remark If the allocator is owned, it gets deleted when the destructor is + /// called.. + uint8_t *ReleaseRaw(size_t &size, size_t &offset) { + Finished(); + return buf_.release_raw(size, offset); + } + + /// @brief get the minimum alignment this buffer needs to be accessed + /// properly. This is only known once all elements have been written (after + /// you call Finish()). You can use this information if you need to embed + /// a FlatBuffer in some other buffer, such that you can later read it + /// without first having to copy it into its own buffer. + size_t GetBufferMinAlignment() const { + Finished(); + return minalign_; + } + + /// @cond FLATBUFFERS_INTERNAL + void Finished() const { + // If you get this assert, you're attempting to get access a buffer + // which hasn't been finished yet. Be sure to call + // FlatBufferBuilder::Finish with your root table. + // If you really need to access an unfinished buffer, call + // GetCurrentBufferPointer instead. + FLATBUFFERS_ASSERT(finished); + } + /// @endcond + + /// @brief In order to save space, fields that are set to their default value + /// don't get serialized into the buffer. + /// @param[in] fd When set to `true`, always serializes default values that + /// are set. Optional fields which are not set explicitly, will still not be + /// serialized. + void ForceDefaults(bool fd) { force_defaults_ = fd; } + + /// @brief By default vtables are deduped in order to save space. + /// @param[in] dedup When set to `true`, dedup vtables. + void DedupVtables(bool dedup) { dedup_vtables_ = dedup; } + + /// @cond FLATBUFFERS_INTERNAL + void Pad(size_t num_bytes) { buf_.fill(num_bytes); } + + void TrackMinAlign(size_t elem_size) { + if (elem_size > minalign_) minalign_ = elem_size; + } + + void Align(size_t elem_size) { + TrackMinAlign(elem_size); + buf_.fill(PaddingBytes(buf_.size(), elem_size)); + } + + void PushFlatBuffer(const uint8_t *bytes, size_t size) { + PushBytes(bytes, size); + finished = true; + } + + void PushBytes(const uint8_t *bytes, size_t size) { buf_.push(bytes, size); } + + void PopBytes(size_t amount) { buf_.pop(amount); } + + template void AssertScalarT() { + // The code assumes power of 2 sizes and endian-swap-ability. + static_assert(flatbuffers::is_scalar::value, "T must be a scalar type"); + } + + // Write a single aligned scalar to the buffer + template uoffset_t PushElement(T element) { + AssertScalarT(); + Align(sizeof(T)); + buf_.push_small(EndianScalar(element)); + return GetSize(); + } + + template uoffset_t PushElement(Offset off) { + // Special case for offsets: see ReferTo below. + return PushElement(ReferTo(off.o)); + } + + // When writing fields, we track where they are, so we can create correct + // vtables later. + void TrackField(voffset_t field, uoffset_t off) { + FieldLoc fl = { off, field }; + buf_.scratch_push_small(fl); + num_field_loc++; + if (field > max_voffset_) { max_voffset_ = field; } + } + + // Like PushElement, but additionally tracks the field this represents. + template void AddElement(voffset_t field, T e, T def) { + // We don't serialize values equal to the default. + if (IsTheSameAs(e, def) && !force_defaults_) return; + TrackField(field, PushElement(e)); + } + + template void AddElement(voffset_t field, T e) { + TrackField(field, PushElement(e)); + } + + template void AddOffset(voffset_t field, Offset off) { + if (off.IsNull()) return; // Don't store. + AddElement(field, ReferTo(off.o), static_cast(0)); + } + + template void AddStruct(voffset_t field, const T *structptr) { + if (!structptr) return; // Default, don't store. + Align(AlignOf()); + buf_.push_small(*structptr); + TrackField(field, GetSize()); + } + + void AddStructOffset(voffset_t field, uoffset_t off) { + TrackField(field, off); + } + + // Offsets initially are relative to the end of the buffer (downwards). + // This function converts them to be relative to the current location + // in the buffer (when stored here), pointing upwards. + uoffset_t ReferTo(uoffset_t off) { + // Align to ensure GetSize() below is correct. + Align(sizeof(uoffset_t)); + // Offset must refer to something already in buffer. + const uoffset_t size = GetSize(); + FLATBUFFERS_ASSERT(off && off <= size); + return size - off + static_cast(sizeof(uoffset_t)); + } + + void NotNested() { + // If you hit this, you're trying to construct a Table/Vector/String + // during the construction of its parent table (between the MyTableBuilder + // and table.Finish(). + // Move the creation of these sub-objects to above the MyTableBuilder to + // not get this assert. + // Ignoring this assert may appear to work in simple cases, but the reason + // it is here is that storing objects in-line may cause vtable offsets + // to not fit anymore. It also leads to vtable duplication. + FLATBUFFERS_ASSERT(!nested); + // If you hit this, fields were added outside the scope of a table. + FLATBUFFERS_ASSERT(!num_field_loc); + } + + // From generated code (or from the parser), we call StartTable/EndTable + // with a sequence of AddElement calls in between. + uoffset_t StartTable() { + NotNested(); + nested = true; + return GetSize(); + } + + // This finishes one serialized object by generating the vtable if it's a + // table, comparing it against existing vtables, and writing the + // resulting vtable offset. + uoffset_t EndTable(uoffset_t start) { + // If you get this assert, a corresponding StartTable wasn't called. + FLATBUFFERS_ASSERT(nested); + // Write the vtable offset, which is the start of any Table. + // We fill it's value later. + auto vtableoffsetloc = PushElement(0); + // Write a vtable, which consists entirely of voffset_t elements. + // It starts with the number of offsets, followed by a type id, followed + // by the offsets themselves. In reverse: + // Include space for the last offset and ensure empty tables have a + // minimum size. + max_voffset_ = + (std::max)(static_cast(max_voffset_ + sizeof(voffset_t)), + FieldIndexToOffset(0)); + buf_.fill_big(max_voffset_); + auto table_object_size = vtableoffsetloc - start; + // Vtable use 16bit offsets. + FLATBUFFERS_ASSERT(table_object_size < 0x10000); + WriteScalar(buf_.data() + sizeof(voffset_t), + static_cast(table_object_size)); + WriteScalar(buf_.data(), max_voffset_); + // Write the offsets into the table + for (auto it = buf_.scratch_end() - num_field_loc * sizeof(FieldLoc); + it < buf_.scratch_end(); it += sizeof(FieldLoc)) { + auto field_location = reinterpret_cast(it); + auto pos = static_cast(vtableoffsetloc - field_location->off); + // If this asserts, it means you've set a field twice. + FLATBUFFERS_ASSERT( + !ReadScalar(buf_.data() + field_location->id)); + WriteScalar(buf_.data() + field_location->id, pos); + } + ClearOffsets(); + auto vt1 = reinterpret_cast(buf_.data()); + auto vt1_size = ReadScalar(vt1); + auto vt_use = GetSize(); + // See if we already have generated a vtable with this exact same + // layout before. If so, make it point to the old one, remove this one. + if (dedup_vtables_) { + for (auto it = buf_.scratch_data(); it < buf_.scratch_end(); + it += sizeof(uoffset_t)) { + auto vt_offset_ptr = reinterpret_cast(it); + auto vt2 = reinterpret_cast(buf_.data_at(*vt_offset_ptr)); + auto vt2_size = ReadScalar(vt2); + if (vt1_size != vt2_size || 0 != memcmp(vt2, vt1, vt1_size)) continue; + vt_use = *vt_offset_ptr; + buf_.pop(GetSize() - vtableoffsetloc); + break; + } + } + // If this is a new vtable, remember it. + if (vt_use == GetSize()) { buf_.scratch_push_small(vt_use); } + // Fill the vtable offset we created above. + // The offset points from the beginning of the object to where the + // vtable is stored. + // Offsets default direction is downward in memory for future format + // flexibility (storing all vtables at the start of the file). + WriteScalar(buf_.data_at(vtableoffsetloc), + static_cast(vt_use) - + static_cast(vtableoffsetloc)); + + nested = false; + return vtableoffsetloc; + } + + FLATBUFFERS_ATTRIBUTE([[deprecated("call the version above instead")]]) + uoffset_t EndTable(uoffset_t start, voffset_t /*numfields*/) { + return EndTable(start); + } + + // This checks a required field has been set in a given table that has + // just been constructed. + template void Required(Offset table, voffset_t field); + + uoffset_t StartStruct(size_t alignment) { + Align(alignment); + return GetSize(); + } + + uoffset_t EndStruct() { return GetSize(); } + + void ClearOffsets() { + buf_.scratch_pop(num_field_loc * sizeof(FieldLoc)); + num_field_loc = 0; + max_voffset_ = 0; + } + + // Aligns such that when "len" bytes are written, an object can be written + // after it with "alignment" without padding. + void PreAlign(size_t len, size_t alignment) { + if (len == 0) return; + TrackMinAlign(alignment); + buf_.fill(PaddingBytes(GetSize() + len, alignment)); + } + template void PreAlign(size_t len) { + AssertScalarT(); + PreAlign(len, sizeof(T)); + } + /// @endcond + + /// @brief Store a string in the buffer, which can contain any binary data. + /// @param[in] str A const char pointer to the data to be stored as a string. + /// @param[in] len The number of bytes that should be stored from `str`. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateString(const char *str, size_t len) { + NotNested(); + PreAlign(len + 1); // Always 0-terminated. + buf_.fill(1); + PushBytes(reinterpret_cast(str), len); + PushElement(static_cast(len)); + return Offset(GetSize()); + } + + /// @brief Store a string in the buffer, which is null-terminated. + /// @param[in] str A const char pointer to a C-string to add to the buffer. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateString(const char *str) { + return CreateString(str, strlen(str)); + } + + /// @brief Store a string in the buffer, which is null-terminated. + /// @param[in] str A char pointer to a C-string to add to the buffer. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateString(char *str) { + return CreateString(str, strlen(str)); + } + + /// @brief Store a string in the buffer, which can contain any binary data. + /// @param[in] str A const reference to a std::string to store in the buffer. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateString(const std::string &str) { + return CreateString(str.c_str(), str.length()); + } + + // clang-format off + #ifdef FLATBUFFERS_HAS_STRING_VIEW + /// @brief Store a string in the buffer, which can contain any binary data. + /// @param[in] str A const string_view to copy in to the buffer. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateString(flatbuffers::string_view str) { + return CreateString(str.data(), str.size()); + } + #endif // FLATBUFFERS_HAS_STRING_VIEW + // clang-format on + + /// @brief Store a string in the buffer, which can contain any binary data. + /// @param[in] str A const pointer to a `String` struct to add to the buffer. + /// @return Returns the offset in the buffer where the string starts + Offset CreateString(const String *str) { + return str ? CreateString(str->c_str(), str->size()) : 0; + } + + /// @brief Store a string in the buffer, which can contain any binary data. + /// @param[in] str A const reference to a std::string like type with support + /// of T::c_str() and T::length() to store in the buffer. + /// @return Returns the offset in the buffer where the string starts. + template Offset CreateString(const T &str) { + return CreateString(str.c_str(), str.length()); + } + + /// @brief Store a string in the buffer, which can contain any binary data. + /// If a string with this exact contents has already been serialized before, + /// instead simply returns the offset of the existing string. This uses a map + /// stored on the heap, but only stores the numerical offsets. + /// @param[in] str A const char pointer to the data to be stored as a string. + /// @param[in] len The number of bytes that should be stored from `str`. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateSharedString(const char *str, size_t len) { + FLATBUFFERS_ASSERT(FLATBUFFERS_GENERAL_HEAP_ALLOC_OK); + if (!string_pool) + string_pool = new StringOffsetMap(StringOffsetCompare(buf_)); + auto size_before_string = buf_.size(); + // Must first serialize the string, since the set is all offsets into + // buffer. + auto off = CreateString(str, len); + auto it = string_pool->find(off); + // If it exists we reuse existing serialized data! + if (it != string_pool->end()) { + // We can remove the string we serialized. + buf_.pop(buf_.size() - size_before_string); + return *it; + } + // Record this string for future use. + string_pool->insert(off); + return off; + } + +#ifdef FLATBUFFERS_HAS_STRING_VIEW + /// @brief Store a string in the buffer, which can contain any binary data. + /// If a string with this exact contents has already been serialized before, + /// instead simply returns the offset of the existing string. This uses a map + /// stored on the heap, but only stores the numerical offsets. + /// @param[in] str A const std::string_view to store in the buffer. + /// @return Returns the offset in the buffer where the string starts + Offset CreateSharedString(const flatbuffers::string_view str) { + return CreateSharedString(str.data(), str.size()); + } +#else + /// @brief Store a string in the buffer, which null-terminated. + /// If a string with this exact contents has already been serialized before, + /// instead simply returns the offset of the existing string. This uses a map + /// stored on the heap, but only stores the numerical offsets. + /// @param[in] str A const char pointer to a C-string to add to the buffer. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateSharedString(const char *str) { + return CreateSharedString(str, strlen(str)); + } + + /// @brief Store a string in the buffer, which can contain any binary data. + /// If a string with this exact contents has already been serialized before, + /// instead simply returns the offset of the existing string. This uses a map + /// stored on the heap, but only stores the numerical offsets. + /// @param[in] str A const reference to a std::string to store in the buffer. + /// @return Returns the offset in the buffer where the string starts. + Offset CreateSharedString(const std::string &str) { + return CreateSharedString(str.c_str(), str.length()); + } +#endif + + /// @brief Store a string in the buffer, which can contain any binary data. + /// If a string with this exact contents has already been serialized before, + /// instead simply returns the offset of the existing string. This uses a map + /// stored on the heap, but only stores the numerical offsets. + /// @param[in] str A const pointer to a `String` struct to add to the buffer. + /// @return Returns the offset in the buffer where the string starts + Offset CreateSharedString(const String *str) { + return CreateSharedString(str->c_str(), str->size()); + } + + /// @cond FLATBUFFERS_INTERNAL + uoffset_t EndVector(size_t len) { + FLATBUFFERS_ASSERT(nested); // Hit if no corresponding StartVector. + nested = false; + return PushElement(static_cast(len)); + } + + void StartVector(size_t len, size_t elemsize) { + NotNested(); + nested = true; + PreAlign(len * elemsize); + PreAlign(len * elemsize, elemsize); // Just in case elemsize > uoffset_t. + } + + // Call this right before StartVector/CreateVector if you want to force the + // alignment to be something different than what the element size would + // normally dictate. + // This is useful when storing a nested_flatbuffer in a vector of bytes, + // or when storing SIMD floats, etc. + void ForceVectorAlignment(size_t len, size_t elemsize, size_t alignment) { + if (len == 0) return; + FLATBUFFERS_ASSERT(VerifyAlignmentRequirements(alignment)); + PreAlign(len * elemsize, alignment); + } + + // Similar to ForceVectorAlignment but for String fields. + void ForceStringAlignment(size_t len, size_t alignment) { + if (len == 0) return; + FLATBUFFERS_ASSERT(VerifyAlignmentRequirements(alignment)); + PreAlign((len + 1) * sizeof(char), alignment); + } + + /// @endcond + + /// @brief Serialize an array into a FlatBuffer `vector`. + /// @tparam T The data type of the array elements. + /// @param[in] v A pointer to the array of type `T` to serialize into the + /// buffer as a `vector`. + /// @param[in] len The number of elements to serialize. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template Offset> CreateVector(const T *v, size_t len) { + // If this assert hits, you're specifying a template argument that is + // causing the wrong overload to be selected, remove it. + AssertScalarT(); + StartVector(len, sizeof(T)); + if (len == 0) { return Offset>(EndVector(len)); } + // clang-format off + #if FLATBUFFERS_LITTLEENDIAN + PushBytes(reinterpret_cast(v), len * sizeof(T)); + #else + if (sizeof(T) == 1) { + PushBytes(reinterpret_cast(v), len); + } else { + for (auto i = len; i > 0; ) { + PushElement(v[--i]); + } + } + #endif + // clang-format on + return Offset>(EndVector(len)); + } + + /// @brief Serialize an array like object into a FlatBuffer `vector`. + /// @tparam T The data type of the array elements. + /// @tparam C The type of the array. + /// @param[in] array A reference to an array like object of type `T` to + /// serialize into the buffer as a `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template Offset> CreateVector(const C &array) { + return CreateVector(array.data(), array.size()); + } + + /// @brief Serialize an initializer list into a FlatBuffer `vector`. + /// @tparam T The data type of the initializer list elements. + /// @param[in] v The value of the initializer list. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVector(std::initializer_list v) { + return CreateVector(v.begin(), v.size()); + } + + template + Offset>> CreateVector(const Offset *v, size_t len) { + StartVector(len, sizeof(Offset)); + for (auto i = len; i > 0;) { PushElement(v[--i]); } + return Offset>>(EndVector(len)); + } + + /// @brief Serialize a `std::vector` into a FlatBuffer `vector`. + /// @tparam T The data type of the `std::vector` elements. + /// @param v A const reference to the `std::vector` to serialize into the + /// buffer as a `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset> CreateVector(const std::vector &v) { + return CreateVector(data(v), v.size()); + } + + // vector may be implemented using a bit-set, so we can't access it as + // an array. Instead, read elements manually. + // Background: https://isocpp.org/blog/2012/11/on-vectorbool + Offset> CreateVector(const std::vector &v) { + StartVector(v.size(), sizeof(uint8_t)); + for (auto i = v.size(); i > 0;) { + PushElement(static_cast(v[--i])); + } + return Offset>(EndVector(v.size())); + } + + /// @brief Serialize values returned by a function into a FlatBuffer `vector`. + /// This is a convenience function that takes care of iteration for you. + /// @tparam T The data type of the `std::vector` elements. + /// @param f A function that takes the current iteration 0..vector_size-1 and + /// returns any type that you can construct a FlatBuffers vector out of. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVector(size_t vector_size, + const std::function &f) { + FLATBUFFERS_ASSERT(FLATBUFFERS_GENERAL_HEAP_ALLOC_OK); + std::vector elems(vector_size); + for (size_t i = 0; i < vector_size; i++) elems[i] = f(i); + return CreateVector(elems); + } + + /// @brief Serialize values returned by a function into a FlatBuffer `vector`. + /// This is a convenience function that takes care of iteration for you. This + /// uses a vector stored on the heap to store the intermediate results of the + /// iteration. + /// @tparam T The data type of the `std::vector` elements. + /// @param f A function that takes the current iteration 0..vector_size-1, + /// and the state parameter returning any type that you can construct a + /// FlatBuffers vector out of. + /// @param state State passed to f. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVector(size_t vector_size, F f, S *state) { + FLATBUFFERS_ASSERT(FLATBUFFERS_GENERAL_HEAP_ALLOC_OK); + std::vector elems(vector_size); + for (size_t i = 0; i < vector_size; i++) elems[i] = f(i, state); + return CreateVector(elems); + } + + /// @brief Serialize a `std::vector` into a FlatBuffer `vector`. + /// whereas StringType is any type that is accepted by the CreateString() + /// overloads. + /// This is a convenience function for a common case. + /// @param v A const reference to the `std::vector` to serialize into the + /// buffer as a `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset>> CreateVectorOfStrings( + const std::vector &v) { + return CreateVectorOfStrings(v.cbegin(), v.cend()); + } + + /// @brief Serialize a collection of Strings into a FlatBuffer `vector`. + /// This is a convenience function for a common case. + /// @param begin The begining iterator of the collection + /// @param end The ending iterator of the collection + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset>> CreateVectorOfStrings(It begin, It end) { + auto size = std::distance(begin, end); + auto scratch_buffer_usage = size * sizeof(Offset); + // If there is not enough space to store the offsets, there definitely won't + // be enough space to store all the strings. So ensuring space for the + // scratch region is OK, for it it fails, it would have failed later. + buf_.ensure_space(scratch_buffer_usage); + for (auto it = begin; it != end; ++it) { + buf_.scratch_push_small(CreateString(*it)); + } + StartVector(size, sizeof(Offset)); + for (auto i = 1; i <= size; i++) { + // Note we re-evaluate the buf location each iteration to account for any + // underlying buffer resizing that may occur. + PushElement(*reinterpret_cast *>( + buf_.scratch_end() - i * sizeof(Offset))); + } + buf_.scratch_pop(scratch_buffer_usage); + return Offset>>(EndVector(size)); + } + + /// @brief Serialize an array of structs into a FlatBuffer `vector`. + /// @tparam T The data type of the struct array elements. + /// @param[in] v A pointer to the array of type `T` to serialize into the + /// buffer as a `vector`. + /// @param[in] len The number of elements to serialize. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVectorOfStructs(const T *v, size_t len) { + StartVector(len * sizeof(T) / AlignOf(), AlignOf()); + if (len > 0) { + PushBytes(reinterpret_cast(v), sizeof(T) * len); + } + return Offset>(EndVector(len)); + } + + /// @brief Serialize an array of native structs into a FlatBuffer `vector`. + /// @tparam T The data type of the struct array elements. + /// @tparam S The data type of the native struct array elements. + /// @param[in] v A pointer to the array of type `S` to serialize into the + /// buffer as a `vector`. + /// @param[in] len The number of elements to serialize. + /// @param[in] pack_func Pointer to a function to convert the native struct + /// to the FlatBuffer struct. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVectorOfNativeStructs( + const S *v, size_t len, T (*const pack_func)(const S &)) { + FLATBUFFERS_ASSERT(pack_func); + auto structs = StartVectorOfStructs(len); + for (size_t i = 0; i < len; i++) { structs[i] = pack_func(v[i]); } + return EndVectorOfStructs(len); + } + + /// @brief Serialize an array of native structs into a FlatBuffer `vector`. + /// @tparam T The data type of the struct array elements. + /// @tparam S The data type of the native struct array elements. + /// @param[in] v A pointer to the array of type `S` to serialize into the + /// buffer as a `vector`. + /// @param[in] len The number of elements to serialize. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVectorOfNativeStructs(const S *v, + size_t len) { + extern T Pack(const S &); + return CreateVectorOfNativeStructs(v, len, Pack); + } + + /// @brief Serialize an array of structs into a FlatBuffer `vector`. + /// @tparam T The data type of the struct array elements. + /// @param[in] filler A function that takes the current iteration + /// 0..vector_size-1 and a pointer to the struct that must be filled. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + /// This is mostly useful when flatbuffers are generated with mutation + /// accessors. + template + Offset> CreateVectorOfStructs( + size_t vector_size, const std::function &filler) { + T *structs = StartVectorOfStructs(vector_size); + for (size_t i = 0; i < vector_size; i++) { + filler(i, structs); + structs++; + } + return EndVectorOfStructs(vector_size); + } + + /// @brief Serialize an array of structs into a FlatBuffer `vector`. + /// @tparam T The data type of the struct array elements. + /// @param[in] f A function that takes the current iteration 0..vector_size-1, + /// a pointer to the struct that must be filled and the state argument. + /// @param[in] state Arbitrary state to pass to f. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + /// This is mostly useful when flatbuffers are generated with mutation + /// accessors. + template + Offset> CreateVectorOfStructs(size_t vector_size, F f, + S *state) { + T *structs = StartVectorOfStructs(vector_size); + for (size_t i = 0; i < vector_size; i++) { + f(i, structs, state); + structs++; + } + return EndVectorOfStructs(vector_size); + } + + /// @brief Serialize a `std::vector` of structs into a FlatBuffer `vector`. + /// @tparam T The data type of the `std::vector` struct elements. + /// @param[in] v A const reference to the `std::vector` of structs to + /// serialize into the buffer as a `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset> CreateVectorOfStructs( + const std::vector &v) { + return CreateVectorOfStructs(data(v), v.size()); + } + + /// @brief Serialize a `std::vector` of native structs into a FlatBuffer + /// `vector`. + /// @tparam T The data type of the `std::vector` struct elements. + /// @tparam S The data type of the `std::vector` native struct elements. + /// @param[in] v A const reference to the `std::vector` of structs to + /// serialize into the buffer as a `vector`. + /// @param[in] pack_func Pointer to a function to convert the native struct + /// to the FlatBuffer struct. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset> CreateVectorOfNativeStructs( + const std::vector &v, T (*const pack_func)(const S &)) { + return CreateVectorOfNativeStructs(data(v), v.size(), pack_func); + } + + /// @brief Serialize a `std::vector` of native structs into a FlatBuffer + /// `vector`. + /// @tparam T The data type of the `std::vector` struct elements. + /// @tparam S The data type of the `std::vector` native struct elements. + /// @param[in] v A const reference to the `std::vector` of structs to + /// serialize into the buffer as a `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset> CreateVectorOfNativeStructs( + const std::vector &v) { + return CreateVectorOfNativeStructs(data(v), v.size()); + } + + /// @cond FLATBUFFERS_INTERNAL + template struct StructKeyComparator { + bool operator()(const T &a, const T &b) const { + return a.KeyCompareLessThan(&b); + } + }; + /// @endcond + + /// @brief Serialize a `std::vector` of structs into a FlatBuffer `vector` + /// in sorted order. + /// @tparam T The data type of the `std::vector` struct elements. + /// @param[in] v A const reference to the `std::vector` of structs to + /// serialize into the buffer as a `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset> CreateVectorOfSortedStructs( + std::vector *v) { + return CreateVectorOfSortedStructs(data(*v), v->size()); + } + + /// @brief Serialize a `std::vector` of native structs into a FlatBuffer + /// `vector` in sorted order. + /// @tparam T The data type of the `std::vector` struct elements. + /// @tparam S The data type of the `std::vector` native struct elements. + /// @param[in] v A const reference to the `std::vector` of structs to + /// serialize into the buffer as a `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset> CreateVectorOfSortedNativeStructs( + std::vector *v) { + return CreateVectorOfSortedNativeStructs(data(*v), v->size()); + } + + /// @brief Serialize an array of structs into a FlatBuffer `vector` in sorted + /// order. + /// @tparam T The data type of the struct array elements. + /// @param[in] v A pointer to the array of type `T` to serialize into the + /// buffer as a `vector`. + /// @param[in] len The number of elements to serialize. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVectorOfSortedStructs(T *v, size_t len) { + std::stable_sort(v, v + len, StructKeyComparator()); + return CreateVectorOfStructs(v, len); + } + + /// @brief Serialize an array of native structs into a FlatBuffer `vector` in + /// sorted order. + /// @tparam T The data type of the struct array elements. + /// @tparam S The data type of the native struct array elements. + /// @param[in] v A pointer to the array of type `S` to serialize into the + /// buffer as a `vector`. + /// @param[in] len The number of elements to serialize. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset> CreateVectorOfSortedNativeStructs(S *v, + size_t len) { + extern T Pack(const S &); + auto structs = StartVectorOfStructs(len); + for (size_t i = 0; i < len; i++) { structs[i] = Pack(v[i]); } + std::stable_sort(structs, structs + len, StructKeyComparator()); + return EndVectorOfStructs(len); + } + + /// @cond FLATBUFFERS_INTERNAL + template struct TableKeyComparator { + TableKeyComparator(vector_downward &buf) : buf_(buf) {} + TableKeyComparator(const TableKeyComparator &other) : buf_(other.buf_) {} + bool operator()(const Offset &a, const Offset &b) const { + auto table_a = reinterpret_cast(buf_.data_at(a.o)); + auto table_b = reinterpret_cast(buf_.data_at(b.o)); + return table_a->KeyCompareLessThan(table_b); + } + vector_downward &buf_; + + private: + FLATBUFFERS_DELETE_FUNC( + TableKeyComparator &operator=(const TableKeyComparator &other)); + }; + /// @endcond + + /// @brief Serialize an array of `table` offsets as a `vector` in the buffer + /// in sorted order. + /// @tparam T The data type that the offset refers to. + /// @param[in] v An array of type `Offset` that contains the `table` + /// offsets to store in the buffer in sorted order. + /// @param[in] len The number of elements to store in the `vector`. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template + Offset>> CreateVectorOfSortedTables(Offset *v, + size_t len) { + std::stable_sort(v, v + len, TableKeyComparator(buf_)); + return CreateVector(v, len); + } + + /// @brief Serialize an array of `table` offsets as a `vector` in the buffer + /// in sorted order. + /// @tparam T The data type that the offset refers to. + /// @param[in] v An array of type `Offset` that contains the `table` + /// offsets to store in the buffer in sorted order. + /// @return Returns a typed `Offset` into the serialized data indicating + /// where the vector is stored. + template> + Offset>> CreateVectorOfSortedTables( + std::vector, Alloc> *v) { + return CreateVectorOfSortedTables(data(*v), v->size()); + } + + /// @brief Specialized version of `CreateVector` for non-copying use cases. + /// Write the data any time later to the returned buffer pointer `buf`. + /// @param[in] len The number of elements to store in the `vector`. + /// @param[in] elemsize The size of each element in the `vector`. + /// @param[out] buf A pointer to a `uint8_t` pointer that can be + /// written to at a later time to serialize the data into a `vector` + /// in the buffer. + uoffset_t CreateUninitializedVector(size_t len, size_t elemsize, + uint8_t **buf) { + NotNested(); + StartVector(len, elemsize); + buf_.make_space(len * elemsize); + auto vec_start = GetSize(); + auto vec_end = EndVector(len); + *buf = buf_.data_at(vec_start); + return vec_end; + } + + /// @brief Specialized version of `CreateVector` for non-copying use cases. + /// Write the data any time later to the returned buffer pointer `buf`. + /// @tparam T The data type of the data that will be stored in the buffer + /// as a `vector`. + /// @param[in] len The number of elements to store in the `vector`. + /// @param[out] buf A pointer to a pointer of type `T` that can be + /// written to at a later time to serialize the data into a `vector` + /// in the buffer. + template + Offset> CreateUninitializedVector(size_t len, T **buf) { + AssertScalarT(); + return CreateUninitializedVector(len, sizeof(T), + reinterpret_cast(buf)); + } + + template + Offset> CreateUninitializedVectorOfStructs(size_t len, + T **buf) { + return CreateUninitializedVector(len, sizeof(T), + reinterpret_cast(buf)); + } + + // @brief Create a vector of scalar type T given as input a vector of scalar + // type U, useful with e.g. pre "enum class" enums, or any existing scalar + // data of the wrong type. + template + Offset> CreateVectorScalarCast(const U *v, size_t len) { + AssertScalarT(); + AssertScalarT(); + StartVector(len, sizeof(T)); + for (auto i = len; i > 0;) { PushElement(static_cast(v[--i])); } + return Offset>(EndVector(len)); + } + + /// @brief Write a struct by itself, typically to be part of a union. + template Offset CreateStruct(const T &structobj) { + NotNested(); + Align(AlignOf()); + buf_.push_small(structobj); + return Offset(GetSize()); + } + + /// @brief Finish serializing a buffer by writing the root offset. + /// @param[in] file_identifier If a `file_identifier` is given, the buffer + /// will be prefixed with a standard FlatBuffers file header. + template + void Finish(Offset root, const char *file_identifier = nullptr) { + Finish(root.o, file_identifier, false); + } + + /// @brief Finish a buffer with a 32 bit size field pre-fixed (size of the + /// buffer following the size field). These buffers are NOT compatible + /// with standard buffers created by Finish, i.e. you can't call GetRoot + /// on them, you have to use GetSizePrefixedRoot instead. + /// All >32 bit quantities in this buffer will be aligned when the whole + /// size pre-fixed buffer is aligned. + /// These kinds of buffers are useful for creating a stream of FlatBuffers. + template + void FinishSizePrefixed(Offset root, + const char *file_identifier = nullptr) { + Finish(root.o, file_identifier, true); + } + + void SwapBufAllocator(FlatBufferBuilder &other) { + buf_.swap_allocator(other.buf_); + } + + /// @brief The length of a FlatBuffer file header. + static const size_t kFileIdentifierLength = + ::flatbuffers::kFileIdentifierLength; + + protected: + // You shouldn't really be copying instances of this class. + FlatBufferBuilder(const FlatBufferBuilder &); + FlatBufferBuilder &operator=(const FlatBufferBuilder &); + + void Finish(uoffset_t root, const char *file_identifier, bool size_prefix) { + NotNested(); + buf_.clear_scratch(); + // This will cause the whole buffer to be aligned. + PreAlign((size_prefix ? sizeof(uoffset_t) : 0) + sizeof(uoffset_t) + + (file_identifier ? kFileIdentifierLength : 0), + minalign_); + if (file_identifier) { + FLATBUFFERS_ASSERT(strlen(file_identifier) == kFileIdentifierLength); + PushBytes(reinterpret_cast(file_identifier), + kFileIdentifierLength); + } + PushElement(ReferTo(root)); // Location of root. + if (size_prefix) { PushElement(GetSize()); } + finished = true; + } + + struct FieldLoc { + uoffset_t off; + voffset_t id; + }; + + vector_downward buf_; + + // Accumulating offsets of table members while it is being built. + // We store these in the scratch pad of buf_, after the vtable offsets. + uoffset_t num_field_loc; + // Track how much of the vtable is in use, so we can output the most compact + // possible vtable. + voffset_t max_voffset_; + + // Ensure objects are not nested. + bool nested; + + // Ensure the buffer is finished before it is being accessed. + bool finished; + + size_t minalign_; + + bool force_defaults_; // Serialize values equal to their defaults anyway. + + bool dedup_vtables_; + + struct StringOffsetCompare { + StringOffsetCompare(const vector_downward &buf) : buf_(&buf) {} + bool operator()(const Offset &a, const Offset &b) const { + auto stra = reinterpret_cast(buf_->data_at(a.o)); + auto strb = reinterpret_cast(buf_->data_at(b.o)); + return StringLessThan(stra->data(), stra->size(), strb->data(), + strb->size()); + } + const vector_downward *buf_; + }; + + // For use with CreateSharedString. Instantiated on first use only. + typedef std::set, StringOffsetCompare> StringOffsetMap; + StringOffsetMap *string_pool; + + private: + // Allocates space for a vector of structures. + // Must be completed with EndVectorOfStructs(). + template T *StartVectorOfStructs(size_t vector_size) { + StartVector(vector_size * sizeof(T) / AlignOf(), AlignOf()); + return reinterpret_cast(buf_.make_space(vector_size * sizeof(T))); + } + + // End the vector of structures in the flatbuffers. + // Vector should have previously be started with StartVectorOfStructs(). + template + Offset> EndVectorOfStructs(size_t vector_size) { + return Offset>(EndVector(vector_size)); + } +}; +/// @} + +/// Helpers to get a typed pointer to objects that are currently being built. +/// @warning Creating new objects will lead to reallocations and invalidates +/// the pointer! +template +T *GetMutableTemporaryPointer(FlatBufferBuilder &fbb, Offset offset) { + return reinterpret_cast(fbb.GetCurrentBufferPointer() + fbb.GetSize() - + offset.o); +} + +template +const T *GetTemporaryPointer(FlatBufferBuilder &fbb, Offset offset) { + return GetMutableTemporaryPointer(fbb, offset); +} + +template +void FlatBufferBuilder::Required(Offset table, voffset_t field) { + auto table_ptr = reinterpret_cast(buf_.data_at(table.o)); + bool ok = table_ptr->GetOptionalFieldOffset(field) != 0; + // If this fails, the caller will show what field needs to be set. + FLATBUFFERS_ASSERT(ok); + (void)ok; +} + +} // namespace flatbuffers + +#endif // FLATBUFFERS_VECTOR_DOWNWARD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h new file mode 100644 index 0000000..7166d4f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h @@ -0,0 +1,509 @@ +/* + * Copyright 2017 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_STL_EMULATION_H_ +#define FLATBUFFERS_STL_EMULATION_H_ + +// clang-format off +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" + +#include +#include +#include +#include +#include + +#ifndef FLATBUFFERS_USE_STD_OPTIONAL + // Detect C++17 compatible compiler. + // __cplusplus >= 201703L - a compiler has support of 'static inline' variables. + #if (defined(__cplusplus) && __cplusplus >= 201703L) \ + || (defined(_MSVC_LANG) && _MSVC_LANG >= 201703L) + #define FLATBUFFERS_USE_STD_OPTIONAL 1 + #else + #define FLATBUFFERS_USE_STD_OPTIONAL 0 + #endif // (defined(__cplusplus) && __cplusplus >= 201703L) ... +#endif // FLATBUFFERS_USE_STD_OPTIONAL + +#if FLATBUFFERS_USE_STD_OPTIONAL + #include +#endif + +// The __cpp_lib_span is the predefined feature macro. +#if defined(FLATBUFFERS_USE_STD_SPAN) + #include +#elif defined(__cpp_lib_span) && defined(__has_include) + #if __has_include() + #include + #define FLATBUFFERS_USE_STD_SPAN + #endif +#else + // Disable non-trivial ctors if FLATBUFFERS_SPAN_MINIMAL defined. + #if !defined(FLATBUFFERS_TEMPLATES_ALIASES) + #define FLATBUFFERS_SPAN_MINIMAL + #else + // Enable implicit construction of a span from a std::array. + #include + #endif +#endif // defined(FLATBUFFERS_USE_STD_SPAN) + +// This header provides backwards compatibility for older versions of the STL. +namespace flatbuffers { + +#if defined(FLATBUFFERS_TEMPLATES_ALIASES) + template + using numeric_limits = std::numeric_limits; +#else + template class numeric_limits : + public std::numeric_limits {}; +#endif // defined(FLATBUFFERS_TEMPLATES_ALIASES) + +#if defined(FLATBUFFERS_TEMPLATES_ALIASES) + template using is_scalar = std::is_scalar; + template using is_same = std::is_same; + template using is_floating_point = std::is_floating_point; + template using is_unsigned = std::is_unsigned; + template using is_enum = std::is_enum; + template using make_unsigned = std::make_unsigned; + template + using conditional = std::conditional; + template + using integral_constant = std::integral_constant; + template + using bool_constant = integral_constant; + using true_type = std::true_type; + using false_type = std::false_type; +#else + // MSVC 2010 doesn't support C++11 aliases. + template struct is_scalar : public std::is_scalar {}; + template struct is_same : public std::is_same {}; + template struct is_floating_point : + public std::is_floating_point {}; + template struct is_unsigned : public std::is_unsigned {}; + template struct is_enum : public std::is_enum {}; + template struct make_unsigned : public std::make_unsigned {}; + template + struct conditional : public std::conditional {}; + template + struct integral_constant : public std::integral_constant {}; + template + struct bool_constant : public integral_constant {}; + typedef bool_constant true_type; + typedef bool_constant false_type; +#endif // defined(FLATBUFFERS_TEMPLATES_ALIASES) + +#if defined(FLATBUFFERS_TEMPLATES_ALIASES) + template using unique_ptr = std::unique_ptr; +#else + // MSVC 2010 doesn't support C++11 aliases. + // We're manually "aliasing" the class here as we want to bring unique_ptr + // into the flatbuffers namespace. We have unique_ptr in the flatbuffers + // namespace we have a completely independent implementation (see below) + // for C++98 STL implementations. + template class unique_ptr : public std::unique_ptr { + public: + unique_ptr() {} + explicit unique_ptr(T* p) : std::unique_ptr(p) {} + unique_ptr(std::unique_ptr&& u) { *this = std::move(u); } + unique_ptr(unique_ptr&& u) { *this = std::move(u); } + unique_ptr& operator=(std::unique_ptr&& u) { + std::unique_ptr::reset(u.release()); + return *this; + } + unique_ptr& operator=(unique_ptr&& u) { + std::unique_ptr::reset(u.release()); + return *this; + } + unique_ptr& operator=(T* p) { + return std::unique_ptr::operator=(p); + } + }; +#endif // defined(FLATBUFFERS_TEMPLATES_ALIASES) + +#if FLATBUFFERS_USE_STD_OPTIONAL +template +using Optional = std::optional; +using nullopt_t = std::nullopt_t; +inline constexpr nullopt_t nullopt = std::nullopt; + +#else +// Limited implementation of Optional type for a scalar T. +// This implementation limited by trivial types compatible with +// std::is_arithmetic or std::is_enum type traits. + +// A tag to indicate an empty flatbuffers::optional. +struct nullopt_t { + explicit FLATBUFFERS_CONSTEXPR_CPP11 nullopt_t(int) {} +}; + +#if defined(FLATBUFFERS_CONSTEXPR_DEFINED) + namespace internal { + template struct nullopt_holder { + static constexpr nullopt_t instance_ = nullopt_t(0); + }; + template + constexpr nullopt_t nullopt_holder::instance_; + } + static constexpr const nullopt_t &nullopt = internal::nullopt_holder::instance_; + +#else + namespace internal { + template struct nullopt_holder { + static const nullopt_t instance_; + }; + template + const nullopt_t nullopt_holder::instance_ = nullopt_t(0); + } + static const nullopt_t &nullopt = internal::nullopt_holder::instance_; + +#endif + +template +class Optional FLATBUFFERS_FINAL_CLASS { + // Non-scalar 'T' would extremely complicated Optional. + // Use is_scalar checking because flatbuffers flatbuffers::is_arithmetic + // isn't implemented. + static_assert(flatbuffers::is_scalar::value, "unexpected type T"); + + public: + ~Optional() {} + + FLATBUFFERS_CONSTEXPR_CPP11 Optional() FLATBUFFERS_NOEXCEPT + : value_(), has_value_(false) {} + + FLATBUFFERS_CONSTEXPR_CPP11 Optional(nullopt_t) FLATBUFFERS_NOEXCEPT + : value_(), has_value_(false) {} + + FLATBUFFERS_CONSTEXPR_CPP11 Optional(T val) FLATBUFFERS_NOEXCEPT + : value_(val), has_value_(true) {} + + FLATBUFFERS_CONSTEXPR_CPP11 Optional(const Optional &other) FLATBUFFERS_NOEXCEPT + : value_(other.value_), has_value_(other.has_value_) {} + + FLATBUFFERS_CONSTEXPR_CPP14 Optional &operator=(const Optional &other) FLATBUFFERS_NOEXCEPT { + value_ = other.value_; + has_value_ = other.has_value_; + return *this; + } + + FLATBUFFERS_CONSTEXPR_CPP14 Optional &operator=(nullopt_t) FLATBUFFERS_NOEXCEPT { + value_ = T(); + has_value_ = false; + return *this; + } + + FLATBUFFERS_CONSTEXPR_CPP14 Optional &operator=(T val) FLATBUFFERS_NOEXCEPT { + value_ = val; + has_value_ = true; + return *this; + } + + void reset() FLATBUFFERS_NOEXCEPT { + *this = nullopt; + } + + void swap(Optional &other) FLATBUFFERS_NOEXCEPT { + std::swap(value_, other.value_); + std::swap(has_value_, other.has_value_); + } + + FLATBUFFERS_CONSTEXPR_CPP11 FLATBUFFERS_EXPLICIT_CPP11 operator bool() const FLATBUFFERS_NOEXCEPT { + return has_value_; + } + + FLATBUFFERS_CONSTEXPR_CPP11 bool has_value() const FLATBUFFERS_NOEXCEPT { + return has_value_; + } + + FLATBUFFERS_CONSTEXPR_CPP11 const T& operator*() const FLATBUFFERS_NOEXCEPT { + return value_; + } + + const T& value() const { + FLATBUFFERS_ASSERT(has_value()); + return value_; + } + + T value_or(T default_value) const FLATBUFFERS_NOEXCEPT { + return has_value() ? value_ : default_value; + } + + private: + T value_; + bool has_value_; +}; + +template +FLATBUFFERS_CONSTEXPR_CPP11 bool operator==(const Optional& opt, nullopt_t) FLATBUFFERS_NOEXCEPT { + return !opt; +} +template +FLATBUFFERS_CONSTEXPR_CPP11 bool operator==(nullopt_t, const Optional& opt) FLATBUFFERS_NOEXCEPT { + return !opt; +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 bool operator==(const Optional& lhs, const U& rhs) FLATBUFFERS_NOEXCEPT { + return static_cast(lhs) && (*lhs == rhs); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 bool operator==(const T& lhs, const Optional& rhs) FLATBUFFERS_NOEXCEPT { + return static_cast(rhs) && (lhs == *rhs); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 bool operator==(const Optional& lhs, const Optional& rhs) FLATBUFFERS_NOEXCEPT { + return static_cast(lhs) != static_cast(rhs) + ? false + : !static_cast(lhs) ? false : (*lhs == *rhs); +} +#endif // FLATBUFFERS_USE_STD_OPTIONAL + + +// Very limited and naive partial implementation of C++20 std::span. +#if defined(FLATBUFFERS_USE_STD_SPAN) + inline constexpr std::size_t dynamic_extent = std::dynamic_extent; + template + using span = std::span; + +#else // !defined(FLATBUFFERS_USE_STD_SPAN) +FLATBUFFERS_CONSTEXPR std::size_t dynamic_extent = static_cast(-1); + +// Exclude this code if MSVC2010 or non-STL Android is active. +// The non-STL Android doesn't have `std::is_convertible` required for SFINAE. +#if !defined(FLATBUFFERS_SPAN_MINIMAL) +namespace internal { + // This is SFINAE helper class for checking of a common condition: + // > This overload only participates in overload resolution + // > Check whether a pointer to an array of From can be converted + // > to a pointer to an array of To. + // This helper is used for checking of 'From -> const From'. + template + struct is_span_convertable { + using type = + typename std::conditional::value + && (Extent == dynamic_extent || N == Extent), + int, void>::type; + }; + + template + struct SpanIterator { + // TODO: upgrade to std::random_access_iterator_tag. + using iterator_category = std::forward_iterator_tag; + using difference_type = std::ptrdiff_t; + using value_type = typename std::remove_cv::type; + using reference = T&; + using pointer = T*; + + // Convince MSVC compiler that this iterator is trusted (it is verified). + #ifdef _MSC_VER + using _Unchecked_type = pointer; + #endif // _MSC_VER + + SpanIterator(pointer ptr) : ptr_(ptr) {} + reference operator*() const { return *ptr_; } + pointer operator->() { return ptr_; } + SpanIterator& operator++() { ptr_++; return *this; } + SpanIterator operator++(int) { auto tmp = *this; ++(*this); return tmp; } + + friend bool operator== (const SpanIterator& lhs, const SpanIterator& rhs) { return lhs.ptr_ == rhs.ptr_; } + friend bool operator!= (const SpanIterator& lhs, const SpanIterator& rhs) { return lhs.ptr_ != rhs.ptr_; } + + private: + pointer ptr_; + }; +} // namespace internal +#endif // !defined(FLATBUFFERS_SPAN_MINIMAL) + +// T - element type; must be a complete type that is not an abstract +// class type. +// Extent - the number of elements in the sequence, or dynamic. +template +class span FLATBUFFERS_FINAL_CLASS { + public: + typedef T element_type; + typedef T& reference; + typedef const T& const_reference; + typedef T* pointer; + typedef const T* const_pointer; + typedef std::size_t size_type; + + static FLATBUFFERS_CONSTEXPR size_type extent = Extent; + + // Returns the number of elements in the span. + FLATBUFFERS_CONSTEXPR_CPP11 size_type size() const FLATBUFFERS_NOEXCEPT { + return count_; + } + + // Returns the size of the sequence in bytes. + FLATBUFFERS_CONSTEXPR_CPP11 + size_type size_bytes() const FLATBUFFERS_NOEXCEPT { + return size() * sizeof(element_type); + } + + // Checks if the span is empty. + FLATBUFFERS_CONSTEXPR_CPP11 bool empty() const FLATBUFFERS_NOEXCEPT { + return size() == 0; + } + + // Returns a pointer to the beginning of the sequence. + FLATBUFFERS_CONSTEXPR_CPP11 pointer data() const FLATBUFFERS_NOEXCEPT { + return data_; + } + + #if !defined(FLATBUFFERS_SPAN_MINIMAL) + using Iterator = internal::SpanIterator; + + Iterator begin() const { return Iterator(data()); } + Iterator end() const { return Iterator(data() + size()); } + #endif + + // Returns a reference to the idx-th element of the sequence. + // The behavior is undefined if the idx is greater than or equal to size(). + FLATBUFFERS_CONSTEXPR_CPP11 reference operator[](size_type idx) const { + return data()[idx]; + } + + FLATBUFFERS_CONSTEXPR_CPP11 span(const span &other) FLATBUFFERS_NOEXCEPT + : data_(other.data_), count_(other.count_) {} + + FLATBUFFERS_CONSTEXPR_CPP14 span &operator=(const span &other) + FLATBUFFERS_NOEXCEPT { + data_ = other.data_; + count_ = other.count_; + } + + // Limited implementation of + // `template constexpr std::span(It first, size_type count);`. + // + // Constructs a span that is a view over the range [first, first + count); + // the resulting span has: data() == first and size() == count. + // The behavior is undefined if [first, first + count) is not a valid range, + // or if (extent != flatbuffers::dynamic_extent && count != extent). + FLATBUFFERS_CONSTEXPR_CPP11 + explicit span(pointer first, size_type count) FLATBUFFERS_NOEXCEPT + : data_ (Extent == dynamic_extent ? first : (Extent == count ? first : nullptr)), + count_(Extent == dynamic_extent ? count : (Extent == count ? Extent : 0)) { + // Make span empty if the count argument is incompatible with span. + } + + // Exclude this code if MSVC2010 is active. The MSVC2010 isn't C++11 + // compliant, it doesn't support default template arguments for functions. + #if defined(FLATBUFFERS_SPAN_MINIMAL) + FLATBUFFERS_CONSTEXPR_CPP11 span() FLATBUFFERS_NOEXCEPT : data_(nullptr), + count_(0) { + static_assert(extent == 0 || extent == dynamic_extent, "invalid span"); + } + + #else + // Constructs an empty span whose data() == nullptr and size() == 0. + // This overload only participates in overload resolution if + // extent == 0 || extent == flatbuffers::dynamic_extent. + // A dummy template argument N is need dependency for SFINAE. + template::type = 0> + FLATBUFFERS_CONSTEXPR_CPP11 span() FLATBUFFERS_NOEXCEPT : data_(nullptr), + count_(0) { + static_assert(extent == 0 || extent == dynamic_extent, "invalid span"); + } + + // Constructs a span that is a view over the array arr; the resulting span + // has size() == N and data() == std::data(arr). These overloads only + // participate in overload resolution if + // extent == std::dynamic_extent || N == extent is true and + // std::remove_pointer_t(*)[] + // is convertible to element_type (*)[]. + template::type = 0> + FLATBUFFERS_CONSTEXPR_CPP11 span(element_type (&arr)[N]) FLATBUFFERS_NOEXCEPT + : data_(arr), count_(N) {} + + template::type = 0> + FLATBUFFERS_CONSTEXPR_CPP11 span(std::array &arr) FLATBUFFERS_NOEXCEPT + : data_(arr.data()), count_(N) {} + + //template + //FLATBUFFERS_CONSTEXPR_CPP11 span(std::array &arr) FLATBUFFERS_NOEXCEPT + // : data_(arr.data()), count_(N) {} + + template::type = 0> + FLATBUFFERS_CONSTEXPR_CPP11 span(const std::array &arr) FLATBUFFERS_NOEXCEPT + : data_(arr.data()), count_(N) {} + + // Converting constructor from another span s; + // the resulting span has size() == s.size() and data() == s.data(). + // This overload only participates in overload resolution + // if extent == std::dynamic_extent || N == extent is true and U (*)[] + // is convertible to element_type (*)[]. + template::type = 0> + FLATBUFFERS_CONSTEXPR_CPP11 span(const flatbuffers::span &s) FLATBUFFERS_NOEXCEPT + : span(s.data(), s.size()) { + } + + #endif // !defined(FLATBUFFERS_SPAN_MINIMAL) + + private: + // This is a naive implementation with 'count_' member even if (Extent != dynamic_extent). + pointer const data_; + size_type count_; +}; +#endif // defined(FLATBUFFERS_USE_STD_SPAN) + +#if !defined(FLATBUFFERS_SPAN_MINIMAL) +template +FLATBUFFERS_CONSTEXPR_CPP11 +flatbuffers::span make_span(ElementType(&arr)[Extent]) FLATBUFFERS_NOEXCEPT { + return span(arr); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 +flatbuffers::span make_span(const ElementType(&arr)[Extent]) FLATBUFFERS_NOEXCEPT { + return span(arr); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 +flatbuffers::span make_span(std::array &arr) FLATBUFFERS_NOEXCEPT { + return span(arr); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 +flatbuffers::span make_span(const std::array &arr) FLATBUFFERS_NOEXCEPT { + return span(arr); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 +flatbuffers::span make_span(ElementType *first, std::size_t count) FLATBUFFERS_NOEXCEPT { + return span(first, count); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 +flatbuffers::span make_span(const ElementType *first, std::size_t count) FLATBUFFERS_NOEXCEPT { + return span(first, count); +} +#endif // !defined(FLATBUFFERS_SPAN_MINIMAL) + +} // namespace flatbuffers + +#endif // FLATBUFFERS_STL_EMULATION_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_string.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_string.h new file mode 100644 index 0000000..45cecf2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_string.h @@ -0,0 +1,64 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_STRING_H_ +#define FLATBUFFERS_STRING_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h" + +namespace flatbuffers { + +struct String : public Vector { + const char *c_str() const { return reinterpret_cast(Data()); } + std::string str() const { return std::string(c_str(), size()); } + + // clang-format off + #ifdef FLATBUFFERS_HAS_STRING_VIEW + flatbuffers::string_view string_view() const { + return flatbuffers::string_view(c_str(), size()); + } + #endif // FLATBUFFERS_HAS_STRING_VIEW + // clang-format on + + bool operator<(const String &o) const { + return StringLessThan(this->data(), this->size(), o.data(), o.size()); + } +}; + +// Convenience function to get std::string from a String returning an empty +// string on null pointer. +static inline std::string GetString(const String *str) { + return str ? str->str() : ""; +} + +// Convenience function to get char* from a String returning an empty string on +// null pointer. +static inline const char *GetCstring(const String *str) { + return str ? str->c_str() : ""; +} + +#ifdef FLATBUFFERS_HAS_STRING_VIEW +// Convenience function to get string_view from a String returning an empty +// string_view on null pointer. +static inline flatbuffers::string_view GetStringView(const String *str) { + return str ? str->string_view() : flatbuffers::string_view(); +} +#endif // FLATBUFFERS_HAS_STRING_VIEW + +} // namespace flatbuffers + +#endif // FLATBUFFERS_STRING_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_struct.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_struct.h new file mode 100644 index 0000000..385d648 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_struct.h @@ -0,0 +1,53 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_STRUCT_H_ +#define FLATBUFFERS_STRUCT_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" + +namespace flatbuffers { + +// "structs" are flat structures that do not have an offset table, thus +// always have all members present and do not support forwards/backwards +// compatible extensions. + +class Struct FLATBUFFERS_FINAL_CLASS { + public: + template T GetField(uoffset_t o) const { + return ReadScalar(&data_[o]); + } + + template T GetStruct(uoffset_t o) const { + return reinterpret_cast(&data_[o]); + } + + const uint8_t *GetAddressOf(uoffset_t o) const { return &data_[o]; } + uint8_t *GetAddressOf(uoffset_t o) { return &data_[o]; } + + private: + // private constructor & copy constructor: you obtain instances of this + // class by pointing to existing data only + Struct(); + Struct(const Struct &); + Struct &operator=(const Struct &); + + uint8_t data_[1]; +}; + +} // namespace flatbuffers + +#endif // FLATBUFFERS_STRUCT_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_table.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_table.h new file mode 100644 index 0000000..3aca63f --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_table.h @@ -0,0 +1,168 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_TABLE_H_ +#define FLATBUFFERS_TABLE_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h" + +namespace flatbuffers { + +// "tables" use an offset table (possibly shared) that allows fields to be +// omitted and added at will, but uses an extra indirection to read. +class Table { + public: + const uint8_t *GetVTable() const { + return data_ - ReadScalar(data_); + } + + // This gets the field offset for any of the functions below it, or 0 + // if the field was not present. + voffset_t GetOptionalFieldOffset(voffset_t field) const { + // The vtable offset is always at the start. + auto vtable = GetVTable(); + // The first element is the size of the vtable (fields + type id + itself). + auto vtsize = ReadScalar(vtable); + // If the field we're accessing is outside the vtable, we're reading older + // data, so it's the same as if the offset was 0 (not present). + return field < vtsize ? ReadScalar(vtable + field) : 0; + } + + template T GetField(voffset_t field, T defaultval) const { + auto field_offset = GetOptionalFieldOffset(field); + return field_offset ? ReadScalar(data_ + field_offset) : defaultval; + } + + template P GetPointer(voffset_t field) { + auto field_offset = GetOptionalFieldOffset(field); + auto p = data_ + field_offset; + return field_offset ? reinterpret_cast

(p + ReadScalar(p)) + : nullptr; + } + template P GetPointer(voffset_t field) const { + return const_cast(this)->GetPointer

(field); + } + + template P GetStruct(voffset_t field) const { + auto field_offset = GetOptionalFieldOffset(field); + auto p = const_cast(data_ + field_offset); + return field_offset ? reinterpret_cast

(p) : nullptr; + } + + template + flatbuffers::Optional GetOptional(voffset_t field) const { + auto field_offset = GetOptionalFieldOffset(field); + auto p = data_ + field_offset; + return field_offset ? Optional(static_cast(ReadScalar(p))) + : Optional(); + } + + template bool SetField(voffset_t field, T val, T def) { + auto field_offset = GetOptionalFieldOffset(field); + if (!field_offset) return IsTheSameAs(val, def); + WriteScalar(data_ + field_offset, val); + return true; + } + template bool SetField(voffset_t field, T val) { + auto field_offset = GetOptionalFieldOffset(field); + if (!field_offset) return false; + WriteScalar(data_ + field_offset, val); + return true; + } + + bool SetPointer(voffset_t field, const uint8_t *val) { + auto field_offset = GetOptionalFieldOffset(field); + if (!field_offset) return false; + WriteScalar(data_ + field_offset, + static_cast(val - (data_ + field_offset))); + return true; + } + + uint8_t *GetAddressOf(voffset_t field) { + auto field_offset = GetOptionalFieldOffset(field); + return field_offset ? data_ + field_offset : nullptr; + } + const uint8_t *GetAddressOf(voffset_t field) const { + return const_cast

(this)->GetAddressOf(field); + } + + bool CheckField(voffset_t field) const { + return GetOptionalFieldOffset(field) != 0; + } + + // Verify the vtable of this table. + // Call this once per table, followed by VerifyField once per field. + bool VerifyTableStart(Verifier &verifier) const { + return verifier.VerifyTableStart(data_); + } + + // Verify a particular field. + template + bool VerifyField(const Verifier &verifier, voffset_t field, + size_t align) const { + // Calling GetOptionalFieldOffset should be safe now thanks to + // VerifyTable(). + auto field_offset = GetOptionalFieldOffset(field); + // Check the actual field. + return !field_offset || verifier.VerifyField(data_, field_offset, align); + } + + // VerifyField for required fields. + template + bool VerifyFieldRequired(const Verifier &verifier, voffset_t field, + size_t align) const { + auto field_offset = GetOptionalFieldOffset(field); + return verifier.Check(field_offset != 0) && + verifier.VerifyField(data_, field_offset, align); + } + + // Versions for offsets. + bool VerifyOffset(const Verifier &verifier, voffset_t field) const { + auto field_offset = GetOptionalFieldOffset(field); + return !field_offset || verifier.VerifyOffset(data_, field_offset); + } + + bool VerifyOffsetRequired(const Verifier &verifier, voffset_t field) const { + auto field_offset = GetOptionalFieldOffset(field); + return verifier.Check(field_offset != 0) && + verifier.VerifyOffset(data_, field_offset); + } + + private: + // private constructor & copy constructor: you obtain instances of this + // class by pointing to existing data only + Table(); + Table(const Table &other); + Table &operator=(const Table &); + + uint8_t data_[1]; +}; + +// This specialization allows avoiding warnings like: +// MSVC C4800: type: forcing value to bool 'true' or 'false'. +template<> +inline flatbuffers::Optional Table::GetOptional( + voffset_t field) const { + auto field_offset = GetOptionalFieldOffset(field); + auto p = data_ + field_offset; + return field_offset ? Optional(ReadScalar(p) != 0) + : Optional(); +} + +} // namespace flatbuffers + +#endif // FLATBUFFERS_TABLE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_util.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_util.h new file mode 100644 index 0000000..10138be --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_util.h @@ -0,0 +1,725 @@ +/* + * Copyright 2014 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_UTIL_H_ +#define FLATBUFFERS_UTIL_H_ + +#include +#include + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h" + +// For TFLM we always want to use FLATBUFFERS_PREFER_PRINTF=1. See +// http://b/211811553 for more context. +#ifndef FLATBUFFERS_PREFER_PRINTF +#define FLATBUFFERS_PREFER_PRINTF 1 +#endif + +#ifndef FLATBUFFERS_PREFER_PRINTF +# include +# include +#else // FLATBUFFERS_PREFER_PRINTF +# include +# include +#endif // FLATBUFFERS_PREFER_PRINTF + +#include + +namespace flatbuffers { + +// @locale-independent functions for ASCII characters set. + +// Fast checking that character lies in closed range: [a <= x <= b] +// using one compare (conditional branch) operator. +inline bool check_ascii_range(char x, char a, char b) { + FLATBUFFERS_ASSERT(a <= b); + // (Hacker's Delight): `a <= x <= b` <=> `(x-a) <={u} (b-a)`. + // The x, a, b will be promoted to int and subtracted without overflow. + return static_cast(x - a) <= static_cast(b - a); +} + +// Case-insensitive isalpha +inline bool is_alpha(char c) { + // ASCII only: alpha to upper case => reset bit 0x20 (~0x20 = 0xDF). + return check_ascii_range(c & 0xDF, 'a' & 0xDF, 'z' & 0xDF); +} + +// Check for uppercase alpha +inline bool is_alpha_upper(char c) { return check_ascii_range(c, 'A', 'Z'); } + +// Check (case-insensitive) that `c` is equal to alpha. +inline bool is_alpha_char(char c, char alpha) { + FLATBUFFERS_ASSERT(is_alpha(alpha)); + // ASCII only: alpha to upper case => reset bit 0x20 (~0x20 = 0xDF). + return ((c & 0xDF) == (alpha & 0xDF)); +} + +// https://en.cppreference.com/w/cpp/string/byte/isxdigit +// isdigit and isxdigit are the only standard narrow character classification +// functions that are not affected by the currently installed C locale. although +// some implementations (e.g. Microsoft in 1252 codepage) may classify +// additional single-byte characters as digits. +inline bool is_digit(char c) { return check_ascii_range(c, '0', '9'); } + +inline bool is_xdigit(char c) { + // Replace by look-up table. + return is_digit(c) || check_ascii_range(c & 0xDF, 'a' & 0xDF, 'f' & 0xDF); +} + +// Case-insensitive isalnum +inline bool is_alnum(char c) { return is_alpha(c) || is_digit(c); } + +inline char CharToUpper(char c) { + return static_cast(::toupper(static_cast(c))); +} + +inline char CharToLower(char c) { + return static_cast(::tolower(static_cast(c))); +} + +// @end-locale-independent functions for ASCII character set + +#ifdef FLATBUFFERS_PREFER_PRINTF +template size_t IntToDigitCount(T t) { + size_t digit_count = 0; + // Count the sign for negative numbers + if (t < 0) digit_count++; + // Count a single 0 left of the dot for fractional numbers + if (-1 < t && t < 1) digit_count++; + // Count digits until fractional part + T eps = std::numeric_limits::epsilon(); + while (t <= (-1 + eps) || (1 - eps) <= t) { + t /= 10; + digit_count++; + } + return digit_count; +} + +template size_t NumToStringWidth(T t, int precision = 0) { + size_t string_width = IntToDigitCount(t); + // Count the dot for floating point numbers + if (precision) string_width += (precision + 1); + return string_width; +} + +template +std::string NumToStringImplWrapper(T t, const char *fmt, int precision = 0) { + size_t string_width = NumToStringWidth(t, precision); + std::string s(string_width, 0x00); + // Allow snprintf to use std::string trailing null to detect buffer overflow + snprintf(const_cast(s.data()), (s.size() + 1), fmt, string_width, t); + return s; +} +#endif // FLATBUFFERS_PREFER_PRINTF + +// Convert an integer or floating point value to a string. +// In contrast to std::stringstream, "char" values are +// converted to a string of digits, and we don't use scientific notation. +template std::string NumToString(T t) { + // clang-format off + + #ifndef FLATBUFFERS_PREFER_PRINTF + std::stringstream ss; + ss << t; + return ss.str(); + #else // FLATBUFFERS_PREFER_PRINTF + auto v = static_cast(t); + return NumToStringImplWrapper(v, "%.*lld"); + #endif // FLATBUFFERS_PREFER_PRINTF + // clang-format on +} +// Avoid char types used as character data. +template<> inline std::string NumToString(signed char t) { + return NumToString(static_cast(t)); +} +template<> inline std::string NumToString(unsigned char t) { + return NumToString(static_cast(t)); +} +template<> inline std::string NumToString(char t) { + return NumToString(static_cast(t)); +} + +// Special versions for floats/doubles. +template std::string FloatToString(T t, int precision) { + // clang-format off + + #ifndef FLATBUFFERS_PREFER_PRINTF + // to_string() prints different numbers of digits for floats depending on + // platform and isn't available on Android, so we use stringstream + std::stringstream ss; + // Use std::fixed to suppress scientific notation. + ss << std::fixed; + // Default precision is 6, we want that to be higher for doubles. + ss << std::setprecision(precision); + ss << t; + auto s = ss.str(); + #else // FLATBUFFERS_PREFER_PRINTF + auto v = static_cast(t); + auto s = NumToStringImplWrapper(v, "%0.*f", precision); + #endif // FLATBUFFERS_PREFER_PRINTF + // clang-format on + // Sadly, std::fixed turns "1" into "1.00000", so here we undo that. + auto p = s.find_last_not_of('0'); + if (p != std::string::npos) { + // Strip trailing zeroes. If it is a whole number, keep one zero. + s.resize(p + (s[p] == '.' ? 2 : 1)); + } + return s; +} + +template<> inline std::string NumToString(double t) { + return FloatToString(t, 12); +} +template<> inline std::string NumToString(float t) { + return FloatToString(t, 6); +} + +// Convert an integer value to a hexadecimal string. +// The returned string length is always xdigits long, prefixed by 0 digits. +// For example, IntToStringHex(0x23, 8) returns the string "00000023". +inline std::string IntToStringHex(int i, int xdigits) { + FLATBUFFERS_ASSERT(i >= 0); + // clang-format off + + #ifndef FLATBUFFERS_PREFER_PRINTF + std::stringstream ss; + ss << std::setw(xdigits) << std::setfill('0') << std::hex << std::uppercase + << i; + return ss.str(); + #else // FLATBUFFERS_PREFER_PRINTF + return NumToStringImplWrapper(i, "%.*X", xdigits); + #endif // FLATBUFFERS_PREFER_PRINTF + // clang-format on +} + +// clang-format off +// Use locale independent functions {strtod_l, strtof_l, strtoll_l, strtoull_l}. +#if defined(FLATBUFFERS_LOCALE_INDEPENDENT) && (FLATBUFFERS_LOCALE_INDEPENDENT > 0) + class ClassicLocale { + #ifdef _MSC_VER + typedef _locale_t locale_type; + #else + typedef locale_t locale_type; // POSIX.1-2008 locale_t type + #endif + ClassicLocale(); + ~ClassicLocale(); + locale_type locale_; + static ClassicLocale instance_; + public: + static locale_type Get() { return instance_.locale_; } + }; + + #ifdef _MSC_VER + #define __strtoull_impl(s, pe, b) _strtoui64_l(s, pe, b, ClassicLocale::Get()) + #define __strtoll_impl(s, pe, b) _strtoi64_l(s, pe, b, ClassicLocale::Get()) + #define __strtod_impl(s, pe) _strtod_l(s, pe, ClassicLocale::Get()) + #define __strtof_impl(s, pe) _strtof_l(s, pe, ClassicLocale::Get()) + #else + #define __strtoull_impl(s, pe, b) strtoull_l(s, pe, b, ClassicLocale::Get()) + #define __strtoll_impl(s, pe, b) strtoll_l(s, pe, b, ClassicLocale::Get()) + #define __strtod_impl(s, pe) strtod_l(s, pe, ClassicLocale::Get()) + #define __strtof_impl(s, pe) strtof_l(s, pe, ClassicLocale::Get()) + #endif +#else + #define __strtod_impl(s, pe) strtod(s, pe) + #define __strtof_impl(s, pe) static_cast(strtod(s, pe)) + #ifdef _MSC_VER + #define __strtoull_impl(s, pe, b) _strtoui64(s, pe, b) + #define __strtoll_impl(s, pe, b) _strtoi64(s, pe, b) + #else + #define __strtoull_impl(s, pe, b) strtoull(s, pe, b) + #define __strtoll_impl(s, pe, b) strtoll(s, pe, b) + #endif +#endif + +inline void strtoval_impl(int64_t *val, const char *str, char **endptr, + int base) { + *val = __strtoll_impl(str, endptr, base); +} + +inline void strtoval_impl(uint64_t *val, const char *str, char **endptr, + int base) { + *val = __strtoull_impl(str, endptr, base); +} + +inline void strtoval_impl(double *val, const char *str, char **endptr) { + *val = __strtod_impl(str, endptr); +} + +// UBSAN: double to float is safe if numeric_limits::is_iec559 is true. +__supress_ubsan__("float-cast-overflow") +inline void strtoval_impl(float *val, const char *str, char **endptr) { + *val = __strtof_impl(str, endptr); +} +#undef __strtoull_impl +#undef __strtoll_impl +#undef __strtod_impl +#undef __strtof_impl +// clang-format on + +// Adaptor for strtoull()/strtoll(). +// Flatbuffers accepts numbers with any count of leading zeros (-009 is -9), +// while strtoll with base=0 interprets first leading zero as octal prefix. +// In future, it is possible to add prefixed 0b0101. +// 1) Checks errno code for overflow condition (out of range). +// 2) If base <= 0, function try to detect base of number by prefix. +// +// Return value (like strtoull and strtoll, but reject partial result): +// - If successful, an integer value corresponding to the str is returned. +// - If full string conversion can't be performed, 0 is returned. +// - If the converted value falls out of range of corresponding return type, a +// range error occurs. In this case value MAX(T)/MIN(T) is returned. +template +inline bool StringToIntegerImpl(T *val, const char *const str, + const int base = 0, + const bool check_errno = true) { + // T is int64_t or uint64_T + FLATBUFFERS_ASSERT(str); + if (base <= 0) { + auto s = str; + while (*s && !is_digit(*s)) s++; + if (s[0] == '0' && is_alpha_char(s[1], 'X')) + return StringToIntegerImpl(val, str, 16, check_errno); + // if a prefix not match, try base=10 + return StringToIntegerImpl(val, str, 10, check_errno); + } else { + if (check_errno) errno = 0; // clear thread-local errno + auto endptr = str; + strtoval_impl(val, str, const_cast(&endptr), base); + if ((*endptr != '\0') || (endptr == str)) { + *val = 0; // erase partial result + return false; // invalid string + } + // errno is out-of-range, return MAX/MIN + if (check_errno && errno) return false; + return true; + } +} + +template +inline bool StringToFloatImpl(T *val, const char *const str) { + // Type T must be either float or double. + FLATBUFFERS_ASSERT(str && val); + auto end = str; + strtoval_impl(val, str, const_cast(&end)); + auto done = (end != str) && (*end == '\0'); + if (!done) *val = 0; // erase partial result + return done; +} + +// Convert a string to an instance of T. +// Return value (matched with StringToInteger64Impl and strtod): +// - If successful, a numeric value corresponding to the str is returned. +// - If full string conversion can't be performed, 0 is returned. +// - If the converted value falls out of range of corresponding return type, a +// range error occurs. In this case value MAX(T)/MIN(T) is returned. +template inline bool StringToNumber(const char *s, T *val) { + // Assert on `unsigned long` and `signed long` on LP64. + // If it is necessary, it could be solved with flatbuffers::enable_if. + static_assert(sizeof(T) < sizeof(int64_t), "unexpected type T"); + FLATBUFFERS_ASSERT(s && val); + int64_t i64; + // The errno check isn't needed, will return MAX/MIN on overflow. + if (StringToIntegerImpl(&i64, s, 0, false)) { + const int64_t max = (flatbuffers::numeric_limits::max)(); + const int64_t min = flatbuffers::numeric_limits::lowest(); + if (i64 > max) { + *val = static_cast(max); + return false; + } + if (i64 < min) { + // For unsigned types return max to distinguish from + // "no conversion can be performed" when 0 is returned. + *val = static_cast(flatbuffers::is_unsigned::value ? max : min); + return false; + } + *val = static_cast(i64); + return true; + } + *val = 0; + return false; +} + +template<> inline bool StringToNumber(const char *str, int64_t *val) { + return StringToIntegerImpl(val, str); +} + +template<> +inline bool StringToNumber(const char *str, uint64_t *val) { + if (!StringToIntegerImpl(val, str)) return false; + // The strtoull accepts negative numbers: + // If the minus sign was part of the input sequence, the numeric value + // calculated from the sequence of digits is negated as if by unary minus + // in the result type, which applies unsigned integer wraparound rules. + // Fix this behaviour (except -0). + if (*val) { + auto s = str; + while (*s && !is_digit(*s)) s++; + s = (s > str) ? (s - 1) : s; // step back to one symbol + if (*s == '-') { + // For unsigned types return the max to distinguish from + // "no conversion can be performed". + *val = (flatbuffers::numeric_limits::max)(); + return false; + } + } + return true; +} + +template<> inline bool StringToNumber(const char *s, float *val) { + return StringToFloatImpl(val, s); +} + +template<> inline bool StringToNumber(const char *s, double *val) { + return StringToFloatImpl(val, s); +} + +inline int64_t StringToInt(const char *s, int base = 10) { + int64_t val; + return StringToIntegerImpl(&val, s, base) ? val : 0; +} + +inline uint64_t StringToUInt(const char *s, int base = 10) { + uint64_t val; + return StringToIntegerImpl(&val, s, base) ? val : 0; +} + +typedef bool (*LoadFileFunction)(const char *filename, bool binary, + std::string *dest); +typedef bool (*FileExistsFunction)(const char *filename); + +LoadFileFunction SetLoadFileFunction(LoadFileFunction load_file_function); + +FileExistsFunction SetFileExistsFunction( + FileExistsFunction file_exists_function); + +// Check if file "name" exists. +bool FileExists(const char *name); + +// Check if "name" exists and it is also a directory. +bool DirExists(const char *name); + +// Load file "name" into "buf" returning true if successful +// false otherwise. If "binary" is false data is read +// using ifstream's text mode, otherwise data is read with +// no transcoding. +bool LoadFile(const char *name, bool binary, std::string *buf); + +// Save data "buf" of length "len" bytes into a file +// "name" returning true if successful, false otherwise. +// If "binary" is false data is written using ifstream's +// text mode, otherwise data is written with no +// transcoding. +bool SaveFile(const char *name, const char *buf, size_t len, bool binary); + +// Save data "buf" into file "name" returning true if +// successful, false otherwise. If "binary" is false +// data is written using ifstream's text mode, otherwise +// data is written with no transcoding. +inline bool SaveFile(const char *name, const std::string &buf, bool binary) { + return SaveFile(name, buf.c_str(), buf.size(), binary); +} + +// Functionality for minimalistic portable path handling. + +// The functions below behave correctly regardless of whether posix ('/') or +// Windows ('/' or '\\') separators are used. + +// Any new separators inserted are always posix. +FLATBUFFERS_CONSTEXPR char kPathSeparator = '/'; + +// Returns the path with the extension, if any, removed. +std::string StripExtension(const std::string &filepath); + +// Returns the extension, if any. +std::string GetExtension(const std::string &filepath); + +// Return the last component of the path, after the last separator. +std::string StripPath(const std::string &filepath); + +// Strip the last component of the path + separator. +std::string StripFileName(const std::string &filepath); + +std::string StripPrefix(const std::string &filepath, + const std::string &prefix_to_remove); + +// Concatenates a path with a filename, regardless of whether the path +// ends in a separator or not. +std::string ConCatPathFileName(const std::string &path, + const std::string &filename); + +// Replaces any '\\' separators with '/' +std::string PosixPath(const char *path); +std::string PosixPath(const std::string &path); + +// This function ensure a directory exists, by recursively +// creating dirs for any parts of the path that don't exist yet. +void EnsureDirExists(const std::string &filepath); + +// Obtains the absolute path from any other path. +// Returns the input path if the absolute path couldn't be resolved. +std::string AbsolutePath(const std::string &filepath); + +// Returns files relative to the --project_root path, prefixed with `//`. +std::string RelativeToRootPath(const std::string &project, + const std::string &filepath); + +// To and from UTF-8 unicode conversion functions + +// Convert a unicode code point into a UTF-8 representation by appending it +// to a string. Returns the number of bytes generated. +inline int ToUTF8(uint32_t ucc, std::string *out) { + FLATBUFFERS_ASSERT(!(ucc & 0x80000000)); // Top bit can't be set. + // 6 possible encodings: http://en.wikipedia.org/wiki/UTF-8 + for (int i = 0; i < 6; i++) { + // Max bits this encoding can represent. + uint32_t max_bits = 6 + i * 5 + static_cast(!i); + if (ucc < (1u << max_bits)) { // does it fit? + // Remaining bits not encoded in the first byte, store 6 bits each + uint32_t remain_bits = i * 6; + // Store first byte: + (*out) += static_cast((0xFE << (max_bits - remain_bits)) | + (ucc >> remain_bits)); + // Store remaining bytes: + for (int j = i - 1; j >= 0; j--) { + (*out) += static_cast(((ucc >> (j * 6)) & 0x3F) | 0x80); + } + return i + 1; // Return the number of bytes added. + } + } + FLATBUFFERS_ASSERT(0); // Impossible to arrive here. + return -1; +} + +// Converts whatever prefix of the incoming string corresponds to a valid +// UTF-8 sequence into a unicode code. The incoming pointer will have been +// advanced past all bytes parsed. +// returns -1 upon corrupt UTF-8 encoding (ignore the incoming pointer in +// this case). +inline int FromUTF8(const char **in) { + int len = 0; + // Count leading 1 bits. + for (int mask = 0x80; mask >= 0x04; mask >>= 1) { + if (**in & mask) { + len++; + } else { + break; + } + } + if ((static_cast(**in) << len) & 0x80) + return -1; // Bit after leading 1's must be 0. + if (!len) return *(*in)++; + // UTF-8 encoded values with a length are between 2 and 4 bytes. + if (len < 2 || len > 4) { return -1; } + // Grab initial bits of the code. + int ucc = *(*in)++ & ((1 << (7 - len)) - 1); + for (int i = 0; i < len - 1; i++) { + if ((**in & 0xC0) != 0x80) return -1; // Upper bits must 1 0. + ucc <<= 6; + ucc |= *(*in)++ & 0x3F; // Grab 6 more bits of the code. + } + // UTF-8 cannot encode values between 0xD800 and 0xDFFF (reserved for + // UTF-16 surrogate pairs). + if (ucc >= 0xD800 && ucc <= 0xDFFF) { return -1; } + // UTF-8 must represent code points in their shortest possible encoding. + switch (len) { + case 2: + // Two bytes of UTF-8 can represent code points from U+0080 to U+07FF. + if (ucc < 0x0080 || ucc > 0x07FF) { return -1; } + break; + case 3: + // Three bytes of UTF-8 can represent code points from U+0800 to U+FFFF. + if (ucc < 0x0800 || ucc > 0xFFFF) { return -1; } + break; + case 4: + // Four bytes of UTF-8 can represent code points from U+10000 to U+10FFFF. + if (ucc < 0x10000 || ucc > 0x10FFFF) { return -1; } + break; + } + return ucc; +} + +#ifndef FLATBUFFERS_PREFER_PRINTF +// Wraps a string to a maximum length, inserting new lines where necessary. Any +// existing whitespace will be collapsed down to a single space. A prefix or +// suffix can be provided, which will be inserted before or after a wrapped +// line, respectively. +inline std::string WordWrap(const std::string in, size_t max_length, + const std::string wrapped_line_prefix, + const std::string wrapped_line_suffix) { + std::istringstream in_stream(in); + std::string wrapped, line, word; + + in_stream >> word; + line = word; + + while (in_stream >> word) { + if ((line.length() + 1 + word.length() + wrapped_line_suffix.length()) < + max_length) { + line += " " + word; + } else { + wrapped += line + wrapped_line_suffix + "\n"; + line = wrapped_line_prefix + word; + } + } + wrapped += line; + + return wrapped; +} +#endif // !FLATBUFFERS_PREFER_PRINTF + +inline bool EscapeString(const char *s, size_t length, std::string *_text, + bool allow_non_utf8, bool natural_utf8) { + std::string &text = *_text; + text += "\""; + for (uoffset_t i = 0; i < length; i++) { + char c = s[i]; + switch (c) { + case '\n': text += "\\n"; break; + case '\t': text += "\\t"; break; + case '\r': text += "\\r"; break; + case '\b': text += "\\b"; break; + case '\f': text += "\\f"; break; + case '\"': text += "\\\""; break; + case '\\': text += "\\\\"; break; + default: + if (c >= ' ' && c <= '~') { + text += c; + } else { + // Not printable ASCII data. Let's see if it's valid UTF-8 first: + const char *utf8 = s + i; + int ucc = FromUTF8(&utf8); + if (ucc < 0) { + if (allow_non_utf8) { + text += "\\x"; + text += IntToStringHex(static_cast(c), 2); + } else { + // There are two cases here: + // + // 1) We reached here by parsing an IDL file. In that case, + // we previously checked for non-UTF-8, so we shouldn't reach + // here. + // + // 2) We reached here by someone calling GenerateText() + // on a previously-serialized flatbuffer. The data might have + // non-UTF-8 Strings, or might be corrupt. + // + // In both cases, we have to give up and inform the caller + // they have no JSON. + return false; + } + } else { + if (natural_utf8) { + // utf8 points to past all utf-8 bytes parsed + text.append(s + i, static_cast(utf8 - s - i)); + } else if (ucc <= 0xFFFF) { + // Parses as Unicode within JSON's \uXXXX range, so use that. + text += "\\u"; + text += IntToStringHex(ucc, 4); + } else if (ucc <= 0x10FFFF) { + // Encode Unicode SMP values to a surrogate pair using two \u + // escapes. + uint32_t base = ucc - 0x10000; + auto high_surrogate = (base >> 10) + 0xD800; + auto low_surrogate = (base & 0x03FF) + 0xDC00; + text += "\\u"; + text += IntToStringHex(high_surrogate, 4); + text += "\\u"; + text += IntToStringHex(low_surrogate, 4); + } + // Skip past characters recognized. + i = static_cast(utf8 - s - 1); + } + } + break; + } + } + text += "\""; + return true; +} + +inline std::string BufferToHexText(const void *buffer, size_t buffer_size, + size_t max_length, + const std::string &wrapped_line_prefix, + const std::string &wrapped_line_suffix) { + std::string text = wrapped_line_prefix; + size_t start_offset = 0; + const char *s = reinterpret_cast(buffer); + for (size_t i = 0; s && i < buffer_size; i++) { + // Last iteration or do we have more? + bool have_more = i + 1 < buffer_size; + text += "0x"; + text += IntToStringHex(static_cast(s[i]), 2); + if (have_more) { text += ','; } + // If we have more to process and we reached max_length + if (have_more && + text.size() + wrapped_line_suffix.size() >= start_offset + max_length) { + text += wrapped_line_suffix; + text += '\n'; + start_offset = text.size(); + text += wrapped_line_prefix; + } + } + text += wrapped_line_suffix; + return text; +} + +// Remove paired quotes in a string: "text"|'text' -> text. +std::string RemoveStringQuotes(const std::string &s); + +// Change th global C-locale to locale with name . +// Returns an actual locale name in <_value>, useful if locale_name is "" or +// null. +bool SetGlobalTestLocale(const char *locale_name, + std::string *_value = nullptr); + +// Read (or test) a value of environment variable. +bool ReadEnvironmentVariable(const char *var_name, + std::string *_value = nullptr); + +// MSVC specific: Send all assert reports to STDOUT to prevent CI hangs. +void SetupDefaultCRTReportMode(); + +enum class Case { + kUnknown = 0, + // TheQuickBrownFox + kUpperCamel = 1, + // theQuickBrownFox + kLowerCamel = 2, + // the_quick_brown_fox + kSnake = 3, + // THE_QUICK_BROWN_FOX + kScreamingSnake = 4, + // THEQUICKBROWNFOX + kAllUpper = 5, + // thequickbrownfox + kAllLower = 6, + // the-quick-brown-fox + kDasher = 7, + // THEQuiCKBr_ownFox (or whatever you want, we won't change it) + kKeep = 8, + // the_quick_brown_fox123 (as opposed to the_quick_brown_fox_123) + kSnake2 = 9, +}; + +// Convert the `input` string of case `input_case` to the specified `output_case`. +std::string ConvertCase(const std::string &input, Case output_case, + Case input_case = Case::kSnake); + +} // namespace flatbuffers + +#endif // FLATBUFFERS_UTIL_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h new file mode 100644 index 0000000..81f583b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h @@ -0,0 +1,389 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_VECTOR_H_ +#define FLATBUFFERS_VECTOR_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h" + +namespace flatbuffers { + +struct String; + +// An STL compatible iterator implementation for Vector below, effectively +// calling Get() for every element. +template struct VectorIterator { + typedef std::random_access_iterator_tag iterator_category; + typedef IT value_type; + typedef ptrdiff_t difference_type; + typedef IT *pointer; + typedef IT &reference; + + VectorIterator(const uint8_t *data, uoffset_t i) + : data_(data + IndirectHelper::element_stride * i) {} + VectorIterator(const VectorIterator &other) : data_(other.data_) {} + VectorIterator() : data_(nullptr) {} + + VectorIterator &operator=(const VectorIterator &other) { + data_ = other.data_; + return *this; + } + + VectorIterator &operator=(VectorIterator &&other) { + data_ = other.data_; + return *this; + } + + bool operator==(const VectorIterator &other) const { + return data_ == other.data_; + } + + bool operator<(const VectorIterator &other) const { + return data_ < other.data_; + } + + bool operator!=(const VectorIterator &other) const { + return data_ != other.data_; + } + + difference_type operator-(const VectorIterator &other) const { + return (data_ - other.data_) / IndirectHelper::element_stride; + } + + // Note: return type is incompatible with the standard + // `reference operator*()`. + IT operator*() const { return IndirectHelper::Read(data_, 0); } + + // Note: return type is incompatible with the standard + // `pointer operator->()`. + IT operator->() const { return IndirectHelper::Read(data_, 0); } + + VectorIterator &operator++() { + data_ += IndirectHelper::element_stride; + return *this; + } + + VectorIterator operator++(int) { + VectorIterator temp(data_, 0); + data_ += IndirectHelper::element_stride; + return temp; + } + + VectorIterator operator+(const uoffset_t &offset) const { + return VectorIterator(data_ + offset * IndirectHelper::element_stride, + 0); + } + + VectorIterator &operator+=(const uoffset_t &offset) { + data_ += offset * IndirectHelper::element_stride; + return *this; + } + + VectorIterator &operator--() { + data_ -= IndirectHelper::element_stride; + return *this; + } + + VectorIterator operator--(int) { + VectorIterator temp(data_, 0); + data_ -= IndirectHelper::element_stride; + return temp; + } + + VectorIterator operator-(const uoffset_t &offset) const { + return VectorIterator(data_ - offset * IndirectHelper::element_stride, + 0); + } + + VectorIterator &operator-=(const uoffset_t &offset) { + data_ -= offset * IndirectHelper::element_stride; + return *this; + } + + private: + const uint8_t *data_; +}; + +template +struct VectorReverseIterator : public std::reverse_iterator { + explicit VectorReverseIterator(Iterator iter) + : std::reverse_iterator(iter) {} + + // Note: return type is incompatible with the standard + // `reference operator*()`. + typename Iterator::value_type operator*() const { + auto tmp = std::reverse_iterator::current; + return *--tmp; + } + + // Note: return type is incompatible with the standard + // `pointer operator->()`. + typename Iterator::value_type operator->() const { + auto tmp = std::reverse_iterator::current; + return *--tmp; + } +}; + +// This is used as a helper type for accessing vectors. +// Vector::data() assumes the vector elements start after the length field. +template class Vector { + public: + typedef VectorIterator::mutable_return_type> + iterator; + typedef VectorIterator::return_type> + const_iterator; + typedef VectorReverseIterator reverse_iterator; + typedef VectorReverseIterator const_reverse_iterator; + + typedef typename flatbuffers::bool_constant::value> + scalar_tag; + + static FLATBUFFERS_CONSTEXPR bool is_span_observable = + scalar_tag::value && (FLATBUFFERS_LITTLEENDIAN || sizeof(T) == 1); + + uoffset_t size() const { return EndianScalar(length_); } + + // Deprecated: use size(). Here for backwards compatibility. + FLATBUFFERS_ATTRIBUTE([[deprecated("use size() instead")]]) + uoffset_t Length() const { return size(); } + + typedef typename IndirectHelper::return_type return_type; + typedef typename IndirectHelper::mutable_return_type mutable_return_type; + typedef return_type value_type; + + return_type Get(uoffset_t i) const { + FLATBUFFERS_ASSERT(i < size()); + return IndirectHelper::Read(Data(), i); + } + + return_type operator[](uoffset_t i) const { return Get(i); } + + // If this is a Vector of enums, T will be its storage type, not the enum + // type. This function makes it convenient to retrieve value with enum + // type E. + template E GetEnum(uoffset_t i) const { + return static_cast(Get(i)); + } + + // If this a vector of unions, this does the cast for you. There's no check + // to make sure this is the right type! + template const U *GetAs(uoffset_t i) const { + return reinterpret_cast(Get(i)); + } + + // If this a vector of unions, this does the cast for you. There's no check + // to make sure this is actually a string! + const String *GetAsString(uoffset_t i) const { + return reinterpret_cast(Get(i)); + } + + const void *GetStructFromOffset(size_t o) const { + return reinterpret_cast(Data() + o); + } + + iterator begin() { return iterator(Data(), 0); } + const_iterator begin() const { return const_iterator(Data(), 0); } + + iterator end() { return iterator(Data(), size()); } + const_iterator end() const { return const_iterator(Data(), size()); } + + reverse_iterator rbegin() { return reverse_iterator(end()); } + const_reverse_iterator rbegin() const { + return const_reverse_iterator(end()); + } + + reverse_iterator rend() { return reverse_iterator(begin()); } + const_reverse_iterator rend() const { + return const_reverse_iterator(begin()); + } + + const_iterator cbegin() const { return begin(); } + + const_iterator cend() const { return end(); } + + const_reverse_iterator crbegin() const { return rbegin(); } + + const_reverse_iterator crend() const { return rend(); } + + // Change elements if you have a non-const pointer to this object. + // Scalars only. See reflection.h, and the documentation. + void Mutate(uoffset_t i, const T &val) { + FLATBUFFERS_ASSERT(i < size()); + WriteScalar(data() + i, val); + } + + // Change an element of a vector of tables (or strings). + // "val" points to the new table/string, as you can obtain from + // e.g. reflection::AddFlatBuffer(). + void MutateOffset(uoffset_t i, const uint8_t *val) { + FLATBUFFERS_ASSERT(i < size()); + static_assert(sizeof(T) == sizeof(uoffset_t), "Unrelated types"); + WriteScalar(data() + i, + static_cast(val - (Data() + i * sizeof(uoffset_t)))); + } + + // Get a mutable pointer to tables/strings inside this vector. + mutable_return_type GetMutableObject(uoffset_t i) const { + FLATBUFFERS_ASSERT(i < size()); + return const_cast(IndirectHelper::Read(Data(), i)); + } + + // The raw data in little endian format. Use with care. + const uint8_t *Data() const { + return reinterpret_cast(&length_ + 1); + } + + uint8_t *Data() { return reinterpret_cast(&length_ + 1); } + + // Similarly, but typed, much like std::vector::data + const T *data() const { return reinterpret_cast(Data()); } + T *data() { return reinterpret_cast(Data()); } + + template return_type LookupByKey(K key) const { + void *search_result = std::bsearch( + &key, Data(), size(), IndirectHelper::element_stride, KeyCompare); + + if (!search_result) { + return nullptr; // Key not found. + } + + const uint8_t *element = reinterpret_cast(search_result); + + return IndirectHelper::Read(element, 0); + } + + template mutable_return_type MutableLookupByKey(K key) { + return const_cast(LookupByKey(key)); + } + + protected: + // This class is only used to access pre-existing data. Don't ever + // try to construct these manually. + Vector(); + + uoffset_t length_; + + private: + // This class is a pointer. Copying will therefore create an invalid object. + // Private and unimplemented copy constructor. + Vector(const Vector &); + Vector &operator=(const Vector &); + + template static int KeyCompare(const void *ap, const void *bp) { + const K *key = reinterpret_cast(ap); + const uint8_t *data = reinterpret_cast(bp); + auto table = IndirectHelper::Read(data, 0); + + // std::bsearch compares with the operands transposed, so we negate the + // result here. + return -table->KeyCompareWithValue(*key); + } +}; + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_span(Vector &vec) + FLATBUFFERS_NOEXCEPT { + static_assert(Vector::is_span_observable, + "wrong type U, only LE-scalar, or byte types are allowed"); + return span(vec.data(), vec.size()); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_span( + const Vector &vec) FLATBUFFERS_NOEXCEPT { + static_assert(Vector::is_span_observable, + "wrong type U, only LE-scalar, or byte types are allowed"); + return span(vec.data(), vec.size()); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_bytes_span( + Vector &vec) FLATBUFFERS_NOEXCEPT { + static_assert(Vector::scalar_tag::value, + "wrong type U, only LE-scalar, or byte types are allowed"); + return span(vec.Data(), vec.size() * sizeof(U)); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_bytes_span( + const Vector &vec) FLATBUFFERS_NOEXCEPT { + static_assert(Vector::scalar_tag::value, + "wrong type U, only LE-scalar, or byte types are allowed"); + return span(vec.Data(), vec.size() * sizeof(U)); +} + +// Convenient helper functions to get a span of any vector, regardless +// of whether it is null or not (the field is not set). +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_span(Vector *ptr) + FLATBUFFERS_NOEXCEPT { + static_assert(Vector::is_span_observable, + "wrong type U, only LE-scalar, or byte types are allowed"); + return ptr ? make_span(*ptr) : span(); +} + +template +FLATBUFFERS_CONSTEXPR_CPP11 flatbuffers::span make_span( + const Vector *ptr) FLATBUFFERS_NOEXCEPT { + static_assert(Vector::is_span_observable, + "wrong type U, only LE-scalar, or byte types are allowed"); + return ptr ? make_span(*ptr) : span(); +} + +// Represent a vector much like the template above, but in this case we +// don't know what the element types are (used with reflection.h). +class VectorOfAny { + public: + uoffset_t size() const { return EndianScalar(length_); } + + const uint8_t *Data() const { + return reinterpret_cast(&length_ + 1); + } + uint8_t *Data() { return reinterpret_cast(&length_ + 1); } + + protected: + VectorOfAny(); + + uoffset_t length_; + + private: + VectorOfAny(const VectorOfAny &); + VectorOfAny &operator=(const VectorOfAny &); +}; + +template +Vector> *VectorCast(Vector> *ptr) { + static_assert(std::is_base_of::value, "Unrelated types"); + return reinterpret_cast> *>(ptr); +} + +template +const Vector> *VectorCast(const Vector> *ptr) { + static_assert(std::is_base_of::value, "Unrelated types"); + return reinterpret_cast> *>(ptr); +} + +// Convenient helper function to get the length of any vector, regardless +// of whether it is null or not (the field is not set). +template static inline size_t VectorLength(const Vector *v) { + return v ? v->size() : 0; +} + +} // namespace flatbuffers + +#endif // FLATBUFFERS_VERIFIER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector_downward.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector_downward.h new file mode 100644 index 0000000..6ff86a9 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector_downward.h @@ -0,0 +1,271 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_VECTOR_DOWNWARD_H_ +#define FLATBUFFERS_VECTOR_DOWNWARD_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_default_allocator.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_detached_buffer.h" + +namespace flatbuffers { + +// This is a minimal replication of std::vector functionality, +// except growing from higher to lower addresses. i.e push_back() inserts data +// in the lowest address in the vector. +// Since this vector leaves the lower part unused, we support a "scratch-pad" +// that can be stored there for temporary data, to share the allocated space. +// Essentially, this supports 2 std::vectors in a single buffer. +class vector_downward { + public: + explicit vector_downward(size_t initial_size, Allocator *allocator, + bool own_allocator, size_t buffer_minalign) + : allocator_(allocator), + own_allocator_(own_allocator), + initial_size_(initial_size), + buffer_minalign_(buffer_minalign), + reserved_(0), + size_(0), + buf_(nullptr), + cur_(nullptr), + scratch_(nullptr) {} + + vector_downward(vector_downward &&other) + // clang-format on + : allocator_(other.allocator_), + own_allocator_(other.own_allocator_), + initial_size_(other.initial_size_), + buffer_minalign_(other.buffer_minalign_), + reserved_(other.reserved_), + size_(other.size_), + buf_(other.buf_), + cur_(other.cur_), + scratch_(other.scratch_) { + // No change in other.allocator_ + // No change in other.initial_size_ + // No change in other.buffer_minalign_ + other.own_allocator_ = false; + other.reserved_ = 0; + other.buf_ = nullptr; + other.cur_ = nullptr; + other.scratch_ = nullptr; + } + + vector_downward &operator=(vector_downward &&other) { + // Move construct a temporary and swap idiom + vector_downward temp(std::move(other)); + swap(temp); + return *this; + } + + ~vector_downward() { + clear_buffer(); + clear_allocator(); + } + + void reset() { + clear_buffer(); + clear(); + } + + void clear() { + if (buf_) { + cur_ = buf_ + reserved_; + } else { + reserved_ = 0; + cur_ = nullptr; + } + size_ = 0; + clear_scratch(); + } + + void clear_scratch() { scratch_ = buf_; } + + void clear_allocator() { + if (own_allocator_ && allocator_) { delete allocator_; } + allocator_ = nullptr; + own_allocator_ = false; + } + + void clear_buffer() { + if (buf_) Deallocate(allocator_, buf_, reserved_); + buf_ = nullptr; + } + + // Relinquish the pointer to the caller. + uint8_t *release_raw(size_t &allocated_bytes, size_t &offset) { + auto *buf = buf_; + allocated_bytes = reserved_; + offset = static_cast(cur_ - buf_); + + // release_raw only relinquishes the buffer ownership. + // Does not deallocate or reset the allocator. Destructor will do that. + buf_ = nullptr; + clear(); + return buf; + } + + // Relinquish the pointer to the caller. + DetachedBuffer release() { + // allocator ownership (if any) is transferred to DetachedBuffer. + DetachedBuffer fb(allocator_, own_allocator_, buf_, reserved_, cur_, + size()); + if (own_allocator_) { + allocator_ = nullptr; + own_allocator_ = false; + } + buf_ = nullptr; + clear(); + return fb; + } + + size_t ensure_space(size_t len) { + FLATBUFFERS_ASSERT(cur_ >= scratch_ && scratch_ >= buf_); + if (len > static_cast(cur_ - scratch_)) { reallocate(len); } + // Beyond this, signed offsets may not have enough range: + // (FlatBuffers > 2GB not supported). + FLATBUFFERS_ASSERT(size() < FLATBUFFERS_MAX_BUFFER_SIZE); + return len; + } + + inline uint8_t *make_space(size_t len) { + if (len) { + ensure_space(len); + cur_ -= len; + size_ += static_cast(len); + } + return cur_; + } + + // Returns nullptr if using the DefaultAllocator. + Allocator *get_custom_allocator() { return allocator_; } + + inline uoffset_t size() const { return size_; } + + uoffset_t scratch_size() const { + return static_cast(scratch_ - buf_); + } + + size_t capacity() const { return reserved_; } + + uint8_t *data() const { + FLATBUFFERS_ASSERT(cur_); + return cur_; + } + + uint8_t *scratch_data() const { + FLATBUFFERS_ASSERT(buf_); + return buf_; + } + + uint8_t *scratch_end() const { + FLATBUFFERS_ASSERT(scratch_); + return scratch_; + } + + uint8_t *data_at(size_t offset) const { return buf_ + reserved_ - offset; } + + void push(const uint8_t *bytes, size_t num) { + if (num > 0) { memcpy(make_space(num), bytes, num); } + } + + // Specialized version of push() that avoids memcpy call for small data. + template void push_small(const T &little_endian_t) { + make_space(sizeof(T)); + *reinterpret_cast(cur_) = little_endian_t; + } + + template void scratch_push_small(const T &t) { + ensure_space(sizeof(T)); + *reinterpret_cast(scratch_) = t; + scratch_ += sizeof(T); + } + + // fill() is most frequently called with small byte counts (<= 4), + // which is why we're using loops rather than calling memset. + void fill(size_t zero_pad_bytes) { + make_space(zero_pad_bytes); + for (size_t i = 0; i < zero_pad_bytes; i++) cur_[i] = 0; + } + + // Version for when we know the size is larger. + // Precondition: zero_pad_bytes > 0 + void fill_big(size_t zero_pad_bytes) { + memset(make_space(zero_pad_bytes), 0, zero_pad_bytes); + } + + void pop(size_t bytes_to_remove) { + cur_ += bytes_to_remove; + size_ -= static_cast(bytes_to_remove); + } + + void scratch_pop(size_t bytes_to_remove) { scratch_ -= bytes_to_remove; } + + void swap(vector_downward &other) { + using std::swap; + swap(allocator_, other.allocator_); + swap(own_allocator_, other.own_allocator_); + swap(initial_size_, other.initial_size_); + swap(buffer_minalign_, other.buffer_minalign_); + swap(reserved_, other.reserved_); + swap(size_, other.size_); + swap(buf_, other.buf_); + swap(cur_, other.cur_); + swap(scratch_, other.scratch_); + } + + void swap_allocator(vector_downward &other) { + using std::swap; + swap(allocator_, other.allocator_); + swap(own_allocator_, other.own_allocator_); + } + + private: + // You shouldn't really be copying instances of this class. + FLATBUFFERS_DELETE_FUNC(vector_downward(const vector_downward &)); + FLATBUFFERS_DELETE_FUNC(vector_downward &operator=(const vector_downward &)); + + Allocator *allocator_; + bool own_allocator_; + size_t initial_size_; + size_t buffer_minalign_; + size_t reserved_; + uoffset_t size_; + uint8_t *buf_; + uint8_t *cur_; // Points at location between empty (below) and used (above). + uint8_t *scratch_; // Points to the end of the scratchpad in use. + + void reallocate(size_t len) { + auto old_reserved = reserved_; + auto old_size = size(); + auto old_scratch_size = scratch_size(); + reserved_ += + (std::max)(len, old_reserved ? old_reserved / 2 : initial_size_); + reserved_ = (reserved_ + buffer_minalign_ - 1) & ~(buffer_minalign_ - 1); + if (buf_) { + buf_ = ReallocateDownward(allocator_, buf_, old_reserved, reserved_, + old_size, old_scratch_size); + } else { + buf_ = Allocate(allocator_, reserved_); + } + cur_ = buf_ + reserved_ - old_size; + scratch_ = buf_ + old_scratch_size; + } +}; + +} // namespace flatbuffers + +#endif // FLATBUFFERS_VECTOR_DOWNWARD_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h new file mode 100644 index 0000000..5f13e27 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h @@ -0,0 +1,304 @@ +/* + * Copyright 2021 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_VERIFIER_H_ +#define FLATBUFFERS_VERIFIER_H_ + +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h" + +namespace flatbuffers { + +// Helper class to verify the integrity of a FlatBuffer +class Verifier FLATBUFFERS_FINAL_CLASS { + public: + Verifier(const uint8_t *const buf, const size_t buf_len, + const uoffset_t _max_depth = 64, + const uoffset_t _max_tables = 1000000, + const bool _check_alignment = true) + : buf_(buf), + size_(buf_len), + max_depth_(_max_depth), + max_tables_(_max_tables), + check_alignment_(_check_alignment), + upper_bound_(0), + depth_(0), + num_tables_(0), + flex_reuse_tracker_(nullptr) { + FLATBUFFERS_ASSERT(size_ < FLATBUFFERS_MAX_BUFFER_SIZE); + } + + // Central location where any verification failures register. + bool Check(const bool ok) const { + // clang-format off + #ifdef FLATBUFFERS_DEBUG_VERIFICATION_FAILURE + FLATBUFFERS_ASSERT(ok); + #endif + #ifdef FLATBUFFERS_TRACK_VERIFIER_BUFFER_SIZE + if (!ok) + upper_bound_ = 0; + #endif + // clang-format on + return ok; + } + + // Verify any range within the buffer. + bool Verify(const size_t elem, const size_t elem_len) const { + // clang-format off + #ifdef FLATBUFFERS_TRACK_VERIFIER_BUFFER_SIZE + auto upper_bound = elem + elem_len; + if (upper_bound_ < upper_bound) + upper_bound_ = upper_bound; + #endif + // clang-format on + return Check(elem_len < size_ && elem <= size_ - elem_len); + } + + bool VerifyAlignment(const size_t elem, const size_t align) const { + return Check((elem & (align - 1)) == 0 || !check_alignment_); + } + + // Verify a range indicated by sizeof(T). + template bool Verify(const size_t elem) const { + return VerifyAlignment(elem, sizeof(T)) && Verify(elem, sizeof(T)); + } + + bool VerifyFromPointer(const uint8_t *const p, const size_t len) { + return Verify(static_cast(p - buf_), len); + } + + // Verify relative to a known-good base pointer. + bool VerifyFieldStruct(const uint8_t *const base, const voffset_t elem_off, + const size_t elem_len, const size_t align) const { + const auto f = static_cast(base - buf_) + elem_off; + return VerifyAlignment(f, align) && Verify(f, elem_len); + } + + template + bool VerifyField(const uint8_t *const base, const voffset_t elem_off, + const size_t align) const { + const auto f = static_cast(base - buf_) + elem_off; + return VerifyAlignment(f, align) && Verify(f, sizeof(T)); + } + + // Verify a pointer (may be NULL) of a table type. + template bool VerifyTable(const T *const table) { + return !table || table->Verify(*this); + } + + // Verify a pointer (may be NULL) of any vector type. + template bool VerifyVector(const Vector *const vec) const { + return !vec || VerifyVectorOrString(reinterpret_cast(vec), + sizeof(T)); + } + + // Verify a pointer (may be NULL) of a vector to struct. + template + bool VerifyVector(const Vector *const vec) const { + return VerifyVector(reinterpret_cast *>(vec)); + } + + // Verify a pointer (may be NULL) to string. + bool VerifyString(const String *const str) const { + size_t end; + return !str || (VerifyVectorOrString(reinterpret_cast(str), + 1, &end) && + Verify(end, 1) && // Must have terminator + Check(buf_[end] == '\0')); // Terminating byte must be 0. + } + + // Common code between vectors and strings. + bool VerifyVectorOrString(const uint8_t *const vec, const size_t elem_size, + size_t *const end = nullptr) const { + const auto veco = static_cast(vec - buf_); + // Check we can read the size field. + if (!Verify(veco)) return false; + // Check the whole array. If this is a string, the byte past the array + // must be 0. + const auto size = ReadScalar(vec); + const auto max_elems = FLATBUFFERS_MAX_BUFFER_SIZE / elem_size; + if (!Check(size < max_elems)) + return false; // Protect against byte_size overflowing. + const auto byte_size = sizeof(size) + elem_size * size; + if (end) *end = veco + byte_size; + return Verify(veco, byte_size); + } + + // Special case for string contents, after the above has been called. + bool VerifyVectorOfStrings(const Vector> *const vec) const { + if (vec) { + for (uoffset_t i = 0; i < vec->size(); i++) { + if (!VerifyString(vec->Get(i))) return false; + } + } + return true; + } + + // Special case for table contents, after the above has been called. + template + bool VerifyVectorOfTables(const Vector> *const vec) { + if (vec) { + for (uoffset_t i = 0; i < vec->size(); i++) { + if (!vec->Get(i)->Verify(*this)) return false; + } + } + return true; + } + + __supress_ubsan__("unsigned-integer-overflow") bool VerifyTableStart( + const uint8_t *const table) { + // Check the vtable offset. + const auto tableo = static_cast(table - buf_); + if (!Verify(tableo)) return false; + // This offset may be signed, but doing the subtraction unsigned always + // gives the result we want. + const auto vtableo = + tableo - static_cast(ReadScalar(table)); + // Check the vtable size field, then check vtable fits in its entirety. + if (!(VerifyComplexity() && Verify(vtableo) && + VerifyAlignment(ReadScalar(buf_ + vtableo), + sizeof(voffset_t)))) + return false; + const auto vsize = ReadScalar(buf_ + vtableo); + return Check((vsize & 1) == 0) && Verify(vtableo, vsize); + } + + template + bool VerifyBufferFromStart(const char *const identifier, const size_t start) { + // Buffers have to be of some size to be valid. The reason it is a runtime + // check instead of static_assert, is that nested flatbuffers go through + // this call and their size is determined at runtime. + if (!Check(size_ >= FLATBUFFERS_MIN_BUFFER_SIZE)) return false; + + // If an identifier is provided, check that we have a buffer + if (identifier && !Check((size_ >= 2 * sizeof(flatbuffers::uoffset_t) && + BufferHasIdentifier(buf_ + start, identifier)))) { + return false; + } + + // Call T::Verify, which must be in the generated code for this type. + const auto o = VerifyOffset(start); + return Check(o != 0) && + reinterpret_cast(buf_ + start + o)->Verify(*this) + // clang-format off + #ifdef FLATBUFFERS_TRACK_VERIFIER_BUFFER_SIZE + && GetComputedSize() + #endif + ; + // clang-format on + } + + template + bool VerifyNestedFlatBuffer(const Vector *const buf, + const char *const identifier) { + // An empty buffer is OK as it indicates not present. + if (!buf) return true; + + // If there is a nested buffer, it must be greater than the min size. + if(!Check(buf->size() >= FLATBUFFERS_MIN_BUFFER_SIZE)) return false; + + Verifier nested_verifier(buf->data(), buf->size()); + return nested_verifier.VerifyBuffer(identifier); + } + + // Verify this whole buffer, starting with root type T. + template bool VerifyBuffer() { return VerifyBuffer(nullptr); } + + template bool VerifyBuffer(const char *const identifier) { + return VerifyBufferFromStart(identifier, 0); + } + + template + bool VerifySizePrefixedBuffer(const char *const identifier) { + return Verify(0U) && + Check(ReadScalar(buf_) == size_ - sizeof(uoffset_t)) && + VerifyBufferFromStart(identifier, sizeof(uoffset_t)); + } + + uoffset_t VerifyOffset(const size_t start) const { + if (!Verify(start)) return 0; + const auto o = ReadScalar(buf_ + start); + // May not point to itself. + if (!Check(o != 0)) return 0; + // Can't wrap around / buffers are max 2GB. + if (!Check(static_cast(o) >= 0)) return 0; + // Must be inside the buffer to create a pointer from it (pointer outside + // buffer is UB). + if (!Verify(start + o, 1)) return 0; + return o; + } + + uoffset_t VerifyOffset(const uint8_t *const base, + const voffset_t start) const { + return VerifyOffset(static_cast(base - buf_) + start); + } + + // Called at the start of a table to increase counters measuring data + // structure depth and amount, and possibly bails out with false if + // limits set by the constructor have been hit. Needs to be balanced + // with EndTable(). + bool VerifyComplexity() { + depth_++; + num_tables_++; + return Check(depth_ <= max_depth_ && num_tables_ <= max_tables_); + } + + // Called at the end of a table to pop the depth count. + bool EndTable() { + depth_--; + return true; + } + + // Returns the message size in bytes + size_t GetComputedSize() const { + // clang-format off + #ifdef FLATBUFFERS_TRACK_VERIFIER_BUFFER_SIZE + uintptr_t size = upper_bound_; + // Align the size to uoffset_t + size = (size - 1 + sizeof(uoffset_t)) & ~(sizeof(uoffset_t) - 1); + return (size > size_) ? 0 : size; + #else + // Must turn on FLATBUFFERS_TRACK_VERIFIER_BUFFER_SIZE for this to work. + (void)upper_bound_; + FLATBUFFERS_ASSERT(false); + return 0; + #endif + // clang-format on + } + + std::vector *GetFlexReuseTracker() { return flex_reuse_tracker_; } + + void SetFlexReuseTracker(std::vector *const rt) { + flex_reuse_tracker_ = rt; + } + + private: + const uint8_t *buf_; + const size_t size_; + const uoffset_t max_depth_; + const uoffset_t max_tables_; + const bool check_alignment_; + + mutable size_t upper_bound_; + + uoffset_t depth_; + uoffset_t num_tables_; + std::vector *flex_reuse_tracker_; +}; + +} // namespace flatbuffers + +#endif // FLATBUFFERS_VERIFIER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h new file mode 100644 index 0000000..051a0ed --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flatbuffers.h @@ -0,0 +1,270 @@ +/* + * Copyright 2014 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_H_ +#define FLATBUFFERS_H_ + +// TODO: These includes are for mitigating the pains of users editing their +// source because they relied on flatbuffers.h to include everything for them. +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_array.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_buffer_ref.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_detached_buffer.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_flatbuffer_builder.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_stl_emulation.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_string.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_struct.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_table.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_vector_downward.h" +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_verifier.h" + +namespace flatbuffers { + +/// @brief This can compute the start of a FlatBuffer from a root pointer, i.e. +/// it is the opposite transformation of GetRoot(). +/// This may be useful if you want to pass on a root and have the recipient +/// delete the buffer afterwards. +inline const uint8_t *GetBufferStartFromRootPointer(const void *root) { + auto table = reinterpret_cast(root); + auto vtable = table->GetVTable(); + // Either the vtable is before the root or after the root. + auto start = (std::min)(vtable, reinterpret_cast(root)); + // Align to at least sizeof(uoffset_t). + start = reinterpret_cast(reinterpret_cast(start) & + ~(sizeof(uoffset_t) - 1)); + // Additionally, there may be a file_identifier in the buffer, and the root + // offset. The buffer may have been aligned to any size between + // sizeof(uoffset_t) and FLATBUFFERS_MAX_ALIGNMENT (see "force_align"). + // Sadly, the exact alignment is only known when constructing the buffer, + // since it depends on the presence of values with said alignment properties. + // So instead, we simply look at the next uoffset_t values (root, + // file_identifier, and alignment padding) to see which points to the root. + // None of the other values can "impersonate" the root since they will either + // be 0 or four ASCII characters. + static_assert(flatbuffers::kFileIdentifierLength == sizeof(uoffset_t), + "file_identifier is assumed to be the same size as uoffset_t"); + for (auto possible_roots = FLATBUFFERS_MAX_ALIGNMENT / sizeof(uoffset_t) + 1; + possible_roots; possible_roots--) { + start -= sizeof(uoffset_t); + if (ReadScalar(start) + start == + reinterpret_cast(root)) + return start; + } + // We didn't find the root, either the "root" passed isn't really a root, + // or the buffer is corrupt. + // Assert, because calling this function with bad data may cause reads + // outside of buffer boundaries. + FLATBUFFERS_ASSERT(false); + return nullptr; +} + +/// @brief This return the prefixed size of a FlatBuffer. +inline uoffset_t GetPrefixedSize(const uint8_t *buf) { + return ReadScalar(buf); +} + +// Base class for native objects (FlatBuffer data de-serialized into native +// C++ data structures). +// Contains no functionality, purely documentative. +struct NativeTable {}; + +/// @brief Function types to be used with resolving hashes into objects and +/// back again. The resolver gets a pointer to a field inside an object API +/// object that is of the type specified in the schema using the attribute +/// `cpp_type` (it is thus important whatever you write to this address +/// matches that type). The value of this field is initially null, so you +/// may choose to implement a delayed binding lookup using this function +/// if you wish. The resolver does the opposite lookup, for when the object +/// is being serialized again. +typedef uint64_t hash_value_t; +typedef std::function + resolver_function_t; +typedef std::function rehasher_function_t; + +// Helper function to test if a field is present, using any of the field +// enums in the generated code. +// `table` must be a generated table type. Since this is a template parameter, +// this is not typechecked to be a subclass of Table, so beware! +// Note: this function will return false for fields equal to the default +// value, since they're not stored in the buffer (unless force_defaults was +// used). +template +bool IsFieldPresent(const T *table, typename T::FlatBuffersVTableOffset field) { + // Cast, since Table is a private baseclass of any table types. + return reinterpret_cast(table)->CheckField( + static_cast(field)); +} + +// Utility function for reverse lookups on the EnumNames*() functions +// (in the generated C++ code) +// names must be NULL terminated. +inline int LookupEnum(const char **names, const char *name) { + for (const char **p = names; *p; p++) + if (!strcmp(*p, name)) return static_cast(p - names); + return -1; +} + +// These macros allow us to layout a struct with a guarantee that they'll end +// up looking the same on different compilers and platforms. +// It does this by disallowing the compiler to do any padding, and then +// does padding itself by inserting extra padding fields that make every +// element aligned to its own size. +// Additionally, it manually sets the alignment of the struct as a whole, +// which is typically its largest element, or a custom size set in the schema +// by the force_align attribute. +// These are used in the generated code only. + +// clang-format off +#if defined(_MSC_VER) + #define FLATBUFFERS_MANUALLY_ALIGNED_STRUCT(alignment) \ + __pragma(pack(1)) \ + struct __declspec(align(alignment)) + #define FLATBUFFERS_STRUCT_END(name, size) \ + __pragma(pack()) \ + static_assert(sizeof(name) == size, "compiler breaks packing rules") +#elif defined(__GNUC__) || defined(__clang__) || defined(__ICCARM__) + #define FLATBUFFERS_MANUALLY_ALIGNED_STRUCT(alignment) \ + _Pragma("pack(1)") \ + struct __attribute__((aligned(alignment))) + #define FLATBUFFERS_STRUCT_END(name, size) \ + _Pragma("pack()") \ + static_assert(sizeof(name) == size, "compiler breaks packing rules") +#else + #error Unknown compiler, please define structure alignment macros +#endif +// clang-format on + +// Minimal reflection via code generation. +// Besides full-fat reflection (see reflection.h) and parsing/printing by +// loading schemas (see idl.h), we can also have code generation for minimal +// reflection data which allows pretty-printing and other uses without needing +// a schema or a parser. +// Generate code with --reflect-types (types only) or --reflect-names (names +// also) to enable. +// See minireflect.h for utilities using this functionality. + +// These types are organized slightly differently as the ones in idl.h. +enum SequenceType { ST_TABLE, ST_STRUCT, ST_UNION, ST_ENUM }; + +// Scalars have the same order as in idl.h +// clang-format off +#define FLATBUFFERS_GEN_ELEMENTARY_TYPES(ET) \ + ET(ET_UTYPE) \ + ET(ET_BOOL) \ + ET(ET_CHAR) \ + ET(ET_UCHAR) \ + ET(ET_SHORT) \ + ET(ET_USHORT) \ + ET(ET_INT) \ + ET(ET_UINT) \ + ET(ET_LONG) \ + ET(ET_ULONG) \ + ET(ET_FLOAT) \ + ET(ET_DOUBLE) \ + ET(ET_STRING) \ + ET(ET_SEQUENCE) // See SequenceType. + +enum ElementaryType { + #define FLATBUFFERS_ET(E) E, + FLATBUFFERS_GEN_ELEMENTARY_TYPES(FLATBUFFERS_ET) + #undef FLATBUFFERS_ET +}; + +inline const char * const *ElementaryTypeNames() { + static const char * const names[] = { + #define FLATBUFFERS_ET(E) #E, + FLATBUFFERS_GEN_ELEMENTARY_TYPES(FLATBUFFERS_ET) + #undef FLATBUFFERS_ET + }; + return names; +} +// clang-format on + +// Basic type info cost just 16bits per field! +// We're explicitly defining the signedness since the signedness of integer +// bitfields is otherwise implementation-defined and causes warnings on older +// GCC compilers. +struct TypeCode { + // ElementaryType + unsigned short base_type : 4; + // Either vector (in table) or array (in struct) + unsigned short is_repeating : 1; + // Index into type_refs below, or -1 for none. + signed short sequence_ref : 11; +}; + +static_assert(sizeof(TypeCode) == 2, "TypeCode"); + +struct TypeTable; + +// Signature of the static method present in each type. +typedef const TypeTable *(*TypeFunction)(); + +struct TypeTable { + SequenceType st; + size_t num_elems; // of type_codes, values, names (but not type_refs). + const TypeCode *type_codes; // num_elems count + const TypeFunction *type_refs; // less than num_elems entries (see TypeCode). + const int16_t *array_sizes; // less than num_elems entries (see TypeCode). + const int64_t *values; // Only set for non-consecutive enum/union or structs. + const char *const *names; // Only set if compiled with --reflect-names. +}; + +// String which identifies the current version of FlatBuffers. +inline const char *flatbuffers_version_string() { + return "FlatBuffers " FLATBUFFERS_STRING(FLATBUFFERS_VERSION_MAJOR) "." + FLATBUFFERS_STRING(FLATBUFFERS_VERSION_MINOR) "." + FLATBUFFERS_STRING(FLATBUFFERS_VERSION_REVISION); +} + +// clang-format off +#define FLATBUFFERS_DEFINE_BITMASK_OPERATORS(E, T)\ + inline E operator | (E lhs, E rhs){\ + return E(T(lhs) | T(rhs));\ + }\ + inline E operator & (E lhs, E rhs){\ + return E(T(lhs) & T(rhs));\ + }\ + inline E operator ^ (E lhs, E rhs){\ + return E(T(lhs) ^ T(rhs));\ + }\ + inline E operator ~ (E lhs){\ + return E(~T(lhs));\ + }\ + inline E operator |= (E &lhs, E rhs){\ + lhs = lhs | rhs;\ + return lhs;\ + }\ + inline E operator &= (E &lhs, E rhs){\ + lhs = lhs & rhs;\ + return lhs;\ + }\ + inline E operator ^= (E &lhs, E rhs){\ + lhs = lhs ^ rhs;\ + return lhs;\ + }\ + inline bool operator !(E rhs) \ + {\ + return !bool(T(rhs)); \ + } +/// @endcond +} // namespace flatbuffers + +// clang-format on + +#endif // FLATBUFFERS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h new file mode 100644 index 0000000..7930949 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/flexbuffers.h @@ -0,0 +1,1903 @@ +/* + * Copyright 2017 Google Inc. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef FLATBUFFERS_FLEXBUFFERS_H_ +#define FLATBUFFERS_FLEXBUFFERS_H_ + +#include +// Used to select STL variant. +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_base.h" +// We use the basic binary writing functions from the regular FlatBuffers. +#include "edge-impulse-sdk/third_party/flatbuffers/include/flatbuffers/fb_util.h" + +#ifdef _MSC_VER +# include +#endif + +#if defined(_MSC_VER) +# pragma warning(push) +# pragma warning(disable : 4127) // C4127: conditional expression is constant +#endif + +namespace flexbuffers { + +class Reference; +class Map; + +// These are used in the lower 2 bits of a type field to determine the size of +// the elements (and or size field) of the item pointed to (e.g. vector). +enum BitWidth { + BIT_WIDTH_8 = 0, + BIT_WIDTH_16 = 1, + BIT_WIDTH_32 = 2, + BIT_WIDTH_64 = 3, +}; + +// These are used as the upper 6 bits of a type field to indicate the actual +// type. +enum Type { + FBT_NULL = 0, + FBT_INT = 1, + FBT_UINT = 2, + FBT_FLOAT = 3, + // Types above stored inline, types below (except FBT_BOOL) store an offset. + FBT_KEY = 4, + FBT_STRING = 5, + FBT_INDIRECT_INT = 6, + FBT_INDIRECT_UINT = 7, + FBT_INDIRECT_FLOAT = 8, + FBT_MAP = 9, + FBT_VECTOR = 10, // Untyped. + FBT_VECTOR_INT = 11, // Typed any size (stores no type table). + FBT_VECTOR_UINT = 12, + FBT_VECTOR_FLOAT = 13, + FBT_VECTOR_KEY = 14, + // DEPRECATED, use FBT_VECTOR or FBT_VECTOR_KEY instead. + // Read test.cpp/FlexBuffersDeprecatedTest() for details on why. + FBT_VECTOR_STRING_DEPRECATED = 15, + FBT_VECTOR_INT2 = 16, // Typed tuple (no type table, no size field). + FBT_VECTOR_UINT2 = 17, + FBT_VECTOR_FLOAT2 = 18, + FBT_VECTOR_INT3 = 19, // Typed triple (no type table, no size field). + FBT_VECTOR_UINT3 = 20, + FBT_VECTOR_FLOAT3 = 21, + FBT_VECTOR_INT4 = 22, // Typed quad (no type table, no size field). + FBT_VECTOR_UINT4 = 23, + FBT_VECTOR_FLOAT4 = 24, + FBT_BLOB = 25, + FBT_BOOL = 26, + FBT_VECTOR_BOOL = + 36, // To Allow the same type of conversion of type to vector type + + FBT_MAX_TYPE = 37 +}; + +inline bool IsInline(Type t) { return t <= FBT_FLOAT || t == FBT_BOOL; } + +inline bool IsTypedVectorElementType(Type t) { + return (t >= FBT_INT && t <= FBT_STRING) || t == FBT_BOOL; +} + +inline bool IsTypedVector(Type t) { + return (t >= FBT_VECTOR_INT && t <= FBT_VECTOR_STRING_DEPRECATED) || + t == FBT_VECTOR_BOOL; +} + +inline bool IsFixedTypedVector(Type t) { + return t >= FBT_VECTOR_INT2 && t <= FBT_VECTOR_FLOAT4; +} + +inline Type ToTypedVector(Type t, size_t fixed_len = 0) { + FLATBUFFERS_ASSERT(IsTypedVectorElementType(t)); + switch (fixed_len) { + case 0: return static_cast(t - FBT_INT + FBT_VECTOR_INT); + case 2: return static_cast(t - FBT_INT + FBT_VECTOR_INT2); + case 3: return static_cast(t - FBT_INT + FBT_VECTOR_INT3); + case 4: return static_cast(t - FBT_INT + FBT_VECTOR_INT4); + default: FLATBUFFERS_ASSERT(0); return FBT_NULL; + } +} + +inline Type ToTypedVectorElementType(Type t) { + FLATBUFFERS_ASSERT(IsTypedVector(t)); + return static_cast(t - FBT_VECTOR_INT + FBT_INT); +} + +inline Type ToFixedTypedVectorElementType(Type t, uint8_t *len) { + FLATBUFFERS_ASSERT(IsFixedTypedVector(t)); + auto fixed_type = t - FBT_VECTOR_INT2; + *len = static_cast(fixed_type / 3 + + 2); // 3 types each, starting from length 2. + return static_cast(fixed_type % 3 + FBT_INT); +} + +// TODO: implement proper support for 8/16bit floats, or decide not to +// support them. +typedef int16_t half; +typedef int8_t quarter; + +// TODO: can we do this without conditionals using intrinsics or inline asm +// on some platforms? Given branch prediction the method below should be +// decently quick, but it is the most frequently executed function. +// We could do an (unaligned) 64-bit read if we ifdef out the platforms for +// which that doesn't work (or where we'd read into un-owned memory). +template +R ReadSizedScalar(const uint8_t *data, uint8_t byte_width) { + return byte_width < 4 + ? (byte_width < 2 + ? static_cast(flatbuffers::ReadScalar(data)) + : static_cast(flatbuffers::ReadScalar(data))) + : (byte_width < 8 + ? static_cast(flatbuffers::ReadScalar(data)) + : static_cast(flatbuffers::ReadScalar(data))); +} + +inline int64_t ReadInt64(const uint8_t *data, uint8_t byte_width) { + return ReadSizedScalar( + data, byte_width); +} + +inline uint64_t ReadUInt64(const uint8_t *data, uint8_t byte_width) { + // This is the "hottest" function (all offset lookups use this), so worth + // optimizing if possible. + // TODO: GCC apparently replaces memcpy by a rep movsb, but only if count is a + // constant, which here it isn't. Test if memcpy is still faster than + // the conditionals in ReadSizedScalar. Can also use inline asm. + + // clang-format off + #if defined(_MSC_VER) && defined(_M_X64) && !defined(_M_ARM64EC) + // This is 64-bit Windows only, __movsb does not work on 32-bit Windows. + uint64_t u = 0; + __movsb(reinterpret_cast(&u), + reinterpret_cast(data), byte_width); + return flatbuffers::EndianScalar(u); + #else + return ReadSizedScalar( + data, byte_width); + #endif + // clang-format on +} + +inline double ReadDouble(const uint8_t *data, uint8_t byte_width) { + return ReadSizedScalar(data, + byte_width); +} + +inline const uint8_t *Indirect(const uint8_t *offset, uint8_t byte_width) { + return offset - ReadUInt64(offset, byte_width); +} + +template const uint8_t *Indirect(const uint8_t *offset) { + return offset - flatbuffers::ReadScalar(offset); +} + +inline BitWidth WidthU(uint64_t u) { +#define FLATBUFFERS_GET_FIELD_BIT_WIDTH(value, width) \ + { \ + if (!((u) & ~((1ULL << (width)) - 1ULL))) return BIT_WIDTH_##width; \ + } + FLATBUFFERS_GET_FIELD_BIT_WIDTH(u, 8); + FLATBUFFERS_GET_FIELD_BIT_WIDTH(u, 16); + FLATBUFFERS_GET_FIELD_BIT_WIDTH(u, 32); +#undef FLATBUFFERS_GET_FIELD_BIT_WIDTH + return BIT_WIDTH_64; +} + +inline BitWidth WidthI(int64_t i) { + auto u = static_cast(i) << 1; + return WidthU(i >= 0 ? u : ~u); +} + +inline BitWidth WidthF(double f) { + return static_cast(static_cast(f)) == f ? BIT_WIDTH_32 + : BIT_WIDTH_64; +} + +// Base class of all types below. +// Points into the data buffer and allows access to one type. +class Object { + public: + Object(const uint8_t *data, uint8_t byte_width) + : data_(data), byte_width_(byte_width) {} + + protected: + const uint8_t *data_; + uint8_t byte_width_; +}; + +// Object that has a size, obtained either from size prefix, or elsewhere. +class Sized : public Object { + public: + // Size prefix. + Sized(const uint8_t *data, uint8_t byte_width) + : Object(data, byte_width), size_(read_size()) {} + // Manual size. + Sized(const uint8_t *data, uint8_t byte_width, size_t sz) + : Object(data, byte_width), size_(sz) {} + size_t size() const { return size_; } + // Access size stored in `byte_width_` bytes before data_ pointer. + size_t read_size() const { + return static_cast(ReadUInt64(data_ - byte_width_, byte_width_)); + } + + protected: + size_t size_; +}; + +class String : public Sized { + public: + // Size prefix. + String(const uint8_t *data, uint8_t byte_width) : Sized(data, byte_width) {} + // Manual size. + String(const uint8_t *data, uint8_t byte_width, size_t sz) + : Sized(data, byte_width, sz) {} + + size_t length() const { return size(); } + const char *c_str() const { return reinterpret_cast(data_); } + std::string str() const { return std::string(c_str(), size()); } + + static String EmptyString() { + static const char *empty_string = ""; + return String(reinterpret_cast(empty_string), 1, 0); + } + bool IsTheEmptyString() const { return data_ == EmptyString().data_; } +}; + +class Blob : public Sized { + public: + Blob(const uint8_t *data_buf, uint8_t byte_width) + : Sized(data_buf, byte_width) {} + + static Blob EmptyBlob() { + static const uint8_t empty_blob[] = { 0 /*len*/ }; + return Blob(empty_blob + 1, 1); + } + bool IsTheEmptyBlob() const { return data_ == EmptyBlob().data_; } + const uint8_t *data() const { return data_; } +}; + +class Vector : public Sized { + public: + Vector(const uint8_t *data, uint8_t byte_width) : Sized(data, byte_width) {} + + Reference operator[](size_t i) const; + + static Vector EmptyVector() { + static const uint8_t empty_vector[] = { 0 /*len*/ }; + return Vector(empty_vector + 1, 1); + } + bool IsTheEmptyVector() const { return data_ == EmptyVector().data_; } +}; + +class TypedVector : public Sized { + public: + TypedVector(const uint8_t *data, uint8_t byte_width, Type element_type) + : Sized(data, byte_width), type_(element_type) {} + + Reference operator[](size_t i) const; + + static TypedVector EmptyTypedVector() { + static const uint8_t empty_typed_vector[] = { 0 /*len*/ }; + return TypedVector(empty_typed_vector + 1, 1, FBT_INT); + } + bool IsTheEmptyVector() const { + return data_ == TypedVector::EmptyTypedVector().data_; + } + + Type ElementType() { return type_; } + + friend Reference; + + private: + Type type_; + + friend Map; +}; + +class FixedTypedVector : public Object { + public: + FixedTypedVector(const uint8_t *data, uint8_t byte_width, Type element_type, + uint8_t len) + : Object(data, byte_width), type_(element_type), len_(len) {} + + Reference operator[](size_t i) const; + + static FixedTypedVector EmptyFixedTypedVector() { + static const uint8_t fixed_empty_vector[] = { 0 /* unused */ }; + return FixedTypedVector(fixed_empty_vector, 1, FBT_INT, 0); + } + bool IsTheEmptyFixedTypedVector() const { + return data_ == FixedTypedVector::EmptyFixedTypedVector().data_; + } + + Type ElementType() const { return type_; } + uint8_t size() const { return len_; } + + private: + Type type_; + uint8_t len_; +}; + +class Map : public Vector { + public: + Map(const uint8_t *data, uint8_t byte_width) : Vector(data, byte_width) {} + + Reference operator[](const char *key) const; + Reference operator[](const std::string &key) const; + + Vector Values() const { return Vector(data_, byte_width_); } + + TypedVector Keys() const { + const size_t num_prefixed_fields = 3; + auto keys_offset = data_ - byte_width_ * num_prefixed_fields; + return TypedVector(Indirect(keys_offset, byte_width_), + static_cast( + ReadUInt64(keys_offset + byte_width_, byte_width_)), + FBT_KEY); + } + + static Map EmptyMap() { + static const uint8_t empty_map[] = { + 0 /*keys_len*/, 0 /*keys_offset*/, 1 /*keys_width*/, 0 /*len*/ + }; + return Map(empty_map + 4, 1); + } + + bool IsTheEmptyMap() const { return data_ == EmptyMap().data_; } +}; + +template +void AppendToString(std::string &s, T &&v, bool keys_quoted) { + s += "[ "; + for (size_t i = 0; i < v.size(); i++) { + if (i) s += ", "; + v[i].ToString(true, keys_quoted, s); + } + s += " ]"; +} + +class Reference { + public: + Reference() + : data_(nullptr), parent_width_(0), byte_width_(0), type_(FBT_NULL) {} + + Reference(const uint8_t *data, uint8_t parent_width, uint8_t byte_width, + Type type) + : data_(data), + parent_width_(parent_width), + byte_width_(byte_width), + type_(type) {} + + Reference(const uint8_t *data, uint8_t parent_width, uint8_t packed_type) + : data_(data), parent_width_(parent_width) { + byte_width_ = 1U << static_cast(packed_type & 3); + type_ = static_cast(packed_type >> 2); + } + + Type GetType() const { return type_; } + + bool IsNull() const { return type_ == FBT_NULL; } + bool IsBool() const { return type_ == FBT_BOOL; } + bool IsInt() const { return type_ == FBT_INT || type_ == FBT_INDIRECT_INT; } + bool IsUInt() const { + return type_ == FBT_UINT || type_ == FBT_INDIRECT_UINT; + } + bool IsIntOrUint() const { return IsInt() || IsUInt(); } + bool IsFloat() const { + return type_ == FBT_FLOAT || type_ == FBT_INDIRECT_FLOAT; + } + bool IsNumeric() const { return IsIntOrUint() || IsFloat(); } + bool IsString() const { return type_ == FBT_STRING; } + bool IsKey() const { return type_ == FBT_KEY; } + bool IsVector() const { return type_ == FBT_VECTOR || type_ == FBT_MAP; } + bool IsUntypedVector() const { return type_ == FBT_VECTOR; } + bool IsTypedVector() const { return flexbuffers::IsTypedVector(type_); } + bool IsFixedTypedVector() const { + return flexbuffers::IsFixedTypedVector(type_); + } + bool IsAnyVector() const { + return (IsTypedVector() || IsFixedTypedVector() || IsVector()); + } + bool IsMap() const { return type_ == FBT_MAP; } + bool IsBlob() const { return type_ == FBT_BLOB; } + bool AsBool() const { + return (type_ == FBT_BOOL ? ReadUInt64(data_, parent_width_) + : AsUInt64()) != 0; + } + + // Reads any type as a int64_t. Never fails, does most sensible conversion. + // Truncates floats, strings are attempted to be parsed for a number, + // vectors/maps return their size. Returns 0 if all else fails. + int64_t AsInt64() const { + if (type_ == FBT_INT) { + // A fast path for the common case. + return ReadInt64(data_, parent_width_); + } else + switch (type_) { + case FBT_INDIRECT_INT: return ReadInt64(Indirect(), byte_width_); + case FBT_UINT: return ReadUInt64(data_, parent_width_); + case FBT_INDIRECT_UINT: return ReadUInt64(Indirect(), byte_width_); + case FBT_FLOAT: + return static_cast(ReadDouble(data_, parent_width_)); + case FBT_INDIRECT_FLOAT: + return static_cast(ReadDouble(Indirect(), byte_width_)); + case FBT_NULL: return 0; + case FBT_STRING: return flatbuffers::StringToInt(AsString().c_str()); + case FBT_VECTOR: return static_cast(AsVector().size()); + case FBT_BOOL: return ReadInt64(data_, parent_width_); + default: + // Convert other things to int. + return 0; + } + } + + // TODO: could specialize these to not use AsInt64() if that saves + // extension ops in generated code, and use a faster op than ReadInt64. + int32_t AsInt32() const { return static_cast(AsInt64()); } + int16_t AsInt16() const { return static_cast(AsInt64()); } + int8_t AsInt8() const { return static_cast(AsInt64()); } + + uint64_t AsUInt64() const { + if (type_ == FBT_UINT) { + // A fast path for the common case. + return ReadUInt64(data_, parent_width_); + } else + switch (type_) { + case FBT_INDIRECT_UINT: return ReadUInt64(Indirect(), byte_width_); + case FBT_INT: return ReadInt64(data_, parent_width_); + case FBT_INDIRECT_INT: return ReadInt64(Indirect(), byte_width_); + case FBT_FLOAT: + return static_cast(ReadDouble(data_, parent_width_)); + case FBT_INDIRECT_FLOAT: + return static_cast(ReadDouble(Indirect(), byte_width_)); + case FBT_NULL: return 0; + case FBT_STRING: return flatbuffers::StringToUInt(AsString().c_str()); + case FBT_VECTOR: return static_cast(AsVector().size()); + case FBT_BOOL: return ReadUInt64(data_, parent_width_); + default: + // Convert other things to uint. + return 0; + } + } + + uint32_t AsUInt32() const { return static_cast(AsUInt64()); } + uint16_t AsUInt16() const { return static_cast(AsUInt64()); } + uint8_t AsUInt8() const { return static_cast(AsUInt64()); } + + double AsDouble() const { + if (type_ == FBT_FLOAT) { + // A fast path for the common case. + return ReadDouble(data_, parent_width_); + } else + switch (type_) { + case FBT_INDIRECT_FLOAT: return ReadDouble(Indirect(), byte_width_); + case FBT_INT: + return static_cast(ReadInt64(data_, parent_width_)); + case FBT_UINT: + return static_cast(ReadUInt64(data_, parent_width_)); + case FBT_INDIRECT_INT: + return static_cast(ReadInt64(Indirect(), byte_width_)); + case FBT_INDIRECT_UINT: + return static_cast(ReadUInt64(Indirect(), byte_width_)); + case FBT_NULL: return 0.0; + case FBT_STRING: { +#if 1 +#if !defined( _MSC_VER) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wnull-dereference" +#endif + // See b/173239141 for additional context. Patched via + // micro/tools/make/flexbuffers_download.sh + // Introduce a segfault for an unsupported code path for TFLM. + return *(static_cast(nullptr)); +#if !defined( _MSC_VER) +#pragma GCC diagnostic pop +#endif +#else + // This is the original code + double d; + flatbuffers::StringToNumber(AsString().c_str(), &d); + return d; +#endif + } + case FBT_VECTOR: return static_cast(AsVector().size()); + case FBT_BOOL: + return static_cast(ReadUInt64(data_, parent_width_)); + default: + // Convert strings and other things to float. + return 0; + } + } + + float AsFloat() const { return static_cast(AsDouble()); } + + const char *AsKey() const { + if (type_ == FBT_KEY || type_ == FBT_STRING) { + return reinterpret_cast(Indirect()); + } else { + return ""; + } + } + + // This function returns the empty string if you try to read something that + // is not a string or key. + String AsString() const { + if (type_ == FBT_STRING) { + return String(Indirect(), byte_width_); + } else if (type_ == FBT_KEY) { + auto key = Indirect(); + return String(key, byte_width_, + strlen(reinterpret_cast(key))); + } else { + return String::EmptyString(); + } + } + + // Unlike AsString(), this will convert any type to a std::string. + std::string ToString() const { + std::string s; + ToString(false, false, s); + return s; + } + + // Convert any type to a JSON-like string. strings_quoted determines if + // string values at the top level receive "" quotes (inside other values + // they always do). keys_quoted determines if keys are quoted, at any level. + // TODO(wvo): add further options to have indentation/newlines. + void ToString(bool strings_quoted, bool keys_quoted, std::string &s) const { + if (type_ == FBT_STRING) { + String str(Indirect(), byte_width_); + if (strings_quoted) { + flatbuffers::EscapeString(str.c_str(), str.length(), &s, true, false); + } else { + s.append(str.c_str(), str.length()); + } + } else if (IsKey()) { + auto str = AsKey(); + if (keys_quoted) { + flatbuffers::EscapeString(str, strlen(str), &s, true, false); + } else { + s += str; + } + } else if (IsInt()) { + s += flatbuffers::NumToString(AsInt64()); + } else if (IsUInt()) { + s += flatbuffers::NumToString(AsUInt64()); + } else if (IsFloat()) { + s += flatbuffers::NumToString(AsDouble()); + } else if (IsNull()) { + s += "null"; + } else if (IsBool()) { + s += AsBool() ? "true" : "false"; + } else if (IsMap()) { + s += "{ "; + auto m = AsMap(); + auto keys = m.Keys(); + auto vals = m.Values(); + for (size_t i = 0; i < keys.size(); i++) { + bool kq = keys_quoted; + if (!kq) { + // FlexBuffers keys may contain arbitrary characters, only allow + // unquoted if it looks like an "identifier": + const char *p = keys[i].AsKey(); + if (!flatbuffers::is_alpha(*p) && *p != '_') { + kq = true; + } else { + while (*++p) { + if (!flatbuffers::is_alnum(*p) && *p != '_') { + kq = true; + break; + } + } + } + } + keys[i].ToString(true, kq, s); + s += ": "; + vals[i].ToString(true, keys_quoted, s); + if (i < keys.size() - 1) s += ", "; + } + s += " }"; + } else if (IsVector()) { + AppendToString(s, AsVector(), keys_quoted); + } else if (IsTypedVector()) { + AppendToString(s, AsTypedVector(), keys_quoted); + } else if (IsFixedTypedVector()) { + AppendToString(s, AsFixedTypedVector(), keys_quoted); + } else if (IsBlob()) { + auto blob = AsBlob(); + flatbuffers::EscapeString(reinterpret_cast(blob.data()), + blob.size(), &s, true, false); + } else { + s += "(?)"; + } + } + + // This function returns the empty blob if you try to read a not-blob. + // Strings can be viewed as blobs too. + Blob AsBlob() const { + if (type_ == FBT_BLOB || type_ == FBT_STRING) { + return Blob(Indirect(), byte_width_); + } else { + return Blob::EmptyBlob(); + } + } + + // This function returns the empty vector if you try to read a not-vector. + // Maps can be viewed as vectors too. + Vector AsVector() const { + if (type_ == FBT_VECTOR || type_ == FBT_MAP) { + return Vector(Indirect(), byte_width_); + } else { + return Vector::EmptyVector(); + } + } + + TypedVector AsTypedVector() const { + if (IsTypedVector()) { + auto tv = + TypedVector(Indirect(), byte_width_, ToTypedVectorElementType(type_)); + if (tv.type_ == FBT_STRING) { + // These can't be accessed as strings, since we don't know the bit-width + // of the size field, see the declaration of + // FBT_VECTOR_STRING_DEPRECATED above for details. + // We change the type here to be keys, which are a subtype of strings, + // and will ignore the size field. This will truncate strings with + // embedded nulls. + tv.type_ = FBT_KEY; + } + return tv; + } else { + return TypedVector::EmptyTypedVector(); + } + } + + FixedTypedVector AsFixedTypedVector() const { + if (IsFixedTypedVector()) { + uint8_t len = 0; + auto vtype = ToFixedTypedVectorElementType(type_, &len); + return FixedTypedVector(Indirect(), byte_width_, vtype, len); + } else { + return FixedTypedVector::EmptyFixedTypedVector(); + } + } + + Map AsMap() const { + if (type_ == FBT_MAP) { + return Map(Indirect(), byte_width_); + } else { + return Map::EmptyMap(); + } + } + + template T As() const; + + // Experimental: Mutation functions. + // These allow scalars in an already created buffer to be updated in-place. + // Since by default scalars are stored in the smallest possible space, + // the new value may not fit, in which case these functions return false. + // To avoid this, you can construct the values you intend to mutate using + // Builder::ForceMinimumBitWidth. + bool MutateInt(int64_t i) { + if (type_ == FBT_INT) { + return Mutate(data_, i, parent_width_, WidthI(i)); + } else if (type_ == FBT_INDIRECT_INT) { + return Mutate(Indirect(), i, byte_width_, WidthI(i)); + } else if (type_ == FBT_UINT) { + auto u = static_cast(i); + return Mutate(data_, u, parent_width_, WidthU(u)); + } else if (type_ == FBT_INDIRECT_UINT) { + auto u = static_cast(i); + return Mutate(Indirect(), u, byte_width_, WidthU(u)); + } else { + return false; + } + } + + bool MutateBool(bool b) { + return type_ == FBT_BOOL && Mutate(data_, b, parent_width_, BIT_WIDTH_8); + } + + bool MutateUInt(uint64_t u) { + if (type_ == FBT_UINT) { + return Mutate(data_, u, parent_width_, WidthU(u)); + } else if (type_ == FBT_INDIRECT_UINT) { + return Mutate(Indirect(), u, byte_width_, WidthU(u)); + } else if (type_ == FBT_INT) { + auto i = static_cast(u); + return Mutate(data_, i, parent_width_, WidthI(i)); + } else if (type_ == FBT_INDIRECT_INT) { + auto i = static_cast(u); + return Mutate(Indirect(), i, byte_width_, WidthI(i)); + } else { + return false; + } + } + + bool MutateFloat(float f) { + if (type_ == FBT_FLOAT) { + return MutateF(data_, f, parent_width_, BIT_WIDTH_32); + } else if (type_ == FBT_INDIRECT_FLOAT) { + return MutateF(Indirect(), f, byte_width_, BIT_WIDTH_32); + } else { + return false; + } + } + + bool MutateFloat(double d) { + if (type_ == FBT_FLOAT) { + return MutateF(data_, d, parent_width_, WidthF(d)); + } else if (type_ == FBT_INDIRECT_FLOAT) { + return MutateF(Indirect(), d, byte_width_, WidthF(d)); + } else { + return false; + } + } + + bool MutateString(const char *str, size_t len) { + auto s = AsString(); + if (s.IsTheEmptyString()) return false; + // This is very strict, could allow shorter strings, but that creates + // garbage. + if (s.length() != len) return false; + memcpy(const_cast(s.c_str()), str, len); + return true; + } + bool MutateString(const char *str) { return MutateString(str, strlen(str)); } + bool MutateString(const std::string &str) { + return MutateString(str.data(), str.length()); + } + + private: + const uint8_t *Indirect() const { + return flexbuffers::Indirect(data_, parent_width_); + } + + template + bool Mutate(const uint8_t *dest, T t, size_t byte_width, + BitWidth value_width) { + auto fits = static_cast(static_cast(1U) << value_width) <= + byte_width; + if (fits) { + t = flatbuffers::EndianScalar(t); + memcpy(const_cast(dest), &t, byte_width); + } + return fits; + } + + template + bool MutateF(const uint8_t *dest, T t, size_t byte_width, + BitWidth value_width) { + if (byte_width == sizeof(double)) + return Mutate(dest, static_cast(t), byte_width, value_width); + if (byte_width == sizeof(float)) + return Mutate(dest, static_cast(t), byte_width, value_width); + FLATBUFFERS_ASSERT(false); + return false; + } + + friend class Verifier; + + const uint8_t *data_; + uint8_t parent_width_; + uint8_t byte_width_; + Type type_; +}; + +// Template specialization for As(). +template<> inline bool Reference::As() const { return AsBool(); } + +template<> inline int8_t Reference::As() const { return AsInt8(); } +template<> inline int16_t Reference::As() const { return AsInt16(); } +template<> inline int32_t Reference::As() const { return AsInt32(); } +template<> inline int64_t Reference::As() const { return AsInt64(); } + +template<> inline uint8_t Reference::As() const { return AsUInt8(); } +template<> inline uint16_t Reference::As() const { + return AsUInt16(); +} +template<> inline uint32_t Reference::As() const { + return AsUInt32(); +} +template<> inline uint64_t Reference::As() const { + return AsUInt64(); +} + +template<> inline double Reference::As() const { return AsDouble(); } +template<> inline float Reference::As() const { return AsFloat(); } + +template<> inline String Reference::As() const { return AsString(); } +template<> inline std::string Reference::As() const { + return AsString().str(); +} + +template<> inline Blob Reference::As() const { return AsBlob(); } +template<> inline Vector Reference::As() const { return AsVector(); } +template<> inline TypedVector Reference::As() const { + return AsTypedVector(); +} +template<> inline FixedTypedVector Reference::As() const { + return AsFixedTypedVector(); +} +template<> inline Map Reference::As() const { return AsMap(); } + +inline uint8_t PackedType(BitWidth bit_width, Type type) { + return static_cast(bit_width | (type << 2)); +} + +inline uint8_t NullPackedType() { return PackedType(BIT_WIDTH_8, FBT_NULL); } + +// Vector accessors. +// Note: if you try to access outside of bounds, you get a Null value back +// instead. Normally this would be an assert, but since this is "dynamically +// typed" data, you may not want that (someone sends you a 2d vector and you +// wanted 3d). +// The Null converts seamlessly into a default value for any other type. +// TODO(wvo): Could introduce an #ifdef that makes this into an assert? +inline Reference Vector::operator[](size_t i) const { + auto len = size(); + if (i >= len) return Reference(nullptr, 1, NullPackedType()); + auto packed_type = (data_ + len * byte_width_)[i]; + auto elem = data_ + i * byte_width_; + return Reference(elem, byte_width_, packed_type); +} + +inline Reference TypedVector::operator[](size_t i) const { + auto len = size(); + if (i >= len) return Reference(nullptr, 1, NullPackedType()); + auto elem = data_ + i * byte_width_; + return Reference(elem, byte_width_, 1, type_); +} + +inline Reference FixedTypedVector::operator[](size_t i) const { + if (i >= len_) return Reference(nullptr, 1, NullPackedType()); + auto elem = data_ + i * byte_width_; + return Reference(elem, byte_width_, 1, type_); +} + +template int KeyCompare(const void *key, const void *elem) { + auto str_elem = reinterpret_cast( + Indirect(reinterpret_cast(elem))); + auto skey = reinterpret_cast(key); + return strcmp(skey, str_elem); +} + +inline Reference Map::operator[](const char *key) const { + auto keys = Keys(); + // We can't pass keys.byte_width_ to the comparison function, so we have + // to pick the right one ahead of time. + int (*comp)(const void *, const void *) = nullptr; + switch (keys.byte_width_) { + case 1: comp = KeyCompare; break; + case 2: comp = KeyCompare; break; + case 4: comp = KeyCompare; break; + case 8: comp = KeyCompare; break; + default: FLATBUFFERS_ASSERT(false); return Reference(); + } + auto res = std::bsearch(key, keys.data_, keys.size(), keys.byte_width_, comp); + if (!res) return Reference(nullptr, 1, NullPackedType()); + auto i = (reinterpret_cast(res) - keys.data_) / keys.byte_width_; + return (*static_cast(this))[i]; +} + +inline Reference Map::operator[](const std::string &key) const { + return (*this)[key.c_str()]; +} + +inline Reference GetRoot(const uint8_t *buffer, size_t size) { + // See Finish() below for the serialization counterpart of this. + // The root starts at the end of the buffer, so we parse backwards from there. + auto end = buffer + size; + auto byte_width = *--end; + auto packed_type = *--end; + end -= byte_width; // The root data item. + return Reference(end, byte_width, packed_type); +} + +inline Reference GetRoot(const std::vector &buffer) { + return GetRoot(buffer.data(), buffer.size()); +} + +// Flags that configure how the Builder behaves. +// The "Share" flags determine if the Builder automatically tries to pool +// this type. Pooling can reduce the size of serialized data if there are +// multiple maps of the same kind, at the expense of slightly slower +// serialization (the cost of lookups) and more memory use (std::set). +// By default this is on for keys, but off for strings. +// Turn keys off if you have e.g. only one map. +// Turn strings on if you expect many non-unique string values. +// Additionally, sharing key vectors can save space if you have maps with +// identical field populations. +enum BuilderFlag { + BUILDER_FLAG_NONE = 0, + BUILDER_FLAG_SHARE_KEYS = 1, + BUILDER_FLAG_SHARE_STRINGS = 2, + BUILDER_FLAG_SHARE_KEYS_AND_STRINGS = 3, + BUILDER_FLAG_SHARE_KEY_VECTORS = 4, + BUILDER_FLAG_SHARE_ALL = 7, +}; + +class Builder FLATBUFFERS_FINAL_CLASS { + public: + Builder(size_t initial_size = 256, + BuilderFlag flags = BUILDER_FLAG_SHARE_KEYS) + : buf_(initial_size), + finished_(false), + has_duplicate_keys_(false), + flags_(flags), + force_min_bit_width_(BIT_WIDTH_8), + key_pool(KeyOffsetCompare(buf_)), + string_pool(StringOffsetCompare(buf_)) { + buf_.clear(); + } + +#ifdef FLATBUFFERS_DEFAULT_DECLARATION + Builder(Builder &&) = default; + Builder &operator=(Builder &&) = default; +#endif + + /// @brief Get the serialized buffer (after you call `Finish()`). + /// @return Returns a vector owned by this class. + const std::vector &GetBuffer() const { + Finished(); + return buf_; + } + + // Size of the buffer. Does not include unfinished values. + size_t GetSize() const { return buf_.size(); } + + // Reset all state so we can re-use the buffer. + void Clear() { + buf_.clear(); + stack_.clear(); + finished_ = false; + // flags_ remains as-is; + force_min_bit_width_ = BIT_WIDTH_8; + key_pool.clear(); + string_pool.clear(); + } + + // All value constructing functions below have two versions: one that + // takes a key (for placement inside a map) and one that doesn't (for inside + // vectors and elsewhere). + + void Null() { stack_.push_back(Value()); } + void Null(const char *key) { + Key(key); + Null(); + } + + void Int(int64_t i) { stack_.push_back(Value(i, FBT_INT, WidthI(i))); } + void Int(const char *key, int64_t i) { + Key(key); + Int(i); + } + + void UInt(uint64_t u) { stack_.push_back(Value(u, FBT_UINT, WidthU(u))); } + void UInt(const char *key, uint64_t u) { + Key(key); + UInt(u); + } + + void Float(float f) { stack_.push_back(Value(f)); } + void Float(const char *key, float f) { + Key(key); + Float(f); + } + + void Double(double f) { stack_.push_back(Value(f)); } + void Double(const char *key, double d) { + Key(key); + Double(d); + } + + void Bool(bool b) { stack_.push_back(Value(b)); } + void Bool(const char *key, bool b) { + Key(key); + Bool(b); + } + + void IndirectInt(int64_t i) { PushIndirect(i, FBT_INDIRECT_INT, WidthI(i)); } + void IndirectInt(const char *key, int64_t i) { + Key(key); + IndirectInt(i); + } + + void IndirectUInt(uint64_t u) { + PushIndirect(u, FBT_INDIRECT_UINT, WidthU(u)); + } + void IndirectUInt(const char *key, uint64_t u) { + Key(key); + IndirectUInt(u); + } + + void IndirectFloat(float f) { + PushIndirect(f, FBT_INDIRECT_FLOAT, BIT_WIDTH_32); + } + void IndirectFloat(const char *key, float f) { + Key(key); + IndirectFloat(f); + } + + void IndirectDouble(double f) { + PushIndirect(f, FBT_INDIRECT_FLOAT, WidthF(f)); + } + void IndirectDouble(const char *key, double d) { + Key(key); + IndirectDouble(d); + } + + size_t Key(const char *str, size_t len) { + auto sloc = buf_.size(); + WriteBytes(str, len + 1); + if (flags_ & BUILDER_FLAG_SHARE_KEYS) { + auto it = key_pool.find(sloc); + if (it != key_pool.end()) { + // Already in the buffer. Remove key we just serialized, and use + // existing offset instead. + buf_.resize(sloc); + sloc = *it; + } else { + key_pool.insert(sloc); + } + } + stack_.push_back(Value(static_cast(sloc), FBT_KEY, BIT_WIDTH_8)); + return sloc; + } + + size_t Key(const char *str) { return Key(str, strlen(str)); } + size_t Key(const std::string &str) { return Key(str.c_str(), str.size()); } + + size_t String(const char *str, size_t len) { + auto reset_to = buf_.size(); + auto sloc = CreateBlob(str, len, 1, FBT_STRING); + if (flags_ & BUILDER_FLAG_SHARE_STRINGS) { + StringOffset so(sloc, len); + auto it = string_pool.find(so); + if (it != string_pool.end()) { + // Already in the buffer. Remove string we just serialized, and use + // existing offset instead. + buf_.resize(reset_to); + sloc = it->first; + stack_.back().u_ = sloc; + } else { + string_pool.insert(so); + } + } + return sloc; + } + size_t String(const char *str) { return String(str, strlen(str)); } + size_t String(const std::string &str) { + return String(str.c_str(), str.size()); + } + void String(const flexbuffers::String &str) { + String(str.c_str(), str.length()); + } + + void String(const char *key, const char *str) { + Key(key); + String(str); + } + void String(const char *key, const std::string &str) { + Key(key); + String(str); + } + void String(const char *key, const flexbuffers::String &str) { + Key(key); + String(str); + } + + size_t Blob(const void *data, size_t len) { + return CreateBlob(data, len, 0, FBT_BLOB); + } + size_t Blob(const std::vector &v) { + return CreateBlob(v.data(), v.size(), 0, FBT_BLOB); + } + + void Blob(const char *key, const void *data, size_t len) { + Key(key); + Blob(data, len); + } + void Blob(const char *key, const std::vector &v) { + Key(key); + Blob(v); + } + + // TODO(wvo): support all the FlexBuffer types (like flexbuffers::String), + // e.g. Vector etc. Also in overloaded versions. + // Also some FlatBuffers types? + + size_t StartVector() { return stack_.size(); } + size_t StartVector(const char *key) { + Key(key); + return stack_.size(); + } + size_t StartMap() { return stack_.size(); } + size_t StartMap(const char *key) { + Key(key); + return stack_.size(); + } + + // TODO(wvo): allow this to specify an alignment greater than the natural + // alignment. + size_t EndVector(size_t start, bool typed, bool fixed) { + auto vec = CreateVector(start, stack_.size() - start, 1, typed, fixed); + // Remove temp elements and return vector. + stack_.resize(start); + stack_.push_back(vec); + return static_cast(vec.u_); + } + + size_t EndMap(size_t start) { + // We should have interleaved keys and values on the stack. + // Make sure it is an even number: + auto len = stack_.size() - start; + FLATBUFFERS_ASSERT(!(len & 1)); + len /= 2; + // Make sure keys are all strings: + for (auto key = start; key < stack_.size(); key += 2) { + FLATBUFFERS_ASSERT(stack_[key].type_ == FBT_KEY); + } + // Now sort values, so later we can do a binary search lookup. + // We want to sort 2 array elements at a time. + struct TwoValue { + Value key; + Value val; + }; + // TODO(wvo): strict aliasing? + // TODO(wvo): allow the caller to indicate the data is already sorted + // for maximum efficiency? With an assert to check sortedness to make sure + // we're not breaking binary search. + // Or, we can track if the map is sorted as keys are added which would be + // be quite cheap (cheaper than checking it here), so we can skip this + // step automatically when appliccable, and encourage people to write in + // sorted fashion. + // std::sort is typically already a lot faster on sorted data though. + auto dict = reinterpret_cast(stack_.data() + start); + std::sort( + dict, dict + len, [&](const TwoValue &a, const TwoValue &b) -> bool { + auto as = reinterpret_cast(buf_.data() + a.key.u_); + auto bs = reinterpret_cast(buf_.data() + b.key.u_); + auto comp = strcmp(as, bs); + // We want to disallow duplicate keys, since this results in a + // map where values cannot be found. + // But we can't assert here (since we don't want to fail on + // random JSON input) or have an error mechanism. + // Instead, we set has_duplicate_keys_ in the builder to + // signal this. + // TODO: Have to check for pointer equality, as some sort + // implementation apparently call this function with the same + // element?? Why? + if (!comp && &a != &b) has_duplicate_keys_ = true; + return comp < 0; + }); + // First create a vector out of all keys. + // TODO(wvo): if kBuilderFlagShareKeyVectors is true, see if we can share + // the first vector. + auto keys = CreateVector(start, len, 2, true, false); + auto vec = CreateVector(start + 1, len, 2, false, false, &keys); + // Remove temp elements and return map. + stack_.resize(start); + stack_.push_back(vec); + return static_cast(vec.u_); + } + + // Call this after EndMap to see if the map had any duplicate keys. + // Any map with such keys won't be able to retrieve all values. + bool HasDuplicateKeys() const { return has_duplicate_keys_; } + + template size_t Vector(F f) { + auto start = StartVector(); + f(); + return EndVector(start, false, false); + } + template size_t Vector(F f, T &state) { + auto start = StartVector(); + f(state); + return EndVector(start, false, false); + } + template size_t Vector(const char *key, F f) { + auto start = StartVector(key); + f(); + return EndVector(start, false, false); + } + template + size_t Vector(const char *key, F f, T &state) { + auto start = StartVector(key); + f(state); + return EndVector(start, false, false); + } + + template void Vector(const T *elems, size_t len) { + if (flatbuffers::is_scalar::value) { + // This path should be a lot quicker and use less space. + ScalarVector(elems, len, false); + } else { + auto start = StartVector(); + for (size_t i = 0; i < len; i++) Add(elems[i]); + EndVector(start, false, false); + } + } + template + void Vector(const char *key, const T *elems, size_t len) { + Key(key); + Vector(elems, len); + } + template void Vector(const std::vector &vec) { + Vector(vec.data(), vec.size()); + } + + template size_t TypedVector(F f) { + auto start = StartVector(); + f(); + return EndVector(start, true, false); + } + template size_t TypedVector(F f, T &state) { + auto start = StartVector(); + f(state); + return EndVector(start, true, false); + } + template size_t TypedVector(const char *key, F f) { + auto start = StartVector(key); + f(); + return EndVector(start, true, false); + } + template + size_t TypedVector(const char *key, F f, T &state) { + auto start = StartVector(key); + f(state); + return EndVector(start, true, false); + } + + template size_t FixedTypedVector(const T *elems, size_t len) { + // We only support a few fixed vector lengths. Anything bigger use a + // regular typed vector. + FLATBUFFERS_ASSERT(len >= 2 && len <= 4); + // And only scalar values. + static_assert(flatbuffers::is_scalar::value, "Unrelated types"); + return ScalarVector(elems, len, true); + } + + template + size_t FixedTypedVector(const char *key, const T *elems, size_t len) { + Key(key); + return FixedTypedVector(elems, len); + } + + template size_t Map(F f) { + auto start = StartMap(); + f(); + return EndMap(start); + } + template size_t Map(F f, T &state) { + auto start = StartMap(); + f(state); + return EndMap(start); + } + template size_t Map(const char *key, F f) { + auto start = StartMap(key); + f(); + return EndMap(start); + } + template size_t Map(const char *key, F f, T &state) { + auto start = StartMap(key); + f(state); + return EndMap(start); + } + template void Map(const std::map &map) { + auto start = StartMap(); + for (auto it = map.begin(); it != map.end(); ++it) + Add(it->first.c_str(), it->second); + EndMap(start); + } + + // If you wish to share a value explicitly (a value not shared automatically + // through one of the BUILDER_FLAG_SHARE_* flags) you can do so with these + // functions. Or if you wish to turn those flags off for performance reasons + // and still do some explicit sharing. For example: + // builder.IndirectDouble(M_PI); + // auto id = builder.LastValue(); // Remember where we stored it. + // .. more code goes here .. + // builder.ReuseValue(id); // Refers to same double by offset. + // LastValue works regardless of whether the value has a key or not. + // Works on any data type. + struct Value; + Value LastValue() { return stack_.back(); } + void ReuseValue(Value v) { stack_.push_back(v); } + void ReuseValue(const char *key, Value v) { + Key(key); + ReuseValue(v); + } + + // Overloaded Add that tries to call the correct function above. + void Add(int8_t i) { Int(i); } + void Add(int16_t i) { Int(i); } + void Add(int32_t i) { Int(i); } + void Add(int64_t i) { Int(i); } + void Add(uint8_t u) { UInt(u); } + void Add(uint16_t u) { UInt(u); } + void Add(uint32_t u) { UInt(u); } + void Add(uint64_t u) { UInt(u); } + void Add(float f) { Float(f); } + void Add(double d) { Double(d); } + void Add(bool b) { Bool(b); } + void Add(const char *str) { String(str); } + void Add(const std::string &str) { String(str); } + void Add(const flexbuffers::String &str) { String(str); } + + template void Add(const std::vector &vec) { Vector(vec); } + + template void Add(const char *key, const T &t) { + Key(key); + Add(t); + } + + template void Add(const std::map &map) { + Map(map); + } + + template void operator+=(const T &t) { Add(t); } + + // This function is useful in combination with the Mutate* functions above. + // It forces elements of vectors and maps to have a minimum size, such that + // they can later be updated without failing. + // Call with no arguments to reset. + void ForceMinimumBitWidth(BitWidth bw = BIT_WIDTH_8) { + force_min_bit_width_ = bw; + } + + void Finish() { + // If you hit this assert, you likely have objects that were never included + // in a parent. You need to have exactly one root to finish a buffer. + // Check your Start/End calls are matched, and all objects are inside + // some other object. + FLATBUFFERS_ASSERT(stack_.size() == 1); + + // Write root value. + auto byte_width = Align(stack_[0].ElemWidth(buf_.size(), 0)); + WriteAny(stack_[0], byte_width); + // Write root type. + Write(stack_[0].StoredPackedType(), 1); + // Write root size. Normally determined by parent, but root has no parent :) + Write(byte_width, 1); + + finished_ = true; + } + + private: + void Finished() const { + // If you get this assert, you're attempting to get access a buffer + // which hasn't been finished yet. Be sure to call + // Builder::Finish with your root object. + FLATBUFFERS_ASSERT(finished_); + } + + // Align to prepare for writing a scalar with a certain size. + uint8_t Align(BitWidth alignment) { + auto byte_width = 1U << alignment; + buf_.insert(buf_.end(), flatbuffers::PaddingBytes(buf_.size(), byte_width), + 0); + return static_cast(byte_width); + } + + void WriteBytes(const void *val, size_t size) { + buf_.insert(buf_.end(), reinterpret_cast(val), + reinterpret_cast(val) + size); + } + + template void Write(T val, size_t byte_width) { + FLATBUFFERS_ASSERT(sizeof(T) >= byte_width); + val = flatbuffers::EndianScalar(val); + WriteBytes(&val, byte_width); + } + + void WriteDouble(double f, uint8_t byte_width) { + switch (byte_width) { + case 8: Write(f, byte_width); break; + case 4: Write(static_cast(f), byte_width); break; + // case 2: Write(static_cast(f), byte_width); break; + // case 1: Write(static_cast(f), byte_width); break; + default: FLATBUFFERS_ASSERT(0); + } + } + + void WriteOffset(uint64_t o, uint8_t byte_width) { + auto reloff = buf_.size() - o; + FLATBUFFERS_ASSERT(byte_width == 8 || reloff < 1ULL << (byte_width * 8)); + Write(reloff, byte_width); + } + + template void PushIndirect(T val, Type type, BitWidth bit_width) { + auto byte_width = Align(bit_width); + auto iloc = buf_.size(); + Write(val, byte_width); + stack_.push_back(Value(static_cast(iloc), type, bit_width)); + } + + static BitWidth WidthB(size_t byte_width) { + switch (byte_width) { + case 1: return BIT_WIDTH_8; + case 2: return BIT_WIDTH_16; + case 4: return BIT_WIDTH_32; + case 8: return BIT_WIDTH_64; + default: FLATBUFFERS_ASSERT(false); return BIT_WIDTH_64; + } + } + + template static Type GetScalarType() { + static_assert(flatbuffers::is_scalar::value, "Unrelated types"); + return flatbuffers::is_floating_point::value + ? FBT_FLOAT + : flatbuffers::is_same::value + ? FBT_BOOL + : (flatbuffers::is_unsigned::value ? FBT_UINT + : FBT_INT); + } + + public: + // This was really intended to be private, except for LastValue/ReuseValue. + struct Value { + union { + int64_t i_; + uint64_t u_; + double f_; + }; + + Type type_; + + // For scalars: of itself, for vector: of its elements, for string: length. + BitWidth min_bit_width_; + + Value() : i_(0), type_(FBT_NULL), min_bit_width_(BIT_WIDTH_8) {} + + Value(bool b) + : u_(static_cast(b)), + type_(FBT_BOOL), + min_bit_width_(BIT_WIDTH_8) {} + + Value(int64_t i, Type t, BitWidth bw) + : i_(i), type_(t), min_bit_width_(bw) {} + Value(uint64_t u, Type t, BitWidth bw) + : u_(u), type_(t), min_bit_width_(bw) {} + + Value(float f) + : f_(static_cast(f)), + type_(FBT_FLOAT), + min_bit_width_(BIT_WIDTH_32) {} + Value(double f) : f_(f), type_(FBT_FLOAT), min_bit_width_(WidthF(f)) {} + + uint8_t StoredPackedType(BitWidth parent_bit_width_ = BIT_WIDTH_8) const { + return PackedType(StoredWidth(parent_bit_width_), type_); + } + + BitWidth ElemWidth(size_t buf_size, size_t elem_index) const { + if (IsInline(type_)) { + return min_bit_width_; + } else { + // We have an absolute offset, but want to store a relative offset + // elem_index elements beyond the current buffer end. Since whether + // the relative offset fits in a certain byte_width depends on + // the size of the elements before it (and their alignment), we have + // to test for each size in turn. + for (size_t byte_width = 1; + byte_width <= sizeof(flatbuffers::largest_scalar_t); + byte_width *= 2) { + // Where are we going to write this offset? + auto offset_loc = buf_size + + flatbuffers::PaddingBytes(buf_size, byte_width) + + elem_index * byte_width; + // Compute relative offset. + auto offset = offset_loc - u_; + // Does it fit? + auto bit_width = WidthU(offset); + if (static_cast(static_cast(1U) << bit_width) == + byte_width) + return bit_width; + } + FLATBUFFERS_ASSERT(false); // Must match one of the sizes above. + return BIT_WIDTH_64; + } + } + + BitWidth StoredWidth(BitWidth parent_bit_width_ = BIT_WIDTH_8) const { + if (IsInline(type_)) { + return (std::max)(min_bit_width_, parent_bit_width_); + } else { + return min_bit_width_; + } + } + }; + + private: + void WriteAny(const Value &val, uint8_t byte_width) { + switch (val.type_) { + case FBT_NULL: + case FBT_INT: Write(val.i_, byte_width); break; + case FBT_BOOL: + case FBT_UINT: Write(val.u_, byte_width); break; + case FBT_FLOAT: WriteDouble(val.f_, byte_width); break; + default: WriteOffset(val.u_, byte_width); break; + } + } + + size_t CreateBlob(const void *data, size_t len, size_t trailing, Type type) { + auto bit_width = WidthU(len); + auto byte_width = Align(bit_width); + Write(len, byte_width); + auto sloc = buf_.size(); + WriteBytes(data, len + trailing); + stack_.push_back(Value(static_cast(sloc), type, bit_width)); + return sloc; + } + + template + size_t ScalarVector(const T *elems, size_t len, bool fixed) { + auto vector_type = GetScalarType(); + auto byte_width = sizeof(T); + auto bit_width = WidthB(byte_width); + // If you get this assert, you're trying to write a vector with a size + // field that is bigger than the scalars you're trying to write (e.g. a + // byte vector > 255 elements). For such types, write a "blob" instead. + // TODO: instead of asserting, could write vector with larger elements + // instead, though that would be wasteful. + FLATBUFFERS_ASSERT(WidthU(len) <= bit_width); + Align(bit_width); + if (!fixed) Write(len, byte_width); + auto vloc = buf_.size(); + for (size_t i = 0; i < len; i++) Write(elems[i], byte_width); + stack_.push_back(Value(static_cast(vloc), + ToTypedVector(vector_type, fixed ? len : 0), + bit_width)); + return vloc; + } + + Value CreateVector(size_t start, size_t vec_len, size_t step, bool typed, + bool fixed, const Value *keys = nullptr) { + FLATBUFFERS_ASSERT( + !fixed || + typed); // typed=false, fixed=true combination is not supported. + // Figure out smallest bit width we can store this vector with. + auto bit_width = (std::max)(force_min_bit_width_, WidthU(vec_len)); + auto prefix_elems = 1; + if (keys) { + // If this vector is part of a map, we will pre-fix an offset to the keys + // to this vector. + bit_width = (std::max)(bit_width, keys->ElemWidth(buf_.size(), 0)); + prefix_elems += 2; + } + Type vector_type = FBT_KEY; + // Check bit widths and types for all elements. + for (size_t i = start; i < stack_.size(); i += step) { + auto elem_width = + stack_[i].ElemWidth(buf_.size(), i - start + prefix_elems); + bit_width = (std::max)(bit_width, elem_width); + if (typed) { + if (i == start) { + vector_type = stack_[i].type_; + } else { + // If you get this assert, you are writing a typed vector with + // elements that are not all the same type. + FLATBUFFERS_ASSERT(vector_type == stack_[i].type_); + } + } + } + // If you get this assert, your typed types are not one of: + // Int / UInt / Float / Key. + FLATBUFFERS_ASSERT(!typed || IsTypedVectorElementType(vector_type)); + auto byte_width = Align(bit_width); + // Write vector. First the keys width/offset if available, and size. + if (keys) { + WriteOffset(keys->u_, byte_width); + Write(1ULL << keys->min_bit_width_, byte_width); + } + if (!fixed) Write(vec_len, byte_width); + // Then the actual data. + auto vloc = buf_.size(); + for (size_t i = start; i < stack_.size(); i += step) { + WriteAny(stack_[i], byte_width); + } + // Then the types. + if (!typed) { + for (size_t i = start; i < stack_.size(); i += step) { + buf_.push_back(stack_[i].StoredPackedType(bit_width)); + } + } + return Value(static_cast(vloc), + keys ? FBT_MAP + : (typed ? ToTypedVector(vector_type, fixed ? vec_len : 0) + : FBT_VECTOR), + bit_width); + } + + // You shouldn't really be copying instances of this class. + Builder(const Builder &); + Builder &operator=(const Builder &); + + std::vector buf_; + std::vector stack_; + + bool finished_; + bool has_duplicate_keys_; + + BuilderFlag flags_; + + BitWidth force_min_bit_width_; + + struct KeyOffsetCompare { + explicit KeyOffsetCompare(const std::vector &buf) : buf_(&buf) {} + bool operator()(size_t a, size_t b) const { + auto stra = reinterpret_cast(buf_->data() + a); + auto strb = reinterpret_cast(buf_->data() + b); + return strcmp(stra, strb) < 0; + } + const std::vector *buf_; + }; + + typedef std::pair StringOffset; + struct StringOffsetCompare { + explicit StringOffsetCompare(const std::vector &buf) + : buf_(&buf) {} + bool operator()(const StringOffset &a, const StringOffset &b) const { + auto stra = buf_->data() + a.first; + auto strb = buf_->data() + b.first; + auto cr = memcmp(stra, strb, (std::min)(a.second, b.second) + 1); + return cr < 0 || (cr == 0 && a.second < b.second); + } + const std::vector *buf_; + }; + + typedef std::set KeyOffsetMap; + typedef std::set StringOffsetMap; + + KeyOffsetMap key_pool; + StringOffsetMap string_pool; + + friend class Verifier; +}; + +// Helper class to verify the integrity of a FlexBuffer +class Verifier FLATBUFFERS_FINAL_CLASS { + public: + Verifier(const uint8_t *buf, size_t buf_len, + // Supplying this vector likely results in faster verification + // of larger buffers with many shared keys/strings, but + // comes at the cost of using additional memory the same size of + // the buffer being verified, so it is by default off. + std::vector *reuse_tracker = nullptr, + bool _check_alignment = true, size_t max_depth = 64) + : buf_(buf), + size_(buf_len), + depth_(0), + max_depth_(max_depth), + num_vectors_(0), + max_vectors_(buf_len), + check_alignment_(_check_alignment), + reuse_tracker_(reuse_tracker) { + FLATBUFFERS_ASSERT(size_ < FLATBUFFERS_MAX_BUFFER_SIZE); + if (reuse_tracker_) { + reuse_tracker_->clear(); + reuse_tracker_->resize(size_, PackedType(BIT_WIDTH_8, FBT_NULL)); + } + } + + private: + // Central location where any verification failures register. + bool Check(bool ok) const { + // clang-format off + #ifdef FLATBUFFERS_DEBUG_VERIFICATION_FAILURE + FLATBUFFERS_ASSERT(ok); + #endif + // clang-format on + return ok; + } + + // Verify any range within the buffer. + bool VerifyFrom(size_t elem, size_t elem_len) const { + return Check(elem_len < size_ && elem <= size_ - elem_len); + } + bool VerifyBefore(size_t elem, size_t elem_len) const { + return Check(elem_len <= elem); + } + + bool VerifyFromPointer(const uint8_t *p, size_t len) { + auto o = static_cast(p - buf_); + return VerifyFrom(o, len); + } + bool VerifyBeforePointer(const uint8_t *p, size_t len) { + auto o = static_cast(p - buf_); + return VerifyBefore(o, len); + } + + bool VerifyByteWidth(size_t width) { + return Check(width == 1 || width == 2 || width == 4 || width == 8); + } + + bool VerifyType(int type) { return Check(type >= 0 && type < FBT_MAX_TYPE); } + + bool VerifyOffset(uint64_t off, const uint8_t *p) { + return Check(off <= static_cast(size_)) && + off <= static_cast(p - buf_); + } + + bool VerifyAlignment(const uint8_t *p, size_t size) const { + auto o = static_cast(p - buf_); + return Check((o & (size - 1)) == 0 || !check_alignment_); + } + +// Macro, since we want to escape from parent function & use lazy args. +#define FLEX_CHECK_VERIFIED(P, PACKED_TYPE) \ + if (reuse_tracker_) { \ + auto packed_type = PACKED_TYPE; \ + auto existing = (*reuse_tracker_)[P - buf_]; \ + if (existing == packed_type) return true; \ + /* Fail verification if already set with different type! */ \ + if (!Check(existing == 0)) return false; \ + (*reuse_tracker_)[P - buf_] = packed_type; \ + } + + bool VerifyVector(Reference r, const uint8_t *p, Type elem_type) { + // Any kind of nesting goes thru this function, so guard against that + // here, both with simple nesting checks, and the reuse tracker if on. + depth_++; + num_vectors_++; + if (!Check(depth_ <= max_depth_ && num_vectors_ <= max_vectors_)) + return false; + auto size_byte_width = r.byte_width_; + if (!VerifyBeforePointer(p, size_byte_width)) return false; + FLEX_CHECK_VERIFIED(p - size_byte_width, + PackedType(Builder::WidthB(size_byte_width), r.type_)); + auto sized = Sized(p, size_byte_width); + auto num_elems = sized.size(); + auto elem_byte_width = r.type_ == FBT_STRING || r.type_ == FBT_BLOB + ? uint8_t(1) + : r.byte_width_; + auto max_elems = SIZE_MAX / elem_byte_width; + if (!Check(num_elems < max_elems)) + return false; // Protect against byte_size overflowing. + auto byte_size = num_elems * elem_byte_width; + if (!VerifyFromPointer(p, byte_size)) return false; + if (elem_type == FBT_NULL) { + // Verify type bytes after the vector. + if (!VerifyFromPointer(p + byte_size, num_elems)) return false; + auto v = Vector(p, size_byte_width); + for (size_t i = 0; i < num_elems; i++) + if (!VerifyRef(v[i])) return false; + } else if (elem_type == FBT_KEY) { + auto v = TypedVector(p, elem_byte_width, FBT_KEY); + for (size_t i = 0; i < num_elems; i++) + if (!VerifyRef(v[i])) return false; + } else { + FLATBUFFERS_ASSERT(IsInline(elem_type)); + } + depth_--; + return true; + } + + bool VerifyKeys(const uint8_t *p, uint8_t byte_width) { + // The vector part of the map has already been verified. + const size_t num_prefixed_fields = 3; + if (!VerifyBeforePointer(p, byte_width * num_prefixed_fields)) return false; + p -= byte_width * num_prefixed_fields; + auto off = ReadUInt64(p, byte_width); + if (!VerifyOffset(off, p)) return false; + auto key_byte_with = + static_cast(ReadUInt64(p + byte_width, byte_width)); + if (!VerifyByteWidth(key_byte_with)) return false; + return VerifyVector(Reference(p, byte_width, key_byte_with, FBT_VECTOR_KEY), + p - off, FBT_KEY); + } + + bool VerifyKey(const uint8_t *p) { + FLEX_CHECK_VERIFIED(p, PackedType(BIT_WIDTH_8, FBT_KEY)); + while (p < buf_ + size_) + if (*p++) return true; + return false; + } + +#undef FLEX_CHECK_VERIFIED + + bool VerifyTerminator(const String &s) { + return VerifyFromPointer(reinterpret_cast(s.c_str()), + s.size() + 1); + } + + bool VerifyRef(Reference r) { + // r.parent_width_ and r.data_ already verified. + if (!VerifyByteWidth(r.byte_width_) || !VerifyType(r.type_)) { + return false; + } + if (IsInline(r.type_)) { + // Inline scalars, don't require further verification. + return true; + } + // All remaining types are an offset. + auto off = ReadUInt64(r.data_, r.parent_width_); + if (!VerifyOffset(off, r.data_)) return false; + auto p = r.Indirect(); + if (!VerifyAlignment(p, r.byte_width_)) return false; + switch (r.type_) { + case FBT_INDIRECT_INT: + case FBT_INDIRECT_UINT: + case FBT_INDIRECT_FLOAT: return VerifyFromPointer(p, r.byte_width_); + case FBT_KEY: return VerifyKey(p); + case FBT_MAP: + return VerifyVector(r, p, FBT_NULL) && VerifyKeys(p, r.byte_width_); + case FBT_VECTOR: return VerifyVector(r, p, FBT_NULL); + case FBT_VECTOR_INT: return VerifyVector(r, p, FBT_INT); + case FBT_VECTOR_BOOL: + case FBT_VECTOR_UINT: return VerifyVector(r, p, FBT_UINT); + case FBT_VECTOR_FLOAT: return VerifyVector(r, p, FBT_FLOAT); + case FBT_VECTOR_KEY: return VerifyVector(r, p, FBT_KEY); + case FBT_VECTOR_STRING_DEPRECATED: + // Use of FBT_KEY here intentional, see elsewhere. + return VerifyVector(r, p, FBT_KEY); + case FBT_BLOB: return VerifyVector(r, p, FBT_UINT); + case FBT_STRING: + return VerifyVector(r, p, FBT_UINT) && + VerifyTerminator(String(p, r.byte_width_)); + case FBT_VECTOR_INT2: + case FBT_VECTOR_UINT2: + case FBT_VECTOR_FLOAT2: + case FBT_VECTOR_INT3: + case FBT_VECTOR_UINT3: + case FBT_VECTOR_FLOAT3: + case FBT_VECTOR_INT4: + case FBT_VECTOR_UINT4: + case FBT_VECTOR_FLOAT4: { + uint8_t len = 0; + auto vtype = ToFixedTypedVectorElementType(r.type_, &len); + if (!VerifyType(vtype)) return false; + return VerifyFromPointer(p, r.byte_width_ * len); + } + default: return false; + } + } + + public: + bool VerifyBuffer() { + if (!Check(size_ >= 3)) return false; + auto end = buf_ + size_; + auto byte_width = *--end; + auto packed_type = *--end; + return VerifyByteWidth(byte_width) && Check(end - buf_ >= byte_width) && + VerifyRef(Reference(end - byte_width, byte_width, packed_type)); + } + + private: + const uint8_t *buf_; + size_t size_; + size_t depth_; + const size_t max_depth_; + size_t num_vectors_; + const size_t max_vectors_; + bool check_alignment_; + std::vector *reuse_tracker_; +}; + +// Utility function that contructs the Verifier for you, see above for +// parameters. +inline bool VerifyBuffer(const uint8_t *buf, size_t buf_len, + std::vector *reuse_tracker = nullptr) { + Verifier verifier(buf, buf_len, reuse_tracker); + return verifier.VerifyBuffer(); +} + +} // namespace flexbuffers + +#if defined(_MSC_VER) +# pragma warning(pop) +#endif + +#endif // FLATBUFFERS_FLEXBUFFERS_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/LICENSE b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/LICENSE new file mode 100644 index 0000000..d645695 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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All Rights Reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// fixedpoint.h: fixed-point arithmetic, with basic operations and +// a few math functions such as tanh. + +#ifndef GEMMLOWP_INTERNAL_FIXEDPOINT_H_ +#define GEMMLOWP_INTERNAL_FIXEDPOINT_H_ + +#include +#include +#include +#include +#include + +#include "../internal/detect_platform.h" + +namespace gemmlowp { + +// Part 1: Low-level integer-arithmetic primitives. +// The implementations here are generic implementations valid for +// scalar types (e.g. std::int32_t). Architecture-specific SIMD types +// (e.g. NEON int32x4_t) may be supported by providing +// specializations for them in separate files. +// +// The purpose of these primitives is two-fold: +// - They will be used to implement higher-level fixed-point +// abstractions, namely the FixedPoint class and its arithmetic +// operators. +// - They will be directly used to implement some more involved +// fixed-point computations, e.g. the fixed-point implementation +// of math functions such as tanh. + +// Some compile-time traits around raw types to handle SIMD aspects: +// number of lanes, underlying scalar type. +template +struct FixedPointRawTypeTraits {}; + +template <> +struct FixedPointRawTypeTraits { + typedef std::int32_t ScalarRawType; + static constexpr int kLanes = 1; +}; + +template <> +struct FixedPointRawTypeTraits { + typedef std::int16_t ScalarRawType; + static constexpr int kLanes = 1; +}; + +// Returns a SIMD value duplicating a scalar value across all lanes. +template +tRawType Dup(typename FixedPointRawTypeTraits::ScalarRawType x) { + return x; +} + +// Plain bit-wise AND +template +tIntegerType BitAnd(tIntegerType a, tIntegerType b) { + return a & b; +} + +// Plain bit-wise OR +template +tIntegerType BitOr(tIntegerType a, tIntegerType b) { + return a | b; +} + +// Plain bit-wise XOR +template +tIntegerType BitXor(tIntegerType a, tIntegerType b) { + return a ^ b; +} + +// Plain bit-wise NOT +template +tIntegerType BitNot(tIntegerType a) { + return ~a; +} + +// Integer addition. Not saturating. Overflow is undefined behavior. +template +tIntegerType Add(tIntegerType a, tIntegerType b) { + return a + b; +} + +// Integer subtraction. Not saturating. Overflow is undefined behavior. +template +tIntegerType Mul(tIntegerType a, tIntegerType b) { + return a * b; +} + +template +tIntegerType Sub(tIntegerType a, tIntegerType b) { + return a - b; +} + +// Integer unary negative. Not saturating. Overflow is undefined behavior. +template +tIntegerType Neg(tIntegerType a) { + return -a; +} + +// Integer arithmetic left-shift, equivalent to multiplying with a power of two. +// Negative values are OK. In case of overflow, no Undefined +// Behavior, but the results are implementation-defined (in practice, +// they currently are saturated, but we make no commitment to that). The idea +// is that the caller will want to implement the overflowing cases with +// saturation with compare-and-mask, so we don't care about the results +// in the overflow case, we just want to avoid undefined behavior. +// +// tIntegerType may be int32 or any narrower signed type. +template +tIntegerType ShiftLeft(tIntegerType a, int offset) { + const std::int64_t wide_a = static_cast(a); + const std::int64_t wide_shifted = wide_a * (1 << offset); + const auto min = std::numeric_limits::min(); + const auto max = std::numeric_limits::max(); + return wide_shifted < min + ? min + : wide_shifted > max ? max + : static_cast(wide_shifted); +} + +// Integer arithmetic right-shift. Not rounding. +// Relying on implementation-defined, but in-practice-consistent, +// C++ compiler behavior. +template +tIntegerType ShiftRight(tIntegerType a, int offset) { + return a >> offset; +} + +// Each bit of the result is set to the corresponding bit of either then_val or +// else_val depending on whether the corresponding bit of if_mask is set. +// Equivalent to the VBSL instruction in ARM NEON. +template +tIntegerType SelectUsingMask(tIntegerType if_mask, tIntegerType then_val, + tIntegerType else_val) { + return BitXor(BitAnd(if_mask, then_val), BitAnd(BitNot(if_mask), else_val)); +} + +// For each input scalar, the corresponding bits of the result are set if the +// input scalar is non-zero. +template +tIntegerType MaskIfNonZero(tIntegerType a) { + static constexpr tIntegerType zero = 0; + return a ? BitNot(zero) : zero; +} + +// For each input scalar, the corresponding bits of the result are set if the +// input scalar is zero. +template +tIntegerType MaskIfZero(tIntegerType a) { + return MaskIfNonZero(!a); +} + +// For each pair of input scalars, the corresponding bits of the result are +// set if the input scalars are equal. +template +tIntegerType MaskIfEqual(tIntegerType a, tIntegerType b) { + return MaskIfNonZero(a == b); +} + +// For each pair of input scalars, the corresponding bits of the result are +// set if the input scalars are not equal. +template +tIntegerType MaskIfNotEqual(tIntegerType a, tIntegerType b) { + return MaskIfNonZero(a != b); +} + +// For each pair of input scalars, the corresponding bits of the result are +// set if the input scalars a, b satisfy a > b. +template +tIntegerType MaskIfGreaterThan(tIntegerType a, tIntegerType b) { + return MaskIfNonZero(a > b); +} + +// For each pair of input scalars, the corresponding bits of the result are +// set if the input scalars a, b satisfy a >= b. +template +tIntegerType MaskIfGreaterThanOrEqual(tIntegerType a, tIntegerType b) { + return MaskIfNonZero(a >= b); +} + +// For each pair of input scalars, the corresponding bits of the result are +// set if the input scalars a, b satisfy a < b. +template +tIntegerType MaskIfLessThan(tIntegerType a, tIntegerType b) { + return MaskIfNonZero(a < b); +} + +// For each pair of input scalars, the corresponding bits of the result are +// set if the input scalars a, b satisfy a <= b. +template +tIntegerType MaskIfLessThanOrEqual(tIntegerType a, tIntegerType b) { + return MaskIfNonZero(a <= b); +} + +// Returns true if all of the input scalars are nonzero. +// This function may currently assume that each of the input scalars has either +// all or none of its bits set. Otherwise, its behavior is currently undefined. +template +bool All(tIntegerType a) { + return a; +} + +// Returns true if any of the input scalars are nonzero. +// This function may currently assume that each of the input scalars has either +// all or none of its bits set. Otherwise, its behavior is currently undefined. +template +bool Any(tIntegerType a) { + return a; +} + +// Returns (a+b)/2, rounded to the nearest integer. +// Equivalent to VRHADD in the ARM NEON instruction set. +template +IntegerType RoundingHalfSum(IntegerType a, IntegerType b) { + static_assert(std::is_same::value, "unimplemented"); + (void)b; + return a; +} + +template <> +inline std::int32_t RoundingHalfSum(std::int32_t a, std::int32_t b) { + std::int64_t a64 = a; + std::int64_t b64 = b; + std::int64_t sum = a64 + b64; + std::int64_t sign = sum >= 0 ? 1 : -1; + return static_cast((sum + sign) / 2); +} + +template <> +inline std::int16_t RoundingHalfSum(std::int16_t a, std::int16_t b) { + std::int32_t a32 = a; + std::int32_t b32 = b; + std::int32_t sum = a32 + b32; + std::int32_t sign = sum >= 0 ? 1 : -1; + return static_cast((sum + sign) / 2); +} + +template +IntegerType SaturatingAdd(IntegerType a, IntegerType b) { + static_assert(std::is_same::value, "unimplemented"); + (void)b; + return a; +} + +// So far this is only needed for int16. +template <> +inline std::int16_t SaturatingAdd(std::int16_t a, std::int16_t b) { + std::int32_t a32 = a; + std::int32_t b32 = b; + std::int32_t sum = a32 + b32; + return static_cast( + std::min(static_cast(32767), + std::max(static_cast(-32768), sum))); +} + +// Returns a+b, saturating if the integers are 16bit or narrower, +// otherwise just a plain addition. +template +struct AddSaturatingIf16BitImpl { + static IntegerType Run(IntegerType a, IntegerType b) { return Add(a, b); } +}; +template +struct AddSaturatingIf16BitImpl { + static IntegerType Run(IntegerType a, IntegerType b) { + return SaturatingAdd(a, b); + } +}; +template +IntegerType AddSaturatingIf16Bit(IntegerType a, IntegerType b) { + using ScalarType = + typename FixedPointRawTypeTraits::ScalarRawType; + return AddSaturatingIf16BitImpl::Run(a, + b); +} + +// Returns the integer that represents the product of two fixed-point +// numbers, interpreting all integers as fixed-point values in the +// interval [-1, 1), rounding to the nearest value, and saturating +// -1 * -1 to the maximum value (since 1 is not in the half-open +// interval [-1, 1)). +// +// [The explanation below specializes to std::int32_t for example purpose.] +// +// The mapping between IntegerType and the interval [-1, 1) is unique and +// implied by IntegerType, which is assumed to be signed. For example, +// for IntegerType==std::int32_t, the mapping is +// real_value = integer_value / 2^31. +// So in this case, and leaving aside rounding and saturating, this +// function computes ((a / 2^31) * (b / 2^31)) * 2^31, which simplifies to +// (a * b) / 2^31. +// +// The 'doubling' part in the name of this function comes from the fact that +// this operation is very close to a "multiply-high" operation, keeping only +// the top half bits, except that that would be effectively computing +// (a * b) / 2^32, +// so here we are computing 2x that, since +// 1/2^31 = 2 * 1/2^32. +// The idea is to use all of the available 32 bits in the destination int32 +// value. +// +// [End of the explanation specializing to int32.] +// +// This is equivalent to the VQRDMULH instruction in ARM NEON. +template +IntegerType SaturatingRoundingDoublingHighMul(IntegerType a, IntegerType b) { + static_assert(std::is_same::value, "unimplemented"); + (void)b; + return a; +} + +// This function implements the same computation as the ARMv7 NEON VQRDMULH +// instruction. +template <> +inline std::int32_t SaturatingRoundingDoublingHighMul(std::int32_t a, + std::int32_t b) { + bool overflow = a == b && a == std::numeric_limits::min(); + std::int64_t a_64(a); + std::int64_t b_64(b); + std::int64_t ab_64 = a_64 * b_64; + std::int32_t nudge = ab_64 >= 0 ? (1 << 30) : (1 - (1 << 30)); + std::int32_t ab_x2_high32 = + static_cast((ab_64 + nudge) / (1ll << 31)); + return overflow ? std::numeric_limits::max() : ab_x2_high32; +} + +template <> +inline std::int16_t SaturatingRoundingDoublingHighMul(std::int16_t a, + std::int16_t b) { + bool overflow = a == b && a == std::numeric_limits::min(); + std::int32_t a_32(a); + std::int32_t b_32(b); + std::int32_t ab_32 = a_32 * b_32; + std::int16_t nudge = ab_32 >= 0 ? (1 << 14) : (1 - (1 << 14)); + std::int16_t ab_x2_high16 = + static_cast((ab_32 + nudge) / (1 << 15)); + return overflow ? std::numeric_limits::max() : ab_x2_high16; +} + +// Correctly-rounded-to-nearest division by a power-of-two. +// Also known as a rounding arithmetic right shift. +template +inline IntegerType RoundingDivideByPOT(IntegerType x, int exponent) { + assert(exponent >= 0); + assert(exponent <= 31); + const IntegerType mask = Dup((1ll << exponent) - 1); + const IntegerType zero = Dup(0); + const IntegerType one = Dup(1); + const IntegerType remainder = BitAnd(x, mask); + const IntegerType threshold = + Add(ShiftRight(mask, 1), BitAnd(MaskIfLessThan(x, zero), one)); + return Add(ShiftRight(x, exponent), + BitAnd(MaskIfGreaterThan(remainder, threshold), one)); +} + +// Returns the product of a run-time integer value by a compile-time power +// of two, with either a positive exponent (equivalent to an arithmetic +// left shift, saturating) or a negative exponent (equivalent to an arithmetic +// right shift, rounding to nearest). +template 0 ? 1 : Exponent < 0 ? -1 : 0)> +struct ImplSaturatingRoundingMultiplyByPOT {}; + +template +struct ImplSaturatingRoundingMultiplyByPOT { + static IntegerType eval(IntegerType x) { return x; } +}; + +template +struct ImplSaturatingRoundingMultiplyByPOT { + static IntegerType eval(IntegerType x) { + using ScalarIntegerType = + typename FixedPointRawTypeTraits::ScalarRawType; + const IntegerType min = + Dup(std::numeric_limits::min()); + const IntegerType max = + Dup(std::numeric_limits::max()); + const int ScalarIntegerTypeBits = 8 * sizeof(ScalarIntegerType); + + const std::int32_t threshold = + ((1 << (ScalarIntegerTypeBits - 1 - Exponent)) - 1); + const IntegerType positive_mask = + MaskIfGreaterThan(x, Dup(threshold)); + const IntegerType negative_mask = + MaskIfLessThan(x, Dup(-threshold)); + + IntegerType result = ShiftLeft(x, Exponent); + result = SelectUsingMask(positive_mask, max, result); + result = SelectUsingMask(negative_mask, min, result); + return result; + } +}; + +template +struct ImplSaturatingRoundingMultiplyByPOT { + static IntegerType eval(IntegerType x) { + return RoundingDivideByPOT(x, -Exponent); + } +}; + +template +IntegerType SaturatingRoundingMultiplyByPOT(IntegerType x) { + return ImplSaturatingRoundingMultiplyByPOT::eval(x); +} + +// Part 2: the FixedPoint class. + +// A FixedPoint object represents a fixed-point value stored in the underlying +// integer type tRawType, if tRawType is a plain scalar integer type. +// Alternatively, tRawType may be a SIMD type (e.g. NEON int32x4_t) in which +// case a FixedPoint object represents a corresponding SIMD vector of fixed +// point values. +// +// tIntegerBits describes the range of the fixed-point format: if +// tIntegerBits == m then the range of representable values is the half-open +// interval [-2^m; 2^m) where the open boundary on the right side means that +// 2^m is not representable (how close the maximum representable value is to +// it, depends on bit-depth of tRawType). +// +// In "Q format notation", +// https://en.wikipedia.org/wiki/Q_(number_format) +// we are describing the format +// Qm.n +// where +// m = tIntegerBits +// and +// n = NumberOfBits(tRawType) - (m + 1) +// Note that the (m + 1) in the above line is because we adopt the convention +// that we count the integer bits exclusively of the sign bit; so (m + 1) is +// the total number of integer bits inclusive of the sign bit. +// +// Accordingly, the number of integral representable values in our range +// [-2^m ; 2^m) +// is equal to 2^(m+1). +template +class FixedPoint { + public: + typedef tRawType RawType; + + typedef FixedPointRawTypeTraits RawTypeTraits; + typedef typename RawTypeTraits::ScalarRawType ScalarRawType; + + static constexpr int kTotalBits = 8 * sizeof(ScalarRawType); + static constexpr int kIntegerBits = tIntegerBits; + static constexpr int kFractionalBits = kTotalBits - 1 - kIntegerBits; + static_assert(kIntegerBits >= 0 && kIntegerBits < kTotalBits, + "bad IntegerBits"); + + typedef FixedPoint ScalarFixedPointType; + + static const ScalarRawType ScalarRawMin() { + return std::numeric_limits::min(); + } + + static const ScalarRawType ScalarRawMax() { + return std::numeric_limits::max(); + } + + static const ScalarRawType RawMin() { + return VectorFromScalar(ScalarRawMin()); + } + + static const ScalarRawType RawMax() { + return VectorFromScalar(ScalarRawMax()); + } + + static FixedPoint FromRaw(RawType x) { + FixedPoint retval; + retval.raw() = x; + return retval; + } + + static FixedPoint FromScalarRaw(ScalarRawType x) { + FixedPoint retval; + retval.raw() = Dup(x); + return retval; + } + + static FixedPoint FromScalarFixedPoint(ScalarFixedPointType x) { + return FromScalarRaw(x.raw()); + } + + template + static FixedPoint ConstantPOT() { + static constexpr int kOffset = kFractionalBits + Exponent; + static_assert( + kOffset < 31, + "Constant not exactly representable in this fixed-point format"); + return FromScalarRaw(ScalarRawType(1) << kOffset); + } + + static FixedPoint Zero() { return FromScalarRaw(0); } + + static FixedPoint One() { + return FromScalarRaw( + kIntegerBits == 0 + ? ScalarRawMax() + : (ScalarRawType(1) << (kIntegerBits == 0 ? 0 : kFractionalBits))); + } + + static FixedPoint FromDouble(double x) { + const double min_bound = static_cast(ScalarRawMin()); + const double max_bound = static_cast(ScalarRawMax()); + return FromScalarRaw(static_cast(std::min( + std::max(round(x * static_cast(1ll << kFractionalBits)), + min_bound), + max_bound))); + } + + RawType raw() const { return i_; } + RawType& raw() { return i_; } + + private: + RawType i_; +}; + +// Part 3: implementation of arithmetic operators for the +// FixedPoint class, and a few related functions. + +// A FixedPoint multiplication is just a +// SaturatingRoundingDoublingHighMul operation on the underlying +// raw integer values. The IntegerBits simply add up, as is obvious +// from the fact that the range is [-2^IntegerBits, 2^IntegerBits). +template +FixedPoint operator*( + FixedPoint a, + FixedPoint b) { + FixedPoint c; + c.raw() = SaturatingRoundingDoublingHighMul(a.raw(), b.raw()); + return c; +} + +// Tweaking IntegerBits gives exact multiplication by a power of two. +template +FixedPoint ExactMulByPot( + FixedPoint a) { + FixedPoint c; + c.raw() = a.raw(); + return c; +} + +// If we want to leave IntegerBits fixed, then multiplication +// by a power of two has to be saturating/rounding, not exact anymore. +template +FixedPoint SaturatingRoundingMultiplyByPOT( + FixedPoint a) { + return FixedPoint::FromRaw( + SaturatingRoundingMultiplyByPOT(a.raw())); +} + +// Generic arithmetic operators. + +#define MAKE_FIXEDPOINT_UNARY_FUNC(FuncName, ImplFuncName) \ + template \ + FixedPoint FuncName( \ + FixedPoint a) { \ + return FixedPoint::FromRaw(ImplFuncName(a.raw())); \ + } + +#define MAKE_FIXEDPOINT_BINARY_FUNC(FuncName, ImplFuncName) \ + template \ + FixedPoint FuncName( \ + FixedPoint a, \ + FixedPoint b) { \ + return FixedPoint::FromRaw( \ + ImplFuncName(a.raw(), b.raw())); \ + } + +MAKE_FIXEDPOINT_UNARY_FUNC(operator-, Neg) +MAKE_FIXEDPOINT_UNARY_FUNC(operator~, BitNot) +MAKE_FIXEDPOINT_BINARY_FUNC(operator+, Add) +MAKE_FIXEDPOINT_BINARY_FUNC(operator-, Sub) +MAKE_FIXEDPOINT_BINARY_FUNC(operator&, BitAnd) +MAKE_FIXEDPOINT_BINARY_FUNC(operator^, BitXor) +MAKE_FIXEDPOINT_BINARY_FUNC(operator|, BitOr) +MAKE_FIXEDPOINT_BINARY_FUNC(RoundingHalfSum, RoundingHalfSum) + +#undef MAKE_FIXEDPOINT_UNARY_FUNC +#undef MAKE_FIXEDPOINT_BINARY_FUNC + +#define MAKE_FIXEDPOINT_UNARY_FUNC_RETURNING_RAW(FuncName) \ + template \ + tRawType FuncName(FixedPoint a) { \ + return FuncName(a.raw()); \ + } + +#define MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW(FuncName) \ + template \ + tRawType FuncName(FixedPoint a, \ + FixedPoint b) { \ + return FuncName(a.raw(), b.raw()); \ + } + +MAKE_FIXEDPOINT_UNARY_FUNC_RETURNING_RAW(MaskIfZero) +MAKE_FIXEDPOINT_UNARY_FUNC_RETURNING_RAW(MaskIfNonZero) +MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW(MaskIfEqual) +MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW(MaskIfNotEqual) +MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW(MaskIfGreaterThan) +MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW(MaskIfGreaterThanOrEqual) +MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW(MaskIfLessThan) +MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW(MaskIfLessThanOrEqual) + +#undef MAKE_FIXEDPOINT_UNARY_FUNC_RETURNING_RAW +#undef MAKE_FIXEDPOINT_BINARY_FUNC_RETURNING_RAW + +template +FixedPoint SelectUsingMask( + tRawType if_mask, FixedPoint then_val, + FixedPoint else_val) { + return FixedPoint::FromRaw( + SelectUsingMask(if_mask, then_val.raw(), else_val.raw())); +} + +template +bool operator==(FixedPoint a, + FixedPoint b) { + return All(MaskIfEqual(a.raw(), b.raw())); +} + +template +bool operator!=(FixedPoint a, + FixedPoint b) { + return !(a == b); +} + +template +FixedPoint SaturatingAdd( + FixedPoint a, + FixedPoint b) { + return FixedPoint::FromRaw( + SaturatingAdd(a.raw(), b.raw())); +} + +template +FixedPoint AddSaturatingIf16Bit( + FixedPoint a, + FixedPoint b) { + return FixedPoint::FromRaw( + AddSaturatingIf16Bit(a.raw(), b.raw())); +} + +// Conversion to floating-point. +template +double ToDouble(FixedPoint x) { + static_assert(FixedPointRawTypeTraits::kLanes == 1, + "not applicable to SIMD types"); + typedef FixedPoint F; + return x.raw() / static_cast(1ll << F::kFractionalBits); +} + +// Rescale changes the number of IntegerBits and updates the underlying +// raw integer value accordingly. +template +FixedPoint Rescale( + FixedPoint x) { + static constexpr int kExponent = tIntegerBitsSrc - tIntegerBitsDst; + FixedPoint result; + result.raw() = SaturatingRoundingMultiplyByPOT(x.raw()); + return result; +} + +// CheckedFixedPointConstant allows to specify fixed-point constants +// initialized as real numbers, in a way that does not compile floating-point +// arithmetic in production code, yet still checks agreement with the +// floating-point expressions when asserts are enabled. +// +// The raw integer value provided is always a int32, encoding a 32-bit +// fixed-point value, regardless of the actual Scalar type. This allows +// writing generic code that applies just as well to the 32-bit and 16-bit +// cases. In the 16-bit case, the raw integer value is internally +// rounding-shifted by 16 bits to the right. +template +inline typename FixedPointType::ScalarRawType RescaleConstantInitializer( + std::int32_t int32_value) { + typedef typename FixedPointType::ScalarRawType ScalarRawType; + static constexpr int ScalarTypeBits = 8 * sizeof(ScalarRawType); + return static_cast( + RoundingDivideByPOT(int32_value, 32 - ScalarTypeBits)); +} +#ifdef GEMMLOWP_ENABLE_FIXEDPOINT_CONSTANTS_CHECKS +template +FixedPointType CheckedFixedPointConstant(std::int32_t raw_value, + double double_value) { + const FixedPointType result = FixedPointType::FromScalarRaw(raw_value); + assert(result == FixedPointType::FromDouble(double_value)); + return result; +} +#define GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(FixedPointType, \ + ScalarRawInt32Value, DoubleValue) \ + (gemmlowp::CheckedFixedPointConstant( \ + gemmlowp::RescaleConstantInitializer( \ + ScalarRawInt32Value), \ + DoubleValue)) + +#else +#define GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(FixedPointType, \ + ScalarRawInt32Value, DoubleValue) \ + (FixedPointType::FromScalarRaw( \ + gemmlowp::RescaleConstantInitializer( \ + ScalarRawInt32Value))) +#endif + +// Implementation of exponential function. + +// Returns exp(x) for x in [-1/4, 0). +template +FixedPoint exp_on_interval_between_negative_one_quarter_and_0_excl( + FixedPoint a) { + typedef FixedPoint F; + const F constant_term = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F, 1895147668, std::exp(-1.0 / 8.0)); + const F constant_1_over_3 = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F, 715827883, 1.0 / 3.0); + // We're evaluating a Taylor expansion around -1/8, so we do the change of + // variable: x = a + 1/8. + // In fixed-point with 0 integer bits, 1/8 is represented by 1 << 28. + F x = a + F::template ConstantPOT<-3>(); + F x2 = x * x; + F x3 = x2 * x; + F x4 = x2 * x2; + F x4_over_4 = SaturatingRoundingMultiplyByPOT<-2>(x4); + F x4_over_24_plus_x3_over_6_plus_x2_over_2 = + SaturatingRoundingMultiplyByPOT<-1>( + ((x4_over_4 + x3) * constant_1_over_3) + x2); + return AddSaturatingIf16Bit( + constant_term, + constant_term * (x + x4_over_24_plus_x3_over_6_plus_x2_over_2)); +} + +// Returns exp(x) for x < 0. +template +FixedPoint exp_on_negative_values( + FixedPoint a) { + typedef FixedPoint InputF; + typedef FixedPoint ResultF; + static constexpr int kFractionalBits = InputF::kFractionalBits; + static constexpr int kIntegerBits = InputF::kIntegerBits; + const InputF kOneQuarter = InputF::template ConstantPOT<-2>(); + InputF mask = kOneQuarter - InputF::FromScalarRaw(1); + InputF a_mod_quarter_minus_one_quarter = (a & mask) - kOneQuarter; + ResultF result = exp_on_interval_between_negative_one_quarter_and_0_excl( + Rescale<0>(a_mod_quarter_minus_one_quarter)); + tRawType remainder = (a_mod_quarter_minus_one_quarter - a).raw(); + +#define GEMMLOWP_EXP_BARREL_SHIFTER(Exponent, FixedPointMultiplier) \ + if (kIntegerBits > Exponent) { \ + const ResultF kMultiplier = GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT( \ + ResultF, FixedPointMultiplier, std::exp(-std::pow(2.0, Exponent))); \ + static constexpr int kShiftAmount = \ + kIntegerBits > Exponent ? kFractionalBits + Exponent : 0; \ + result = SelectUsingMask( \ + MaskIfNonZero(BitAnd(remainder, Dup(1 << kShiftAmount))), \ + result * kMultiplier, result); \ + } + + GEMMLOWP_EXP_BARREL_SHIFTER(-2, 1672461947); + GEMMLOWP_EXP_BARREL_SHIFTER(-1, 1302514674); + GEMMLOWP_EXP_BARREL_SHIFTER(+0, 790015084); + GEMMLOWP_EXP_BARREL_SHIFTER(+1, 290630308); + GEMMLOWP_EXP_BARREL_SHIFTER(+2, 39332535); + GEMMLOWP_EXP_BARREL_SHIFTER(+3, 720401); + GEMMLOWP_EXP_BARREL_SHIFTER(+4, 242); + +#undef GEMMLOWP_EXP_BARREL_SHIFTER + + static constexpr int clampB = kIntegerBits > 5 ? 36 - kIntegerBits : 0; + if (kIntegerBits > 5) { + const InputF clamp = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(InputF, -(1 << clampB), -32.0); + result = SelectUsingMask(MaskIfLessThan(a, clamp), ResultF::Zero(), result); + } + + result = SelectUsingMask(MaskIfZero(a), ResultF::One(), result); + return result; +} + +// Implementation of tanh: (1 - exp(-2x)) / (1 + exp(-2x)). + +// Returns (1 - x) / (1 + x) for x in (0, 1). +template +FixedPoint one_minus_x_over_one_plus_x_for_x_in_0_1( + FixedPoint a) { + typedef FixedPoint F0; + typedef FixedPoint F2; + F0 half_denominator = RoundingHalfSum(a, F0::One()); + // Newton-Raphson division + // https://en.wikipedia.org/wiki/Division_algorithm#Newton.E2.80.93Raphson_division + // Refer to that page for the logic behind the 48/17 and 32/17 constants. + const F2 constant_48_over_17 = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F2, 1515870810, 48.0 / 17.0); + const F2 constant_neg_32_over_17 = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F2, -1010580540, -32.0 / 17.0); + F2 x = constant_48_over_17 + half_denominator * constant_neg_32_over_17; + for (int i = 0; i < 3; i++) { + F2 half_denominator_times_x = half_denominator * x; + F2 one_minus_half_denominator_times_x = + F2::One() - half_denominator_times_x; + x = x + Rescale<2>(x * one_minus_half_denominator_times_x); + } + return Rescale<0>(x - F2::One()); +} + +// Returns -tanh(x) for x < 0. +template +FixedPoint neg_tanh_on_negative_values( + FixedPoint a) { + return one_minus_x_over_one_plus_x_for_x_in_0_1( + exp_on_negative_values(ExactMulByPot<1>(a))); +} + +// Returns tanh(x) for any x. +template +FixedPoint tanh(FixedPoint a) { + typedef FixedPoint InputF; + typedef FixedPoint ResultF; + tRawType mask_if_negative = MaskIfLessThan(a, InputF::Zero()); + tRawType mask_if_zero = MaskIfZero(a); + InputF n = SelectUsingMask(mask_if_negative, a, -a); + ResultF t = neg_tanh_on_negative_values(n); + return SelectUsingMask(mask_if_zero, ResultF::Zero(), + SelectUsingMask(mask_if_negative, -t, t)); +} + +// Implementation of logistic function. + +// Returns 1 / (1 + x) for x in (0, 1). +template +FixedPoint one_over_one_plus_x_for_x_in_0_1( + FixedPoint a) { + typedef FixedPoint F0; + typedef FixedPoint F2; + F0 half_denominator = RoundingHalfSum(a, F0::One()); + // Newton-Raphson division + // https://en.wikipedia.org/wiki/Division_algorithm#Newton.E2.80.93Raphson_division + // Refer to that page for the logic behind the 48/17 and 32/17 constants. + const F2 constant_48_over_17 = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F2, 1515870810, 48.0 / 17.0); + const F2 constant_neg_32_over_17 = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(F2, -1010580540, -32.0 / 17.0); + F2 x = constant_48_over_17 + half_denominator * constant_neg_32_over_17; + for (int i = 0; i < 3; i++) { + F2 half_denominator_times_x = half_denominator * x; + F2 one_minus_half_denominator_times_x = + F2::One() - half_denominator_times_x; + x = x + Rescale<2>(x * one_minus_half_denominator_times_x); + } + return Rescale<0>(ExactMulByPot<-1>(x)); +} + +// Returns logistic(x) = 1 / (1 + exp(-x)) for x > 0. +template +FixedPoint logistic_on_positive_values( + FixedPoint a) { + return one_over_one_plus_x_for_x_in_0_1(exp_on_negative_values(-a)); +} + +// Returns logistic(x) = 1 / (1 + exp(-x)) for any x. +template +FixedPoint logistic(FixedPoint a) { + typedef FixedPoint InputF; + typedef FixedPoint ResultF; + tRawType mask_if_positive = MaskIfGreaterThan(a, InputF::Zero()); + tRawType mask_if_zero = MaskIfZero(a); + InputF abs_input = SelectUsingMask(mask_if_positive, a, -a); + ResultF result_if_positive = logistic_on_positive_values(abs_input); + ResultF result_if_negative = ResultF::One() - result_if_positive; + const ResultF one_half = + GEMMLOWP_CHECKED_FIXEDPOINT_CONSTANT(ResultF, 1 << 30, 0.5); + return SelectUsingMask(mask_if_zero, one_half, + SelectUsingMask(mask_if_positive, result_if_positive, + result_if_negative)); +} + +} // end namespace gemmlowp + +#ifdef GEMMLOWP_NEON +#include "./fixedpoint_neon.h" +#elif defined(GEMMLOWP_AVX2) +#include "./fixedpoint_avx.h" +#elif defined(GEMMLOWP_SSE4) +#include "./fixedpoint_sse.h" +#elif defined(GEMMLOWP_MSA) +#include "./fixedpoint_msa.h" +#endif + +#endif // GEMMLOWP_INTERNAL_FIXEDPOINT_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_neon.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_neon.h new file mode 100644 index 0000000..646c590 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_neon.h @@ -0,0 +1,331 @@ +// Copyright 2015 The Gemmlowp Authors. All Rights Reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// fixedpoint_neon.h: optimized NEON specializations of the templates +// in fixedpoint.h. + +#ifndef GEMMLOWP_INTERNAL_FIXEDPOINT_NEON_H_ +#define GEMMLOWP_INTERNAL_FIXEDPOINT_NEON_H_ + +#include + +namespace gemmlowp { + +template <> +struct FixedPointRawTypeTraits { + typedef std::int32_t ScalarRawType; + static constexpr int kLanes = 4; +}; + +template <> +struct FixedPointRawTypeTraits { + typedef std::int16_t ScalarRawType; + static constexpr int kLanes = 8; +}; + +template <> +inline int32x4_t BitAnd(int32x4_t a, int32x4_t b) { + return vandq_s32(a, b); +} + +template <> +inline int16x8_t BitAnd(int16x8_t a, int16x8_t b) { + return vandq_s16(a, b); +} + +template <> +inline int32x4_t BitOr(int32x4_t a, int32x4_t b) { + return vorrq_s32(a, b); +} + +template <> +inline int16x8_t BitOr(int16x8_t a, int16x8_t b) { + return vorrq_s16(a, b); +} + +template <> +inline int32x4_t BitXor(int32x4_t a, int32x4_t b) { + return veorq_s32(a, b); +} + +template <> +inline int16x8_t BitXor(int16x8_t a, int16x8_t b) { + return veorq_s16(a, b); +} + +template <> +inline int32x4_t BitNot(int32x4_t a) { + return veorq_s32(a, vdupq_n_s32(-1)); +} + +template <> +inline int16x8_t BitNot(int16x8_t a) { + return veorq_s16(a, vdupq_n_s16(-1)); +} + +template <> +inline int32x4_t Add(int32x4_t a, int32x4_t b) { + return vaddq_s32(a, b); +} + +template <> +inline int16x8_t Add(int16x8_t a, int16x8_t b) { + return vaddq_s16(a, b); +} + +template <> +inline int32x4_t Sub(int32x4_t a, int32x4_t b) { + return vsubq_s32(a, b); +} + +template <> +inline int16x8_t Sub(int16x8_t a, int16x8_t b) { + return vsubq_s16(a, b); +} + +template <> +inline int32x4_t Neg(int32x4_t a) { + return vnegq_s32(a); +} + +template <> +inline int16x8_t Neg(int16x8_t a) { + return vnegq_s16(a); +} + +template <> +inline int32x4_t ShiftLeft(int32x4_t a, int offset) { + return vshlq_s32(a, vdupq_n_s32(offset)); +} + +template <> +inline int16x8_t ShiftLeft(int16x8_t a, int offset) { + return vshlq_s16(a, vdupq_n_s16(offset)); +} + +template <> +inline int32x4_t ShiftRight(int32x4_t a, int offset) { + return vshlq_s32(a, vdupq_n_s32(-offset)); +} + +template <> +inline int16x8_t ShiftRight(int16x8_t a, int offset) { + return vshlq_s16(a, vdupq_n_s16(-offset)); +} + +template <> +inline int32x4_t SelectUsingMask(int32x4_t if_mask, int32x4_t then_val, + int32x4_t else_val) { + return vbslq_s32(vreinterpretq_u32_s32(if_mask), then_val, else_val); +} + +template <> +inline int16x8_t SelectUsingMask(int16x8_t if_mask, int16x8_t then_val, + int16x8_t else_val) { + return vbslq_s16(vreinterpretq_u16_s16(if_mask), then_val, else_val); +} + +template <> +inline int32x4_t MaskIfEqual(int32x4_t a, int32x4_t b) { + return vreinterpretq_s32_u32(vceqq_s32(a, b)); +} + +template <> +inline int16x8_t MaskIfEqual(int16x8_t a, int16x8_t b) { + return vreinterpretq_s16_u16(vceqq_s16(a, b)); +} + +template <> +inline int32x4_t MaskIfNotEqual(int32x4_t a, int32x4_t b) { + return BitNot(MaskIfEqual(a, b)); +} + +template <> +inline int16x8_t MaskIfNotEqual(int16x8_t a, int16x8_t b) { + return BitNot(MaskIfEqual(a, b)); +} + +template <> +inline int32x4_t MaskIfZero(int32x4_t a) { + return MaskIfEqual(a, vdupq_n_s32(0)); +} + +template <> +inline int16x8_t MaskIfZero(int16x8_t a) { + return MaskIfEqual(a, vdupq_n_s16(0)); +} + +template <> +inline int32x4_t MaskIfNonZero(int32x4_t a) { + return vreinterpretq_s32_u32(vtstq_s32(a, a)); +} + +template <> +inline int16x8_t MaskIfNonZero(int16x8_t a) { + return vreinterpretq_s16_u16(vtstq_s16(a, a)); +} + +template <> +inline int32x4_t MaskIfGreaterThan(int32x4_t a, int32x4_t b) { + return vreinterpretq_s32_u32(vcgtq_s32(a, b)); +} + +template <> +inline int16x8_t MaskIfGreaterThan(int16x8_t a, int16x8_t b) { + return vreinterpretq_s16_u16(vcgtq_s16(a, b)); +} + +template <> +inline int32x4_t MaskIfGreaterThanOrEqual(int32x4_t a, int32x4_t b) { + return vreinterpretq_s32_u32(vcgeq_s32(a, b)); +} + +template <> +inline int16x8_t MaskIfGreaterThanOrEqual(int16x8_t a, int16x8_t b) { + return vreinterpretq_s16_u16(vcgeq_s16(a, b)); +} + +template <> +inline int32x4_t MaskIfLessThan(int32x4_t a, int32x4_t b) { + return vreinterpretq_s32_u32(vcltq_s32(a, b)); +} + +template <> +inline int16x8_t MaskIfLessThan(int16x8_t a, int16x8_t b) { + return vreinterpretq_s16_u16(vcltq_s16(a, b)); +} + +template <> +inline int32x4_t MaskIfLessThanOrEqual(int32x4_t a, int32x4_t b) { + return vreinterpretq_s32_u32(vcleq_s32(a, b)); +} + +template <> +inline int16x8_t MaskIfLessThanOrEqual(int16x8_t a, int16x8_t b) { + return vreinterpretq_s16_u16(vcleq_s16(a, b)); +} + +template <> +inline bool All(int32x4_t a) { + a = vandq_s32(a, vextq_s32(a, a, 1)); + a = vandq_s32(a, vextq_s32(a, a, 2)); + return vgetq_lane_s32(a, 0); +} + +template <> +inline bool All(int16x8_t a) { + a = vandq_s16(a, vextq_s16(a, a, 1)); + a = vandq_s16(a, vextq_s16(a, a, 2)); + a = vandq_s16(a, vextq_s16(a, a, 4)); + return vgetq_lane_s16(a, 0); +} + +template <> +inline bool Any(int32x4_t a) { + a = vorrq_s32(a, vextq_s32(a, a, 1)); + a = vorrq_s32(a, vextq_s32(a, a, 2)); + return vgetq_lane_s32(a, 0); +} + +template <> +inline bool Any(int16x8_t a) { + a = vorrq_s16(a, vextq_s16(a, a, 1)); + a = vorrq_s16(a, vextq_s16(a, a, 2)); + a = vorrq_s16(a, vextq_s16(a, a, 4)); + return vgetq_lane_s16(a, 0); +} + +template <> +inline int32x4_t RoundingHalfSum(int32x4_t a, int32x4_t b) { + return vrhaddq_s32(a, b); +} + +template <> +inline int16x8_t RoundingHalfSum(int16x8_t a, int16x8_t b) { + return vrhaddq_s16(a, b); +} + +template <> +inline int32x4_t SaturatingRoundingDoublingHighMul(int32x4_t a, int32x4_t b) { + return vqrdmulhq_s32(a, b); +} + +template <> +inline int16x8_t SaturatingRoundingDoublingHighMul(int16x8_t a, int16x8_t b) { + return vqrdmulhq_s16(a, b); +} + +template <> +inline int32x4_t RoundingDivideByPOT(int32x4_t x, int exponent) { + const int32x4_t shift_vec = vdupq_n_s32(-exponent); + const int32x4_t fixup = vshrq_n_s32(vandq_s32(x, shift_vec), 31); + const int32x4_t fixed_up_x = vqaddq_s32(x, fixup); + return vrshlq_s32(fixed_up_x, shift_vec); +} + +template <> +inline int16x8_t RoundingDivideByPOT(int16x8_t x, int exponent) { + const int16x8_t shift_vec = vdupq_n_s16(-exponent); + const int16x8_t fixup = vshrq_n_s16(vandq_s16(x, shift_vec), 15); + const int16x8_t fixed_up_x = vqaddq_s16(x, fixup); + return vrshlq_s16(fixed_up_x, shift_vec); +} + +template +struct ImplSaturatingRoundingMultiplyByPOT { + static int32x4_t eval(int32x4_t x) { return vqshlq_n_s32(x, Exponent); } +}; + +template +struct ImplSaturatingRoundingMultiplyByPOT { + static int32x4_t eval(int32x4_t x) { + const int32x4_t fixup = vshrq_n_s32(x, 31); + const int32x4_t fixed_up_x = vqaddq_s32(x, fixup); + return vrshrq_n_s32(fixed_up_x, -Exponent); + } +}; + +template +struct ImplSaturatingRoundingMultiplyByPOT { + static int16x8_t eval(int16x8_t x) { return vqshlq_n_s16(x, Exponent); } +}; + +template +struct ImplSaturatingRoundingMultiplyByPOT { + static int16x8_t eval(int16x8_t x) { + const int16x8_t fixup = vshrq_n_s16(x, 15); + const int16x8_t fixed_up_x = vqaddq_s16(x, fixup); + return vrshrq_n_s16(fixed_up_x, -Exponent); + } +}; + +template <> +inline int32x4_t Dup(std::int32_t x) { + return vdupq_n_s32(x); +} + +template <> +inline int16x8_t Dup(std::int16_t x) { + return vdupq_n_s16(x); +} + +// So far this is only needed for int16. +template <> +inline int16x8_t SaturatingAdd(int16x8_t a, int16x8_t b) { + return vqaddq_s16(a, b); +} + +} // end namespace gemmlowp + +#endif // GEMMLOWP_INTERNAL_FIXEDPOINT_NEON_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_sse.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_sse.h new file mode 100644 index 0000000..a1fae32 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/fixedpoint/fixedpoint_sse.h @@ -0,0 +1,384 @@ +// Copyright 2015 Google Inc. All Rights Reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// fixedpoint_SSE.h: optimized SSE specializations of the templates +// in fixedpoint.h. + +#ifndef GEMMLOWP_INTERNAL_FIXEDPOINT_SSE_H_ +#define GEMMLOWP_INTERNAL_FIXEDPOINT_SSE_H_ + +#include +#include "fixedpoint.h" + +namespace gemmlowp { + +// SSE intrinsics are not finely typed: there is a single __m128i vector +// type that does not distinguish between "int32x4" and "int16x8" use +// cases, unlike the NEON equivalents. Because we had initially focused +// on int32x4, we did not pay attention and specialized these fixedpoint +// templates directly for __m128i hardcoding the int32x4 semantics, +// not leaving room for int16x8 semantics. Amending that by adding a separate +// data type, int16x8_m128i, that wraps __m128i while being a separate +// type. +struct int16x8_m128i { + int16x8_m128i() {} + explicit int16x8_m128i(__m128i w) : v(w) {} + ~int16x8_m128i() {} + + __m128i v; +}; + +template <> +struct FixedPointRawTypeTraits<__m128i> { + typedef std::int32_t ScalarRawType; + static constexpr int kLanes = 4; +}; + +template <> +struct FixedPointRawTypeTraits { + typedef std::int16_t ScalarRawType; + static constexpr int kLanes = 8; +}; + +template <> +inline __m128i BitAnd(__m128i a, __m128i b) { + return _mm_and_si128(a, b); +} + +template <> +inline int16x8_m128i BitAnd(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_and_si128(a.v, b.v)); +} + +template <> +inline __m128i BitOr(__m128i a, __m128i b) { + return _mm_or_si128(a, b); +} + +template <> +inline int16x8_m128i BitOr(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_or_si128(a.v, b.v)); +} + +template <> +inline __m128i BitXor(__m128i a, __m128i b) { + return _mm_xor_si128(a, b); +} + +template <> +inline int16x8_m128i BitXor(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_xor_si128(a.v, b.v)); +} + +template <> +inline __m128i BitNot(__m128i a) { + return _mm_andnot_si128(a, _mm_set1_epi32(-1)); +} + +template <> +inline int16x8_m128i BitNot(int16x8_m128i a) { + return int16x8_m128i(_mm_andnot_si128(a.v, _mm_set1_epi16(-1))); +} + +template <> +inline __m128i Add(__m128i a, __m128i b) { + return _mm_add_epi32(a, b); +} + +template <> +inline int16x8_m128i Add(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_add_epi16(a.v, b.v)); +} + +template <> +inline __m128i Mul(__m128i a, __m128i b) { + return _mm_mullo_epi32(a, b); +} + +template <> +inline int16x8_m128i Mul(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_mullo_epi16(a.v, b.v)); +} + +template <> +inline __m128i Sub(__m128i a, __m128i b) { + return _mm_sub_epi32(a, b); +} + +template <> +inline int16x8_m128i Sub(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_sub_epi16(a.v, b.v)); +} + +template <> +inline __m128i Neg(__m128i a) { + return _mm_sign_epi32(a, _mm_set1_epi32(-1)); +} + +template <> +inline int16x8_m128i Neg(int16x8_m128i a) { + return int16x8_m128i(_mm_sign_epi16(a.v, _mm_set1_epi16(-1))); +} + +template <> +inline __m128i ShiftLeft(__m128i a, int offset) { + return _mm_slli_epi32(a, offset); +} + +template <> +inline int16x8_m128i ShiftLeft(int16x8_m128i a, int offset) { + return int16x8_m128i(_mm_slli_epi16(a.v, offset)); +} + +template <> +inline __m128i ShiftRight(__m128i a, int offset) { + return _mm_srai_epi32(a, offset); +} + +template <> +inline int16x8_m128i ShiftRight(int16x8_m128i a, int offset) { + return int16x8_m128i(_mm_srai_epi16(a.v, offset)); +} + +template <> +inline __m128i SelectUsingMask(__m128i if_mask, __m128i then_val, + __m128i else_val) { + // borrowed from Intel's arm_neon_sse.h header. + return _mm_or_si128(_mm_and_si128(if_mask, then_val), + _mm_andnot_si128(if_mask, else_val)); +} + +template <> +inline int16x8_m128i SelectUsingMask(int16x8_m128i if_mask, + int16x8_m128i then_val, + int16x8_m128i else_val) { + // borrowed from Intel's arm_neon_sse.h header. + return int16x8_m128i(SelectUsingMask(if_mask.v, then_val.v, else_val.v)); +} + +template <> +inline __m128i MaskIfEqual(__m128i a, __m128i b) { + return _mm_cmpeq_epi32(a, b); +} + +template <> +inline int16x8_m128i MaskIfEqual(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_cmpeq_epi16(a.v, b.v)); +} + +template <> +inline __m128i MaskIfNotEqual(__m128i a, __m128i b) { + return BitNot(MaskIfEqual(a, b)); +} + +template <> +inline int16x8_m128i MaskIfNotEqual(int16x8_m128i a, int16x8_m128i b) { + return BitNot(MaskIfEqual(a, b)); +} + +template <> +inline __m128i MaskIfZero(__m128i a) { + return MaskIfEqual(a, _mm_set1_epi32(0)); +} + +template <> +inline int16x8_m128i MaskIfZero(int16x8_m128i a) { + return MaskIfEqual(a, int16x8_m128i(_mm_set1_epi16(0))); +} + +template <> +inline __m128i MaskIfNonZero(__m128i a) { + return MaskIfNotEqual(a, _mm_set1_epi32(0)); +} + +template <> +inline int16x8_m128i MaskIfNonZero(int16x8_m128i a) { + return MaskIfNotEqual(a, int16x8_m128i(_mm_set1_epi16(0))); +} + +template <> +inline __m128i MaskIfGreaterThan(__m128i a, __m128i b) { + return _mm_cmpgt_epi32(a, b); +} + +template <> +inline int16x8_m128i MaskIfGreaterThan(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_cmpgt_epi16(a.v, b.v)); +} + +template <> +inline __m128i MaskIfLessThan(__m128i a, __m128i b) { + return _mm_cmplt_epi32(a, b); +} + +template <> +inline int16x8_m128i MaskIfLessThan(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_cmplt_epi16(a.v, b.v)); +} + +template <> +inline __m128i MaskIfGreaterThanOrEqual(__m128i a, __m128i b) { + return BitNot(MaskIfLessThan(a, b)); +} + +template <> +inline int16x8_m128i MaskIfGreaterThanOrEqual(int16x8_m128i a, + int16x8_m128i b) { + return BitNot(MaskIfLessThan(a, b)); +} + +template <> +inline __m128i MaskIfLessThanOrEqual(__m128i a, __m128i b) { + return BitNot(MaskIfGreaterThan(a, b)); +} + +template <> +inline int16x8_m128i MaskIfLessThanOrEqual(int16x8_m128i a, int16x8_m128i b) { + return BitNot(MaskIfGreaterThan(a, b)); +} + +/* Assumptions: + - All and Any are used on masks. + - masks are all_ones for true lanes, all_zeroes otherwise. +Hence, All means all 128bits set, and Any means any bit set. +*/ + +template <> +inline bool All(__m128i a) { + return _mm_testc_si128(a, a); +} + +template <> +inline bool All(int16x8_m128i a) { + return _mm_testc_si128(a.v, a.v); +} + +template <> +inline bool Any(__m128i a) { + return !_mm_testz_si128(a, a); +} + +template <> +inline bool Any(int16x8_m128i a) { + return !_mm_testz_si128(a.v, a.v); +} + +template <> +inline __m128i RoundingHalfSum(__m128i a, __m128i b) { + /* __m128i round_bit_mask, a_over_2, b_over_2, round_bit, sum; */ + /* We divide the inputs before the add to avoid the overflow and costly test + */ + /* of checking if an overflow occured on signed add */ + /* round_bit_mask = _mm_set1_epi32(1); */ + /* a_over_2 = _mm_srai_epi32(a, 1); */ + /* b_over_2 = _mm_srai_epi32(b, 1); */ + /* sum = Add(a_over_2, b_over_2); */ + /* round_bit = _mm_sign_epi32(BitAnd(BitOr(a,b), round_bit_mask), sum); */ + /* return Add(sum, round_bit); */ + + /* Other possibility detecting overflow and xor the sign if an overflow + * happened*/ + __m128i one, sign_bit_mask, sum, rounded_half_sum, overflow, result; + one = _mm_set1_epi32(1); + sign_bit_mask = _mm_set1_epi32(0x80000000); + sum = Add(a, b); + rounded_half_sum = _mm_srai_epi32(Add(sum, one), 1); + overflow = + BitAnd(BitAnd(BitXor(a, rounded_half_sum), BitXor(b, rounded_half_sum)), + sign_bit_mask); + result = BitXor(rounded_half_sum, overflow); + return result; +} + +template <> +inline int16x8_m128i RoundingHalfSum(int16x8_m128i a, int16x8_m128i b) { + // Idea: go to unsigned to use _mm_avg_epu16, + // borrowed from Intel's arm_neon_sse.h header. + __m128i constant_neg_32768 = _mm_set1_epi16(-32768); + __m128i a_unsigned = _mm_sub_epi16(a.v, constant_neg_32768); + __m128i b_unsigned = _mm_sub_epi16(b.v, constant_neg_32768); + __m128i avg_unsigned = _mm_avg_epu16(a_unsigned, b_unsigned); + __m128i avg = _mm_add_epi16(avg_unsigned, constant_neg_32768); + return int16x8_m128i(avg); +} + +template <> +inline __m128i SaturatingRoundingDoublingHighMul(__m128i a, __m128i b) { + __m128i min, saturation_mask, a0_a2, a1_a3, b0_b2, b1_b3; + __m128i a0b0_a2b2, a1b1_a3b3, a0b0_a2b2_rounded, a1b1_a3b3_rounded; + __m128i a0b0_a2b2_rounded_2x, a1b1_a3b3_rounded_2x, result; + __m128i nudge; + + // saturation only happen if a == b == INT_MIN + min = _mm_set1_epi32(std::numeric_limits::min()); + saturation_mask = BitAnd(MaskIfEqual(a, b), MaskIfEqual(a, min)); + + // a = a0 | a1 | a2 | a3 + // b = b0 | b1 | b2 | b3 + a0_a2 = a; + a1_a3 = _mm_srli_si128(a, 4); + b0_b2 = b; + b1_b3 = _mm_srli_si128(b, 4); + + a0b0_a2b2 = _mm_mul_epi32(a0_a2, b0_b2); + a1b1_a3b3 = _mm_mul_epi32(a1_a3, b1_b3); + + // do the rounding and take into account that it will be doubled + nudge = _mm_set1_epi64x(1 << 30); + a0b0_a2b2_rounded = _mm_add_epi64(a0b0_a2b2, nudge); + a1b1_a3b3_rounded = _mm_add_epi64(a1b1_a3b3, nudge); + + // do the doubling + a0b0_a2b2_rounded_2x = _mm_slli_epi64(a0b0_a2b2_rounded, 1); + a1b1_a3b3_rounded_2x = _mm_slli_epi64(a1b1_a3b3_rounded, 1); + + // get the high part of the products + result = _mm_blend_epi16(_mm_srli_si128(a0b0_a2b2_rounded_2x, 4), + a1b1_a3b3_rounded_2x, 0xcc); + + // saturate those which overflowed + return SelectUsingMask(saturation_mask, min, result); +} + +template <> +inline int16x8_m128i SaturatingRoundingDoublingHighMul(int16x8_m128i a, + int16x8_m128i b) { + // Idea: use _mm_mulhrs_epi16 then saturate with a bit-operation, + // borrowed from Intel's arm_neon_sse.h header. + __m128i result_unsaturated = _mm_mulhrs_epi16(a.v, b.v); + __m128i saturation_mask = + _mm_cmpeq_epi16(result_unsaturated, _mm_set1_epi16(0x8000)); + __m128i result = _mm_xor_si128(result_unsaturated, saturation_mask); + return int16x8_m128i(result); +} + +template <> +inline __m128i Dup<__m128i>(std::int32_t x) { + return _mm_set1_epi32(x); +} + +template <> +inline int16x8_m128i Dup(std::int16_t x) { + return int16x8_m128i(_mm_set1_epi16(x)); +} + +// So far this is only needed for int16. +template <> +inline int16x8_m128i SaturatingAdd(int16x8_m128i a, int16x8_m128i b) { + return int16x8_m128i(_mm_adds_epi16(a.v, b.v)); +} + +} // end namespace gemmlowp + +#endif // GEMMLOWP_INTERNAL_FIXEDPOINT_SSE_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/internal/detect_platform.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/internal/detect_platform.h new file mode 100644 index 0000000..6f06d19 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/gemmlowp/internal/detect_platform.h @@ -0,0 +1,166 @@ +// Copyright 2018 The Gemmlowp Authors. All Rights Reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// detect_platform.h: Sets up macros that control architecture-specific +// features of gemmlowp's implementation. + +#ifndef GEMMLOWP_INTERNAL_DETECT_PLATFORM_H_ +#define GEMMLOWP_INTERNAL_DETECT_PLATFORM_H_ + +// Our inline assembly path assume GCC/Clang syntax. +// Native Client doesn't seem to support inline assembly(?). +#if defined(__GNUC__) && !defined(__native_client__) +#define GEMMLOWP_ALLOW_INLINE_ASM +#endif + +// Define macro statement that avoids inlining for GCC. +// For non-GCC, define as empty macro. +#if defined(__GNUC__) +#define GEMMLOWP_NOINLINE __attribute__((noinline)) +#else +#define GEMMLOWP_NOINLINE +#endif + +// Detect ARM, 32-bit or 64-bit +#ifdef __arm__ +#define GEMMLOWP_ARM_32 +#endif + +#ifdef __aarch64__ +#define GEMMLOWP_ARM_64 +#endif + +#if defined(GEMMLOWP_ARM_32) || defined(GEMMLOWP_ARM_64) +#define GEMMLOWP_ARM +#endif + +// Detect MIPS, 32-bit or 64-bit +#if defined(__mips) && !defined(__LP64__) +#define GEMMLOWP_MIPS_32 +#endif + +#if defined(__mips) && defined(__LP64__) +#define GEMMLOWP_MIPS_64 +#endif + +#if defined(GEMMLOWP_MIPS_32) || defined(GEMMLOWP_MIPS_64) +#define GEMMLOWP_MIPS +#endif + +// Detect x86, 32-bit or 64-bit +#if defined(__i386__) || defined(_M_IX86) || defined(_X86_) || defined(__i386) +#define GEMMLOWP_X86_32 +#endif + +#if defined(__x86_64__) || defined(_M_X64) || defined(__amd64) +#define GEMMLOWP_X86_64 +#endif + +#if defined(GEMMLOWP_X86_32) || defined(GEMMLOWP_X86_64) +#define GEMMLOWP_X86 +#endif + +// Some of our optimized paths use inline assembly and for +// now we don't bother enabling some other optimized paths using intrinddics +// where we can't use inline assembly paths. +#ifdef GEMMLOWP_ALLOW_INLINE_ASM + +// Detect NEON. It's important to check for both tokens. +#if (defined __ARM_NEON) || (defined __ARM_NEON__) +#define GEMMLOWP_NEON +#endif + +// Convenience NEON tokens for 32-bit or 64-bit +#if defined(GEMMLOWP_NEON) && defined(GEMMLOWP_ARM_32) +#define GEMMLOWP_NEON_32 +#endif + +#if defined(GEMMLOWP_NEON) && defined(GEMMLOWP_ARM_64) +#define GEMMLOWP_NEON_64 +#endif + +// Detect MIPS MSA. +// Limit MSA optimizations to little-endian CPUs for now. +// TODO: Perhaps, eventually support MSA optimizations on big-endian CPUs? +#if defined(GEMMLOWP_MIPS) && (__mips_isa_rev >= 5) && defined(__mips_msa) && \ + defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) +#define GEMMLOWP_MSA +#endif + +// Convenience MIPS MSA tokens for 32-bit or 64-bit. +#if defined(GEMMLOWP_MSA) && defined(GEMMLOWP_MIPS_32) +#define GEMMLOWP_MSA_32 +#endif + +#if defined(GEMMLOWP_MSA) && defined(GEMMLOWP_MIPS_64) +#define GEMMLOWP_MSA_64 +#endif + +// compiler define for AVX2 -D GEMMLOWP_ENABLE_AVX2 +// Detect AVX2 +#if defined(__AVX2__) && defined(GEMMLOWP_ENABLE_AVX2) +#define GEMMLOWP_AVX2 +// Detect SSE4. +// MSVC does not have __SSE4_1__ macro, but will enable SSE4 +// when AVX is turned on. +#elif defined(__SSE4_1__) || (defined(_MSC_VER) && defined(__AVX__)) +#define GEMMLOWP_SSE4 +// Detect SSE3. +#elif defined(__SSE3__) +#define GEMMLOWP_SSE3 +#endif + +// Convenience SSE4 tokens for 32-bit or 64-bit +#if defined(GEMMLOWP_SSE4) && defined(GEMMLOWP_X86_32) && \ + !defined(GEMMLOWP_DISABLE_SSE4) +#define GEMMLOWP_SSE4_32 +#endif + +#if defined(GEMMLOWP_SSE3) && defined(GEMMLOWP_X86_32) +#define GEMMLOWP_SSE3_32 +#endif + +#if defined(GEMMLOWP_SSE4) && defined(GEMMLOWP_X86_64) && \ + !defined(GEMMLOWP_DISABLE_SSE4) +#define GEMMLOWP_SSE4_64 +#endif + +#if defined(GEMMLOWP_SSE3) && defined(GEMMLOWP_X86_64) +#define GEMMLOWP_SSE3_64 +#endif + +#if defined(GEMMLOWP_AVX2) && defined(GEMMLOWP_X86_64) +#define GEMMLOWP_AVX2_64 +#endif + +#if defined(__has_feature) +#if __has_feature(memory_sanitizer) +#include +#define GEMMLOWP_MARK_MEMORY_AS_INITIALIZED __msan_unpoison +#elif __has_feature(address_sanitizer) +#include +#define GEMMLOWP_MARK_MEMORY_AS_INITIALIZED __asan_unpoison_memory_region +#endif +#endif + +#endif // GEMMLOWP_ALLOW_INLINE_ASM + +// Detect Android. Don't conflate with ARM - we care about tuning +// for non-ARM Android devices too. This can be used in conjunction +// with x86 to tune differently for mobile x86 CPUs (Atom) vs. desktop x86 CPUs. +#if defined(__ANDROID__) || defined(ANDROID) +#define GEMMLOWP_ANDROID +#endif + +#endif // GEMMLOWP_INTERNAL_DETECT_PLATFORM_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h new file mode 100644 index 0000000..c4df1e6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/edge-impulse-sdk/third_party/ruy/ruy/profiler/instrumentation.h @@ -0,0 +1,203 @@ +/* Copyright 2020 Google LLC. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef RUY_RUY_PROFILER_INSTRUMENTATION_H_ +#define RUY_RUY_PROFILER_INSTRUMENTATION_H_ + +#ifdef RUY_PROFILER +#include +#include +#include +#endif + +namespace ruy { +namespace profiler { + +#ifdef RUY_PROFILER + +// A label is how a code scope is annotated to appear in profiles. +// The stacks that are sampled by the profiler are stacks of such labels. +// A label consists of a literal string, plus optional integer arguments. +class Label { + public: + Label() {} + template + explicit Label(Args... args) { + Set(args...); + } + void Set(const char* format) { + format_ = format; + args_count_ = 0; + } + template + void Set(const char* format, Args... args) { + format_ = format; + args_count_ = sizeof...(args); + SetArgs(0, args...); + } + + void operator=(const Label& other); + + bool operator==(const Label& other) const; + + std::string Formatted() const; + const char* format() const { return format_; } + + private: + void SetArgs(int position, int arg0) { args_[position] = arg0; } + + template + void SetArgs(int position, int arg0, Args... args) { + SetArgs(position, arg0); + SetArgs(position + 1, args...); + } + + static constexpr int kMaxArgs = 4; + const char* format_ = nullptr; + int args_count_ = 0; + int args_[kMaxArgs]; +}; + +namespace detail { + +// Forward-declaration, see class ThreadStack below. +class ThreadStack; + +bool& GlobalIsProfilerRunning(); + +// Returns the global vector of pointers to all stacks, there being one stack +// per thread executing instrumented code. +std::vector* GlobalAllThreadStacks(); + +// Returns the mutex to be locked around any access to GlobalAllThreadStacks(). +std::mutex* GlobalsMutex(); + +// Returns the thread-local stack, specific to the current thread. +ThreadStack* ThreadLocalThreadStack(); + +// This 'stack' is what may be more appropriately called a 'pseudostack': +// It contains Label entries that are 'manually' entered by instrumentation +// code. It's unrelated to real call stacks. +struct Stack { + std::uint32_t id = 0; + static constexpr int kMaxSize = 64; + int size = 0; + Label labels[kMaxSize]; +}; + +// Returns the buffer byte size required by CopyToSample. +int GetBufferSize(const Stack& stack); + +// Copies this Stack into a byte buffer, called a 'sample'. +void CopyToBuffer(const Stack& stack, char* dst); + +// Populates this Stack from an existing sample buffer, typically +// produced by CopyToSample. +void ReadFromBuffer(const char* src, Stack* stack); + +// ThreadStack is meant to be used as a thread-local singleton, assigning to +// each thread a Stack object holding its pseudo-stack of profile labels, +// plus a mutex allowing to synchronize accesses to this pseudo-stack between +// this thread and a possible profiler thread sampling it. +class ThreadStack { + public: + ThreadStack(); + ~ThreadStack(); + + const Stack& stack() const { return stack_; } + + // Returns the mutex to lock around any access to this stack. Each stack is + // accessed by potentially two threads: the thread that it belongs to + // (which calls Push and Pop) and the profiler thread during profiling + // (which calls CopyToSample). + std::mutex& Mutex() const { return mutex_; } + + // Pushes a new label on the top of this Stack. + template + void Push(Args... args) { + // This mutex locking is needed to guard against race conditions as both + // the current thread and the profiler thread may be concurrently accessing + // this stack. In addition to that, this mutex locking also serves the other + // purpose of acting as a barrier (of compiler code reordering, of runtime + // CPU instruction reordering, and of memory access reordering), which + // gives a measure of correctness to this profiler. The downside is some + // latency. As this lock will be uncontended most of the times, the cost + // should be roughly that of an sequentially-consistent atomic access, + // comparable to an access to the level of CPU data cache that is shared + // among all cores, typically 60 cycles on current ARM CPUs, plus side + // effects from barrier instructions. + std::lock_guard lock(mutex_); + // Avoid overrunning the stack, even in 'release' builds. This profiling + // instrumentation code should not ship in release builds anyway, the + // overhead of this check is negligible, and overrunning a stack array would + // be bad. + if (stack_.size >= Stack::kMaxSize) { + abort(); + } + stack_.labels[stack_.size++].Set(args...); + } + + // Pops the top-most label from this Stack. + void Pop() { + // See the comment in Push about this lock. While it would be tempting to + // try to remove this lock and just atomically decrement size_ with a + // store-release, that would not necessarily be a substitute for all of the + // purposes that this lock serves, or if it was done carefully to serve all + // of the same purposes, then that wouldn't be faster than this (mostly + // uncontended) lock. + std::lock_guard lock(mutex_); + stack_.size--; + } + + private: + mutable std::mutex mutex_; + Stack stack_; +}; + +} // namespace detail + +// RAII user-facing way to construct Labels associated with their life scope +// and get them pushed to / popped from the current thread stack. +class ScopeLabel { + public: + template + ScopeLabel(Args... args) : thread_stack_(detail::ThreadLocalThreadStack()) { + thread_stack_->Push(args...); + } + + ~ScopeLabel() { thread_stack_->Pop(); } + + private: + detail::ThreadStack* thread_stack_; +}; + +#else // no RUY_PROFILER + +class ScopeLabel { + public: + template + explicit ScopeLabel(Args...) {} + + // This destructor is needed to consistently silence clang's -Wunused-variable + // which seems to trigger semi-randomly. + ~ScopeLabel() {} +}; + +#endif + +} // namespace profiler +} // namespace ruy + +#endif // RUY_RUY_PROFILER_INSTRUMENTATION_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/anomaly_metadata.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/anomaly_metadata.h new file mode 100644 index 0000000..3c7f5d2 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/anomaly_metadata.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2024 EdgeImpulse Inc. + * + * Generated by Edge Impulse and licensed under the applicable Edge Impulse + * Terms of Service. Community and Professional Terms of Service + * (https://docs.edgeimpulse.com/page/terms-of-service) or Enterprise Terms of + * Service (https://docs.edgeimpulse.com/page/enterprise-terms-of-service), + * according to your product plan subscription (the “License”). + * + * This software, documentation and other associated files (collectively referred + * to as the “Software”) is a single SDK variation generated by the Edge Impulse + * platform and requires an active paid Edge Impulse subscription to use this + * Software for any purpose. + * + * You may NOT use this Software unless you have an active Edge Impulse subscription + * that meets the eligibility requirements for the applicable License, subject to + * your full and continued compliance with the terms and conditions of the License, + * including without limitation any usage restrictions under the applicable License. + * + * If you do not have an active Edge Impulse product plan subscription, or if use + * of this Software exceeds the usage limitations of your Edge Impulse product plan + * subscription, you are not permitted to use this Software and must immediately + * delete and erase all copies of this Software within your control or possession. + * Edge Impulse reserves all rights and remedies available to enforce its rights. + * + * Unless required by applicable law or agreed to in writing, the Software is + * distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific language governing + * permissions, disclaimers and limitations under the License. + */ + +#ifndef _EI_CLASSIFIER_ANOMALY_METADATA_H_ +#define _EI_CLASSIFIER_ANOMALY_METADATA_H_ + +#include "edge-impulse-sdk/classifier/ei_model_types.h" + +const uint16_t ei_classifier_anom_axes[] = { 10, 20, 21, 22 }; + +// (before - mean) / scale +const float ei_classifier_anom_scale[4] = { 3.5554213574211886, 3.631274923461154, 1.2544628263586233, 3.4789077257377907 }; +const float ei_classifier_anom_mean[4] = { 3.072650739514246, 4.442065243912564, -1.0220593318908202, 2.8165316343991624 }; +const ei_classifier_anom_cluster_t ei_classifier_anom_clusters[10] = { + { ( float[4] ) { -0.4302690327167511, -0.5157585144042969, -0.45605042576789856, 0.1880578249692917 }, 0.5980749628081169 }, + { ( float[4] ) { -0.3290398120880127, -0.37850335240364075, 0.14749404788017273, -0.5175421237945557 }, 0.6542907989231638 }, + { ( float[4] ) { 0.7905887961387634, 1.096022129058838, 1.1115347146987915, -0.8244106769561768 }, 2.3656984038246223 }, + { ( float[4] ) { -0.09615929424762726, 0.17192387580871582, 1.6955640316009521, -0.30946528911590576 }, 1.8793978936700775 }, + { ( float[4] ) { -0.5398526191711426, -0.5995153784751892, -1.0127919912338257, 0.9784511923789978 }, 0.6955306962627714 }, + { ( float[4] ) { 2.086632251739502, 1.764082431793213, 0.9194198250770569, -0.8863421678543091 }, 1.711206206352889 }, + { ( float[4] ) { -0.8050190210342407, -0.6507596969604492, -1.7849925756454468, 2.1953675746917725 }, 0.6983371664579998 }, + { ( float[4] ) { 3.094244956970215, 4.224006175994873, 0.9576370716094971, -0.5145342946052551 }, 2.1599142232871262 }, + { ( float[4] ) { -0.010327845811843872, -0.04280847683548927, 0.7279984354972839, -0.8842476606369019 }, 1.0876545065847454 }, + { ( float[4] ) { 4.057709693908691, 2.495816230773926, 0.8436998128890991, -0.6405178904533386 }, 1.7640114124003214 }, +}; + +#endif // _EI_CLASSIFIER_ANOMALY_METADATA_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/model_metadata.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/model_metadata.h new file mode 100644 index 0000000..44e262a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/model_metadata.h @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2024 EdgeImpulse Inc. + * + * Generated by Edge Impulse and licensed under the applicable Edge Impulse + * Terms of Service. Community and Professional Terms of Service + * (https://docs.edgeimpulse.com/page/terms-of-service) or Enterprise Terms of + * Service (https://docs.edgeimpulse.com/page/enterprise-terms-of-service), + * according to your product plan subscription (the “License”). + * + * This software, documentation and other associated files (collectively referred + * to as the “Software”) is a single SDK variation generated by the Edge Impulse + * platform and requires an active paid Edge Impulse subscription to use this + * Software for any purpose. + * + * You may NOT use this Software unless you have an active Edge Impulse subscription + * that meets the eligibility requirements for the applicable License, subject to + * your full and continued compliance with the terms and conditions of the License, + * including without limitation any usage restrictions under the applicable License. + * + * If you do not have an active Edge Impulse product plan subscription, or if use + * of this Software exceeds the usage limitations of your Edge Impulse product plan + * subscription, you are not permitted to use this Software and must immediately + * delete and erase all copies of this Software within your control or possession. + * Edge Impulse reserves all rights and remedies available to enforce its rights. + * + * Unless required by applicable law or agreed to in writing, the Software is + * distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific language governing + * permissions, disclaimers and limitations under the License. + */ + +#ifndef _EI_CLASSIFIER_MODEL_METADATA_H_ +#define _EI_CLASSIFIER_MODEL_METADATA_H_ + +#include +#include +#include + +#define EI_CLASSIFIER_NONE 255 +#define EI_CLASSIFIER_UTENSOR 1 +#define EI_CLASSIFIER_TFLITE 2 +#define EI_CLASSIFIER_CUBEAI 3 +#define EI_CLASSIFIER_TFLITE_FULL 4 +#define EI_CLASSIFIER_TENSAIFLOW 5 +#define EI_CLASSIFIER_TENSORRT 6 +#define EI_CLASSIFIER_DRPAI 7 +#define EI_CLASSIFIER_TFLITE_TIDL 8 +#define EI_CLASSIFIER_AKIDA 9 +#define EI_CLASSIFIER_SYNTIANT 10 +#define EI_CLASSIFIER_ONNX_TIDL 11 +#define EI_CLASSIFIER_MEMRYX 12 + +#define EI_CLASSIFIER_SENSOR_UNKNOWN -1 +#define EI_CLASSIFIER_SENSOR_MICROPHONE 1 +#define EI_CLASSIFIER_SENSOR_ACCELEROMETER 2 +#define EI_CLASSIFIER_SENSOR_CAMERA 3 +#define EI_CLASSIFIER_SENSOR_9DOF 4 +#define EI_CLASSIFIER_SENSOR_ENVIRONMENTAL 5 +#define EI_CLASSIFIER_SENSOR_FUSION 6 + +#define EI_ANOMALY_TYPE_UNKNOWN 0 +#define EI_ANOMALY_TYPE_KMEANS 1 +#define EI_ANOMALY_TYPE_GMM 2 +#define EI_ANOMALY_TYPE_VISUAL_GMM 3 + +// These must match the enum values in TensorFlow Lite's "TfLiteType" +#define EI_CLASSIFIER_DATATYPE_FLOAT32 1 +#define EI_CLASSIFIER_DATATYPE_UINT8 3 +#define EI_CLASSIFIER_DATATYPE_INT8 9 + +#define EI_CLASSIFIER_PROJECT_ID 440960 +#define EI_CLASSIFIER_PROJECT_OWNER "Paula" +#define EI_CLASSIFIER_PROJECT_NAME "bike-3s-10Hz-5class" +#define EI_CLASSIFIER_PROJECT_DEPLOY_VERSION 10 +#define EI_CLASSIFIER_NN_INPUT_FRAME_SIZE 60 +#define EI_CLASSIFIER_RAW_SAMPLE_COUNT 31 +#define EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME 6 +#define EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE (EI_CLASSIFIER_RAW_SAMPLE_COUNT * EI_CLASSIFIER_RAW_SAMPLES_PER_FRAME) +#define EI_CLASSIFIER_INPUT_WIDTH 0 +#define EI_CLASSIFIER_INPUT_HEIGHT 0 +#define EI_CLASSIFIER_INPUT_FRAMES 0 +#define EI_CLASSIFIER_NN_OUTPUT_COUNT 5 +#define EI_CLASSIFIER_INTERVAL_MS 96 +#define EI_CLASSIFIER_LABEL_COUNT 5 +#define EI_CLASSIFIER_HAS_ANOMALY EI_ANOMALY_TYPE_KMEANS +#define EI_CLASSIFIER_HAS_VISUAL_ANOMALY 0 +#define EI_CLASSIFIER_SINGLE_FEATURE_INPUT 1 +#define EI_CLASSIFIER_FREQUENCY 10.416666666666666 +#define EI_CLASSIFIER_HAS_MODEL_VARIABLES 1 +#define EI_CLASSIFIER_THRESHOLD 0.4 + +#define EI_CLASSIFIER_OBJECT_DETECTION 0 +#define EI_CLASSIFIER_TFLITE_OUTPUT_DATA_TENSOR 0 +#define EI_CLASSIFIER_OBJECT_DETECTION_LAST_LAYER EI_CLASSIFIER_LAST_LAYER_UNKNOWN + +#define EI_CLASSIFIER_TFLITE_INPUT_DATATYPE EI_CLASSIFIER_DATATYPE_INT8 +#define EI_CLASSIFIER_TFLITE_OUTPUT_DATATYPE EI_CLASSIFIER_DATATYPE_INT8 + + +#define EI_CLASSIFIER_INFERENCING_ENGINE EI_CLASSIFIER_TFLITE + +#define EI_CLASSIFIER_QUANTIZATION_ENABLED 1 + +#define EI_CLASSIFIER_COMPILED 0 +#define EI_CLASSIFIER_HAS_TFLITE_OPS_RESOLVER 1 + +#define EI_CLASSIFIER_LOAD_IMAGE_SCALING 0 + + +#define EI_CLASSIFIER_HAS_FFT_INFO 1 +#define EI_CLASSIFIER_LOAD_FFT_32 0 +#define EI_CLASSIFIER_LOAD_FFT_64 0 +#define EI_CLASSIFIER_LOAD_FFT_128 0 +#define EI_CLASSIFIER_LOAD_FFT_256 0 +#define EI_CLASSIFIER_LOAD_FFT_512 0 +#define EI_CLASSIFIER_LOAD_FFT_1024 0 +#define EI_CLASSIFIER_LOAD_FFT_2048 0 +#define EI_CLASSIFIER_LOAD_FFT_4096 0 + +#define EI_DSP_PARAMS_GENERATED 1 +#define EI_DSP_PARAMS_SPECTRAL_ANALYSIS_ANALYSIS_TYPE_FFT 1 + +#define EI_CLASSIFIER_SENSOR EI_CLASSIFIER_SENSOR_FUSION +#define EI_CLASSIFIER_FUSION_AXES_STRING "AccX + AccY + AccZ + GyrX + GyrY + GyrZ" +#define EI_CLASSIFIER_CALIBRATION_ENABLED 0 + +#ifndef EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW +#define EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW 4 +#endif // EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW +#define EI_CLASSIFIER_SLICE_SIZE (EI_CLASSIFIER_RAW_SAMPLE_COUNT / EI_CLASSIFIER_SLICES_PER_MODEL_WINDOW) + +#define EI_STUDIO_VERSION_MAJOR 1 +#define EI_STUDIO_VERSION_MINOR 54 +#define EI_STUDIO_VERSION_PATCH 3 + +#define EI_CLASSIFIER_HR_ENABLED 0 + +#if ((EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) || (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI)) && EI_CLASSIFIER_USE_FULL_TFLITE == 1 + +#if EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE +#undef EI_CLASSIFIER_INFERENCING_ENGINE +#define EI_CLASSIFIER_INFERENCING_ENGINE EI_CLASSIFIER_TFLITE_FULL +#endif + +#undef EI_CLASSIFIER_HAS_TFLITE_OPS_RESOLVER +#define EI_CLASSIFIER_HAS_TFLITE_OPS_RESOLVER 0 + +#if EI_CLASSIFIER_COMPILED == 1 +#error "Cannot use full TensorFlow Lite with EON" +#endif +#endif // ((EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_TFLITE) || (EI_CLASSIFIER_INFERENCING_ENGINE == EI_CLASSIFIER_DRPAI)) && EI_CLASSIFIER_USE_FULL_TFLITE == 1 + +typedef struct { + const char *name; + int axis; +} ei_dsp_named_axis_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + float scale_axes; + bool average; + bool minimum; + bool maximum; + bool rms; + bool stdev; + bool skewness; + bool kurtosis; + int moving_avg_num_windows; +} ei_dsp_config_flatten_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + ei_dsp_named_axis_t * named_axes; + size_t named_axes_size; + const char * channels; +} ei_dsp_config_image_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + ei_dsp_named_axis_t * named_axes; + size_t named_axes_size; + int num_cepstral; + float frame_length; + float frame_stride; + int num_filters; + int fft_length; + int win_size; + int low_frequency; + int high_frequency; + float pre_cof; + int pre_shift; +} ei_dsp_config_mfcc_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + ei_dsp_named_axis_t * named_axes; + size_t named_axes_size; + float frame_length; + float frame_stride; + int num_filters; + int fft_length; + int low_frequency; + int high_frequency; + int win_size; + int noise_floor_db; +} ei_dsp_config_mfe_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + float scale_axes; +} ei_dsp_config_raw_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + float scale_axes; + int input_decimation_ratio; + const char * filter_type; + float filter_cutoff; + int filter_order; + const char * analysis_type; + int fft_length; + int spectral_peaks_count; + float spectral_peaks_threshold; + const char * spectral_power_edges; + bool do_log; + bool do_fft_overlap; + int wavelet_level; + const char * wavelet; + bool extra_low_freq; +} ei_dsp_config_spectral_analysis_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + ei_dsp_named_axis_t * named_axes; + size_t named_axes_size; + float frame_length; + float frame_stride; + int fft_length; + int noise_floor_db; + bool show_axes; +} ei_dsp_config_spectrogram_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + ei_dsp_named_axis_t * named_axes; + size_t named_axes_size; + float frame_length; + float frame_stride; + int num_filters; + int fft_length; + int low_frequency; + int high_frequency; + float pre_cof; + const char * extractor; +} ei_dsp_config_audio_syntiant_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + bool scaling; + bool scaling_raw; + bool padding; +} ei_dsp_config_imu_syntiant_t; + +typedef struct { + uint32_t block_id; + uint16_t implementation_version; + int axes; + ei_dsp_named_axis_t * named_axes; + size_t named_axes_size; + const char * ppg_ecg; + int filter_preset; + float sensitivity; + float acc_resting_std; + const char * hrv_features; + bool include_hr; + float hrv_update_interval_s; + float hrv_win_size_s; +} ei_dsp_config_hr_t; + +#endif // _EI_CLASSIFIER_MODEL_METADATA_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/model_variables.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/model_variables.h new file mode 100644 index 0000000..d27ac41 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/model-parameters/model_variables.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2024 EdgeImpulse Inc. + * + * Generated by Edge Impulse and licensed under the applicable Edge Impulse + * Terms of Service. Community and Professional Terms of Service + * (https://docs.edgeimpulse.com/page/terms-of-service) or Enterprise Terms of + * Service (https://docs.edgeimpulse.com/page/enterprise-terms-of-service), + * according to your product plan subscription (the “License”). + * + * This software, documentation and other associated files (collectively referred + * to as the “Software”) is a single SDK variation generated by the Edge Impulse + * platform and requires an active paid Edge Impulse subscription to use this + * Software for any purpose. + * + * You may NOT use this Software unless you have an active Edge Impulse subscription + * that meets the eligibility requirements for the applicable License, subject to + * your full and continued compliance with the terms and conditions of the License, + * including without limitation any usage restrictions under the applicable License. + * + * If you do not have an active Edge Impulse product plan subscription, or if use + * of this Software exceeds the usage limitations of your Edge Impulse product plan + * subscription, you are not permitted to use this Software and must immediately + * delete and erase all copies of this Software within your control or possession. + * Edge Impulse reserves all rights and remedies available to enforce its rights. + * + * Unless required by applicable law or agreed to in writing, the Software is + * distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific language governing + * permissions, disclaimers and limitations under the License. + */ + +#ifndef _EI_CLASSIFIER_MODEL_VARIABLES_H_ +#define _EI_CLASSIFIER_MODEL_VARIABLES_H_ + +#include +#include "model_metadata.h" +#include "anomaly_metadata.h" +#include "tflite-model/tflite_learn_5.h" + +#include "edge-impulse-sdk/classifier/ei_model_types.h" +#include "edge-impulse-sdk/classifier/inferencing_engines/engines.h" + +const char* ei_classifier_inferencing_categories[] = { "asphalt", "compacted", "paving", "sett", "standing" }; + +uint8_t ei_dsp_config_4_axes[] = { 0, 1, 2, 3, 4, 5 }; +const uint32_t ei_dsp_config_4_axes_size = 6; +ei_dsp_config_spectral_analysis_t ei_dsp_config_4 = { + 4, // uint32_t blockId + 4, // int implementationVersion + 6, // int length of axes + 1.0f, // float scale-axes + 1, // int input-decimation-ratio + "low", // select filter-type + 3.0f, // float filter-cutoff + 6, // int filter-order + "FFT", // select analysis-type + 16, // int fft-length + 3, // int spectral-peaks-count + 0.1f, // float spectral-peaks-threshold + "0.1, 0.5, 1.0, 2.0, 5.0", // string spectral-power-edges + true, // boolean do-log + true, // boolean do-fft-overlap + 1, // int wavelet-level + "db4", // select wavelet + false // boolean extra-low-freq +}; + +const size_t ei_dsp_blocks_size = 1; +ei_model_dsp_t ei_dsp_blocks[ei_dsp_blocks_size] = { + { // DSP block 4 + 4, + 60, // output size + &extract_spectral_analysis_features, // DSP function pointer + (void*)&ei_dsp_config_4, // pointer to config struct + ei_dsp_config_4_axes, // array of offsets into the input stream, one for each axis + ei_dsp_config_4_axes_size, // number of axes + 1, // version + nullptr, // factory function + } +}; +const ei_config_tflite_graph_t ei_config_tflite_graph_5 = { + .implementation_version = 1, + .model = tflite_learn_5, + .model_size = tflite_learn_5_len, + .arena_size = tflite_learn_5_arena_size +}; + + +const ei_learning_block_config_tflite_graph_t ei_learning_block_config_5 = { + .implementation_version = 1, + .classification_mode = EI_CLASSIFIER_CLASSIFICATION_MODE_CLASSIFICATION, + .block_id = 5, + .object_detection = 0, + .object_detection_last_layer = EI_CLASSIFIER_LAST_LAYER_UNKNOWN, + .output_data_tensor = 0, + .output_labels_tensor = 1, + .output_score_tensor = 2, + .threshold = 0, + .quantized = 1, + .compiled = 0, + .graph_config = (void*)&ei_config_tflite_graph_5 +}; + +const ei_learning_block_config_anomaly_kmeans_t ei_learning_block_config_8 = { + .implementation_version = 1, + .classification_mode = EI_CLASSIFIER_CLASSIFICATION_MODE_ANOMALY_KMEANS, + .anom_axis = ei_classifier_anom_axes, + .anom_axes_size = 4, + .anom_clusters = ei_classifier_anom_clusters, + .anom_cluster_count = 10, + .anom_scale = ei_classifier_anom_scale, + .anom_mean = ei_classifier_anom_mean, +}; + +const size_t ei_learning_blocks_size = 2; +const uint32_t ei_learning_block_5_inputs[1] = { 4 }; +const uint32_t ei_learning_block_5_inputs_size = 1; +const uint32_t ei_learning_block_8_inputs[1] = { 4 }; +const uint32_t ei_learning_block_8_inputs_size = 1; +const ei_learning_block_t ei_learning_blocks[ei_learning_blocks_size] = { + { + 5, + false, + &run_nn_inference, + (void*)&ei_learning_block_config_5, + EI_CLASSIFIER_IMAGE_SCALING_NONE, + ei_learning_block_5_inputs, + ei_learning_block_5_inputs_size, + 5 + }, + { + 8, + false, + &run_kmeans_anomaly, + (void*)&ei_learning_block_config_8, + EI_CLASSIFIER_IMAGE_SCALING_NONE, + ei_learning_block_8_inputs, + ei_learning_block_8_inputs_size, + 1 + }, +}; + +const ei_model_performance_calibration_t ei_calibration = { + 1, /* integer version number */ + false, /* has configured performance calibration */ + (int32_t)(EI_CLASSIFIER_RAW_SAMPLE_COUNT / ((EI_CLASSIFIER_FREQUENCY > 0) ? EI_CLASSIFIER_FREQUENCY : 1)) * 1000, /* Model window */ + 0.8f, /* Default threshold */ + (int32_t)(EI_CLASSIFIER_RAW_SAMPLE_COUNT / ((EI_CLASSIFIER_FREQUENCY > 0) ? EI_CLASSIFIER_FREQUENCY : 1)) * 500, /* Half of model window */ + 0 /* Don't use flags */ +}; +const ei_object_detection_nms_config_t ei_object_detection_nms = { + 0.0f, /* NMS confidence threshold */ + 0.2f /* NMS IOU threshold */ +}; + +const ei_impulse_t impulse_440960_0 = { + .project_id = 440960, + .project_owner = "Paula", + .project_name = "bike-3s-10Hz-5class", + .deploy_version = 10, + + .nn_input_frame_size = 60, + .raw_sample_count = 31, + .raw_samples_per_frame = 6, + .dsp_input_frame_size = 31 * 6, + .input_width = 0, + .input_height = 0, + .input_frames = 0, + .interval_ms = 96, + .frequency = 10.416666666666666, + .dsp_blocks_size = ei_dsp_blocks_size, + .dsp_blocks = ei_dsp_blocks, + + .object_detection_count = 0, + .fomo_output_size = 0, + + .tflite_output_features_count = 5, + .learning_blocks_size = ei_learning_blocks_size, + .learning_blocks = ei_learning_blocks, + + .inferencing_engine = EI_CLASSIFIER_TFLITE, + + .sensor = EI_CLASSIFIER_SENSOR_FUSION, + .fusion_string = "AccX + AccY + AccZ + GyrX + GyrY + GyrZ", + .slice_size = (31/4), + .slices_per_model_window = 4, + + .has_anomaly = EI_ANOMALY_TYPE_KMEANS, + .label_count = 5, + .calibration = ei_calibration, + .categories = ei_classifier_inferencing_categories, + .object_detection_nms = ei_object_detection_nms +}; + +ei_impulse_handle_t impulse_handle_440960_0 = ei_impulse_handle_t( &impulse_440960_0 ); +ei_impulse_handle_t& ei_default_impulse = impulse_handle_440960_0; + +#endif // _EI_CLASSIFIER_MODEL_METADATA_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/surface_inferencing.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/surface_inferencing.h new file mode 100644 index 0000000..5048860 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/surface_inferencing.h @@ -0,0 +1,56 @@ +/* Edge Impulse ingestion SDK + * Copyright (c) 2022 EdgeImpulse Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef _INFERENCE_H +#define _INFERENCE_H + +// Undefine min/max macros as these conflict with C++ std min/max functions +// these are often included by Arduino cores +#include +#include +#ifdef min +#undef min +#endif // min +#ifdef max +#undef max +#endif // max +#ifdef round +#undef round +#endif // round +// Similar the ESP32 seems to define this, which is also used as an enum value in TFLite +#ifdef DEFAULT +#undef DEFAULT +#endif // DEFAULT +// Infineon core defines this, conflicts with CMSIS/DSP/Include/dsp/controller_functions.h +#ifdef A0 +#undef A0 +#endif // A0 +#ifdef A1 +#undef A1 +#endif // A1 +#ifdef A2 +#undef A2 +#endif // A2 + +/* Includes ---------------------------------------------------------------- */ +#include "edge-impulse-sdk/classifier/ei_run_classifier.h" +#include "edge-impulse-sdk/dsp/numpy.hpp" +#include "model-parameters/model_metadata.h" +#include "edge-impulse-sdk/classifier/ei_classifier_smooth.h" + +extern void ei_printf(const char *format, ...); + +#endif // _INFERENCE_H diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite-resolver.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite-resolver.h new file mode 100644 index 0000000..6599548 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite-resolver.h @@ -0,0 +1,31 @@ +/* Generated by Edge Impulse + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + #ifndef _EI_CLASSIFIER_TFLITE_RESOLVER_H_ + #define _EI_CLASSIFIER_TFLITE_RESOLVER_H_ + + #include "edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h" + +#define EI_TFLITE_RESOLVER static tflite::MicroMutableOpResolver<2> resolver; \ + resolver.AddFullyConnected(); \ + resolver.AddSoftmax(); + +#endif // _EI_CLASSIFIER_TFLITE_RESOLVER_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite_learn_5.cpp b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite_learn_5.cpp new file mode 100644 index 0000000..dbae209 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite_learn_5.cpp @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 EdgeImpulse Inc. + * + * Generated by Edge Impulse and licensed under the applicable Edge Impulse + * Terms of Service. Community and Professional Terms of Service + * (https://docs.edgeimpulse.com/page/terms-of-service) or Enterprise Terms of + * Service (https://docs.edgeimpulse.com/page/enterprise-terms-of-service), + * according to your product plan subscription (the “License”). + * + * This software, documentation and other associated files (collectively referred + * to as the “Software”) is a single SDK variation generated by the Edge Impulse + * platform and requires an active paid Edge Impulse subscription to use this + * Software for any purpose. + * + * You may NOT use this Software unless you have an active Edge Impulse subscription + * that meets the eligibility requirements for the applicable License, subject to + * your full and continued compliance with the terms and conditions of the License, + * including without limitation any usage restrictions under the applicable License. + * + * If you do not have an active Edge Impulse product plan subscription, or if use + * of this Software exceeds the usage limitations of your Edge Impulse product plan + * subscription, you are not permitted to use this Software and must immediately + * delete and erase all copies of this Software within your control or possession. + * Edge Impulse reserves all rights and remedies available to enforce its rights. + * + * Unless required by applicable law or agreed to in writing, the Software is + * distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific language governing + * permissions, disclaimers and limitations under the License. + */ + +// Empty on purpose diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite_learn_5.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite_learn_5.h new file mode 100644 index 0000000..792bc86 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/tflite_learn_5.h @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2024 EdgeImpulse Inc. + * + * Generated by Edge Impulse and licensed under the applicable Edge Impulse + * Terms of Service. Community and Professional Terms of Service + * (https://docs.edgeimpulse.com/page/terms-of-service) or Enterprise Terms of + * Service (https://docs.edgeimpulse.com/page/enterprise-terms-of-service), + * according to your product plan subscription (the “License”). + * + * This software, documentation and other associated files (collectively referred + * to as the “Software”) is a single SDK variation generated by the Edge Impulse + * platform and requires an active paid Edge Impulse subscription to use this + * Software for any purpose. + * + * You may NOT use this Software unless you have an active Edge Impulse subscription + * that meets the eligibility requirements for the applicable License, subject to + * your full and continued compliance with the terms and conditions of the License, + * including without limitation any usage restrictions under the applicable License. + * + * If you do not have an active Edge Impulse product plan subscription, or if use + * of this Software exceeds the usage limitations of your Edge Impulse product plan + * subscription, you are not permitted to use this Software and must immediately + * delete and erase all copies of this Software within your control or possession. + * Edge Impulse reserves all rights and remedies available to enforce its rights. + * + * Unless required by applicable law or agreed to in writing, the Software is + * distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. See the License for the specific language governing + * permissions, disclaimers and limitations under the License. + */ + +#ifndef _EI_CLASSIFIER_TFLITE_LEARN_5_H_ +#define _EI_CLASSIFIER_TFLITE_LEARN_5_H_ + +#define EI_CLASSIFIER_TFLITE_LEARN_5_ARENA_SIZE 3001 +const size_t tflite_learn_5_arena_size = 3001; + +#ifdef EI_CLASSIFIER_TFLITE_ARENA_SIZE +#if EI_CLASSIFIER_TFLITE_ARENA_SIZE < EI_CLASSIFIER_TFLITE_LEARN_5_ARENA_SIZE +#undef EI_CLASSIFIER_TFLITE_ARENA_SIZE +#define EI_CLASSIFIER_TFLITE_ARENA_SIZE EI_CLASSIFIER_TFLITE_LEARN_5_ARENA_SIZE +#endif // #if EI_CLASSIFIER_TFLITE_ARENA_SIZE < EI_CLASSIFIER_TFLITE_LEARN_5_ARENA_SIZE +#else +#define EI_CLASSIFIER_TFLITE_ARENA_SIZE EI_CLASSIFIER_TFLITE_LEARN_5_ARENA_SIZE +#endif // #ifdef EI_CLASSIFIER_TFLITE_ARENA_SIZE + +#if defined __GNUC__ +#define ALIGN(X) __attribute__((aligned(X))) +#elif defined _MSC_VER +#define ALIGN(X) __declspec(align(X)) +#elif defined __TASKING__ +#define ALIGN(X) __align(X) +#else +#define ALIGN(X) +#endif + +ALIGN(16) const unsigned char tflite_learn_5[] = { + 0x20, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x00, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x20, 0x00, 0x1c, 0x00, 0x18, 0x00, 0x14, 0x00, 0x10, 0x00, + 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, + 0x1c, 0x00, 0x00, 0x00, 0x8c, 0x00, 0x00, 0x00, 0xe4, 0x00, 0x00, 0x00, + 0x9c, 0x0c, 0x00, 0x00, 0xac, 0x0c, 0x00, 0x00, 0x70, 0x13, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0a, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, + 0x0a, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, + 0x3c, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x73, 0x65, 0x72, 0x76, + 0x69, 0x6e, 0x67, 0x5f, 0x64, 0x65, 0x66, 0x61, 0x75, 0x6c, 0x74, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x9c, 0xff, 0xff, 0xff, + 0x0a, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x6f, 0x75, 0x74, 0x70, 0x75, 0x74, 0x5f, 0x30, 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0x75, 0x6c, 0x74, 0x5f, + 0x78, 0x3a, 0x30, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x3c, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x19, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x0c, 0x00, 0x10, 0x00, + 0x0f, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09 +}; +unsigned int tflite_learn_5_len = 5088; +#endif // _EI_CLASSIFIER_TFLITE_LEARN_5_H_ diff --git a/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/trained_model_ops_define.h b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/trained_model_ops_define.h new file mode 100644 index 0000000..3931552 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/lib/surface_inferencing/src/tflite-model/trained_model_ops_define.h @@ -0,0 +1,34 @@ +/* Generated by Edge Impulse + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef EI_TFLITE_MODEL_OPS_DEFINES_H +#define EI_TFLITE_MODEL_OPS_DEFINES_H + + + + + + + + + + +#endif // EI_TFLITE_MODEL_OPS_DEFINES_H diff --git a/sensebox-bike-atrai-v2-esp32s3/platformio.ini b/sensebox-bike-atrai-v2-esp32s3/platformio.ini new file mode 100644 index 0000000..e2aa263 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/platformio.ini @@ -0,0 +1,26 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env:adafruit_feather_esp32s3] +platform = espressif32 +board = adafruit_feather_esp32s3 +platform_packages = platformio/framework-arduinoespressif32 @ https://github.com/espressif/arduino-esp32.git#2.0.17 +framework = arduino +lib_deps = + adafruit/Adafruit SSD1306 @ ^2.5.10 + adafruit/Adafruit HDC1000 Library@^2.0.2 + sensirion/sensirion-sps@^1.1.2 + https://github.com/felixerdy/QRCodeGenerator.git + adafruit/Adafruit MAX1704X@^1.0.3 + stm32duino/STM32duino VL53L8CX@^2.0.1 + adafruit/Adafruit MPU6050@^2.2.6 + ; sensebox/SenseBoxBLE@^1.1.0 + adafruit/Adafruit NeoPixel@^1.12.2 + ; tanakamasayuki/TensorFlowLite_ESP32@^1.0.0 diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp new file mode 100644 index 0000000..504b575 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp @@ -0,0 +1,115 @@ +#include "BLEModule.h" + +bool isConnectedVar = false; +BLEServer *pServer; +BLEService *pService; + + +BLEModule::BLEModule() +{ + bleName = ""; +} + +bool BLEModule::begin() +{ + BLEDevice::init("senseBox-BLE[xxxyyy]"); // not sure how to adjust the id + pServer = BLEDevice::createServer(); + + return true; +} + +String BLEModule::getBLEName() +{ + return bleName; +} + +bool BLEModule::isConnected() +{ + return isConnectedVar; +} + +const char **BLEModule::getBLEConnectionString() +{ + String bleId = "[xxxyyy]"; + String bleIdBegin = bleId.substring(0, bleId.length() / 2); + String bleIdEnd = bleId.substring(bleId.length() / 2); + const char *MESSAGE_CONFIGURE_WIFI[] = { + "senseBox", + "bike", + bleIdBegin.c_str(), + bleIdEnd.c_str()}; + return MESSAGE_CONFIGURE_WIFI; +} + +int BLEModule::createService(const char *uuid) +{ + pService = pServer->createService(uuid); + pService->start(); + return 1; +} + +int BLEModule::createCharacteristic(const char *uuid) +{ + BLECharacteristic *pCharacteristic = pService->createCharacteristic(uuid, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE); + return 1; +} + +bool BLEModule::writeBLE(const char * characteristicId, float value) +{ + BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); + pCharacteristic->setValue(value); + // pCharacteristic->notify(); ?? + return true; +} + +bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2) +{ + BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); + uint8_t buf[2] = {value, value2}; + pCharacteristic->setValue(buf,1); + return true; +} + +bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3) +{ + BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); + uint8_t buf[3] = {value, value2, value3}; + pCharacteristic->setValue(buf,1); + return true; +} + +bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4) +{ + BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); + uint8_t buf[4] = {value, value2, value3, value4}; + pCharacteristic->setValue(buf,1); + return true; +} + +bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4, uint8_t value5) +{ + BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); + uint8_t buf[5] = {value, value2, value3, value4}; + pCharacteristic->setValue(buf,1); + return true; +} + +void BLEModule::bleTask() +{ + while (true) + { + BLEDevice::startAdvertising(); + vTaskDelay(pdMS_TO_TICKS(5)); + } +} + +void BLEModule::bleStartPoll(const char *uuid) +{ + pService->start(); + BLEAdvertising *pAdvertising = BLEDevice::getAdvertising(); + pAdvertising->addServiceUUID(uuid); + pAdvertising->setScanResponse(true); + pAdvertising->setMinPreferred(0x06); // functions that help with iPhone connections issue + pAdvertising->setMinPreferred(0x12); + BLEDevice::startAdvertising(); +} diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h new file mode 100644 index 0000000..63b5f81 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h @@ -0,0 +1,51 @@ +#ifndef BLE_MODULE_H +#define BLE_MODULE_H + +#include +#include +#include +#include + +class BLEModule +{ +public: + BLEModule(); + + // Initialize the BLE module + bool begin(); + + // Get the BLE module ID + String getBLEName(); + + void bleStartPoll(const char *uuid); + + const char **getBLEConnectionString(); + + static int createService(const char *uuid); + + // Create a BLE characteristic + static int createCharacteristic(const char *uuid); + + static bool writeBLE(const char * characteristicId, float value); + static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2); + static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3); + static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4); + static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4, uint8_t value5); + + // Set callback for receiving data + // void setReceiveCallback(void (*callback)(BLEDevice, BLECharacteristic)); + + // Task function for polling BLE + static void bleTask(); + + static bool isConnected(); + +private: + // BLEService* service; + String bleName; + + // static void onReceive(BLEDevice central, BLECharacteristic characteristic); + // static void (*receiveCallback)(BLEDevice, BLECharacteristic); +}; + +#endif // BLE_MODULE_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp new file mode 100644 index 0000000..a1ddd1c --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp @@ -0,0 +1,193 @@ +#include "Display.h" +#include +// #include +#include +#include +#include +#include +#include "bicycle_loading_bitmap.h" + +// Adafruit_SSD1306 SBDisplay::display(SCREEN_WIDTH, SCREEN_HEIGHT, &Wire, OLED_RESET); +QRCode SBDisplay::qrcode; + +float batteryCharge = 0; + +TaskHandle_t xBicycleAnimationTaskHandle; +bool isBicycleAnimationShowing = false; +String loadingMessage; +float loadingProgress; + +String bleId = ""; + +void SBDisplay::bicycleAnimationTask(void *pvParameter) +{ + int dsplW = 128; + int dsplH = 64; + int prgsW = 120; + int prgsH = 2; + + while (1) + { + for (int i = 0; i < 36; i++) + { + display.clearDisplay(); + display.drawBitmap(32, -10, bicycle_loading_bitmap[i], 64, 64, 1); // this displays each frame hex value + drawProgressbar(4, (dsplH - 12) - prgsH - 8, prgsW, prgsH, loadingProgress * 100); + display.setCursor(4, dsplH - 12); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println(loadingMessage); + // drawBattery(0, 0, 16, 4); + display.display(); + vTaskDelay(pdMS_TO_TICKS(100)); + + if (!isBicycleAnimationShowing) + { + vTaskDelete(xBicycleAnimationTaskHandle); + } + } + } +} + +void SBDisplay::begin() +{ + display.begin(SSD1306_SWITCHCAPVCC, 0x3D); + display.setRotation(2); + display.display(); + delay(100); + display.clearDisplay(); +} + +void SBDisplay::drawProgressbar(int x, int y, int width, int height, int progress) +{ + progress = progress > 100 ? 100 : progress; // set the progress value to 100 + progress = progress < 0 ? 0 : progress; // start the counting to 0-100 + float bar = ((float)(width - 1) / 100) * progress; + display.drawRect(x, y, width, height + 4, WHITE); + display.fillRect(x + 2, y + 2, bar - 3, height, WHITE); // initailize the graphics fillRect(int x, int y, int width, int height) +} + +void SBDisplay::drawBattery(int x, int y, int width, int height) +{ + batteryCharge = BatterySensor::getBatteryCharge(); + drawProgressbar(x, y, width, height, batteryCharge); + display.fillRect(x + width, y + 2, 2, height, WHITE); + if (BatterySensor::getBatteryChargeRate() > 0) + { + display.setCursor(x + width + 4, y + 1); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + display.println("+"); + display.setCursor(0, 0); + } +} + +void SBDisplay::showLoading(String msg, float val) +{ + if (!isBicycleAnimationShowing) + { + isBicycleAnimationShowing = true; + xTaskCreate(&bicycleAnimationTask, "bicycle_animation_task", 1536, (void *)NULL, 1, &xBicycleAnimationTaskHandle); + } + loadingMessage = msg; + loadingProgress = val; +} + +void SBDisplay::showSystemStatus() +{ + if (isBicycleAnimationShowing) + { + isBicycleAnimationShowing = false; + } + + display.clearDisplay(); + + display.setCursor(0, 0); + display.println(""); + display.setTextSize(1); + display.setTextColor(WHITE, BLACK); + + display.println(F("Batt Percent: ")); + display.setTextSize(1); + display.print(batteryCharge, 1); + display.println(" %"); + + drawBattery(0, 0, 16, 4); + + display.display(); +} + +void SBDisplay::showConnectionScreen() +{ + if (isBicycleAnimationShowing) + { + isBicycleAnimationShowing = false; + } + + // String bleIdBrackets = "[" + bleId + "]"; + // String name = "senseBox:bike " + bleIdBrackets; + // String bleIdBegin = bleIdBrackets.substring(0, bleIdBrackets.length() / 2); + // String bleIdEnd = bleIdBrackets.substring(bleIdBrackets.length() / 2); + // const char *message[] = { + // "senseBox", + // "bike", + // bleIdBegin.c_str(), + // bleIdEnd.c_str()}; + + // drawQrCode(name.c_str(), message); + + drawBattery(0, 0, 16, 4); + display.display(); +} + +void SBDisplay::drawQrCode(const char *qrStr, const char *lines[]) +{ + if (isBicycleAnimationShowing) + { + isBicycleAnimationShowing = false; + } + + display.clearDisplay(); + display.setTextSize(1); + + uint8_t qrcodeData[qrcode_getBufferSize(3)]; + qrcode_initText(&qrcode, qrcodeData, 3, ECC_MEDIUM, qrStr); + + // Text starting point + int cursor_start_y = 10; + int cursor_start_x = 4; + int font_height = 12; + + // QR Code Starting Point + int offset_x = 62; + int offset_y = 3; + + for (int y = 0; y < qrcode.size; y++) + { + for (int x = 0; x < qrcode.size; x++) + { + int newX = offset_x + (x * 2); + int newY = offset_y + (y * 2); + + if (qrcode_getModule(&qrcode, x, y)) + { + display.fillRect(newX, newY, 2, 2, 1); + } + else + { + display.fillRect(newX, newY, 2, 2, 0); + } + } + } + display.setTextColor(1, 0); + for (int i = 0; i < 4; i++) + { + display.setCursor(cursor_start_x, cursor_start_y + font_height * i); + display.println(lines[i]); + } +} + +void SBDisplay::readBleId() +{ + // bleId = SenseBoxBLE::getMCUId(); +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.h b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.h new file mode 100644 index 0000000..aa8b11e --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.h @@ -0,0 +1,36 @@ +#ifndef MY_DISPLAY_H +#define MY_DISPLAY_H + +#include +#include +#include + +// #include "../ble/BLEModule.h" +#include "../sensors/BatterySensor/BatterySensor.h" + +#include +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +#define SCREEN_WIDTH 128 +#define SCREEN_HEIGHT 64 +#define OLED_RESET -1 + +class SBDisplay +{ +public: + static void begin(); + static void showSystemStatus(); + static void showConnectionScreen(); + static void drawQrCode(const char *qrStr, const char *lines[]); + static void showLoading(String msg, float val); + static void drawProgressbar(int x, int y, int width, int height, int progress); + static void drawBattery(int x, int y, int width, int height); + static void bicycleAnimationTask(void *pvParams); + static void readBleId(); + +private: + static Adafruit_SSD1306 display; + static QRCode qrcode; +}; +#endif // MY_DISPLAY_H \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/display/bicycle_loading_bitmap.h b/sensebox-bike-atrai-v2-esp32s3/src/display/bicycle_loading_bitmap.h new file mode 100644 index 0000000..0263063 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/display/bicycle_loading_bitmap.h @@ -0,0 +1,1227 @@ +const unsigned char bicycle_loading_bitmap[36][512] PROGMEM = { + + // 'frame_00_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x60, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x9f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x9c, 0x00, 0x00, 0x00, 0x1f, 0xf7, 0xf0, 0x07, 0x0f, 0xf8, 0x00, + 0x00, 0x3f, 0xfe, 0x70, 0x0e, 0x1f, 0xfe, 0x00, 0x00, 0xf8, 0x3e, 0x38, 0x0e, 0x7e, 0x1f, 0x00, + 0x00, 0xe0, 0x1f, 0x38, 0x1c, 0xf7, 0x07, 0x00, 0x01, 0xc0, 0x3f, 0x1c, 0x38, 0xc7, 0x03, 0x80, + 0x03, 0x80, 0x73, 0x8e, 0x79, 0xc7, 0x01, 0xc0, 0x03, 0x00, 0x71, 0xce, 0x73, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x83, 0x80, 0xc0, 0x07, 0x01, 0xc0, 0xc7, 0xe3, 0x03, 0x80, 0xe0, + 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, 0x06, 0x03, 0xff, 0xff, 0x83, 0x01, 0xc0, 0x60, + 0x07, 0x00, 0xff, 0xff, 0x83, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0xc1, 0x83, 0x00, 0x00, 0xe0, + 0x03, 0x00, 0x01, 0x81, 0xf3, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x01, 0x8f, 0xf1, 0x80, 0x01, 0xc0, + 0x01, 0xc0, 0x03, 0x8f, 0xc1, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x04, 0x00, 0xe0, 0x07, 0x80, + 0x00, 0xf0, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_01_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0xe0, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x07, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x1f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x9c, 0x00, 0x00, 0x00, 0x1f, 0xef, 0xe0, 0x07, 0x0f, 0xf0, 0x00, + 0x00, 0x7f, 0xfe, 0x70, 0x0e, 0x3f, 0xfc, 0x00, 0x00, 0xf8, 0x3e, 0x38, 0x1e, 0x7e, 0x1f, 0x00, + 0x01, 0xe0, 0x3f, 0x38, 0x1c, 0xe7, 0x07, 0x00, 0x01, 0xc0, 0x3f, 0x1c, 0x38, 0xc7, 0x03, 0x80, + 0x03, 0x80, 0x73, 0x9e, 0x79, 0xc7, 0x01, 0xc0, 0x03, 0x00, 0xf1, 0x8e, 0x73, 0x83, 0x81, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x03, 0x80, 0xc0, 0x07, 0x01, 0xc1, 0xc7, 0xe3, 0x03, 0x9c, 0xe0, + 0x06, 0x03, 0xff, 0xff, 0xc3, 0x01, 0x9c, 0xe0, 0x06, 0x03, 0xff, 0xff, 0x83, 0x01, 0x80, 0xe0, + 0x07, 0x01, 0xef, 0xdb, 0x83, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x01, 0xc3, 0xe3, 0x80, 0x00, 0xc0, + 0x03, 0x00, 0x01, 0xc3, 0xe3, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x03, 0x87, 0xe1, 0x80, 0x01, 0xc0, + 0x03, 0xc0, 0x03, 0x8f, 0x81, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x0e, 0x00, 0xe0, 0x07, 0x80, + 0x00, 0xf0, 0x1e, 0x00, 0x00, 0x78, 0x1f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfc, 0x00, + 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_02_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x60, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0xe0, 0x70, 0x00, + 0x00, 0x00, 0xff, 0x80, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x01, 0xff, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x1f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xe1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x03, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x07, 0xc0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x1c, 0x00, 0x00, 0x00, 0x1f, 0xee, 0xe0, 0x0f, 0x1f, 0xf0, 0x00, + 0x00, 0x7f, 0xfe, 0x70, 0x0e, 0x3f, 0xfc, 0x00, 0x00, 0xf0, 0x3c, 0x70, 0x1c, 0x7e, 0x1e, 0x00, + 0x01, 0xe0, 0x3e, 0x38, 0x3c, 0xee, 0x07, 0x00, 0x03, 0x80, 0x7f, 0x1c, 0x39, 0xc6, 0x03, 0x80, + 0x03, 0x00, 0x73, 0x9c, 0x71, 0x87, 0x01, 0x80, 0x07, 0x00, 0xe1, 0x8e, 0xf3, 0x87, 0x01, 0xc0, + 0x06, 0x01, 0xe1, 0x8f, 0xe3, 0x03, 0x00, 0xc0, 0x06, 0x01, 0xc1, 0xc7, 0xc3, 0x03, 0xbc, 0xc0, + 0x06, 0x03, 0xff, 0xff, 0xc3, 0x03, 0xbc, 0xc0, 0x06, 0x03, 0xff, 0xff, 0x87, 0x01, 0x80, 0xc0, + 0x06, 0x01, 0xbb, 0xff, 0x83, 0x00, 0x00, 0xc0, 0x06, 0x00, 0x01, 0xc3, 0xc3, 0x00, 0x00, 0xc0, + 0x07, 0x00, 0x01, 0x83, 0xc3, 0x80, 0x01, 0xc0, 0x03, 0x00, 0x03, 0x87, 0x83, 0x80, 0x01, 0x80, + 0x03, 0x80, 0x07, 0x0f, 0x01, 0xc0, 0x03, 0x80, 0x01, 0xc0, 0x0f, 0x0e, 0x00, 0xe0, 0x07, 0x00, + 0x00, 0xf0, 0x1e, 0x0c, 0x00, 0xf8, 0x1e, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfc, 0x00, + 0x00, 0x3f, 0xf0, 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_03_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc1, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0, 0xe0, 0x00, 0x00, 0x01, 0xff, 0x00, 0x00, 0xc0, 0xe0, 0x00, + 0x00, 0x01, 0xff, 0x80, 0x00, 0xe0, 0xe0, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0xe0, 0x00, 0x00, + 0x00, 0x00, 0x1c, 0x00, 0x0f, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x01, 0xff, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0x3f, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0xe3, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xfc, 0x03, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x07, 0x80, 0x07, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0xc0, 0x0f, 0x38, 0x00, 0x00, 0x00, 0x1f, 0xff, 0xe0, 0x0e, 0x1f, 0xe0, 0x00, + 0x00, 0x7f, 0xfc, 0xe0, 0x1c, 0x7f, 0xf8, 0x00, 0x00, 0xf0, 0x7c, 0x70, 0x3c, 0xfc, 0x3e, 0x00, + 0x01, 0xc0, 0x7e, 0x78, 0x39, 0xee, 0x0e, 0x00, 0x03, 0x80, 0x76, 0x38, 0x71, 0x8e, 0x07, 0x00, + 0x07, 0x00, 0xe7, 0x1c, 0xf3, 0x8e, 0x03, 0x80, 0x06, 0x01, 0xe3, 0x1c, 0xe3, 0x07, 0x01, 0x80, + 0x06, 0x01, 0xc3, 0x8f, 0xc7, 0x07, 0x01, 0x80, 0x0e, 0x03, 0x81, 0x8f, 0xc6, 0x07, 0xfd, 0xc0, + 0x0e, 0x07, 0xff, 0xff, 0x86, 0x03, 0xfd, 0xc0, 0x0e, 0x07, 0xff, 0xff, 0x06, 0x03, 0x81, 0xc0, + 0x0e, 0x01, 0xdf, 0xff, 0x06, 0x00, 0x01, 0xc0, 0x0e, 0x00, 0x03, 0x87, 0x87, 0x00, 0x01, 0xc0, + 0x06, 0x00, 0x03, 0x8f, 0x07, 0x00, 0x01, 0x80, 0x07, 0x00, 0x03, 0x0e, 0x03, 0x00, 0x03, 0x80, + 0x03, 0x80, 0x07, 0x1e, 0x03, 0x80, 0x07, 0x00, 0x03, 0xc0, 0x0e, 0x1c, 0x01, 0xc0, 0x0f, 0x00, + 0x01, 0xe0, 0x3c, 0x18, 0x00, 0xf0, 0x1e, 0x00, 0x00, 0xff, 0xf8, 0x00, 0x00, 0x7f, 0xfc, 0x00, + 0x00, 0x3f, 0xe0, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_04_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x83, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x81, 0xc0, 0x00, 0x00, 0x01, 0xff, 0x00, 0x01, 0xc1, 0xc0, 0x00, + 0x00, 0x03, 0xff, 0x00, 0x01, 0xc0, 0xc0, 0x00, 0x00, 0x00, 0x7a, 0x00, 0x01, 0xc0, 0x00, 0x00, + 0x00, 0x00, 0x1c, 0x00, 0x1f, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x03, 0xff, 0xe0, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x7f, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xc3, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xfc, 0x07, 0x70, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x80, 0x0f, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x1f, 0x80, 0x0e, 0x38, 0x00, 0x00, 0x00, 0x3f, 0xdd, 0xc0, 0x1c, 0x3f, 0xe0, 0x00, + 0x00, 0xff, 0xf9, 0xc0, 0x3c, 0x7f, 0xf8, 0x00, 0x01, 0xe0, 0x78, 0xe0, 0x38, 0xfc, 0x7c, 0x00, + 0x03, 0x80, 0x7c, 0x70, 0x71, 0xdc, 0x1e, 0x00, 0x07, 0x00, 0xfe, 0x70, 0xf3, 0x9c, 0x06, 0x00, + 0x06, 0x01, 0xe6, 0x38, 0xe7, 0x0e, 0x07, 0x00, 0x0e, 0x01, 0xc7, 0x3d, 0xc6, 0x0e, 0x03, 0x00, + 0x0c, 0x03, 0x83, 0x1f, 0xc6, 0x0e, 0x03, 0x80, 0x0c, 0x07, 0x83, 0x0f, 0x8e, 0x1f, 0xfd, 0x80, + 0x1c, 0x07, 0xff, 0xff, 0x0e, 0x1f, 0xfd, 0x80, 0x1c, 0x07, 0xff, 0xff, 0x0e, 0x07, 0x01, 0x80, + 0x0c, 0x03, 0xd3, 0xde, 0x0e, 0x02, 0x01, 0x80, 0x0c, 0x00, 0x03, 0x1e, 0x0e, 0x00, 0x03, 0x80, + 0x0e, 0x00, 0x07, 0x1c, 0x06, 0x00, 0x03, 0x80, 0x0e, 0x00, 0x06, 0x38, 0x07, 0x00, 0x03, 0x00, + 0x07, 0x00, 0x0e, 0x78, 0x03, 0x80, 0x07, 0x00, 0x03, 0x80, 0x1c, 0x70, 0x03, 0xc0, 0x0e, 0x00, + 0x03, 0xe0, 0x78, 0x20, 0x01, 0xe0, 0x3c, 0x00, 0x00, 0xff, 0xf0, 0x00, 0x00, 0xff, 0xf8, 0x00, + 0x00, 0x7f, 0xe0, 0x00, 0x00, 0x3f, 0xe0, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_05_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xfe, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x83, 0x80, 0x00, 0x00, 0x03, 0xfe, 0x00, 0x03, 0x81, 0x80, 0x00, + 0x00, 0x07, 0xfe, 0x00, 0x03, 0x81, 0x80, 0x00, 0x00, 0x02, 0xf8, 0x00, 0x01, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x38, 0x00, 0x3f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x07, 0xff, 0xc0, 0x00, 0x00, + 0x00, 0x00, 0x1c, 0x7f, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xff, 0x87, 0xe0, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0xf8, 0x0e, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x0e, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x1f, 0x00, 0x1c, 0x70, 0x00, 0x00, 0x00, 0x7f, 0xbb, 0x80, 0x3c, 0x7f, 0xc0, 0x00, + 0x01, 0xff, 0xfb, 0xc0, 0x38, 0xff, 0xf0, 0x00, 0x03, 0xc0, 0xf1, 0xc0, 0x71, 0xf8, 0x78, 0x00, + 0x07, 0x00, 0xf8, 0xe0, 0xe3, 0xb8, 0x3c, 0x00, 0x0e, 0x01, 0xfc, 0xf0, 0xe7, 0x18, 0x0e, 0x00, + 0x0c, 0x01, 0xcc, 0x71, 0xce, 0x1c, 0x0e, 0x00, 0x1c, 0x03, 0x8e, 0x3b, 0x8c, 0x1c, 0x07, 0x00, + 0x18, 0x07, 0x86, 0x3f, 0x8c, 0x1c, 0x07, 0x00, 0x18, 0x07, 0x06, 0x1f, 0x1f, 0xff, 0xff, 0x00, + 0x18, 0x0f, 0xff, 0xff, 0x1d, 0xff, 0xff, 0x00, 0x18, 0x0f, 0xff, 0xfe, 0x1c, 0x0e, 0x03, 0x00, + 0x18, 0x07, 0xff, 0xfc, 0x1c, 0x00, 0x03, 0x00, 0x18, 0x00, 0x06, 0x78, 0x0c, 0x00, 0x03, 0x00, + 0x1c, 0x00, 0x0e, 0xf0, 0x0c, 0x00, 0x07, 0x00, 0x0c, 0x00, 0x0e, 0xe0, 0x0e, 0x00, 0x06, 0x00, + 0x0e, 0x00, 0x1d, 0xc0, 0x07, 0x00, 0x0e, 0x00, 0x07, 0x00, 0x38, 0x80, 0x03, 0x80, 0x1c, 0x00, + 0x03, 0xc0, 0x70, 0x00, 0x03, 0xc0, 0x78, 0x00, 0x01, 0xff, 0xe0, 0x00, 0x01, 0xff, 0xf0, 0x00, + 0x00, 0xff, 0xc0, 0x00, 0x00, 0x7f, 0xc0, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_06_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x07, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0x03, 0x00, 0x00, 0x00, 0x07, 0xfc, 0x00, 0x07, 0x03, 0x81, 0x80, + 0x00, 0x0f, 0xfc, 0x00, 0x07, 0x03, 0x83, 0x80, 0x00, 0x06, 0xf0, 0x00, 0x03, 0x80, 0x01, 0x00, + 0x00, 0x00, 0x70, 0x00, 0x7f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x78, 0x07, 0xff, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x38, 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xff, 0x0f, 0xc0, 0x00, 0x00, + 0x00, 0x00, 0x1f, 0xf0, 0x1f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x1c, 0xe0, 0x00, 0x00, + 0x00, 0x00, 0x3f, 0x00, 0x38, 0xe0, 0x00, 0x00, 0x00, 0xff, 0x77, 0x00, 0x78, 0xff, 0x80, 0x00, + 0x03, 0xff, 0xf3, 0x80, 0x71, 0xff, 0xe0, 0x00, 0x07, 0xc1, 0xe3, 0xc0, 0xe3, 0xf0, 0xf0, 0x00, + 0x0f, 0x01, 0xf1, 0xc1, 0xe7, 0x70, 0x38, 0x00, 0x0c, 0x03, 0xf9, 0xe1, 0xce, 0x38, 0x1c, 0x00, + 0x1c, 0x03, 0x9c, 0xe3, 0x8c, 0x38, 0x0c, 0x00, 0x18, 0x07, 0x0c, 0x77, 0x9c, 0x38, 0x0e, 0x00, + 0x38, 0x0f, 0x0e, 0x7f, 0x18, 0x1c, 0x06, 0x00, 0x30, 0x0e, 0x0e, 0x7e, 0x7f, 0xff, 0xfe, 0x00, + 0x30, 0x1f, 0xff, 0xfe, 0x3f, 0xff, 0xfe, 0x00, 0x30, 0x1f, 0xff, 0xfc, 0x38, 0x0c, 0x06, 0x00, + 0x30, 0x0f, 0xdf, 0xf8, 0x18, 0x00, 0x06, 0x00, 0x30, 0x00, 0x0f, 0xc0, 0x18, 0x00, 0x06, 0x00, + 0x38, 0x00, 0x0f, 0x80, 0x1c, 0x00, 0x0e, 0x00, 0x18, 0x00, 0x1f, 0x00, 0x1c, 0x00, 0x0e, 0x00, + 0x1c, 0x00, 0x38, 0x00, 0x0e, 0x00, 0x1c, 0x00, 0x0e, 0x00, 0x78, 0x00, 0x07, 0x00, 0x38, 0x00, + 0x07, 0x80, 0xf0, 0x00, 0x07, 0xc0, 0xf0, 0x00, 0x03, 0xff, 0xc0, 0x00, 0x01, 0xff, 0xe0, 0x00, + 0x00, 0xff, 0x80, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_07_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0e, 0x07, 0x00, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x0e, 0x07, 0x03, 0x80, + 0x00, 0x0f, 0xfc, 0x00, 0x07, 0x07, 0x07, 0x80, 0x00, 0x03, 0xe0, 0x00, 0x07, 0x00, 0x03, 0x00, + 0x00, 0x00, 0xe0, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0f, 0xff, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x71, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x1f, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x3f, 0xe0, 0x1d, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x39, 0xc0, 0x00, 0x00, + 0x00, 0x00, 0x7e, 0x00, 0x79, 0xc0, 0x00, 0x00, 0x01, 0xff, 0xfe, 0x00, 0x70, 0xff, 0x00, 0x00, + 0x03, 0xff, 0xe7, 0x00, 0xe3, 0xff, 0xc0, 0x00, 0x0f, 0x83, 0xe3, 0x81, 0xe7, 0xe1, 0xf0, 0x00, + 0x0e, 0x03, 0xf3, 0x81, 0xce, 0x60, 0x70, 0x00, 0x1c, 0x03, 0xf1, 0xc3, 0x8c, 0x70, 0x38, 0x00, + 0x38, 0x07, 0x39, 0xe7, 0x98, 0x70, 0x1c, 0x00, 0x30, 0x0f, 0x18, 0xe7, 0x18, 0x30, 0x1c, 0x00, + 0x70, 0x0e, 0x1c, 0xfe, 0x38, 0x38, 0x0c, 0x00, 0x70, 0x1c, 0x0d, 0xff, 0xff, 0xff, 0xfe, 0x00, + 0x70, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x60, 0x3f, 0xff, 0xf8, 0x30, 0x1c, 0x0e, 0x00, + 0x70, 0x0f, 0xdf, 0xf0, 0x30, 0x00, 0x0e, 0x00, 0x70, 0x00, 0x1e, 0x00, 0x30, 0x00, 0x0c, 0x00, + 0x30, 0x00, 0x18, 0x00, 0x38, 0x00, 0x0c, 0x00, 0x38, 0x00, 0x18, 0x00, 0x18, 0x00, 0x1c, 0x00, + 0x18, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x1e, 0x00, 0x70, 0x00, 0x0e, 0x00, 0x78, 0x00, + 0x0f, 0x01, 0xe0, 0x00, 0x07, 0x80, 0xf0, 0x00, 0x07, 0xff, 0xc0, 0x00, 0x03, 0xff, 0xc0, 0x00, + 0x01, 0xff, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_08_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0e, 0x00, 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x06, 0x07, 0x80, + 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x06, 0x0f, 0x80, 0x00, 0x03, 0xc0, 0x00, 0x0e, 0x00, 0x07, 0x00, + 0x00, 0x00, 0xe0, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0xff, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x73, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfe, 0x1f, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x3f, 0xc0, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x7b, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x7c, 0x00, 0x71, 0xc0, 0x00, 0x00, 0x01, 0xfe, 0xee, 0x00, 0xe1, 0xff, 0x00, 0x00, + 0x07, 0xff, 0xcf, 0x01, 0xe3, 0xff, 0xc0, 0x00, 0x0f, 0x03, 0xc7, 0x01, 0xc7, 0xe3, 0xe0, 0x00, + 0x1c, 0x03, 0xe3, 0x83, 0x8e, 0xe0, 0xf0, 0x00, 0x38, 0x07, 0xf3, 0xc3, 0x9c, 0xe0, 0x30, 0x00, + 0x30, 0x07, 0x31, 0xe7, 0x38, 0x70, 0x38, 0x00, 0x70, 0x0e, 0x39, 0xee, 0x30, 0x70, 0x18, 0x00, + 0x60, 0x1c, 0x1b, 0xfe, 0x30, 0x70, 0x1c, 0x00, 0x60, 0x1c, 0x1f, 0xff, 0xff, 0xff, 0xfc, 0x00, + 0x60, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0xe0, 0x3f, 0xff, 0xf8, 0x70, 0x38, 0x0c, 0x00, + 0x60, 0x1f, 0xbf, 0xe0, 0x70, 0x00, 0x0c, 0x00, 0x60, 0x00, 0x18, 0x00, 0x30, 0x00, 0x0c, 0x00, + 0x70, 0x00, 0x38, 0x00, 0x30, 0x00, 0x1c, 0x00, 0x70, 0x00, 0x38, 0x00, 0x38, 0x00, 0x18, 0x00, + 0x38, 0x00, 0x70, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x1c, 0x00, 0xe0, 0x00, 0x1e, 0x00, 0x70, 0x00, + 0x0f, 0x03, 0xc0, 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x07, 0xff, 0x80, 0x00, 0x07, 0xff, 0xc0, 0x00, + 0x03, 0xff, 0x00, 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_10_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1c, 0x0e, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x1c, 0x0e, 0xff, 0x80, + 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x0e, 0xff, 0x80, 0x00, 0x07, 0xe0, 0x00, 0x0e, 0x04, 0xff, 0x00, + 0x00, 0x01, 0xc0, 0x00, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0xff, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xe3, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfe, 0x3f, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x7f, 0xc0, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x73, 0x80, 0x00, 0x00, + 0x00, 0x00, 0xfc, 0x00, 0xf3, 0x80, 0x00, 0x00, 0x03, 0xff, 0xfe, 0x00, 0xe1, 0xfe, 0x00, 0x00, + 0x0f, 0xff, 0xce, 0x01, 0xc7, 0xff, 0x80, 0x00, 0x1f, 0x07, 0xc7, 0x03, 0xcf, 0xc3, 0xc0, 0x00, + 0x3c, 0x07, 0xe7, 0x03, 0x9f, 0xc0, 0xe0, 0x00, 0x38, 0x07, 0xe3, 0x9f, 0x3f, 0xe0, 0x70, 0x00, + 0x70, 0x0e, 0x73, 0xff, 0x38, 0xe0, 0x38, 0x00, 0x60, 0x1e, 0x31, 0xff, 0x70, 0x60, 0x18, 0x00, + 0xe0, 0x1c, 0x38, 0xfc, 0x70, 0x70, 0x18, 0x00, 0xe0, 0x38, 0x7f, 0xff, 0xff, 0xff, 0xfc, 0x00, + 0xc0, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0xc0, 0x7f, 0xff, 0xf0, 0x60, 0x30, 0x1c, 0x00, + 0xe0, 0x1f, 0xfb, 0xe0, 0x60, 0x00, 0x1c, 0x00, 0xe0, 0x00, 0x38, 0x00, 0x60, 0x00, 0x18, 0x00, + 0x60, 0x00, 0x30, 0x00, 0x70, 0x00, 0x18, 0x00, 0x70, 0x00, 0x70, 0x00, 0x30, 0x00, 0x38, 0x00, + 0x70, 0x00, 0x70, 0x00, 0x38, 0x00, 0x70, 0x00, 0x3c, 0x00, 0xe0, 0x00, 0x1c, 0x00, 0xf0, 0x00, + 0x1e, 0x03, 0xc0, 0x00, 0x0f, 0x03, 0xe0, 0x00, 0x0f, 0xff, 0x80, 0x00, 0x07, 0xff, 0x80, 0x00, + 0x03, 0xfe, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_11_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1c, 0x0e, 0x00, 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x0f, 0xff, 0x80, + 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x07, 0xff, 0x80, 0x00, 0x0b, 0xe0, 0x00, 0x0e, 0x03, 0xff, 0x00, + 0x00, 0x01, 0xe0, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0xff, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x73, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfe, 0x1f, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x3f, 0xc0, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x7b, 0x80, 0x00, 0x00, + 0x00, 0x00, 0xfc, 0x00, 0x71, 0x80, 0x00, 0x00, 0x03, 0xfe, 0xee, 0x00, 0xe1, 0xff, 0x00, 0x00, + 0x07, 0xff, 0xce, 0x01, 0xe3, 0xff, 0x80, 0x00, 0x0f, 0x07, 0xc7, 0x01, 0xcf, 0xc3, 0xe0, 0x00, + 0x1c, 0x03, 0xe7, 0x83, 0xbf, 0xe0, 0xf0, 0x00, 0x38, 0x07, 0x73, 0x87, 0x9f, 0xe0, 0x70, 0x00, + 0x70, 0x0f, 0x71, 0xc7, 0x38, 0x60, 0x38, 0x00, 0x70, 0x0e, 0x39, 0xcf, 0xf0, 0x70, 0x18, 0x00, + 0x60, 0x1c, 0x38, 0xff, 0xf0, 0x70, 0x1c, 0x00, 0xe0, 0x39, 0xff, 0xff, 0xff, 0xff, 0xdc, 0x00, + 0xe0, 0x3f, 0xff, 0xff, 0xff, 0xff, 0xcc, 0x00, 0xe0, 0x3f, 0xff, 0xf8, 0x60, 0x38, 0x0c, 0x00, + 0xe0, 0x1f, 0xbf, 0xe0, 0x60, 0x00, 0x0c, 0x00, 0x60, 0x00, 0x18, 0x00, 0x70, 0x00, 0x1c, 0x00, + 0x60, 0x00, 0x38, 0x00, 0x30, 0x00, 0x18, 0x00, 0x70, 0x00, 0x30, 0x00, 0x38, 0x00, 0x38, 0x00, + 0x38, 0x00, 0x70, 0x00, 0x18, 0x00, 0x38, 0x00, 0x1c, 0x00, 0xe0, 0x00, 0x1c, 0x00, 0x70, 0x00, + 0x1e, 0x03, 0xc0, 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x0f, 0xff, 0x80, 0x00, 0x07, 0xff, 0xc0, 0x00, + 0x03, 0xff, 0x00, 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_09_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1c, 0x0e, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x0c, 0x0e, 0x3f, 0x80, + 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x0e, 0x3f, 0x80, 0x00, 0x05, 0xd0, 0x00, 0x0e, 0x00, 0x3f, 0x00, + 0x00, 0x01, 0xc0, 0x00, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0xff, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xf3, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfe, 0x3f, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x7f, 0xc0, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x73, 0x80, 0x00, 0x00, + 0x00, 0x00, 0xfc, 0x00, 0xf3, 0x80, 0x00, 0x00, 0x03, 0xff, 0xfe, 0x00, 0xe1, 0xfe, 0x00, 0x00, + 0x07, 0xff, 0xce, 0x01, 0xc7, 0xff, 0x80, 0x00, 0x1f, 0x07, 0xc7, 0x03, 0xcf, 0xc3, 0xe0, 0x00, + 0x1c, 0x03, 0xe7, 0x03, 0x9f, 0xe0, 0xe0, 0x00, 0x38, 0x07, 0x63, 0xbf, 0x1d, 0xe0, 0x70, 0x00, + 0x70, 0x0e, 0x71, 0xff, 0x38, 0xe0, 0x38, 0x00, 0x60, 0x0e, 0x3b, 0xfe, 0x30, 0x70, 0x18, 0x00, + 0x60, 0x1c, 0x3b, 0xfe, 0x70, 0x70, 0x1c, 0x00, 0xe0, 0x38, 0x1f, 0xff, 0xff, 0xff, 0xfc, 0x00, + 0xe0, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00, 0xc0, 0x7f, 0xff, 0xf0, 0x60, 0x38, 0x0c, 0x00, + 0xe0, 0x1f, 0xff, 0xe0, 0x60, 0x00, 0x1c, 0x00, 0xe0, 0x00, 0x18, 0x00, 0x70, 0x00, 0x1c, 0x00, + 0x60, 0x00, 0x38, 0x00, 0x70, 0x00, 0x18, 0x00, 0x70, 0x00, 0x30, 0x00, 0x30, 0x00, 0x38, 0x00, + 0x38, 0x00, 0x70, 0x00, 0x38, 0x00, 0x70, 0x00, 0x3c, 0x00, 0xe0, 0x00, 0x1c, 0x00, 0xf0, 0x00, + 0x1e, 0x03, 0xc0, 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x0f, 0xff, 0x80, 0x00, 0x07, 0xff, 0xc0, 0x00, + 0x03, 0xfe, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_12_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0e, 0x07, 0x00, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x06, 0x1f, 0xff, 0x80, + 0x00, 0x0f, 0xfc, 0x00, 0x07, 0x3f, 0xff, 0x80, 0x00, 0x00, 0xf8, 0x00, 0x07, 0x1f, 0xff, 0x00, + 0x00, 0x00, 0xe0, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0f, 0xff, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x71, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x1f, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x3f, 0xe0, 0x1d, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x39, 0xc0, 0x00, 0x00, + 0x00, 0x00, 0x7e, 0x00, 0x79, 0xc0, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x70, 0xff, 0x00, 0x00, + 0x03, 0xff, 0xe7, 0x00, 0xe3, 0xff, 0xc0, 0x00, 0x0f, 0x83, 0xe3, 0x81, 0xe7, 0xe1, 0xf0, 0x00, + 0x1e, 0x03, 0xf3, 0x81, 0xff, 0xf0, 0x70, 0x00, 0x1c, 0x03, 0xf1, 0xc3, 0xff, 0xf0, 0x38, 0x00, + 0x38, 0x07, 0x39, 0xe7, 0x9c, 0x70, 0x1c, 0x00, 0x30, 0x0f, 0x18, 0xe7, 0x38, 0x38, 0x1c, 0x00, + 0x70, 0x0e, 0x1c, 0x7e, 0x38, 0x38, 0x0c, 0x00, 0x70, 0x1d, 0xff, 0xff, 0xff, 0xf8, 0x0e, 0x00, + 0x70, 0x3f, 0xff, 0xff, 0xff, 0xfc, 0x0e, 0x00, 0x60, 0x3f, 0xff, 0xff, 0xf0, 0x1c, 0x0e, 0x00, + 0x70, 0x0f, 0xff, 0xff, 0xf0, 0x00, 0x0e, 0x00, 0x70, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x0c, 0x00, + 0x30, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x0c, 0x00, 0x38, 0x00, 0x18, 0x00, 0x18, 0x00, 0x1c, 0x00, + 0x1c, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x1e, 0x00, 0x70, 0x00, 0x0e, 0x00, 0x78, 0x00, + 0x0f, 0x01, 0xe0, 0x00, 0x07, 0x80, 0xf0, 0x00, 0x07, 0xff, 0xc0, 0x00, 0x03, 0xff, 0xe0, 0x00, + 0x01, 0xff, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_13_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x7f, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xfe, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x77, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0x03, 0x80, 0x00, 0x00, 0x07, 0xfe, 0x00, 0x03, 0xff, 0xff, 0x80, + 0x00, 0x07, 0xfe, 0x00, 0x03, 0xff, 0xff, 0x80, 0x00, 0x00, 0xfc, 0x00, 0x03, 0xff, 0xff, 0x00, + 0x00, 0x00, 0x78, 0x00, 0x3f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x38, 0x07, 0xff, 0xc0, 0x00, 0x00, + 0x00, 0x00, 0x1c, 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xff, 0x87, 0xe0, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0xf0, 0x0e, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x1e, 0xe0, 0x00, 0x00, + 0x00, 0x00, 0x3f, 0x00, 0x1c, 0x60, 0x00, 0x00, 0x00, 0x7f, 0xbb, 0x80, 0x38, 0x7f, 0xc0, 0x00, + 0x01, 0xff, 0xf3, 0x80, 0x78, 0xff, 0xe0, 0x00, 0x03, 0xc0, 0xf1, 0xc0, 0x73, 0xf0, 0xf8, 0x00, + 0x07, 0x00, 0xf9, 0xff, 0xff, 0xb8, 0x3c, 0x00, 0x0e, 0x01, 0xdc, 0xff, 0xff, 0xb8, 0x1c, 0x00, + 0x1c, 0x03, 0xcc, 0x71, 0xce, 0x18, 0x0e, 0x00, 0x1c, 0x03, 0x8e, 0x73, 0x8c, 0x1c, 0x06, 0x00, + 0x18, 0x07, 0x0e, 0x3f, 0x9c, 0x1c, 0x07, 0x00, 0x38, 0x0f, 0xff, 0xff, 0xfe, 0x0c, 0x03, 0x00, + 0x38, 0x0f, 0xff, 0xff, 0xfe, 0x0e, 0x03, 0x00, 0x38, 0x0f, 0xff, 0xfe, 0x18, 0x0e, 0x03, 0x00, + 0x38, 0x07, 0xff, 0xbf, 0x18, 0x00, 0x07, 0x00, 0x18, 0x00, 0x06, 0x07, 0xfc, 0x00, 0x07, 0x00, + 0x18, 0x00, 0x0e, 0x0f, 0xfc, 0x00, 0x06, 0x00, 0x1c, 0x00, 0x0c, 0x0f, 0xfe, 0x00, 0x0e, 0x00, + 0x0e, 0x00, 0x1c, 0x00, 0x06, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x38, 0x00, 0x07, 0x00, 0x1c, 0x00, + 0x07, 0xc0, 0xf0, 0x00, 0x03, 0xc0, 0x78, 0x00, 0x03, 0xff, 0xe0, 0x00, 0x01, 0xff, 0xf0, 0x00, + 0x00, 0xff, 0xc0, 0x00, 0x00, 0x7f, 0xc0, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_14_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x03, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x01, 0xf7, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc1, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0, 0xe0, 0x00, 0x00, 0x01, 0xff, 0x00, 0x01, 0xff, 0xff, 0x00, + 0x00, 0x01, 0xff, 0x80, 0x01, 0xff, 0xff, 0x00, 0x00, 0x00, 0xbc, 0x00, 0x00, 0xff, 0xff, 0x00, + 0x00, 0x00, 0x1c, 0x00, 0x1f, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x01, 0xff, 0xe0, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x3f, 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0xff, 0xe3, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xfc, 0x03, 0xb0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x80, 0x07, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0xc0, 0x0e, 0x38, 0x00, 0x00, 0x00, 0x3f, 0xdf, 0xc0, 0x1e, 0x3f, 0xe0, 0x00, + 0x00, 0x7f, 0xfc, 0xe0, 0x1c, 0x7f, 0xf8, 0x00, 0x01, 0xf0, 0x7c, 0xf0, 0x7c, 0xfc, 0x3c, 0x00, + 0x03, 0xc0, 0x7f, 0xff, 0xff, 0xec, 0x0e, 0x00, 0x07, 0x80, 0x7f, 0xff, 0xff, 0x8e, 0x07, 0x00, + 0x07, 0x00, 0xe7, 0x38, 0xe3, 0x0e, 0x03, 0x80, 0x0e, 0x01, 0xe3, 0x1c, 0xe7, 0x0e, 0x03, 0x80, + 0x0e, 0x01, 0xc3, 0x9f, 0xc6, 0x07, 0x01, 0x80, 0x0c, 0x03, 0xff, 0xff, 0xc6, 0x07, 0x01, 0x80, + 0x0c, 0x07, 0xff, 0xff, 0x86, 0x07, 0x01, 0xc0, 0x0c, 0x07, 0xff, 0xff, 0x06, 0x03, 0x01, 0xc0, + 0x0c, 0x03, 0xbf, 0xff, 0x06, 0x00, 0x01, 0x80, 0x0e, 0x00, 0x03, 0x87, 0x06, 0x00, 0x01, 0x80, + 0x0e, 0x00, 0x03, 0x0f, 0xc7, 0x00, 0x01, 0x80, 0x07, 0x00, 0x07, 0x3f, 0xc7, 0x00, 0x03, 0x80, + 0x07, 0x00, 0x06, 0x3f, 0x83, 0x80, 0x07, 0x00, 0x03, 0x80, 0x0e, 0x00, 0x01, 0xc0, 0x0f, 0x00, + 0x01, 0xe0, 0x3c, 0x00, 0x00, 0xf0, 0x1e, 0x00, 0x00, 0xff, 0xf8, 0x00, 0x00, 0x7f, 0xf8, 0x00, + 0x00, 0x3f, 0xe0, 0x00, 0x00, 0x3f, 0xf0, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x07, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_15_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x7f, 0xc0, 0x01, 0xff, 0xfc, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x01, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x01, 0xff, 0xfc, 0x00, + 0x00, 0x00, 0x07, 0x00, 0x07, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x8f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xf0, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xfe, 0x01, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x01, 0xcc, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xf0, 0x03, 0x8e, 0x00, 0x00, 0x00, 0x0f, 0xf7, 0x70, 0x07, 0x0f, 0xf8, 0x00, + 0x00, 0x3f, 0xff, 0x38, 0x07, 0x1f, 0xfe, 0x00, 0x00, 0x78, 0x3e, 0x38, 0x0e, 0x3f, 0x0f, 0x00, + 0x00, 0xe1, 0xff, 0xff, 0xff, 0xf7, 0x07, 0x80, 0x01, 0xc0, 0xff, 0xff, 0xff, 0xe3, 0x01, 0xc0, + 0x01, 0x80, 0x39, 0x8e, 0x38, 0xc3, 0x80, 0xc0, 0x03, 0x80, 0x71, 0xc7, 0x79, 0xc3, 0x80, 0xe0, + 0x03, 0x00, 0xf0, 0xc7, 0xf1, 0x81, 0x80, 0x60, 0x03, 0x01, 0xff, 0xc3, 0xe3, 0x81, 0xc0, 0x60, + 0x03, 0x01, 0xff, 0xff, 0xe3, 0x81, 0xc0, 0x60, 0x03, 0x01, 0xff, 0xff, 0xc3, 0x80, 0xc0, 0x60, + 0x03, 0x00, 0xef, 0xff, 0x83, 0x80, 0x00, 0x60, 0x03, 0x00, 0x00, 0xff, 0x81, 0x80, 0x00, 0x60, + 0x03, 0x80, 0x00, 0xff, 0x01, 0x80, 0x00, 0xe0, 0x01, 0x80, 0x01, 0xc0, 0x01, 0xc0, 0x00, 0xc0, + 0x01, 0xc0, 0x03, 0x80, 0x00, 0xe0, 0x01, 0xc0, 0x00, 0xe0, 0x07, 0x00, 0x00, 0xf0, 0x03, 0x80, + 0x00, 0x78, 0x0f, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x1f, 0xfe, 0x00, + 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_16_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x1f, 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xff, 0xff, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x0f, 0xef, 0x7f, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x38, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x1c, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x01, 0xff, 0xfc, 0x00, + 0x00, 0x00, 0x3f, 0xf0, 0x03, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x03, 0x80, 0x01, 0xff, 0xf0, 0x00, + 0x00, 0x00, 0x03, 0x80, 0x03, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0, 0x3f, 0xfe, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xe7, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xfc, 0x3e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xff, 0x80, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0xf7, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xf8, 0x01, 0xe3, 0x00, 0x00, 0x00, 0x03, 0xfd, 0xfc, 0x01, 0xc3, 0xfc, 0x00, + 0x00, 0x0f, 0xff, 0x9c, 0x03, 0x87, 0xff, 0x00, 0x00, 0x3f, 0x0f, 0x9e, 0x17, 0x9f, 0x87, 0xc0, + 0x00, 0x3f, 0xff, 0xff, 0xff, 0xbd, 0xc1, 0xe0, 0x00, 0x7f, 0xff, 0xff, 0xff, 0xf9, 0xc0, 0xe0, + 0x00, 0xe0, 0x1e, 0xe3, 0x9e, 0x71, 0xc0, 0x70, 0x00, 0xc0, 0x1c, 0x63, 0x9c, 0x60, 0xe0, 0x30, + 0x00, 0xc0, 0x38, 0x71, 0xf8, 0xe0, 0xe0, 0x38, 0x01, 0xc1, 0xf8, 0x3f, 0xf8, 0xc0, 0xe0, 0x38, + 0x01, 0xc1, 0xff, 0xff, 0xf0, 0xc0, 0x70, 0x38, 0x01, 0xc0, 0xff, 0xff, 0xe0, 0xc0, 0x70, 0x18, + 0x01, 0xc0, 0x3f, 0xff, 0xc0, 0xe0, 0x00, 0x38, 0x01, 0xc0, 0x00, 0x30, 0x00, 0xe0, 0x00, 0x38, + 0x00, 0xc0, 0x00, 0x70, 0x00, 0x60, 0x00, 0x30, 0x00, 0xe0, 0x00, 0x60, 0x00, 0x60, 0x00, 0x70, + 0x00, 0x70, 0x00, 0xe0, 0x00, 0x70, 0x00, 0x60, 0x00, 0x78, 0x01, 0xc0, 0x00, 0x38, 0x00, 0xe0, + 0x00, 0x3e, 0x07, 0x80, 0x00, 0x1e, 0x03, 0xc0, 0x00, 0x1f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x80, + 0x00, 0x07, 0xfe, 0x00, 0x00, 0x03, 0xfe, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x70, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_17_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x3f, 0xff, 0xdf, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xdf, 0xf8, 0x00, + 0x00, 0x00, 0x00, 0x1f, 0xff, 0x9f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1e, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0e, 0x00, 0x00, 0x00, 0x0f, 0xf8, 0x01, 0xff, 0x06, 0x00, + 0x00, 0x00, 0x1f, 0xf8, 0x01, 0xff, 0x86, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x01, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x71, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfe, 0x1f, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x3f, 0xe0, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x7b, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x7c, 0x00, 0x71, 0xc0, 0x00, 0x00, 0x01, 0xfe, 0xee, 0x00, 0xe1, 0xff, 0x00, + 0x00, 0x07, 0xff, 0xcf, 0x01, 0xe3, 0xff, 0xc0, 0x00, 0x5f, 0x8f, 0xc7, 0x01, 0xc7, 0xe3, 0xe0, + 0x01, 0xff, 0xff, 0xff, 0xff, 0x8e, 0xe0, 0xf0, 0x01, 0xff, 0xff, 0xff, 0xff, 0x9c, 0xe0, 0x30, + 0x00, 0x30, 0x0f, 0x33, 0xff, 0x38, 0x70, 0x38, 0x00, 0x70, 0x0e, 0x3b, 0xfe, 0x30, 0x70, 0x18, + 0x00, 0x60, 0x1c, 0x19, 0xfe, 0x30, 0x70, 0x1c, 0x00, 0x61, 0xfc, 0x18, 0x7c, 0x70, 0x38, 0x0c, + 0x00, 0x61, 0xff, 0xff, 0xf8, 0x70, 0x38, 0x0c, 0x00, 0xe0, 0x3f, 0xff, 0xf8, 0x70, 0x38, 0x0c, + 0x00, 0x60, 0x1f, 0xfd, 0xe0, 0x70, 0x00, 0x0c, 0x00, 0x60, 0x00, 0x18, 0x00, 0x30, 0x00, 0x0c, + 0x00, 0x70, 0x00, 0x38, 0x00, 0x30, 0x00, 0x1c, 0x00, 0x70, 0x00, 0x38, 0x00, 0x38, 0x00, 0x18, + 0x00, 0x38, 0x00, 0x70, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x1c, 0x00, 0xe0, 0x00, 0x1e, 0x00, 0x70, + 0x00, 0x0e, 0x03, 0xc0, 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x07, 0xff, 0x80, 0x00, 0x07, 0xff, 0xc0, + 0x00, 0x03, 0xff, 0x00, 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x3c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_21_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x3c, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x1f, 0xfc, 0x00, + 0x00, 0x00, 0x00, 0x1c, 0x00, 0x0f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x07, 0x00, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x07, 0x07, 0x00, + 0x00, 0x00, 0x0f, 0xfc, 0x00, 0x07, 0x07, 0x00, 0x00, 0x00, 0x04, 0xf0, 0x00, 0x07, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0f, 0xff, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x39, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x1f, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x1f, 0xe0, 0x1d, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3d, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x7e, 0x00, 0x39, 0xc0, 0x00, 0x00, 0x00, 0xff, 0x7f, 0x00, 0x70, 0xff, 0x80, + 0x00, 0x03, 0xff, 0xe7, 0x00, 0xe1, 0xff, 0xc0, 0x00, 0x0f, 0xc3, 0xe3, 0x80, 0xe7, 0xe1, 0xf0, + 0x3f, 0xff, 0xff, 0xf3, 0xc1, 0xcf, 0x70, 0x78, 0x3f, 0xff, 0xff, 0xf9, 0xc3, 0x8c, 0x70, 0x38, + 0x00, 0x38, 0x07, 0x38, 0xe7, 0x9c, 0x70, 0x1c, 0x00, 0x38, 0x07, 0x18, 0xe7, 0x18, 0x38, 0x0c, + 0x00, 0x30, 0x0e, 0x1c, 0x7e, 0x38, 0x38, 0x0e, 0x00, 0x70, 0x1e, 0x0c, 0x3e, 0x30, 0x38, 0x0e, + 0x00, 0x70, 0x1f, 0xff, 0xfc, 0x30, 0x1c, 0x0e, 0x00, 0x70, 0x3f, 0xff, 0xfc, 0x30, 0x1c, 0x0e, + 0x00, 0x70, 0x0f, 0xbf, 0xbc, 0x30, 0x00, 0x06, 0x00, 0x30, 0x00, 0x0c, 0x1c, 0x38, 0x00, 0x0e, + 0x00, 0x30, 0x00, 0x1c, 0x7f, 0x18, 0x00, 0x0c, 0x00, 0x38, 0x00, 0x18, 0x7f, 0x9c, 0x00, 0x1c, + 0x00, 0x1c, 0x00, 0x38, 0x7f, 0x1c, 0x00, 0x38, 0x00, 0x1e, 0x00, 0x70, 0x00, 0x0e, 0x00, 0x78, + 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x07, 0x80, 0xf0, 0x00, 0x07, 0xff, 0xc0, 0x00, 0x03, 0xff, 0xe0, + 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x1c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_19_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x0f, 0xfc, 0x00, + 0x00, 0x00, 0x00, 0x1f, 0xe0, 0x0f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x07, 0x00, 0x00, 0x00, 0x07, 0xfc, 0x01, 0xc7, 0x03, 0x00, + 0x00, 0x00, 0x0f, 0xfc, 0x03, 0xe7, 0x03, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0xc7, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x70, 0x00, 0x7f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0f, 0xff, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x39, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x0f, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x1f, 0xe0, 0x1d, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3d, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x3e, 0x00, 0x38, 0xe0, 0x00, 0x00, 0x00, 0xff, 0x77, 0x00, 0x70, 0xff, 0x80, + 0x00, 0x03, 0xff, 0xe7, 0x80, 0x71, 0xff, 0xe0, 0x00, 0x0f, 0xc3, 0xe3, 0x80, 0xe3, 0xf1, 0xf0, + 0x1f, 0xff, 0xff, 0xff, 0xf9, 0xc7, 0x70, 0x78, 0x1f, 0xff, 0xff, 0xff, 0xfb, 0xce, 0x70, 0x38, + 0x00, 0x18, 0x03, 0x98, 0xe3, 0x9c, 0x38, 0x1c, 0x00, 0x38, 0x07, 0x1c, 0x77, 0x18, 0x38, 0x0c, + 0x00, 0x30, 0x0e, 0x0c, 0x7f, 0x18, 0x38, 0x0e, 0x00, 0x30, 0x0e, 0x0c, 0x3f, 0xf8, 0x1c, 0x06, + 0x00, 0x30, 0x1f, 0xff, 0xff, 0xf8, 0x1c, 0x06, 0x00, 0x30, 0x1f, 0xff, 0xff, 0xb8, 0x1c, 0x06, + 0x00, 0x30, 0x0f, 0xff, 0xf8, 0x38, 0x08, 0x06, 0x00, 0x30, 0x00, 0x0c, 0x00, 0x38, 0x00, 0x0e, + 0x00, 0x38, 0x00, 0x0c, 0x00, 0x18, 0x00, 0x0e, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x1c, 0x00, 0x0c, + 0x00, 0x1c, 0x00, 0x38, 0x00, 0x0e, 0x00, 0x1c, 0x00, 0x0e, 0x00, 0x70, 0x00, 0x0f, 0x00, 0x38, + 0x00, 0x07, 0x80, 0xe0, 0x00, 0x07, 0xc0, 0xf0, 0x00, 0x03, 0xff, 0xc0, 0x00, 0x03, 0xff, 0xe0, + 0x00, 0x01, 0xff, 0x80, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x1c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_22_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x30, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x1f, 0xfc, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x1f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0f, 0x00, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x0e, 0x07, 0x00, + 0x00, 0x00, 0x0f, 0xfc, 0x00, 0x07, 0x07, 0x00, 0x00, 0x00, 0x03, 0xf8, 0x00, 0x07, 0x02, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0f, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x73, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x1f, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x3f, 0xe0, 0x3d, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x39, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x7e, 0x00, 0x79, 0xc0, 0x00, 0x00, 0x01, 0xfe, 0xfe, 0x00, 0xf1, 0xff, 0x00, + 0x00, 0x07, 0xff, 0xe7, 0x00, 0xe3, 0xff, 0xc0, 0x00, 0x0f, 0x83, 0xe7, 0x81, 0xc7, 0xe1, 0xe0, + 0x3f, 0xff, 0xe3, 0xf3, 0x81, 0xce, 0xe0, 0x70, 0x3f, 0xff, 0xe3, 0xf1, 0xc3, 0x9c, 0x70, 0x38, + 0x00, 0x38, 0x07, 0x39, 0xc7, 0x18, 0x70, 0x18, 0x00, 0x30, 0x0f, 0x18, 0xe7, 0x38, 0x70, 0x1c, + 0x00, 0x70, 0x0e, 0x1c, 0x7e, 0x30, 0x38, 0x0c, 0x00, 0x60, 0x1c, 0x1c, 0x7c, 0x30, 0x38, 0x0c, + 0x00, 0x60, 0x3f, 0xff, 0xfc, 0x30, 0x38, 0x0e, 0x00, 0x60, 0x3f, 0xff, 0xf8, 0x30, 0x18, 0x0e, + 0x00, 0x60, 0x1f, 0xff, 0xf0, 0x30, 0x00, 0x0c, 0x00, 0x70, 0x00, 0x1f, 0xf0, 0x30, 0x00, 0x0c, + 0x00, 0x70, 0x00, 0x1f, 0xf8, 0x38, 0x00, 0x0c, 0x00, 0x38, 0x00, 0x3f, 0xf8, 0x18, 0x00, 0x1c, + 0x00, 0x38, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x1c, 0x00, 0xf0, 0x00, 0x0e, 0x00, 0x70, + 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x07, 0x80, 0xf0, 0x00, 0x07, 0xff, 0xc0, 0x00, 0x03, 0xff, 0xc0, + 0x00, 0x03, 0xff, 0x00, 0x00, 0x01, 0xff, 0x80, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x3c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_23_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xf8, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1e, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0e, 0x00, 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x06, 0x00, + 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x06, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x73, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfe, 0x1f, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x3b, 0x80, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x7b, 0x80, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0x00, 0x71, 0xc0, 0x00, 0x00, 0x01, 0xfe, 0xee, 0x00, 0xe1, 0xff, 0x00, + 0x00, 0x07, 0xff, 0xcf, 0x01, 0xe3, 0xff, 0xc0, 0x00, 0x3f, 0x03, 0xc7, 0x01, 0xcf, 0xe3, 0xe0, + 0x3f, 0xfc, 0x03, 0xe3, 0x83, 0x8e, 0xe0, 0xf0, 0x3f, 0xf8, 0x07, 0xf3, 0xc7, 0x9c, 0xe0, 0x38, + 0x00, 0x70, 0x0f, 0x31, 0xc7, 0x38, 0x70, 0x38, 0x00, 0x70, 0x0e, 0x39, 0xee, 0x30, 0x70, 0x18, + 0x00, 0x60, 0x1c, 0x18, 0xfe, 0x70, 0x70, 0x1c, 0x00, 0x60, 0x3c, 0x18, 0x7c, 0x70, 0x38, 0x0c, + 0x00, 0xe0, 0x3f, 0xff, 0xf8, 0x70, 0x38, 0x0c, 0x00, 0x60, 0x3f, 0xff, 0xf8, 0x70, 0x38, 0x0c, + 0x00, 0x60, 0x1f, 0xff, 0xf0, 0x70, 0x00, 0x0c, 0x00, 0x60, 0x00, 0x18, 0x00, 0x70, 0x00, 0x1c, + 0x00, 0x70, 0x00, 0x38, 0x00, 0x30, 0x00, 0x1c, 0x00, 0x70, 0x00, 0x38, 0x00, 0x38, 0x00, 0x18, + 0x00, 0x38, 0x00, 0x70, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x1c, 0x00, 0xe0, 0x00, 0x1e, 0x00, 0x70, + 0x00, 0x0f, 0x03, 0xc0, 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x07, 0xff, 0x80, 0x00, 0x07, 0xff, 0xc0, + 0x00, 0x03, 0xff, 0x00, 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x3c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_25_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x3c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x1c, 0x00, 0x00, 0x00, 0x3f, 0xf0, 0x00, 0x1c, 0x1c, 0x00, + 0x00, 0x00, 0x3f, 0xf0, 0x00, 0x1c, 0x0c, 0x00, 0x00, 0x00, 0x13, 0xc0, 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xc0, 0x03, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x01, 0xc0, 0x3f, 0xfe, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe7, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xfc, 0x3e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x7f, 0x80, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0xf7, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xf8, 0x00, 0xe3, 0x80, 0x00, 0x00, 0x03, 0xfd, 0xdc, 0x01, 0xc3, 0xfe, 0x00, + 0x00, 0x0f, 0xff, 0x9c, 0x03, 0xc7, 0xff, 0x00, 0x00, 0x1e, 0x07, 0x8e, 0x03, 0x9f, 0x87, 0xc0, + 0x38, 0x38, 0x07, 0xcf, 0x07, 0x3d, 0xc1, 0xe0, 0x18, 0x70, 0x0e, 0xe7, 0xcf, 0x39, 0xc0, 0xe0, + 0x00, 0xe0, 0x1e, 0xe7, 0xfe, 0x70, 0xc0, 0x70, 0x00, 0xe0, 0x1c, 0x73, 0xfc, 0x60, 0xe0, 0x30, + 0x00, 0xc0, 0x38, 0x31, 0xfc, 0xe0, 0xe0, 0x38, 0x01, 0xc0, 0x78, 0x30, 0xf8, 0xc0, 0x60, 0x38, + 0x01, 0xc0, 0x7f, 0xff, 0xf0, 0xc0, 0x70, 0x18, 0x01, 0xc0, 0x7f, 0xff, 0xf0, 0xc0, 0x70, 0x18, + 0x00, 0xc0, 0x1f, 0xff, 0xc0, 0xe0, 0x00, 0x18, 0x00, 0xc0, 0x00, 0x30, 0x00, 0xe0, 0x00, 0x38, + 0x00, 0xc0, 0x00, 0x70, 0x00, 0x60, 0x00, 0x30, 0x00, 0xe0, 0x00, 0x60, 0x00, 0x70, 0x00, 0x70, + 0x00, 0x70, 0x00, 0xe0, 0x00, 0x30, 0x00, 0x70, 0x00, 0x78, 0x01, 0xc0, 0x00, 0x3c, 0x00, 0xe0, + 0x00, 0x3c, 0x07, 0x80, 0x00, 0x1e, 0x03, 0xc0, 0x00, 0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x80, + 0x00, 0x07, 0xfe, 0x00, 0x00, 0x03, 0xfe, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x70, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_26_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x38, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x18, 0x00, 0x00, 0x00, 0x3f, 0xe0, 0x00, 0x38, 0x1c, 0x00, + 0x00, 0x00, 0x3f, 0xe0, 0x00, 0x38, 0x1c, 0x00, 0x00, 0x00, 0x07, 0x80, 0x00, 0x1c, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x80, 0x03, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x7f, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xc7, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xf8, 0x7e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xff, 0x80, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0xe7, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xf8, 0x01, 0xc7, 0x00, 0x00, 0x00, 0x07, 0xfb, 0xb8, 0x03, 0xc7, 0xfc, 0x00, + 0x00, 0x1f, 0xff, 0x9c, 0x03, 0x8f, 0xff, 0x00, 0x00, 0x3c, 0x0f, 0x1c, 0x07, 0x1f, 0x87, 0x80, + 0x00, 0x78, 0x0f, 0x8e, 0x0f, 0x3b, 0x83, 0xc0, 0x00, 0xf0, 0x1f, 0xc7, 0xee, 0x71, 0xc0, 0xe0, + 0x00, 0xe0, 0x1c, 0xe7, 0xfe, 0x61, 0xc0, 0x60, 0x01, 0xc0, 0x38, 0xe3, 0xfe, 0xe1, 0xc0, 0x70, + 0x01, 0xc0, 0x78, 0x63, 0xfe, 0xc0, 0xe0, 0x30, 0x01, 0x80, 0x70, 0x71, 0xf0, 0xc0, 0xe0, 0x30, + 0x01, 0x80, 0xff, 0xff, 0xf1, 0xc0, 0xe0, 0x30, 0x01, 0x80, 0xff, 0xff, 0xe1, 0xc0, 0x60, 0x30, + 0x01, 0x80, 0x5f, 0xff, 0xc0, 0xc0, 0x00, 0x30, 0x01, 0x80, 0x00, 0x60, 0x00, 0xc0, 0x00, 0x30, + 0x01, 0xc0, 0x00, 0x60, 0x00, 0xc0, 0x00, 0x70, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0x60, + 0x00, 0xe0, 0x01, 0xc0, 0x00, 0x70, 0x00, 0xe0, 0x00, 0x70, 0x03, 0xc0, 0x00, 0x38, 0x01, 0xc0, + 0x00, 0x3c, 0x07, 0x80, 0x00, 0x1c, 0x07, 0x80, 0x00, 0x1f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, + 0x00, 0x07, 0xfc, 0x00, 0x00, 0x07, 0xfe, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_20_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x3f, 0x80, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x80, 0x0f, 0xfc, 0x00, + 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x07, 0x00, 0x00, 0x00, 0x0f, 0xfc, 0x01, 0x87, 0x03, 0x00, + 0x00, 0x00, 0x0f, 0xfc, 0x03, 0x87, 0x03, 0x00, 0x00, 0x00, 0x04, 0xe8, 0x01, 0x87, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x70, 0x00, 0x7f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0f, 0xff, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x39, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x0f, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x1f, 0xe0, 0x1d, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3d, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x3e, 0x00, 0x38, 0xe0, 0x00, 0x00, 0x00, 0xff, 0x77, 0x00, 0x70, 0xff, 0x80, + 0x00, 0x03, 0xff, 0xe7, 0x80, 0xf1, 0xff, 0xe0, 0x00, 0x0f, 0xc3, 0xe3, 0x80, 0xe7, 0xf1, 0xf0, + 0x3f, 0xff, 0xff, 0xff, 0xc1, 0xc7, 0x70, 0x78, 0x3f, 0xff, 0xff, 0xff, 0xc3, 0xce, 0x70, 0x38, + 0x00, 0x18, 0x07, 0x98, 0xe3, 0x9c, 0x38, 0x1c, 0x00, 0x38, 0x07, 0x1c, 0x77, 0x18, 0x38, 0x0c, + 0x00, 0x30, 0x0e, 0x0c, 0x7f, 0x18, 0x38, 0x0e, 0x00, 0x30, 0x1e, 0x0c, 0x3e, 0x38, 0x1c, 0x06, + 0x00, 0x70, 0x1f, 0xff, 0xfc, 0x30, 0x1c, 0x06, 0x00, 0x70, 0x1f, 0xff, 0xfe, 0x30, 0x1c, 0x06, + 0x00, 0x30, 0x0f, 0xbf, 0xff, 0xf8, 0x00, 0x06, 0x00, 0x30, 0x00, 0x0c, 0x0f, 0xf8, 0x00, 0x0e, + 0x00, 0x38, 0x00, 0x1c, 0x0f, 0xf8, 0x00, 0x0e, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x1c, 0x00, 0x0c, + 0x00, 0x1c, 0x00, 0x38, 0x00, 0x0e, 0x00, 0x1c, 0x00, 0x0e, 0x00, 0x70, 0x00, 0x0f, 0x00, 0x38, + 0x00, 0x0f, 0x00, 0xe0, 0x00, 0x07, 0x80, 0xf0, 0x00, 0x03, 0xff, 0xc0, 0x00, 0x03, 0xff, 0xe0, + 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x1c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_27_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x78, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x38, 0x00, 0x00, 0x00, 0x7f, 0xe0, 0x00, 0x30, 0x38, 0x00, + 0x00, 0x00, 0x7f, 0xe0, 0x00, 0x38, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x40, 0x00, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x80, 0x07, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0x80, 0x7f, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xcf, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xf8, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xff, 0x00, 0xee, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf0, 0x01, 0xce, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xf0, 0x01, 0xc6, 0x00, 0x00, 0x00, 0x07, 0xff, 0xb8, 0x03, 0x87, 0xfc, 0x00, + 0x00, 0x1f, 0xff, 0x38, 0x07, 0x0f, 0xfe, 0x00, 0x00, 0x7c, 0x1f, 0x1c, 0x0f, 0x3f, 0x0f, 0x00, + 0x00, 0x70, 0x0f, 0x9e, 0x0e, 0x7b, 0x83, 0xc0, 0x00, 0xe0, 0x1d, 0x8e, 0x1c, 0x73, 0x81, 0xc0, + 0x01, 0xc0, 0x39, 0xcf, 0x3c, 0xe3, 0x80, 0xe0, 0x01, 0x80, 0x78, 0xe7, 0x7d, 0xc1, 0xc0, 0x60, + 0x01, 0x80, 0x70, 0xe3, 0xff, 0xc1, 0xc0, 0x60, 0x03, 0x80, 0xe0, 0x63, 0xff, 0x81, 0xc0, 0x70, + 0x03, 0x81, 0xff, 0xff, 0xf1, 0x80, 0xe0, 0x70, 0x03, 0x81, 0xff, 0xff, 0xe1, 0x80, 0xe0, 0x30, + 0x03, 0x80, 0x7d, 0xff, 0x81, 0x80, 0x00, 0x70, 0x01, 0x80, 0x00, 0xe0, 0x01, 0xc0, 0x00, 0x70, + 0x01, 0x80, 0x00, 0xe0, 0x01, 0xc0, 0x00, 0x60, 0x01, 0xc0, 0x00, 0xc0, 0x00, 0xe0, 0x00, 0xe0, + 0x00, 0xc0, 0x01, 0xc0, 0x00, 0xe0, 0x00, 0xc0, 0x00, 0xf0, 0x03, 0x80, 0x00, 0x70, 0x01, 0xc0, + 0x00, 0x78, 0x0f, 0x00, 0x00, 0x3c, 0x07, 0x80, 0x00, 0x3f, 0xfe, 0x00, 0x00, 0x1f, 0xff, 0x00, + 0x00, 0x0f, 0xfc, 0x00, 0x00, 0x07, 0xfc, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x00, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_18_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x3f, 0xfe, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x1f, 0xfc, 0x00, + 0x00, 0x00, 0x00, 0x17, 0xf6, 0x0f, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x07, 0x00, 0x00, 0x00, 0x0f, 0xf8, 0x01, 0xff, 0x07, 0x00, + 0x00, 0x00, 0x0f, 0xfc, 0x01, 0xff, 0x03, 0x00, 0x00, 0x00, 0x04, 0xf0, 0x01, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xf0, 0x00, 0x7f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x70, 0x0f, 0xff, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x79, 0xff, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0x0f, 0x80, 0x00, + 0x00, 0x00, 0x00, 0x1f, 0xe0, 0x1d, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x3d, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x7e, 0x00, 0x38, 0xc0, 0x00, 0x00, 0x00, 0xff, 0x7f, 0x00, 0x70, 0xff, 0x00, + 0x00, 0x03, 0xff, 0xe7, 0x00, 0xe1, 0xff, 0xe0, 0x00, 0x0f, 0xc3, 0xe3, 0x81, 0xe7, 0xe1, 0xf0, + 0x0f, 0xff, 0xff, 0xff, 0xff, 0xcf, 0x70, 0x70, 0x0f, 0xff, 0xff, 0xff, 0xff, 0x8e, 0x70, 0x38, + 0x00, 0x38, 0x07, 0xb8, 0xff, 0xdc, 0x30, 0x1c, 0x00, 0x38, 0x0f, 0x18, 0xff, 0xd8, 0x38, 0x0c, + 0x00, 0x30, 0x0e, 0x1c, 0x7f, 0x38, 0x38, 0x0e, 0x00, 0x70, 0x1c, 0x0c, 0x7e, 0x30, 0x38, 0x0e, + 0x00, 0x70, 0x1f, 0xff, 0xfc, 0x30, 0x1c, 0x0e, 0x00, 0x70, 0x3f, 0xff, 0xfc, 0x30, 0x1c, 0x06, + 0x00, 0x70, 0x0f, 0xfd, 0xf0, 0x30, 0x00, 0x0e, 0x00, 0x30, 0x00, 0x1c, 0x00, 0x38, 0x00, 0x0e, + 0x00, 0x30, 0x00, 0x1c, 0x00, 0x18, 0x00, 0x0e, 0x00, 0x38, 0x00, 0x18, 0x00, 0x1c, 0x00, 0x1c, + 0x00, 0x1c, 0x00, 0x38, 0x00, 0x1c, 0x00, 0x18, 0x00, 0x1e, 0x00, 0x70, 0x00, 0x0e, 0x00, 0x38, + 0x00, 0x0f, 0x01, 0xe0, 0x00, 0x07, 0x80, 0xf0, 0x00, 0x07, 0xff, 0xc0, 0x00, 0x03, 0xff, 0xe0, + 0x00, 0x01, 0xff, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x1c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_30_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x70, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x2e, 0x80, 0x00, 0x70, 0x20, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x07, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x9f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf0, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x8c, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0x07, 0x0f, 0xf8, 0x00, + 0x00, 0x7f, 0xfe, 0x70, 0x0e, 0x1f, 0xfc, 0x00, 0x00, 0xf8, 0x3e, 0x38, 0x0e, 0x7e, 0x1f, 0x00, + 0x00, 0xe0, 0x1f, 0x3c, 0x1c, 0xf7, 0x07, 0x80, 0x01, 0xc0, 0x3b, 0x9c, 0x3c, 0xe7, 0x03, 0x80, + 0x03, 0x80, 0x7b, 0x8e, 0x39, 0xc7, 0x01, 0xc0, 0x03, 0x00, 0x71, 0x8e, 0x71, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x83, 0x80, 0xc0, 0x07, 0x01, 0xe0, 0xc7, 0xe3, 0x83, 0x80, 0xe0, + 0x07, 0x01, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0x60, 0x07, 0x03, 0xff, 0xff, 0xe3, 0x01, 0xc0, 0xe0, + 0x07, 0x00, 0xff, 0xff, 0xf3, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x01, 0xc0, 0xff, 0x80, 0x00, 0xe0, + 0x03, 0x00, 0x01, 0xc0, 0xff, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x03, 0x80, 0xf9, 0x80, 0x01, 0xc0, + 0x01, 0xc0, 0x03, 0x80, 0x01, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x00, 0x00, 0xe0, 0x07, 0x80, + 0x00, 0xf8, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_33_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x60, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x07, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x9f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x9c, 0x00, 0x00, 0x00, 0x0f, 0xf7, 0xf0, 0x07, 0x0f, 0xf0, 0x00, + 0x00, 0x3f, 0xfe, 0x70, 0x0e, 0x3f, 0xfc, 0x00, 0x00, 0x78, 0x3e, 0x38, 0x1e, 0x7e, 0x1e, 0x00, + 0x00, 0xe0, 0x3f, 0x38, 0x1c, 0xf7, 0x07, 0x80, 0x01, 0xc0, 0x3b, 0x1c, 0x38, 0xc7, 0x03, 0x80, + 0x03, 0x80, 0x7b, 0x8e, 0x79, 0xc7, 0x01, 0xc0, 0x03, 0x00, 0x71, 0xce, 0x73, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x83, 0x80, 0xc0, 0x07, 0x01, 0xc0, 0xc7, 0xe3, 0x03, 0x80, 0xe0, + 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, + 0x07, 0x00, 0xbf, 0xff, 0xc3, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x01, 0xc1, 0xc3, 0x80, 0x00, 0xe0, + 0x03, 0x00, 0x01, 0xc7, 0xf3, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x03, 0x87, 0xf9, 0x80, 0x01, 0xc0, + 0x01, 0xc0, 0x03, 0x87, 0xf1, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x00, 0x00, 0xe0, 0x07, 0x80, + 0x00, 0xf0, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_24_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xf8, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x1c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x0e, 0x00, 0x00, 0x00, 0x1f, 0xf0, 0x00, 0x1c, 0x0e, 0x00, + 0x00, 0x00, 0x1f, 0xf8, 0x00, 0x0e, 0x0e, 0x00, 0x00, 0x00, 0x07, 0xd0, 0x00, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xc0, 0x01, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0xfe, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe3, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfe, 0x3f, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x7f, 0xc0, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x73, 0x80, 0x00, + 0x00, 0x00, 0x00, 0xfc, 0x00, 0xe3, 0x80, 0x00, 0x00, 0x03, 0xfd, 0xfc, 0x00, 0xe3, 0xfe, 0x00, + 0x00, 0x0f, 0xff, 0xce, 0x01, 0xc7, 0xff, 0x80, 0x00, 0x1f, 0x07, 0xcf, 0x03, 0xcf, 0xc3, 0xc0, + 0x3f, 0x3c, 0x07, 0xe7, 0x03, 0x9d, 0xc0, 0xe0, 0x3f, 0x38, 0x07, 0xe3, 0x87, 0x38, 0xe0, 0x70, + 0x00, 0x70, 0x0e, 0x73, 0x8f, 0x38, 0xe0, 0x30, 0x00, 0x60, 0x1c, 0x3f, 0xce, 0x70, 0xe0, 0x38, + 0x00, 0xe0, 0x1c, 0x3f, 0xfc, 0x70, 0x70, 0x18, 0x00, 0xc0, 0x38, 0x3f, 0xf8, 0x60, 0x70, 0x18, + 0x00, 0xc0, 0x7f, 0xff, 0xf8, 0x60, 0x70, 0x1c, 0x00, 0xc0, 0x7f, 0xff, 0xf0, 0x60, 0x30, 0x1c, + 0x00, 0xc0, 0x1f, 0xff, 0xc0, 0x60, 0x00, 0x18, 0x00, 0xe0, 0x00, 0x38, 0x00, 0x60, 0x00, 0x18, + 0x00, 0xe0, 0x00, 0x30, 0x00, 0x70, 0x00, 0x38, 0x00, 0x70, 0x00, 0x70, 0x00, 0x30, 0x00, 0x38, + 0x00, 0x70, 0x00, 0x60, 0x00, 0x38, 0x00, 0x70, 0x00, 0x38, 0x01, 0xe0, 0x00, 0x1c, 0x00, 0xe0, + 0x00, 0x1e, 0x03, 0xc0, 0x00, 0x0f, 0x03, 0xe0, 0x00, 0x0f, 0xff, 0x80, 0x00, 0x07, 0xff, 0x80, + 0x00, 0x03, 0xfe, 0x00, 0x00, 0x03, 0xff, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x70, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_29_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x70, 0x00, 0x00, 0x00, 0x7f, 0xc0, 0x00, 0x70, 0x30, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x30, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x00, 0x07, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x8f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf0, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x03, 0xdc, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x03, 0x8e, 0x00, 0x00, 0x00, 0x0f, 0xf7, 0x70, 0x07, 0x0f, 0xf8, 0x00, + 0x00, 0x3f, 0xfe, 0x78, 0x0f, 0x1f, 0xfe, 0x00, 0x00, 0x78, 0x1e, 0x38, 0x0e, 0x7f, 0x1f, 0x00, + 0x00, 0xe0, 0x1f, 0x1c, 0x1c, 0x77, 0x07, 0x80, 0x01, 0xc0, 0x3b, 0x9c, 0x3c, 0xe7, 0x01, 0xc0, + 0x01, 0x80, 0x79, 0x8e, 0x39, 0xc3, 0x81, 0xc0, 0x03, 0x80, 0x71, 0xcf, 0x71, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe0, 0xc7, 0xf3, 0x83, 0x80, 0xe0, 0x03, 0x01, 0xe0, 0xc3, 0xe3, 0x81, 0xc0, 0x60, + 0x07, 0x01, 0xff, 0xff, 0xe3, 0x81, 0xc0, 0x60, 0x07, 0x01, 0xff, 0xff, 0xff, 0x81, 0xc0, 0x60, + 0x03, 0x00, 0xdd, 0xfd, 0xff, 0x80, 0x00, 0x60, 0x03, 0x00, 0x00, 0xc0, 0x7f, 0x80, 0x00, 0xe0, + 0x03, 0x80, 0x01, 0xc0, 0x01, 0x80, 0x00, 0xe0, 0x03, 0x80, 0x01, 0x80, 0x01, 0xc0, 0x00, 0xc0, + 0x01, 0xc0, 0x03, 0x80, 0x00, 0xe0, 0x01, 0xc0, 0x00, 0xe0, 0x07, 0x00, 0x00, 0xf0, 0x03, 0x80, + 0x00, 0xf8, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x3f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x00, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_28_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x7f, 0xc0, 0x00, 0x70, 0x38, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x38, 0x00, 0x00, 0x00, 0x0f, 0x40, 0x00, 0x38, 0x10, 0x00, + 0x00, 0x00, 0x07, 0x00, 0x07, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x07, 0x80, 0x7f, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x8f, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xf8, 0xfc, 0x00, 0x00, + 0x00, 0x00, 0x01, 0xff, 0x01, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x01, 0xce, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xf0, 0x03, 0x8e, 0x00, 0x00, 0x00, 0x0f, 0xf7, 0x70, 0x07, 0x8f, 0xf8, 0x00, + 0x00, 0x3f, 0xff, 0x38, 0x07, 0x1f, 0xfe, 0x00, 0x00, 0x7c, 0x1e, 0x38, 0x0e, 0x3f, 0x0f, 0x00, + 0x00, 0xf0, 0x1f, 0x1c, 0x1e, 0x77, 0x03, 0x80, 0x01, 0xc0, 0x3f, 0x9e, 0x1c, 0xe3, 0x81, 0xc0, + 0x01, 0xc0, 0x39, 0xce, 0x38, 0xc3, 0x80, 0xc0, 0x03, 0x80, 0x70, 0xc7, 0x79, 0xc3, 0x80, 0xe0, + 0x03, 0x80, 0xf0, 0xc7, 0xf1, 0x81, 0xc0, 0x60, 0x03, 0x00, 0xe0, 0xe3, 0xfd, 0x81, 0xc0, 0x60, + 0x03, 0x01, 0xff, 0xff, 0xff, 0x81, 0xc0, 0x60, 0x03, 0x01, 0xff, 0xff, 0xff, 0x80, 0xc0, 0x60, + 0x03, 0x00, 0xff, 0xff, 0xc1, 0x80, 0x00, 0x60, 0x03, 0x80, 0x00, 0xc0, 0x01, 0x80, 0x00, 0x60, + 0x03, 0x80, 0x00, 0xc0, 0x01, 0xc0, 0x00, 0xe0, 0x01, 0x80, 0x01, 0xc0, 0x01, 0xc0, 0x00, 0xe0, + 0x01, 0xc0, 0x03, 0x80, 0x00, 0xe0, 0x01, 0xc0, 0x00, 0xe0, 0x07, 0x80, 0x00, 0xf0, 0x03, 0x80, + 0x00, 0x78, 0x0f, 0x00, 0x00, 0x78, 0x0f, 0x80, 0x00, 0x3f, 0xfe, 0x00, 0x00, 0x1f, 0xfe, 0x00, + 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x0f, 0xfc, 0x00, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x01, 0xe0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_31_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x60, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x9f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x9c, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0x07, 0x0f, 0xf8, 0x00, + 0x00, 0x3f, 0xfe, 0x70, 0x0e, 0x3f, 0xfc, 0x00, 0x00, 0xf8, 0x3e, 0x38, 0x0e, 0x7e, 0x1f, 0x00, + 0x00, 0xe0, 0x1f, 0x38, 0x1c, 0xf7, 0x07, 0x80, 0x01, 0xc0, 0x3b, 0x1c, 0x38, 0xc7, 0x03, 0x80, + 0x03, 0x80, 0x7b, 0x8e, 0x39, 0xc7, 0x01, 0xc0, 0x03, 0x00, 0x71, 0xce, 0x71, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x83, 0x80, 0xc0, 0x07, 0x01, 0xc0, 0xc7, 0xe3, 0x03, 0x80, 0xe0, + 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0x60, + 0x07, 0x00, 0xfb, 0xff, 0xc3, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x01, 0xc0, 0xe3, 0x80, 0x00, 0xe0, + 0x03, 0x00, 0x01, 0xc3, 0xff, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x01, 0x83, 0xfd, 0x80, 0x01, 0xc0, + 0x01, 0xc0, 0x03, 0x80, 0x01, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x00, 0x00, 0xe0, 0x03, 0x80, + 0x00, 0xf0, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0xc0, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_35_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x60, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x07, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x9f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x9c, 0x00, 0x00, 0x00, 0x0f, 0xf7, 0xf0, 0x07, 0x0f, 0xf0, 0x00, + 0x00, 0x3f, 0xfe, 0x70, 0x0e, 0x3f, 0xfc, 0x00, 0x00, 0x78, 0x3e, 0x38, 0x1e, 0x7e, 0x1e, 0x00, + 0x00, 0xe0, 0x3f, 0x38, 0x1c, 0xf7, 0x07, 0x00, 0x01, 0xc0, 0x3b, 0x1c, 0x38, 0xc7, 0x03, 0x80, + 0x03, 0x80, 0x7b, 0x8e, 0x39, 0xc7, 0x01, 0xc0, 0x03, 0x00, 0x71, 0xce, 0x73, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x83, 0x80, 0xc0, 0x07, 0x01, 0xc0, 0xc7, 0xe3, 0x03, 0x80, 0xe0, + 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, 0x07, 0x03, 0xff, 0xff, 0x83, 0x01, 0xc0, 0xe0, + 0x07, 0x00, 0xfb, 0xff, 0x83, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x01, 0xc1, 0x83, 0x80, 0x00, 0xe0, + 0x03, 0x00, 0x01, 0xc1, 0xf3, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x03, 0x8f, 0xf1, 0x80, 0x01, 0xc0, + 0x01, 0xc0, 0x03, 0x8f, 0xe1, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x04, 0x00, 0xe0, 0x07, 0x80, + 0x00, 0xf0, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_32_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x60, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x0f, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x9f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xc0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x9c, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0x07, 0x0f, 0xf0, 0x00, + 0x00, 0x3f, 0xfe, 0x70, 0x0e, 0x1f, 0xfc, 0x00, 0x00, 0xf8, 0x3e, 0x38, 0x1e, 0x7e, 0x1e, 0x00, + 0x00, 0xe0, 0x3f, 0x38, 0x1c, 0xf7, 0x07, 0x80, 0x01, 0xc0, 0x3b, 0x1c, 0x38, 0xc7, 0x03, 0x80, + 0x03, 0x80, 0x7b, 0x8e, 0x79, 0xc7, 0x01, 0xc0, 0x03, 0x00, 0x71, 0xce, 0x73, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x83, 0x80, 0xc0, 0x07, 0x01, 0xc0, 0xc7, 0xe3, 0x03, 0x80, 0xe0, + 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, 0x07, 0x03, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, + 0x07, 0x00, 0xfd, 0xff, 0xc3, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x01, 0xc1, 0xc3, 0x80, 0x00, 0xe0, + 0x03, 0x00, 0x01, 0xc3, 0xfb, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x03, 0x87, 0xf9, 0x80, 0x01, 0xc0, + 0x01, 0xc0, 0x03, 0x83, 0xf9, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x00, 0x00, 0xe0, 0x07, 0x80, + 0x00, 0xf0, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf8, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + // 'frame_34_delay-0, 64x64px + + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xff, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xf0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x70, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x60, 0x70, 0x00, + 0x00, 0x00, 0xff, 0xc0, 0x00, 0x70, 0x70, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x07, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xff, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x07, 0x9f, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x03, 0xff, 0xf1, 0xf8, 0x00, 0x00, + 0x00, 0x00, 0x03, 0xfe, 0x01, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x03, 0x9c, 0x00, 0x00, + 0x00, 0x00, 0x07, 0xe0, 0x07, 0x9c, 0x00, 0x00, 0x00, 0x0f, 0xff, 0xf0, 0x07, 0x0f, 0xf0, 0x00, + 0x00, 0x3f, 0xfe, 0x70, 0x0e, 0x3f, 0xfc, 0x00, 0x00, 0x78, 0x3e, 0x38, 0x1e, 0x7e, 0x1e, 0x00, + 0x00, 0xe0, 0x3f, 0x38, 0x1c, 0xf7, 0x07, 0x80, 0x01, 0xc0, 0x3b, 0x1c, 0x38, 0xc7, 0x03, 0x80, + 0x03, 0x80, 0x7b, 0x8e, 0x79, 0xc7, 0x01, 0xc0, 0x03, 0x80, 0x71, 0xce, 0x73, 0x83, 0x80, 0xc0, + 0x03, 0x00, 0xe1, 0xc7, 0xe3, 0x83, 0x80, 0xc0, 0x07, 0x01, 0xc0, 0xc7, 0xe3, 0x03, 0x80, 0xe0, + 0x07, 0x01, 0xff, 0xff, 0xc3, 0x01, 0xc0, 0xe0, 0x07, 0x03, 0xff, 0xff, 0x83, 0x01, 0xc0, 0xe0, + 0x07, 0x00, 0xff, 0xfd, 0x83, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x01, 0xc1, 0x83, 0x80, 0x00, 0xe0, + 0x03, 0x00, 0x01, 0xc3, 0xf3, 0x80, 0x00, 0xc0, 0x03, 0x80, 0x03, 0x8f, 0xf1, 0x80, 0x01, 0xc0, + 0x01, 0xc0, 0x03, 0x8f, 0xf1, 0xc0, 0x03, 0x80, 0x01, 0xe0, 0x07, 0x00, 0x00, 0xe0, 0x07, 0x80, + 0x00, 0xf0, 0x1e, 0x00, 0x00, 0x78, 0x0f, 0x00, 0x00, 0x7f, 0xfc, 0x00, 0x00, 0x3f, 0xfe, 0x00, + 0x00, 0x1f, 0xf0, 0x00, 0x00, 0x0f, 0xf8, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x01, 0xc0, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } +}; \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/led/LED.cpp b/sensebox-bike-atrai-v2-esp32s3/src/led/LED.cpp new file mode 100644 index 0000000..86e3ddc --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/led/LED.cpp @@ -0,0 +1,87 @@ +#include "LED.h" + +// Constructor +LED::LED(uint8_t pin, uint16_t numPixels, uint8_t brightness) + : pixels(numPixels, pin, NEO_GRB + NEO_KHZ800), hue(0), taskHandle(NULL) +{ + pixels.setBrightness(brightness); +} + +// Initialize the NeoPixel strip +void LED::begin() +{ + pixels.begin(); +} + +// Start the FreeRTOS task to update the LED color +void LED::startRainbow() +{ + // Create the LED update task + xTaskCreate( + LEDTask, // Task function + "LED Task", // Name of the task (for debugging) + 1024, // Stack size (in words) + this, // Task input parameter (this LED instance) + 1, // Priority of the task + &taskHandle // Task handle + ); +} + +// Stop the FreeRTOS task +void LED::stopRainbow() +{ + if (taskHandle != NULL) + { + vTaskDelete(taskHandle); + taskHandle = NULL; + } + // turn off the LED + pixels.clear(); + pixels.show(); +} + +// Task function to update the LED color +void LED::LEDTask(void *pvParameters) +{ + LED *ledInstance = static_cast(pvParameters); + + // Infinite loop to continuously update the LED color + while (true) + { + ledInstance->update(); + vTaskDelay(pdMS_TO_TICKS(5)); // Delay of 10 milliseconds + } +} + +// Update the LED color to the next hue +void LED::update() +{ + pixels.setPixelColor(0, Wheel(hue)); + pixels.show(); + + hue += 1; + if (hue > 255) + { + hue = 0; + } +} + +// Private function to generate rainbow colors across 0-255 positions +uint32_t LED::Wheel(byte WheelPos) +{ + WheelPos = 255 - WheelPos; + if (WheelPos < 85) + { + return pixels.Color(255 - WheelPos * 3, 0, WheelPos * 3); + } + else if (WheelPos < 170) + { + WheelPos -= 85; + return pixels.Color(0, WheelPos * 3, 255 - WheelPos * 3); + } + else + { + WheelPos -= 170; + return pixels.Color(WheelPos * 3, 255 - WheelPos * 3, 0); + } +} diff --git a/sensebox-bike-atrai-v2-esp32s3/src/led/LED.h b/sensebox-bike-atrai-v2-esp32s3/src/led/LED.h new file mode 100644 index 0000000..07d82de --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/led/LED.h @@ -0,0 +1,25 @@ +#ifndef LED_H +#define LED_H + +#include +#include + +class LED +{ +public: + LED(uint8_t pin, uint16_t numPixels, uint8_t brightness = 50); + void begin(); + void startRainbow(); + void stopRainbow(); + +private: + uint32_t Wheel(byte WheelPos); + void update(); + static void LEDTask(void *pvParameters); + + Adafruit_NeoPixel pixels; + uint16_t hue; + TaskHandle_t taskHandle; +}; + +#endif diff --git a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp new file mode 100644 index 0000000..db93d53 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp @@ -0,0 +1,103 @@ +#include +#include "sensors/TempHumiditySensor/TempHumiditySensor.h" +#include "sensors/DustSensor/DustSensor.h" +#include "sensors/DistanceSensor/DistanceSensor.h" +#include "sensors/AccelerationSensor/AccelerationSensor.h" +#include "sensors/BatterySensor/BatterySensor.h" +// #include "display/Display.h" +#include "ble/BLEModule.h" +// #include "led/LED.h" + +// DustSensor dustSensor; +// TempHumiditySensor tempHumiditySensor; +DistanceSensor distanceSensor; +AccelerationSensor accelerationSensor; +// BatterySensor batterySensor; + +BaseSensor *sensors[] = { + // &dustSensor, + // &tempHumiditySensor, + &distanceSensor, + &accelerationSensor, + // &batterySensor + }; + +// SBDisplay display; + +BLEModule bleModule; +// LED led(1, 1); + +unsigned long previousMillis = 0; // stores the last time the sensors were read +const long interval = 3000; // interval at which to read the temperature and fine dust sensors (1 second) + +void setup() +{ + Serial.begin(115200); + delay(1000); + + // led.begin(); + + // led.startRainbow(); + + // SBDisplay::begin(); + + // pinMode(IO_ENABLE, OUTPUT); + // digitalWrite(IO_ENABLE, LOW); + + // SBDisplay::showLoading("Setup BLE...", 0.2); + bleModule.begin(); + + // batterySensor.begin(); + + bleModule.createService("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); + + // SBDisplay::showLoading("Setup Sensors...", 0.4); + for (BaseSensor *sensor : sensors) + { + sensor->begin(); + } + + // SBDisplay::showLoading("Ventilation...", 0.6); + // pinMode(3, OUTPUT); + // delay(100); + // digitalWrite(3, HIGH); + + // SBDisplay::showLoading("Start measurements...", 0.8); + // Start sensor measurements + for (BaseSensor *sensor : sensors) + { + sensor->startSubscription(); + } + + // SBDisplay::showLoading("Enable BLE...", 1); + + // Start BLE advertising + for (BaseSensor *sensor : sensors) + { + sensor->startBLE(); + } + + // display.readBleId(); + + // led.stopRainbow(); + + // display.showConnectionScreen(); + bleModule.bleStartPoll("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); +} + +void loop() +{ + // Read acceleration and distance sensor data as fast as possible + // distanceSensor.readSensorData(); + // bool classified = accelerationSensor.readSensorData(); + + // Read temperature and fine dust sensor data after a surface classification + // if (classified) + // { + // dustSensor.readSensorData(); + // tempHumiditySensor.readSensorData(); + // display.showConnectionScreen(); + // } + + // Perform BLE polling +} diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp new file mode 100644 index 0000000..1de9c1d --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp @@ -0,0 +1,121 @@ +#include "AccelerationSensor.h" +#include "edge-impulse-sdk/classifier/ei_run_classifier.h" + +AccelerationSensor::AccelerationSensor() : BaseSensor("accelerationSensorTask", 2048, 0) {} + +String surfaceClassificationUUID = "b944af10-f495-4560-968f-2f0d18cab521"; +// String accUUID = "B944AF10F4954560968F2F0D18CAB522"; +String anomalyUUID = "b944af10-f495-4560-968f-2f0d18cab523"; +int surfaceClassificationCharacteristic = 0; +int anomalyCharacteristic = 0; + +Adafruit_MPU6050 mpu; + +void AccelerationSensor::initSensor() +{ + Serial.println("setting up MPU6050..."); + + if (!mpu.begin(0x68, &Wire)) + { + Serial.println("MPU6050 Chip wurde nicht gefunden"); + delay(500); + return; + } + else + { + Serial.println("MPU6050 Found!"); + mpu.setAccelerometerRange(MPU6050_RANGE_8_G); + mpu.setGyroRange(MPU6050_RANGE_500_DEG); + mpu.setFilterBandwidth(MPU6050_BAND_21_HZ); + delay(100); + }; + + surfaceClassificationCharacteristic = BLEModule::createCharacteristic(surfaceClassificationUUID.c_str()); + anomalyCharacteristic = BLEModule::createCharacteristic(anomalyUUID.c_str()); +} + +float buffer[6] = {}; +size_t ix = 0; +float probAsphalt = 0.0; +float probCompact = 0.0; +float probPaving = 0.0; +float probSett = 0.0; +float probStanding = 0.0; +float anomaly = 0.0; + +float prevAccTime = millis(); + +bool AccelerationSensor::readSensorData() +{ + bool classified = false; + sensors_event_t a, g, temp; + + mpu.getEvent(&a, &g, &temp); + + buffer[0] = 1.0; + buffer[1] = 1.0; + buffer[2] = 1.0; + buffer[3] = 1.0; + buffer[4] = 1.0; + buffer[5] = 1.0; + + // Serial.println(millis() - prevAccTime); + prevAccTime = millis(); + + // one second inverval + if (EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE <= ix) + { + classified = true; + // Turn the raw buffer in a signal which we can the classify + signal_t signal; + int err = numpy::signal_from_buffer(buffer, EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE, &signal); + if (err != 0) + { + ei_printf("Failed to create signal from buffer (%d)\n", err); + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = {}; + return classified; + } + + // Run the classifier + ei_impulse_result_t result = {}; + + err = run_classifier(&signal, &result, false); + if (err != EI_IMPULSE_OK) + { + ei_printf("ERR: Failed to run classifier (%d)\n", err); + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = {}; + return classified; + } + + probAsphalt = result.classification[0].value; + probCompact = result.classification[1].value; + probPaving = result.classification[2].value; + probSett = result.classification[3].value; + probStanding = result.classification[4].value; + + anomaly = result.anomaly; + + if (sendBLE) + { + + notifyBLE(probAsphalt, probCompact, probPaving, probSett, probStanding, anomaly); + } + + ix = 0; + + buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = {}; + } + + if (measurementCallback) + { + measurementCallback({probAsphalt, probCompact, probPaving, probSett, probStanding}); + } + + return classified; +} + +void AccelerationSensor::notifyBLE(float probAsphalt, float probCompact, float probPaving, float probSett, float probStanding, float anomaly) +{ + BLEModule::writeBLE(surfaceClassificationUUID.c_str(), probAsphalt, probCompact, probPaving, probSett, probStanding); + BLEModule::writeBLE(anomalyUUID.c_str(), anomaly); +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.h new file mode 100644 index 0000000..ffb5335 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.h @@ -0,0 +1,18 @@ +#ifndef ACCELERATION_SENSOR_H +#define ACCELERATION_SENSOR_H + +#include "../BaseSensor.h" +#include + +class AccelerationSensor : public BaseSensor +{ +public: + AccelerationSensor(); + bool readSensorData() override; + +protected: + void initSensor() override; + void notifyBLE(float probAsphalt, float probCompact, float probPaving, float probSett, float probStanding, float anomaly); +}; + +#endif // ACCELERATION_SENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp new file mode 100644 index 0000000..c31719a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp @@ -0,0 +1,64 @@ +#include "BaseSensor.h" + +BaseSensor::BaseSensor(const char *taskName, uint32_t taskStackSize, uint32_t taskDelay) + : activeSubscription(false), sendBLE(false), taskStackSize(taskStackSize), taskDelay(taskDelay) {} + +static SemaphoreHandle_t i2c_mutex; + +void BaseSensor::begin() +{ + i2c_mutex = xSemaphoreCreateMutex(); + initSensor(); + delay(500); + // xTaskCreate(sensorTask, taskName, taskStackSize, this, 1, NULL); +} + +void BaseSensor::subscribe(std::function)> callback) +{ + this->measurementCallback = callback; +} + +void BaseSensor::startSubscription() +{ + if (this->taskHandle == NULL) + { + xTaskCreate(sensorTask, taskName, taskStackSize, this, 1, &this->taskHandle); + } + activeSubscription = true; +} + +void BaseSensor::stopSubscription() +{ + if (this->taskHandle != NULL) + { + vTaskDelete(this->taskHandle); + } + activeSubscription = false; +} + +void BaseSensor::startBLE() +{ + sendBLE = true; +} + +void BaseSensor::stopBLE() +{ + sendBLE = false; +} + +void BaseSensor::sensorTask(void *pvParameters) +{ + BaseSensor *sensor = static_cast(pvParameters); + while (true) + { + if (sensor->activeSubscription) + { + if (xSemaphoreTake(i2c_mutex, portMAX_DELAY) == pdTRUE) + { + sensor->readSensorData(); + xSemaphoreGive(i2c_mutex); + } + } + vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay)); + } +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.h new file mode 100644 index 0000000..bae48fe --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.h @@ -0,0 +1,36 @@ +#ifndef BASESENSOR_H +#define BASESENSOR_H + +#include +#include +#include +#include "../ble/BLEModule.h" + +class BaseSensor +{ +public: + BaseSensor(const char *taskName, uint32_t taskStackSize = 8192, uint32_t taskDelay = 1000); + + void begin(); + void subscribe(std::function)> callback); + void startSubscription(); + void stopSubscription(); + void startBLE(); + void stopBLE(); + +protected: + virtual void initSensor() = 0; + virtual bool readSensorData() = 0; + static void sensorTask(void *pvParameters); + bool activeSubscription; + bool sendBLE; + std::function)> measurementCallback; + +private: + const char *taskName; + uint32_t taskStackSize; + uint32_t taskDelay; + TaskHandle_t taskHandle; +}; + +#endif // BASESENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp new file mode 100644 index 0000000..522ef6a --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp @@ -0,0 +1,59 @@ +#include "BatterySensor.h" + +BatterySensor::BatterySensor() : BaseSensor("batterySensorTask", 2048, 10000) {} + +// 5b262dea-4565-4ea0-912f-1e453bda0ca7 +// String batteryUUID = "5B262DEA45654EA0912F1E453BDA0CA7"; +String batteryUUID = "2A19"; +int batteryCharacteristic = 0; + +Adafruit_MAX17048 maxlipo; + +// add more if needed + +void BatterySensor::initSensor() +{ + while (!maxlipo.begin()) + { + Serial.println(F("Couldnt find Adafruit MAX17048?\nMake sure a battery is plugged in!")); + delay(2000); + } + + // BLEModule::createService("180F"); + // batteryCharacteristic = BLEModule::createCharacteristic(batteryUUID.c_str()); + // add more if needed +} + +bool BatterySensor::readSensorData() +{ + // read sensor data + float batteryCharge = maxlipo.cellPercent(); + + if (measurementCallback) + { + measurementCallback({batteryCharge}); + } + + if (sendBLE) + { + notifyBLE(batteryCharge); + } + return false; +} + +void BatterySensor::notifyBLE(float batteryCharge) +{ + // BLEModule::writeBLE(batteryCharacteristic, batteryCharge); +} + +float BatterySensor::getBatteryCharge() +{ + float batteryCharge = maxlipo.cellPercent(); + return batteryCharge; +} + +float BatterySensor::getBatteryChargeRate() +{ + float batteryChargeRate = maxlipo.chargeRate(); + return batteryChargeRate; +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.h new file mode 100644 index 0000000..6d95533 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.h @@ -0,0 +1,22 @@ +#ifndef SAMPLE_SENSOR_H +#define SAMPLE_SENSOR_H + +#include "../BaseSensor.h" +#include + +// include necceary libraries + +class BatterySensor : public BaseSensor +{ +public: + BatterySensor(); + static float getBatteryCharge(); + static float getBatteryChargeRate(); + +protected: + void initSensor() override; + bool readSensorData() override; + void notifyBLE(float batteryCharge); // change this to match the data type of the sensor data +}; + +#endif // SAMPLE_SENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp new file mode 100644 index 0000000..a73c4c8 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp @@ -0,0 +1,223 @@ +#include "DistanceSensor.h" + +#include "model_data.h" +#include +#include + +#include + +#include +// #include +// #include "tensorflow/lite/micro/kernels/micro_ops.h" +// #include "tensorflow/lite/micro/micro_interpreter.h" +// #include "tensorflow/lite/micro/micro_mutable_op_resolver.h" +// #include "tensorflow/lite/micro/all_ops_resolver.h" +// #include "tensorflow/lite/schema/schema_generated.h" +// #include +#include "edge-impulse-sdk/tensorflow/lite/micro/kernels/micro_ops.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_interpreter.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/micro_mutable_op_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/micro/all_ops_resolver.h" +#include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" +#include + +DistanceSensor::DistanceSensor() : BaseSensor("distanceTask", 8192, 0) {} + +// String distanceUUID = "B3491B60C0F34306A30D49C91F37A62B"; +String distanceUUID = "b3491b60-c0f3-4306-a30d-49c91f37a62b"; +int distanceCharacteristic = 0; + +// String overtakingUUID = "FC01C6882C444965AE18373AF9FED18D"; +String overtakingUUID = "fc01c688-2c44-4965-ae18-373af9fed18d"; +int overtakingCharacteristic = 0; + +VL53L8CX sensor_vl53l8cx_top(&Wire, -1, -1); +const int kChannelNumber = 64; +const int kFrameNumber = 20; +const tflite::Model *model = nullptr; +tflite::MicroInterpreter *interpreter = nullptr; +TfLiteTensor *model_input = nullptr; +int input_length; +// Create an area of memory to use for input, output, and intermediate arrays. +// The size of this will depend on the model you're using, and may need to be +// determined by experimentation. +constexpr int kTensorArenaSize = 14 * 1024 + 1008; +uint8_t tensor_arena[kTensorArenaSize]; + +// A buffer holding the last 20 sets of 8x8 pixels +const int RING_BUFFER_SIZE = 1280; +float save_data[RING_BUFFER_SIZE] = {0.0}; +// Most recent position in the save_data buffer +int begin_index = 0; +// True if there is not yet enough data to run inference +bool pending_initial_data = true; + +long prevDistanceTime = millis(); + +void DistanceSensor::initSensor() +{ + // ------------------------------ setup VL53L8CX ------------------------------ + Serial.println("setting up VL53L8CX..."); + Wire.begin(); + // Wire.setClock(1000000); // Sensor has max I2C freq of 1MHz + uint8_t status = sensor_vl53l8cx_top.begin(); + status = sensor_vl53l8cx_top.init(); + sensor_vl53l8cx_top.set_ranging_frequency_hz(15); + sensor_vl53l8cx_top.set_resolution(VL53L8CX_RESOLUTION_8X8); + status = sensor_vl53l8cx_top.start_ranging(); + // -------------------------- setup tensorflow model -------------------------- + Serial.println("setting up tensorflow..."); + model = tflite::GetModel(g_model_data); + if (model->version() != TFLITE_SCHEMA_VERSION) + { + Serial.printf("Model provided is schema version %d not equal " + "to supported version %d.", + model->version(), TFLITE_SCHEMA_VERSION); + return; + } + // static tflite::MicroErrorReporter tflErrorReporter; + // This imports all operations, which is more intensive, than just importing the ones we need. + // If we ever run out of storage with a model, we can check here to free some space + static tflite::AllOpsResolver resolver; + // Build an interpreter to run the model with. + static tflite::MicroInterpreter static_interpreter( + (tflite::Model*)(model), (tflite::MicroOpResolver&)(resolver), (uint8_t *)(tensor_arena), (size_t)(kTensorArenaSize)); + // , (tflite::MicroErrorReporter*)(&tflErrorReporter)); + interpreter = &static_interpreter; + // Allocate memory from the tensor_arena for the model's tensors. + interpreter->AllocateTensors(true); + // Obtain pointer to the model's input tensor. + model_input = interpreter->input(0); + if ((model_input->dims->size != 3) || (model_input->dims->data[0] != 1) || + (model_input->dims->data[1] != kFrameNumber) || + (model_input->dims->data[2] != kChannelNumber) || + (model_input->type != kTfLiteFloat32)) + { + Serial.println(model_input->dims->size); + Serial.println(model_input->dims->data[0]); + Serial.println(model_input->dims->data[1]); + Serial.println(model_input->dims->data[2]); + Serial.println(model_input->type); + Serial.println("Bad input tensor parameters in model"); + return; + } + input_length = model_input->bytes / sizeof(float); + // ----------------------------- setup complete ----------------------------- + Serial.println("setup complete"); + + distanceCharacteristic = BLEModule::createCharacteristic(distanceUUID.c_str()); + overtakingCharacteristic = BLEModule::createCharacteristic(overtakingUUID.c_str()); + Wire.setClock(100000); // Sensor has max I2C freq of 1MHz +} + +bool DistanceSensor::readSensorData() +{ + Wire.setClock(1000000); // Sensor has max I2C freq of 1MHz + + VL53L8CX_ResultsData Results; + uint8_t NewDataReady = 0; + uint8_t status = sensor_vl53l8cx_top.check_data_ready(&NewDataReady); + + float distance = -1.0; + + if ((!status) && (NewDataReady != 0)) + { + // Serial.println("data ready"); + Serial.println(millis()-prevDistanceTime); + prevDistanceTime = millis(); + sensor_vl53l8cx_top.get_ranging_data(&Results); + float overtakingPredictionPercentage = -1.0; + float oldVl53l8cxMin = -1.0; + float min = 10000.0; + for (int j = 0; j < VL53L8CX_RESOLUTION_8X8; j += 8) + { + for (int l = 0; l < VL53L8CX_NB_TARGET_PER_ZONE; l++) + { + for (int k = (8 - 1); k >= 0; k--) + { + if ((float)(&Results)->target_status[(VL53L8CX_NB_TARGET_PER_ZONE * (j + k)) + l] != 255) + { + if ((float)(&Results)->distance_mm[(VL53L8CX_NB_TARGET_PER_ZONE * (j + k)) + l] > 2000.0) + { + save_data[begin_index++] = 0.0; + } + else + { + save_data[begin_index++] = (float)(&Results)->distance_mm[(VL53L8CX_NB_TARGET_PER_ZONE * (j + k)) + l]; + } + float distance = ((&Results)->distance_mm[(VL53L8CX_NB_TARGET_PER_ZONE * (j + k)) + l]) / 10; + if (min > distance) + { + min = distance; + } + } + else + { + save_data[begin_index++] = 0.0; + } + } + } + } + oldVl53l8cxMin = (min == 10000.0) ? 0.0 : min; + + // If we reached the end of the circle buffer, reset + if (begin_index >= (RING_BUFFER_SIZE)) + { + begin_index = 0; + // Check if we are ready for prediction or still pending more initial data + if (pending_initial_data) + { + pending_initial_data = false; + } + } + if (!pending_initial_data) + { + for (int i = 0; i < input_length; ++i) + { + int ring_array_index = begin_index + i - input_length; + if (ring_array_index < 0) + { + ring_array_index += (RING_BUFFER_SIZE); + } + // normalize + model_input->data.f[i] = save_data[ring_array_index] / 2000.0; + } + // Run inference, and report any error. + TfLiteStatus invoke_status = interpreter->Invoke(); + if (invoke_status == kTfLiteOk) + { + const float *prediction_scores = interpreter->output(0)->data.f; + overtakingPredictionPercentage = prediction_scores[0]; + Serial.print(overtakingPredictionPercentage); + Serial.print(" "); + } + } + + float distance = oldVl53l8cxMin; + + Wire.setClock(100000); // Sensor has max I2C freq of 1MHz + + if (measurementCallback) + { + measurementCallback({distance, overtakingPredictionPercentage}); + } + + if (sendBLE) + { + notifyBLE(distance, overtakingPredictionPercentage); + } + } + if ((millis() - prevDistanceTime) < 65) + { + vTaskDelay(pdMS_TO_TICKS(65 - (millis() - prevDistanceTime))); + } + // Serial.print("distance: "); + // Serial.println(millis() - prevDistanceTime); + return false; +} + +void DistanceSensor::notifyBLE(float distance, float overtakingPredictionPercentage) +{ + BLEModule::writeBLE(distanceUUID.c_str(), distance); + BLEModule::writeBLE(overtakingUUID.c_str(), overtakingPredictionPercentage); +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.h new file mode 100644 index 0000000..ab4a4ec --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.h @@ -0,0 +1,19 @@ +#ifndef DISTANCESENSOR_H +#define DISTANCESENSOR_H + +#include "../BaseSensor.h" +#include +#include + +class DistanceSensor : public BaseSensor +{ +public: + DistanceSensor(); + bool readSensorData() override; + +protected: + void initSensor() override; + void notifyBLE(float distance, float overtakingPredictionPercentage); +}; + +#endif // DISTANCESENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/model_data.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/model_data.h new file mode 100644 index 0000000..d1fa6b6 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/model_data.h @@ -0,0 +1,553 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This is a standard TensorFlow Lite model file that has been converted into a +// C data array, so it can be easily compiled into a binary for devices that +// don't have a file system. It was created using the command: +// xxd -i magic_wand_model.tflite > magic_wand_model_data.cc + +#ifndef TENSORFLOW_LITE_MICRO_MODEL_DATA_H_ +#define TENSORFLOW_LITE_MICRO_MODEL_DATA_H_ + +extern const unsigned char g_model_data[] PROGMEM = { + 0x1c, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x14, 0x00, 0x20, 0x00, + 0x1c, 0x00, 0x18, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, + 0x90, 0x00, 0x00, 0x00, 0xe8, 0x00, 0x00, 0x00, 0x08, 0x0c, 0x00, 0x00, + 0x18, 0x0c, 0x00, 0x00, 0xdc, 0x17, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7e, 0xf2, 0xff, 0xff, + 0x0c, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, + 0x0f, 0x00, 0x00, 0x00, 0x73, 0x65, 0x72, 0x76, 0x69, 0x6e, 0x67, 0x5f, + 0x64, 0x65, 0x66, 0x61, 0x75, 0x6c, 0x74, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x8c, 0xff, 0xff, 0xff, 0x14, 0x00, 0x00, 0x00, + 0x04, 0x00, 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0x00, 0x2d, 0x0c, 0x00, 0x0c, 0x00, 0x0b, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x4d, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x4d}; +extern const int model_tflite_len PROGMEM = 6304; + +#endif // TENSORFLOW_LITE_MICRO_MODEL_DATA_H_ \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp new file mode 100644 index 0000000..483e159 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp @@ -0,0 +1,92 @@ +#include "DustSensor.h" + +DustSensor::DustSensor() : BaseSensor("DustSensorTask", 2048, 1000) {} + +String dustUUID = "7E14E07084EA489FB45AE1317364B979"; +int dustCharacteristic = 0; + +// add more if needed + +void DustSensor::initSensor() +{ + int16_t ret; + uint8_t auto_clean_days = 4; + uint32_t auto_clean; + + sensirion_i2c_init(); + + while (sps30_probe() != 0) + { + Serial.print("SPS sensor probing failed\n"); + delay(500); + } + + Serial.print("SPS sensor probing successful\n"); + + ret = sps30_set_fan_auto_cleaning_interval_days(auto_clean_days); + if (ret) + { + Serial.print("error setting the auto-clean interval: "); + Serial.println(ret); + } + + ret = sps30_start_measurement(); + if (ret < 0) + { + Serial.print("error starting measurement\n"); + } + + Serial.print("measurements started\n"); + + // dustCharacteristic = BLEModule::createCharacteristic(dustUUID.c_str()); +} + +bool DustSensor::readSensorData() +{ + // Wire.setClock(100000); // Sensor has max I2C freq of 1MHz + struct sps30_measurement m; + char serial[SPS30_MAX_SERIAL_LEN]; + uint16_t data_ready; + int16_t ret; + + // retry 5 times until the sensor has data ready + int retries = 5; + int retryCount = 0; + ret = sps30_read_data_ready(&data_ready); + if (ret < 0) + { + Serial.print("error reading data-ready flag: "); + Serial.println(ret); + } + else if (!data_ready) + Serial.print("data not ready, no new measurement available\n"); + else { + ret = sps30_read_measurement(&m); + if (ret < 0) + { + Serial.print("error reading measurement\n"); + } + else + { + float pm1 = m.mc_1p0; + float pm2_5 = m.mc_2p5; + float pm4 = m.mc_4p0; + float pm10 = m.mc_10p0; + if (measurementCallback) + { + measurementCallback({pm1, pm2_5, pm4, pm10}); + } + + if (sendBLE) + { + notifyBLE(pm1, pm2_5, pm4, pm10); + } + } + } + return false; +} + +void DustSensor::notifyBLE(float pm1, float pm2_5, float pm4, float pm10) +{ + // BLEModule::writeBLE(dustCharacteristic, pm1, pm2_5, pm4, pm10); +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h new file mode 100644 index 0000000..177f401 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h @@ -0,0 +1,21 @@ +#ifndef DUST_SENSOR_H +#define DUST_SENSOR_H + +#include "../BaseSensor.h" +#include +// #include + +// include necceary libraries + +class DustSensor : public BaseSensor +{ +public: + DustSensor(); + bool readSensorData() override; + +protected: + void initSensor() override; + void notifyBLE(float pm1, float pm2_5, float pm4, float pm10); +}; + +#endif // DUST_SENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp new file mode 100644 index 0000000..7772cdd --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp @@ -0,0 +1,38 @@ +#include "SampleSensor.h" + +SampleSensor::SampleSensor() : BaseSensor("sampleSensorTask", 2048, 1000) {} + +String sampleUUID = "00000000000000000"; +int sampleCharacteristic = 0; + +// add more if needed + +void SampleSensor::initSensor() +{ + // init sensor + + // sampleCharacteristic = BLEModule::createCharacteristic(sampleUUID.c_str()); + // add more if needed +} + +bool SampleSensor::readSensorData() +{ + float sampleValue = 0.0; + // read sensor data + + if (measurementCallback) + { + measurementCallback({sampleValue}); + } + + if (sendBLE) + { + notifyBLE(sampleValue); + } + return false; +} + +void SampleSensor::notifyBLE(float sampleValue) +{ + // BLEModule::writeBLE(sampleCharacteristic, sampleValue); +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h new file mode 100644 index 0000000..c46b53b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h @@ -0,0 +1,19 @@ +#ifndef SAMPLE_SENSOR_H +#define SAMPLE_SENSOR_H + +#include "../BaseSensor.h" + +// include necceary libraries + +class SampleSensor : public BaseSensor +{ +public: + SampleSensor(); + +protected: + void initSensor() override; + bool readSensorData() override; + void notifyBLE(float sampleValue); // change this to match the data type of the sensor data +}; + +#endif // SAMPLE_SENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp new file mode 100644 index 0000000..562ff86 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp @@ -0,0 +1,53 @@ +#include "TempHumiditySensor.h" + +TempHumiditySensor::TempHumiditySensor() : BaseSensor("temperatureHumidityTask", 2048, 1000) {} + +String tempUUID = "2CDF217435BEFDC44CA26FD173F8B3A8"; +String humUUID = "772DF7EC8CDC4EA986AF410ABE0BA257"; + +int temperatureCharacteristic = 0; +int humidityCharacteristic = 0; + +Adafruit_HDC1000 hdc; + +void TempHumiditySensor::initSensor() +{ + if (!hdc.begin()) + { + Serial.println("Couldn't find HDC1080 sensor!"); + while (1) + ; + } + + // temperatureCharacteristic = BLEModule::createCharacteristic(tempUUID.c_str()); + // humidityCharacteristic = BLEModule::createCharacteristic(humUUID.c_str()); +} + +bool TempHumiditySensor::readSensorData() +{ + float temperature = hdc.readTemperature(); + float humidity = hdc.readHumidity(); + + if (temperature < -37 || humidity < 2) + { + Serial.println("Invalid temperature or humidity value"); + return false; + } + + if (measurementCallback) + { + measurementCallback({temperature, humidity}); + } + + if (sendBLE) + { + notifyBLE(temperature, humidity); + } + return false; +} + +void TempHumiditySensor::notifyBLE(float temoperature, float humidity) +{ + // BLEModule::writeBLE(temperatureCharacteristic, temoperature); + // BLEModule::writeBLE(humidityCharacteristic, humidity); +} \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.h new file mode 100644 index 0000000..46cf4bb --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.h @@ -0,0 +1,18 @@ +#ifndef TEMP_HUMIDITY_SENSOR_H +#define TEMP_HUMIDITY_SENSOR_H + +#include "../BaseSensor.h" +#include "Adafruit_HDC1000.h" + +class TempHumiditySensor : public BaseSensor +{ +public: + TempHumiditySensor(); + bool readSensorData() override; + +protected: + void initSensor() override; + void notifyBLE(float temperature, float humidity); +}; + +#endif // TEMP_HUMIDITY_SENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/test/README b/sensebox-bike-atrai-v2-esp32s3/test/README new file mode 100644 index 0000000..9b1e87b --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PlatformIO Test Runner and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PlatformIO Unit Testing: +- https://docs.platformio.org/en/latest/advanced/unit-testing/index.html From 8003e28f56675682518e3cee224bec5ec8e96920 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Fri, 25 Oct 2024 15:44:50 +0200 Subject: [PATCH 02/18] add description --- sensebox-bike-atrai-v2-esp32s3/README.md | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 sensebox-bike-atrai-v2-esp32s3/README.md diff --git a/sensebox-bike-atrai-v2-esp32s3/README.md b/sensebox-bike-atrai-v2-esp32s3/README.md new file mode 100644 index 0000000..c44a032 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/README.md @@ -0,0 +1,32 @@ +# Results of the performance tests + +## Test 1: Distance, Overtaking Prediction +Threading done without mutex + +**senseBox MCUS2** +- linear: 83ms +- threading: 230ms + +**Adafruit Feather ESP32S3** +- linear: 65ms +- threading: 116ms + +## Test 2: Distance, Overtaking Prediction, Surface Classification, BLE +Threading with mutex + +**senseBox MCUS2** +- linear: 86ms +- threading: 184ms + +**Adafruit Feather ESP32S3** +- linear: 68ms +- threading: 123ms + +# Some lessons learnt +- I had to rename the edge impulse library (the previous name was too long) +- ESP32 BLE + - expects different format for characteristic/service ids + - no need to actively regularly poll, it does that on its own somehow + +# Open Issues +- How to set and get BLE device id like its done for senseBox? \ No newline at end of file From d7a5f5547bd73977497ab38cc96d9c797d73ead2 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Fri, 25 Oct 2024 15:47:01 +0200 Subject: [PATCH 03/18] s3 --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index a8b4167..877638f 100644 --- a/README.md +++ b/README.md @@ -11,7 +11,7 @@ A mobile measurement station that measures temperature, relative humidity, parti | [senseBox:bike](senseBox-bike) | senseBox MCU S2 | BLE | | Used for the [senseBox:bike to buy](https://sensebox.kaufen/product/sensebox-bike) | | [senseBox:bike Atrai Bike](senseBox-bike-atrai) | senseBox MCU S2 | BLE | | Initial draft for [Atrai Bike](https://atrai.bike/) project | | [senseBox:bike Atrai Bike v2](senseBox-bike-atrai-v2) | senseBox MCU S2 | BLE | ✅ | AI powered version for [Atrai Bike](https://atrai.bike/) project | -| [senseBox:bike Atrai Bike v2 ESP32S2](senseBox-bike-atrai-v2-esp32s2) | Adafruit Feather ESP32S3 (with 2MB PSRAM) | BLE | ✅ | Testing the AI powered version for [Atrai Bike](https://atrai.bike/) project with an ESP32S3 chip | +| [senseBox:bike Atrai Bike v2 ESP32S2](senseBox-bike-atrai-v2-esp32s3) | Adafruit Feather ESP32S3 (with 2MB PSRAM) | BLE | ✅ | Testing the AI powered version for [Atrai Bike](https://atrai.bike/) project with an ESP32S3 chip | ### License From 5de71a0e6ae1e108248291ea6bf4d9d39f2b1775 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Fri, 25 Oct 2024 15:48:42 +0200 Subject: [PATCH 04/18] B --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 877638f..39854af 100644 --- a/README.md +++ b/README.md @@ -11,7 +11,7 @@ A mobile measurement station that measures temperature, relative humidity, parti | [senseBox:bike](senseBox-bike) | senseBox MCU S2 | BLE | | Used for the [senseBox:bike to buy](https://sensebox.kaufen/product/sensebox-bike) | | [senseBox:bike Atrai Bike](senseBox-bike-atrai) | senseBox MCU S2 | BLE | | Initial draft for [Atrai Bike](https://atrai.bike/) project | | [senseBox:bike Atrai Bike v2](senseBox-bike-atrai-v2) | senseBox MCU S2 | BLE | ✅ | AI powered version for [Atrai Bike](https://atrai.bike/) project | -| [senseBox:bike Atrai Bike v2 ESP32S2](senseBox-bike-atrai-v2-esp32s3) | Adafruit Feather ESP32S3 (with 2MB PSRAM) | BLE | ✅ | Testing the AI powered version for [Atrai Bike](https://atrai.bike/) project with an ESP32S3 chip | +| [senseBox:bike Atrai Bike v2 ESP32S2](sensebox-bike-atrai-v2-esp32s3) | Adafruit Feather ESP32S3 (with 2MB PSRAM) | BLE | ✅ | Testing the AI powered version for [Atrai Bike](https://atrai.bike/) project with an ESP32S3 chip | ### License From 06ce8be1e2eb4fed7b5d589cd62db60a56107761 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Tue, 5 Nov 2024 17:34:04 +0100 Subject: [PATCH 05/18] ble notify --- sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp index 504b575..923f1e7 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp @@ -50,7 +50,7 @@ int BLEModule::createService(const char *uuid) int BLEModule::createCharacteristic(const char *uuid) { - BLECharacteristic *pCharacteristic = pService->createCharacteristic(uuid, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE); + BLECharacteristic *pCharacteristic = pService->createCharacteristic(uuid, BLECharacteristic::PROPERTY_READ | BLECharacteristic::PROPERTY_WRITE | BLECharacteristic::PROPERTY_INDICATE| BLECharacteristic::PROPERTY_NOTIFY); return 1; } @@ -58,7 +58,7 @@ bool BLEModule::writeBLE(const char * characteristicId, float value) { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); pCharacteristic->setValue(value); - // pCharacteristic->notify(); ?? + pCharacteristic->notify(); return true; } From ad389e3f7457a013158d9077668bd950d34e68b2 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Mon, 11 Nov 2024 16:21:38 +0100 Subject: [PATCH 06/18] BLE MacAddress and display --- sensebox-bike-atrai-v2-esp32s3/partition.csv | 6 +++++ sensebox-bike-atrai-v2-esp32s3/platformio.ini | 1 + .../src/ble/BLEModule.cpp | 23 +++++++++++++--- .../src/ble/BLEModule.h | 2 ++ .../src/display/Display.cpp | 18 +++---------- .../src/display/Display.h | 2 +- sensebox-bike-atrai-v2-esp32s3/src/main.cpp | 27 +++++++++++++------ 7 files changed, 52 insertions(+), 27 deletions(-) create mode 100644 sensebox-bike-atrai-v2-esp32s3/partition.csv diff --git a/sensebox-bike-atrai-v2-esp32s3/partition.csv b/sensebox-bike-atrai-v2-esp32s3/partition.csv new file mode 100644 index 0000000..1d00925 --- /dev/null +++ b/sensebox-bike-atrai-v2-esp32s3/partition.csv @@ -0,0 +1,6 @@ +# Name, Type, SubType, Offset, Size, Flags +nvs, data, nvs, 0x9000, 0x5000, +otadata, data, ota, 0xe000, 0x2000, +app0, app, ota_0, 0x10000, 0x300000, +spiffs, data, spiffs, 0x310000,0xE0000, +coredump, data, coredump,0x3F0000,0x10000, diff --git a/sensebox-bike-atrai-v2-esp32s3/platformio.ini b/sensebox-bike-atrai-v2-esp32s3/platformio.ini index e2aa263..d609b8c 100644 --- a/sensebox-bike-atrai-v2-esp32s3/platformio.ini +++ b/sensebox-bike-atrai-v2-esp32s3/platformio.ini @@ -11,6 +11,7 @@ [env:adafruit_feather_esp32s3] platform = espressif32 board = adafruit_feather_esp32s3 +board_build.partitions = partition.csv platform_packages = platformio/framework-arduinoespressif32 @ https://github.com/espressif/arduino-esp32.git#2.0.17 framework = arduino lib_deps = diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp index 923f1e7..507f86b 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp @@ -4,6 +4,7 @@ bool isConnectedVar = false; BLEServer *pServer; BLEService *pService; +char macString[32]; // Enough space for the MAC string BLEModule::BLEModule() { @@ -12,7 +13,14 @@ BLEModule::BLEModule() bool BLEModule::begin() { - BLEDevice::init("senseBox-BLE[xxxyyy]"); // not sure how to adjust the id + uint8_t baseMac[6]; + esp_read_mac(baseMac, ESP_MAC_BT); + snprintf(macString, sizeof(macString), "%02X:%02X:%02X:%02X:%02X:%02X", + baseMac[0], baseMac[1], baseMac[2], baseMac[3], baseMac[4], baseMac[5]); + char bleName[64]; + snprintf(bleName, sizeof(bleName), "senseBox-BLE[%s]", macString); + + BLEDevice::init(bleName); pServer = BLEDevice::createServer(); return true; @@ -30,9 +38,11 @@ bool BLEModule::isConnected() const char **BLEModule::getBLEConnectionString() { - String bleId = "[xxxyyy]"; - String bleIdBegin = bleId.substring(0, bleId.length() / 2); - String bleIdEnd = bleId.substring(bleId.length() / 2); + char bleId[34]; + snprintf(bleId, sizeof(bleId), "[%s]", macString); + std::string bleIdStr = bleId; + std::string bleIdBegin = bleIdStr.substr(0, bleIdStr.length() / 2); + std::string bleIdEnd = bleIdStr.substr(bleIdStr.length() / 2); const char *MESSAGE_CONFIGURE_WIFI[] = { "senseBox", "bike", @@ -113,3 +123,8 @@ void BLEModule::bleStartPoll(const char *uuid) pAdvertising->setMinPreferred(0x12); BLEDevice::startAdvertising(); } + +const char *BLEModule::getMacAddress() +{ + return macString; // Enough space for the MAC string; +} diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h index 63b5f81..bedc618 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h @@ -40,6 +40,8 @@ class BLEModule static bool isConnected(); + const char *getMacAddress(); + private: // BLEService* service; String bleName; diff --git a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp index a1ddd1c..1a64e56 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp @@ -1,13 +1,13 @@ #include "Display.h" #include -// #include +#include #include #include #include #include #include "bicycle_loading_bitmap.h" -// Adafruit_SSD1306 SBDisplay::display(SCREEN_WIDTH, SCREEN_HEIGHT, &Wire, OLED_RESET); +Adafruit_SSD1306 SBDisplay::display(SCREEN_WIDTH, SCREEN_HEIGHT, &Wire, OLED_RESET); QRCode SBDisplay::qrcode; float batteryCharge = 0; @@ -117,24 +117,14 @@ void SBDisplay::showSystemStatus() display.display(); } -void SBDisplay::showConnectionScreen() +void SBDisplay::showConnectionScreen(String name, const char *message[]) { if (isBicycleAnimationShowing) { isBicycleAnimationShowing = false; } - // String bleIdBrackets = "[" + bleId + "]"; - // String name = "senseBox:bike " + bleIdBrackets; - // String bleIdBegin = bleIdBrackets.substring(0, bleIdBrackets.length() / 2); - // String bleIdEnd = bleIdBrackets.substring(bleIdBrackets.length() / 2); - // const char *message[] = { - // "senseBox", - // "bike", - // bleIdBegin.c_str(), - // bleIdEnd.c_str()}; - - // drawQrCode(name.c_str(), message); + drawQrCode(name.c_str(), message); drawBattery(0, 0, 16, 4); display.display(); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.h b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.h index aa8b11e..48e8b0b 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.h @@ -21,7 +21,7 @@ class SBDisplay public: static void begin(); static void showSystemStatus(); - static void showConnectionScreen(); + static void showConnectionScreen(String name, const char *message[]); static void drawQrCode(const char *qrStr, const char *lines[]); static void showLoading(String msg, float val); static void drawProgressbar(int x, int y, int width, int height, int progress); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp index db93d53..f359413 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp @@ -4,7 +4,7 @@ #include "sensors/DistanceSensor/DistanceSensor.h" #include "sensors/AccelerationSensor/AccelerationSensor.h" #include "sensors/BatterySensor/BatterySensor.h" -// #include "display/Display.h" +#include "display/Display.h" #include "ble/BLEModule.h" // #include "led/LED.h" @@ -22,7 +22,7 @@ BaseSensor *sensors[] = { // &batterySensor }; -// SBDisplay display; +SBDisplay display; BLEModule bleModule; // LED led(1, 1); @@ -39,19 +39,19 @@ void setup() // led.startRainbow(); - // SBDisplay::begin(); + SBDisplay::begin(); // pinMode(IO_ENABLE, OUTPUT); // digitalWrite(IO_ENABLE, LOW); - // SBDisplay::showLoading("Setup BLE...", 0.2); + SBDisplay::showLoading("Setup BLE...", 0.2); bleModule.begin(); // batterySensor.begin(); bleModule.createService("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); - // SBDisplay::showLoading("Setup Sensors...", 0.4); + SBDisplay::showLoading("Setup Sensors...", 0.4); for (BaseSensor *sensor : sensors) { sensor->begin(); @@ -62,14 +62,14 @@ void setup() // delay(100); // digitalWrite(3, HIGH); - // SBDisplay::showLoading("Start measurements...", 0.8); + SBDisplay::showLoading("Start measurements...", 0.8); // Start sensor measurements for (BaseSensor *sensor : sensors) { sensor->startSubscription(); } - // SBDisplay::showLoading("Enable BLE...", 1); + SBDisplay::showLoading("Enable BLE...", 1); // Start BLE advertising for (BaseSensor *sensor : sensors) @@ -81,7 +81,18 @@ void setup() // led.stopRainbow(); - // display.showConnectionScreen(); + const char* macString = bleModule.getMacAddress(); + String bleId = "[" + String(macString) + "]"; + String bleIdBegin = bleId.substring(0, bleId.length() / 2); + String bleIdEnd = bleId.substring(bleId.length() / 2); + String name = "senseBox:bike " + bleId; + const char *message[] = { + "senseBox", + "bike", + bleIdBegin.c_str(), + bleIdEnd.c_str()}; + + display.showConnectionScreen(name, message); bleModule.bleStartPoll("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); } From c6728872570583ae589e66752c192d0cac4e8ecf Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Mon, 11 Nov 2024 16:39:43 +0100 Subject: [PATCH 07/18] update readme --- sensebox-bike-atrai-v2-esp32s3/README.md | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/README.md b/sensebox-bike-atrai-v2-esp32s3/README.md index c44a032..90a7d26 100644 --- a/sensebox-bike-atrai-v2-esp32s3/README.md +++ b/sensebox-bike-atrai-v2-esp32s3/README.md @@ -22,11 +22,10 @@ Threading with mutex - linear: 68ms - threading: 123ms -# Some lessons learnt +# Some notes - I had to rename the edge impulse library (the previous name was too long) - ESP32 BLE - expects different format for characteristic/service ids - no need to actively regularly poll, it does that on its own somehow - -# Open Issues -- How to set and get BLE device id like its done for senseBox? \ No newline at end of file + - I used the BLE-MacAddress for the name (because Im not sure where to get the MCUId from, like it was done with the senseBox-ble library) +- I had to adjust the partitions because flash was flowing over \ No newline at end of file From e2b6d2c83a00087df86ae785b6f1e6c29a61a736 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Mon, 18 Nov 2024 15:29:51 +0100 Subject: [PATCH 08/18] add dust temp humid --- sensebox-bike-atrai-v2-esp32s3/src/main.cpp | 15 ++++++++------- .../src/sensors/DustSensor/DustSensor.cpp | 8 ++++---- .../TempHumiditySensor/TempHumiditySensor.cpp | 16 ++++++++-------- 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp index f359413..31802e0 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp @@ -8,15 +8,15 @@ #include "ble/BLEModule.h" // #include "led/LED.h" -// DustSensor dustSensor; -// TempHumiditySensor tempHumiditySensor; +DustSensor dustSensor; +TempHumiditySensor tempHumiditySensor; DistanceSensor distanceSensor; AccelerationSensor accelerationSensor; // BatterySensor batterySensor; BaseSensor *sensors[] = { - // &dustSensor, - // &tempHumiditySensor, + &dustSensor, + &tempHumiditySensor, &distanceSensor, &accelerationSensor, // &batterySensor @@ -57,7 +57,7 @@ void setup() sensor->begin(); } - // SBDisplay::showLoading("Ventilation...", 0.6); + SBDisplay::showLoading("Ventilation...", 0.6); // pinMode(3, OUTPUT); // delay(100); // digitalWrite(3, HIGH); @@ -77,7 +77,7 @@ void setup() sensor->startBLE(); } - // display.readBleId(); + display.readBleId(); // led.stopRainbow(); @@ -90,7 +90,8 @@ void setup() "senseBox", "bike", bleIdBegin.c_str(), - bleIdEnd.c_str()}; + bleIdEnd.c_str() + }; display.showConnectionScreen(name, message); bleModule.bleStartPoll("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp index 483e159..2c9fa7e 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp @@ -1,8 +1,8 @@ #include "DustSensor.h" -DustSensor::DustSensor() : BaseSensor("DustSensorTask", 2048, 1000) {} +DustSensor::DustSensor() : BaseSensor("DustSensorTask", 8192, 1000) {} -String dustUUID = "7E14E07084EA489FB45AE1317364B979"; +String dustUUID = "7e14e070-84ea-489f-b45a-e1317364b979"; int dustCharacteristic = 0; // add more if needed @@ -38,7 +38,7 @@ void DustSensor::initSensor() Serial.print("measurements started\n"); - // dustCharacteristic = BLEModule::createCharacteristic(dustUUID.c_str()); + dustCharacteristic = BLEModule::createCharacteristic(dustUUID.c_str()); } bool DustSensor::readSensorData() @@ -88,5 +88,5 @@ bool DustSensor::readSensorData() void DustSensor::notifyBLE(float pm1, float pm2_5, float pm4, float pm10) { - // BLEModule::writeBLE(dustCharacteristic, pm1, pm2_5, pm4, pm10); + BLEModule::writeBLE(dustUUID.c_str(), pm1, pm2_5, pm4, pm10); } \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp index 562ff86..4195be2 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp @@ -1,9 +1,9 @@ #include "TempHumiditySensor.h" -TempHumiditySensor::TempHumiditySensor() : BaseSensor("temperatureHumidityTask", 2048, 1000) {} +TempHumiditySensor::TempHumiditySensor() : BaseSensor("temperatureHumidityTask", 8192, 0) {} -String tempUUID = "2CDF217435BEFDC44CA26FD173F8B3A8"; -String humUUID = "772DF7EC8CDC4EA986AF410ABE0BA257"; +String tempUUID = "2cdf2174-35be-fdc4-4Ca2-6fd173f8b3a8"; +String humUUID = "772df7ec-8cdc-4ea9-86af-410abe0ba257"; int temperatureCharacteristic = 0; int humidityCharacteristic = 0; @@ -19,8 +19,8 @@ void TempHumiditySensor::initSensor() ; } - // temperatureCharacteristic = BLEModule::createCharacteristic(tempUUID.c_str()); - // humidityCharacteristic = BLEModule::createCharacteristic(humUUID.c_str()); + temperatureCharacteristic = BLEModule::createCharacteristic(tempUUID.c_str()); + humidityCharacteristic = BLEModule::createCharacteristic(humUUID.c_str()); } bool TempHumiditySensor::readSensorData() @@ -46,8 +46,8 @@ bool TempHumiditySensor::readSensorData() return false; } -void TempHumiditySensor::notifyBLE(float temoperature, float humidity) +void TempHumiditySensor::notifyBLE(float temperature, float humidity) { - // BLEModule::writeBLE(temperatureCharacteristic, temoperature); - // BLEModule::writeBLE(humidityCharacteristic, humidity); + BLEModule::writeBLE(tempUUID.c_str(), temperature); + BLEModule::writeBLE(humUUID.c_str(), humidity); } \ No newline at end of file From 90549723a6afdb52cb67bfbc01835cd48ccc5001 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Tue, 19 Nov 2024 11:47:57 +0100 Subject: [PATCH 09/18] battery sensor --- .../src/display/Display.cpp | 2 +- sensebox-bike-atrai-v2-esp32s3/src/main.cpp | 6 ++---- .../src/sensors/BatterySensor/BatterySensor.cpp | 11 ++++------- .../src/sensors/BatterySensor/BatterySensor.h | 2 +- .../src/sensors/DustSensor/DustSensor.h | 2 +- .../src/sensors/SampleSensor/SampleSensor.h | 2 +- 6 files changed, 10 insertions(+), 15 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp index 1a64e56..004050a 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/display/Display.cpp @@ -112,7 +112,7 @@ void SBDisplay::showSystemStatus() display.print(batteryCharge, 1); display.println(" %"); - drawBattery(0, 0, 16, 4); + // drawBattery(0, 0, 16, 4); display.display(); } diff --git a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp index 31802e0..bedd412 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp @@ -12,14 +12,14 @@ DustSensor dustSensor; TempHumiditySensor tempHumiditySensor; DistanceSensor distanceSensor; AccelerationSensor accelerationSensor; -// BatterySensor batterySensor; +BatterySensor batterySensor; BaseSensor *sensors[] = { &dustSensor, &tempHumiditySensor, &distanceSensor, &accelerationSensor, - // &batterySensor + &batterySensor }; SBDisplay display; @@ -47,8 +47,6 @@ void setup() SBDisplay::showLoading("Setup BLE...", 0.2); bleModule.begin(); - // batterySensor.begin(); - bleModule.createService("4fafc201-1fb5-459e-8fcc-c5c9c331914b"); SBDisplay::showLoading("Setup Sensors...", 0.4); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp index 522ef6a..e09bb21 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp @@ -1,10 +1,8 @@ #include "BatterySensor.h" -BatterySensor::BatterySensor() : BaseSensor("batterySensorTask", 2048, 10000) {} +BatterySensor::BatterySensor() : BaseSensor("batterySensorTask", 8192, 1000) {} -// 5b262dea-4565-4ea0-912f-1e453bda0ca7 -// String batteryUUID = "5B262DEA45654EA0912F1E453BDA0CA7"; -String batteryUUID = "2A19"; +String batteryUUID = "5b262dea-4565-4ea0-912f-1e453bda0ca7"; int batteryCharacteristic = 0; Adafruit_MAX17048 maxlipo; @@ -18,9 +16,8 @@ void BatterySensor::initSensor() Serial.println(F("Couldnt find Adafruit MAX17048?\nMake sure a battery is plugged in!")); delay(2000); } - // BLEModule::createService("180F"); - // batteryCharacteristic = BLEModule::createCharacteristic(batteryUUID.c_str()); + batteryCharacteristic = BLEModule::createCharacteristic(batteryUUID.c_str()); // add more if needed } @@ -43,7 +40,7 @@ bool BatterySensor::readSensorData() void BatterySensor::notifyBLE(float batteryCharge) { - // BLEModule::writeBLE(batteryCharacteristic, batteryCharge); + BLEModule::writeBLE(batteryUUID.c_str(), batteryCharge); } float BatterySensor::getBatteryCharge() diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.h index 6d95533..f57c063 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.h @@ -4,7 +4,7 @@ #include "../BaseSensor.h" #include -// include necceary libraries +// include necessary libraries class BatterySensor : public BaseSensor { diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h index 177f401..b98c237 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.h @@ -5,7 +5,7 @@ #include // #include -// include necceary libraries +// include necessary libraries class DustSensor : public BaseSensor { diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h index c46b53b..cc756e4 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.h @@ -3,7 +3,7 @@ #include "../BaseSensor.h" -// include necceary libraries +// include necessary libraries class SampleSensor : public BaseSensor { From 84707d50e08b55579f95e766320a4fedbaa3829c Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Tue, 19 Nov 2024 12:21:47 +0100 Subject: [PATCH 10/18] notify --- sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp index 507f86b..2c87fea 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp @@ -77,6 +77,7 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); uint8_t buf[2] = {value, value2}; pCharacteristic->setValue(buf,1); + pCharacteristic->notify(); return true; } @@ -85,6 +86,7 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); uint8_t buf[3] = {value, value2, value3}; pCharacteristic->setValue(buf,1); + pCharacteristic->notify(); return true; } @@ -93,6 +95,7 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); uint8_t buf[4] = {value, value2, value3, value4}; pCharacteristic->setValue(buf,1); + pCharacteristic->notify(); return true; } @@ -101,6 +104,7 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); uint8_t buf[5] = {value, value2, value3, value4}; pCharacteristic->setValue(buf,1); + pCharacteristic->notify(); return true; } From d9dd01cab9b9f30dd5984270f36299bfda2ce0eb Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Tue, 19 Nov 2024 15:45:44 +0100 Subject: [PATCH 11/18] fix value sending --- .../src/ble/BLEModule.cpp | 10 +++++----- .../AccelerationSensor/AccelerationSensor.cpp | 19 +++++++++---------- .../src/sensors/DustSensor/DustSensor.cpp | 2 +- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp index 2c87fea..a8e6100 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp @@ -76,7 +76,7 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); uint8_t buf[2] = {value, value2}; - pCharacteristic->setValue(buf,1); + pCharacteristic->setValue(buf,2); pCharacteristic->notify(); return true; } @@ -85,7 +85,7 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); uint8_t buf[3] = {value, value2, value3}; - pCharacteristic->setValue(buf,1); + pCharacteristic->setValue(buf,3); pCharacteristic->notify(); return true; } @@ -94,7 +94,7 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); uint8_t buf[4] = {value, value2, value3, value4}; - pCharacteristic->setValue(buf,1); + pCharacteristic->setValue(buf,4); pCharacteristic->notify(); return true; } @@ -102,8 +102,8 @@ bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t v bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4, uint8_t value5) { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); - uint8_t buf[5] = {value, value2, value3, value4}; - pCharacteristic->setValue(buf,1); + uint8_t buf[5] = {value, value2, value3, value4, value5}; + pCharacteristic->setValue(buf,5); pCharacteristic->notify(); return true; } diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp index 1de9c1d..4d7d6e1 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp @@ -1,7 +1,7 @@ #include "AccelerationSensor.h" #include "edge-impulse-sdk/classifier/ei_run_classifier.h" -AccelerationSensor::AccelerationSensor() : BaseSensor("accelerationSensorTask", 2048, 0) {} +AccelerationSensor::AccelerationSensor() : BaseSensor("accelerationSensorTask", 8192, 0) {} String surfaceClassificationUUID = "b944af10-f495-4560-968f-2f0d18cab521"; // String accUUID = "B944AF10F4954560968F2F0D18CAB522"; @@ -34,7 +34,7 @@ void AccelerationSensor::initSensor() anomalyCharacteristic = BLEModule::createCharacteristic(anomalyUUID.c_str()); } -float buffer[6] = {}; +float buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = {}; size_t ix = 0; float probAsphalt = 0.0; float probCompact = 0.0; @@ -52,12 +52,12 @@ bool AccelerationSensor::readSensorData() mpu.getEvent(&a, &g, &temp); - buffer[0] = 1.0; - buffer[1] = 1.0; - buffer[2] = 1.0; - buffer[3] = 1.0; - buffer[4] = 1.0; - buffer[5] = 1.0; + buffer[ix++] = 1.0; + buffer[ix++] = 1.0; + buffer[ix++] = 1.0; + buffer[ix++] = 1.0; + buffer[ix++] = 1.0; + buffer[ix++] = 1.0; // Serial.println(millis() - prevAccTime); prevAccTime = millis(); @@ -97,7 +97,6 @@ bool AccelerationSensor::readSensorData() if (sendBLE) { - notifyBLE(probAsphalt, probCompact, probPaving, probSett, probStanding, anomaly); } @@ -116,6 +115,6 @@ bool AccelerationSensor::readSensorData() void AccelerationSensor::notifyBLE(float probAsphalt, float probCompact, float probPaving, float probSett, float probStanding, float anomaly) { - BLEModule::writeBLE(surfaceClassificationUUID.c_str(), probAsphalt, probCompact, probPaving, probSett, probStanding); + BLEModule::writeBLE(surfaceClassificationUUID.c_str(), probAsphalt*100, probCompact*100, probPaving*100, probSett*100, probStanding*100); BLEModule::writeBLE(anomalyUUID.c_str(), anomaly); } \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp index 2c9fa7e..423a6a8 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp @@ -88,5 +88,5 @@ bool DustSensor::readSensorData() void DustSensor::notifyBLE(float pm1, float pm2_5, float pm4, float pm10) { - BLEModule::writeBLE(dustUUID.c_str(), pm1, pm2_5, pm4, pm10); + BLEModule::writeBLE(dustUUID.c_str(), pm1*100, pm2_5*100, pm4*100, pm10*100); } \ No newline at end of file From a84f89b9d29394c15977c84c6539a141492f8e94 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Tue, 19 Nov 2024 15:47:03 +0100 Subject: [PATCH 12/18] setValue int --- sensebox-bike-atrai-v2-esp32s3/README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/sensebox-bike-atrai-v2-esp32s3/README.md b/sensebox-bike-atrai-v2-esp32s3/README.md index 90a7d26..06f4f63 100644 --- a/sensebox-bike-atrai-v2-esp32s3/README.md +++ b/sensebox-bike-atrai-v2-esp32s3/README.md @@ -28,4 +28,5 @@ Threading with mutex - expects different format for characteristic/service ids - no need to actively regularly poll, it does that on its own somehow - I used the BLE-MacAddress for the name (because Im not sure where to get the MCUId from, like it was done with the senseBox-ble library) + - I think it only accepts int values for characteristics with multiple values - I had to adjust the partitions because flash was flowing over \ No newline at end of file From e54b05408e9f0625e0d6de91435b9bb95139c086 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Tue, 26 Nov 2024 17:51:26 +0100 Subject: [PATCH 13/18] fix sending of multiple values through one characteristic --- .../src/ble/BLEModule.cpp | 30 ++++++++++++++----- .../src/ble/BLEModule.h | 8 ++--- 2 files changed, 26 insertions(+), 12 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp index a8e6100..fd416c8 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp @@ -72,37 +72,51 @@ bool BLEModule::writeBLE(const char * characteristicId, float value) return true; } -bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2) +bool BLEModule::writeBLE(const char * characteristicId, float value, float value2) { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); - uint8_t buf[2] = {value, value2}; + uint8_t buf[8]; + memcpy(&buf[0], &value, sizeof(float)); + memcpy(&buf[4], &value2, sizeof(float)); pCharacteristic->setValue(buf,2); pCharacteristic->notify(); return true; } -bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3) +bool BLEModule::writeBLE(const char * characteristicId, float value, float value2, float value3) { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); - uint8_t buf[3] = {value, value2, value3}; + uint8_t buf[12]; + memcpy(&buf[0], &value, sizeof(float)); + memcpy(&buf[4], &value2, sizeof(float)); + memcpy(&buf[8], &value3, sizeof(float)); pCharacteristic->setValue(buf,3); pCharacteristic->notify(); return true; } -bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4) +bool BLEModule::writeBLE(const char * characteristicId, float value, float value2, float value3, float value4) { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); - uint8_t buf[4] = {value, value2, value3, value4}; + uint8_t buf[16]; + memcpy(&buf[0], &value, sizeof(float)); + memcpy(&buf[4], &value2, sizeof(float)); + memcpy(&buf[8], &value3, sizeof(float)); + memcpy(&buf[12], &value4, sizeof(float)); pCharacteristic->setValue(buf,4); pCharacteristic->notify(); return true; } -bool BLEModule::writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4, uint8_t value5) +bool BLEModule::writeBLE(const char * characteristicId, float value, float value2, float value3, float value4, float value5) { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); - uint8_t buf[5] = {value, value2, value3, value4, value5}; + uint8_t buf[20]; + memcpy(&buf[0], &value, sizeof(float)); + memcpy(&buf[4], &value2, sizeof(float)); + memcpy(&buf[8], &value3, sizeof(float)); + memcpy(&buf[12], &value4, sizeof(float)); + memcpy(&buf[16], &value5, sizeof(float)); pCharacteristic->setValue(buf,5); pCharacteristic->notify(); return true; diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h index bedc618..aa578e9 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h @@ -27,10 +27,10 @@ class BLEModule static int createCharacteristic(const char *uuid); static bool writeBLE(const char * characteristicId, float value); - static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2); - static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3); - static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4); - static bool writeBLE(const char * characteristicId, uint8_t value, uint8_t value2, uint8_t value3, uint8_t value4, uint8_t value5); + static bool writeBLE(const char * characteristicId, float value, float value2); + static bool writeBLE(const char * characteristicId, float value, float value2, float value3); + static bool writeBLE(const char * characteristicId, float value, float value2, float value3, float value4); + static bool writeBLE(const char * characteristicId, float value, float value2, float value3, float value4, float value5); // Set callback for receiving data // void setReceiveCallback(void (*callback)(BLEDevice, BLECharacteristic)); From 48d8c3c4f9c4fcf6e0683083ab9d2b96a8fa1f7f Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Thu, 28 Nov 2024 12:57:08 +0100 Subject: [PATCH 14/18] higher task priority --- sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp index c31719a..655a1f0 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp @@ -22,7 +22,9 @@ void BaseSensor::startSubscription() { if (this->taskHandle == NULL) { - xTaskCreate(sensorTask, taskName, taskStackSize, this, 1, &this->taskHandle); + // https://docs.espressif.com/projects/esp-idf/en/v5.2.3/esp32s3/api-guides/performance/speed.html#choosing-task-priorities-of-the-application + xTaskCreate(sensorTask, taskName, taskStackSize, this, 17, &this->taskHandle); + // very important tasks could run on priority 20 on core 0 } activeSubscription = true; } From 300840f0d22af30055ce74067a38893f8dd180fe Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Wed, 4 Dec 2024 17:22:06 +0100 Subject: [PATCH 15/18] add taskPriority and pin to core --- .../AccelerationSensor/AccelerationSensor.cpp | 17 ++++++++---- .../src/sensors/BaseSensor.cpp | 15 ++++++++--- .../src/sensors/BaseSensor.h | 4 ++- .../sensors/BatterySensor/BatterySensor.cpp | 11 +++++++- .../sensors/DistanceSensor/DistanceSensor.cpp | 26 +++++++++++++------ .../src/sensors/DustSensor/DustSensor.cpp | 12 ++++++++- .../src/sensors/SampleSensor/SampleSensor.cpp | 7 ++++- .../TempHumiditySensor/TempHumiditySensor.cpp | 12 +++++++-- 8 files changed, 81 insertions(+), 23 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp index 4d7d6e1..d18deef 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/AccelerationSensor/AccelerationSensor.cpp @@ -1,7 +1,12 @@ #include "AccelerationSensor.h" #include "edge-impulse-sdk/classifier/ei_run_classifier.h" -AccelerationSensor::AccelerationSensor() : BaseSensor("accelerationSensorTask", 8192, 0) {} +AccelerationSensor::AccelerationSensor() : BaseSensor("accelerationSensorTask", +4096, // taskStackSize, +30, // taskDelay, +17, // taskPriority, +1 // core +) {} String surfaceClassificationUUID = "b944af10-f495-4560-968f-2f0d18cab521"; // String accUUID = "B944AF10F4954560968F2F0D18CAB522"; @@ -43,8 +48,7 @@ float probSett = 0.0; float probStanding = 0.0; float anomaly = 0.0; -float prevAccTime = millis(); - +unsigned long startAccTime = millis(); bool AccelerationSensor::readSensorData() { bool classified = false; @@ -59,8 +63,9 @@ bool AccelerationSensor::readSensorData() buffer[ix++] = 1.0; buffer[ix++] = 1.0; - // Serial.println(millis() - prevAccTime); - prevAccTime = millis(); + unsigned long endAccTime = millis(); + Serial.printf("acceleration: %lu ms\n", endAccTime - startAccTime); + startAccTime = millis(); // one second inverval if (EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE <= ix) @@ -103,6 +108,8 @@ bool AccelerationSensor::readSensorData() ix = 0; buffer[EI_CLASSIFIER_DSP_INPUT_FRAME_SIZE] = {}; + + startAccTime = millis(); } if (measurementCallback) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp index 655a1f0..8c28ffe 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp @@ -1,7 +1,7 @@ #include "BaseSensor.h" -BaseSensor::BaseSensor(const char *taskName, uint32_t taskStackSize, uint32_t taskDelay) - : activeSubscription(false), sendBLE(false), taskStackSize(taskStackSize), taskDelay(taskDelay) {} +BaseSensor::BaseSensor(const char *taskName, uint32_t taskStackSize, uint32_t taskDelay, uint32_t taskPriority, uint16_t core) + : activeSubscription(false), sendBLE(false), taskStackSize(taskStackSize), taskDelay(taskDelay), taskPriority(taskPriority), core(core) {} static SemaphoreHandle_t i2c_mutex; @@ -23,7 +23,7 @@ void BaseSensor::startSubscription() if (this->taskHandle == NULL) { // https://docs.espressif.com/projects/esp-idf/en/v5.2.3/esp32s3/api-guides/performance/speed.html#choosing-task-priorities-of-the-application - xTaskCreate(sensorTask, taskName, taskStackSize, this, 17, &this->taskHandle); + xTaskCreatePinnedToCore(sensorTask, taskName, taskStackSize, this, taskPriority, &this->taskHandle, core); // very important tasks could run on priority 20 on core 0 } activeSubscription = true; @@ -48,11 +48,13 @@ void BaseSensor::stopBLE() sendBLE = false; } + void BaseSensor::sensorTask(void *pvParameters) { BaseSensor *sensor = static_cast(pvParameters); while (true) { + unsigned long prevTime = millis(); if (sensor->activeSubscription) { if (xSemaphoreTake(i2c_mutex, portMAX_DELAY) == pdTRUE) @@ -61,6 +63,11 @@ void BaseSensor::sensorTask(void *pvParameters) xSemaphoreGive(i2c_mutex); } } - vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay)); + + if ((millis() - prevTime) < sensor->taskDelay) + { + vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay - (millis() - prevTime))); + } + // vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay)); } } \ No newline at end of file diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.h b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.h index bae48fe..6dff5c8 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.h @@ -9,7 +9,7 @@ class BaseSensor { public: - BaseSensor(const char *taskName, uint32_t taskStackSize = 8192, uint32_t taskDelay = 1000); + BaseSensor(const char *taskName, uint32_t taskStackSize = 8192, uint32_t taskDelay = 1000, uint32_t taskPriority = 1, uint16_t core = 1); void begin(); void subscribe(std::function)> callback); @@ -31,6 +31,8 @@ class BaseSensor uint32_t taskStackSize; uint32_t taskDelay; TaskHandle_t taskHandle; + uint32_t taskPriority; + uint16_t core; }; #endif // BASESENSOR_H diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp index e09bb21..1c3750e 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BatterySensor/BatterySensor.cpp @@ -1,6 +1,11 @@ #include "BatterySensor.h" -BatterySensor::BatterySensor() : BaseSensor("batterySensorTask", 8192, 1000) {} +BatterySensor::BatterySensor() : BaseSensor("batterySensorTask", +4096, // taskStackSize, +1000, // taskDelay, +1, // taskPriority, +1 // core +) {} String batteryUUID = "5b262dea-4565-4ea0-912f-1e453bda0ca7"; int batteryCharacteristic = 0; @@ -21,6 +26,7 @@ void BatterySensor::initSensor() // add more if needed } +unsigned long startBatTime = millis(); bool BatterySensor::readSensorData() { // read sensor data @@ -31,6 +37,9 @@ bool BatterySensor::readSensorData() measurementCallback({batteryCharge}); } + unsigned long endBatTime = millis(); + Serial.printf("battery: %lu ms\n", endBatTime - startBatTime); + startBatTime = millis(); if (sendBLE) { notifyBLE(batteryCharge); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp index a73c4c8..6ca8f42 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp @@ -21,7 +21,12 @@ #include "edge-impulse-sdk/tensorflow/lite/schema/schema_generated.h" #include -DistanceSensor::DistanceSensor() : BaseSensor("distanceTask", 8192, 0) {} +DistanceSensor::DistanceSensor() : BaseSensor("distanceTask", +8192, // taskStackSize, +0, // taskDelay, +20, // taskPriority, +0 // core +) {} // String distanceUUID = "B3491B60C0F34306A30D49C91F37A62B"; String distanceUUID = "b3491b60-c0f3-4306-a30d-49c91f37a62b"; @@ -110,6 +115,7 @@ void DistanceSensor::initSensor() Wire.setClock(100000); // Sensor has max I2C freq of 1MHz } +unsigned long startDisTime = millis(); bool DistanceSensor::readSensorData() { Wire.setClock(1000000); // Sensor has max I2C freq of 1MHz @@ -123,7 +129,7 @@ bool DistanceSensor::readSensorData() if ((!status) && (NewDataReady != 0)) { // Serial.println("data ready"); - Serial.println(millis()-prevDistanceTime); + // Serial.println(millis()-prevDistanceTime); prevDistanceTime = millis(); sensor_vl53l8cx_top.get_ranging_data(&Results); float overtakingPredictionPercentage = -1.0; @@ -188,8 +194,8 @@ bool DistanceSensor::readSensorData() { const float *prediction_scores = interpreter->output(0)->data.f; overtakingPredictionPercentage = prediction_scores[0]; - Serial.print(overtakingPredictionPercentage); - Serial.print(" "); + // Serial.print(overtakingPredictionPercentage); + // Serial.print(" "); } } @@ -202,15 +208,19 @@ bool DistanceSensor::readSensorData() measurementCallback({distance, overtakingPredictionPercentage}); } + unsigned long endDisTime = millis(); + Serial.printf("distance: %lu ms\n", endDisTime - startDisTime); + startDisTime = millis(); + if (sendBLE) { notifyBLE(distance, overtakingPredictionPercentage); } } - if ((millis() - prevDistanceTime) < 65) - { - vTaskDelay(pdMS_TO_TICKS(65 - (millis() - prevDistanceTime))); - } + // if ((millis() - prevDistanceTime) < 65) + // { + // vTaskDelay(pdMS_TO_TICKS(65 - (millis() - prevDistanceTime))); + // } // Serial.print("distance: "); // Serial.println(millis() - prevDistanceTime); return false; diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp index 423a6a8..1cb3745 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DustSensor/DustSensor.cpp @@ -1,6 +1,11 @@ #include "DustSensor.h" -DustSensor::DustSensor() : BaseSensor("DustSensorTask", 8192, 1000) {} +DustSensor::DustSensor() : BaseSensor("DustSensorTask", +4096, // taskStackSize, +1000, // taskDelay, +1, // taskPriority, +1 // core +) {} String dustUUID = "7e14e070-84ea-489f-b45a-e1317364b979"; int dustCharacteristic = 0; @@ -41,6 +46,7 @@ void DustSensor::initSensor() dustCharacteristic = BLEModule::createCharacteristic(dustUUID.c_str()); } +unsigned long startDusTime = millis(); bool DustSensor::readSensorData() { // Wire.setClock(100000); // Sensor has max I2C freq of 1MHz @@ -77,6 +83,10 @@ bool DustSensor::readSensorData() measurementCallback({pm1, pm2_5, pm4, pm10}); } + unsigned long endDusTime = millis(); + Serial.printf("dust: %lu ms\n", endDusTime - startDusTime); + startDusTime = millis(); + if (sendBLE) { notifyBLE(pm1, pm2_5, pm4, pm10); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp index 7772cdd..23ac285 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/SampleSensor/SampleSensor.cpp @@ -1,6 +1,11 @@ #include "SampleSensor.h" -SampleSensor::SampleSensor() : BaseSensor("sampleSensorTask", 2048, 1000) {} +SampleSensor::SampleSensor() : BaseSensor("sampleSensorTask", +2048, // taskStackSize +1000, // taskDelay +1, // taskPriority +1 // core +) {} String sampleUUID = "00000000000000000"; int sampleCharacteristic = 0; diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp index 4195be2..5279799 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/TempHumiditySensor/TempHumiditySensor.cpp @@ -1,6 +1,11 @@ #include "TempHumiditySensor.h" -TempHumiditySensor::TempHumiditySensor() : BaseSensor("temperatureHumidityTask", 8192, 0) {} +TempHumiditySensor::TempHumiditySensor() : BaseSensor("temperatureHumidityTask", +4096, // taskStackSize +1000, // taskDelay +1, // taskPriority +1 // core +) {} String tempUUID = "2cdf2174-35be-fdc4-4Ca2-6fd173f8b3a8"; String humUUID = "772df7ec-8cdc-4ea9-86af-410abe0ba257"; @@ -22,7 +27,7 @@ void TempHumiditySensor::initSensor() temperatureCharacteristic = BLEModule::createCharacteristic(tempUUID.c_str()); humidityCharacteristic = BLEModule::createCharacteristic(humUUID.c_str()); } - +unsigned long startTemTime = millis(); bool TempHumiditySensor::readSensorData() { float temperature = hdc.readTemperature(); @@ -39,6 +44,9 @@ bool TempHumiditySensor::readSensorData() measurementCallback({temperature, humidity}); } + unsigned long endTemTime = millis(); + Serial.printf("temperature/humidity: %lu ms\n", endTemTime - startTemTime); + startTemTime = millis(); if (sendBLE) { notifyBLE(temperature, humidity); From 33e03aa63c10c8088be375402ba97ef7e4562700 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Wed, 11 Dec 2024 16:16:59 +0100 Subject: [PATCH 16/18] immediatly reset I2C clock after vl53l8cx --- .../src/sensors/DistanceSensor/DistanceSensor.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp index 6ca8f42..e8cfd5b 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/DistanceSensor/DistanceSensor.cpp @@ -108,7 +108,6 @@ void DistanceSensor::initSensor() } input_length = model_input->bytes / sizeof(float); // ----------------------------- setup complete ----------------------------- - Serial.println("setup complete"); distanceCharacteristic = BLEModule::createCharacteristic(distanceUUID.c_str()); overtakingCharacteristic = BLEModule::createCharacteristic(overtakingUUID.c_str()); @@ -118,11 +117,12 @@ void DistanceSensor::initSensor() unsigned long startDisTime = millis(); bool DistanceSensor::readSensorData() { - Wire.setClock(1000000); // Sensor has max I2C freq of 1MHz VL53L8CX_ResultsData Results; uint8_t NewDataReady = 0; + Wire.setClock(1000000); // Sensor has max I2C freq of 1MHz uint8_t status = sensor_vl53l8cx_top.check_data_ready(&NewDataReady); + Wire.setClock(100000); // back to normal frequency float distance = -1.0; @@ -131,7 +131,9 @@ bool DistanceSensor::readSensorData() // Serial.println("data ready"); // Serial.println(millis()-prevDistanceTime); prevDistanceTime = millis(); + Wire.setClock(1000000); // Sensor has max I2C freq of 1MHz sensor_vl53l8cx_top.get_ranging_data(&Results); + Wire.setClock(100000); // back to normal frequency float overtakingPredictionPercentage = -1.0; float oldVl53l8cxMin = -1.0; float min = 10000.0; @@ -201,8 +203,6 @@ bool DistanceSensor::readSensorData() float distance = oldVl53l8cxMin; - Wire.setClock(100000); // Sensor has max I2C freq of 1MHz - if (measurementCallback) { measurementCallback({distance, overtakingPredictionPercentage}); From fb7ec74f49e910773ae61fa92eae18fcb5b38ca2 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Fri, 13 Dec 2024 14:03:32 +0100 Subject: [PATCH 17/18] activeSubscription --- sensebox-bike-atrai-v2-esp32s3/src/main.cpp | 9 ++++++--- .../src/sensors/BaseSensor.cpp | 12 ++++++------ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp index bedd412..6a569ef 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/main.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/main.cpp @@ -16,10 +16,10 @@ BatterySensor batterySensor; BaseSensor *sensors[] = { &dustSensor, - &tempHumiditySensor, - &distanceSensor, &accelerationSensor, - &batterySensor + &distanceSensor, + &batterySensor, + &tempHumiditySensor, }; SBDisplay display; @@ -54,6 +54,7 @@ void setup() { sensor->begin(); } + Serial.println("Setup complete"); SBDisplay::showLoading("Ventilation...", 0.6); // pinMode(3, OUTPUT); @@ -66,6 +67,7 @@ void setup() { sensor->startSubscription(); } + Serial.println("Subscriptions started"); SBDisplay::showLoading("Enable BLE...", 1); @@ -74,6 +76,7 @@ void setup() { sensor->startBLE(); } + Serial.println("BLE enabled"); display.readBleId(); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp index 8c28ffe..dbe730a 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/sensors/BaseSensor.cpp @@ -22,11 +22,11 @@ void BaseSensor::startSubscription() { if (this->taskHandle == NULL) { + activeSubscription = true; // https://docs.espressif.com/projects/esp-idf/en/v5.2.3/esp32s3/api-guides/performance/speed.html#choosing-task-priorities-of-the-application xTaskCreatePinnedToCore(sensorTask, taskName, taskStackSize, this, taskPriority, &this->taskHandle, core); // very important tasks could run on priority 20 on core 0 } - activeSubscription = true; } void BaseSensor::stopSubscription() @@ -64,10 +64,10 @@ void BaseSensor::sensorTask(void *pvParameters) } } - if ((millis() - prevTime) < sensor->taskDelay) - { - vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay - (millis() - prevTime))); - } - // vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay)); + // if (sensor->taskDelay > 0 && (millis() - prevTime) < sensor->taskDelay) + // { + // vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay - (millis() - prevTime))); + // } + vTaskDelay(pdMS_TO_TICKS(sensor->taskDelay)); } } \ No newline at end of file From 2e3fb6ec079a41c970c40982d67c05834aa0f659 Mon Sep 17 00:00:00 2001 From: PaulaScharf Date: Fri, 13 Dec 2024 14:03:55 +0100 Subject: [PATCH 18/18] receiving data --- .../src/ble/BLEModule.cpp | 29 +++++++++++++++++++ .../src/ble/BLEModule.h | 1 + 2 files changed, 30 insertions(+) diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp index fd416c8..79f6fd9 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.cpp @@ -6,6 +6,20 @@ BLEService *pService; char macString[32]; // Enough space for the MAC string +class CustomBLECallbacks : public BLECharacteristicCallbacks { + void onWrite(BLECharacteristic *pCharacteristic) override { + std::string value = pCharacteristic->getValue(); + + if (value.length() > 0) { + Serial.println("Received data:"); + for (int i = 0; i < value.length(); i++) { + Serial.print(value[i]); + } + Serial.println(); + } + } +}; + BLEModule::BLEModule() { bleName = ""; @@ -64,6 +78,21 @@ int BLEModule::createCharacteristic(const char *uuid) return 1; } +// for receiving data +int BLEModule::createCharacteristicWithCallback(const char *uuid) { + BLECharacteristic *pCharacteristic = pService->createCharacteristic( + uuid, + BLECharacteristic::PROPERTY_READ | + BLECharacteristic::PROPERTY_WRITE | + BLECharacteristic::PROPERTY_INDICATE | + BLECharacteristic::PROPERTY_NOTIFY + ); + + // Attach the callback to handle incoming data + pCharacteristic->setCallbacks(new CustomBLECallbacks()); + return 1; +} + bool BLEModule::writeBLE(const char * characteristicId, float value) { BLECharacteristic *pCharacteristic = pService->getCharacteristic(characteristicId); diff --git a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h index aa578e9..95e8bb8 100644 --- a/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h +++ b/sensebox-bike-atrai-v2-esp32s3/src/ble/BLEModule.h @@ -25,6 +25,7 @@ class BLEModule // Create a BLE characteristic static int createCharacteristic(const char *uuid); + static int createCharacteristicWithCallback(const char *uuid); static bool writeBLE(const char * characteristicId, float value); static bool writeBLE(const char * characteristicId, float value, float value2);